Merge tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 8 Feb 2018 19:42:05 +0000 (11:42 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 8 Feb 2018 19:42:05 +0000 (11:42 -0800)
Pull more drm updates from Dave Airlie:
 "Ben missed sending his nouveau tree, but he really didn't have much
  stuff in it:

   - GP108 acceleration support is enabled by "secure boot" support

   - some clockgating work on Kepler, and bunch of fixes

   - the bulk of the diff is regenerated firmware files, the change to
     them really isn't that large.

  Otherwise this contains regular Intel and AMDGPU fixes"

* tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux: (59 commits)
  drm/i915/bios: add DP max link rate to VBT child device struct
  drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
  drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
  drm/i915/cmdparser: Do not check past the cmd length.
  drm/i915/cmdparser: Check reg_table_count before derefencing.
  drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
  drm/i915/gvt: Use KVM r/w to access guest opregion
  drm/i915/gvt: Fix aperture read/write emulation when enable x-no-mmap=on
  drm/i915/gvt: only reset execlist state of one engine during VM engine reset
  drm/i915/gvt: refine intel_vgpu_submission_ops as per engine ops
  drm/amdgpu: re-enable CGCG on CZ and disable on ST
  drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
  drm/nouveau/mmu: Fix trailing semicolon
  drm/nouveau: Introduce NvPmEnableGating option
  drm/nouveau: Add support for SLCG for Kepler2
  drm/nouveau: Add support for BLCG on Kepler2
  drm/nouveau: Add support for BLCG on Kepler1
  drm/nouveau: Add support for basic clockgating on Kepler1
  drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion
  drm/nouveau/kms/nv50: use INTERPOLATE_257_UNITY_RANGE LUT on newer chipsets
  ...

1  2 
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

index 554d1db1f3c8d02c2396cac49cf413067c6ccc72,801a3375c7b4fcbf6e2d73c261221faa8d565bba..909499b73d03acba1a1af1f6f5b77c7ccdd07b5c
@@@ -651,6 -651,39 +651,39 @@@ static int intel_vgpu_bar_rw(struct int
        return ret;
  }
  
+ static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, uint64_t off)
+ {
+       return off >= vgpu_aperture_offset(vgpu) &&
+              off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu);
+ }
+ static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t off,
+               void *buf, unsigned long count, bool is_write)
+ {
+       void *aperture_va;
+       if (!intel_vgpu_in_aperture(vgpu, off) ||
+           !intel_vgpu_in_aperture(vgpu, off + count)) {
+               gvt_vgpu_err("Invalid aperture offset %llu\n", off);
+               return -EINVAL;
+       }
+       aperture_va = io_mapping_map_wc(&vgpu->gvt->dev_priv->ggtt.iomap,
+                                       ALIGN_DOWN(off, PAGE_SIZE),
+                                       count + offset_in_page(off));
+       if (!aperture_va)
+               return -EIO;
+       if (is_write)
+               memcpy(aperture_va + offset_in_page(off), buf, count);
+       else
+               memcpy(buf, aperture_va + offset_in_page(off), count);
+       io_mapping_unmap(aperture_va);
+       return 0;
+ }
  static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
                        size_t count, loff_t *ppos, bool is_write)
  {
                                        buf, count, is_write);
                break;
        case VFIO_PCI_BAR2_REGION_INDEX:
-               ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_2, pos,
-                                       buf, count, is_write);
+               ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write);
                break;
        case VFIO_PCI_BAR1_REGION_INDEX:
        case VFIO_PCI_BAR3_REGION_INDEX:
@@@ -1019,8 -1051,6 +1051,8 @@@ static long intel_vgpu_ioctl(struct mde
                        if (!sparse)
                                return -ENOMEM;
  
 +                      sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP;
 +                      sparse->header.version = 1;
                        sparse->nr_areas = nr_areas;
                        cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP;
                        sparse->areas[0].offset =
                        break;
                default:
                        {
 -                              struct vfio_region_info_cap_type cap_type;
 +                              struct vfio_region_info_cap_type cap_type = {
 +                                      .header.id = VFIO_REGION_INFO_CAP_TYPE,
 +                                      .header.version = 1 };
  
                                if (info.index >= VFIO_PCI_NUM_REGIONS +
                                                vgpu->vdev.num_regions)
                                cap_type.subtype = vgpu->vdev.region[i].subtype;
  
                                ret = vfio_info_add_capability(&caps,
 -                                              VFIO_REGION_INFO_CAP_TYPE,
 -                                              &cap_type);
 +                                                      &cap_type.header,
 +                                                      sizeof(cap_type));
                                if (ret)
                                        return ret;
                        }
                        switch (cap_type_id) {
                        case VFIO_REGION_INFO_CAP_SPARSE_MMAP:
                                ret = vfio_info_add_capability(&caps,
 -                                      VFIO_REGION_INFO_CAP_SPARSE_MMAP,
 -                                      sparse);
 +                                      &sparse->header, sizeof(*sparse) +
 +                                      (sparse->nr_areas *
 +                                              sizeof(*sparse->areas)));
                                kfree(sparse);
                                if (ret)
                                        return ret;
@@@ -1575,6 -1602,21 +1607,21 @@@ static unsigned long kvmgt_virt_to_pfn(
        return PFN_DOWN(__pa(addr));
  }
  
+ static bool kvmgt_is_valid_gfn(unsigned long handle, unsigned long gfn)
+ {
+       struct kvmgt_guest_info *info;
+       struct kvm *kvm;
+       if (!handle_valid(handle))
+               return false;
+       info = (struct kvmgt_guest_info *)handle;
+       kvm = info->kvm;
+       return kvm_is_visible_gfn(kvm, gfn);
+ }
  struct intel_gvt_mpt kvmgt_mpt = {
        .host_init = kvmgt_host_init,
        .host_exit = kvmgt_host_exit,
        .set_opregion = kvmgt_set_opregion,
        .get_vfio_device = kvmgt_get_vfio_device,
        .put_vfio_device = kvmgt_put_vfio_device,
+       .is_valid_gfn = kvmgt_is_valid_gfn,
  };
  EXPORT_SYMBOL_GPL(kvmgt_mpt);
  
index 08e77cd55e6e46a20f5c089fddc0308ee9e9ca19,073534ab6911822dbd3e78db51225adf9898a12b..05cd674326a63f67a7d4f0ce31bd6b682dcbafe8
@@@ -28,6 -28,7 +28,7 @@@
  #include <core/option.h>
  
  #include <subdev/bios.h>
+ #include <subdev/therm.h>
  
  static DEFINE_MUTEX(nv_devices_mutex);
  static LIST_HEAD(nv_devices);
@@@ -1251,7 -1252,7 +1252,7 @@@ nvaa_chipset = 
        .i2c = g94_i2c_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
 -      .mmu = g84_mmu_new,
 +      .mmu = mcp77_mmu_new,
        .mxm = nv50_mxm_new,
        .pci = g94_pci_new,
        .therm = g84_therm_new,
@@@ -1283,7 -1284,7 +1284,7 @@@ nvac_chipset = 
        .i2c = g94_i2c_new,
        .imem = nv50_instmem_new,
        .mc = g98_mc_new,
 -      .mmu = g84_mmu_new,
 +      .mmu = mcp77_mmu_new,
        .mxm = nv50_mxm_new,
        .pci = g94_pci_new,
        .therm = g84_therm_new,
@@@ -1682,7 -1683,7 +1683,7 @@@ nve4_chipset = 
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk104_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -1721,7 -1722,7 +1722,7 @@@ nve6_chipset = 
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk104_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -1760,7 -1761,7 +1761,7 @@@ nve7_chipset = 
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk104_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -1811,7 -1812,7 +1812,7 @@@ nvf0_chipset = 
        .bus = gf100_bus_new,
        .clk = gk104_clk_new,
        .devinit = gf100_devinit_new,
-       .fb = gk104_fb_new,
+       .fb = gk110_fb_new,
        .fuse = gf100_fuse_new,
        .gpio = gk104_gpio_new,
        .i2c = gk104_i2c_new,
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk110_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -1849,7 -1850,7 +1850,7 @@@ nvf1_chipset = 
        .bus = gf100_bus_new,
        .clk = gk104_clk_new,
        .devinit = gf100_devinit_new,
-       .fb = gk104_fb_new,
+       .fb = gk110_fb_new,
        .fuse = gf100_fuse_new,
        .gpio = gk104_gpio_new,
        .i2c = gk104_i2c_new,
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk110_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -1887,7 -1888,7 +1888,7 @@@ nv106_chipset = 
        .bus = gf100_bus_new,
        .clk = gk104_clk_new,
        .devinit = gf100_devinit_new,
-       .fb = gk104_fb_new,
+       .fb = gk110_fb_new,
        .fuse = gf100_fuse_new,
        .gpio = gk104_gpio_new,
        .i2c = gk104_i2c_new,
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk208_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -1925,7 -1926,7 +1926,7 @@@ nv108_chipset = 
        .bus = gf100_bus_new,
        .clk = gk104_clk_new,
        .devinit = gf100_devinit_new,
-       .fb = gk104_fb_new,
+       .fb = gk110_fb_new,
        .fuse = gf100_fuse_new,
        .gpio = gk104_gpio_new,
        .i2c = gk104_i2c_new,
        .mxm = nv50_mxm_new,
        .pci = gk104_pci_new,
        .pmu = gk208_pmu_new,
-       .therm = gf119_therm_new,
+       .therm = gk104_therm_new,
        .timer = nv41_timer_new,
        .top = gk104_top_new,
        .volt = gk104_volt_new,
@@@ -2345,6 -2346,7 +2346,7 @@@ nv138_chipset = 
        .mc = gp100_mc_new,
        .mmu = gp100_mmu_new,
        .therm = gp100_therm_new,
+       .secboot = gp108_secboot_new,
        .pci = gp100_pci_new,
        .pmu = gp102_pmu_new,
        .timer = gk20a_timer_new,
        .disp = gp102_disp_new,
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
+       .gr = gp107_gr_new,
+       .nvdec = gp102_nvdec_new,
+       .sec2 = gp102_sec2_new,
+       .sw = gf100_sw_new,
  };
  
  static const struct nvkm_device_chip
@@@ -2508,6 -2514,7 +2514,7 @@@ nvkm_device_fini(struct nvkm_device *de
                }
        }
  
+       nvkm_therm_clkgate_fini(device->therm, suspend);
  
        if (device->func->fini)
                device->func->fini(device, suspend);
@@@ -2597,6 -2604,7 +2604,7 @@@ nvkm_device_init(struct nvkm_device *de
        }
  
        nvkm_acpi_init(device);
+       nvkm_therm_clkgate_enable(device->therm);
  
        time = ktime_to_us(ktime_get()) - time;
        nvdev_trace(device, "init completed in %lldus\n", time);