Merge branch 'akpm' (patches from Andrew)
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 9 Sep 2017 17:30:07 +0000 (10:30 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 9 Sep 2017 17:30:07 +0000 (10:30 -0700)
Merge more updates from Andrew Morton:

 - most of the rest of MM

 - a small number of misc things

 - lib/ updates

 - checkpatch

 - autofs updates

 - ipc/ updates

* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (126 commits)
  ipc: optimize semget/shmget/msgget for lots of keys
  ipc/sem: play nicer with large nsops allocations
  ipc/sem: drop sem_checkid helper
  ipc: convert kern_ipc_perm.refcount from atomic_t to refcount_t
  ipc: convert sem_undo_list.refcnt from atomic_t to refcount_t
  ipc: convert ipc_namespace.count from atomic_t to refcount_t
  kcov: support compat processes
  sh: defconfig: cleanup from old Kconfig options
  mn10300: defconfig: cleanup from old Kconfig options
  m32r: defconfig: cleanup from old Kconfig options
  drivers/pps: use surrounding "if PPS" to remove numerous dependency checks
  drivers/pps: aesthetic tweaks to PPS-related content
  cpumask: make cpumask_next() out-of-line
  kmod: move #ifdef CONFIG_MODULES wrapper to Makefile
  kmod: split off umh headers into its own file
  MAINTAINERS: clarify kmod is just a kernel module loader
  kmod: split out umh code into its own file
  test_kmod: flip INT checks to be consistent
  test_kmod: remove paranoid UINT_MAX check on uint range processing
  vfat: deduplicate hex2bin()
  ...

320 files changed:
CREDITS
Documentation/admin-guide/kernel-parameters.txt
Documentation/devicetree/bindings/arc/hsdk.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pci/83xx-512x-pci.txt
Documentation/devicetree/bindings/pci/altera-pcie.txt
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
Documentation/devicetree/bindings/pci/designware-pcie.txt
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
Documentation/devicetree/bindings/pci/kirin-pcie.txt
Documentation/devicetree/bindings/pci/layerscape-pci.txt
Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt [deleted file]
Documentation/devicetree/bindings/pci/mediatek-pcie.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pci/mvebu-pci.txt
Documentation/devicetree/bindings/pci/pci-armada8k.txt
Documentation/devicetree/bindings/pci/pci-keystone.txt
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
Documentation/devicetree/bindings/pci/qcom,pcie.txt
Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
Documentation/devicetree/bindings/pci/rcar-pci.txt
Documentation/devicetree/bindings/pci/rockchip-pcie.txt
Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
Documentation/devicetree/bindings/pci/ti-pci.txt
Documentation/devicetree/bindings/pci/versatile.txt
Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
Documentation/devicetree/bindings/pci/xgene-pci.txt
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
Documentation/laptops/thinkpad-acpi.txt
Documentation/virtual/kvm/devices/arm-vgic.txt
Documentation/virtual/kvm/devices/vm.txt
MAINTAINERS
arch/alpha/kernel/pci.c
arch/alpha/kernel/sys_nautilus.c
arch/arc/Kconfig
arch/arc/Makefile
arch/arc/boot/dts/axc001.dtsi
arch/arc/boot/dts/axc003.dtsi
arch/arc/boot/dts/axc003_idu.dtsi
arch/arc/boot/dts/hsdk.dts [new file with mode: 0644]
arch/arc/boot/dts/nsim_hs.dts
arch/arc/configs/hsdk_defconfig [new file with mode: 0644]
arch/arc/include/asm/cache.h
arch/arc/include/asm/entry-compact.h
arch/arc/include/asm/irqflags-arcv2.h
arch/arc/include/asm/irqflags-compact.h
arch/arc/include/asm/page.h
arch/arc/include/asm/processor.h
arch/arc/include/asm/ptrace.h
arch/arc/include/asm/spinlock.h
arch/arc/include/asm/switch_to.h
arch/arc/kernel/Makefile
arch/arc/kernel/devtree.c
arch/arc/kernel/entry-compact.S
arch/arc/kernel/entry.S
arch/arc/kernel/pcibios.c [deleted file]
arch/arc/kernel/process.c
arch/arc/kernel/setup.c
arch/arc/kernel/traps.c
arch/arc/kernel/troubleshoot.c
arch/arc/mm/cache.c
arch/arc/mm/fault.c
arch/arc/mm/init.c
arch/arc/mm/tlb.c
arch/arc/mm/tlbex.S
arch/arc/plat-axs10x/axs10x.c
arch/arc/plat-eznps/Kconfig
arch/arc/plat-eznps/Makefile
arch/arc/plat-eznps/ctop.c [new file with mode: 0644]
arch/arc/plat-eznps/entry.S
arch/arc/plat-eznps/include/plat/ctop.h
arch/arc/plat-eznps/mtm.c
arch/arc/plat-hsdk/Kconfig [new file with mode: 0644]
arch/arc/plat-hsdk/Makefile [new file with mode: 0644]
arch/arc/plat-hsdk/platform.c [new file with mode: 0644]
arch/arm/include/asm/kvm_arm.h
arch/arm/include/asm/kvm_emulate.h
arch/arm/kvm/handle_exit.c
arch/arm64/boot/dts/rockchip/rk3399.dtsi
arch/arm64/include/asm/kvm_emulate.h
arch/arm64/kernel/pci.c
arch/arm64/kvm/handle_exit.c
arch/arm64/kvm/vgic-sys-reg-v3.c
arch/cris/arch-v32/drivers/pci/bios.c
arch/ia64/pci/pci.c
arch/m68k/coldfire/pci.c
arch/microblaze/include/asm/pci.h
arch/microblaze/pci/pci-common.c
arch/mips/kvm/mips.c
arch/mips/pci/pci-legacy.c
arch/powerpc/include/asm/book3s/64/mmu-hash.h
arch/powerpc/kvm/book3s_64_mmu_hv.c
arch/powerpc/kvm/book3s_64_vio.c
arch/powerpc/kvm/book3s_hv.c
arch/powerpc/kvm/book3s_hv_rm_mmu.c
arch/powerpc/kvm/book3s_hv_rmhandlers.S
arch/powerpc/kvm/e500.c
arch/powerpc/kvm/e500mc.c
arch/powerpc/kvm/powerpc.c
arch/s390/include/asm/kvm_host.h
arch/s390/include/asm/page-states.h
arch/s390/include/uapi/asm/kvm.h
arch/s390/kvm/diag.c
arch/s390/kvm/guestdbg.c
arch/s390/kvm/interrupt.c
arch/s390/kvm/kvm-s390.c
arch/s390/kvm/kvm-s390.h
arch/s390/kvm/priv.c
arch/s390/kvm/sigp.c
arch/s390/kvm/sthyi.c
arch/s390/kvm/vsie.c
arch/s390/mm/pgtable.c
arch/s390/pci/pci.c
arch/s390/tools/gen_facilities.c
arch/sh/drivers/pci/fixups-cayman.c
arch/sh/drivers/pci/fixups-dreamcast.c
arch/sh/drivers/pci/fixups-r7780rp.c
arch/sh/drivers/pci/fixups-rts7751r2d.c
arch/sh/drivers/pci/fixups-sdk7780.c
arch/sh/drivers/pci/fixups-se7751.c
arch/sh/drivers/pci/fixups-sh03.c
arch/sh/drivers/pci/fixups-snapgear.c
arch/sh/drivers/pci/fixups-titan.c
arch/sh/drivers/pci/pci.c
arch/sh/drivers/pci/pcie-sh7786.c
arch/sparc/kernel/leon_pci.c
arch/sparc/kernel/pci.c
arch/sparc/kernel/pcic.c
arch/tile/kernel/pci.c
arch/tile/kernel/pci_gx.c
arch/unicore32/kernel/pci.c
arch/x86/include/asm/cpufeatures.h
arch/x86/include/asm/kvm_emulate.h
arch/x86/include/asm/kvm_host.h
arch/x86/include/asm/svm.h
arch/x86/include/asm/vmx.h
arch/x86/kvm/cpuid.c
arch/x86/kvm/cpuid.h
arch/x86/kvm/emulate.c
arch/x86/kvm/hyperv.c
arch/x86/kvm/kvm_cache_regs.h
arch/x86/kvm/lapic.c
arch/x86/kvm/lapic.h
arch/x86/kvm/mmu.c
arch/x86/kvm/mmu.h
arch/x86/kvm/mmu_audit.c
arch/x86/kvm/mtrr.c
arch/x86/kvm/paging_tmpl.h
arch/x86/kvm/svm.c
arch/x86/kvm/trace.h
arch/x86/kvm/vmx.c
arch/x86/kvm/x86.c
arch/x86/kvm/x86.h
arch/x86/pci/fixup.c
drivers/iommu/intel-iommu.c
drivers/misc/pci_endpoint_test.c
drivers/pci/dwc/Kconfig
drivers/pci/dwc/pci-dra7xx.c
drivers/pci/dwc/pci-exynos.c
drivers/pci/dwc/pci-imx6.c
drivers/pci/dwc/pci-keystone-dw.c
drivers/pci/dwc/pci-keystone.c
drivers/pci/dwc/pci-keystone.h
drivers/pci/dwc/pci-layerscape.c
drivers/pci/dwc/pcie-armada8k.c
drivers/pci/dwc/pcie-artpec6.c
drivers/pci/dwc/pcie-designware-ep.c
drivers/pci/dwc/pcie-designware-host.c
drivers/pci/dwc/pcie-designware-plat.c
drivers/pci/dwc/pcie-designware.c
drivers/pci/dwc/pcie-designware.h
drivers/pci/dwc/pcie-hisi.c
drivers/pci/dwc/pcie-kirin.c
drivers/pci/dwc/pcie-qcom.c
drivers/pci/dwc/pcie-spear13xx.c
drivers/pci/endpoint/functions/pci-epf-test.c
drivers/pci/endpoint/pci-epc-core.c
drivers/pci/endpoint/pci-epc-mem.c
drivers/pci/endpoint/pci-epf-core.c
drivers/pci/host/Kconfig
drivers/pci/host/pci-aardvark.c
drivers/pci/host/pci-ftpci100.c
drivers/pci/host/pci-hyperv.c
drivers/pci/host/pci-mvebu.c
drivers/pci/host/pci-tegra.c
drivers/pci/host/pci-xgene-msi.c
drivers/pci/host/pci-xgene.c
drivers/pci/host/pcie-altera-msi.c
drivers/pci/host/pcie-altera.c
drivers/pci/host/pcie-iproc-msi.c
drivers/pci/host/pcie-iproc-platform.c
drivers/pci/host/pcie-iproc.c
drivers/pci/host/pcie-iproc.h
drivers/pci/host/pcie-mediatek.c
drivers/pci/host/pcie-rcar.c
drivers/pci/host/pcie-rockchip.c
drivers/pci/host/pcie-xilinx-nwl.c
drivers/pci/host/pcie-xilinx.c
drivers/pci/host/vmd.c
drivers/pci/hotplug/cpcihp_zt5550.c
drivers/pci/hotplug/cpqphp_core.c
drivers/pci/hotplug/ibmphp_core.c
drivers/pci/hotplug/ibmphp_ebda.c
drivers/pci/hotplug/pciehp_hpc.c
drivers/pci/hotplug/pnv_php.c
drivers/pci/hotplug/rpadlpar_core.c
drivers/pci/hotplug/rpadlpar_sysfs.c
drivers/pci/hotplug/rpaphp_core.c
drivers/pci/hotplug/rpaphp_pci.c
drivers/pci/hotplug/rpaphp_slot.c
drivers/pci/hotplug/shpchp_core.c
drivers/pci/hotplug/shpchp_hpc.c
drivers/pci/iov.c
drivers/pci/msi.c
drivers/pci/pci-label.c
drivers/pci/pci-sysfs.c
drivers/pci/pci.c
drivers/pci/pci.h
drivers/pci/pcie/aer/aerdrv.c
drivers/pci/pcie/aer/aerdrv_core.c
drivers/pci/pcie/pcie-dpc.c
drivers/pci/pcie/portdrv_pci.c
drivers/pci/probe.c
drivers/pci/quirks.c
drivers/pci/setup-irq.c
drivers/pci/setup-res.c
drivers/phy/rockchip/phy-rockchip-pcie.c
drivers/platform/x86/alienware-wmi.c
drivers/platform/x86/asus-wmi.c
drivers/platform/x86/dell-wmi.c
drivers/platform/x86/hp-wmi.c
drivers/platform/x86/ibm_rtl.c
drivers/platform/x86/ideapad-laptop.c
drivers/platform/x86/intel-hid.c
drivers/platform/x86/intel-vbtn.c
drivers/platform/x86/intel_mid_powerbtn.c
drivers/platform/x86/intel_pmc_core.c
drivers/platform/x86/intel_pmc_core.h
drivers/platform/x86/intel_scu_ipc.c
drivers/platform/x86/intel_telemetry_debugfs.c
drivers/platform/x86/intel_telemetry_pltdrv.c
drivers/platform/x86/msi-wmi.c
drivers/platform/x86/mxm-wmi.c
drivers/platform/x86/peaq-wmi.c
drivers/platform/x86/thinkpad_acpi.c
drivers/platform/x86/wmi.c
include/linux/aer.h
include/linux/ftrace.h
include/linux/kvm_host.h
include/linux/pci-epc.h
include/linux/pci-epf.h
include/linux/pci.h
include/linux/pcieport_if.h
include/linux/trace_events.h
include/uapi/linux/kvm.h
include/uapi/linux/pci_regs.h
kernel/trace/ftrace.c
kernel/trace/trace.c
kernel/trace/trace.h
kernel/trace/trace_events.c
kernel/trace/trace_selftest.c
scripts/Makefile.lib
scripts/genksyms/lex.l
scripts/genksyms/lex.lex.c_shipped
tools/pci/pcitest.c
tools/testing/selftests/breakpoints/breakpoint_test.c
tools/testing/selftests/capabilities/test_execve.c
tools/testing/selftests/capabilities/validate_cap.c
tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh
tools/testing/selftests/ftrace/ftracetest
tools/testing/selftests/futex/functional/futex_requeue_pi.c
tools/testing/selftests/futex/functional/futex_requeue_pi_mismatched_ops.c
tools/testing/selftests/futex/functional/futex_requeue_pi_signal_restart.c
tools/testing/selftests/futex/functional/futex_wait_private_mapped_file.c
tools/testing/selftests/futex/functional/futex_wait_timeout.c
tools/testing/selftests/futex/functional/futex_wait_uninitialized_heap.c
tools/testing/selftests/futex/functional/futex_wait_wouldblock.c
tools/testing/selftests/futex/include/logging.h
tools/testing/selftests/kselftest.h
tools/testing/selftests/kselftest_harness.h
tools/testing/selftests/lib.mk
tools/testing/selftests/memfd/fuse_test.c
tools/testing/selftests/nsfs/config [new file with mode: 0644]
tools/testing/selftests/pstore/.gitignore [new file with mode: 0644]
tools/testing/selftests/ptp/Makefile
tools/testing/selftests/seccomp/seccomp_bpf.c
tools/testing/selftests/sigaltstack/sas.c
tools/testing/selftests/splice/.gitignore [new file with mode: 0644]
tools/testing/selftests/splice/Makefile
tools/testing/selftests/sync/sync_test.c
tools/testing/selftests/sync/synctest.h
tools/testing/selftests/timers/Makefile
tools/testing/selftests/timers/adjtick.c
tools/testing/selftests/timers/alarmtimer-suspend.c
tools/testing/selftests/timers/change_skew.c
tools/testing/selftests/timers/clocksource-switch.c
tools/testing/selftests/timers/inconsistency-check.c
tools/testing/selftests/timers/leap-a-day.c
tools/testing/selftests/timers/leapcrash.c
tools/testing/selftests/timers/mqueue-lat.c
tools/testing/selftests/timers/nanosleep.c
tools/testing/selftests/timers/nsleep-lat.c
tools/testing/selftests/timers/raw_skew.c
tools/testing/selftests/timers/rtctest.c
tools/testing/selftests/timers/set-2038.c
tools/testing/selftests/timers/set-tai.c
tools/testing/selftests/timers/set-timer-lat.c
tools/testing/selftests/timers/set-tz.c
tools/testing/selftests/timers/skew_consistency.c
tools/testing/selftests/timers/threadtest.c
tools/testing/selftests/timers/valid-adjtimex.c
tools/testing/selftests/watchdog/watchdog-test.c
virt/kvm/arm/arm.c
virt/kvm/arm/mmu.c
virt/kvm/arm/vgic/vgic-debug.c
virt/kvm/arm/vgic/vgic-its.c
virt/kvm/arm/vgic/vgic-mmio-v2.c
virt/kvm/arm/vgic/vgic.h
virt/kvm/kvm_main.c

diff --git a/CREDITS b/CREDITS
index 5d09c26d69cdc0f4709cf48f5f3ff6195d53e85d..0d2d60de5a2539cc48c21eee25a226b08b8a2040 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -2090,7 +2090,7 @@ S: Kuala Lumpur, Malaysia
 
 N: Mohit Kumar
 D: ST Microelectronics SPEAr13xx PCI host bridge driver
-D: Synopsys Designware PCI host bridge driver
+D: Synopsys DesignWare PCI host bridge driver
 
 N: Gabor Kuti
 E: seasons@falcon.sch.bme.hu
index 86b0e8ec8ad78bc5ec3035ccd0d11288fbde5b61..05496622b4effb8212eb2175bea67f9a7bebe0d0 100644 (file)
                        If the dependencies are under your control, you can
                        turn on cpu0_hotplug.
 
+       nps_mtm_hs_ctr= [KNL,ARC]
+                       This parameter sets the maximum duration, in
+                       cycles, each HW thread of the CTOP can run
+                       without interruptions, before HW switches it.
+                       The actual maximum duration is 16 times this
+                       parameter's value.
+                       Format: integer between 1 and 255
+                       Default: 255
+
        nptcg=          [IA-64] Override max number of concurrent global TLB
                        purges which is reported from either PAL_VM_SUMMARY or
                        SAL PALO.
diff --git a/Documentation/devicetree/bindings/arc/hsdk.txt b/Documentation/devicetree/bindings/arc/hsdk.txt
new file mode 100644 (file)
index 0000000..be50654
--- /dev/null
@@ -0,0 +1,7 @@
+Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
+---------------------------------------------------------------------------
+
+ARC HSDK Board with quad-core ARC HS38x4 in silicon.
+
+Required root node properties:
+    - compatible = "snps,hsdk";
index 35a465362408c2916797f2cf2f107232bb92fe30..b9165b72473c10f6245bd656a6ac169d67cd3257 100644 (file)
@@ -1,11 +1,11 @@
 * Freescale 83xx and 512x PCI bridges
 
-Freescale 83xx and 512x SOCs include the same pci bridge core.
+Freescale 83xx and 512x SOCs include the same PCI bridge core.
 
 83xx/512x specific notes:
 - reg: should contain two address length tuples
-    The first is for the internal pci bridge registers
-    The second is for the pci config space access registers
+    The first is for the internal PCI bridge registers
+    The second is for the PCI config space access registers
 
 Example (MPC8313ERDB)
        pci0: pci@e0008500 {
index 2951a6a50704bf3234782be2e64abcfaf2496684..495880193adc8c9e9403b5fda893df580718630c 100644 (file)
@@ -7,21 +7,21 @@ Required properties:
                "Txs": TX slave port region
                "Cra": Control register access region
 - interrupt-parent:    interrupt source phandle.
-- interrupts:  specifies the interrupt source of the parent interrupt controller.
-               The format of the interrupt specifier depends on the parent interrupt
-               controller.
+- interrupts:  specifies the interrupt source of the parent interrupt
+               controller.  The format of the interrupt specifier depends
+               on the parent interrupt controller.
 - device_type: must be "pci"
 - #address-cells:      set to <3>
-- #size-cells: set to <2>
+- #size-cells:         set to <2>
 - #interrupt-cells:    set to <1>
-- ranges:              describes the translation of addresses for root ports and standard
-               PCI regions.
+- ranges:      describes the translation of addresses for root ports and
+               standard PCI regions.
 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
                mapping of the PCIe interface to interrupt numbers.
 
 Optional properties:
-- msi-parent:  Link to the hardware entity that serves as the MSI controller for this PCIe
-               controller.
+- msi-parent:  Link to the hardware entity that serves as the MSI controller
+               for this PCIe controller.
 - bus-range:   PCI bus numbers covered
 
 Example
@@ -45,5 +45,5 @@ Example
                                    <0 0 0 3 &pcie_0 3>,
                                    <0 0 0 4 &pcie_0 4>;
                ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
-                           0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+                         0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
        };
index 5ecaea1e6eee8bdbd533f45d1afe371820b72b8d..4e4aee4439ea12acc6eb43a24587e7d67a8acd2e 100644 (file)
@@ -6,7 +6,7 @@ and thus inherits all the common properties defined in designware-pcie.txt.
 Required properties:
 - compatible: "axis,artpec6-pcie", "snps,dw-pcie"
 - reg: base addresses and lengths of the PCIe controller (DBI),
-       the phy controller, and configuration address space.
+       the PHY controller, and configuration address space.
 - reg-names: Must include the following entries:
        - "dbi"
        - "phy"
index b2480dd38c1135747c6bcceb5153df94a6a36326..1da7ade3183c8f7e0b88a7315036bdd16fcaa09c 100644 (file)
@@ -1,4 +1,4 @@
-* Synopsys Designware PCIe interface
+* Synopsys DesignWare PCIe interface
 
 Required properties:
 - compatible: should contain "snps,dw-pcie" to identify the core.
@@ -17,29 +17,27 @@ RC mode:
        properties to define the mapping of the PCIe interface to interrupt
        numbers.
 EP mode:
-- num-ib-windows: number of inbound address translation
-        windows
-- num-ob-windows: number of outbound address translation
-        windows
+- num-ib-windows: number of inbound address translation windows
+- num-ob-windows: number of outbound address translation windows
 
 Optional properties:
 - num-lanes: number of lanes to use (this property should be specified unless
   the link is brought already up in BIOS)
-- reset-gpio: gpio pin number of power good signal
+- reset-gpio: GPIO pin number of power good signal
 - clocks: Must contain an entry for each entry in clock-names.
        See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
        - "pcie"
        - "pcie_bus"
 RC mode:
-- num-viewport: number of view ports configured in
-  hardware. If a platform does not specify it, the driver assumes 2.
-- bus-range: PCI bus numbers covered (it is recommended
-  for new devicetrees to specify this property, to keep backwards
-  compatibility a range of 0x00-0xff is assumed if not present)
+- num-viewport: number of view ports configured in hardware. If a platform
+  does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
+  to specify this property, to keep backwards compatibility a range of
+  0x00-0xff is assumed if not present)
+
 EP mode:
-- max-functions: maximum number of functions that can be
-  configured
+- max-functions: maximum number of functions that can be configured
 
 Example configuration:
 
index cf92d3ba5a269fc10de4eef2057b33fd4fcd6928..7b1e48bf172b74ba51755409cf8510dc0a15fb6d 100644 (file)
@@ -1,6 +1,6 @@
 * Freescale i.MX6 PCIe interface
 
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
index 7a579c816951501137b2005272714a973fd439c8..bdb7ab39d2d7effafede0803adef4eeef1d9bf9a 100644 (file)
@@ -1,7 +1,7 @@
 HiSilicon Hip05 and Hip06 PCIe host bridge DT description
 
-HiSilicon PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver and inherits
+HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and inherits
 common properties defined in
 Documentation/devicetree/bindings/pci/designware-pci.txt.
 
index 68ffa0fbcd73361b61807d2eef5975846439cadb..6e217c63123db6c1021dba04d09ec419be05fd67 100644 (file)
@@ -1,8 +1,8 @@
 HiSilicon Kirin SoCs PCIe host DT description
 
-Kirin PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver
-and inherits common properties defined in
+Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
 Documentation/devicetree/bindings/pci/designware-pci.txt.
 
 Additional properties are described here:
@@ -16,7 +16,7 @@ Required properties
   "apb": apb Ctrl register defined by Kirin;
   "phy": apb PHY register defined by Kirin;
   "config": PCIe configuration space registers.
-- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
 
 Optional properties:
 
index ee1c72d5162ea191ca9a83fd8dcd7baac21312fa..c0484da0f20d9d87f3be44f9bfd844362820bb59 100644 (file)
@@ -15,8 +15,10 @@ Required properties:
 - compatible: should contain the platform identifier such as:
         "fsl,ls1021a-pcie", "snps,dw-pcie"
         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+        "fsl,ls2088a-pcie"
+        "fsl,ls1088a-pcie"
         "fsl,ls1046a-pcie"
-- reg: base addresses and lengths of the PCIe controller
+- reg: base addresses and lengths of the PCIe controller register blocks.
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:
diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
deleted file mode 100644 (file)
index fe80dda..0000000
+++ /dev/null
@@ -1,130 +0,0 @@
-MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
-
-PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
-ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
-
-Required properties:
-- compatible: Should contain "mediatek,mt7623-pcie".
-- device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe controller.
-- #address-cells: Address representation for root ports (must be 3)
-- #size-cells: Size representation for root ports (must be 2)
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
-  Please refer to the standard PCI bus binding document for a more detailed
-  explanation.
-- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - free_ck :for reference clock of PCIe subsys
-  - sys_ck0 :for clock of Port0
-  - sys_ck1 :for clock of Port1
-  - sys_ck2 :for clock of Port2
-- resets: Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
-  - pcie-rst0 :port0 reset
-  - pcie-rst1 :port1 reset
-  - pcie-rst2 :port2 reset
-- phys: List of PHY specifiers (used by generic PHY framework).
-- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
-  number of PHYs as specified in *phys* property.
-- power-domains: A phandle and power domain specifier pair to the power domain
-  which is responsible for collapsing and restoring power to the peripheral.
-- bus-range: Range of bus numbers associated with this controller.
-- ranges: Ranges for the PCI memory and I/O regions.
-
-In addition, the device tree node must have sub-nodes describing each
-PCIe port interface, having the following mandatory properties:
-
-Required properties:
-- device_type: Must be "pci"
-- reg: Only the first four bytes are used to refer to the correct bus number
-  and device number.
-- #address-cells: Must be 3
-- #size-cells: Must be 2
-- #interrupt-cells: Must be 1
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
-  Please refer to the standard PCI bus binding document for a more detailed
-  explanation.
-- ranges: Sub-ranges distributed from the PCIe controller node. An empty
-  property is sufficient.
-- num-lanes: Number of lanes to use for this port.
-
-Examples:
-
-       hifsys: syscon@1a000000 {
-               compatible = "mediatek,mt7623-hifsys",
-                            "mediatek,mt2701-hifsys",
-                            "syscon";
-               reg = <0 0x1a000000 0 0x1000>;
-               #clock-cells = <1>;
-               #reset-cells = <1>;
-       };
-
-       pcie: pcie-controller@1a140000 {
-               compatible = "mediatek,mt7623-pcie";
-               device_type = "pci";
-               reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
-                     <0 0x1a142000 0 0x1000>, /* Port0 registers */
-                     <0 0x1a143000 0 0x1000>, /* Port1 registers */
-                     <0 0x1a144000 0 0x1000>; /* Port2 registers */
-               #address-cells = <3>;
-               #size-cells = <2>;
-               #interrupt-cells = <1>;
-               interrupt-map-mask = <0xf800 0 0 0>;
-               interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
-                               <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
-                               <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
-                        <&hifsys CLK_HIFSYS_PCIE0>,
-                        <&hifsys CLK_HIFSYS_PCIE1>,
-                        <&hifsys CLK_HIFSYS_PCIE2>;
-               clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
-               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
-                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
-                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
-               reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
-               phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
-               phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
-               bus-range = <0x00 0xff>;
-               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000     /* I/O space */
-                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;   /* memory space */
-
-               pcie@0,0 {
-                       device_type = "pci";
-                       reg = <0x0000 0 0 0 0>;
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-                       #interrupt-cells = <1>;
-                       interrupt-map-mask = <0 0 0 0>;
-                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
-                       ranges;
-                       num-lanes = <1>;
-               };
-
-               pcie@1,0 {
-                       device_type = "pci";
-                       reg = <0x0800 0 0 0 0>;
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-                       #interrupt-cells = <1>;
-                       interrupt-map-mask = <0 0 0 0>;
-                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
-                       ranges;
-                       num-lanes = <1>;
-               };
-
-               pcie@2,0 {
-                       device_type = "pci";
-                       reg = <0x1000 0 0 0 0>;
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-                       #interrupt-cells = <1>;
-                       interrupt-map-mask = <0 0 0 0>;
-                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
-                       ranges;
-                       num-lanes = <1>;
-               };
-       };
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
new file mode 100644 (file)
index 0000000..3a6ce55
--- /dev/null
@@ -0,0 +1,284 @@
+MediaTek Gen2 PCIe controller
+
+Required properties:
+- compatible: Should contain one of the following strings:
+       "mediatek,mt2701-pcie"
+       "mediatek,mt2712-pcie"
+       "mediatek,mt7622-pcie"
+       "mediatek,mt7623-pcie"
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource lookup.
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names:
+  Mandatory entries:
+   - sys_ckN :transaction layer and data link layer clock
+  Required entries for MT2701/MT7623:
+   - free_ck :for reference clock of PCIe subsys
+  Required entries for MT2712/MT7622:
+   - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+             initiated MMIO access
+  Required entries for MT7622:
+   - axi_ckN :application layer MMIO channel operating clock
+   - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+             pcie_mac_ck/pcie_pipe_ck is turned off
+   - obff_ckN :OBFF functional block operating clock
+   - pipe_ckN :LTSSM and PHY/MAC layer operating clock
+  where N starting from 0 to one less than the number of root ports.
+- phys: List of PHY specifiers (used by generic PHY framework).
+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+  number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+  which is responsible for collapsing and restoring power to the peripheral.
+- bus-range: Range of bus numbers associated with this controller.
+- ranges: Ranges for the PCI memory and I/O regions.
+
+Required properties for MT7623/MT2701:
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+  number of root ports.
+
+Required properties for MT2712/MT7622:
+-interrupts: A list of interrupt outputs of the controller, must have one
+            entry for each PCIe port
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- reg: Only the first four bytes are used to refer to the correct bus number
+  and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Must be 1
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+  property is sufficient.
+- num-lanes: Number of lanes to use for this port.
+
+Examples for MT7623:
+
+       hifsys: syscon@1a000000 {
+               compatible = "mediatek,mt7623-hifsys",
+                            "mediatek,mt2701-hifsys",
+                            "syscon";
+               reg = <0 0x1a000000 0 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       pcie: pcie-controller@1a140000 {
+               compatible = "mediatek,mt7623-pcie";
+               device_type = "pci";
+               reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+                     <0 0x1a142000 0 0x1000>, /* Port0 registers */
+                     <0 0x1a143000 0 0x1000>, /* Port1 registers */
+                     <0 0x1a144000 0 0x1000>; /* Port2 registers */
+               reg-names = "subsys", "port0", "port1", "port2";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0xf800 0 0 0>;
+               interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+                               <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+                               <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+                        <&hifsys CLK_HIFSYS_PCIE0>,
+                        <&hifsys CLK_HIFSYS_PCIE1>,
+                        <&hifsys CLK_HIFSYS_PCIE2>;
+               clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+               reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+               phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
+                      <&pcie2_phy PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000     /* I/O space */
+                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;   /* memory space */
+
+               pcie@0,0 {
+                       device_type = "pci";
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       num-lanes = <1>;
+               };
+
+               pcie@1,0 {
+                       device_type = "pci";
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       num-lanes = <1>;
+               };
+
+               pcie@2,0 {
+                       device_type = "pci";
+                       reg = <0x1000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       num-lanes = <1>;
+               };
+       };
+
+Examples for MT2712:
+       pcie: pcie@11700000 {
+               compatible = "mediatek,mt2712-pcie";
+               device_type = "pci";
+               reg = <0 0x11700000 0 0x1000>,
+                     <0 0x112ff000 0 0x1000>;
+               reg-names = "port0", "port1";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+                        <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+                        <&pericfg CLK_PERI_PCIE0>,
+                        <&pericfg CLK_PERI_PCIE1>;
+               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+               phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy0", "pcie-phy1";
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+
+               pcie0: pcie@0,0 {
+                       device_type = "pci";
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       num-lanes = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                                       <0 0 0 2 &pcie_intc0 1>,
+                                       <0 0 0 3 &pcie_intc0 2>,
+                                       <0 0 0 4 &pcie_intc0 3>;
+                       pcie_intc0: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               pcie1: pcie@1,0 {
+                       device_type = "pci";
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       num-lanes = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                                       <0 0 0 2 &pcie_intc1 1>,
+                                       <0 0 0 3 &pcie_intc1 2>,
+                                       <0 0 0 4 &pcie_intc1 3>;
+                       pcie_intc1: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };
+
+Examples for MT7622:
+       pcie: pcie@1a140000 {
+               compatible = "mediatek,mt7622-pcie";
+               device_type = "pci";
+               reg = <0 0x1a140000 0 0x1000>,
+                     <0 0x1a143000 0 0x1000>,
+                     <0 0x1a145000 0 0x1000>;
+               reg-names = "subsys", "port0", "port1";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+                        <&pciesys CLK_PCIE_P1_MAC_EN>,
+                        <&pciesys CLK_PCIE_P0_AHB_EN>,
+                        <&pciesys CLK_PCIE_P1_AHB_EN>,
+                        <&pciesys CLK_PCIE_P0_AUX_EN>,
+                        <&pciesys CLK_PCIE_P1_AUX_EN>,
+                        <&pciesys CLK_PCIE_P0_AXI_EN>,
+                        <&pciesys CLK_PCIE_P1_AXI_EN>,
+                        <&pciesys CLK_PCIE_P0_OBFF_EN>,
+                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
+                        <&pciesys CLK_PCIE_P0_PIPE_EN>,
+                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
+               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+                             "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+                             "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+               phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy0", "pcie-phy1";
+               power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
+
+               pcie0: pcie@0,0 {
+                       device_type = "pci";
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       num-lanes = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                                       <0 0 0 2 &pcie_intc0 1>,
+                                       <0 0 0 3 &pcie_intc0 2>,
+                                       <0 0 0 4 &pcie_intc0 3>;
+                       pcie_intc0: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               pcie1: pcie@1,0 {
+                       device_type = "pci";
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       num-lanes = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                                       <0 0 0 2 &pcie_intc1 1>,
+                                       <0 0 0 3 &pcie_intc1 2>,
+                                       <0 0 0 4 &pcie_intc1 3>;
+                       pcie_intc1: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };
index 9c7fce69570b66c824a032c3655785dc11843810..127ae1f53e5a2d5b4da6893efc7fba898a14fd27 100644 (file)
@@ -77,7 +77,7 @@ and the following optional properties:
 - marvell,pcie-lane: the physical PCIe lane number, for ports having
   multiple lanes. If this property is not found, we assume that the
   value is 0.
-- reset-gpios: optional gpio to PERST#
+- reset-gpios: optional GPIO to PERST#
 - reset-delay-us: delay in us to wait after reset de-assertion, if not
   specified will default to 100ms, as required by the PCIe specification.
 
index 6b115fd10fec81720800b2b7d424097a18dae6b0..c1e4c3d10a747c008c2b914c89194228caed395e 100644 (file)
@@ -1,6 +1,6 @@
 * Marvell Armada 7K/8K PCIe interface
 
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
index d08a4d51108f7419e2ec547dbed4d9b9620ccc09..7e05487544edffae025e1071406fe711cf220773 100644 (file)
@@ -1,12 +1,12 @@
 TI Keystone PCIe interface
 
-Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
-It shares common functions with PCIe Designware core driver and inherit
-common properties defined in
+Keystone PCI host Controller is based on the Synopsys DesignWare PCI
+hardware version 3.65.  It shares common functions with the PCIe DesignWare
+core driver and inherits common properties defined in
 Documentation/devicetree/bindings/pci/designware-pci.txt
 
 Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
-for the details of Designware DT bindings.  Additional properties are
+for the details of DesignWare DT bindings.  Additional properties are
 described here as well as properties that are not applicable.
 
 Required Properties:-
@@ -52,13 +52,12 @@ pcie_intc: Interrupt controller device node for Legacy IRQ chip
        };
 
 Optional properties:-
-       phys: phandle to Generic Keystone SerDes phy for PCI
-       phy-names: name of the Generic Keystine SerDes phy for PCI
+       phys: phandle to generic Keystone SerDes PHY for PCI
+       phy-names: name of the generic Keystone SerDes PHY for PCI
          - If boot loader already does PCI link establishment, then phys and
            phy-names shouldn't be present.
        interrupts: platform interrupt for error interrupts.
 
-Designware DT Properties not applicable for Keystone PCI
+DesignWare DT Properties not applicable for Keystone PCI
 
 1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
-
index 07a75094c5a8ed07e927c0641584d5e8348e3dc6..3d038638612b8ec2af704adaf6dcd5b0bc81b1e6 100644 (file)
@@ -6,11 +6,14 @@ AHB. There is one bridge instance per USB port connected to the internal
 OHCI and EHCI controllers.
 
 Required properties:
-- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
+- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC;
+             "renesas,pci-r8a7745" for the R8A7745 SoC;
+             "renesas,pci-r8a7790" for the R8A7790 SoC;
              "renesas,pci-r8a7791" for the R8A7791 SoC;
              "renesas,pci-r8a7793" for the R8A7793 SoC;
              "renesas,pci-r8a7794" for the R8A7794 SoC;
-             "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
+             "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
+                                     RZ/G1 compatible device.
 
 
              When compatible with the generic version, nodes must list the
index 9d418b71774f356c22c640c72943a836fdb5fe14..3c9d321b3d3b0d22e04d7ba8f022982ffc452cce 100644 (file)
@@ -9,6 +9,7 @@
                        - "qcom,pcie-apq8084" for apq8084
                        - "qcom,pcie-msm8996" for msm8996 or apq8096
                        - "qcom,pcie-ipq4019" for ipq4019
+                       - "qcom,pcie-ipq8074" for ipq8074
 
 - reg:
        Usage: required
@@ -20,7 +21,7 @@
        Value type: <stringlist>
        Definition: Must include the following entries
                        - "parf"   Qualcomm specific registers
-                       - "dbi"    Designware PCIe registers
+                       - "dbi"    DesignWare PCIe registers
                        - "elbi"   External local bus interface registers
                        - "config" PCIe configuration space
 
                        - "bus_master"  Master AXI clock
                        - "bus_slave"   Slave AXI clock
 
+- clock-names:
+       Usage: required for ipq8074
+       Value type: <stringlist>
+       Definition: Should contain the following entries
+                       - "iface"       PCIe to SysNOC BIU clock
+                       - "axi_m"       AXI Master clock
+                       - "axi_s"       AXI Slave clock
+                       - "ahb"         AHB clock
+                       - "aux"         Auxiliary clock
+
 - resets:
        Usage: required
        Value type: <prop-encoded-array>
                        - "ahb"                 AHB reset
                        - "phy_ahb"             PHY AHB reset
 
+- reset-names:
+       Usage: required for ipq8074
+       Value type: <stringlist>
+       Definition: Should contain the following entries
+                       - "pipe"                PIPE reset
+                       - "sleep"               Sleep reset
+                       - "sticky"              Core Sticky reset
+                       - "axi_m"               AXI Master reset
+                       - "axi_s"               AXI Slave reset
+                       - "ahb"                 AHB Reset
+                       - "axi_m_sticky"        AXI Master Sticky reset
+
 - power-domains:
        Usage: required for apq8084 and msm8996/apq8096
        Value type: <prop-encoded-array>
 - <name>-gpios:
        Usage: optional
        Value type: <prop-encoded-array>
-       Definition: List of phandle and gpio specifier pairs. Should contain
+       Definition: List of phandle and GPIO specifier pairs. Should contain
                        - "perst-gpios" PCIe endpoint reset signal line
                        - "wake-gpios"  PCIe endpoint wake signal line
 
index 8e0a1eb0acbbd73938e9a22cba8e96f497e9ef59..a04ab1b762110fc3f63441e5aa771c04334a6a44 100644 (file)
@@ -71,7 +71,7 @@
    - interrupt-map: standard PCI properties to define the mapping of the
      PCI interface to interrupt numbers.
 
-   The PCI host bridge node migh have additional sub-nodes representing
+   The PCI host bridge node might have additional sub-nodes representing
    the onboard PCI devices/PCI slots. Each such sub-node must have the
    following mandatory properties:
 
index a7e3dd43b2a8a5ff58f61d16ce3138d1a7f9022a..76ba3a61d1a31c1fea2e492a438e6d4a01a316cd 100644 (file)
@@ -14,7 +14,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
            SoC-specific version corresponding to the platform first
            followed by the generic version.
 
-- reg: base address and length of the pcie controller registers.
+- reg: base address and length of the PCIe controller registers.
 - #address-cells: set to <3>
 - #size-cells: set to <2>
 - bus-range: PCI bus numbers covered
@@ -25,15 +25,14 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
        source for hardware related interrupts (e.g. link speed change).
 - #interrupt-cells: set to <1>
 - interrupt-map-mask and interrupt-map: standard PCI properties
-       to define the mapping of the PCIe interface to interrupt
-       numbers.
+       to define the mapping of the PCIe interface to interrupt numbers.
 - clocks: from common clock binding: clock specifiers for the PCIe controller
        and PCIe bus clocks.
 - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
 
 Example:
 
-SoC specific DT Entry:
+SoC-specific DT Entry:
 
        pcie: pcie@fe000000 {
                compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
index 1453a734c2f5b53bf606807e99871619ca132b12..af34c65773fd7fc540411b06be96011cc84828d1 100644 (file)
@@ -19,8 +19,6 @@ Required properties:
        - "pm"
 - msi-map: Maps a Requester ID to an MSI controller and associated
        msi-specifier data. See ./pci-msi.txt
-- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
-- phy-names:  MUST be "pcie-phy".
 - interrupts: Three interrupt entries must be specified.
 - interrupt-names: Must include the following names
        - "sys"
@@ -42,11 +40,24 @@ Required properties:
        interrupt source. The value must be 1.
 - interrupt-map-mask and interrupt-map: standard PCI properties
 
+Required properties for legacy PHY model (deprecated):
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names:  MUST be "pcie-phy".
+
+Required properties for per-lane PHY model (preferred):
+- phys: Must contain an phandle to a PHY for each entry in phy-names.
+- phy-names: Must include 4 entries for all 4 lanes even if some of
+  them won't be used for your cases. Entries are of the form "pcie-phy-N":
+  where N ranges from 0 to 3.
+  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+  for changing the #phy-cells of phy node to support it)
+
 Optional Property:
 - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
        using 24MHz OSC for RC's PHY.
-- ep-gpios: contain the entry for pre-reset gpio
+- ep-gpios: contain the entry for pre-reset GPIO
 - num-lanes: number of lanes to use
+- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
 - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
@@ -95,6 +106,7 @@ pcie0: pcie@f8000000 {
                 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
        reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
                      "pm", "pclk", "aclk";
+       /* deprecated legacy PHY model */
        phys = <&pcie_phy>;
        phy-names = "pcie-phy";
        pinctrl-names = "default";
@@ -111,3 +123,13 @@ pcie0: pcie@f8000000 {
                #interrupt-cells = <1>;
        };
 };
+
+pcie0: pcie@f8000000 {
+       ...
+
+       /* preferred per-lane PHY model */
+       phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+       phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+
+       ...
+};
index 7d3b09474657b81b7574932786e856475ead2f10..34a11bfbfb600ea38ceaabfea145811b4f40f946 100644 (file)
@@ -1,29 +1,29 @@
 * Samsung Exynos 5440 PCIe interface
 
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
 - compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the pcie controller,
-       the phy controller, additional register for the phy controller.
-       (Registers for the phy controller are DEPRECATED.
+- reg: base addresses and lengths of the PCIe controller,
+       the PHY controller, additional register for the PHY controller.
+       (Registers for the PHY controller are DEPRECATED.
         Use the PHY framework.)
 - reg-names : First name should be set to "elbi".
-       And use the "config" instead of getting the confgiruation address space
+       And use the "config" instead of getting the configuration address space
        from "ranges".
-       NOTE: When use the "config" property, reg-names must be set.
+       NOTE: When using the "config" property, reg-names must be set.
 - interrupts: A list of interrupt outputs for level interrupt,
        pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the Generic PHY.
+- phys: From PHY binding. Phandle for the generic PHY.
        Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
 
-Other common properties refer to
-       Documentation/devicetree/binding/pci/designware-pcie.txt
+For other common properties, refer to
+       Documentation/devicetree/bindings/pci/designware-pcie.txt
 
 Example:
 
-SoC specific DT Entry:
+SoC-specific DT Entry:
 
        pcie@290000 {
                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
@@ -83,7 +83,7 @@ With using PHY framework:
                ...
        };
 
-Board specific DT Entry:
+Board-specific DT Entry:
 
        pcie@290000 {
                reset-gpio = <&pin_ctrl 5 0>;
index 49ea76da77183cf89a15a1cfff13ed4a7ac1b3c5..d5a14f5dad46cc5937031045cc0bd698610130f4 100644 (file)
@@ -1,12 +1,12 @@
 SPEAr13XX PCIe DT detail:
 ================================
 
-SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
+SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
 controller.
 
 Required properties:
-- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
-- phys             : phandle to phy node associated with pcie controller
+- compatible       : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys             : phandle to PHY node associated with PCIe controller
 - phy-names        : must be "pcie-phy"
 - All other definitions as per generic PCI bindings
 
index 6a07c96227e0a0a9bd96530c2833df195657e7dc..7f7af3044016a6b4578cb4df6e8ff90e2a7ed45c 100644 (file)
@@ -1,6 +1,6 @@
 TI PCI Controllers
 
-PCIe Designware Controller
+PCIe DesignWare Controller
  - compatible: Should be "ti,dra7-pcie" for RC
               Should be "ti,dra7-pcie-ep" for EP
  - phys : list of PHY specifiers (used by generic PHY framework)
@@ -13,7 +13,7 @@ PCIe Designware Controller
 HOST MODE
 =========
  - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ - reg-names : The first entry must be "ti-conf" for the TI-specific registers
               The second entry must be "rc-dbics" for the DesignWare PCIe
               registers
               The third entry must be "config" for the PCIe configuration space
@@ -30,7 +30,7 @@ HOST MODE
 DEVICE MODE
 ===========
  - reg : Four register ranges as listed in the reg-names property
- - reg-names : "ti-conf" for the TI specific registers
+ - reg-names : "ti-conf" for the TI-specific registers
               "ep_dbics" for the standard configuration registers as
                they are locally accessed within the DIF CS space
               "ep_dbics2" for the standard configuration registers as
@@ -46,7 +46,7 @@ DEVICE MODE
                               access.
 
 Optional Property:
- - gpios : Should be added if a gpio line is required to drive PERST# line
+ - gpios : Should be added if a GPIO line is required to drive PERST# line
 
 NOTE: Two DT nodes may be added for each PCI controller; one for host
 mode and another for device mode. So in order for PCI to
index ebd1e7d0403ed1406a846f0cf08f173cb3a8eab7..0a702b13d2acc28a5e460f033384e2d4f57dbc25 100644 (file)
@@ -5,7 +5,7 @@ PCI host controller found on the ARM Versatile PB board's FPGA.
 Required properties:
 - compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
   controller.
-- reg: base addresses and lengths of the pci controller. There must be 3
+- reg: base addresses and lengths of the PCI controller. There must be 3
   entries:
        - Versatile-specific registers
        - Self Config space
index 54bac7f8860c02fa10cde3f241863a0db00d347a..85d9b95234f7d914af80ae1c81b98cd2ff31cdae 100644 (file)
@@ -4,7 +4,7 @@ Required properties:
 
 - compatible: should be "apm,xgene1-msi" to identify
              X-Gene v1 PCIe MSI controller block.
-- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node
+- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
 - reg: physical base address (0x79000000) and length (0x900000) for controller
        registers. These registers include the MSI termination address and data
        registers as well as the MSI interrupt status registers.
@@ -13,7 +13,8 @@ Required properties:
              interrupt number 0x10 to 0x1f.
 - interrupt-names: not required
 
-Each PCIe node needs to have property msi-parent that points to msi controller node
+Each PCIe node needs to have property msi-parent that points to an MSI
+controller node
 
 Examples:
 
index 1070b068c7c6496e917eadeff79083b41328077a..6fd2decfa66c4b30d0de6d77f57ceef77eadd28a 100644 (file)
@@ -8,7 +8,7 @@ Required properties:
        property.
 - reg-names: Must include the following entries:
   "csr": controller configuration registers.
-  "cfg": pcie configuration space registers.
+  "cfg": PCIe configuration space registers.
 - #address-cells: set to <3>
 - #size-cells: set to <2>
 - ranges: ranges for the outbound memory, I/O regions.
@@ -21,11 +21,11 @@ Required properties:
 
 Optional properties:
 - status: Either "ok" or "disabled".
-- dma-coherent: Present if dma operations are coherent
+- dma-coherent: Present if DMA operations are coherent
 
 Example:
 
-SoC specific DT Entry:
+SoC-specific DT Entry:
 
        pcie0: pcie@1f2b0000 {
                status = "disabled";
@@ -51,7 +51,7 @@ SoC specific DT Entry:
        };
 
 
-Board specific DT Entry:
+Board-specific DT Entry:
        &pcie0 {
                status = "ok";
        };
index 3259798a1192b051520b3cad2412a6f59fb6dfa5..01bf7fdf4c19208f38dba304909e432a45b90560 100644 (file)
@@ -15,9 +15,9 @@ Required properties:
 - device_type: must be "pci"
 - interrupts: Should contain NWL PCIe interrupt
 - interrupt-names: Must include the following entries:
-       "msi1, msi0": interrupt asserted when MSI is received
+       "msi1, msi0": interrupt asserted when an MSI is received
        "intx": interrupt asserted when a legacy interrupt is received
-       "misc": interrupt asserted when miscellaneous is received
+       "misc": interrupt asserted when miscellaneous interrupt is received
 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
        mapping of the PCI interface to interrupt numbers.
 - ranges: ranges for the PCI memory regions (I/O space region is not
@@ -26,7 +26,8 @@ Required properties:
        detailed explanation
 - msi-controller: indicates that this is MSI controller node
 - msi-parent:  MSI parent of the root complex itself
-- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts
+- legacy-interrupt-controller: Interrupt controller device node for Legacy
+       interrupts
        - interrupt-controller: identifies the node as an interrupt controller
        - #interrupt-cells: should be set to 1
        - #address-cells: specifies the number of cells needed to encode an
index 0f6222a672ced616ba4e21b5310f7087dcb31655..b496042f1f4436f4543b7b835d41afd1d1e4adb7 100644 (file)
@@ -3,7 +3,6 @@ Rockchip PCIE PHY
 
 Required properties:
  - compatible: rockchip,rk3399-pcie-phy
- - #phy-cells: must be 0
  - clocks: Must contain an entry in clock-names.
        See ../clocks/clock-bindings.txt for details.
  - clock-names: Must be "refclk"
@@ -11,6 +10,12 @@ Required properties:
        See ../reset/reset.txt for details.
  - reset-names: Must be "phy"
 
+Required properties for legacy PHY mode (deprecated):
+ - #phy-cells: must be 0
+
+Required properties for per-lane PHY mode (preferred):
+ - #phy-cells: must be 1
+
 Example:
 
 grf: syscon@ff770000 {
index ba2e7d2548429a249a2462cf58a24938245ee047..00b6dfed573cf595594714df451621eb2f991893 100644 (file)
@@ -121,8 +121,9 @@ space, for 2.6.23+ this is /sys/devices/platform/thinkpad_acpi/.
 Sysfs device attributes for the sensors and fan are on the
 thinkpad_hwmon device's sysfs attribute space, but you should locate it
 looking for a hwmon device with the name attribute of "thinkpad", or
-better yet, through libsensors.
-
+better yet, through libsensors. For 4.14+ sysfs attributes were moved to the
+hwmon device (/sys/bus/platform/devices/thinkpad_hwmon/hwmon/hwmon? or
+/sys/class/hwmon/hwmon?).
 
 Driver version
 --------------
@@ -1478,3 +1479,7 @@ Sysfs interface changelog:
 0x020700:      Support for mute-only mixers.
                Volume control in read-only mode by default.
                Marker for ALSA mixer support.
+
+0x030000:      Thermal and fan sysfs attributes were moved to the hwmon
+               device instead of being attached to the backing platform
+               device.
index b2f60ca8b60cad64d9ffba81f61919bc4b8edacb..b3ce12643553f3edbe327029bbfe61ecaa8cc506 100644 (file)
@@ -83,6 +83,11 @@ Groups:
 
     Bits for undefined preemption levels are RAZ/WI.
 
+    Note that this differs from a CPU's view of the APRs on hardware in which
+    a GIC without the security extensions expose group 0 and group 1 active
+    priorities in separate register groups, whereas we show a combined view
+    similar to GICv2's GICH_APR.
+
     For historical reasons and to provide ABI compatibility with userspace we
     export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask
     field in the lower 5 bits of a word, meaning that userspace must always
index 903fc926860b522bc92122a65c750d4f28be2d71..95ca68d663a4c111eb99b280e6d1d60c85461804 100644 (file)
@@ -176,7 +176,8 @@ Architectures: s390
 
 3.1. ATTRIBUTE: KVM_S390_VM_TOD_HIGH
 
-Allows user space to set/get the TOD clock extension (u8).
+Allows user space to set/get the TOD clock extension (u8) (superseded by
+KVM_S390_VM_TOD_EXT).
 
 Parameters: address of a buffer in user space to store the data (u8) to
 Returns:    -EFAULT if the given address is not accessible from kernel space
@@ -190,6 +191,17 @@ the POP (u64).
 Parameters: address of a buffer in user space to store the data (u64) to
 Returns:    -EFAULT if the given address is not accessible from kernel space
 
+3.3. ATTRIBUTE: KVM_S390_VM_TOD_EXT
+Allows user space to set/get bits 0-63 of the TOD clock register as defined in
+the POP (u64). If the guest CPU model supports the TOD clock extension (u8), it
+also allows user space to get/set it. If the guest CPU model does not support
+it, it is stored as 0 and not allowed to be set to a value != 0.
+
+Parameters: address of a buffer in user space to store the data
+            (kvm_s390_vm_tod_clock) to
+Returns:    -EFAULT if the given address is not accessible from kernel space
+           -EINVAL if setting the TOD clock extension to != 0 is not supported
+
 4. GROUP: KVM_S390_VM_CRYPTO
 Architectures: s390
 
index 109c5d9a04c4bd2149af9f5480f7ca1b1a0e5beb..7f32b510fdea9b69262a31b343942c3a7af82c77 100644 (file)
@@ -7471,18 +7471,30 @@ L:      kvm@vger.kernel.org
 W:     http://www.linux-kvm.org
 T:     git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
 S:     Supported
-F:     Documentation/*/kvm*.txt
 F:     Documentation/virtual/kvm/
-F:     arch/*/kvm/
-F:     arch/x86/kernel/kvm.c
-F:     arch/x86/kernel/kvmclock.c
-F:     arch/*/include/asm/kvm*
-F:     include/linux/kvm*
+F:     include/trace/events/kvm.h
+F:     include/uapi/asm-generic/kvm*
 F:     include/uapi/linux/kvm*
-F:     virt/kvm/
+F:     include/asm-generic/kvm*
+F:     include/linux/kvm*
+F:     include/kvm/iodev.h
+F:     virt/kvm/*
 F:     tools/kvm/
 
-KERNEL VIRTUAL MACHINE (KVM) FOR AMD-V
+KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
+M:     Paolo Bonzini <pbonzini@redhat.com>
+M:     Radim KrÄmář <rkrcmar@redhat.com>
+L:     kvm@vger.kernel.org
+W:     http://www.linux-kvm.org
+T:     git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
+S:     Supported
+F:     arch/x86/kvm/
+F:     arch/x86/include/uapi/asm/kvm*
+F:     arch/x86/include/asm/kvm*
+F:     arch/x86/kernel/kvm.c
+F:     arch/x86/kernel/kvmclock.c
+
+KERNEL VIRTUAL MACHINE FOR AMD-V (KVM/amd)
 M:     Joerg Roedel <joro@8bytes.org>
 L:     kvm@vger.kernel.org
 W:     http://www.linux-kvm.org/
@@ -7490,7 +7502,7 @@ S:        Maintained
 F:     arch/x86/include/asm/svm.h
 F:     arch/x86/kvm/svm.c
 
-KERNEL VIRTUAL MACHINE (KVM) FOR ARM
+KERNEL VIRTUAL MACHINE FOR ARM (KVM/arm)
 M:     Christoffer Dall <christoffer.dall@linaro.org>
 M:     Marc Zyngier <marc.zyngier@arm.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -7504,14 +7516,16 @@ F:      arch/arm/kvm/
 F:     virt/kvm/arm/
 F:     include/kvm/arm_*
 
-KERNEL VIRTUAL MACHINE (KVM) FOR POWERPC
+KERNEL VIRTUAL MACHINE FOR POWERPC (KVM/powerpc)
 M:     Alexander Graf <agraf@suse.com>
 L:     kvm-ppc@vger.kernel.org
 W:     http://www.linux-kvm.org/
 T:     git git://github.com/agraf/linux-2.6.git
 S:     Supported
+F:     arch/powerpc/include/uapi/asm/kvm*
 F:     arch/powerpc/include/asm/kvm*
 F:     arch/powerpc/kvm/
+F:     arch/powerpc/kernel/kvm*
 
 KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)
 M:     Christoffer Dall <christoffer.dall@linaro.org>
@@ -7538,7 +7552,8 @@ L:        linux-s390@vger.kernel.org
 W:     http://www.ibm.com/developerworks/linux/linux390/
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
 S:     Supported
-F:     Documentation/s390/kvm.txt
+F:     arch/s390/include/uapi/asm/kvm*
+F:     arch/s390/include/asm/gmap.h
 F:     arch/s390/include/asm/kvm*
 F:     arch/s390/kvm/
 F:     arch/s390/mm/gmap.c
@@ -10243,6 +10258,7 @@ F:      drivers/pci/dwc/*imx6*
 
 PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
 M:     Keith Busch <keith.busch@intel.com>
+M:     Jonathan Derrick <jonathan.derrick@intel.com>
 L:     linux-pci@vger.kernel.org
 S:     Supported
 F:     drivers/pci/host/vmd.c
@@ -10289,7 +10305,7 @@ L:      linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 S:     Maintained
 F:     drivers/pci/dwc/pci-exynos.c
 
-PCI DRIVER FOR SYNOPSIS DESIGNWARE
+PCI DRIVER FOR SYNOPSYS DESIGNWARE
 M:     Jingoo Han <jingoohan1@gmail.com>
 M:     Joao Pinto <Joao.Pinto@synopsys.com>
 L:     linux-pci@vger.kernel.org
index 8322df174bbfb84a4619123b6774d0cce8935dbf..564114eb85e143f384d1b814cc29df48150ed933 100644 (file)
@@ -312,8 +312,9 @@ common_init_pci(void)
 {
        struct pci_controller *hose;
        struct list_head resources;
+       struct pci_host_bridge *bridge;
        struct pci_bus *bus;
-       int next_busno;
+       int ret, next_busno;
        int need_domain_info = 0;
        u32 pci_mem_end;
        u32 sg_base;
@@ -336,11 +337,25 @@ common_init_pci(void)
                pci_add_resource_offset(&resources, hose->mem_space,
                                        hose->mem_space->start);
 
-               bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
-                                       hose, &resources);
-               if (!bus)
+               bridge = pci_alloc_host_bridge(0);
+               if (!bridge)
                        continue;
-               hose->bus = bus;
+
+               list_splice_init(&resources, &bridge->windows);
+               bridge->dev.parent = NULL;
+               bridge->sysdata = hose;
+               bridge->busnr = next_busno;
+               bridge->ops = alpha_mv.pci_ops;
+               bridge->swizzle_irq = alpha_mv.pci_swizzle;
+               bridge->map_irq = alpha_mv.pci_map_irq;
+
+               ret = pci_scan_root_bus_bridge(bridge);
+               if (ret) {
+                       pci_free_host_bridge(bridge);
+                       continue;
+               }
+
+               bus = hose->bus = bridge->bus;
                hose->need_domain_info = need_domain_info;
                next_busno = bus->busn_res.end + 1;
                /* Don't allow 8-bit bus number overflow inside the hose -
@@ -354,7 +369,6 @@ common_init_pci(void)
        pcibios_claim_console_setup();
 
        pci_assign_unassigned_resources();
-       pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
        for (hose = hose_head; hose; hose = hose->next) {
                bus = hose->bus;
                if (bus)
@@ -362,7 +376,6 @@ common_init_pci(void)
        }
 }
 
-
 struct pci_controller * __init
 alloc_pci_controller(void)
 {
index 2cfaa0e5c5777b2f0c49c5e0688d38cad512d840..8ae04a121186e2b090256956b3e7e425a571e1c4 100644 (file)
@@ -194,22 +194,46 @@ static struct resource irongate_mem = {
        .name   = "Irongate PCI MEM",
        .flags  = IORESOURCE_MEM,
 };
+static struct resource busn_resource = {
+       .name   = "PCI busn",
+       .start  = 0,
+       .end    = 255,
+       .flags  = IORESOURCE_BUS,
+};
 
 void __init
 nautilus_init_pci(void)
 {
        struct pci_controller *hose = hose_head;
+       struct pci_host_bridge *bridge;
        struct pci_bus *bus;
        struct pci_dev *irongate;
        unsigned long bus_align, bus_size, pci_mem;
        unsigned long memtop = max_low_pfn << PAGE_SHIFT;
+       int ret;
+
+       bridge = pci_alloc_host_bridge(0);
+       if (!bridge)
+               return;
+
+       pci_add_resource(&bridge->windows, &ioport_resource);
+       pci_add_resource(&bridge->windows, &iomem_resource);
+       pci_add_resource(&bridge->windows, &busn_resource);
+       bridge->dev.parent = NULL;
+       bridge->sysdata = hose;
+       bridge->busnr = 0;
+       bridge->ops = alpha_mv.pci_ops;
+       bridge->swizzle_irq = alpha_mv.pci_swizzle;
+       bridge->map_irq = alpha_mv.pci_map_irq;
 
        /* Scan our single hose.  */
-       bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
-       if (!bus)
+       ret = pci_scan_root_bus_bridge(bridge);
+       if (ret) {
+               pci_free_host_bridge(bridge);
                return;
+       }
 
-       hose->bus = bus;
+       bus = hose->bus = bridge->bus;
        pcibios_claim_one_bus(bus);
 
        irongate = pci_get_bus_and_slot(0, 0);
@@ -254,7 +278,6 @@ nautilus_init_pci(void)
        /* pci_common_swizzle() relies on bus->self being NULL
           for the root bus, so just clear it. */
        bus->self = NULL;
-       pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
        pci_bus_add_devices(bus);
 }
 
index 7db85ab00c522315c3108930365fc57c59fd311c..a598641eed98ef4d60dc65a25a4279a70be7e134 100644 (file)
@@ -100,6 +100,7 @@ source "arch/arc/plat-tb10x/Kconfig"
 source "arch/arc/plat-axs10x/Kconfig"
 #New platform adds here
 source "arch/arc/plat-eznps/Kconfig"
+source "arch/arc/plat-hsdk/Kconfig"
 
 endmenu
 
@@ -418,7 +419,7 @@ endif       # ISA_ARCV2
 endmenu   # "ARC CPU Configuration"
 
 config LINUX_LINK_BASE
-       hex "Linux Link Address"
+       hex "Kernel link address"
        default "0x80000000"
        help
          ARC700 divides the 32 bit phy address space into two equal halves
@@ -431,6 +432,14 @@ config LINUX_LINK_BASE
          If you don't know what the above means, leave this setting alone.
          This needs to match memory start address specified in Device Tree
 
+config LINUX_RAM_BASE
+       hex "RAM base address"
+       default LINUX_LINK_BASE
+       help
+         By default Linux is linked at base of RAM. However in some special
+         cases (such as HSDK), Linux can't be linked at start of DDR, hence
+         this option.
+
 config HIGHMEM
        bool "High Memory Support"
        select ARCH_DISCONTIGMEM_ENABLE
index 3a61cfcc38c0dd78f58247512a4d31231a2daa4b..3a4b52b7e09d61456daf12335e7e5b7c75ec7077 100644 (file)
@@ -111,6 +111,7 @@ core-y                              += arch/arc/plat-sim/
 core-$(CONFIG_ARC_PLAT_TB10X)  += arch/arc/plat-tb10x/
 core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
 core-$(CONFIG_ARC_PLAT_EZNPS)  += arch/arc/plat-eznps/
+core-$(CONFIG_ARC_SOC_HSDK)    += arch/arc/plat-hsdk/
 
 ifdef CONFIG_ARC_PLAT_EZNPS
 KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include
index a380ffa1a4589b11de92a5a0c21bc831e6dc751b..fdc266504ada273e6efaf72c18cc8c2e2f48edf2 100644 (file)
@@ -99,7 +99,7 @@
 
        memory {
                device_type = "memory";
-               /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+               /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
                reg = <0x0 0x80000000 0x0 0x1b000000>;  /* (512 - 32) MiB */
        };
 
index cc9239ef8d08c9f6efbe6dbee0323f283c4f5e37..4e6e9f57e790ac0cefcade55664124c9351e830e 100644 (file)
 
                ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
 
-               core_clk: core_clk {
+               input_clk: input-clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                       clock-frequency = <90000000>;
+                       clock-frequency = <33333333>;
+               };
+
+               core_clk: core-clk@80 {
+                       compatible = "snps,axs10x-arc-pll-clock";
+                       reg = <0x80 0x10>, <0x100 0x10>;
+                       #clock-cells = <0>;
+                       clocks = <&input_clk>;
                };
 
                core_intc: archs-intc@cpu {
 
        memory {
                device_type = "memory";
-               /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+               /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
                reg = <0x0 0x80000000 0x0 0x20000000    /* 512 MiB low mem */
                       0x1 0xc0000000 0x0 0x40000000>;  /* 1 GiB highmem */
        };
index 4ebb2170abecc7e00cd581a7ca6dcef6e94231e0..63954a8b0100ebf5746394fedb62b4825048d903 100644 (file)
 
                ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
 
-               core_clk: core_clk {
+               input_clk: input-clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                       clock-frequency = <100000000>;
+                       clock-frequency = <33333333>;
+               };
+
+               core_clk: core-clk@80 {
+                       compatible = "snps,axs10x-arc-pll-clock";
+                       reg = <0x80 0x10>, <0x100 0x10>;
+                       #clock-cells = <0>;
+                       clocks = <&input_clk>;
                };
 
                core_intc: archs-intc@cpu {
 
        memory {
                device_type = "memory";
-               /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+               /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
                reg = <0x0 0x80000000 0x0 0x20000000    /* 512 MiB low mem */
                       0x1 0xc0000000 0x0 0x40000000>;  /* 1 GiB highmem */
        };
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
new file mode 100644 (file)
index 0000000..229d13a
--- /dev/null
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Device Tree for ARC HS Development Kit
+ */
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+       model = "snps,hsdk";
+       compatible = "snps,hsdk";
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "snps,archs38";
+                       reg = <0>;
+                       clocks = <&core_clk>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "snps,archs38";
+                       reg = <1>;
+                       clocks = <&core_clk>;
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "snps,archs38";
+                       reg = <2>;
+                       clocks = <&core_clk>;
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "snps,archs38";
+                       reg = <3>;
+                       clocks = <&core_clk>;
+               };
+       };
+
+       core_clk: core-clk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <500000000>;
+       };
+
+       cpu_intc: cpu-interrupt-controller {
+               compatible = "snps,archs-intc";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
+       idu_intc: idu-interrupt-controller {
+               compatible = "snps,archs-idu-intc";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               interrupt-parent = <&cpu_intc>;
+       };
+
+       arcpct: pct {
+               compatible = "snps,archs-pct";
+       };
+
+       /* TIMER0 with interrupt for clockevent */
+       timer {
+               compatible = "snps,arc-timer";
+               interrupts = <16>;
+               interrupt-parent = <&cpu_intc>;
+               clocks = <&core_clk>;
+       };
+
+       /* 64-bit Global Free Running Counter */
+       gfrc {
+               compatible = "snps,archs-timer-gfrc";
+               clocks = <&core_clk>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&idu_intc>;
+
+               ranges = <0x00000000 0xf0000000 0x10000000>;
+
+               serial: serial@5000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x5000 0x100>;
+                       clock-frequency = <33330000>;
+                       interrupts = <6>;
+                       baud = <115200>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+               };
+
+               gmacclk: gmacclk {
+                       compatible = "fixed-clock";
+                       clock-frequency = <400000000>;
+                       #clock-cells = <0>;
+               };
+
+               mmcclk_ciu: mmcclk-ciu {
+                       compatible = "fixed-clock";
+                       clock-frequency = <100000000>;
+                       #clock-cells = <0>;
+               };
+
+               mmcclk_biu: mmcclk-biu {
+                       compatible = "fixed-clock";
+                       clock-frequency = <400000000>;
+                       #clock-cells = <0>;
+               };
+
+               ethernet@8000 {
+                       #interrupt-cells = <1>;
+                       compatible = "snps,dwmac";
+                       reg = <0x8000 0x2000>;
+                       interrupts = <10>;
+                       interrupt-names = "macirq";
+                       phy-mode = "rgmii";
+                       snps,pbl = <32>;
+                       clocks = <&gmacclk>;
+                       clock-names = "stmmaceth";
+                       phy-handle = <&phy0>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "snps,dwmac-mdio";
+                               phy0: ethernet-phy@0 {
+                                       reg = <0>;
+                                       ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+                                       ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+                                       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                               };
+                       };
+               };
+
+               ohci@60000 {
+                       compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
+                       reg = <0x60000 0x100>;
+                       interrupts = <15>;
+               };
+
+               ehci@40000 {
+                       compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
+                       reg = <0x40000 0x100>;
+                       interrupts = <15>;
+               };
+
+               mmc@a000 {
+                       compatible = "altr,socfpga-dw-mshc";
+                       reg = <0xa000 0x400>;
+                       num-slots = <1>;
+                       fifo-depth = <16>;
+                       card-detect-delay = <200>;
+                       clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+                       clock-names = "biu", "ciu";
+                       interrupts = <12>;
+                       bus-width = <4>;
+               };
+       };
+
+       memory@80000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "memory";
+               reg = <0x80000000 0x40000000>;  /* 1 GiB */
+       };
+};
index 3772c40c245ecaf546de55aac1a48e7fdff0ca85..8d787b251f73746191cfea3bd176bfb2869eccce 100644 (file)
@@ -18,7 +18,7 @@
 
        memory {
                device_type = "memory";
-               /* CONFIG_LINUX_LINK_BASE needs to match low mem start */
+               /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
                reg = <0x0 0x80000000 0x0 0x20000000    /* 512 MB low mem */
                       0x1 0x00000000 0x0 0x40000000>;  /* 1 GB highmem */
        };
diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig
new file mode 100644 (file)
index 0000000..9a3fcf4
--- /dev/null
@@ -0,0 +1,80 @@
+CONFIG_DEFAULT_HOSTNAME="ARCLinux"
+CONFIG_SYSVIPC=y
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARC_SOC_HSDK=y
+CONFIG_ISA_ARCV2=y
+CONFIG_SMP=y
+CONFIG_LINUX_LINK_BASE=0x90000000
+CONFIG_LINUX_RAM_BASE=0x80000000
+CONFIG_ARC_BUILTIN_DTB_NAME="hsdk"
+CONFIG_PREEMPT=y
+# CONFIG_COMPACTION is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_DEVTMPFS=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+CONFIG_MICREL_PHY=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_UDL=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_DW=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT3_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_ECHAINIV=y
index 02fd1cece6ef339209c993a6b56b87312e39d648..8486f328cc5d2aea087812ab19be949001e64b73 100644 (file)
@@ -47,7 +47,8 @@
        : "r"(data), "r"(ptr));         \
 })
 
-#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
+/* Largest line length for either L1 or L2 is 128 bytes */
+#define ARCH_DMA_MINALIGN      128
 
 extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
@@ -95,6 +96,8 @@ extern unsigned long perip_base, perip_end;
 #define ARC_REG_SLC_CTRL       0x903
 #define ARC_REG_SLC_FLUSH      0x904
 #define ARC_REG_SLC_INVALIDATE 0x905
+#define ARC_AUX_SLC_IVDL       0x910
+#define ARC_AUX_SLC_FLDL       0x912
 #define ARC_REG_SLC_RGN_START  0x914
 #define ARC_REG_SLC_RGN_START1 0x915
 #define ARC_REG_SLC_RGN_END    0x916
index 14c310f2e0b198ecac4d4d9f19a33d80b258005b..ec36d5b6d435bfca7a05148e05cd1f801c5cdecf 100644 (file)
        PUSHAX  lp_start
        PUSHAX  erbta
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+       .word CTOP_INST_SCHD_RW
+       PUSHAX  CTOP_AUX_GPA1
+       PUSHAX  CTOP_AUX_EFLAGS
+#endif
+
        lr      r9, [ecr]
        st      r9, [sp, PT_event]    /* EV_Trap expects r9 to have ECR */
 .endm
  * by hardware and that is not good.
  *-------------------------------------------------------------*/
 .macro EXCEPTION_EPILOGUE
+#ifdef CONFIG_ARC_PLAT_EZNPS
+       .word CTOP_INST_SCHD_RW
+       POPAX   CTOP_AUX_EFLAGS
+       POPAX   CTOP_AUX_GPA1
+#endif
+
        POPAX   erbta
        POPAX   lp_start
        POPAX   lp_end
        PUSHAX  lp_end
        PUSHAX  lp_start
        PUSHAX  bta_l\LVL\()
+
+#ifdef CONFIG_ARC_PLAT_EZNPS
+       .word CTOP_INST_SCHD_RW
+       PUSHAX  CTOP_AUX_GPA1
+       PUSHAX  CTOP_AUX_EFLAGS
+#endif
 .endm
 
 /*--------------------------------------------------------------
  * by hardware and that is not good.
  *-------------------------------------------------------------*/
 .macro INTERRUPT_EPILOGUE  LVL
+#ifdef CONFIG_ARC_PLAT_EZNPS
+       .word CTOP_INST_SCHD_RW
+       POPAX   CTOP_AUX_EFLAGS
+       POPAX   CTOP_AUX_GPA1
+#endif
+
        POPAX   bta_l\LVL\()
        POPAX   lp_start
        POPAX   lp_end
index a64c447b0337804568c69cf2e15998deabdd9b40..8a4f77ea3238e6f017ae24ab6b55e2952637fe04 100644 (file)
@@ -47,9 +47,6 @@
 #define ISA_INIT_STATUS_BITS   (STATUS_IE_MASK | STATUS_AD_MASK | \
                                        (ARCV2_IRQ_DEF_PRIO << 1))
 
-/* SLEEP needs default irq priority (<=) which can interrupt the doze */
-#define ISA_SLEEP_ARG          (0x10 | ARCV2_IRQ_DEF_PRIO)
-
 #ifndef __ASSEMBLY__
 
 /*
index 4c6eed80cd8ba3bd935e60b30ffadf147326aeca..fcb80171fc346252c55d1593ac9198862daf5b15 100644 (file)
@@ -43,8 +43,6 @@
 
 #define ISA_INIT_STATUS_BITS   STATUS_IE_MASK
 
-#define ISA_SLEEP_ARG          0x3
-
 #ifndef __ASSEMBLY__
 
 /******************************************************************
index 296c3426a6ad3589df2926c50c26832960a48ab8..109baa06831cecc38cf1d9f11ba447a31c0c4b14 100644 (file)
@@ -85,7 +85,7 @@ typedef pte_t * pgtable_t;
  */
 #define virt_to_pfn(kaddr)     (__pa(kaddr) >> PAGE_SHIFT)
 
-#define ARCH_PFN_OFFSET                virt_to_pfn(CONFIG_LINUX_LINK_BASE)
+#define ARCH_PFN_OFFSET                virt_to_pfn(CONFIG_LINUX_RAM_BASE)
 
 #ifdef CONFIG_FLATMEM
 #define pfn_valid(pfn)         (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
index 4104a08392146f6c479710557010135aa4774a15..d400a2161935de5442c0ae1ddc7159ae16c003a4 100644 (file)
@@ -27,6 +27,13 @@ struct arc_fpu {
 };
 #endif
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+struct eznps_dp {
+       unsigned int eflags;
+       unsigned int gpa1;
+};
+#endif
+
 /* Arch specific stuff which needs to be saved per task.
  * However these items are not so important so as to earn a place in
  * struct thread_info
@@ -38,6 +45,9 @@ struct thread_struct {
 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
        struct arc_fpu fpu;
 #endif
+#ifdef CONFIG_ARC_PLAT_EZNPS
+       struct eznps_dp dp;
+#endif
 };
 
 #define INIT_THREAD  {                          \
index 5297faa8a37803fd702da4270a7e23f5d6ba4f2b..5a8cb22724a1ef21a5043c6954aeed22c7904ff7 100644 (file)
 #ifdef CONFIG_ISA_ARCOMPACT
 struct pt_regs {
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+       unsigned long eflags;   /* Extended FLAGS */
+       unsigned long gpa1;     /* General Purpose Aux */
+#endif
+
        /* Real registers */
        unsigned long bta;      /* bta_l1, bta_l2, erbta */
 
index a325e6a365231cca8b39890b0d2db6253d4efcaf..47efc8451b7034b752337e0958af0d653470bc57 100644 (file)
@@ -247,9 +247,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
        __asm__ __volatile__(
        "1:     ex  %0, [%1]            \n"
+#ifdef CONFIG_EZNPS_MTM_EXT
+       "       .word %3                \n"
+#endif
        "       breq  %0, %2, 1b        \n"
        : "+&r" (val)
        : "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
+#ifdef CONFIG_EZNPS_MTM_EXT
+       , "i"(CTOP_INST_SCHD_RW)
+#endif
        : "memory");
 
        /*
@@ -291,6 +297,12 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
         */
        smp_mb();
 
+       /*
+        * EX is not really required here, a simple STore of 0 suffices.
+        * However this causes tasklist livelocks in SystemC based SMP virtual
+        * platforms where the systemc core scheduler uses EX as a cue for
+        * moving to next core. Do a git log of this file for details
+        */
        __asm__ __volatile__(
        "       ex  %0, [%1]            \n"
        : "+r" (val)
index 1b171ab5fec0523f5dec5b1732b3d1c97f1243d8..f7d07feeea61593786682e0e81a7ce7236ee6016 100644 (file)
@@ -26,10 +26,19 @@ extern void fpu_save_restore(struct task_struct *p, struct task_struct *n);
 
 #endif /* !CONFIG_ARC_FPU_SAVE_RESTORE */
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+extern void dp_save_restore(struct task_struct *p, struct task_struct *n);
+#define ARC_EZNPS_DP_PREV(p, n)      dp_save_restore(p, n)
+#else
+#define ARC_EZNPS_DP_PREV(p, n)
+
+#endif /* !CONFIG_ARC_PLAT_EZNPS */
+
 struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n);
 
 #define switch_to(prev, next, last)    \
 do {                                   \
+       ARC_EZNPS_DP_PREV(prev, next);  \
        ARC_FPU_PREV(prev, next);       \
        last = __switch_to(prev, next);\
        ARC_FPU_NEXT(next);             \
index 8942c5c3b4c519eed7227200eaaa54cc4468698e..2dc5f4296d44afdb43aa20627e498f5364818c95 100644 (file)
@@ -12,7 +12,6 @@ obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
 obj-y  += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o
 obj-$(CONFIG_ISA_ARCOMPACT)            += entry-compact.o intc-compact.o
 obj-$(CONFIG_ISA_ARCV2)                        += entry-arcv2.o intc-arcv2.o
-obj-$(CONFIG_PCI)                      += pcibios.o
 
 obj-$(CONFIG_MODULES)                  += arcksyms.o module.o
 obj-$(CONFIG_SMP)                      += smp.o
index 3b67f538f1425699219fb2cd481be592ba047731..521ef3521a1cc932b8ae71f74bda9ce1491c3d98 100644 (file)
@@ -29,8 +29,9 @@ static void __init arc_set_early_base_baud(unsigned long dt_root)
 {
        if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x"))
                arc_base_baud = 166666666;      /* Fixed 166.6MHz clk (TB10x) */
-       else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp"))
-               arc_base_baud = 33333333;       /* Fixed 33MHz clk (AXS10x) */
+       else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp") ||
+                of_flat_dt_is_compatible(dt_root, "snps,hsdk"))
+               arc_base_baud = 33333333;       /* Fixed 33MHz clk (AXS10x & HSDK) */
        else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps"))
                arc_base_baud = 800000000;      /* Fixed 800MHz clk (NPS) */
        else
index 9211707634dcf57e1aa0ac13fa4a6bbc79b99eeb..f285dbb280666cc1d9094d4175913e42b2b44587 100644 (file)
  *
  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
  *   need ptregs anymore
  *
  * Vineetg: Oct 2009
  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
  */
 
 #include <linux/errno.h>
-#include <linux/linkage.h>     /* {EXTRY,EXIT} */
+#include <linux/linkage.h>     /* {ENTRY,EXIT} */
 #include <asm/entry.h>
 #include <asm/irqflags.h>
 
@@ -80,8 +80,8 @@
        .align 4
 
 /* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
  * a section other than .vector.
  */
 
@@ -105,13 +105,13 @@ VECTOR   handle_interrupt_level1 ; Other devices
 
 ; ******************** Exceptions **********************
 VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
-VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
+VECTOR   EV_TLBMissI             ; 0x108, Instruction TLB miss  (0x21)
 VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
 VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
                                 ;         or Misaligned Access
 VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
 VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
-VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
+VECTOR   EV_Extension            ; 0x130, Extn Instruction Excp (0x26)
 
 .rept   24
 VECTOR   reserved                ; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
 
 ; ---------------------------------------------
 ; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
 ; ---------------------------------------------
 ENTRY(mem_service)
 
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
        ;------ (5) Type of Protection Violation? ----------
        ;
        ; ProtV Hardware Exception is triggered for Access Faults of 2 types
-       ;   -Access Violaton    : 00_23_(00|01|02|03)_00
+       ;   -Access Violation   : 00_23_(00|01|02|03)_00
        ;                                x  r  w  r+w
        ;   -Unaligned Access   : 00_23_04_00
        ;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
 
 .Lrestore_regs:
 
-       # Interrpts are actually disabled from this point on, but will get
+       # Interrupts are actually disabled from this point on, but will get
        # reenabled after we return from interrupt/exception.
        # But irq tracer needs to be told now...
        TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
        lr      r10, [status32]
 
        ; Restore REG File. In case multiple Events outstanding,
-       ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+       ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
        ; Note that we use realtime STATUS32 (not pt_regs->status32) to
        ; decide that.
 
index 1eea99beecc3b016c0f9d13129da65c26d333c30..85d9ea4a0acccc937a1cf51b29fc0480afa4010d 100644 (file)
@@ -92,6 +92,12 @@ ENTRY(EV_MachineCheck)
        lr  r0, [efa]
        mov r1, sp
 
+       ; hardware auto-disables MMU, re-enable it to allow kernel vaddr
+       ; access for say stack unwinding of modules for crash dumps
+       lr      r3, [ARC_REG_PID]
+       or      r3, r3, MMU_ENABLE
+       sr      r3, [ARC_REG_PID]
+
        lsr     r3, r2, 8
        bmsk    r3, r3, 7
        brne    r3, ECR_C_MCHK_DUP_TLB, 1f
diff --git a/arch/arc/kernel/pcibios.c b/arch/arc/kernel/pcibios.c
deleted file mode 100644 (file)
index 72e1d73..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/pci.h>
-
-/*
- * We don't have to worry about legacy ISA devices, so nothing to do here
- */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-}
index 2a018de6d6cdbce2abc9f02b9671c41136c9ffb7..5ac3b547453fd5b4b5393fdc10dfff34a047941f 100644 (file)
@@ -79,15 +79,40 @@ done:
        return uval;
 }
 
+#ifdef CONFIG_ISA_ARCV2
+
 void arch_cpu_idle(void)
 {
-       /* sleep, but enable all interrupts before committing */
+       /* Re-enable interrupts <= default irq priority before commiting SLEEP */
+       const unsigned int arg = 0x10 | ARCV2_IRQ_DEF_PRIO;
+
        __asm__ __volatile__(
                "sleep %0       \n"
                :
-               :"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const */
+               :"I"(arg)); /* can't be "r" has to be embedded const */
+}
+
+#elif defined(CONFIG_EZNPS_MTM_EXT)    /* ARC700 variant in NPS */
+
+void arch_cpu_idle(void)
+{
+       /* only the calling HW thread needs to sleep */
+       __asm__ __volatile__(
+               ".word %0       \n"
+               :
+               :"i"(CTOP_INST_HWSCHD_WFT_IE12));
+}
+
+#else  /* ARC700 */
+
+void arch_cpu_idle(void)
+{
+       /* sleep, but enable both set E1/E2 (levels of interrutps) before committing */
+       __asm__ __volatile__("sleep 0x3 \n");
 }
 
+#endif
+
 asmlinkage void ret_from_fork(void);
 
 /*
@@ -209,6 +234,10 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
         */
        regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS;
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+       regs->eflags = 0;
+#endif
+
        /* bogus seed values for debugging */
        regs->lp_start = 0x10;
        regs->lp_end = 0x80;
index 666613fde91d09cb48f76370dc5b9ff0bd91feae..c4ffb441716c405d61cc16fd74e6fe071076940f 100644 (file)
@@ -385,13 +385,13 @@ void setup_processor(void)
        read_arc_build_cfg_regs();
        arc_init_IRQ();
 
-       printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+       pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
        arc_mmu_init();
        arc_cache_init();
 
-       printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-       printk(arc_platform_smp_cpuinfo());
+       pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+       pr_info("%s", arc_platform_smp_cpuinfo());
 
        arc_chk_core_config();
 }
index ff83e78d0cfb5583eb44e874c0fd290cdeb24926..bcd7c9fc5d0fc9868c04ff98d08b2e1492d50bb8 100644 (file)
@@ -80,7 +80,7 @@ int name(unsigned long address, struct pt_regs *regs) \
 DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)
 DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
 DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
-DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
+DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", __weak do_memory_error, BUS_ADRERR)
 DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
 DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
 
@@ -103,7 +103,7 @@ int do_misaligned_access(unsigned long address, struct pt_regs *regs,
  */
 void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
 {
-       die("Machine Check Exception", regs, address);
+       die("Unhandled Machine Check Exception", regs, address);
 }
 
 
index f9caf79186d42dac848e2ca4ed8bd728bb659279..7e94476f39943026eda5522f281d50233b4d8d79 100644 (file)
@@ -140,7 +140,7 @@ static void show_ecr_verbose(struct pt_regs *regs)
        } else if (vec == ECR_V_ITLB_MISS) {
                pr_cont("Insn could not be fetched\n");
        } else if (vec == ECR_V_MACH_CHK) {
-               pr_cont("%s\n", (cause_code == 0x0) ?
+               pr_cont("Machine Check (%s)\n", (cause_code == 0x0) ?
                                        "Double Fault" : "Other Fatal Err");
 
        } else if (vec == ECR_V_PROTV) {
@@ -233,6 +233,9 @@ void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
 {
        current->thread.fault_address = address;
 
+       /* Show fault description */
+       pr_info("\n%s\n", str);
+
        /* Caller and Callee regs */
        show_regs(regs);
 
index 7db283b46ebde8daccf779525e82526e47ad2722..eee924dfffa6e1baf08221ee5e7e2cd23937d782 100644 (file)
@@ -652,7 +652,7 @@ static void __ic_line_inv_vaddr(phys_addr_t paddr, unsigned long vaddr,
 
 #endif /* CONFIG_ARC_HAS_ICACHE */
 
-noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
+noinline void slc_op_rgn(phys_addr_t paddr, unsigned long sz, const int op)
 {
 #ifdef CONFIG_ISA_ARCV2
        /*
@@ -715,6 +715,58 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 #endif
 }
 
+noinline void slc_op_line(phys_addr_t paddr, unsigned long sz, const int op)
+{
+#ifdef CONFIG_ISA_ARCV2
+       /*
+        * SLC is shared between all cores and concurrent aux operations from
+        * multiple cores need to be serialized using a spinlock
+        * A concurrent operation can be silently ignored and/or the old/new
+        * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop
+        * below)
+        */
+       static DEFINE_SPINLOCK(lock);
+
+       const unsigned long SLC_LINE_MASK = ~(l2_line_sz - 1);
+       unsigned int ctrl, cmd;
+       unsigned long flags;
+       int num_lines;
+
+       spin_lock_irqsave(&lock, flags);
+
+       ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
+
+       /* Don't rely on default value of IM bit */
+       if (!(op & OP_FLUSH))           /* i.e. OP_INV */
+               ctrl &= ~SLC_CTRL_IM;   /* clear IM: Disable flush before Inv */
+       else
+               ctrl |= SLC_CTRL_IM;
+
+       write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
+
+       cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
+
+       sz += paddr & ~SLC_LINE_MASK;
+       paddr &= SLC_LINE_MASK;
+
+       num_lines = DIV_ROUND_UP(sz, l2_line_sz);
+
+       while (num_lines-- > 0) {
+               write_aux_reg(cmd, paddr);
+               paddr += l2_line_sz;
+       }
+
+       /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+       read_aux_reg(ARC_REG_SLC_CTRL);
+
+       while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
+
+       spin_unlock_irqrestore(&lock, flags);
+#endif
+}
+
+#define slc_op(paddr, sz, op)  slc_op_rgn(paddr, sz, op)
+
 noinline static void slc_entire_op(const int op)
 {
        unsigned int ctrl, r = ARC_REG_SLC_CTRL;
@@ -1095,7 +1147,7 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
  */
 noinline void __init arc_ioc_setup(void)
 {
-       unsigned int ap_sz;
+       unsigned int ioc_base, mem_sz;
 
        /* Flush + invalidate + disable L1 dcache */
        __dc_disable();
@@ -1104,18 +1156,29 @@ noinline void __init arc_ioc_setup(void)
        if (read_aux_reg(ARC_REG_SLC_BCR))
                slc_entire_op(OP_FLUSH_N_INV);
 
-       /* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
-       write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
-
        /*
-        * IOC Aperture size:
-        *   decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
+        * currently IOC Aperture covers entire DDR
         * TBD: fix for PGU + 1GB of low mem
         * TBD: fix for PAE
         */
-       ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
-       write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
+       mem_sz = arc_get_mem_sz();
+
+       if (!is_power_of_2(mem_sz) || mem_sz < 4096)
+               panic("IOC Aperture size must be power of 2 larger than 4KB");
+
+       /*
+        * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
+        * so setting 0x11 implies 512MB, 0x12 implies 1GB...
+        */
+       write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);
+
+       /* for now assume kernel base is start of IOC aperture */
+       ioc_base = CONFIG_LINUX_RAM_BASE;
+
+       if (ioc_base % mem_sz != 0)
+               panic("IOC Aperture start must be aligned to the size of the aperture");
 
+       write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);
        write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
        write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
 
@@ -1207,7 +1270,7 @@ void __ref arc_cache_init(void)
        unsigned int __maybe_unused cpu = smp_processor_id();
        char str[256];
 
-       printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+       pr_info("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
        if (!cpu)
                arc_cache_init_master();
index 162c975288725167a02ab369cc5c5445dd1ac5db..a0b7bd6d030d698594b844886768f5ddc690b04b 100644 (file)
@@ -207,7 +207,7 @@ no_context:
        /* Are we prepared to handle this kernel fault?
         *
         * (The kernel has valid exception-points in the source
-        *  when it acesses user-memory. When it fails in one
+        *  when it accesses user-memory. When it fails in one
         *  of those points, we find it in a table and do a jump
         *  to some fixup code that loads an appropriate error
         *  code)
index 8c9415ed62804d0a8b4a35df176f1b43e6c1be44..ba145065c579bfff5af1d0ca4e569a8b8c49da32 100644 (file)
@@ -26,7 +26,7 @@ pgd_t swapper_pg_dir[PTRS_PER_PGD] __aligned(PAGE_SIZE);
 char empty_zero_page[PAGE_SIZE] __aligned(PAGE_SIZE);
 EXPORT_SYMBOL(empty_zero_page);
 
-static const unsigned long low_mem_start = CONFIG_LINUX_LINK_BASE;
+static const unsigned long low_mem_start = CONFIG_LINUX_RAM_BASE;
 static unsigned long low_mem_sz;
 
 #ifdef CONFIG_HIGHMEM
@@ -63,7 +63,7 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 
        if (!low_mem_sz) {
                if (base != low_mem_start)
-                       panic("CONFIG_LINUX_LINK_BASE != DT memory { }");
+                       panic("CONFIG_LINUX_RAM_BASE != DT memory { }");
 
                low_mem_sz = size;
                in_use = 1;
@@ -161,7 +161,7 @@ void __init setup_arch_memory(void)
         * We can't use the helper free_area_init(zones[]) because it uses
         * PAGE_OFFSET to compute the @min_low_pfn which would be wrong
         * when our kernel doesn't start at PAGE_OFFSET, i.e.
-        * PAGE_OFFSET != CONFIG_LINUX_LINK_BASE
+        * PAGE_OFFSET != CONFIG_LINUX_RAM_BASE
         */
        free_area_init_node(0,                  /* node-id */
                            zones_size,         /* num pages per zone */
index b181f3ee38aab54565d8de8c1e5136375c6358cc..8ceefbf72fb0f8b0d1ce9ca1516bb7edd487cc9a 100644 (file)
@@ -821,7 +821,7 @@ void arc_mmu_init(void)
        char str[256];
        struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
 
-       printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+       pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
        /*
         * Can't be done in processor.h due to header include depenedencies
@@ -908,9 +908,6 @@ void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
 
        local_irq_save(flags);
 
-       /* re-enable the MMU */
-       write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
-
        /* loop thru all sets of TLB */
        for (set = 0; set < mmu->sets; set++) {
 
index b30e4e36bb00dd3c5feaa685fe08dd0629404119..0e1e47a67c73617232c4ed62ca96c2ac74286975 100644 (file)
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+       /* verify if entry for this vaddr+ASID already exists */
+       sr    TLBProbe, [ARC_REG_TLBCOMMAND]
+       lr    r0, [ARC_REG_TLBINDEX]
+       bbit0 r0, 31, 88f
+#endif
+
        /* Get free TLB slot: Set = computed from vaddr, way = random */
        sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,8 @@ ex_saved_reg1:
 #else
        sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+
+88:
 .endm
 
 
index 38ff349d7f2a79331fbaac9e33bb4ba2325aef1a..f1ac6790da5fe64782b59b720bf3ea80d999bff1 100644 (file)
@@ -80,22 +80,6 @@ static void __init axs10x_enable_gpio_intc_wire(void)
        iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
 }
 
-static inline void __init
-write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)
-{
-       unsigned int loops = 128 * 1024, ctr;
-
-       iowrite32(value, reg);
-
-       ctr = loops;
-       while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */
-               cpu_relax();
-
-       ctr = loops;
-       while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */
-               cpu_relax();
-}
-
 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
 {
        union ver {
@@ -314,7 +298,6 @@ static void __init axs101_early_init(void)
 
 #ifdef CONFIG_AXS103
 
-#define AXC003_CGU     0xF0000000
 #define AXC003_CREG    0xF0001000
 #define AXC003_MST_AXI_TUNNEL  0
 #define AXC003_MST_HS38                1
@@ -324,131 +307,38 @@ static void __init axs101_early_init(void)
 #define CREG_CPU_TUN_IO_CTRL   (AXC003_CREG + 0x494)
 
 
-union pll_reg {
-       struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-               unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6;
-#else
-               unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17;
-#endif
-       };
-       unsigned int val;
-};
-
-static unsigned int __init axs103_get_freq(void)
-{
-       union pll_reg idiv, fbdiv, odiv;
-       unsigned int f = 33333333;
-
-       idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
-       fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
-       odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
-
-       if (idiv.bypass != 1)
-               f = f / (idiv.low + idiv.high);
-
-       if (fbdiv.bypass != 1)
-               f = f * (fbdiv.low + fbdiv.high);
-
-       if (odiv.bypass != 1)
-               f = f / (odiv.low + odiv.high);
-
-       f = (f + 500000) / 1000000; /* Rounding */
-       return f;
-}
-
-static inline unsigned int __init encode_div(unsigned int id, int upd)
-{
-       union pll_reg div;
-
-       div.val = 0;
-
-       div.noupd = !upd;
-       div.bypass = id == 1 ? 1 : 0;
-       div.edge = (id%2 == 0) ? 0 : 1;  /* 0 = rising */
-       div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
-       div.high = id >> 1;
-
-       return div.val;
-}
-
-noinline static void __init
-axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
-{
-       write_cgu_reg(encode_div(id, 0),
-                     (void __iomem *)AXC003_CGU + 0x80 + 0,
-                     (void __iomem *)AXC003_CGU + 0x110);
-
-       write_cgu_reg(encode_div(fd, 0),
-                     (void __iomem *)AXC003_CGU + 0x80 + 4,
-                     (void __iomem *)AXC003_CGU + 0x110);
-
-       write_cgu_reg(encode_div(od, 1),
-                     (void __iomem *)AXC003_CGU + 0x80 + 8,
-                     (void __iomem *)AXC003_CGU + 0x110);
-}
-
 static void __init axs103_early_init(void)
 {
-       int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
-       const struct fdt_property *prop = fdt_get_property(initial_boot_params,
-                                                          offset,
-                                                          "clock-frequency",
-                                                          NULL);
-       u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
-
+#ifdef CONFIG_ARC_MCIP
        /*
         * AXS103 configurations for SMP/QUAD configurations share device tree
-        * which defaults to 90 MHz. However recent failures of Quad config
+        * which defaults to 100 MHz. However recent failures of Quad config
         * revealed P&R timing violations so clamp it down to safe 50 MHz
         * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
-        *
-        * This hack is really hacky as of now. Fix it properly by getting the
-        * number of cores as return value of platform's early SMP callback
+        * of fudging the freq in DT
         */
-#ifdef CONFIG_ARC_MCIP
        unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
-       if (num_cores > 2)
-               freq = 50;
-#endif
-
-       switch (freq) {
-       case 33:
-               axs103_set_freq(1, 1, 1);
-               break;
-       case 50:
-               axs103_set_freq(1, 30, 20);
-               break;
-       case 75:
-               axs103_set_freq(2, 45, 10);
-               break;
-       case 90:
-               axs103_set_freq(2, 54, 10);
-               break;
-       case 100:
-               axs103_set_freq(1, 30, 10);
-               break;
-       case 125:
-               axs103_set_freq(2, 45,  6);
-               break;
-       default:
+       if (num_cores > 2) {
+               u32 freq = 50, orig;
                /*
-                * In this case, core_frequency derived from
-                * DT "clock-frequency" might not match with board value.
-                * Hence update it to match the board value.
+                * TODO: use cpu node "cpu-freq" param instead of platform-specific
+                * "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
                 */
-               freq = axs103_get_freq();
-               break;
-       }
-
-       pr_info("Freq is %dMHz\n", freq);
-
-       /* Patching .dtb in-place with new core clock value */
-       if (freq != orig ) {
-               freq = cpu_to_be32(freq * 1000000);
-               fdt_setprop_inplace(initial_boot_params, offset,
-                                   "clock-frequency", &freq, sizeof(freq));
+               int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
+               const struct fdt_property *prop;
+
+               prop = fdt_get_property(initial_boot_params, off,
+                                       "clock-frequency", NULL);
+               orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;
+
+               /* Patching .dtb in-place with new core clock value */
+               if (freq != orig ) {
+                       freq = cpu_to_be32(freq * 1000000);
+                       fdt_setprop_inplace(initial_boot_params, off,
+                                           "clock-frequency", &freq, sizeof(freq));
+               }
        }
+#endif
 
        /* Memory maps already config in pre-bootloader */
 
index 1595a38e50cd86f841639702b2b707243c64f5d8..e151e2067886ea52ec75d151210c9e71a4ec0a81 100644 (file)
@@ -12,8 +12,8 @@ menuconfig ARC_PLAT_EZNPS
        help
          Support for EZchip development platforms,
          based on ARC700 cores.
-         We handle few flavours:
-           - Hardware Emulator AKA HE which is FPGA based chasis
+         We handle few flavors:
+           - Hardware Emulator AKA HE which is FPGA based chassis
            - Simulator based on MetaWare nSIM
            - NPS400 chip based on ASIC
 
@@ -32,3 +32,25 @@ config EZNPS_MTM_EXT
          any of them seem like CPU from Linux point of view.
          All threads within same core share the execution unit of the
          core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR_ALIGN
+       bool "ARC-EZchip Memory error as an exception"
+       depends on EZNPS_MTM_EXT
+       default n
+       help
+         On the real chip of the NPS, user memory errors are handled
+         as a machine check exception, which is fatal, whereas on
+         simulator platform for NPS, is handled as a Level 2 interrupt
+         (just a stock ARC700) which is recoverable. This option makes
+         simulator behave like hardware.
+
+config EZNPS_SHARED_AUX_REGS
+       bool "ARC-EZchip Shared Auxiliary Registers Per Core"
+       depends on ARC_PLAT_EZNPS
+       default y
+       help
+         On the real chip of the NPS, auxiliary registers are shared between
+         all the cpus of the core, whereas on simulator platform for NPS,
+         each cpu has a different set of auxiliary registers. Configuration
+         should be unset if auxiliary registers are not shared between the cpus
+         of the core, so there will be a need to initialize them per cpu.
index 21091b199df025141c76b8c8fcac2e62fc5d6115..8d4371706b2fcc6d1c3d7c4487c9d7c2237dbbd3 100644 (file)
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y := entry.o platform.o
+obj-y := entry.o platform.o ctop.o
 obj-$(CONFIG_SMP) += smp.o
 obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
diff --git a/arch/arc/plat-eznps/ctop.c b/arch/arc/plat-eznps/ctop.c
new file mode 100644 (file)
index 0000000..030bcd0
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include <linux/sched.h>
+#include <asm/processor.h>
+#include <plat/ctop.h>
+
+void dp_save_restore(struct task_struct *prev, struct task_struct *next)
+{
+       struct eznps_dp *prev_task_dp = &prev->thread.dp;
+       struct eznps_dp *next_task_dp = &next->thread.dp;
+
+       /* Here we save all Data Plane related auxiliary registers */
+       prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS);
+       write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags);
+
+       prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1);
+       write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1);
+}
index 328261c27cdac008543898c8f115da9c24f95e09..091c92c32ab65c24d8a8f79ca444e4b9d1408c19 100644 (file)
@@ -27,7 +27,7 @@
        .align 1024     ; HW requierment for restart first PC
 
 ENTRY(res_service)
-#ifdef CONFIG_EZNPS_MTM_EXT
+#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
        ; There is no work for HW thread id != 0
        lr      r3, [CTOP_AUX_THREAD_ID]
        cmp     r3, 0
index ee2e32df5e90d5d77090a415335ac6f4708e161b..0c7d11022d0f8875256e64162d2ee0f1f0aa85e1 100644 (file)
@@ -39,6 +39,7 @@
 #define CTOP_AUX_LOGIC_CORE_ID                 (CTOP_AUX_BASE + 0x018)
 #define CTOP_AUX_MT_CTRL                       (CTOP_AUX_BASE + 0x020)
 #define CTOP_AUX_HW_COMPLY                     (CTOP_AUX_BASE + 0x024)
+#define CTOP_AUX_DPC                           (CTOP_AUX_BASE + 0x02C)
 #define CTOP_AUX_LPC                           (CTOP_AUX_BASE + 0x030)
 #define CTOP_AUX_EFLAGS                                (CTOP_AUX_BASE + 0x080)
 #define CTOP_AUX_IACK                          (CTOP_AUX_BASE + 0x088)
@@ -46,6 +47,7 @@
 #define CTOP_AUX_UDMC                          (CTOP_AUX_BASE + 0x300)
 
 /* EZchip core instructions */
+#define CTOP_INST_HWSCHD_WFT_IE12              0x3E6F7344
 #define CTOP_INST_HWSCHD_OFF_R4                        0x3C6F00BF
 #define CTOP_INST_HWSCHD_RESTORE_R4            0x3E6F7103
 #define CTOP_INST_SCHD_RW                      0x3E6F7004
index aaaaffd3d94052fbbbd65da8b7eb509b72eb01d5..2388de3d09ef9e71f710ec4625e20a9e85cbdc1e 100644 (file)
 #include <plat/mtm.h>
 #include <plat/smp.h>
 
-#define MT_CTRL_HS_CNT         0xFF
+#define MT_HS_CNT_MIN          0x01
+#define MT_HS_CNT_MAX          0xFF
 #define MT_CTRL_ST_CNT         0xF
 #define NPS_NUM_HW_THREADS     0x10
 
+static int mtm_hs_ctr = MT_HS_CNT_MAX;
+
+#ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN
+int do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+       die("Invalid Mem Access", regs, address);
+
+       return 1;
+}
+#endif
+
 static void mtm_init_nat(int cpu)
 {
        struct nps_host_reg_mtm_cfg mtm_cfg;
@@ -98,6 +110,18 @@ void mtm_enable_core(unsigned int cpu)
        int i;
        struct nps_host_reg_aux_mt_ctrl mt_ctrl;
        struct nps_host_reg_mtm_cfg mtm_cfg;
+       struct nps_host_reg_aux_dpc dpc;
+
+       /*
+        * Initializing dpc register in each CPU.
+        * Overwriting the init value of the DPC
+        * register so that CMEM and FMT virtual address
+        * spaces are accessible, and Data Plane HW
+        * facilities are enabled.
+        */
+       dpc.ien = 1;
+       dpc.men = 1;
+       write_aux_reg(CTOP_AUX_DPC, dpc.value);
 
        if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
                return;
@@ -118,9 +142,7 @@ void mtm_enable_core(unsigned int cpu)
        /* Enable HW schedule, stall counter, mtm */
        mt_ctrl.value = 0;
        mt_ctrl.hsen = 1;
-       mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
-       mt_ctrl.sten = 1;
-       mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
+       mt_ctrl.hs_cnt = mtm_hs_ctr;
        mt_ctrl.mten = 1;
        write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
@@ -131,3 +153,23 @@ void mtm_enable_core(unsigned int cpu)
         */
        cpu_relax();
 }
+
+/* Verify and set the value of the mtm hs counter */
+static int __init set_mtm_hs_ctr(char *ctr_str)
+{
+       long hs_ctr;
+       int ret;
+
+       ret = kstrtol(ctr_str, 0, &hs_ctr);
+
+       if (ret || hs_ctr > MT_HS_CNT_MAX || hs_ctr < MT_HS_CNT_MIN) {
+               pr_err("** Invalid @nps_mtm_hs_ctr [%d] needs to be [%d:%d] (incl)\n",
+                      hs_ctr, MT_HS_CNT_MIN, MT_HS_CNT_MAX);
+               return -EINVAL;
+       }
+
+       mtm_hs_ctr = hs_ctr;
+
+       return 0;
+}
+early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
diff --git a/arch/arc/plat-hsdk/Kconfig b/arch/arc/plat-hsdk/Kconfig
new file mode 100644 (file)
index 0000000..5a6ed5a
--- /dev/null
@@ -0,0 +1,9 @@
+# Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+
+menuconfig ARC_SOC_HSDK
+       bool "ARC HS Development Kit SOC"
diff --git a/arch/arc/plat-hsdk/Makefile b/arch/arc/plat-hsdk/Makefile
new file mode 100644 (file)
index 0000000..9a50c51
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+
+obj-y := platform.o
diff --git a/arch/arc/plat-hsdk/platform.c b/arch/arc/plat-hsdk/platform.c
new file mode 100644 (file)
index 0000000..a2e7fd1
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * ARC HSDK Platform support code
+ *
+ * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <asm/arcregs.h>
+#include <asm/io.h>
+#include <asm/mach_desc.h>
+
+#define ARC_CCM_UNUSED_ADDR    0x60000000
+
+static void __init hsdk_init_per_cpu(unsigned int cpu)
+{
+       /*
+        * By default ICCM is mapped to 0x7z while this area is used for
+        * kernel virtual mappings, so move it to currently unused area.
+        */
+       if (cpuinfo_arc700[cpu].iccm.sz)
+               write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
+
+       /*
+        * By default DCCM is mapped to 0x8z while this area is used by kernel,
+        * so move it to currently unused area.
+        */
+       if (cpuinfo_arc700[cpu].dccm.sz)
+               write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
+}
+
+#define ARC_PERIPHERAL_BASE    0xf0000000
+#define CREG_BASE              (ARC_PERIPHERAL_BASE + 0x1000)
+#define CREG_PAE               (CREG_BASE + 0x180)
+#define CREG_PAE_UPDATE                (CREG_BASE + 0x194)
+
+static void __init hsdk_init_early(void)
+{
+       /*
+        * PAE remapping for DMA clients does not work due to an RTL bug, so
+        * CREG_PAE register must be programmed to all zeroes, otherwise it
+        * will cause problems with DMA to/from peripherals even if PAE40 is
+        * not used.
+        */
+
+       /* Default is 1, which means "PAE offset = 4GByte" */
+       writel_relaxed(0, (void __iomem *) CREG_PAE);
+
+       /* Really apply settings made above */
+       writel(1, (void __iomem *) CREG_PAE_UPDATE);
+}
+
+static const char *hsdk_compat[] __initconst = {
+       "snps,hsdk",
+       NULL,
+};
+
+MACHINE_START(SIMULATION, "hsdk")
+       .dt_compat      = hsdk_compat,
+       .init_early     = hsdk_init_early,
+       .init_per_cpu   = hsdk_init_per_cpu,
+MACHINE_END
index ebf020b02bc8ff60623ccccfd100f7f0addeeb97..c8781450905be94995e0df72aeb3cc722afd1b60 100644 (file)
 
 #define HSR_DABT_S1PTW         (_AC(1, UL) << 7)
 #define HSR_DABT_CM            (_AC(1, UL) << 8)
-#define HSR_DABT_EA            (_AC(1, UL) << 9)
 
 #define kvm_arm_exception_type \
        {0, "RESET" },          \
index 9a8a45aaf19a4d4eeeece7d2616833644fe35090..98089ffd91bb602649cc7724adafe5ce045b9c8a 100644 (file)
@@ -149,11 +149,6 @@ static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu)
        return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
 }
 
-static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
-{
-       return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_EA;
-}
-
 static inline bool kvm_vcpu_dabt_iss1tw(struct kvm_vcpu *vcpu)
 {
        return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_S1PTW;
@@ -206,6 +201,25 @@ static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
        return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
 }
 
+static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
+{
+       switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
+       case FSC_SEA:
+       case FSC_SEA_TTW0:
+       case FSC_SEA_TTW1:
+       case FSC_SEA_TTW2:
+       case FSC_SEA_TTW3:
+       case FSC_SECC:
+       case FSC_SECC_TTW0:
+       case FSC_SECC_TTW1:
+       case FSC_SECC_TTW2:
+       case FSC_SECC_TTW3:
+               return true;
+       default:
+               return false;
+       }
+}
+
 static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
 {
        return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
index 54442e3753542e342d8ba8b2c227ec4f31910175..cf8bf6bf87c4b822ff6f19f0206602baca519479 100644 (file)
@@ -67,7 +67,7 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
        if (kvm_vcpu_get_hsr(vcpu) & HSR_WFI_IS_WFE) {
                trace_kvm_wfx(*vcpu_pc(vcpu), true);
                vcpu->stat.wfe_exit_stat++;
-               kvm_vcpu_on_spin(vcpu);
+               kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu));
        } else {
                trace_kvm_wfx(*vcpu_pc(vcpu), false);
                vcpu->stat.wfi_exit_stat++;
index 69c56f7316c4577105f44d01762d5d1852df05df..5b78ce16a87e75ad355895777e2de8a1e8f1e12b 100644 (file)
                linux,pci-domain = <0>;
                max-link-speed = <1>;
                msi-map = <0x0 &its 0x0 0x1000>;
-               phys = <&pcie_phy>;
-               phy-names = "pcie-phy";
+               phys = <&pcie_phy 0>, <&pcie_phy 1>,
+                      <&pcie_phy 2>, <&pcie_phy 3>;
+               phy-names = "pcie-phy-0", "pcie-phy-1",
+                           "pcie-phy-2", "pcie-phy-3";
                ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
                          0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
                resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
                        compatible = "rockchip,rk3399-pcie-phy";
                        clocks = <&cru SCLK_PCIEPHY_REF>;
                        clock-names = "refclk";
-                       #phy-cells = <0>;
+                       #phy-cells = <1>;
                        resets = <&cru SRST_PCIEPHY>;
                        reset-names = "phy";
                        status = "disabled";
index fe39e6841326f01c9ae2d933b8048459c2e8ef6e..e5df3fce00082a3aa6d1711188e6d1055012dc9d 100644 (file)
@@ -188,11 +188,6 @@ static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
        return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
 }
 
-static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
-{
-       return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_EA);
-}
-
 static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
 {
        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
@@ -240,6 +235,25 @@ static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
        return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
 }
 
+static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
+{
+       switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
+       case FSC_SEA:
+       case FSC_SEA_TTW0:
+       case FSC_SEA_TTW1:
+       case FSC_SEA_TTW2:
+       case FSC_SEA_TTW3:
+       case FSC_SECC:
+       case FSC_SECC_TTW0:
+       case FSC_SECC_TTW1:
+       case FSC_SECC_TTW2:
+       case FSC_SECC_TTW3:
+               return true;
+       default:
+               return false;
+       }
+}
+
 static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
 {
        u32 esr = kvm_vcpu_get_hsr(vcpu);
index e2b7e4f9cc3180d7a1059cb4983c3739ca4be19c..0e2ea1c785427849b68435eb1c188e8b7d65eb64 100644 (file)
 #include <linux/pci-ecam.h>
 #include <linux/slab.h>
 
-/*
- * Called after each bus is probed, but before its children are examined
- */
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-       /* nothing to do, expected to be removed in the future */
-}
-
-/*
- * We don't have to worry about legacy ISA devices, so nothing to do here
- */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-
 #ifdef CONFIG_ACPI
 /*
  * Try to assign the IRQ number when probing a new device
index 17d8a1677a0b34baf4356bf09b0a809cf0a8e58d..7debb74843a053bfdec33cb69326f3f3d0968297 100644 (file)
@@ -84,7 +84,7 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
        if (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WFx_ISS_WFE) {
                trace_kvm_wfx_arm64(*vcpu_pc(vcpu), true);
                vcpu->stat.wfe_exit_stat++;
-               kvm_vcpu_on_spin(vcpu);
+               kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu));
        } else {
                trace_kvm_wfx_arm64(*vcpu_pc(vcpu), false);
                vcpu->stat.wfi_exit_stat++;
index 116786d2e8e8fdbe7c2dfc4056b87918e4bf25bf..c77d508b74620e0d5c5868a542346efff9f70ab9 100644 (file)
@@ -208,29 +208,12 @@ static void vgic_v3_access_apr_reg(struct kvm_vcpu *vcpu,
 static bool access_gic_aprn(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
                            const struct sys_reg_desc *r, u8 apr)
 {
-       struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
        u8 idx = r->Op2 & 3;
 
-       /*
-        * num_pri_bits are initialized with HW supported values.
-        * We can rely safely on num_pri_bits even if VM has not
-        * restored ICC_CTLR_EL1 before restoring APnR registers.
-        */
-       switch (vgic_v3_cpu->num_pri_bits) {
-       case 7:
-               vgic_v3_access_apr_reg(vcpu, p, apr, idx);
-               break;
-       case 6:
-               if (idx > 1)
-                       goto err;
-               vgic_v3_access_apr_reg(vcpu, p, apr, idx);
-               break;
-       default:
-               if (idx > 0)
-                       goto err;
-               vgic_v3_access_apr_reg(vcpu, p, apr, idx);
-       }
+       if (idx > vgic_v3_max_apr_idx(vcpu))
+               goto err;
 
+       vgic_v3_access_apr_reg(vcpu, p, apr, idx);
        return true;
 err:
        if (!p->is_write)
index 394c2a73d5e25bb6cf748a37ddeeb62aa5fed5c2..5cc622c0225e0497406bdb7227e7638a05835062 100644 (file)
@@ -2,10 +2,6 @@
 #include <linux/kernel.h>
 #include <hwregs/intr_vect.h>
 
-void pcibios_fixup_bus(struct pci_bus *b)
-{
-}
-
 void pcibios_set_master(struct pci_dev *dev)
 {
        u8 lat;
index 4068bde623dc3dd40c1dc81ccc021d6fdc6303a2..f5ec736100ee6a6a036b6b5b3fa024125aa43154 100644 (file)
@@ -411,13 +411,6 @@ pcibios_disable_device (struct pci_dev *dev)
                acpi_pci_irq_disable(dev);
 }
 
-resource_size_t
-pcibios_align_resource (void *data, const struct resource *res,
-                       resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-
 /**
  * ia64_pci_get_legacy_mem - generic legacy mem routine
  * @bus: bus to get legacy memory base address for
index 6a640be485684f00497a63ee9630bd77df9dbe4a..3097fa2ca746729d842a5dbb8d98ea2810afb78d 100644 (file)
@@ -243,6 +243,13 @@ static struct resource mcf_pci_io = {
        .flags  = IORESOURCE_IO,
 };
 
+static struct resource busn_resource = {
+       .name   = "PCI busn",
+       .start  = 0,
+       .end    = 255,
+       .flags  = IORESOURCE_BUS,
+};
+
 /*
  * Interrupt mapping and setting.
  */
@@ -258,6 +265,13 @@ static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 
 static int __init mcf_pci_init(void)
 {
+       struct pci_host_bridge *bridge;
+       int ret;
+
+       bridge = pci_alloc_host_bridge(0);
+       if (!bridge)
+               return -ENOMEM;
+
        pr_info("ColdFire: PCI bus initialization...\n");
 
        /* Reset the external PCI bus */
@@ -312,14 +326,28 @@ static int __init mcf_pci_init(void)
        set_current_state(TASK_UNINTERRUPTIBLE);
        schedule_timeout(msecs_to_jiffies(200));
 
-       rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL);
-       if (!rootbus)
-               return -ENODEV;
+
+       pci_add_resource(&bridge->windows, &ioport_resource);
+       pci_add_resource(&bridge->windows, &iomem_resource);
+       pci_add_resource(&bridge->windows, &busn_resource);
+       bridge->dev.parent = NULL;
+       bridge->sysdata = NULL;
+       bridge->busnr = 0;
+       bridge->ops = &mcf_pci_ops;
+       bridge->swizzle_irq = pci_common_swizzle;
+       bridge->map_irq = mcf_pci_map_irq;
+
+       ret = pci_scan_root_bus_bridge(bridge);
+       if (ret) {
+               pci_free_host_bridge(bridge);
+               return ret;
+       }
+
+       rootbus = bridge->bus;
 
        rootbus->resource[0] = &mcf_pci_io;
        rootbus->resource[1] = &mcf_pci_mem;
 
-       pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq);
        pci_bus_size_bridges(rootbus);
        pci_bus_assign_resources(rootbus);
        pci_bus_add_devices(rootbus);
index efd4983cb6972a2b774950617141b9ace491230f..114b93488193283e4f1801b59d3a4fdf50704ab9 100644 (file)
@@ -81,9 +81,6 @@ extern pgprot_t       pci_phys_mem_access_prot(struct file *file,
 
 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 
-extern void pcibios_setup_bus_devices(struct pci_bus *bus);
-extern void pcibios_setup_bus_self(struct pci_bus *bus);
-
 /* This part of code was originally in xilinx-pci.h */
 #ifdef CONFIG_PCI_XILINX
 extern void __init xilinx_pci_init(void);
index 180f4755ca66a64a703cd8a3f7f1457f812faa5b..ae79e8638d50ba18410bfeb0cdcc227b5b481dc4 100644 (file)
@@ -678,144 +678,6 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
 
-/* This function tries to figure out if a bridge resource has been initialized
- * by the firmware or not. It doesn't have to be absolutely bullet proof, but
- * things go more smoothly when it gets it right. It should covers cases such
- * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
- */
-static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
-                                                struct resource *res)
-{
-       struct pci_controller *hose = pci_bus_to_host(bus);
-       struct pci_dev *dev = bus->self;
-       resource_size_t offset;
-       u16 command;
-       int i;
-
-       /* Job is a bit different between memory and IO */
-       if (res->flags & IORESOURCE_MEM) {
-               /* If the BAR is non-0 (res != pci_mem_offset) then it's
-                * probably been initialized by somebody
-                */
-               if (res->start != hose->pci_mem_offset)
-                       return 0;
-
-               /* The BAR is 0, let's check if memory decoding is enabled on
-                * the bridge. If not, we consider it unassigned
-                */
-               pci_read_config_word(dev, PCI_COMMAND, &command);
-               if ((command & PCI_COMMAND_MEMORY) == 0)
-                       return 1;
-
-               /* Memory decoding is enabled and the BAR is 0. If any of
-                * the bridge resources covers that starting address (0 then
-                * it's good enough for us for memory
-                */
-               for (i = 0; i < 3; i++) {
-                       if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
-                          hose->mem_resources[i].start == hose->pci_mem_offset)
-                               return 0;
-               }
-
-               /* Well, it starts at 0 and we know it will collide so we may as
-                * well consider it as unassigned. That covers the Apple case.
-                */
-               return 1;
-       } else {
-               /* If the BAR is non-0, then we consider it assigned */
-               offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-               if (((res->start - offset) & 0xfffffffful) != 0)
-                       return 0;
-
-               /* Here, we are a bit different than memory as typically IO
-                * space starting at low addresses -is- valid. What we do
-                * instead if that we consider as unassigned anything that
-                * doesn't have IO enabled in the PCI command register,
-                * and that's it.
-                */
-               pci_read_config_word(dev, PCI_COMMAND, &command);
-               if (command & PCI_COMMAND_IO)
-                       return 0;
-
-               /* It's starting at 0 and IO is disabled in the bridge, consider
-                * it unassigned
-                */
-               return 1;
-       }
-}
-
-/* Fixup resources of a PCI<->PCI bridge */
-static void pcibios_fixup_bridge(struct pci_bus *bus)
-{
-       struct resource *res;
-       int i;
-
-       struct pci_dev *dev = bus->self;
-
-       pci_bus_for_each_resource(bus, res, i) {
-               if (!res)
-                       continue;
-               if (!res->flags)
-                       continue;
-               if (i >= 3 && bus->self->transparent)
-                       continue;
-
-               pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
-                        pci_name(dev), i,
-                        (unsigned long long)res->start,
-                        (unsigned long long)res->end,
-                        (unsigned int)res->flags);
-
-               /* Try to detect uninitialized P2P bridge resources,
-                * and clear them out so they get re-assigned later
-                */
-               if (pcibios_uninitialized_bridge_resource(bus, res)) {
-                       res->flags = 0;
-                       pr_debug("PCI:%s            (unassigned)\n",
-                                                               pci_name(dev));
-               } else {
-                       pr_debug("PCI:%s            %016llx-%016llx\n",
-                                pci_name(dev),
-                                (unsigned long long)res->start,
-                                (unsigned long long)res->end);
-               }
-       }
-}
-
-void pcibios_setup_bus_self(struct pci_bus *bus)
-{
-       /* Fix up the bus resources for P2P bridges */
-       if (bus->self != NULL)
-               pcibios_fixup_bridge(bus);
-}
-
-void pcibios_setup_bus_devices(struct pci_bus *bus)
-{
-       struct pci_dev *dev;
-
-       pr_debug("PCI: Fixup bus devices %d (%s)\n",
-                bus->number, bus->self ? pci_name(bus->self) : "PHB");
-
-       list_for_each_entry(dev, &bus->devices, bus_list) {
-               /* Setup OF node pointer in archdata */
-               dev->dev.of_node = pci_device_to_OF_node(dev);
-
-               /* Fixup NUMA node as it may not be setup yet by the generic
-                * code and is needed by the DMA init
-                */
-               set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
-
-               /* Read default IRQs and fixup if necessary */
-               dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
-       }
-}
-
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-       /* nothing to do */
-}
-EXPORT_SYMBOL(pcibios_fixup_bus);
-
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
@@ -829,13 +691,6 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-EXPORT_SYMBOL(pcibios_align_resource);
-
 int pcibios_add_device(struct pci_dev *dev)
 {
        dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
index d4b2ad18eef2023d23701b0dd5a320d2370fee5d..bce2a6431430366ee626ddc4f6282665caeb7f06 100644 (file)
@@ -98,6 +98,11 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
        return !!(vcpu->arch.pending_exceptions);
 }
 
+bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
+{
+       return false;
+}
+
 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 {
        return 1;
index 174575a9a112dcb73634e31b21040df3ad6ad470..fc7726088103c7d48fbc556eab168ce8b53eadc3 100644 (file)
@@ -78,6 +78,12 @@ static void pcibios_scanbus(struct pci_controller *hose)
        static int need_domain_info;
        LIST_HEAD(resources);
        struct pci_bus *bus;
+       struct pci_host_bridge *bridge;
+       int ret;
+
+       bridge = pci_alloc_host_bridge(0);
+       if (!bridge)
+               return;
 
        if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
                next_busno = (*hose->get_busno)();
@@ -87,18 +93,24 @@ static void pcibios_scanbus(struct pci_controller *hose)
        pci_add_resource_offset(&resources,
                                hose->io_resource, hose->io_offset);
        pci_add_resource(&resources, hose->busn_resource);
-       bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
-                               &resources);
-       hose->bus = bus;
+       list_splice_init(&resources, &bridge->windows);
+       bridge->dev.parent = NULL;
+       bridge->sysdata = hose;
+       bridge->busnr = next_busno;
+       bridge->ops = hose->pci_ops;
+       bridge->swizzle_irq = pci_common_swizzle;
+       bridge->map_irq = pcibios_map_irq;
+       ret = pci_scan_root_bus_bridge(bridge);
+       if (ret) {
+               pci_free_host_bridge(bridge);
+               return;
+       }
+
+       hose->bus = bus = bridge->bus;
 
        need_domain_info = need_domain_info || pci_domain_nr(bus);
        set_pci_need_domain_info(hose, need_domain_info);
 
-       if (!bus) {
-               pci_free_resource_list(&resources);
-               return;
-       }
-
        next_busno = bus->busn_res.end + 1;
        /* Don't allow 8-bit bus number overflow inside the hose -
           reserve some space for bridges. */
@@ -224,8 +236,6 @@ static int __init pcibios_init(void)
        list_for_each_entry(hose, &controllers, list)
                pcibios_scanbus(hose);
 
-       pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
-
        pci_initialized = 1;
 
        return 0;
index f28d21c69f79d90a839cfd09929639b63f90ac14..508275bb05d51b2908d7549acb71bc0978e901c8 100644 (file)
 #define HPTE_R_C               ASM_CONST(0x0000000000000080)
 #define HPTE_R_R               ASM_CONST(0x0000000000000100)
 #define HPTE_R_KEY_LO          ASM_CONST(0x0000000000000e00)
+#define HPTE_R_KEY             (HPTE_R_KEY_LO | HPTE_R_KEY_HI)
 
 #define HPTE_V_1TB_SEG         ASM_CONST(0x4000000000000000)
 #define HPTE_V_VRMA_MASK       ASM_CONST(0x4001ffffff000000)
index 67075e065ef2d39a69763b47ce34660226be440b..7c62967d672caa818d12c26620520603fb3c49c7 100644 (file)
@@ -1941,6 +1941,7 @@ int kvm_vm_ioctl_get_htab_fd(struct kvm *kvm, struct kvm_get_htab_fd *ghf)
        rwflag = (ghf->flags & KVM_GET_HTAB_WRITE) ? O_WRONLY : O_RDONLY;
        ret = anon_inode_getfd("kvm-htab", &kvm_htab_fops, ctx, rwflag | O_CLOEXEC);
        if (ret < 0) {
+               kfree(ctx);
                kvm_put_kvm(kvm);
                return ret;
        }
index 53766e2bc029e25efc87270f6983e3b7975be31d..8f2da8bba737b066488a5c0b3909a02ede239ba6 100644 (file)
@@ -265,8 +265,11 @@ static int kvm_spapr_tce_release(struct inode *inode, struct file *filp)
 {
        struct kvmppc_spapr_tce_table *stt = filp->private_data;
        struct kvmppc_spapr_tce_iommu_table *stit, *tmp;
+       struct kvm *kvm = stt->kvm;
 
+       mutex_lock(&kvm->lock);
        list_del_rcu(&stt->list);
+       mutex_unlock(&kvm->lock);
 
        list_for_each_entry_safe(stit, tmp, &stt->iommu_tables, next) {
                WARN_ON(!kref_read(&stit->kref));
@@ -298,7 +301,6 @@ long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
        unsigned long npages, size;
        int ret = -ENOMEM;
        int i;
-       int fd = -1;
 
        if (!args->size)
                return -EINVAL;
@@ -328,11 +330,6 @@ long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
                        goto fail;
        }
 
-       ret = fd = anon_inode_getfd("kvm-spapr-tce", &kvm_spapr_tce_fops,
-                                   stt, O_RDWR | O_CLOEXEC);
-       if (ret < 0)
-               goto fail;
-
        mutex_lock(&kvm->lock);
 
        /* Check this LIOBN hasn't been previously allocated */
@@ -344,17 +341,19 @@ long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
                }
        }
 
-       if (!ret) {
+       if (!ret)
+               ret = anon_inode_getfd("kvm-spapr-tce", &kvm_spapr_tce_fops,
+                                      stt, O_RDWR | O_CLOEXEC);
+
+       if (ret >= 0) {
                list_add_rcu(&stt->list, &kvm->arch.spapr_tce_tables);
                kvm_get_kvm(kvm);
        }
 
        mutex_unlock(&kvm->lock);
 
-       if (!ret)
-               return fd;
-
-       put_unused_fd(fd);
+       if (ret >= 0)
+               return ret;
 
  fail:
        for (i = 0; i < npages; i++)
index ebcf97cb5c98be3e5c2141177af7d62b3a9d216e..18e974a34fced58328ecb062fee539279f3df7cd 100644 (file)
@@ -485,7 +485,13 @@ static unsigned long do_h_register_vpa(struct kvm_vcpu *vcpu,
 
        switch (subfunc) {
        case H_VPA_REG_VPA:             /* register VPA */
-               if (len < sizeof(struct lppaca))
+               /*
+                * The size of our lppaca is 1kB because of the way we align
+                * it for the guest to avoid crossing a 4kB boundary. We only
+                * use 640 bytes of the structure though, so we should accept
+                * clients that set a size of 640.
+                */
+               if (len < 640)
                        break;
                vpap = &tvcpu->arch.vpa;
                err = 0;
@@ -3336,6 +3342,14 @@ static int kvm_vm_ioctl_get_smmu_info_hv(struct kvm *kvm,
        if (radix_enabled())
                return -EINVAL;
 
+       /*
+        * POWER7, POWER8 and POWER9 all support 32 storage keys for data.
+        * POWER7 doesn't support keys for instruction accesses,
+        * POWER8 and POWER9 do.
+        */
+       info->data_keys = 32;
+       info->instr_keys = cpu_has_feature(CPU_FTR_ARCH_207S) ? 32 : 0;
+
        info->flags = KVM_PPC_PAGE_SIZES_REAL;
        if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
                info->flags |= KVM_PPC_1T_SEGMENTS;
index fedb0139524c838008c77aeea3910a3ec11679db..4efe364f11881b573acb1c18356be40bd34a553a 100644 (file)
@@ -269,7 +269,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
        if (!realmode)
                local_irq_restore(irq_flags);
 
-       ptel &= ~(HPTE_R_PP0 - psize);
+       ptel &= HPTE_R_KEY | HPTE_R_PP0 | (psize-1);
        ptel |= pa;
 
        if (pa)
index 2259b6cde119da459bdf94d12ecefe94b5d91100..663a4a861e7f3600903c61df65240fe32e58e5d3 100644 (file)
@@ -982,7 +982,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
 #ifdef CONFIG_KVM_XICS
        /* We are entering the guest on that thread, push VCPU to XIVE */
        ld      r10, HSTATE_XIVE_TIMA_PHYS(r13)
-       cmpldi  cr0, r10, r0
+       cmpldi  cr0, r10, 0
        beq     no_xive
        ld      r11, VCPU_XIVE_SAVED_STATE(r4)
        li      r9, TM_QW1_OS
@@ -1286,7 +1286,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
        cmpwi   r12,BOOK3S_INTERRUPT_HV_DECREMENTER
        bne     2f
        mfspr   r3,SPRN_HDEC
-       cmpwi   r3,0
+       EXTEND_HDEC(r3)
+       cmpdi   r3,0
        mr      r4,r9
        bge     fast_guest_return
 2:
index 32fdab57d604d02eb16886818b0631b6612e3e61..f9f6468f41712549666771fa730c24bdf6673684 100644 (file)
@@ -455,16 +455,20 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_e500(struct kvm *kvm,
        if (err)
                goto free_vcpu;
 
-       if (kvmppc_e500_id_table_alloc(vcpu_e500) == NULL)
+       if (kvmppc_e500_id_table_alloc(vcpu_e500) == NULL) {
+               err = -ENOMEM;
                goto uninit_vcpu;
+       }
 
        err = kvmppc_e500_tlb_init(vcpu_e500);
        if (err)
                goto uninit_id;
 
        vcpu->arch.shared = (void*)__get_free_page(GFP_KERNEL|__GFP_ZERO);
-       if (!vcpu->arch.shared)
+       if (!vcpu->arch.shared) {
+               err = -ENOMEM;
                goto uninit_tlb;
+       }
 
        return vcpu;
 
index f48a0c22e8f9024e87965df7b0821596d43c926a..d0b6b5788afcff7b15f63fb80f9d2c0c3d656d3b 100644 (file)
@@ -331,8 +331,10 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_e500mc(struct kvm *kvm,
                goto uninit_vcpu;
 
        vcpu->arch.shared = (void *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
-       if (!vcpu->arch.shared)
+       if (!vcpu->arch.shared) {
+               err = -ENOMEM;
                goto uninit_tlb;
+       }
 
        return vcpu;
 
index 1a75c0b5f4ca8fba049f572e829d46c0cd40329d..3480faaf1ef886118ba1ee26389ea25c4c3d8a69 100644 (file)
@@ -58,6 +58,11 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
        return !!(v->arch.pending_exceptions) || kvm_request_pending(v);
 }
 
+bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
+{
+       return false;
+}
+
 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 {
        return 1;
index a409d59919344a277fac0858c2bd12ece1bd83c9..51375e766e905a955a4df21fa185c669bfaa9544 100644 (file)
@@ -226,7 +226,9 @@ struct kvm_s390_sie_block {
 #define ECB3_RI  0x01
        __u8    ecb3;                   /* 0x0063 */
        __u32   scaol;                  /* 0x0064 */
-       __u8    reserved68[4];          /* 0x0068 */
+       __u8    reserved68;             /* 0x0068 */
+       __u8    epdx;                   /* 0x0069 */
+       __u8    reserved6a[2];          /* 0x006a */
        __u32   todpr;                  /* 0x006c */
        __u8    reserved70[16];         /* 0x0070 */
        __u64   mso;                    /* 0x0080 */
@@ -265,6 +267,7 @@ struct kvm_s390_sie_block {
        __u64   cbrlo;                  /* 0x01b8 */
        __u8    reserved1c0[8];         /* 0x01c0 */
 #define ECD_HOSTREGMGMT        0x20000000
+#define ECD_MEF                0x08000000
        __u32   ecd;                    /* 0x01c8 */
        __u8    reserved1cc[18];        /* 0x01cc */
        __u64   pp;                     /* 0x01de */
@@ -739,6 +742,7 @@ struct kvm_arch{
        struct kvm_s390_cpu_model model;
        struct kvm_s390_crypto crypto;
        struct kvm_s390_vsie vsie;
+       u8 epdx;
        u64 epoch;
        struct kvm_s390_migration_state *migration_state;
        /* subset of available cpu features enabled by user space */
index ca21b28a7b1710a3176af60ac466df71b5788645..22b0f49e87c1a74ec726be3440e100e80efc645f 100644 (file)
@@ -15,6 +15,6 @@
 #define ESSA_SET_STABLE_IF_RESIDENT    6
 #define ESSA_SET_STABLE_NODAT          7
 
-#define ESSA_MAX       ESSA_SET_STABLE_IF_RESIDENT
+#define ESSA_MAX       ESSA_SET_STABLE_NODAT
 
 #endif
index 69d09c39bbcd00858121ebf9f6bb1f7a57ff20e1..cd7359e23d869465d1cb70b637c64c85283e37ac 100644 (file)
@@ -88,6 +88,12 @@ struct kvm_s390_io_adapter_req {
 /* kvm attributes for KVM_S390_VM_TOD */
 #define KVM_S390_VM_TOD_LOW            0
 #define KVM_S390_VM_TOD_HIGH           1
+#define KVM_S390_VM_TOD_EXT            2
+
+struct kvm_s390_vm_tod_clock {
+       __u8  epoch_idx;
+       __u64 tod;
+};
 
 /* kvm attributes for KVM_S390_VM_CPU_MODEL */
 /* processor related attributes are r/w */
index e4d36094aceb53eed6a542c7c1f145870e9595f3..d93a2c0474bf67e45698882ecb5f36f0d8688a7d 100644 (file)
@@ -150,7 +150,7 @@ static int __diag_time_slice_end(struct kvm_vcpu *vcpu)
 {
        VCPU_EVENT(vcpu, 5, "%s", "diag time slice end");
        vcpu->stat.diagnose_44++;
-       kvm_vcpu_on_spin(vcpu);
+       kvm_vcpu_on_spin(vcpu, true);
        return 0;
 }
 
index c2e0ddc1356e551ebd8c466b73956e2574b67436..bcbd86621d018085d036f43d815ae1c97791951c 100644 (file)
@@ -308,7 +308,7 @@ static inline int in_addr_range(u64 addr, u64 a, u64 b)
                return (addr >= a) && (addr <= b);
        else
                /* "overflowing" interval */
-               return (addr <= a) && (addr >= b);
+               return (addr >= a) || (addr <= b);
 }
 
 #define end_of_range(bp_info) (bp_info->addr + bp_info->len - 1)
index a619ddae610da2c0fabaf66a9a123d1572b51f9c..a832ad031cee78f5cc6fe17b93fb315e17fdd50a 100644 (file)
@@ -2479,6 +2479,7 @@ void kvm_s390_reinject_machine_check(struct kvm_vcpu *vcpu,
        struct kvm_s390_mchk_info *mchk;
        union mci mci;
        __u64 cr14 = 0;         /* upper bits are not used */
+       int rc;
 
        mci.val = mcck_info->mcic;
        if (mci.sr)
@@ -2496,12 +2497,13 @@ void kvm_s390_reinject_machine_check(struct kvm_vcpu *vcpu,
        if (mci.ck) {
                /* Inject the floating machine check */
                inti.type = KVM_S390_MCHK;
-               WARN_ON_ONCE(__inject_vm(vcpu->kvm, &inti));
+               rc = __inject_vm(vcpu->kvm, &inti);
        } else {
                /* Inject the machine check to specified vcpu */
                irq.type = KVM_S390_MCHK;
-               WARN_ON_ONCE(kvm_s390_inject_vcpu(vcpu, &irq));
+               rc = kvm_s390_inject_vcpu(vcpu, &irq);
        }
+       WARN_ON_ONCE(rc);
 }
 
 int kvm_set_routing_entry(struct kvm *kvm,
index af09d3437631d348dca2f1a6699c34ed49c624ed..40d0a1a97889b04f5e0bf1beb9d509721e1d5ff8 100644 (file)
@@ -130,6 +130,12 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
        { NULL }
 };
 
+struct kvm_s390_tod_clock_ext {
+       __u8 epoch_idx;
+       __u64 tod;
+       __u8 reserved[7];
+} __packed;
+
 /* allow nested virtualization in KVM (if enabled by user space) */
 static int nested;
 module_param(nested, int, S_IRUGO);
@@ -874,6 +880,26 @@ static int kvm_s390_vm_get_migration(struct kvm *kvm,
        return 0;
 }
 
+static int kvm_s390_set_tod_ext(struct kvm *kvm, struct kvm_device_attr *attr)
+{
+       struct kvm_s390_vm_tod_clock gtod;
+
+       if (copy_from_user(&gtod, (void __user *)attr->addr, sizeof(gtod)))
+               return -EFAULT;
+
+       if (test_kvm_facility(kvm, 139))
+               kvm_s390_set_tod_clock_ext(kvm, &gtod);
+       else if (gtod.epoch_idx == 0)
+               kvm_s390_set_tod_clock(kvm, gtod.tod);
+       else
+               return -EINVAL;
+
+       VM_EVENT(kvm, 3, "SET: TOD extension: 0x%x, TOD base: 0x%llx",
+               gtod.epoch_idx, gtod.tod);
+
+       return 0;
+}
+
 static int kvm_s390_set_tod_high(struct kvm *kvm, struct kvm_device_attr *attr)
 {
        u8 gtod_high;
@@ -909,6 +935,9 @@ static int kvm_s390_set_tod(struct kvm *kvm, struct kvm_device_attr *attr)
                return -EINVAL;
 
        switch (attr->attr) {
+       case KVM_S390_VM_TOD_EXT:
+               ret = kvm_s390_set_tod_ext(kvm, attr);
+               break;
        case KVM_S390_VM_TOD_HIGH:
                ret = kvm_s390_set_tod_high(kvm, attr);
                break;
@@ -922,6 +951,43 @@ static int kvm_s390_set_tod(struct kvm *kvm, struct kvm_device_attr *attr)
        return ret;
 }
 
+static void kvm_s390_get_tod_clock_ext(struct kvm *kvm,
+                                       struct kvm_s390_vm_tod_clock *gtod)
+{
+       struct kvm_s390_tod_clock_ext htod;
+
+       preempt_disable();
+
+       get_tod_clock_ext((char *)&htod);
+
+       gtod->tod = htod.tod + kvm->arch.epoch;
+       gtod->epoch_idx = htod.epoch_idx + kvm->arch.epdx;
+
+       if (gtod->tod < htod.tod)
+               gtod->epoch_idx += 1;
+
+       preempt_enable();
+}
+
+static int kvm_s390_get_tod_ext(struct kvm *kvm, struct kvm_device_attr *attr)
+{
+       struct kvm_s390_vm_tod_clock gtod;
+
+       memset(&gtod, 0, sizeof(gtod));
+
+       if (test_kvm_facility(kvm, 139))
+               kvm_s390_get_tod_clock_ext(kvm, &gtod);
+       else
+               gtod.tod = kvm_s390_get_tod_clock_fast(kvm);
+
+       if (copy_to_user((void __user *)attr->addr, &gtod, sizeof(gtod)))
+               return -EFAULT;
+
+       VM_EVENT(kvm, 3, "QUERY: TOD extension: 0x%x, TOD base: 0x%llx",
+               gtod.epoch_idx, gtod.tod);
+       return 0;
+}
+
 static int kvm_s390_get_tod_high(struct kvm *kvm, struct kvm_device_attr *attr)
 {
        u8 gtod_high = 0;
@@ -954,6 +1020,9 @@ static int kvm_s390_get_tod(struct kvm *kvm, struct kvm_device_attr *attr)
                return -EINVAL;
 
        switch (attr->attr) {
+       case KVM_S390_VM_TOD_EXT:
+               ret = kvm_s390_get_tod_ext(kvm, attr);
+               break;
        case KVM_S390_VM_TOD_HIGH:
                ret = kvm_s390_get_tod_high(kvm, attr);
                break;
@@ -1505,7 +1574,7 @@ static int kvm_s390_get_cmma_bits(struct kvm *kvm,
                if (r < 0)
                        pgstev = 0;
                /* save the value */
-               res[i++] = (pgstev >> 24) & 0x3;
+               res[i++] = (pgstev >> 24) & 0x43;
                /*
                 * if the next bit is too far away, stop.
                 * if we reached the previous "next", find the next one
@@ -1583,7 +1652,7 @@ static int kvm_s390_set_cmma_bits(struct kvm *kvm,
 
                pgstev = bits[i];
                pgstev = pgstev << 24;
-               mask &= _PGSTE_GPS_USAGE_MASK;
+               mask &= _PGSTE_GPS_USAGE_MASK | _PGSTE_GPS_NODAT;
                set_pgste_bits(kvm->mm, hva, mask, pgstev);
        }
        srcu_read_unlock(&kvm->srcu, srcu_idx);
@@ -1858,8 +1927,16 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
        memcpy(kvm->arch.model.fac_list, kvm->arch.model.fac_mask,
               S390_ARCH_FAC_LIST_SIZE_BYTE);
 
+       /* we are always in czam mode - even on pre z14 machines */
+       set_kvm_facility(kvm->arch.model.fac_mask, 138);
+       set_kvm_facility(kvm->arch.model.fac_list, 138);
+       /* we emulate STHYI in kvm */
        set_kvm_facility(kvm->arch.model.fac_mask, 74);
        set_kvm_facility(kvm->arch.model.fac_list, 74);
+       if (MACHINE_HAS_TLB_GUEST) {
+               set_kvm_facility(kvm->arch.model.fac_mask, 147);
+               set_kvm_facility(kvm->arch.model.fac_list, 147);
+       }
 
        kvm->arch.model.cpuid = kvm_s390_get_initial_cpuid();
        kvm->arch.model.ibc = sclp.ibc & 0x0fff;
@@ -2369,6 +2446,9 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
                vcpu->arch.sie_block->eca |= ECA_VX;
                vcpu->arch.sie_block->ecd |= ECD_HOSTREGMGMT;
        }
+       if (test_kvm_facility(vcpu->kvm, 139))
+               vcpu->arch.sie_block->ecd |= ECD_MEF;
+
        vcpu->arch.sie_block->sdnxo = ((unsigned long) &vcpu->run->s.regs.sdnx)
                                        | SDNXC;
        vcpu->arch.sie_block->riccbd = (unsigned long) &vcpu->run->s.regs.riccb;
@@ -2447,6 +2527,11 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
        return kvm_s390_vcpu_has_irq(vcpu, 0);
 }
 
+bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
+{
+       return !(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE);
+}
+
 void kvm_s390_vcpu_block(struct kvm_vcpu *vcpu)
 {
        atomic_or(PROG_BLOCK_SIE, &vcpu->arch.sie_block->prog20);
@@ -2855,6 +2940,35 @@ retry:
        return 0;
 }
 
+void kvm_s390_set_tod_clock_ext(struct kvm *kvm,
+                                const struct kvm_s390_vm_tod_clock *gtod)
+{
+       struct kvm_vcpu *vcpu;
+       struct kvm_s390_tod_clock_ext htod;
+       int i;
+
+       mutex_lock(&kvm->lock);
+       preempt_disable();
+
+       get_tod_clock_ext((char *)&htod);
+
+       kvm->arch.epoch = gtod->tod - htod.tod;
+       kvm->arch.epdx = gtod->epoch_idx - htod.epoch_idx;
+
+       if (kvm->arch.epoch > gtod->tod)
+               kvm->arch.epdx -= 1;
+
+       kvm_s390_vcpu_block_all(kvm);
+       kvm_for_each_vcpu(i, vcpu, kvm) {
+               vcpu->arch.sie_block->epoch = kvm->arch.epoch;
+               vcpu->arch.sie_block->epdx  = kvm->arch.epdx;
+       }
+
+       kvm_s390_vcpu_unblock_all(kvm);
+       preempt_enable();
+       mutex_unlock(&kvm->lock);
+}
+
 void kvm_s390_set_tod_clock(struct kvm *kvm, u64 tod)
 {
        struct kvm_vcpu *vcpu;
index 6fedc8bc7a37393bd1fa50be94d22d53f431a076..9f8fdd7b231134da9b2d2d4d8971a05546b33c6b 100644 (file)
@@ -272,6 +272,8 @@ int kvm_s390_handle_sigp_pei(struct kvm_vcpu *vcpu);
 int handle_sthyi(struct kvm_vcpu *vcpu);
 
 /* implemented in kvm-s390.c */
+void kvm_s390_set_tod_clock_ext(struct kvm *kvm,
+                                const struct kvm_s390_vm_tod_clock *gtod);
 void kvm_s390_set_tod_clock(struct kvm *kvm, u64 tod);
 long kvm_arch_fault_in_page(struct kvm_vcpu *vcpu, gpa_t gpa, int writable);
 int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr);
index 785ad028bde602de4699d987d1a4c7552211ba39..c954ac49eee47158ac27bd1d16ba9dbcab7e25a3 100644 (file)
@@ -988,6 +988,8 @@ static inline int do_essa(struct kvm_vcpu *vcpu, const int orc)
                if (pgstev & _PGSTE_GPS_ZERO)
                        res |= 1;
        }
+       if (pgstev & _PGSTE_GPS_NODAT)
+               res |= 0x20;
        vcpu->run->s.regs.gprs[r1] = res;
        /*
         * It is possible that all the normal 511 slots were full, in which case
@@ -1027,7 +1029,9 @@ static int handle_essa(struct kvm_vcpu *vcpu)
                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
        /* Check for invalid operation request code */
        orc = (vcpu->arch.sie_block->ipb & 0xf0000000) >> 28;
-       if (orc > ESSA_MAX)
+       /* ORCs 0-6 are always valid */
+       if (orc > (test_kvm_facility(vcpu->kvm, 147) ? ESSA_SET_STABLE_NODAT
+                                               : ESSA_SET_STABLE_IF_RESIDENT))
                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
        if (likely(!vcpu->kvm->arch.migration_state)) {
index 1a252f5370818e5febbe5d05f96432be93f33488..9d592ef4104b0416029944fed5770a8ea74a47cb 100644 (file)
@@ -155,29 +155,26 @@ static int __sigp_stop_and_store_status(struct kvm_vcpu *vcpu,
        return rc;
 }
 
-static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
+static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter,
+                          u64 *status_reg)
 {
-       int rc;
        unsigned int i;
        struct kvm_vcpu *v;
+       bool all_stopped = true;
 
-       switch (parameter & 0xff) {
-       case 0:
-               rc = SIGP_CC_NOT_OPERATIONAL;
-               break;
-       case 1:
-       case 2:
-               kvm_for_each_vcpu(i, v, vcpu->kvm) {
-                       v->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID;
-                       kvm_clear_async_pf_completion_queue(v);
-               }
-
-               rc = SIGP_CC_ORDER_CODE_ACCEPTED;
-               break;
-       default:
-               rc = -EOPNOTSUPP;
+       kvm_for_each_vcpu(i, v, vcpu->kvm) {
+               if (v == vcpu)
+                       continue;
+               if (!is_vcpu_stopped(v))
+                       all_stopped = false;
        }
-       return rc;
+
+       *status_reg &= 0xffffffff00000000UL;
+
+       /* Reject set arch order, with czam we're always in z/Arch mode. */
+       *status_reg |= (all_stopped ? SIGP_STATUS_INVALID_PARAMETER :
+                                       SIGP_STATUS_INCORRECT_STATE);
+       return SIGP_CC_STATUS_STORED;
 }
 
 static int __sigp_set_prefix(struct kvm_vcpu *vcpu, struct kvm_vcpu *dst_vcpu,
@@ -446,7 +443,8 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
        switch (order_code) {
        case SIGP_SET_ARCHITECTURE:
                vcpu->stat.instruction_sigp_arch++;
-               rc = __sigp_set_arch(vcpu, parameter);
+               rc = __sigp_set_arch(vcpu, parameter,
+                                    &vcpu->run->s.regs.gprs[r1]);
                break;
        default:
                rc = handle_sigp_dst(vcpu, order_code, cpu_addr,
index a2e5c24f47a7471a1e7730f654b8ce4599434ef0..395926b8c1ed48f7994210c8ff6c7de7ae43e709 100644 (file)
@@ -436,14 +436,6 @@ int handle_sthyi(struct kvm_vcpu *vcpu)
        if (addr & ~PAGE_MASK)
                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
-       /*
-        * If the page has not yet been faulted in, we want to do that
-        * now and not after all the expensive calculations.
-        */
-       r = write_guest(vcpu, addr, reg2, &cc, 1);
-       if (r)
-               return kvm_s390_inject_prog_cond(vcpu, r);
-
        sctns = (void *)get_zeroed_page(GFP_KERNEL);
        if (!sctns)
                return -ENOMEM;
index ba8203e4d516da2ec13c10d45beb1f1744580243..b18b5652e5c59b84f64f24a89fb2a14033e65e36 100644 (file)
@@ -349,6 +349,9 @@ static int shadow_scb(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
                scb_s->eca |= scb_o->eca & ECA_IB;
        if (test_kvm_cpu_feat(vcpu->kvm, KVM_S390_VM_CPU_FEAT_CEI))
                scb_s->eca |= scb_o->eca & ECA_CEI;
+       /* Epoch Extension */
+       if (test_kvm_facility(vcpu->kvm, 139))
+               scb_s->ecd |= scb_o->ecd & ECD_MEF;
 
        prepare_ibc(vcpu, vsie_page);
        rc = shadow_crycb(vcpu, vsie_page);
@@ -806,8 +809,6 @@ static int do_vsie_run(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
 {
        struct kvm_s390_sie_block *scb_s = &vsie_page->scb_s;
        struct kvm_s390_sie_block *scb_o = vsie_page->scb_o;
-       struct mcck_volatile_info *mcck_info;
-       struct sie_page *sie_page;
        int rc;
 
        handle_last_fault(vcpu, vsie_page);
@@ -831,9 +832,7 @@ static int do_vsie_run(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
 
        if (rc == -EINTR) {
                VCPU_EVENT(vcpu, 3, "%s", "machine check");
-               sie_page = container_of(scb_s, struct sie_page, sie_block);
-               mcck_info = &sie_page->mcck_info;
-               kvm_s390_reinject_machine_check(vcpu, mcck_info);
+               kvm_s390_reinject_machine_check(vcpu, &vsie_page->mcck_info);
                return 0;
        }
 
@@ -919,6 +918,13 @@ static void register_shadow_scb(struct kvm_vcpu *vcpu,
         */
        preempt_disable();
        scb_s->epoch += vcpu->kvm->arch.epoch;
+
+       if (scb_s->ecd & ECD_MEF) {
+               scb_s->epdx += vcpu->kvm->arch.epdx;
+               if (scb_s->epoch < vcpu->kvm->arch.epoch)
+                       scb_s->epdx += 1;
+       }
+
        preempt_enable();
 }
 
index 4198a71b8fddc5d456ab35aecf55c8ea9e405d79..ae677f814bc07a406f7f996a81ed2db65718f5ff 100644 (file)
@@ -919,7 +919,7 @@ int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc,
        case ESSA_GET_STATE:
                break;
        case ESSA_SET_STABLE:
-               pgstev &= ~_PGSTE_GPS_USAGE_MASK;
+               pgstev &= ~(_PGSTE_GPS_USAGE_MASK | _PGSTE_GPS_NODAT);
                pgstev |= _PGSTE_GPS_USAGE_STABLE;
                break;
        case ESSA_SET_UNUSED:
@@ -965,6 +965,10 @@ int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc,
                        pgstev |= _PGSTE_GPS_USAGE_STABLE;
                }
                break;
+       case ESSA_SET_STABLE_NODAT:
+               pgstev &= ~_PGSTE_GPS_USAGE_MASK;
+               pgstev |= _PGSTE_GPS_USAGE_STABLE | _PGSTE_GPS_NODAT;
+               break;
        default:
                /* we should never get here! */
                break;
index 7b30af5da222a947cceb1cf226945884e0682847..ddb9923fb45df18c6b6d19b630acf89a75a6abd2 100644 (file)
@@ -262,10 +262,6 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
        return rc;
 }
 
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-}
-
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                       resource_size_t size,
                                       resource_size_t align)
index 29d72bf8ed2b997e3cca9c8c7733344be1489e76..70dd8f17d0547ebc2c2ee059b0e54834b67c0f79 100644 (file)
@@ -83,6 +83,7 @@ static struct facility_def facility_defs[] = {
                        78, /* enhanced-DAT 2 */
                        130, /* instruction-execution-protection */
                        131, /* enhanced-SOP 2 and side-effect */
+                       139, /* multiple epoch facility */
                        146, /* msa extension 8 */
                        -1  /* END */
                }
index edc2fb7a5bb25540e75cf42b86877b8c16ed8558..32467884d6f796fe8f59f331c3c9e91e2819c5f2 100644 (file)
@@ -5,7 +5,7 @@
 #include <cpu/irq.h>
 #include "pci-sh5.h"
 
-int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        int result = -1;
 
index 1d1c5a227e509e50e865011b7e9912c8db109196..9d597f7ab8ddd09f345826e603c2383fb9bdd44a 100644 (file)
@@ -76,7 +76,7 @@ static void gapspci_fixup_resources(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, gapspci_fixup_resources);
 
-int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        /*
         * The interrupt routing semantics here are quite trivial.
index 57ed3f09d0c2b838d5e0daa372b319ff32fb3565..2c9b58f848dd3457fd4913f56269445409d96fac 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/sh_intc.h>
 #include "pci-sh4.h"
 
-int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
        return evt2irq(0xa20) + slot;
 }
index eaddb56c45c612493e0c996183d092df25efa882..358ac104f08c4ee572f08d9d9b701f04125def57 100644 (file)
 #define PCIMCR_MRSET_OFF       0xBFFFFFFF
 #define PCIMCR_RFSH_OFF                0xFFFFFFFB
 
-static u8 rts7751r2d_irq_tab[] __initdata = {
+static u8 rts7751r2d_irq_tab[] = {
        IRQ_PCI_INTA,
        IRQ_PCI_INTB,
        IRQ_PCI_INTC,
        IRQ_PCI_INTD,
 };
 
-static char lboxre2_irq_tab[] __initdata = {
+static char lboxre2_irq_tab[] = {
        IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
 };
 
-int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
        if (mach_is_lboxre2())
                return lboxre2_irq_tab[slot];
index c0a015ae6ecf718df7a2bfba9ea4fc4edd35bd82..24e96dfbdb229c3992bee3c200229283af24e87c 100644 (file)
@@ -22,7 +22,7 @@
 #define IRQ_INTD       evt2irq(0xa80)
 
 /* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
-static char sdk7780_irq_tab[4][16] __initdata = {
+static char sdk7780_irq_tab[4][16] = {
        /* INTA */
        { IRQ_INTA, IRQ_INTD, IRQ_INTC, IRQ_INTD, -1, -1, -1, -1, -1, -1,
          -1, -1, -1, -1, -1, -1 },
@@ -37,7 +37,7 @@ static char sdk7780_irq_tab[4][16] __initdata = {
          -1, -1, -1 },
 };
 
-int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
        return sdk7780_irq_tab[pin-1][slot];
 }
index 84a88ca9200821c4fbd9b1266967ded716c89d72..1cb8d0ac4fdb5aebf4e1b616422fb3a8db83e463 100644 (file)
@@ -7,7 +7,7 @@
 #include <linux/sh_intc.h>
 #include "pci-sh4.h"
 
-int __init pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
 {
         switch (slot) {
         case 0: return evt2irq(0x3a0);
index 16207bef9f52586dee90548d6c472e318dbc3a68..55ac1ba2c74fefbf597346a40d3ac2c4b718a217 100644 (file)
@@ -4,7 +4,7 @@
 #include <linux/pci.h>
 #include <linux/sh_intc.h>
 
-int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        int irq;
 
index 6e33ba4cd0765254ea0f7c0b7c274c2f3cf92b0d..a931e5928f58ca544b4715dae6da08a4f0017d81 100644 (file)
@@ -19,7 +19,7 @@
 #include <linux/sh_intc.h>
 #include "pci-sh4.h"
 
-int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
        int irq = -1;
 
index bd1addb1b8be4f91c8f25d3bdf3d58346450712b..a9d563e479d5c12b418957f4202dbbcf3fa61023 100644 (file)
@@ -19,7 +19,7 @@
 #include <mach/titan.h>
 #include "pci-sh4.h"
 
-static char titan_irq_tab[] __initdata = {
+static char titan_irq_tab[] = {
        TITAN_IRQ_WAN,
        TITAN_IRQ_LAN,
        TITAN_IRQ_MPCIA,
@@ -27,7 +27,7 @@ static char titan_irq_tab[] __initdata = {
        TITAN_IRQ_USB,
 };
 
-int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
        int irq = titan_irq_tab[slot];
 
index c99ee286b69f126506eebe9814588096cb224a5b..5976a2c8a3e350db0e228b224593f17fb47dc602 100644 (file)
@@ -39,8 +39,12 @@ static void pcibios_scanbus(struct pci_channel *hose)
        LIST_HEAD(resources);
        struct resource *res;
        resource_size_t offset;
-       int i;
-       struct pci_bus *bus;
+       int i, ret;
+       struct pci_host_bridge *bridge;
+
+       bridge = pci_alloc_host_bridge(0);
+       if (!bridge)
+               return;
 
        for (i = 0; i < hose->nr_resources; i++) {
                res = hose->resources + i;
@@ -52,19 +56,26 @@ static void pcibios_scanbus(struct pci_channel *hose)
                pci_add_resource_offset(&resources, res, offset);
        }
 
-       bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
-                               &resources);
-       hose->bus = bus;
+       list_splice_init(&resources, &bridge->windows);
+       bridge->dev.parent = NULL;
+       bridge->sysdata = hose;
+       bridge->busnr = next_busno;
+       bridge->ops = hose->pci_ops;
+       bridge->swizzle_irq = pci_common_swizzle;
+       bridge->map_irq = pcibios_map_platform_irq;
+
+       ret = pci_scan_root_bus_bridge(bridge);
+       if (ret) {
+               pci_free_host_bridge(bridge);
+               return;
+       }
+
+       hose->bus = bridge->bus;
 
        need_domain_info = need_domain_info || hose->index;
        hose->need_domain_info = need_domain_info;
 
-       if (!bus) {
-               pci_free_resource_list(&resources);
-               return;
-       }
-
-       next_busno = bus->busn_res.end + 1;
+       next_busno = hose->bus->busn_res.end + 1;
        /* Don't allow 8-bit bus number overflow inside the hose -
           reserve some space for bridges. */
        if (next_busno > 224) {
@@ -72,9 +83,9 @@ static void pcibios_scanbus(struct pci_channel *hose)
                need_domain_info = 1;
        }
 
-       pci_bus_size_bridges(bus);
-       pci_bus_assign_resources(bus);
-       pci_bus_add_devices(bus);
+       pci_bus_size_bridges(hose->bus);
+       pci_bus_assign_resources(hose->bus);
+       pci_bus_add_devices(hose->bus);
 }
 
 /*
@@ -144,8 +155,6 @@ static int __init pcibios_init(void)
        for (hose = hose_head; hose; hose = hose->next)
                pcibios_scanbus(hose);
 
-       pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
-
        dma_debug_add_bus(&pci_bus_type);
 
        pci_initialized = 1;
@@ -154,14 +163,6 @@ static int __init pcibios_init(void)
 }
 subsys_initcall(pcibios_init);
 
-/*
- *  Called after each bus is probed, but before its children
- *  are examined.
- */
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-}
-
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
index a162a7f86b2e500e1439ea639e233a5cdabbb904..0167a735271942a04580d527c844ce6dd0628673 100644 (file)
@@ -467,7 +467,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
        return 0;
 }
 
-int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
         return evt2irq(0xae0);
 }
index 4371f72ff02500d57c56343a254468375324490c..98c223edac84f47361cce51fa429026f15ed984f 100644 (file)
@@ -25,6 +25,12 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
 {
        LIST_HEAD(resources);
        struct pci_bus *root_bus;
+       struct pci_host_bridge *bridge;
+       int ret;
+
+       bridge = pci_alloc_host_bridge(0);
+       if (!bridge)
+               return;
 
        pci_add_resource_offset(&resources, &info->io_space,
                                info->io_space.start - 0x1000);
@@ -32,15 +38,21 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
        info->busn.flags = IORESOURCE_BUS;
        pci_add_resource(&resources, &info->busn);
 
-       root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
-                                    &resources);
-       if (!root_bus) {
-               pci_free_resource_list(&resources);
+       list_splice_init(&resources, &bridge->windows);
+       bridge->dev.parent = &ofdev->dev;
+       bridge->sysdata = info;
+       bridge->busnr = 0;
+       bridge->ops = info->ops;
+       bridge->swizzle_irq = pci_common_swizzle;
+       bridge->map_irq = info->map_irq;
+
+       ret = pci_scan_root_bus_bridge(bridge);
+       if (ret) {
+               pci_free_host_bridge(bridge);
                return;
        }
 
-       /* Setup IRQs of all devices using custom routines */
-       pci_fixup_irqs(pci_common_swizzle, info->map_irq);
+       root_bus = bridge->bus;
 
        /* Assign devices with resources */
        pci_assign_unassigned_resources();
@@ -94,9 +106,3 @@ void pcibios_fixup_bus(struct pci_bus *pbus)
                }
        }
 }
-
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
index 7eceaa10836f0141472a7b71c445b4a65140a3e6..3f8670c9295115d4186762f89726a9ab7f55442f 100644 (file)
@@ -690,16 +690,6 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
        return bus;
 }
 
-void pcibios_fixup_bus(struct pci_bus *pbus)
-{
-}
-
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-
 int pcibios_enable_device(struct pci_dev *dev, int mask)
 {
        u16 cmd, oldcmd;
index 732af9a9f6ddef510e39da7d6eca5547e210296e..4a133c052af89cc7cbb2118bf16e60a40d428ec4 100644 (file)
@@ -746,12 +746,6 @@ static void watchdog_reset() {
 }
 #endif
 
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                               resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-
 int pcibios_enable_device(struct pci_dev *pdev, int mask)
 {
        return 0;
index bc6656b5708b168f8f26c99b599b0233cf7ba5e2..bbf81579b1f84f7fbbc3738bb14b511a65134f1a 100644 (file)
@@ -66,16 +66,6 @@ static int pci_scan_flags[TILE_NUM_PCIE];
 static struct pci_ops tile_cfg_ops;
 
 
-/*
- * We don't need to worry about the alignment of resources.
- */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                           resource_size_t size, resource_size_t align)
-{
-       return res->start;
-}
-EXPORT_SYMBOL(pcibios_align_resource);
-
 /*
  * Open a FD to the hypervisor PCI device.
  *
@@ -274,6 +264,7 @@ static void fixup_read_and_payload_sizes(void)
  */
 int __init pcibios_init(void)
 {
+       struct pci_host_bridge *bridge;
        int i;
 
        pr_info("PCI: Probing PCI hardware\n");
@@ -306,16 +297,26 @@ int __init pcibios_init(void)
 
                        pci_add_resource(&resources, &ioport_resource);
                        pci_add_resource(&resources, &iomem_resource);
-                       bus = pci_scan_root_bus(NULL, 0, controller->ops,
-                                               controller, &resources);
+
+                       bridge = pci_alloc_host_bridge(0);
+                       if (!bridge)
+                               break;
+
+                       list_splice_init(&resources, &bridge->windows);
+                       bridge->dev.parent = NULL;
+                       bridge->sysdata = controller;
+                       bridge->busnr = 0;
+                       bridge->ops = controller->ops;
+                       bridge->swizzle_irq = pci_common_swizzle;
+                       bridge->map_irq = tile_map_irq;
+
+                       pci_scan_root_bus_bridge(bridge);
+                       bus = bridge->bus;
                        controller->root_bus = bus;
                        controller->last_busno = bus->busn_res.end;
                }
        }
 
-       /* Do machine dependent PCI interrupt routing */
-       pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
-
        /*
         * This comes from the generic Linux PCI driver.
         *
@@ -369,14 +370,6 @@ int __init pcibios_init(void)
 }
 subsys_initcall(pcibios_init);
 
-/*
- * No bus fixups needed.
- */
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-       /* Nothing needs to be done. */
-}
-
 void pcibios_set_master(struct pci_dev *dev)
 {
        /* No special bus mastering setup handling. */
index b554a68eea1bbeb4b65aae2b0b6fcf226ca381ec..9aa238ac7b3582a6894b03295811b60f02874e9e 100644 (file)
@@ -108,15 +108,6 @@ static struct pci_ops tile_cfg_ops;
 /* Mask of CPUs that should receive PCIe interrupts. */
 static struct cpumask intr_cpus_map;
 
-/* We don't need to worry about the alignment of resources. */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
-                                      resource_size_t size,
-                                      resource_size_t align)
-{
-       return res->start;
-}
-EXPORT_SYMBOL(pcibios_align_resource);
-
 /*
  * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
  * For now, we simply send interrupts to non-dataplane CPUs.
@@ -669,6 +660,7 @@ int __init pcibios_init(void)
        resource_size_t offset;
        LIST_HEAD(resources);
        int next_busno;
+       struct pci_host_bridge *bridge;
        int i;
 
        tile_pci_init();
@@ -881,15 +873,25 @@ int __init pcibios_init(void)
                                        controller->mem_offset);
                pci_add_resource(&resources, &controller->io_space);
                controller->first_busno = next_busno;
-     &n