Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Fri, 20 Sep 2019 22:53:02 +0000 (15:53 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Fri, 20 Sep 2019 22:53:02 +0000 (15:53 -0700)
Pull ARM SoC late updates from Arnd Bergmann:
 "This is some material that we picked up into our tree late or that had
  complex inter-depondencies. The fact that there are these
  interdependencies tends to meant that these are often actually the
  most interesting new additions:

   - The new Aspeed AST2600 baseboard management controller is added,
     this is a Cortex-A7 based follow-up to the ARM11 based AST2500 and
     had some dependencies on other device drivers.

   - After many years, support for the MMP2 based OLPC XO-1.75 finally
     makes it into the kernel.

   - The Armada 3720 based Turris Mox open source router platform is a
     late addition and it follows some preparatory work across multiple
     branches.

   - The OMAP2+ platform had some large-scale cleanup involving driver
     changes and DT changes, here we finish it off, dropping a lot of
     the now-unused platform data.

   - The TI K3 platform that got added for 5.3 gains a lot more support
     for individual bits on the SoC, this part just came late for the
     merge window"

[ This pull request itself wasn't actually sent late at all by Arnd, but
  I waited on the branches that it used to be pulled first, so it ends
  up being merged much later than the other ARM SoC pull requests this
  merge window     - Linus ]

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
  ARM: dts: dir685: Drop spi-cpol from the display
  ARM: dts: aspeed: Add AST2600 pinmux nodes
  ARM: dts: aspeed: Add AST2600 and EVB
  ARM: exynos: Enable support for ARM architected timers
  ARM: samsung: Fix system restart on S3C6410
  ARM: dts: mmp2: add OLPC XO 1.75 machine
  ARM: dts: mmp2: rename the USB PHY node
  ARM: dts: mmp2: specify reg-shift for the UARTs
  ARM: dts: mmp2: add camera interfaces
  ARM: dts: mmp2: fix the SPI nodes
  ARM: dts: mmp2: trivial whitespace fix
  arm64: dts: marvell: add DTS for Turris Mox
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-j721e-main: Add hwspinlock node
  arm64: dts: ti: k3-am65-main: Add hwspinlock node
  arm64: dts: k3-j721e: Add gpio-keys on common processor board
  dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
  ...

47 files changed:
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
MAINTAINERS
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/am33xx-l4.dtsi
arch/arm/boot/dts/am3517.dtsi
arch/arm/boot/dts/am437x-l4.dtsi
arch/arm/boot/dts/aspeed-ast2600-evb.dts [new file with mode: 0644]
arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi [new file with mode: 0644]
arch/arm/boot/dts/aspeed-g6.dtsi [new file with mode: 0644]
arch/arm/boot/dts/dra7-l4.dtsi
arch/arm/boot/dts/gemini-dlink-dir-685.dts
arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts [new file with mode: 0644]
arch/arm/boot/dts/mmp2.dtsi
arch/arm/boot/dts/omap34xx.dtsi
arch/arm/boot/dts/omap36xx.dtsi
arch/arm/boot/dts/omap4-l4-abe.dtsi
arch/arm/boot/dts/omap4-l4.dtsi
arch/arm/boot/dts/omap4.dtsi
arch/arm/boot/dts/omap5.dtsi
arch/arm/boot/dts/omap54xx-clocks.dtsi
arch/arm/mach-exynos/Kconfig
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
arch/arm/plat-samsung/watchdog-reset.c
arch/arm64/boot/dts/marvell/Makefile
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts [new file with mode: 0644]
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
arch/arm64/boot/dts/ti/k3-am65.dtsi
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
arch/arm64/boot/dts/ti/k3-j721e.dtsi
drivers/bus/ti-sysc.c
drivers/clk/ti/clk-54xx.c
include/dt-bindings/bus/ti-sysc.h
include/dt-bindings/clock/omap5.h
include/dt-bindings/pinctrl/k3.h
include/linux/platform_data/ti-sysc.h

index eddde4faef01584ad96c4298b667aa7c276c00d3..f6d6642d81c0758eb61e5c8c9433665194950da8 100644 (file)
@@ -48,3 +48,11 @@ avs: avs@11500 {
        compatible = "marvell,armada-3700-avs", "syscon";
        reg = <0x11500 0x40>;
 }
+
+
+CZ.NIC's Turris Mox SOHO router Device Tree Bindings
+----------------------------------------------------
+
+Required root node property:
+
+ - compatible: must contain "cznic,turris-mox"
index fed7f9743f14d212bfeb2c75080013a743e3cda5..c590a37e87a1f79210519facb9fbb40f5a68b5b5 100644 (file)
@@ -11867,6 +11867,7 @@ S:      Maintained
 F:     arch/arm/mach-omap2/
 F:     arch/arm/plat-omap/
 F:     arch/arm/configs/omap2plus_defconfig
+F:     drivers/bus/ti-sysc.c
 F:     drivers/i2c/busses/i2c-omap.c
 F:     drivers/irqchip/irq-omap-intc.c
 F:     drivers/mfd/*omap*.c
@@ -11887,6 +11888,7 @@ F:      drivers/regulator/tps65910-regulator.c
 F:     drivers/regulator/twl-regulator.c
 F:     drivers/regulator/twl6030-regulator.c
 F:     include/linux/platform_data/i2c-omap.h
+F:     include/linux/platform_data/ti-sysc.h
 
 ONION OMEGA2+ BOARD
 M:     Harvey Hunt <harveyhuntnexus@gmail.com>
index a24a6a132b07967aa72d74e500c1aa50618d069a..b21b3a64641a768733896e6db3b50500432e3b96 100644 (file)
@@ -336,7 +336,8 @@ dtb-$(CONFIG_MACH_MESON8) += \
 dtb-$(CONFIG_ARCH_MMP) += \
        pxa168-aspenite.dtb \
        pxa910-dkb.dtb \
-       mmp2-brownstone.dtb
+       mmp2-brownstone.dtb \
+       mmp2-olpc-xo-1-75.dtb
 dtb-$(CONFIG_ARCH_MPS2) += \
        mps2-an385.dtb \
        mps2-an399.dtb
@@ -1278,6 +1279,7 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
 dtb-$(CONFIG_ARCH_ASPEED) += \
        aspeed-ast2500-evb.dtb \
+       aspeed-ast2600-evb.dtb \
        aspeed-bmc-arm-centriq2400-rep.dtb \
        aspeed-bmc-arm-stardragon4800-rep2.dtb \
        aspeed-bmc-facebook-cmm.dtb \
index 46849d6ecb3e264fb2b6f0fbef0c0e8e1031306a..9915c891e05fa5e5c9d76149f5f90f5c4cc54578 100644 (file)
 
                target-module@100000 {                  /* 0x4a100000, ap 3 08.0 */
                        compatible = "ti,sysc-omap4-simple", "ti,sysc";
-                       ti,hwmods = "cpgmac0";
                        reg = <0x101200 0x4>,
                              <0x101208 0x4>,
                              <0x101204 0x4>;
 
                                davinci_mdio: mdio@1000 {
                                        compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+                                       clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
+                                       clock-names = "fck";
                                        #address-cells = <1>;
                                        #size-cells = <0>;
-                                       ti,hwmods = "davinci_mdio";
                                        bus_freq = <1000000>;
                                        reg = <0x1000 0x100>;
                                        status = "disabled";
index 23ea381d363fd12e6d9ac7f08e8613f1bf12443e..bf3002009b002faafe0d9ddc8338248d7a145f9d 100644 (file)
                        interrupts = <24>;
                        clocks = <&hecc_ck>;
                };
+
+               /*
+                * On am3517 the OCP registers do not seem to be accessible
+                * similar to the omap34xx. Maybe SGX is permanently set to
+                * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
+                * write-only at 0x50000e10. We detect SGX based on the SGX
+                * revision register instead of the unreadable OCP revision
+                * register.
+                */
+               sgx_module: target-module@50000000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x50000014 0x4>;
+                       reg-names = "rev";
+                       clocks = <&sgx_fck>, <&sgx_ick>;
+                       clock-names = "fck", "ick";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x50000000 0x4000>;
+
+                       /*
+                        * Closed source PowerVR driver, no child device
+                        * binding or driver in mainline
+                        */
+               };
        };
 };
 
index 04bee4ff9dcb86e6ea435834d5826c9eca98ab00..59770dd3785eedd89eb065840045585a7a971d7e 100644 (file)
 
                target-module@100000 {                  /* 0x4a100000, ap 3 04.0 */
                        compatible = "ti,sysc-omap4-simple", "ti,sysc";
-                       ti,hwmods = "cpgmac0";
                        reg = <0x101200 0x4>,
                              <0x101208 0x4>,
                              <0x101204 0x4>;
                                davinci_mdio: mdio@1000 {
                                        compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
                                        reg = <0x1000 0x100>;
+                                       clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
+                                       clock-names = "fck";
                                        #address-cells = <1>;
                                        #size-cells = <0>;
-                                       clocks = <&cpsw_125mhz_gclk>;
-                                       clock-names = "fck";
-                                       ti,hwmods = "davinci_mdio";
                                        bus_freq = <1000000>;
                                        status = "disabled";
                                };
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
new file mode 100644 (file)
index 0000000..9870553
--- /dev/null
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+
+/ {
+       model = "AST2600 EVB";
+       compatible = "aspeed,ast2600";
+
+       aliases {
+               serial4 = &uart5;
+       };
+
+       chosen {
+               bootargs = "console=ttyS4,115200n8";
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x80000000>;
+       };
+};
+
+&mdio1 {
+       status = "okay";
+
+       ethphy1: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0>;
+       };
+};
+
+&mdio2 {
+       status = "okay";
+
+       ethphy2: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0>;
+       };
+};
+
+&mdio3 {
+       status = "okay";
+
+       ethphy3: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0>;
+       };
+};
+
+&mac1 {
+       status = "okay";
+
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy1>;
+};
+
+&mac2 {
+       status = "okay";
+
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy2>;
+};
+
+&mac3 {
+       status = "okay";
+
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy3>;
+};
+
+&emmc {
+       status = "okay";
+};
+
+&rtc {
+       status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..5b8bf58
--- /dev/null
@@ -0,0 +1,1154 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+
+&pinctrl {
+       pinctrl_adc0_default: adc0_default {
+               function = "ADC0";
+               groups = "ADC0";
+       };
+
+       pinctrl_adc1_default: adc1_default {
+               function = "ADC1";
+               groups = "ADC1";
+       };
+
+       pinctrl_adc10_default: adc10_default {
+               function = "ADC10";
+               groups = "ADC10";
+       };
+
+       pinctrl_adc11_default: adc11_default {
+               function = "ADC11";
+               groups = "ADC11";
+       };
+
+       pinctrl_adc12_default: adc12_default {
+               function = "ADC12";
+               groups = "ADC12";
+       };
+
+       pinctrl_adc13_default: adc13_default {
+               function = "ADC13";
+               groups = "ADC13";
+       };
+
+       pinctrl_adc14_default: adc14_default {
+               function = "ADC14";
+               groups = "ADC14";
+       };
+
+       pinctrl_adc15_default: adc15_default {
+               function = "ADC15";
+               groups = "ADC15";
+       };
+
+       pinctrl_adc2_default: adc2_default {
+               function = "ADC2";
+               groups = "ADC2";
+       };
+
+       pinctrl_adc3_default: adc3_default {
+               function = "ADC3";
+               groups = "ADC3";
+       };
+
+       pinctrl_adc4_default: adc4_default {
+               function = "ADC4";
+               groups = "ADC4";
+       };
+
+       pinctrl_adc5_default: adc5_default {
+               function = "ADC5";
+               groups = "ADC5";
+       };
+
+       pinctrl_adc6_default: adc6_default {
+               function = "ADC6";
+               groups = "ADC6";
+       };
+
+       pinctrl_adc7_default: adc7_default {
+               function = "ADC7";
+               groups = "ADC7";
+       };
+
+       pinctrl_adc8_default: adc8_default {
+               function = "ADC8";
+               groups = "ADC8";
+       };
+
+       pinctrl_adc9_default: adc9_default {
+               function = "ADC9";
+               groups = "ADC9";
+       };
+
+       pinctrl_bmcint_default: bmcint_default {
+               function = "BMCINT";
+               groups = "BMCINT";
+       };
+
+       pinctrl_espi_default: espi_default {
+               function = "ESPI";
+               groups = "ESPI";
+       };
+
+       pinctrl_espialt_default: espialt_default {
+               function = "ESPIALT";
+               groups = "ESPIALT";
+       };
+
+       pinctrl_fsi1_default: fsi1_default {
+               function = "FSI1";
+               groups = "FSI1";
+       };
+
+       pinctrl_fsi2_default: fsi2_default {
+               function = "FSI2";
+               groups = "FSI2";
+       };
+
+       pinctrl_fwspiabr_default: fwspiabr_default {
+               function = "FWSPIABR";
+               groups = "FWSPIABR";
+       };
+
+       pinctrl_fwspid_default: fwspid_default {
+               function = "FWSPID";
+               groups = "FWSPID";
+       };
+
+       pinctrl_fwqspid_default: fwqspid_default {
+               function = "FWQSPID";
+               groups = "FWQSPID";
+       };
+
+       pinctrl_fwspiwp_default: fwspiwp_default {
+               function = "FWSPIWP";
+               groups = "FWSPIWP";
+       };
+
+       pinctrl_gpit0_default: gpit0_default {
+               function = "GPIT0";
+               groups = "GPIT0";
+       };
+
+       pinctrl_gpit1_default: gpit1_default {
+               function = "GPIT1";
+               groups = "GPIT1";
+       };
+
+       pinctrl_gpit2_default: gpit2_default {
+               function = "GPIT2";
+               groups = "GPIT2";
+       };
+
+       pinctrl_gpit3_default: gpit3_default {
+               function = "GPIT3";
+               groups = "GPIT3";
+       };
+
+       pinctrl_gpit4_default: gpit4_default {
+               function = "GPIT4";
+               groups = "GPIT4";
+       };
+
+       pinctrl_gpit5_default: gpit5_default {
+               function = "GPIT5";
+               groups = "GPIT5";
+       };
+
+       pinctrl_gpit6_default: gpit6_default {
+               function = "GPIT6";
+               groups = "GPIT6";
+       };
+
+       pinctrl_gpit7_default: gpit7_default {
+               function = "GPIT7";
+               groups = "GPIT7";
+       };
+
+       pinctrl_gpiu0_default: gpiu0_default {
+               function = "GPIU0";
+               groups = "GPIU0";
+       };
+
+       pinctrl_gpiu1_default: gpiu1_default {
+               function = "GPIU1";
+               groups = "GPIU1";
+       };
+
+       pinctrl_gpiu2_default: gpiu2_default {
+               function = "GPIU2";
+               groups = "GPIU2";
+       };
+
+       pinctrl_gpiu3_default: gpiu3_default {
+               function = "GPIU3";
+               groups = "GPIU3";
+       };
+
+       pinctrl_gpiu4_default: gpiu4_default {
+               function = "GPIU4";
+               groups = "GPIU4";
+       };
+
+       pinctrl_gpiu5_default: gpiu5_default {
+               function = "GPIU5";
+               groups = "GPIU5";
+       };
+
+       pinctrl_gpiu6_default: gpiu6_default {
+               function = "GPIU6";
+               groups = "GPIU6";
+       };
+
+       pinctrl_gpiu7_default: gpiu7_default {
+               function = "GPIU7";
+               groups = "GPIU7";
+       };
+
+       pinctrl_hvi3c3_default: hvi3c3_default {
+               function = "HVI3C3";
+               groups = "HVI3C3";
+       };
+
+       pinctrl_hvi3c4_default: hvi3c4_default {
+               function = "HVI3C4";
+               groups = "HVI3C4";
+       };
+
+       pinctrl_i2c1_default: i2c1_default {
+               function = "I2C1";
+               groups = "I2C1";
+       };
+
+       pinctrl_i2c10_default: i2c10_default {
+               function = "I2C10";
+               groups = "I2C10";
+       };
+
+       pinctrl_i2c11_default: i2c11_default {
+               function = "I2C11";
+               groups = "I2C11";
+       };
+
+       pinctrl_i2c12_default: i2c12_default {
+               function = "I2C12";
+               groups = "I2C12";
+       };
+
+       pinctrl_i2c13_default: i2c13_default {
+               function = "I2C13";
+               groups = "I2C13";
+       };
+
+       pinctrl_i2c14_default: i2c14_default {
+               function = "I2C14";
+               groups = "I2C14";
+       };
+
+       pinctrl_i2c15_default: i2c15_default {
+               function = "I2C15";
+               groups = "I2C15";
+       };
+
+       pinctrl_i2c16_default: i2c16_default {
+               function = "I2C16";
+               groups = "I2C16";
+       };
+
+       pinctrl_i2c2_default: i2c2_default {
+               function = "I2C2";
+               groups = "I2C2";
+       };
+
+       pinctrl_i2c3_default: i2c3_default {
+               function = "I2C3";
+               groups = "I2C3";
+       };
+
+       pinctrl_i2c4_default: i2c4_default {
+               function = "I2C4";
+               groups = "I2C4";
+       };
+
+       pinctrl_i2c5_default: i2c5_default {
+               function = "I2C5";
+               groups = "I2C5";
+       };
+
+       pinctrl_i2c6_default: i2c6_default {
+               function = "I2C6";
+               groups = "I2C6";
+       };
+
+       pinctrl_i2c7_default: i2c7_default {
+               function = "I2C7";
+               groups = "I2C7";
+       };
+
+       pinctrl_i2c8_default: i2c8_default {
+               function = "I2C8";
+               groups = "I2C8";
+       };
+
+       pinctrl_i2c9_default: i2c9_default {
+               function = "I2C9";
+               groups = "I2C9";
+       };
+
+       pinctrl_i3c3_default: i3c3_default {
+               function = "I3C3";
+               groups = "I3C3";
+       };
+
+       pinctrl_i3c4_default: i3c4_default {
+               function = "I3C4";
+               groups = "I3C4";
+       };
+
+       pinctrl_i3c5_default: i3c5_default {
+               function = "I3C5";
+               groups = "I3C5";
+       };
+
+       pinctrl_i3c6_default: i3c6_default {
+               function = "I3C6";
+               groups = "I3C6";
+       };
+
+       pinctrl_jtagm_default: jtagm_default {
+               function = "JTAGM";
+               groups = "JTAGM";
+       };
+
+       pinctrl_lhpd_default: lhpd_default {
+               function = "LHPD";
+               groups = "LHPD";
+       };
+
+       pinctrl_lhsirq_default: lhsirq_default {
+               function = "LHSIRQ";
+               groups = "LHSIRQ";
+       };
+
+       pinctrl_lpc_default: lpc_default {
+               function = "LPC";
+               groups = "LPC";
+       };
+
+       pinctrl_lpchc_default: lpchc_default {
+               function = "LPCHC";
+               groups = "LPCHC";
+       };
+
+       pinctrl_lpcpd_default: lpcpd_default {
+               function = "LPCPD";
+               groups = "LPCPD";
+       };
+
+       pinctrl_lpcpme_default: lpcpme_default {
+               function = "LPCPME";
+               groups = "LPCPME";
+       };
+
+       pinctrl_lpcsmi_default: lpcsmi_default {
+               function = "LPCSMI";
+               groups = "LPCSMI";
+       };
+
+       pinctrl_lsirq_default: lsirq_default {
+               function = "LSIRQ";
+               groups = "LSIRQ";
+       };
+
+       pinctrl_maclink1_default: maclink1_default {
+               function = "MACLINK1";
+               groups = "MACLINK1";
+       };
+
+       pinctrl_maclink2_default: maclink2_default {
+               function = "MACLINK2";
+               groups = "MACLINK2";
+       };
+
+       pinctrl_maclink3_default: maclink3_default {
+               function = "MACLINK3";
+               groups = "MACLINK3";
+       };
+
+       pinctrl_maclink4_default: maclink4_default {
+               function = "MACLINK4";
+               groups = "MACLINK4";
+       };
+
+       pinctrl_mdio1_default: mdio1_default {
+               function = "MDIO1";
+               groups = "MDIO1";
+       };
+
+       pinctrl_mdio2_default: mdio2_default {
+               function = "MDIO2";
+               groups = "MDIO2";
+       };
+
+       pinctrl_mdio3_default: mdio3_default {
+               function = "MDIO3";
+               groups = "MDIO3";
+       };
+
+       pinctrl_mdio4_default: mdio4_default {
+               function = "MDIO4";
+               groups = "MDIO4";
+       };
+
+       pinctrl_ncts1_default: ncts1_default {
+               function = "NCTS1";
+               groups = "NCTS1";
+       };
+
+       pinctrl_ncts2_default: ncts2_default {
+               function = "NCTS2";
+               groups = "NCTS2";
+       };
+
+       pinctrl_ncts3_default: ncts3_default {
+               function = "NCTS3";
+               groups = "NCTS3";
+       };
+
+       pinctrl_ncts4_default: ncts4_default {
+               function = "NCTS4";
+               groups = "NCTS4";
+       };
+
+       pinctrl_ndcd1_default: ndcd1_default {
+               function = "NDCD1";
+               groups = "NDCD1";
+       };
+
+       pinctrl_ndcd2_default: ndcd2_default {
+               function = "NDCD2";
+               groups = "NDCD2";
+       };
+
+       pinctrl_ndcd3_default: ndcd3_default {
+               function = "NDCD3";
+               groups = "NDCD3";
+       };
+
+       pinctrl_ndcd4_default: ndcd4_default {
+               function = "NDCD4";
+               groups = "NDCD4";
+       };
+
+       pinctrl_ndsr1_default: ndsr1_default {
+               function = "NDSR1";
+               groups = "NDSR1";
+       };
+
+       pinctrl_ndsr2_default: ndsr2_default {
+               function = "NDSR2";
+               groups = "NDSR2";
+       };
+
+       pinctrl_ndsr3_default: ndsr3_default {
+               function = "NDSR3";
+               groups = "NDSR3";
+       };
+
+       pinctrl_ndsr4_default: ndsr4_default {
+               function = "NDSR4";
+               groups = "NDSR4";
+       };
+
+       pinctrl_ndtr1_default: ndtr1_default {
+               function = "NDTR1";
+               groups = "NDTR1";
+       };
+
+       pinctrl_ndtr2_default: ndtr2_default {
+               function = "NDTR2";
+               groups = "NDTR2";
+       };
+
+       pinctrl_ndtr3_default: ndtr3_default {
+               function = "NDTR3";
+               groups = "NDTR3";
+       };
+
+       pinctrl_ndtr4_default: ndtr4_default {
+               function = "NDTR4";
+               groups = "NDTR4";
+       };
+
+       pinctrl_nri1_default: nri1_default {
+               function = "NRI1";
+               groups = "NRI1";
+       };
+
+       pinctrl_nri2_default: nri2_default {
+               function = "NRI2";
+               groups = "NRI2";
+       };
+
+       pinctrl_nri3_default: nri3_default {
+               function = "NRI3";
+               groups = "NRI3";
+       };
+
+       pinctrl_nri4_default: nri4_default {
+               function = "NRI4";
+               groups = "NRI4";
+       };
+
+       pinctrl_nrts1_default: nrts1_default {
+               function = "NRTS1";
+               groups = "NRTS1";
+       };
+
+       pinctrl_nrts2_default: nrts2_default {
+               function = "NRTS2";
+               groups = "NRTS2";
+       };
+
+       pinctrl_nrts3_default: nrts3_default {
+               function = "NRTS3";
+               groups = "NRTS3";
+       };
+
+       pinctrl_nrts4_default: nrts4_default {
+               function = "NRTS4";
+               groups = "NRTS4";
+       };
+
+       pinctrl_oscclk_default: oscclk_default {
+               function = "OSCCLK";
+               groups = "OSCCLK";
+       };
+
+       pinctrl_pewake_default: pewake_default {
+               function = "PEWAKE";
+               groups = "PEWAKE";
+       };
+
+       pinctrl_pwm0_default: pwm0_default {
+               function = "PWM0";
+               groups = "PWM0";
+       };
+
+       pinctrl_pwm1_default: pwm1_default {
+               function = "PWM1";
+               groups = "PWM1";
+       };
+
+       pinctrl_pwm10g0_default: pwm10g0_default {
+               function = "PWM10";
+               groups = "PWM10G0";
+       };
+
+       pinctrl_pwm10g1_default: pwm10g1_default {
+               function = "PWM10";
+               groups = "PWM10G1";
+       };
+
+       pinctrl_pwm11g0_default: pwm11g0_default {
+               function = "PWM11";
+               groups = "PWM11G0";
+       };
+
+       pinctrl_pwm11g1_default: pwm11g1_default {
+               function = "PWM11";
+               groups = "PWM11G1";
+       };
+
+       pinctrl_pwm12g0_default: pwm12g0_default {
+               function = "PWM12";
+               groups = "PWM12G0";
+       };
+
+       pinctrl_pwm12g1_default: pwm12g1_default {
+               function = "PWM12";
+               groups = "PWM12G1";
+       };
+
+       pinctrl_pwm13g0_default: pwm13g0_default {
+               function = "PWM13";
+               groups = "PWM13G0";
+       };
+
+       pinctrl_pwm13g1_default: pwm13g1_default {
+               function = "PWM13";
+               groups = "PWM13G1";
+       };
+
+       pinctrl_pwm14g0_default: pwm14g0_default {
+               function = "PWM14";
+               groups = "PWM14G0";
+       };
+
+       pinctrl_pwm14g1_default: pwm14g1_default {
+               function = "PWM14";
+               groups = "PWM14G1";
+       };
+
+       pinctrl_pwm15g0_default: pwm15g0_default {
+               function = "PWM15";
+               groups = "PWM15G0";
+       };
+
+       pinctrl_pwm15g1_default: pwm15g1_default {
+               function = "PWM15";
+               groups = "PWM15G1";
+       };
+
+       pinctrl_pwm2_default: pwm2_default {
+               function = "PWM2";
+               groups = "PWM2";
+       };
+
+       pinctrl_pwm3_default: pwm3_default {
+               function = "PWM3";
+               groups = "PWM3";
+       };
+
+       pinctrl_pwm4_default: pwm4_default {
+               function = "PWM4";
+               groups = "PWM4";
+       };
+
+       pinctrl_pwm5_default: pwm5_default {
+               function = "PWM5";
+               groups = "PWM5";
+       };
+
+       pinctrl_pwm6_default: pwm6_default {
+               function = "PWM6";
+               groups = "PWM6";
+       };
+
+       pinctrl_pwm7_default: pwm7_default {
+               function = "PWM7";
+               groups = "PWM7";
+       };
+
+       pinctrl_pwm8g0_default: pwm8g0_default {
+               function = "PWM8";
+               groups = "PWM8G0";
+       };
+
+       pinctrl_pwm8g1_default: pwm8g1_default {
+               function = "PWM8";
+               groups = "PWM8G1";
+       };
+
+       pinctrl_pwm9g0_default: pwm9g0_default {
+               function = "PWM9";
+               groups = "PWM9G0";
+       };
+
+       pinctrl_pwm9g1_default: pwm9g1_default {
+               function = "PWM9";
+               groups = "PWM9G1";
+       };
+
+       pinctrl_qspi1_default: qspi1_default {
+               function = "QSPI1";
+               groups = "QSPI1";
+       };
+
+       pinctrl_qspi2_default: qspi2_default {
+               function = "QSPI2";
+               groups = "QSPI2";
+       };
+
+       pinctrl_rgmii1_default: rgmii1_default {
+               function = "RGMII1";
+               groups = "RGMII1";
+       };
+
+       pinctrl_rgmii2_default: rgmii2_default {
+               function = "RGMII2";
+               groups = "RGMII2";
+       };
+
+       pinctrl_rgmii3_default: rgmii3_default {
+               function = "RGMII3";
+               groups = "RGMII3";
+       };
+
+       pinctrl_rgmii4_default: rgmii4_default {
+               function = "RGMII4";
+               groups = "RGMII4";
+       };
+
+       pinctrl_rmii1_default: rmii1_default {
+               function = "RMII1";
+               groups = "RMII1";
+       };
+
+       pinctrl_rmii2_default: rmii2_default {
+               function = "RMII2";
+               groups = "RMII2";
+       };
+
+       pinctrl_rmii3_default: rmii3_default {
+               function = "RMII3";
+               groups = "RMII3";
+       };
+
+       pinctrl_rmii4_default: rmii4_default {
+               function = "RMII4";
+               groups = "RMII4";
+       };
+
+       pinctrl_rxd1_default: rxd1_default {
+               function = "RXD1";
+               groups = "RXD1";
+       };
+
+       pinctrl_rxd2_default: rxd2_default {
+               function = "RXD2";
+               groups = "RXD2";
+       };
+
+       pinctrl_rxd3_default: rxd3_default {
+               function = "RXD3";
+               groups = "RXD3";
+       };
+
+       pinctrl_rxd4_default: rxd4_default {
+               function = "RXD4";
+               groups = "RXD4";
+       };
+
+       pinctrl_salt1_default: salt1_default {
+               function = "SALT1";
+               groups = "SALT1";
+       };
+
+       pinctrl_salt10g0_default: salt10g0_default {
+               function = "SALT10";
+               groups = "SALT10G0";
+       };
+
+       pinctrl_salt10g1_default: salt10g1_default {
+               function = "SALT10";
+               groups = "SALT10G1";
+       };
+
+       pinctrl_salt11g0_default: salt11g0_default {
+               function = "SALT11";
+               groups = "SALT11G0";
+       };
+
+       pinctrl_salt11g1_default: salt11g1_default {
+               function = "SALT11";
+               groups = "SALT11G1";
+       };
+
+       pinctrl_salt12g0_default: salt12g0_default {
+               function = "SALT12";
+               groups = "SALT12G0";
+       };
+
+       pinctrl_salt12g1_default: salt12g1_default {
+               function = "SALT12";
+               groups = "SALT12G1";
+       };
+
+       pinctrl_salt13g0_default: salt13g0_default {
+               function = "SALT13";
+               groups = "SALT13G0";
+       };
+
+       pinctrl_salt13g1_default: salt13g1_default {
+               function = "SALT13";
+               groups = "SALT13G1";
+       };
+
+       pinctrl_salt14g0_default: salt14g0_default {
+               function = "SALT14";
+               groups = "SALT14G0";
+       };
+
+       pinctrl_salt14g1_default: salt14g1_default {
+               function = "SALT14";
+               groups = "SALT14G1";
+       };
+
+       pinctrl_salt15g0_default: salt15g0_default {
+               function = "SALT15";
+               groups = "SALT15G0";
+       };
+
+       pinctrl_salt15g1_default: salt15g1_default {
+               function = "SALT15";
+               groups = "SALT15G1";
+       };
+
+       pinctrl_salt16g0_default: salt16g0_default {
+               function = "SALT16";
+               groups = "SALT16G0";
+       };
+
+       pinctrl_salt16g1_default: salt16g1_default {
+               function = "SALT16";
+               groups = "SALT16G1";
+       };
+
+       pinctrl_salt2_default: salt2_default {
+               function = "SALT2";
+               groups = "SALT2";
+       };
+
+       pinctrl_salt3_default: salt3_default {
+               function = "SALT3";
+               groups = "SALT3";
+       };
+
+       pinctrl_salt4_default: salt4_default {
+               function = "SALT4";
+               groups = "SALT4";
+       };
+
+       pinctrl_salt5_default: salt5_default {
+               function = "SALT5";
+               groups = "SALT5";
+       };
+
+       pinctrl_salt6_default: salt6_default {
+               function = "SALT6";
+               groups = "SALT6";
+       };
+
+       pinctrl_salt7_default: salt7_default {
+               function = "SALT7";
+               groups = "SALT7";
+       };
+
+       pinctrl_salt8_default: salt8_default {
+               function = "SALT8";
+               groups = "SALT8";
+       };
+
+       pinctrl_salt9g0_default: salt9g0_default {
+               function = "SALT9";
+               groups = "SALT9G0";
+       };
+
+       pinctrl_salt9g1_default: salt9g1_default {
+               function = "SALT9";
+               groups = "SALT9G1";
+       };
+
+       pinctrl_sd1_default: sd1_default {
+               function = "SD1";
+               groups = "SD1";
+       };
+
+       pinctrl_sd2_default: sd2_default {
+               function = "SD2";
+               groups = "SD2";
+       };
+
+       pinctrl_sd3_default: sd3_default {
+               function = "SD3";
+               groups = "SD3";
+       };
+
+       pinctrl_emmc_default: emmc_default {
+               function = "SD3";
+               groups = "EMMC";
+       };
+
+       pinctrl_sgpm1_default: sgpm1_default {
+               function = "SGPM1";
+               groups = "SGPM1";
+       };
+
+       pinctrl_sgps1_default: sgps1_default {
+               function = "SGPS1";
+               groups = "SGPS1";
+       };
+
+       pinctrl_sioonctrl_default: sioonctrl_default {
+               function = "SIOONCTRL";
+               groups = "SIOONCTRL";
+       };
+
+       pinctrl_siopbi_default: siopbi_default {
+               function = "SIOPBI";
+               groups = "SIOPBI";
+       };
+
+       pinctrl_siopbo_default: siopbo_default {
+               function = "SIOPBO";
+               groups = "SIOPBO";
+       };
+
+       pinctrl_siopwreq_default: siopwreq_default {
+               function = "SIOPWREQ";
+               groups = "SIOPWREQ";
+       };
+
+       pinctrl_siopwrgd_default: siopwrgd_default {
+               function = "SIOPWRGD";
+               groups = "SIOPWRGD";
+       };
+
+       pinctrl_sios3_default: sios3_default {
+               function = "SIOS3";
+               groups = "SIOS3";
+       };
+
+       pinctrl_sios5_default: sios5_default {
+               function = "SIOS5";
+               groups = "SIOS5";
+       };
+
+       pinctrl_siosci_default: siosci_default {
+               function = "SIOSCI";
+               groups = "SIOSCI";
+       };
+
+       pinctrl_spi1_default: spi1_default {
+               function = "SPI1";
+               groups = "SPI1";
+       };
+
+       pinctrl_spi1abr_default: spi1abr_default {
+               function = "SPI1ABR";
+               groups = "SPI1ABR";
+       };
+
+       pinctrl_spi1cs1_default: spi1cs1_default {
+               function = "SPI1CS1";
+               groups = "SPI1CS1";
+       };
+
+       pinctrl_spi1wp_default: spi1wp_default {
+               function = "SPI1WP";
+               groups = "SPI1WP";
+       };
+
+       pinctrl_spi2_default: spi2_default {
+               function = "SPI2";
+               groups = "SPI2";
+       };
+
+       pinctrl_spi2cs1_default: spi2cs1_default {
+               function = "SPI2CS1";
+               groups = "SPI2CS1";
+       };
+
+       pinctrl_spi2cs2_default: spi2cs2_default {
+               function = "SPI2CS2";
+               groups = "SPI2CS2";
+       };
+
+       pinctrl_tach0_default: tach0_default {
+               function = "TACH0";
+               groups = "TACH0";
+       };
+
+       pinctrl_tach1_default: tach1_default {
+               function = "TACH1";
+               groups = "TACH1";
+       };
+
+       pinctrl_tach10_default: tach10_default {
+               function = "TACH10";
+               groups = "TACH10";
+       };
+
+       pinctrl_tach11_default: tach11_default {
+               function = "TACH11";
+               groups = "TACH11";
+       };
+
+       pinctrl_tach12_default: tach12_default {
+               function = "TACH12";
+               groups = "TACH12";
+       };
+
+       pinctrl_tach13_default: tach13_default {
+               function = "TACH13";
+               groups = "TACH13";
+       };
+
+       pinctrl_tach14_default: tach14_default {
+               function = "TACH14";
+               groups = "TACH14";
+       };
+
+       pinctrl_tach15_default: tach15_default {
+               function = "TACH15";
+               groups = "TACH15";
+       };
+
+       pinctrl_tach2_default: tach2_default {
+               function = "TACH2";
+               groups = "TACH2";
+       };
+
+       pinctrl_tach3_default: tach3_default {
+               function = "TACH3";
+               groups = "TACH3";
+       };
+
+       pinctrl_tach4_default: tach4_default {
+               function = "TACH4";
+               groups = "TACH4";
+       };
+
+       pinctrl_tach5_default: tach5_default {
+               function = "TACH5";
+               groups = "TACH5";
+       };
+
+       pinctrl_tach6_default: tach6_default {
+               function = "TACH6";
+               groups = "TACH6";
+       };
+
+       pinctrl_tach7_default: tach7_default {
+               function = "TACH7";
+               groups = "TACH7";
+       };
+
+       pinctrl_tach8_default: tach8_default {
+               function = "TACH8";
+               groups = "TACH8";
+       };
+
+       pinctrl_tach9_default: tach9_default {
+               function = "TACH9";
+               groups = "TACH9";
+       };
+
+       pinctrl_thru0_default: thru0_default {
+               function = "THRU0";
+               groups = "THRU0";
+       };
+
+       pinctrl_thru1_default: thru1_default {
+               function = "THRU1";
+               groups = "THRU1";
+       };
+
+       pinctrl_thru2_default: thru2_default {
+               function = "THRU2";
+               groups = "THRU2";
+       };
+
+       pinctrl_thru3_default: thru3_default {
+               function = "THRU3";
+               groups = "THRU3";
+       };
+
+       pinctrl_txd1_default: txd1_default {
+               function = "TXD1";
+               groups = "TXD1";
+       };
+
+       pinctrl_txd2_default: txd2_default {
+               function = "TXD2";
+               groups = "TXD2";
+       };
+
+       pinctrl_txd3_default: txd3_default {
+               function = "TXD3";
+               groups = "TXD3";
+       };
+
+       pinctrl_txd4_default: txd4_default {
+               function = "TXD4";
+               groups = "TXD4";
+       };
+
+       pinctrl_uart10_default: uart10_default {
+               function = "UART10";
+               groups = "UART10";
+       };
+
+       pinctrl_uart11_default: uart11_default {
+               function = "UART11";
+               groups = "UART11";
+       };
+
+       pinctrl_uart12g0_default: uart12g0_default {
+               function = "UART12";
+               groups = "UART12G0";
+       };
+
+       pinctrl_uart12g1_default: uart12g1_default {
+               function = "UART12";
+               groups = "UART12G1";
+       };
+
+       pinctrl_uart13g0_default: uart13g0_default {
+               function = "UART13";
+               groups = "UART13G0";
+       };
+
+       pinctrl_uart13g1_default: uart13g1_default {
+               function = "UART13";
+               groups = "UART13G1";
+       };
+
+       pinctrl_uart6_default: uart6_default {
+               function = "UART6";
+               groups = "UART6";
+       };
+
+       pinctrl_uart7_default: uart7_default {
+               function = "UART7";
+               groups = "UART7";
+       };
+
+       pinctrl_uart8_default: uart8_default {
+               function = "UART8";
+               groups = "UART8";
+       };
+
+       pinctrl_uart9_default: uart9_default {
+               function = "UART9";
+               groups = "UART9";
+       };
+
+       pinctrl_vb_default: vb_default {
+               function = "VB";
+               groups = "VB";
+       };
+
+       pinctrl_vgahs_default: vgahs_default {
+               function = "VGAHS";
+               groups = "VGAHS";
+       };
+
+       pinctrl_vgavs_default: vgavs_default {
+               function = "VGAVS";
+               groups = "VGAVS";
+       };
+
+       pinctrl_wdtrst1_default: wdtrst1_default {
+               function = "WDTRST1";
+               groups = "WDTRST1";
+       };
+
+       pinctrl_wdtrst2_default: wdtrst2_default {
+               function = "WDTRST2";
+               groups = "WDTRST2";
+       };
+
+       pinctrl_wdtrst3_default: wdtrst3_default {
+               function = "WDTRST3";
+               groups = "WDTRST3";
+       };
+
+       pinctrl_wdtrst4_default: wdtrst4_default {
+               function = "WDTRST4";
+               groups = "WDTRST4";
+       };
+};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
new file mode 100644 (file)
index 0000000..3a1422f
--- /dev/null
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/ast2600-clock.h>
+
+/ {
+       model = "Aspeed BMC";
+       compatible = "aspeed,ast2600";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&gic>;
+
+       aliases {
+               serial4 = &uart5;
+       };
+
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "aspeed,ast2600-smp";
+
+               cpu@f00 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0xf00>;
+               };
+
+               cpu@f01 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0xf01>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+               clocks = <&syscon ASPEED_CLK_HPLL>;
+               arm,cpu-registers-not-fw-configured;
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               ranges;
+
+               gic: interrupt-controller@40461000 {
+                       compatible = "arm,cortex-a7-gic";
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       interrupt-parent = <&gic>;
+                       reg = <0x40461000 0x1000>,
+                           <0x40462000 0x1000>,
+                           <0x40464000 0x2000>,
+                           <0x40466000 0x2000>;
+                       };
+
+               mdio0: mdio@1e650000 {
+                       compatible = "aspeed,ast2600-mdio";
+                       reg = <0x1e650000 0x8>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               mdio1: mdio@1e650008 {
+                       compatible = "aspeed,ast2600-mdio";
+                       reg = <0x1e650008 0x8>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               mdio2: mdio@1e650010 {
+                       compatible = "aspeed,ast2600-mdio";
+                       reg = <0x1e650010 0x8>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               mdio3: mdio@1e650018 {
+                       compatible = "aspeed,ast2600-mdio";
+                       reg = <0x1e650018 0x8>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               mac0: ftgmac@1e660000 {
+                       compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
+                       reg = <0x1e660000 0x180>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
+                       status = "disabled";
+               };
+
+               mac1: ftgmac@1e680000 {
+                       compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
+                       reg = <0x1e680000 0x180>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
+                       status = "disabled";
+               };
+
+               mac2: ftgmac@1e670000 {
+                       compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
+                       reg = <0x1e670000 0x180>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
+                       status = "disabled";
+               };
+
+               mac3: ftgmac@1e690000 {
+                       compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
+                       reg = <0x1e690000 0x180>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
+                       status = "disabled";
+               };
+
+               apb {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       syscon: syscon@1e6e2000 {
+                               compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
+                               reg = <0x1e6e2000 0x1000>;
+                               ranges = <0 0x1e6e2000 0x1000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               #clock-cells = <1>;
+                               #reset-cells = <1>;
+
+                               pinctrl: pinctrl {
+                                       compatible = "aspeed,ast2600-pinctrl";
+                               };
+
+                               smp-memram@180 {
+                                       compatible = "aspeed,ast2600-smpmem";
+                                       reg = <0x180 0x40>;
+                               };
+                       };
+
+                       rng: hwrng@1e6e2524 {
+                               compatible = "timeriomem_rng";
+                               reg = <0x1e6e2524 0x4>;
+                               period = <1>;
+                               quality = <100>;
+                       };
+
+                       rtc: rtc@1e781000 {
+                               compatible = "aspeed,ast2600-rtc";
+                               reg = <0x1e781000 0x18>;
+                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                               status = "disabled";
+                       };
+
+                       uart5: serial@1e784000 {
+                               compatible = "ns16550a";
+                               reg = <0x1e784000 0x1000>;
+                               reg-shift = <2>;
+                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
+                               no-loopback-test;
+                       };
+
+                       wdt1: watchdog@1e785000 {
+                               compatible = "aspeed,ast2600-wdt";
+                               reg = <0x1e785000 0x40>;
+                       };
+
+                       wdt2: watchdog@1e785040 {
+                               compatible = "aspeed,ast2600-wdt";
+                               reg = <0x1e785040 0x40>;
+                               status = "disabled";
+                       };
+
+                       wdt3: watchdog@1e785080 {
+                               compatible = "aspeed,ast2600-wdt";
+                               reg = <0x1e785080 0x40>;
+                               status = "disabled";
+                       };
+
+                       wdt4: watchdog@1e7850C0 {
+                               compatible = "aspeed,ast2600-wdt";
+                               reg = <0x1e7850C0 0x40>;
+                               status = "disabled";
+                       };
+
+                       sdc: sdc@1e740000 {
+                               compatible = "aspeed,ast2600-sd-controller";
+                               reg = <0x1e740000 0x100>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x1e740000 0x10000>;
+                               clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
+                               status = "disabled";
+
+                               sdhci0: sdhci@1e740100 {
+                                       compatible = "aspeed,ast2600-sdhci", "sdhci";
+                                       reg = <0x100 0x100>;
+                                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                                       sdhci,auto-cmd12;
+                                       clocks = <&syscon ASPEED_CLK_SDIO>;
+                                       status = "disabled";
+                               };
+
+                               sdhci1: sdhci@1e740200 {
+                                       compatible = "aspeed,ast2600-sdhci", "sdhci";
+                                       reg = <0x200 0x100>;
+                                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                                       sdhci,auto-cmd12;
+                                       clocks = <&syscon ASPEED_CLK_SDIO>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       emmc: sdc@1e750000 {
+                               compatible = "aspeed,ast2600-sd-controller";
+                               reg = <0x1e750000 0x100>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x1e750000 0x10000>;
+                               clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
+                               status = "disabled";
+
+                               sdhci@1e750100 {
+                                       compatible = "aspeed,ast2600-sdhci";
+                                       reg = <0x100 0x100>;
+                                       sdhci,auto-cmd12;
+                                       interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&syscon ASPEED_CLK_EMMC>;
+                                       pinctrl-names = "default";
+                                       pinctrl-0 = <&pinctrl_emmc_default>;
+                               };
+                       };
+               };
+       };
+};
+
+#include "aspeed-g6-pinctrl.dtsi"
index 21e5914fdd6209157b7149710b4cec249056c9dc..ea0e7c19eb4e3e3cb4fcdeb790229bcda971f928 100644 (file)
 
                target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart3";
                        reg = <0x20050 0x4>,
                              <0x20054 0x4>,
                              <0x20058 0x4>;
 
                gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio7";
                        reg = <0x51000 0x4>,
                              <0x51010 0x4>,
                              <0x51114 0x4>;
 
                target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio8";
                        reg = <0x53000 0x4>,
                              <0x53010 0x4>,
                              <0x53114 0x4>;
 
                target-module@55000 {                   /* 0x48055000, ap 13 0e.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio2";
                        reg = <0x55000 0x4>,
                              <0x55010 0x4>,
                              <0x55114 0x4>;
 
                target-module@57000 {                   /* 0x48057000, ap 15 06.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio3";
                        reg = <0x57000 0x4>,
                              <0x57010 0x4>,
                              <0x57114 0x4>;
 
                target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio4";
                        reg = <0x59000 0x4>,
                              <0x59010 0x4>,
                              <0x59114 0x4>;
 
                target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio5";
                        reg = <0x5b000 0x4>,
                              <0x5b010 0x4>,
                              <0x5b114 0x4>;
 
                target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio6";
                        reg = <0x5d000 0x4>,
                              <0x5d010 0x4>,
                              <0x5d114 0x4>;
 
                target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c3";
                        reg = <0x60000 0x8>,
                              <0x60010 0x8>,
                              <0x60090 0x8>;
 
                target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart5";
                        reg = <0x66050 0x4>,
                              <0x66054 0x4>,
                              <0x66058 0x4>;
 
                target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart6";
                        reg = <0x68050 0x4>,
                              <0x68054 0x4>,
                              <0x68058 0x4>;
 
                target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart1";
                        reg = <0x6a050 0x4>,
                              <0x6a054 0x4>,
                              <0x6a058 0x4>;
 
                target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart2";
                        reg = <0x6c050 0x4>,
                              <0x6c054 0x4>,
                              <0x6c058 0x4>;
 
                target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart4";
                        reg = <0x6e050 0x4>,
                              <0x6e054 0x4>,
                              <0x6e058 0x4>;
 
                target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c1";
                        reg = <0x70000 0x8>,
                              <0x70010 0x8>,
                              <0x70090 0x8>;
 
                target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c2";
                        reg = <0x72000 0x8>,
                              <0x72010 0x8>,
                              <0x72090 0x8>;
 
                target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c4";
                        reg = <0x7a000 0x8>,
                              <0x7a010 0x8>,
                              <0x7a090 0x8>;
 
                target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c5";
                        reg = <0x7c000 0x8>,
                              <0x7c010 0x8>,
                              <0x7c090 0x8>;
 
                target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mcspi1";
                        reg = <0x98000 0x4>,
                              <0x98010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mcspi2";
                        reg = <0x9a000 0x4>,
                              <0x9a010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mmc1";
                        reg = <0x9c000 0x4>,
                              <0x9c010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mmc3";
                        reg = <0xad000 0x4>,
                              <0xad010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mmc2";
                        reg = <0xb4000 0x4>,
                              <0xb4010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mcspi3";
                        reg = <0xb8000 0x4>,
                              <0xb8010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mcspi4";
                        reg = <0xba000 0x4>,
                              <0xba010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "mmc4";
                        reg = <0xd1000 0x4>,
                              <0xd1010 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart7";
                        reg = <0x20050 0x4>,
                              <0x20054 0x4>,
                              <0x20058 0x4>;
 
                target-module@22000 {                   /* 0x48422000, ap 49 0a.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart8";
                        reg = <0x22050 0x4>,
                              <0x22054 0x4>,
                              <0x22058 0x4>;
 
                target-module@24000 {                   /* 0x48424000, ap 51 12.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart9";
                        reg = <0x24050 0x4>,
                              <0x24054 0x4>,
                              <0x24058 0x4>;
 
                target-module@60000 {                   /* 0x48460000, ap 9 0e.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp1";
                        reg = <0x60000 0x4>,
                              <0x60004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@64000 {                   /* 0x48464000, ap 11 1e.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp2";
                        reg = <0x64000 0x4>,
                              <0x64004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@68000 {                   /* 0x48468000, ap 13 26.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp3";
                        reg = <0x68000 0x4>,
                              <0x68004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@6c000 {                   /* 0x4846c000, ap 15 2e.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp4";
                        reg = <0x6c000 0x4>,
                              <0x6c004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@70000 {                   /* 0x48470000, ap 19 36.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp5";
                        reg = <0x70000 0x4>,
                              <0x70004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@74000 {                   /* 0x48474000, ap 35 14.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp6";
                        reg = <0x74000 0x4>,
                              <0x74004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@78000 {                   /* 0x48478000, ap 39 0c.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp7";
                        reg = <0x78000 0x4>,
                              <0x78004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@7c000 {                   /* 0x4847c000, ap 43 04.0 */
                        compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
-                       ti,hwmods = "mcasp8";
                        reg = <0x7c000 0x4>,
                              <0x7c004 0x4>;
                        reg-names = "rev", "sysc";
 
                target-module@84000 {                   /* 0x48484000, ap 3 10.0 */
                        compatible = "ti,sysc-omap4-simple", "ti,sysc";
-                       ti,hwmods = "gmac";
                        reg = <0x85200 0x4>,
                              <0x85208 0x4>,
                              <0x85204 0x4>;
 
                                davinci_mdio: mdio@1000 {
                                        compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+                                       clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
+                                       clock-names = "fck";
                                        #address-cells = <1>;
                                        #size-cells = <0>;
-                                       ti,hwmods = "davinci_mdio";
                                        bus_freq = <1000000>;
                                        reg = <0x1000 0x100>;
                                };
 
                target-module@0 {                       /* 0x4ae10000, ap 5 20.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "gpio1";
                        reg = <0x0 0x4>,
                              <0x10 0x4>,
                              <0x114 0x4>;
 
                target-module@b000 {                    /* 0x4ae2b000, ap 28 02.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "uart10";
                        reg = <0xb050 0x4>,
                              <0xb054 0x4>,
                              <0xb058 0x4>;
index bfaa2de63a1001e7aec1ca5154b47f60983dad1c..e2030ba16512f52c927e0b53a2fca54b9a613490 100644 (file)
@@ -72,7 +72,6 @@
                        reg = <0>;
                        /* 50 ns min period = 20 MHz */
                        spi-max-frequency = <20000000>;
-                       spi-cpol; /* Clock active low */
                        vcc-supply = <&vdisp>;
                        iovcc-supply = <&vdisp>;
                        vci-supply = <&vdisp>;
diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts
new file mode 100644 (file)
index 0000000..6cfa0d4
--- /dev/null
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * OLPC XO 1.75 Laptop.
+ *
+ * Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+/dts-v1/;
+#include "mmp2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       model = "OLPC XO-1.75";
+       compatible = "olpc,xo-1.75", "mrvl,mmp2";
+
+       chosen {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               framebuffer@1fc00000 {
+                       compatible = "simple-framebuffer";
+                       reg = <0x1fc00000 (1200 * 900 * 2)>;
+                       width = <1200>;
+                       height = <900>;
+                       stride = <(1200 * 2)>;
+                       format = "r5g6b5";
+                       clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>,
+                                <&soc_clocks MMP2_CLK_DISP0>;
+               };
+       };
+
+       memory {
+               linux,usable-memory = <0x0 0x1f800000>;
+               available = <0xcf000 0x1ef31000 0x1000 0xbf000>;
+               reg = <0x0 0x20000000>;
+               device_type = "memory";
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               lid {
+                       label = "Lid";
+                       gpios = <&gpio 129 GPIO_ACTIVE_LOW>;
+                       linux,input-type = <EV_SW>;
+                       linux,code = <SW_LID>;
+                       wakeup-source;
+               };
+
+               tablet_mode {
+                       label = "E-Book Mode";
+                       gpios = <&gpio 128 GPIO_ACTIVE_LOW>;
+                       linux,input-type = <EV_SW>;
+                       linux,code = <SW_TABLET_MODE>;
+                       wakeup-source;
+               };
+
+               microphone_insert {
+                       label = "Microphone Plug";
+                       gpios = <&gpio 96 GPIO_ACTIVE_HIGH>;
+                       linux,input-type = <EV_SW>;
+                       linux,code = <SW_MICROPHONE_INSERT>;
+                       debounce-interval = <100>;
+                       wakeup-source;
+               };
+
+               headphone_insert {
+                       label = "Headphone Plug";
+                       gpios = <&gpio 97 GPIO_ACTIVE_HIGH>;
+                       linux,input-type = <EV_SW>;
+                       linux,code = <SW_HEADPHONE_INSERT>;
+                       debounce-interval = <100>;
+                       wakeup-source;
+               };
+       };
+
+       camera_i2c {
+               compatible = "i2c-gpio";
+               gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
+                       <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-gpio,timeout-ms = <1000>;
+               status = "okay";
+
+               camera@21 {
+                       compatible = "ovti,ov7670";
+                       reg = <0x21>;
+                       reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>;
+                       powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>;
+                       clocks = <&camera0>;
+                       clock-names = "xclk";
+
+                       port {
+                               ov7670_0: endpoint {
+                                       hsync-active = <1>;
+                                       vsync-active = <1>;
+                                       remote-endpoint = <&camera0_0>;
+                               };
+                       };
+               };
+       };
+
+       battery {
+               compatible = "olpc,xo1.5-battery", "olpc,xo1-battery";
+       };
+
+       wlan_reg: fixedregulator0 {
+               compatible = "regulator-fixed";
+               regulator-name = "wlan";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio 34 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       wlan_pwrseq: pwrseq0 {
+               compatible = "mmc-pwrseq-sd8787";
+               powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>;
+       };
+
+       soc {
+               axi@d4200000 {
+                       ap-sp@d4290000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "olpc,ap-sp";
+                               interrupts = <40>;
+                               reg = <0xd4290000 0x1000>;
+                               data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
+                               clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>;
+                               status = "okay";
+                       };
+               };
+       };
+};
+
+&uart3 {
+       status = "okay";
+};
+
+&uart4 {
+       status = "okay";
+};
+
+&rtc {
+       status = "okay";
+};
+
+&usb_phy0 {
+       status = "okay";
+};
+
+&usb_otg0 {
+       status = "okay";
+};
+
+&mmc1 {
+       clock-frequency = <50000000>;
+       no-1-8-v;
+       mrvl,clk-delay-cycles = <31>;
+       broken-cd;
+       status = "okay";
+};
+
+&mmc2 {
+       clock-frequency = <50000000>;
+       no-1-8-v;
+       bus-width = <4>;
+       non-removable;
+       broken-cd;
+       wakeup-source;
+       keep-power-in-suspend;
+       mmc-pwrseq = <&wlan_pwrseq>;
+       vmmc-supply = <&wlan_reg>;
+       status = "okay";
+};
+
+&mmc3 {
+       clock-frequency = <50000000>;
+       no-1-8-v;
+       bus-width = <8>;
+       non-removable;
+       broken-cd;
+       mrvl,clk-delay-cycles = <31>;
+       status = "okay";
+};
+
+&twsi1 {
+       status = "okay";
+
+       audio-codec@1a {
+               compatible = "realtek,alc5631";
+               reg = <0x1a>;
+               status = "okay";
+       };
+};
+
+&twsi2 {
+       status = "okay";
+
+       rtc@68 {
+               compatible = "dallas,ds1338";
+               reg = <0x68>;
+               status = "okay";
+       };
+};
+
+&twsi6 {
+       status = "okay";
+
+       accelerometer@1d {
+               compatible = "st,lis331dlh", "st,lis3lv02d";
+               reg = <0x1d>;
+               status = "okay";
+       };
+};
+
+&ssp3 {
+       #address-cells = <0>;
+       spi-slave;
+       status = "okay";
+       ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>;
+
+       slave {
+               compatible = "olpc,xo1.75-ec";
+               spi-cpha;
+               cmd-gpio = <&gpio 155 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&camera0 {
+       status = "okay";
+
+       port {
+               camera0_0: endpoint {
+                       remote-endpoint = <&ov7670_0>;
+               };
+       };
+};
index b6f40743e07b0e68be484a7f9cc5ce909ade97ed..6a2f072c1d0a88cd1d71cceb5e05f5ecd20e9151 100644 (file)
                                mrvl,intc-nr-irqs = <2>;
                        };
 
-                       usb_otg_phy0: usb-otg-phy@d4207000 {
+                       usb_phy0: usb-phy@d4207000 {
                                compatible = "marvell,mmp2-usb-phy";
                                reg = <0xd4207000 0x40>;
                                #phy-cells = <0>;
                                interrupts = <44>;
                                clocks = <&soc_clocks MMP2_CLK_USB>;
                                clock-names = "USBCLK";
-                               phys = <&usb_otg_phy0>;
+                               phys = <&usb_phy0>;
                                phy-names = "usb";
                                status = "disabled";
                        };
                                interrupts = <54>;
                                status = "disabled";
                        };
+
+                       camera0: camera@d420a000 {
+                               compatible = "marvell,mmp2-ccic";
+                               reg = <0xd420a000 0x800>;
+                               interrupts = <42>;
+                               clocks = <&soc_clocks MMP2_CLK_CCIC0>;
+                               clock-names = "axi";
+                               #clock-cells = <0>;
+                               clock-output-names = "mclk";
+                               status = "disabled";
+                       };
+
+                       camera1: camera@d420a800 {
+                               compatible = "marvell,mmp2-ccic";
+                               reg = <0xd420a800 0x800>;
+                               interrupts = <30>;
+                               clocks = <&soc_clocks MMP2_CLK_CCIC1>;
+                               clock-names = "axi";
+                               #clock-cells = <0>;
+                               clock-output-names = "mclk";
+                               status = "disabled";
+                       };
                };
 
                apb@d4000000 {  /* APB */
                                interrupts = <27>;
                                clocks = <&soc_clocks MMP2_CLK_UART0>;
                                resets = <&soc_clocks MMP2_CLK_UART0>;
+                               reg-shift = <2>;
                                status = "disabled";
                        };
 
                                interrupts = <28>;
                                clocks = <&soc_clocks MMP2_CLK_UART1>;
                                resets = <&soc_clocks MMP2_CLK_UART1>;
+                               reg-shift = <2>;
                                status = "disabled";
                        };
 
                                interrupts = <24>;
                                clocks = <&soc_clocks MMP2_CLK_UART2>;
                                resets = <&soc_clocks MMP2_CLK_UART2>;
+                               reg-shift = <2>;
                                status = "disabled";
                        };
 
                                interrupts = <46>;
                                clocks = <&soc_clocks MMP2_CLK_UART3>;
                                resets = <&soc_clocks MMP2_CLK_UART3>;
+                               reg-shift = <2>;
                                status = "disabled";
                        };
 
                                status = "disabled";
                        };
 
-                       ssp1: ssp@d4035000 {
+                       ssp1: spi@d4035000 {
                                compatible = "marvell,mmp2-ssp";
                                reg = <0xd4035000 0x1000>;
                                clocks = <&soc_clocks MMP2_CLK_SSP0>;
                                interrupts = <0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
-                       ssp2: ssp@d4036000 {
+                       ssp2: spi@d4036000 {
                                compatible = "marvell,mmp2-ssp";
                                reg = <0xd4036000 0x1000>;
                                clocks = <&soc_clocks MMP2_CLK_SSP1>;
                                interrupts = <1>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
-                       ssp3: ssp@d4037000 {
+                       ssp3: spi@d4037000 {
                                compatible = "marvell,mmp2-ssp";
                                reg = <0xd4037000 0x1000>;
                                clocks = <&soc_clocks MMP2_CLK_SSP2>;
                                interrupts = <20>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
 
-                       ssp4: ssp@d4039000 {
+                       ssp4: spi@d4039000 {
                                compatible = "marvell,mmp2-ssp";
                                reg = <0xd4039000 0x1000>;
                                clocks = <&soc_clocks MMP2_CLK_SSP3>;
                                interrupts = <21>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
                                status = "disabled";
                        };
                };
 
-               soc_clocks: clocks{
+               soc_clocks: clocks {
                        compatible = "marvell,mmp2-clock";
                        reg = <0xd4050000 0x1000>,
                              <0xd4282800 0x400>,
index f572a477f74ca2a5c7d1538d9582fc6fc5202917..7b09cbee8bb8b515387c6f787c97324d0b410f98 100644 (file)
                                interrupts = <18>;
                        };
                };
+
+               /*
+                * On omap34xx the OCP registers do not seem to be accessible
+                * at all unlike on 36xx. Maybe SGX is permanently set to
+                * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
+                * write-only at 0x50000e10. We detect SGX based on the SGX
+                * revision register instead of the unreadable OCP revision
+                * register. Also note that on early 34xx es1 revision there
+                * are also different clocks, but we do not have any dts users
+                * for it.
+                */
+               sgx_module: target-module@50000000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x50000014 0x4>;
+                       reg-names = "rev";
+                       clocks = <&sgx_fck>, <&sgx_ick>;
+                       clock-names = "fck", "ick";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x50000000 0x4000>;
+
+                       /*
+                        * Closed source PowerVR driver, no child device
+                        * binding or driver in mainline
+                        */
+               };
        };
 
        thermal_zones: thermal-zones {
index 6fb23ada1f64dea9e6ad91701c78a5c2a50725d2..1e552f08f120ed2b1fc3966e9dec2aca83b783d3 100644 (file)
                                interrupts = <18>;
                        };
                };
+
+               /*
+                * Note that the sysconfig register layout is a subset of the
+                * "ti,sysc-omap4" type register with just sidle and midle bits
+                * available while omap34xx has "ti,sysc-omap2" type sysconfig.
+                */
+               sgx_module: target-module@50000000 {
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       reg = <0x5000fe00 0x4>,
+                             <0x5000fe10 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       clocks = <&sgx_fck>, <&sgx_ick>;
+                       clock-names = "fck", "ick";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x50000000 0x2000000>;
+
+                       /*
+                        * Closed source PowerVR driver, no child device
+                        * binding or driver in mainline
+                        */
+               };
        };
 
        thermal_zones: thermal-zones {
index 67072df39bc7453eaf2d182bc6190d05b8c2a3a7..8e6662bb9e837f48b1c39880162f1d4310ca11ae 100644 (file)
 
                target-module@30000 {                   /* 0x40130000, ap 14 0e.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "wd_timer3";
                        reg = <0x30000 0x4>,
                              <0x30010 0x4>,
                              <0x30014 0x4>;
index bea05dc4ef0f96ce3ae8c596b2392ac8d95129da..d60d5e0ecc4c14b69abc29224f6bd70b7363f1c6 100644 (file)
                        };
                };
 
+               /* d2d mdm */
                target-module@36000 {                   /* 0x4a0b6000, ap 69 60.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x36000 0x4>,
+                             <0x36010 0x4>,
+                             <0x36014 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,syss-mask = <1>;
+                       /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
+                       clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
+                       clock-names = "fck";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x0 0x36000 0x1000>;
                };
 
+               /* d2d mpu */
                target-module@4d000 {                   /* 0x4a0cd000, ap 78 58.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x4d000 0x4>,
+                             <0x4d010 0x4>,
+                             <0x4d014 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,syss-mask = <1>;
+                       /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
+                       clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
+                       clock-names = "fck";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x0 0x4d000 0x1000>;
 
                target-module@4000 {                    /* 0x4a314000, ap 7 18.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "wd_timer2";
                        reg = <0x4000 0x4>,
                              <0x4010 0x4>,
                              <0x4014 0x4>;
 
                target-module@60000 {                   /* 0x48060000, ap 25 1e.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c3";
                        reg = <0x60000 0x8>,
                              <0x60010 0x8>,
                              <0x60090 0x8>;
 
                target-module@70000 {                   /* 0x48070000, ap 32 28.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c1";
                        reg = <0x70000 0x8>,
                              <0x70010 0x8>,
                              <0x70090 0x8>;
 
                target-module@72000 {                   /* 0x48072000, ap 34 30.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c2";
                        reg = <0x72000 0x8>,
                              <0x72010 0x8>,
                              <0x72090 0x8>;
 
                target-module@150000 {                  /* 0x48350000, ap 77 4c.0 */
                        compatible = "ti,sysc-omap2", "ti,sysc";
-                       ti,hwmods = "i2c4";
                        reg = <0x150000 0x8>,
                              <0x150010 0x8>,
                              <0x150090 0x8>;
index c43e52fd5f65cf144bf61b396249f42ecfb12565..7cc95bc1598b6f88b774f7ff7ad3dd58daa36466 100644 (file)
 
                target-module@56000000 {
                        compatible = "ti,sysc-omap4", "ti,sysc";
-                       ti,hwmods = "gpu";
                        reg = <0x5601fc00 0x4>,
                              <0x5601fc10 0x4>;
                        reg-names = "rev", "sysc";
index edfd26c0346218746cc69b5dd473954bcbcecd54..1fb7937638f07890c55a7608e3a7599632e5d9b7 100644 (file)
                        ports-implemented = <0x1>;
                };
 
+               target-module@56000000 {
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       reg = <0x5600fe00 0x4>,
+                             <0x5600fe10 0x4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x56000000 0x2000000>;
+
+                       /*
+                        * Closed source PowerVR driver, no child device
+                        * binding or driver in mainline
+                        */
+               };
+
                dss: dss@58000000 {
                        compatible = "ti,omap5-dss";
                        reg = <0x58000000 0x80>;
index 33e8dd905bff7d3658d6b82df57a254f06435379..fac2e57dcca905e6dd8af4bebcb57d89aa727805 100644 (file)
                };
        };
 
+       gpu_cm: clock-controller@1500 {
+               compatible = "ti,omap4-cm";
+               reg = <0x1500 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x1500 0x100>;
+
+               gpu_clkctrl: clk@20 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x20 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
        l3init_cm: l3init_cm@1600 {
                compatible = "ti,omap4-cm";
                reg = <0x1600 0x100>;
index f83786640f94205da1432b056759dd74c1cd2cc7..9dab1f50a02f83c35d6beaed5769cbace59485b4 100644 (file)
@@ -19,6 +19,7 @@ menuconfig ARCH_EXYNOS
        select EXYNOS_SROM
        select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
        select GPIOLIB
+       select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 && VIRTUALIZATION
        select HAVE_ARM_SCU if SMP
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
index aaa6092426ea2b9d3c25ed584607de67b4b2325b..3de3d7a115b3a6c45b0735feef1440057df5df84 100644 (file)
@@ -30,7 +30,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
 extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
 extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
 extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
-extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
@@ -72,8 +71,6 @@ extern struct omap_hwmod am33xx_rng_hwmod;
 extern struct omap_hwmod am33xx_ocmcram_hwmod;
 extern struct omap_hwmod am33xx_smartreflex0_hwmod;
 extern struct omap_hwmod am33xx_smartreflex1_hwmod;
-extern struct omap_hwmod am33xx_cpgmac0_hwmod;
-extern struct omap_hwmod am33xx_mdio_hwmod;
 extern struct omap_hwmod am33xx_dcan0_hwmod;
 extern struct omap_hwmod am33xx_dcan1_hwmod;
 extern struct omap_hwmod am33xx_elm_hwmod;
index 47a0e301b193f598d3b9f6b9438626552cee0b69..63698ffa6d27d72b89cdb23c5c43871f23c1688c 100644 (file)
@@ -122,12 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
-       .master         = &am33xx_cpgmac0_hwmod,
-       .slave          = &am33xx_mdio_hwmod,
-       .user           = OCP_USER_MPU,
-};
-
 struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_elm_hwmod,
index adb6271f819be0caa4ea0154e77b21ee5756782b..dd939e1325c64a4d1496c02465b18f225bd22b9b 100644 (file)
@@ -349,54 +349,6 @@ struct omap_hwmod_class am33xx_control_hwmod_class = {
        .name           = "control",
 };
 
-/*
- * 'cpgmac' class
- * cpsw/cpgmac sub system
- */
-static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
-       .rev_offs       = 0x0,
-       .sysc_offs      = 0x8,
-       .syss_offs      = 0x4,
-       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-                          SYSS_HAS_RESET_STATUS),
-       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
-                          MSTANDBY_NO),
-       .sysc_fields    = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
-       .name           = "cpgmac0",
-       .sysc           = &am33xx_cpgmac_sysc,
-};
-
-struct omap_hwmod am33xx_cpgmac0_hwmod = {
-       .name           = "cpgmac0",
-       .class          = &am33xx_cpgmac0_hwmod_class,
-       .clkdm_name     = "cpsw_125mhz_clkdm",
-       .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-       .main_clk       = "cpsw_125mhz_gclk",
-       .mpu_rt_idx     = 1,
-       .prcm           = {
-               .omap4  = {
-                       .modulemode     = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/*
- * mdio class
- */
-static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
-       .name           = "davinci_mdio",
-};
-
-struct omap_hwmod am33xx_mdio_hwmod = {
-       .name           = "davinci_mdio",
-       .class          = &am33xx_mdio_hwmod_class,
-       .clkdm_name     = "cpsw_125mhz_clkdm",
-       .main_clk       = "cpsw_125mhz_gclk",
-};
-
 /*
  * dcan class
  */
@@ -1072,7 +1024,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
        CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
-       CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
@@ -1134,7 +1085,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
        CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
-       CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
index c965af275e34148668d4f99adbefd99a26dd466b..2bcb6345b8735bc75accd0b82f4c3d2e63919570 100644 (file)
@@ -372,13 +372,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
        .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
-       .master         = &am33xx_l4_hs_hwmod,
-       .slave          = &am33xx_cpgmac0_hwmod,
-       .clk            = "cpsw_125mhz_gclk",
-       .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
        .master         = &am33xx_l3_main_hwmod,
        .slave          = &am33xx_lcdc_hwmod,
@@ -462,8 +455,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l3_main__tptc2,
        &am33xx_l3_main__ocmc,
        &am33xx_l3_s__usbss,
-       &am33xx_l4_hs__cpgmac0,
-       &am33xx_cpgmac0__mdio,
        &am33xx_l3_main__sha0,
        &am33xx_l3_main__aes0,
        &am33xx_l4_per__rng,
index 69571abc14fd063192d445fdd69f5142d5cf7fbd..5c3db6b6438bc34c6aa90d12d89e7914f46b2497 100644 (file)
@@ -597,13 +597,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
        .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
-       .master         = &am43xx_l4_hs_hwmod,
-       .slave          = &am33xx_cpgmac0_hwmod,
-       .clk            = "cpsw_125mhz_gclk",
-       .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_timer1_hwmod,
@@ -859,8 +852,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l3_main__tptc1,
        &am33xx_l3_main__tptc2,
        &am33xx_l3_main__ocmc,
-       &am43xx_l4_hs__cpgmac0,
-       &am33xx_cpgmac0__mdio,
        &am33xx_l3_main__sha0,
        &am33xx_l3_main__aes0,
        &am43xx_l3_main__des,
index a6f2a10cdc3e47881d6184858f13f853539ff60d..28ea2960a9b28cfc453b10770018c93d89e4100e 100644 (file)
@@ -28,7 +28,6 @@
 #include "cm2_44xx.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
-#include "wd_timer.h"
 
 /* Base offset for all OMAP4 interrupts external to MPUSS */
 #define OMAP44XX_IRQ_GIC_START 32
@@ -275,29 +274,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
        },
 };
 
-/*
- * 'c2c' class
- * chip 2 chip interface used to plug the ape soc (omap) with an external modem
- * soc
- */
-
-static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
-       .name   = "c2c",
-};
-
-/* c2c */
-static struct omap_hwmod omap44xx_c2c_hwmod = {
-       .name           = "c2c",
-       .class          = &omap44xx_c2c_hwmod_class,
-       .clkdm_name     = "d2d_clkdm",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
-                       .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
-               },
-       },
-};
-
 /*
  * 'counter' class
  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
@@ -1085,41 +1061,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
        },
 };
 
-/*
- * 'gpu' class
- * 2d/3d graphics accelerator
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
-       .rev_offs       = 0x1fc00,
-       .sysc_offs      = 0x1fc10,
-       .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
-       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                          MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-       .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
-       .name   = "gpu",
-       .sysc   = &omap44xx_gpu_sysc,
-};
-
-/* gpu */
-static struct omap_hwmod omap44xx_gpu_hwmod = {
-       .name           = "gpu",
-       .class          = &omap44xx_gpu_hwmod_class,
-       .clkdm_name     = "l3_gfx_clkdm",
-       .main_clk       = "sgx_clk_mux",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
-                       .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
 /*
  * 'hdq1w' class
  * hdq / 1-wire serial interface controller
@@ -2433,61 +2374,6 @@ static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
        },
 };
 
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
-       .rev_offs       = 0x0000,
-       .sysc_offs      = 0x0010,
-       .syss_offs      = 0x0014,
-       .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-       .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
-       .name           = "wd_timer",
-       .sysc           = &omap44xx_wd_timer_sysc,
-       .pre_shutdown   = &omap2_wd_timer_disable,
-       .reset          = &omap2_wd_timer_reset,
-};
-
-/* wd_timer2 */
-static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
-       .name           = "wd_timer2",
-       .class          = &omap44xx_wd_timer_hwmod_class,
-       .clkdm_name     = "l4_wkup_clkdm",
-       .main_clk       = "sys_32k_ck",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
-                       .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/* wd_timer3 */
-static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
-       .name           = "wd_timer3",
-       .class          = &omap44xx_wd_timer_hwmod_class,
-       .clkdm_name     = "abe_clkdm",
-       .main_clk       = "sys_32k_ck",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
-                       .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-
 /*
  * interfaces
  */
@@ -2596,14 +2482,6 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* gpu -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
-       .master         = &omap44xx_gpu_hwmod,
-       .slave          = &omap44xx_l3_main_2_hwmod,
-       .clk            = "l3_div_ck",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* hsi -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
        .master         = &omap44xx_hsi_hwmod,
@@ -2788,14 +2666,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
        .user           = OCP_USER_SDMA,
 };
 
-/* l3_main_2 -> c2c */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
-       .master         = &omap44xx_l3_main_2_hwmod,
-       .slave          = &omap44xx_c2c_hwmod,
-       .clk            = "l3_div_ck",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_wkup -> counter_32k */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
        .master         = &omap44xx_l4_wkup_hwmod,
@@ -3028,14 +2898,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3_main_2 -> gpu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
-       .master         = &omap44xx_l3_main_2_hwmod,
-       .slave          = &omap44xx_gpu_hwmod,
-       .clk            = "l3_div_ck",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_per -> hdq1w */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
        .master         = &omap44xx_l4_per_hwmod,
@@ -3396,30 +3258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
-       .master         = &omap44xx_l4_wkup_hwmod,
-       .slave          = &omap44xx_wd_timer2_hwmod,
-       .clk            = "l4_wkup_clk_mux_ck",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> wd_timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
-       .master         = &omap44xx_l4_abe_hwmod,
-       .slave          = &omap44xx_wd_timer3_hwmod,
-       .clk            = "ocp_abe_iclk",
-       .user           = OCP_USER_MPU,
-};
-
-/* l4_abe -> wd_timer3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
-       .master         = &omap44xx_l4_abe_hwmod,
-       .slave          = &omap44xx_wd_timer3_hwmod,
-       .clk            = "ocp_abe_iclk",
-       .user           = OCP_USER_SDMA,
-};
-
 /* mpu -> emif1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
        .master         = &omap44xx_mpu_hwmod,
@@ -3450,7 +3288,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_debugss__l3_main_2,
        &omap44xx_dma_system__l3_main_2,
        &omap44xx_fdif__l3_main_2,
-       &omap44xx_gpu__l3_main_2,
        &omap44xx_hsi__l3_main_2,
        &omap44xx_ipu__l3_main_2,
        &omap44xx_iss__l3_main_2,
@@ -3474,7 +3311,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_cfg__ocp_wp_noc,
        &omap44xx_l4_abe__aess,
        &omap44xx_l4_abe__aess_dma,
-       &omap44xx_l3_main_2__c2c,
        &omap44xx_l4_wkup__counter_32k,
        &omap44xx_l4_cfg__ctrl_module_core,
        &omap44xx_l4_cfg__ctrl_module_pad_core,
@@ -3503,7 +3339,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_per__elm,
        &omap44xx_l4_cfg__fdif,
        &omap44xx_l3_main_2__gpmc,
-       &omap44xx_l3_main_2__gpu,
        &omap44xx_l4_per__hdq1w,
        &omap44xx_l4_cfg__hsi,
        &omap44xx_l3_main_2__ipu,
@@ -3551,9 +3386,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_cfg__usb_host_hs,
        &omap44xx_l4_cfg__usb_otg_hs,
        &omap44xx_l4_cfg__usb_tll_hs,
-       &omap44xx_l4_wkup__wd_timer2,
-       &omap44xx_l4_abe__wd_timer3,
-       &omap44xx_l4_abe__wd_timer3_dma,
        &omap44xx_mpu__emif1,
        &omap44xx_mpu__emif2,
        &omap44xx_l3_main_2__aes1,
index 1ec21e9ba1e99aa565f1a70c8978f7ef58457f12..e5bd549d2a5e7f308ef21866a3384538276127da 100644 (file)
@@ -284,56 +284,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
        },
 };
 
-/*
- * 'gmac' class
- * cpsw/gmac sub system
- */
-static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
-       .rev_offs       = 0x0,
-       .sysc_offs      = 0x8,
-       .syss_offs      = 0x4,
-       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-                          SYSS_HAS_RESET_STATUS),
-       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
-                          MSTANDBY_NO),
-       .sysc_fields    = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
-       .name           = "gmac",
-       .sysc           = &dra7xx_gmac_sysc,
-};
-
-static struct omap_hwmod dra7xx_gmac_hwmod = {
-       .name           = "gmac",
-       .class          = &dra7xx_gmac_hwmod_class,
-       .clkdm_name     = "gmac_clkdm",
-       .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-       .main_clk       = "dpll_gmac_ck",
-       .mpu_rt_idx     = 1,
-       .prcm           = {
-               .omap4  = {
-                       .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
-                       .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
-                       .modulemode     = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/*
- * 'mdio' class
- */
-static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
-       .name           = "davinci_mdio",
-};
-
-static struct omap_hwmod dra7xx_mdio_hwmod = {
-       .name           = "davinci_mdio",
-       .class          = &dra7xx_mdio_hwmod_class,
-       .clkdm_name     = "gmac_clkdm",
-       .main_clk       = "dpll_gmac_ck",
-};
-
 /*
  * 'dcan' class
  *
@@ -1046,281 +996,6 @@ static struct omap_hwmod dra7xx_mailbox13_hwmod = {
        },
 };
 
-/*
- * 'mcspi' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
-       .rev_offs       = 0x0000,
-       .sysc_offs      = 0x0010,
-       .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
-                          SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-       .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
-       .name   = "mcspi",
-       .sysc   = &dra7xx_mcspi_sysc,
-};
-
-/* mcspi1 */
-static struct omap_hwmod dra7xx_mcspi1_hwmod = {
-       .name           = "mcspi1",
-       .class          = &dra7xx_mcspi_hwmod_class,
-       .clkdm_name     = "l4per_clkdm",
-       .main_clk       = "func_48m_fclk",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/* mcspi2 */
-static struct omap_hwmod dra7xx_mcspi2_hwmod = {
-       .name           = "mcspi2",
-       .class          = &dra7xx_mcspi_hwmod_class,
-       .clkdm_name     = "l4per_clkdm",
-       .main_clk       = "func_48m_fclk",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/* mcspi3 */
-static struct omap_hwmod dra7xx_mcspi3_hwmod = {
-       .name           = "mcspi3",
-       .class          = &dra7xx_mcspi_hwmod_class,
-       .clkdm_name     = "l4per_clkdm",
-       .main_clk       = "func_48m_fclk",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/* mcspi4 */
-static struct omap_hwmod dra7xx_mcspi4_hwmod = {
-       .name           = "mcspi4",
-       .class          = &dra7xx_mcspi_hwmod_class,
-       .clkdm_name     = "l4per_clkdm",
-       .main_clk       = "func_48m_fclk",
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-};
-
-/*
- * 'mcasp' class
- *
- */
-static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
-       .rev_offs       = 0,
-       .sysc_offs      = 0x0004,
-       .sysc_flags     = SYSC_HAS_SIDLEMODE,
-       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-       .sysc_fields    = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
-       .name   = "mcasp",
-       .sysc   = &dra7xx_mcasp_sysc,
-};
-
-/* mcasp1 */
-static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
-       { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp1_hwmod = {
-       .name           = "mcasp1",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "ipu_clkdm",
-       .main_clk       = "mcasp1_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp1_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
-};
-
-/* mcasp2 */
-static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
-       { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp2_hwmod = {
-       .name           = "mcasp2",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp2_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp2_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
-};
-
-/* mcasp3 */
-static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp3_hwmod = {
-       .name           = "mcasp3",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp3_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp3_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
-};
-
-/* mcasp4 */
-static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp4_hwmod = {
-       .name           = "mcasp4",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp4_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp4_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
-};
-
-/* mcasp5 */
-static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp5_hwmod = {
-       .name           = "mcasp5",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp5_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp5_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
-};
-
-/* mcasp6 */
-static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp6_hwmod = {
-       .name           = "mcasp6",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp6_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp6_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
-};
-
-/* mcasp7 */
-static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp7_hwmod = {
-       .name           = "mcasp7",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp7_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp7_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
-};
-
-/* mcasp8 */
-static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
-       { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
-};
-
-static struct omap_hwmod dra7xx_mcasp8_hwmod = {
-       .name           = "mcasp8",
-       .class          = &dra7xx_mcasp_hwmod_class,
-       .clkdm_name     = "l4per2_clkdm",
-       .main_clk       = "mcasp8_aux_gfclk_mux",
-       .flags          = HWMOD_OPT_CLKS_NEEDED,
-       .prcm = {
-               .omap4 = {
-                       .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
-                       .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
-                       .modulemode   = MODULEMODE_SWCTRL,
-               },
-       },
-       .opt_clks       = mcasp8_opt_clks,
-       .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
-};
-
 /*
  * 'mpu' class
  *
@@ -2303,19 +1978,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_gmac_hwmod,
-       .clk            = "dpll_gmac_ck",
-       .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
-       .master         = &dra7xx_gmac_hwmod,
-       .slave          = &dra7xx_mdio_hwmod,
-       .user           = OCP_USER_MPU,
-};
-
 /* l4_wkup -> dcan1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
        .master         = &dra7xx_l4_wkup_hwmod,
@@ -2412,94 +2074,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per2 -> mcasp1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp1_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> mcasp1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
-       .master         = &dra7xx_l3_main_1_hwmod,
-       .slave          = &dra7xx_mcasp1_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp2_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> mcasp2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
-       .master         = &dra7xx_l3_main_1_hwmod,
-       .slave          = &dra7xx_mcasp2_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp3_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> mcasp3 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
-       .master         = &dra7xx_l3_main_1_hwmod,
-       .slave          = &dra7xx_mcasp3_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp4_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp5_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp6_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp7_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> mcasp8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
-       .master         = &dra7xx_l4_per2_hwmod,
-       .slave          = &dra7xx_mcasp8_hwmod,
-       .clk            = "l4_root_clk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_per1 -> elm */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
        .master         = &dra7xx_l4_per1_hwmod,
@@ -2628,38 +2202,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per1 -> mcspi1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
-       .master         = &dra7xx_l4_per1_hwmod,
-       .slave          = &dra7xx_mcspi1_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> mcspi2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
-       .master         = &dra7xx_l4_per1_hwmod,
-       .slave          = &dra7xx_mcspi2_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> mcspi3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
-       .master         = &dra7xx_l4_per1_hwmod,
-       .slave          = &dra7xx_mcspi3_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> mcspi4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
-       .master         = &dra7xx_l4_per1_hwmod,
-       .slave          = &dra7xx_mcspi4_hwmod,
-       .clk            = "l3_iclk_div",
-       .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_cfg -> mpu */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
        .master         = &dra7xx_l4_cfg_hwmod,
@@ -3021,19 +2563,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_wkup__ctrl_module_wkup,
        &dra7xx_l4_wkup__dcan1,
        &dra7xx_l4_per2__dcan2,
-       &dra7xx_l4_per2__cpgmac0,
-       &dra7xx_l4_per2__mcasp1,
-       &dra7xx_l3_main_1__mcasp1,
-       &dra7xx_l4_per2__mcasp2,
-       &dra7xx_l3_main_1__mcasp2,
-       &dra7xx_l4_per2__mcasp3,
-       &dra7xx_l3_main_1__mcasp3,
-       &dra7xx_l4_per2__mcasp4,
-       &dra7xx_l4_per2__mcasp5,
-       &dra7xx_l4_per2__mcasp6,
-       &dra7xx_l4_per2__mcasp7,
-       &dra7xx_l4_per2__mcasp8,
-       &dra7xx_gmac__mdio,
        &dra7xx_l4_cfg__dma_system,
        &dra7xx_l3_main_1__tpcc,
        &dra7xx_l3_main_1__tptc0,
@@ -3060,10 +2589,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_per3__mailbox11,
        &dra7xx_l4_per3__mailbox12,
        &dra7xx_l4_per3__mailbox13,
-       &dra7xx_l4_per1__mcspi1,
-       &dra7xx_l4_per1__mcspi2,
-       &dra7xx_l4_per1__mcspi3,
-       &dra7xx_l4_per1__mcspi4,
        &dra7xx_l4_cfg__mpu,
        &dra7xx_l4_cfg__ocp2scp1,
        &dra7xx_l4_cfg__ocp2scp3,
index ce42cc640a61a32b66ad84fdb8e2f82af976f4ef..71d85ff323f73d0e13d98ad5803287c1aba38e18 100644 (file)
@@ -62,6 +62,7 @@ void samsung_wdt_reset(void)
 #ifdef CONFIG_OF
 static const struct of_device_id s3c2410_wdt_match[] = {
        { .compatible = "samsung,s3c2410-wdt" },
+       { .compatible = "samsung,s3c6410-wdt" },
        {},
 };
 
index caed4334f27deaa0c79f0853e9142a5fe544c68d..243338c914a4f580d133bca5ae0815538853e876 100644 (file)
@@ -2,6 +2,7 @@
 # Mvebu SoC Family
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
new file mode 100644 (file)
index 0000000..d105986
--- /dev/null
@@ -0,0 +1,840 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for CZ.NIC Turris Mox Board
+ * 2019 by Marek Behun <marek.behun@nic.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/bus/moxtet.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-372x.dtsi"
+
+/ {
+       model = "CZ.NIC Turris Mox Board";
+       compatible = "cznic,turris-mox", "marvell,armada3720",
+                    "marvell,armada3710";
+
+       aliases {
+               spi0 = &spi0;
+               ethernet1 = &eth1;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               red {
+                       label = "mox:red:activity";
+                       gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "default-on";
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               reset {
+                       label = "reset";
+                       linux,code = <KEY_RESTART>;
+                       gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
+                       debounce-interval = <60>;
+               };
+       };
+
+       exp_usb3_vbus: usb3-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb3-vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               enable-active-high;
+               regulator-always-on;
+               gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
+       };
+
+       usb3_phy: usb3-phy {
+               compatible = "usb-nop-xceiv";
+               vcc-supply = <&exp_usb3_vbus>;
+       };
+
+       vsdc_reg: vsdc-reg {
+               compatible = "regulator-gpio";
+               regulator-name = "vsdc";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+
+               gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+               gpios-states = <0>;
+               states = <1800000 0x1
+                         3300000 0x0>;
+               enable-active-high;
+       };
+
+       vsdio_reg: vsdio-reg {
+               compatible = "regulator-gpio";
+               regulator-name = "vsdio";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+
+               gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
+               gpios-states = <0>;
+               states = <1800000 0x1
+                         3300000 0x0>;
+               enable-active-high;
+       };
+
+       sdhci1_pwrseq: sdhci1-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
+               status = "okay";
+       };
+
+       sfp: sfp {
+               compatible = "sff,sfp+";
+               i2c-bus = <&i2c0>;
+               los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
+               rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
+
+               /* enabled by U-Boot if SFP module is present */
+               status = "disabled";
+       };
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
+       clock-frequency = <100000>;
+       status = "okay";
+
+       rtc@6f {
+               compatible = "microchip,mcp7940x";
+               reg = <0x6f>;
+       };
+};
+
+&pcie_reset_pins {
+       function = "gpio";
+};
+
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+       status = "okay";
+       max-link-speed = <2>;
+       reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+       phys = <&comphy1 0>;
+
+       /* enabled by U-Boot if PCIe module is present */
+       status = "disabled";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&eth0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>;
+       phy-mode = "rgmii-id";
+       phy = <&phy1>;
+       status = "okay";
+};
+
+&eth1 {
+       phy-mode = "2500base-x";
+       managed = "in-band-status";
+       phys = <&comphy0 1>;
+};
+
+&sdhci0 {
+       wp-inverted;
+       bus-width = <4>;
+       cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
+       vqmmc-supply = <&vsdc_reg>;
+       marvell,pad-type = "sd";
+       status = "okay";
+};
+
+&sdhci1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdio_pins>;
+       non-removable;
+       bus-width = <4>;
+       marvell,pad-type = "sd";
+       vqmmc-supply = <&vsdio_reg>;
+       mmc-pwrseq = <&sdhci1_pwrseq>;
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
+       assigned-clocks = <&nb_periph_clk 7>;
+       assigned-clock-parents = <&tbg 1>;
+       assigned-clock-rates = <20000000>;
+
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <20000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "secure-firmware";
+                               reg = <0x0 0x20000>;
+                       };
+
+                       partition@20000 {
+                               label = "u-boot";
+                               reg = <0x20000 0x160000>;
+                       };
+
+                       partition@180000 {
+                               label = "u-boot-env";
+                               reg = <0x180000 0x10000>;
+                       };
+
+                       partition@190000 {
+                               label = "Rescue system";
+                               reg = <0x190000 0x660000>;
+                       };
+
+                       partition@7f0000 {
+                               label = "dtb";
+                               reg = <0x7f0000 0x10000>;
+                       };
+               };
+       };
+
+       moxtet: moxtet@1 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "cznic,moxtet";
+               reg = <1>;
+               reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+               spi-max-frequency = <10000000>;
+               spi-cpol;
+               spi-cpha;
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               interrupt-parent = <&gpiosb>;
+               interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+               status = "okay";
+
+               moxtet_sfp: gpio@0 {
+                       compatible = "cznic,moxtet-gpio";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0>;
+                       status = "disabled";
+               };
+       };
+};
+
+&usb2 {
+       status = "okay";
+};
+
+&usb3 {
+       status = "okay";
+       phys = <&comphy2 0>;
+       usb-phy = <&usb3_phy>;
+};
+
+&mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&smi_pins>;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+
+       /* switch nodes are enabled by U-Boot if modules are present */
+       switch0@10 {
+               compatible = "marvell,mv88e6190";
+               reg = <0x10 0>;
+               dsa,member = <0 0>;
+               interrupt-parent = <&moxtet>;
+               interrupts = <MOXTET_IRQ_PERIDOT(0)>;
+               status = "disabled";
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       switch0phy1: switch0phy1@1 {
+                               reg = <0x1>;
+                       };
+
+                       switch0phy2: switch0phy2@2 {
+                               reg = <0x2>;
+                       };
+
+                       switch0phy3: switch0phy3@3 {
+                               reg = <0x3>;
+                       };
+
+                       switch0phy4: switch0phy4@4 {
+                               reg = <0x4>;
+                       };
+
+                       switch0phy5: switch0phy5@5 {
+                               reg = <0x5>;
+                       };
+
+                       switch0phy6: switch0phy6@6 {
+                               reg = <0x6>;
+                       };
+
+                       switch0phy7: switch0phy7@7 {
+                               reg = <0x7>;
+                       };
+
+                       switch0phy8: switch0phy8@8 {
+                               reg = <0x8>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <0x1>;
+                               label = "lan1";
+                               phy-handle = <&switch0phy1>;
+                       };
+
+                       port@2 {
+                               reg = <0x2>;
+                               label = "lan2";
+                               phy-handle = <&switch0phy2>;
+                       };
+
+                       port@3 {
+                               reg = <0x3>;
+                               label = "lan3";
+                               phy-handle = <&switch0phy3>;
+                       };
+
+                       port@4 {
+                               reg = <0x4>;
+                               label = "lan4";
+                               phy-handle = <&switch0phy4>;
+                       };
+
+                       port@5 {
+                               reg = <0x5>;
+                               label = "lan5";
+                               phy-handle = <&switch0phy5>;
+                       };
+
+                       port@6 {
+                               reg = <0x6>;
+                               label = "lan6";
+                               phy-handle = <&switch0phy6>;
+                       };
+
+                       port@7 {
+                               reg = <0x7>;
+                               label = "lan7";
+                               phy-handle = <&switch0phy7>;
+                       };
+
+                       port@8 {
+                               reg = <0x8>;
+                               label = "lan8";
+                               phy-handle = <&switch0phy8>;
+                       };
+
+                       port@9 {
+                               reg = <0x9>;
+                               label = "cpu";
+                               ethernet = <&eth1>;
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                       };
+
+                       switch0port10: port@a {
+                               reg = <0xa>;
+                               label = "dsa";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               link = <&switch1port9 &switch2port9>;
+                               status = "disabled";
+                       };
+
+                       port-sfp@a {
+                               reg = <0xa>;
+                               label = "sfp";
+                               sfp = <&sfp>;
+                               phy-mode = "sgmii";
+                               managed = "in-band-status";
+                               status = "disabled";
+                       };
+               };
+       };
+
+       switch0@2 {
+               compatible = "marvell,mv88e6085";
+               reg = <0x2 0>;
+               dsa,member = <0 0>;
+               interrupt-parent = <&moxtet>;
+               interrupts = <MOXTET_IRQ_TOPAZ>;
+               status = "disabled";
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       switch0phy1_topaz: switch0phy1@11 {
+                               reg = <0x11>;
+                       };
+
+                       switch0phy2_topaz: switch0phy2@12 {
+                               reg = <0x12>;
+                       };
+
+                       switch0phy3_topaz: switch0phy3@13 {
+                               reg = <0x13>;
+                       };
+
+                       switch0phy4_topaz: switch0phy4@14 {
+                               reg = <0x14>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <0x1>;
+                               label = "lan1";
+                               phy-handle = <&switch0phy1_topaz>;
+                       };
+
+                       port@2 {
+                               reg = <0x2>;
+                               label = "lan2";
+                               phy-handle = <&switch0phy2_topaz>;
+                       };
+
+                       port@3 {
+                               reg = <0x3>;
+                               label = "lan3";
+                               phy-handle = <&switch0phy3_topaz>;
+                       };
+
+                       port@4 {
+                               reg = <0x4>;
+                               label = "lan4";
+                               phy-handle = <&switch0phy4_topaz>;
+                       };
+
+                       port@5 {
+                               reg = <0x5>;
+                               label = "cpu";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               ethernet = <&eth1>;
+                       };
+               };
+       };
+
+       switch1@11 {
+               compatible = "marvell,mv88e6190";
+               reg = <0x11 0>;
+               dsa,member = <0 1>;
+               interrupt-parent = <&moxtet>;
+               interrupts = <MOXTET_IRQ_PERIDOT(1)>;
+               status = "disabled";
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       switch1phy1: switch1phy1@1 {
+                               reg = <0x1>;
+                       };
+
+                       switch1phy2: switch1phy2@2 {
+                               reg = <0x2>;
+                       };
+
+                       switch1phy3: switch1phy3@3 {
+                               reg = <0x3>;
+                       };
+
+                       switch1phy4: switch1phy4@4 {
+                               reg = <0x4>;
+                       };
+
+                       switch1phy5: switch1phy5@5 {
+                               reg = <0x5>;
+                       };
+
+                       switch1phy6: switch1phy6@6 {
+                               reg = <0x6>;
+                       };
+
+                       switch1phy7: switch1phy7@7 {
+                               reg = <0x7>;
+                       };
+
+                       switch1phy8: switch1phy8@8 {
+                               reg = <0x8>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <0x1>;
+                               label = "lan9";
+                               phy-handle = <&switch1phy1>;
+                       };
+
+                       port@2 {
+                               reg = <0x2>;
+                               label = "lan10";
+                               phy-handle = <&switch1phy2>;
+                       };
+
+                       port@3 {
+                               reg = <0x3>;
+                               label = "lan11";
+                               phy-handle = <&switch1phy3>;
+                       };
+
+                       port@4 {
+                               reg = <0x4>;
+                               label = "lan12";
+                               phy-handle = <&switch1phy4>;
+                       };
+
+                       port@5 {
+                               reg = <0x5>;
+                               label = "lan13";
+                               phy-handle = <&switch1phy5>;
+                       };
+
+                       port@6 {
+                               reg = <0x6>;
+                               label = "lan14";
+                               phy-handle = <&switch1phy6>;
+                       };
+
+                       port@7 {
+                               reg = <0x7>;
+                               label = "lan15";
+                               phy-handle = <&switch1phy7>;
+                       };
+
+                       port@8 {
+                               reg = <0x8>;
+                               label = "lan16";
+                               phy-handle = <&switch1phy8>;
+                       };
+
+                       switch1port9: port@9 {
+                               reg = <0x9>;
+                               label = "dsa";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               link = <&switch0port10>;
+                       };
+
+                       switch1port10: port@a {
+                               reg = <0xa>;
+                               label = "dsa";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               link = <&switch2port9>;
+                               status = "disabled";
+                       };
+
+                       port-sfp@a {
+                               reg = <0xa>;
+                               label = "sfp";
+                               sfp = <&sfp>;
+                               phy-mode = "sgmii";
+                               managed = "in-band-status";
+                               status = "disabled";
+                       };
+               };
+       };
+
+       switch1@2 {
+               compatible = "marvell,mv88e6085";
+               reg = <0x2 0>;
+               dsa,member = <0 1>;
+               interrupt-parent = <&moxtet>;
+               interrupts = <MOXTET_IRQ_TOPAZ>;
+               status = "disabled";
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       switch1phy1_topaz: switch1phy1@11 {
+                               reg = <0x11>;
+                       };
+
+                       switch1phy2_topaz: switch1phy2@12 {
+                               reg = <0x12>;
+                       };
+
+                       switch1phy3_topaz: switch1phy3@13 {
+                               reg = <0x13>;
+                       };
+
+                       switch1phy4_topaz: switch1phy4@14 {
+                               reg = <0x14>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <0x1>;
+                               label = "lan9";
+                               phy-handle = <&switch1phy1_topaz>;
+                       };
+
+                       port@2 {
+                               reg = <0x2>;
+                               label = "lan10";
+                               phy-handle = <&switch1phy2_topaz>;
+                       };
+
+                       port@3 {
+                               reg = <0x3>;
+                               label = "lan11";
+                               phy-handle = <&switch1phy3_topaz>;
+                       };
+
+                       port@4 {
+                               reg = <0x4>;
+                               label = "lan12";
+                               phy-handle = <&switch1phy4_topaz>;
+                       };
+
+                       port@5 {
+                               reg = <0x5>;
+                               label = "dsa";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               link = <&switch0port10>;
+                       };
+               };
+       };
+
+       switch2@12 {
+               compatible = "marvell,mv88e6190";
+               reg = <0x12 0>;
+               dsa,member = <0 2>;
+               interrupt-parent = <&moxtet>;
+               interrupts = <MOXTET_IRQ_PERIDOT(2)>;
+               status = "disabled";
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       switch2phy1: switch2phy1@1 {
+                               reg = <0x1>;
+                       };
+
+                       switch2phy2: switch2phy2@2 {
+                               reg = <0x2>;
+                       };
+
+                       switch2phy3: switch2phy3@3 {
+                               reg = <0x3>;
+                       };
+
+                       switch2phy4: switch2phy4@4 {
+                               reg = <0x4>;
+                       };
+
+                       switch2phy5: switch2phy5@5 {
+                               reg = <0x5>;
+                       };
+
+                       switch2phy6: switch2phy6@6 {
+                               reg = <0x6>;
+                       };
+
+                       switch2phy7: switch2phy7@7 {
+                               reg = <0x7>;
+                       };
+
+                       switch2phy8: switch2phy8@8 {
+                               reg = <0x8>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <0x1>;
+                               label = "lan17";
+                               phy-handle = <&switch2phy1>;
+                       };
+
+                       port@2 {
+                               reg = <0x2>;
+                               label = "lan18";
+                               phy-handle = <&switch2phy2>;
+                       };
+
+                       port@3 {
+                               reg = <0x3>;
+                               label = "lan19";
+                               phy-handle = <&switch2phy3>;
+                       };
+
+                       port@4 {
+                               reg = <0x4>;
+                               label = "lan20";
+                               phy-handle = <&switch2phy4>;
+                       };
+
+                       port@5 {
+                               reg = <0x5>;
+                               label = "lan21";
+                               phy-handle = <&switch2phy5>;
+                       };
+
+                       port@6 {
+                               reg = <0x6>;
+                               label = "lan22";
+                               phy-handle = <&switch2phy6>;
+                       };
+
+                       port@7 {
+                               reg = <0x7>;
+                               label = "lan23";
+                               phy-handle = <&switch2phy7>;
+                       };
+
+                       port@8 {
+                               reg = <0x8>;
+                               label = "lan24";
+                               phy-handle = <&switch2phy8>;
+                       };
+
+                       switch2port9: port@9 {
+                               reg = <0x9>;
+                               label = "dsa";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               link = <&switch1port10 &switch0port10>;
+                       };
+
+                       port-sfp@a {
+                               reg = <0xa>;
+                               label = "sfp";
+                               sfp = <&sfp>;
+                               phy-mode = "sgmii";
+                               managed = "in-band-status";
+                               status = "disabled";
+                       };
+               };
+       };
+
+       switch2@2 {
+               compatible = "marvell,mv88e6085";
+               reg = <0x2 0>;
+               dsa,member = <0 2>;
+               interrupt-parent = <&moxtet>;
+               interrupts = <MOXTET_IRQ_TOPAZ>;
+               status = "disabled";
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       switch2phy1_topaz: switch2phy1@11 {
+                               reg = <0x11>;
+                       };
+
+                       switch2phy2_topaz: switch2phy2@12 {
+                               reg = <0x12>;
+                       };
+
+                       switch2phy3_topaz: switch2phy3@13 {
+                               reg = <0x13>;
+                       };
+
+                       switch2phy4_topaz: switch2phy4@14 {
+                               reg = <0x14>;
+                       };
+               };
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <0x1>;
+                               label = "lan17";
+                               phy-handle = <&switch2phy1_topaz>;
+                       };
+
+                       port@2 {
+                               reg = <0x2>;
+                               label = "lan18";
+                               phy-handle = <&switch2phy2_topaz>;
+                       };
+
+                       port@3 {
+                               reg = <0x3>;
+                               label = "lan19";
+                               phy-handle = <&switch2phy3_topaz>;
+                       };
+
+                       port@4 {
+                               reg = <0x4>;
+                               label = "lan20";
+                               phy-handle = <&switch2phy4_topaz>;
+                       };
+
+                       port@5 {
+                               reg = <0x5>;
+                               label = "dsa";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               link = <&switch1port10 &switch0port10>;
+                       };
+               };
+       };
+};
index 7f69e3dfcb13ae85034c5210ad19740ed7d736ca..000c135e39b73cdc52edb211bf14cc1ebd68771e 100644 (file)
                                        function = "spi";
                                };
 
+                               spi_cs1_pins: spi-cs1-pins {
+                                       groups = "spi_cs1";
+                                       function = "spi";
+                               };
+
                                i2c1_pins: i2c1-pins {
                                        groups = "i2c1";
                                        function = "i2c";
index ca70ff73f171d9b0600b597deb77f8d86fd46941..799c75fa7981e2d55d65eb5ff3d453118cd04e0d 100644 (file)
@@ -42,7 +42,7 @@
                 */
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-               gic_its: gic-its@18200000 {
+               gic_its: gic-its@1820000 {
                        compatible = "arm,gic-v3-its";
                        reg = <0x00 0x01820000 0x00 0x10000>;
                        socionext,synquacer-pre-its = <0x1000000 0x400000>;
@@ -67,7 +67,7 @@
                reg = <0x0 0x900000 0x0 0x2000>;
                reg-names = "serdes";
                #phy-cells = <2>;
-               power-domains = <&k3_pds 153>;
+               power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
                clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
                assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
@@ -82,7 +82,7 @@
                reg = <0x0 0x910000 0x0 0x2000>;
                reg-names = "serdes";
                #phy-cells = <2>;
-               power-domains = <&k3_pds 154>;
+               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
                clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
                assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
                interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 146>;
+               power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
        };
 
        main_uart1: serial@2810000 {
                reg-io-width = <4>;
                interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
-               power-domains = <&k3_pds 147>;
+               power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
        };
 
        main_uart2: serial@2820000 {
                reg-io-width = <4>;
                interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
-               power-domains = <&k3_pds 148>;
+               power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
        };
 
        main_pmx0: pinmux@11c000 {
                #size-cells = <0>;
                clock-names = "fck";
                clocks = <&k3_clks 110 1>;
-               power-domains = <&k3_pds 110>;
+               power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
        };
 
        main_i2c1: i2c@2010000 {
                #size-cells = <0>;
                clock-names = "fck";
                clocks = <&k3_clks 111 1>;
-               power-domains = <&k3_pds 111>;
+               power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
        };
 
        main_i2c2: i2c@2020000 {
                #size-cells = <0>;
                clock-names = "fck";
                clocks = <&k3_clks 112 1>;
-               power-domains = <&k3_pds 112>;
+               power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
        };
 
        main_i2c3: i2c@2030000 {
                #size-cells = <0>;
                clock-names = "fck";
                clocks = <&k3_clks 113 1>;
-               power-domains = <&k3_pds 113>;
+               power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
        };
 
        ecap0: pwm@3100000 {
                compatible = "ti,am654-ecap", "ti,am3352-ecap";
                #pwm-cells = <3>;
                reg = <0x0 0x03100000 0x0 0x60>;
-               power-domains = <&k3_pds 39>;
+               power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 39 0>;
                clock-names = "fck";
        };
                reg = <0x0 0x2100000 0x0 0x400>;
                interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 137 1>;
-               power-domains = <&k3_pds 137>;
+               power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
                reg = <0x0 0x2110000 0x0 0x400>;
                interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 138 1>;
-               power-domains = <&k3_pds 138>;
+               power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
                assigned-clocks = <&k3_clks 137 1>;
                reg = <0x0 0x2120000 0x0 0x400>;
                interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 139 1>;
-               power-domains = <&k3_pds 139>;
+               power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
                reg = <0x0 0x2130000 0x0 0x400>;
                interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 140 1>;
-               power-domains = <&k3_pds 140>;
+               power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
                reg = <0x0 0x2140000 0x0 0x400>;
                interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 141 1>;
-               power-domains = <&k3_pds 141>;
+               power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
        sdhci0: sdhci@4f80000 {
                compatible = "ti,am654-sdhci-5.1";
                reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
-               power-domains = <&k3_pds 47>;
+               power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
                clock-names = "clk_ahb", "clk_xin";
                interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
                ranges = <0x0 0x0 0x4000000 0x20000>;
                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                dma-coherent;
-               power-domains = <&k3_pds 151>;
+               power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
                assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
                assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
                                         <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
                ranges = <0x0 0x0 0x4020000 0x20000>;
                interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
                dma-coherent;
-               power-domains = <&k3_pds 152>;
+               power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
                assigned-clocks = <&k3_clks 152 2>;
                assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 
                        ti,sci-rm-range-vint = <0x0>;
                        ti,sci-rm-range-global-event = <0x1>;
                };
+
+               hwspinlock: spinlock@30e00000 {
+                       compatible = "ti,am654-hwspinlock";
+                       reg = <0x00 0x30e00000 0x00 0x1000>;
+                       #hwlock-cells = <1>;
+               };
        };
 
        main_gpio0:  main_gpio0@600000 {
                compatible = "ti,am654-pcie-rc";
                reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
                reg-names = "app", "dbics", "config", "atu";
-               power-domains = <&k3_pds 120>;
+               power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <3>;
                #size-cells = <2>;
                ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
                compatible = "ti,am654-pcie-ep";
                reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
                reg-names = "app", "dbics", "addr_space", "atu";
-               power-domains = <&k3_pds 120>;
+               power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
                ti,syscon-pcie-mode = <&pcie0_mode>;
                num-ib-windows = <16>;
                num-ob-windows = <16>;
                compatible = "ti,am654-pcie-rc";
                reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
                reg-names = "app", "dbics", "config", "atu";
-               power-domains = <&k3_pds 121>;
+               power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <3>;
                #size-cells = <2>;
                ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
                compatible = "ti,am654-pcie-ep";
                reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
                reg-names = "app", "dbics", "addr_space", "atu";
-               power-domains = <&k3_pds 121>;
+               power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
                ti,syscon-pcie-mode = <&pcie1_mode>;
                num-ib-windows = <16>;
                num-ob-windows = <16>;
index afc29eaa263839e72e27e357a00c1d930c0d984e..7bdf5342f58f33783d10d3fd943f8f27a54f4d83 100644 (file)
@@ -14,7 +14,7 @@
                        interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
                        clock-frequency = <96000000>;
                        current-speed = <115200>;
-                       power-domains = <&k3_pds 149>;
+                       power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
        };
 
        mcu_ram: sram@41c00000 {
@@ -33,7 +33,7 @@
                #size-cells = <0>;
                clock-names = "fck";
                clocks = <&k3_clks 114 1>;
-               power-domains = <&k3_pds 114>;
+               power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
        };
 
        mcu_spi0: spi@40300000 {
@@ -41,7 +41,7 @@
                reg = <0x0 0x40300000 0x0 0x400>;
                interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 142 1>;
-               power-domains = <&k3_pds 142>;
+               power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -51,7 +51,7 @@
                reg = <0x0 0x40310000 0x0 0x400>;
                interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 143 1>;
-               power-domains = <&k3_pds 143>;
+               power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -61,7 +61,7 @@
                reg = <0x0 0x40320000 0x0 0x400>;
                interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 144 1>;
-               power-domains = <&k3_pds 144>;
+               power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
        };
index 9cf2c0849a24c6ce9fc2cf565a40f0247bb3d750..f4227e2743f26afe6c0d4f6346d4da13662ff50b 100644 (file)
@@ -20,7 +20,7 @@
 
                k3_pds: power-controller {
                        compatible = "ti,sci-pm-domain";
-                       #power-domain-cells = <1>;
+                       #power-domain-cells = <2>;
                };
 
                k3_clks: clocks {
@@ -50,7 +50,7 @@
                interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 150>;
+               power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
        };
 
        wkup_i2c0: i2c@42120000 {
@@ -61,7 +61,7 @@
                #size-cells = <0>;
                clock-names = "fck";
                clocks = <&k3_clks 115 1>;
-               power-domains = <&k3_pds 115>;
+               power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
        };
 
        intr_wkup_gpio: interrupt-controller2 {
index 82edf10b2378107a87fd1804eb9e1a8dd3b6e010..6dfccd5d56c848f10f4c9677b7a7a8803d710f76 100644 (file)
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
 
 / {
        model = "Texas Instruments K3 AM654 SoC";
index 52c245d36db921a7ee163596c387540eca40994a..1102b84f853d71c661a126ec4a01cf42d34a6f2d 100644 (file)
 &main_uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart0_pins_default>;
+       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 };
 
 &wkup_i2c0 {
index c680123f067c9186445e40ac19196bb8db6dd8b7..d2894d55fbbeda93ce0bc9aa7ccc1ea1c619c8ad 100644 (file)
@@ -6,12 +6,49 @@
 /dts-v1/;
 
 #include "k3-j721e-som-p0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
        chosen {
                stdout-path = "serial2:115200n8";
                bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
        };
+
+       gpio_keys: gpio-keys {
+               compatible = "gpio-keys";
+               autorepeat;
+               pinctrl-names = "default";
+               pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+
+               sw10: sw10 {
+                       label = "GPIO Key USER1";
+                       linux,code = <BTN_0>;
+                       gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
+               };
+
+               sw11: sw11 {
+                       label = "GPIO Key USER2";
+                       linux,code = <BTN_1>;
+                       gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+&main_pmx0 {
+       sw10_button_pins_default: sw10_button_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
+               >;
+       };
+};
+
+&wkup_pmx0 {
+       sw11_button_pins_default: sw11_button_pins_default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
+               >;
+       };
 };
 
 &wkup_uart0 {
        status = "disabled";
 };
 
+&main_uart0 {
+       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
 &main_uart3 {
        /* UART not brought out */
        status = "disabled";
        /* UART not brought out */
        status = "disabled";
 };
+
+&main_gpio2 {
+       status = "disabled";
+};
+
+&main_gpio3 {
+       status = "disabled";
+};
+
+&main_gpio4 {
+       status = "disabled";
+};
+
+&main_gpio5 {
+       status = "disabled";
+};
+
+&main_gpio6 {
+       status = "disabled";
+};
+
+&main_gpio7 {
+       status = "disabled";
+};
+
+&wkup_gpio1 {
+       status = "disabled";
+};
index a01308142f77d1ed1b6702f27b79ff47af1681b3..698ef9a1d5b75ce175ed572e16191de920fdc8e7 100644 (file)
@@ -31,7 +31,7 @@
                /* vcpumntirq: virtual CPU interface maintenance interrupt */
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-               gic_its: gic-its@18200000 {
+               gic_its: gic-its@1820000 {
                        compatible = "arm,gic-v3-its";
                        reg = <0x00 0x01820000 0x00 0x10000>;
                        socionext,synquacer-pre-its = <0x1000000 0x400000>;
                        ti,sci-rm-range-vint = <0xa>;
                        ti,sci-rm-range-global-event = <0xd>;
                };
+
+               hwspinlock: spinlock@30e00000 {
+                       compatible = "ti,am654-hwspinlock";
+                       reg = <0x00 0x30e00000 0x00 0x1000>;
+                       #hwlock-cells = <1>;
+               };
        };
 
        secure_proxy_main: mailbox@32c00000 {
                interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 146>;
+               power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 146 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 278>;
+               power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 278 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 279>;
+               power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 279 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 280>;
+               power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 280 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 281>;
+               power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 281 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 282>;
+               power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 282 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 283>;
+               power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 283 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 284>;
+               power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 284 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 285>;
+               power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 285 0>;
                clock-names = "fclk";
        };
                interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 286>;
+               power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 286 0>;
                clock-names = "fclk";
        };
+
+       main_gpio0: gpio@600000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00600000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
+                            <105 4>, <105 5>, <105 6>, <105 7>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <128>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 105 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio1: gpio@601000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00601000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <106 0>, <106 1>, <106 2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <36>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 106 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio2: gpio@610000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00610000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
+                            <107 4>, <107 5>, <107 6>, <107 7>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <128>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 107 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio3: gpio@611000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00611000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <108 0>, <108 1>, <108 2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <36>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 108 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio4: gpio@620000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00620000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
+                            <109 4>, <109 5>, <109 6>, <109 7>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <128>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 109 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio5: gpio@621000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00621000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <110 0>, <110 1>, <110 2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <36>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 110 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio6: gpio@630000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00630000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
+                            <111 4>, <111 5>, <111 6>, <111 7>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <128>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 111 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio7: gpio@631000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00631000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <112 0>, <112 1>, <112 2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <36>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 112 0>;
+               clock-names = "gpio";
+       };
 };
index 07b58eeebceb0ba91e8845c608e4fb8f25cec11f..555dc7b7aedc964e61ce541aaa33dca69272f3ca 100644 (file)
@@ -20,7 +20,7 @@
 
                k3_pds: power-controller {
                        compatible = "ti,sci-pm-domain";
-                       #power-domain-cells = <1>;
+                       #power-domain-cells = <2>;
                };
 
                k3_clks: clocks {
@@ -59,7 +59,7 @@
                interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <48000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 287>;
+               power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 287 0>;
                clock-names = "fclk";
        };
@@ -72,7 +72,7 @@
                interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <96000000>;
                current-speed = <115200>;
-               power-domains = <&k3_pds 149>;
+               power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 149 0>;
                clock-names = "fclk";
        };
                ti,sci-dst-id = <14>;
                ti,sci-rm-range-girq = <0x5>;
        };
+
+       wkup_gpio0: gpio@42110000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x42110000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&wkup_gpio_intr>;
+               interrupts = <113 0>, <113 1>, <113 2>,
+                            <113 3>, <113 4>, <113 5>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <84>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 113 0>;
+               clock-names = "gpio";
+       };
+
+       wkup_gpio1: gpio@42100000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x42100000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&wkup_gpio_intr>;
+               interrupts = <114 0>, <114 1>, <114 2>,
+                            <114 3>, <114 4>, <114 5>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <84>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 114 0>;
+               clock-names = "gpio";
+       };
 };
index f8dd74b17bfb9a79de6edf38ca53222ad02b062c..43ea1ba9792203d445b589b160de68f4edafa1e9 100644 (file)
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
 
 / {
        model = "Texas Instruments K3 J721E SoC";
index 2db474ab4c6bea105a5f355f9036d3f7027b3143..9207ac2913412e9da29daa41222930442fd37673 100644 (file)
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * ti-sysc.c - Texas Instruments sysc interconnect target driver
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/io.h>
@@ -62,18 +54,26 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = {
  * @module_size: size of the interconnect target module
  * @module_va: virtual address of the interconnect target module
  * @offsets: register offsets from module base
+ * @mdata: ti-sysc to hwmod translation data for a module
  * @clocks: clocks used by the interconnect target module
  * @clock_roles: clock role names for the found clocks
  * @nr_clocks: number of clocks used by the interconnect target module
+ * @rsts: resets used by the interconnect target module
  * @legacy_mode: configured for legacy mode if set
  * @cap: interconnect target module capabilities
  * @cfg: interconnect target module configuration
+ * @cookie: data used by legacy platform callbacks
  * @name: name if available
  * @revision: interconnect target module revision
+ * @enabled: sysc runtime enabled status
  * @needs_resume: runtime resume needed on resume from suspend
+ * @child_needs_resume: runtime resume needed for child on resume from suspend
+ * @disable_on_idle: status flag used for disabling modules with resets
+ * @idle_work: work structure used to perform delayed idle on a module
  * @clk_enable_quirk: module specific clock enable quirk
  * @clk_disable_quirk: module specific clock disable quirk
  * @reset_done_quirk: module specific reset done quirk
+ * @module_enable_quirk: module specific enable quirk
  */
 struct sysc {
        struct device *dev;
@@ -95,11 +95,11 @@ struct sysc {
        unsigned int enabled:1;
        unsigned int needs_resume:1;
        unsigned int child_needs_resume:1;
-       unsigned int disable_on_idle:1;
        struct delayed_work idle_work;
        void (*clk_enable_quirk)(struct sysc *sysc);
        void (*clk_disable_quirk)(struct sysc *sysc);
        void (*reset_done_quirk)(struct sysc *sysc);
+       void (*module_enable_quirk)(struct sysc *sysc);
 };
 
 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
@@ -503,7 +503,7 @@ static void sysc_clkdm_allow_idle(struct sysc *ddata)
 static int sysc_init_resets(struct sysc *ddata)
 {
        ddata->rsts =
-               devm_reset_control_get_optional(ddata->dev, "rstctrl");
+               devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
        if (IS_ERR(ddata->rsts))
                return PTR_ERR(ddata->rsts);
 
@@ -615,8 +615,8 @@ static void sysc_check_quirk_stdout(struct sysc *ddata,
  * node but children have "ti,hwmods". These belong to the interconnect
  * target node and are managed by this driver.
  */
-static int sysc_check_one_child(struct sysc *ddata,
-                               struct device_node *np)
+static void sysc_check_one_child(struct sysc *ddata,
+                                struct device_node *np)
 {
        const char *name;
 
@@ -626,22 +626,14 @@ static int sysc_check_one_child(struct sysc *ddata,
 
        sysc_check_quirk_stdout(ddata, np);
        sysc_parse_dts_quirks(ddata, np, true);
-
-       return 0;
 }
 
-static int sysc_check_children(struct sysc *ddata)
+static void sysc_check_children(struct sysc *ddata)
 {
        struct device_node *child;
-       int error;
-
-       for_each_child_of_node(ddata->dev->of_node, child) {
-               error = sysc_check_one_child(ddata, child);
-               if (error)
-                       return error;
-       }
 
-       return 0;
+       for_each_child_of_node(ddata->dev->of_node, child)
+               sysc_check_one_child(ddata, child);
 }
 
 /*
@@ -794,9 +786,7 @@ static int sysc_map_and_check_registers(struct sysc *ddata)
        if (error)
                return error;
 
-       error = sysc_check_children(ddata);
-       if (error)
-               return error;
+       sysc_check_children(ddata);
 
        error = sysc_parse_registers(ddata);
        if (error)
@@ -940,6 +930,9 @@ set_autoidle:
                sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
        }
 
+       if (ddata->module_enable_quirk)
+               ddata->module_enable_quirk(ddata);
+
        return 0;
 }
 
@@ -1031,8 +1024,7 @@ static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
                dev_err(dev, "%s: could not idle: %i\n",
                        __func__, error);
 
-       if (ddata->disable_on_idle)
-               reset_control_assert(ddata->rsts);
+       reset_control_assert(ddata->rsts);
 
        return 0;
 }
@@ -1043,8 +1035,7 @@ static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
        struct ti_sysc_platform_data *pdata;
        int error;
 
-       if (ddata->disable_on_idle)
-               reset_control_deassert(ddata->rsts);
+       reset_control_deassert(ddata->rsts);
 
        pdata = dev_get_platdata(ddata->dev);
        if (!pdata)
@@ -1091,10 +1082,9 @@ static int __maybe_unused sysc_runtime_suspend(struct device *dev)
        ddata->enabled = false;
 
 err_allow_idle:
-       sysc_clkdm_allow_idle(ddata);
+       reset_control_assert(ddata->rsts);
 
-       if (ddata->disable_on_idle)
-               reset_control_assert(ddata->rsts);
+       sysc_clkdm_allow_idle(ddata);
 
        return error;
 }
@@ -1109,11 +1099,11 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev)
        if (ddata->enabled)
                return 0;
 
-       if (ddata->disable_on_idle)
-               reset_control_deassert(ddata->rsts);
 
        sysc_clkdm_deny_idle(ddata);
 
+       reset_control_deassert(ddata->rsts);
+
        if (sysc_opt_clks_needed(ddata)) {
                error = sysc_enable_opt_clocks(ddata);
                if (error)
@@ -1256,6 +1246,9 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
                   SYSC_MODULE_QUIRK_I2C),
        SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
                   SYSC_MODULE_QUIRK_I2C),
+       SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
+       SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
+                  SYSC_MODULE_QUIRK_SGX),
        SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
                   SYSC_MODULE_QUIRK_WDT),
 
@@ -1271,8 +1264,11 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
        SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
        SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
        SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
+       SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
+       SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
        SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
        SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
+       SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
        SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
        SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
        SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
@@ -1424,6 +1420,15 @@ static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
        sysc_clk_quirk_i2c(ddata, false);
 }
 
+/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
+static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
+{
+       int offset = 0xff08;    /* OCP_DEBUG_CONFIG */
+       u32 val = BIT(31);      /* THALIA_INT_BYPASS */
+
+       sysc_write(ddata, offset, val);
+}
+
 /* Watchdog timer needs a disable sequence after reset */
 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
 {
@@ -1466,6 +1471,9 @@ static void sysc_init_module_quirks(struct sysc *ddata)
                return;
        }
 
+       if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
+               ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
+
        if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT)
                ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
 }
@@ -1532,7 +1540,7 @@ static int sysc_legacy_init(struct sysc *ddata)
  */
 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
 {
-       int error, val;
+       int error;
 
        if (!ddata->rsts)
                return 0;
@@ -1543,14 +1551,9 @@ static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
                        return error;
        }
 
-       error = reset_control_deassert(ddata->rsts);
-       if (error == -EEXIST)
-               return 0;
+       reset_control_deassert(ddata->rsts);
 
-       error = readx_poll_timeout(reset_control_status, ddata->rsts, val,
-                                  val == 0, 100, MAX_MODULE_SOFTRESET_WAIT);
-
-       return error;
+       return 0;
 }
 
 /*
@@ -1559,12 +1562,11 @@ static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
  */
 static int sysc_reset(struct sysc *ddata)
 {
-       int sysc_offset, syss_offset, sysc_val, rstval, quirks, error = 0;
+       int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
        u32 sysc_mask, syss_done;
 
        sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
        syss_offset = ddata->offsets[SYSC_SYSSTATUS];
-       quirks = ddata->cfg.quirks;
 
        if (ddata->legacy_mode || sysc_offset < 0 ||
            ddata->cap->regbits->srst_shift < 0 ||
@@ -2427,6 +2429,10 @@ static int sysc_probe(struct platform_device *pdev)
                goto unprepare;
        }
 
+       /* Balance reset counts */
+       if (ddata->rsts)
+               reset_control_assert(ddata->rsts);
+
        sysc_show_registers(ddata);
 
        ddata->dev->type = &sysc_device_type;
@@ -2446,9 +2452,6 @@ static int sysc_probe(struct platform_device *pdev)
                pm_runtime_put(&pdev->dev);
        }
 
-       if (!of_get_available_child_count(ddata->dev->of_node))
-               ddata->disable_on_idle = true;
-
        return 0;
 
 err:
index dafef7e70ba8344eab5d084d5188b9ec6b1e0f92..e675e27f1203cb31418bb9d989a15175e7887372 100644 (file)
@@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst =
        { 0 },
 };
 
+static const char * const omap5_gpu_core_mux_parents[] __initconst = {
+       "dpll_core_h14x2_ck",
+       "dpll_per_h14x2_ck",
+       NULL,
+};
+
+static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
+       "dpll_core_h14x2_ck",
+       "dpll_per_h14x2_ck",
+       NULL,
+};
+
+static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
+       "sys_clkin",
+       NULL,
+};
+
+static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
+       .max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
+       { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
+       { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
+       { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
+       { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
+       { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
+       { 0 },
+};
+
 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
        "func_128m_clk",
        "dpll_per_m2x2_ck",
@@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
        { 0x4a008e20, omap5_l3instr_clkctrl_regs },
        { 0x4a009020, omap5_l4per_clkctrl_regs },
        { 0x4a009420, omap5_dss_clkctrl_regs },
+       { 0x4a009520, omap5_gpu_clkctrl_regs },
        { 0x4a009620, omap5_l3init_clkctrl_regs },
        { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
        { 0 },
index 7138384e2ef9f4ef9865d4b417ea986ff9e36ef3..babd08a1d2267bfef88457f83446c31d593f842a 100644 (file)
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /* TI sysc interconnect target module defines */
 
 /* Generic sysc found on omap2 and later, also known as type1 */
index f3283957f48ddf92ddc9ff3d6cf94fa633fa9177..e5411938983cd2501cc8669c3fc248dea3f49d2c 100644 (file)
@@ -89,6 +89,9 @@
 /* dss clocks */
 #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
 
+/* gpu clocks */
+#define OMAP5_GPU_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x20)
+
 /* l3init clocks */
 #define OMAP5_MMC1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x28)
 #define OMAP5_MMC2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x30)
index 45e11b6170ca908f48f09b2fb69b4ae5fa345771..499de62165811d081a30ecd1b6e10407271d4cef 100644 (file)
@@ -32,4 +32,7 @@
 #define AM65X_IOPAD(pa, val, muxmode)          (((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM65X_WKUP_IOPAD(pa, val, muxmode)     (((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define J721E_IOPAD(pa, val, muxmode)          (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_WKUP_IOPAD(pa, val, muxmode)     (((pa) & 0x1fff)) ((val) | (muxmode))
+
 #endif
index 0c587d4fc718bcdc9852b6f0c3a224343d6d6336..b5b7a3423ca8161659426ceb6e8b2e350479cbea 100644 (file)
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
 #ifndef __TI_SYSC_DATA_H__
 #define __TI_SYSC_DATA_H__
 
@@ -47,6 +49,7 @@ struct sysc_regbits {
        s8 emufree_shift;
 };
 
+#define SYSC_MODULE_QUIRK_SGX          BIT(18)
 #define SYSC_MODULE_QUIRK_HDQ1W                BIT(17)
 #define SYSC_MODULE_QUIRK_I2C          BIT(16)
 #define SYSC_MODULE_QUIRK_WDT          BIT(15)
@@ -70,7 +73,7 @@ struct sysc_regbits {
 
 /**
  * struct sysc_capabilities - capabilities for an interconnect target module
- *
+ * @type: sysc type identifier for the module
  * @sysc_mask: bitmask of supported SYSCONFIG register bits
  * @regbits: bitmask of SYSCONFIG register bits
  * @mod_quirks: bitmask of module specific quirks
@@ -85,8 +88,9 @@ struct sysc_capabilities {
 /**
  * struct sysc_config - configuration for an interconnect target module
  * @sysc_val: configured value for sysc register
+ * @syss_mask: configured mask value for SYSSTATUS register
  * @midlemodes: bitmask of supported master idle modes
- * @sidlemodes: bitmask of supported master idle modes
+ * @sidlemodes: bitmask of supported slave idle modes
  * @srst_udelay: optional delay needed after OCP soft reset
  * @quirks: bitmask of enabled quirks
  */