S: Supported
F: drivers/spi/spi-atmel.*
+ATMEL SSC DRIVER
+M: Bo Shen <voice.shen@atmel.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Supported
+F: drivers/misc/atmel-ssc.c
+F: include/linux/atmel-ssc.h
+
ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS
M: Nicolas Ferre <nicolas.ferre@atmel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
- atmel,clk-input-range = <1000000 5000000>;
+ atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+ atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+ <190000000 240000000 2 1>;
};
mck: masterck {
status = "disabled";
};
- gpio@ff708000 {
+ gpio0: gpio@ff708000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
clocks = <&per_base_clk>;
status = "disabled";
- gpio0: gpio-controller@0 {
+ porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
};
};
- gpio@ff709000 {
+ gpio1: gpio@ff709000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
clocks = <&per_base_clk>;
status = "disabled";
- gpio1: gpio-controller@0 {
+ portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
};
};
- gpio@ff70a000 {
+ gpio2: gpio@ff70a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
clocks = <&per_base_clk>;
status = "disabled";
- gpio2: gpio-controller@0 {
+ portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
};
};
- dwmmc0@ff704000 {
+ mmc0: dwmmc0@ff704000 {
num-slots = <1>;
broken-cd;
bus-width = <4>;
*/
ethernet0 = &gmac1;
};
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&gmac1 {
};
};
+&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
&usb1 {
status = "okay";
};
*/
ethernet0 = &gmac1;
};
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&gmac1 {
rxc-skew-ps = <2000>;
};
+&gpio1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
&mmc0 {
- cd-gpios = <&gpio1 18 0>;
+ cd-gpios = <&portb 18 0>;
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
};
&usb1 {
*/
ethernet0 = &gmac1;
};
+
+ regulator_3_3v: vcc3p3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&gmac1 {
rxc-skew-ps = <2000>;
};
+&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
&usb1 {
status = "okay";
};
/* kHz uV */
666667 1000000
333334 1000000
- 222223 1000000
>;
};
interrupt-parent = <&intc>;
ranges;
- adc@f8007100 {
+ adc: adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
<0xF8F00100 0x100>;
};
- L2: cache-controller {
+ L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
arm,data-latency = <3 2 2>;
cache-level = <2>;
};
- memory-controller@f8006000 {
+ mc: memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
- } ;
+ };
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
- reg = <0xe000b000 0x4000>;
+ reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
gem1: ethernet@e000c000 {
compatible = "cdns,gem";
- reg = <0xe000c000 0x4000>;
+ reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
};
+
+ watchdog0: watchdog@f8005000 {
+ clocks = <&clkc 45>;
+ compatible = "xlnx,zynq-wdt-r1p2";
+ device_type = "watchdog";
+ interrupt-parent = <&intc>;
+ interrupts = <0 9 1>;
+ reg = <0xf8005000 0x1000>;
+ reset = <0>;
+ timeout-sec = <10>;
+ };
};
};
CONFIG_MMC_SUNXI=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_SUNXI_WATCHDOG=y
CONFIG_MFD_AXP20X=y
CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
extern struct smp_operations socfpga_smp_ops;
extern char secondary_trampoline, secondary_trampoline_end;
-extern unsigned long cpu1start_addr;
+extern unsigned long socfpga_cpu1start_addr;
#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/memory.h>
.arch armv7-a
ENTRY(secondary_trampoline)
- movw r2, #:lower16:cpu1start_addr
- movt r2, #:upper16:cpu1start_addr
-
- /* The socfpga VT cannot handle a 0xC0000000 page offset when loading
- the cpu1start_addr, we bit clear it. Tested on HW and VT. */
- bic r2, r2, #0x40000000
-
- ldr r0, [r2]
- ldr r1, [r0]
- bx r1
+ /* CPU1 will always fetch from 0x0 when it is brought out of reset.
+ * Thus, we can just subtract the PAGE_OFFSET to get the physical
+ * address of &cpu1start_addr. This would not work for platforms
+ * where the physical memory does not start at 0x0.
+ */
+ adr r0, 1f
+ ldmia r0, {r1, r2}
+ sub r2, r2, #PAGE_OFFSET
+ ldr r3, [r2]
+ ldr r4, [r3]
+ bx r4
+ .align
+1: .long .
+ .long socfpga_cpu1start_addr
ENTRY(secondary_trampoline_end)
ENTRY(socfpga_secondary_startup)
{
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
- if (cpu1start_addr) {
+ if (socfpga_cpu1start_addr) {
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
__raw_writel(virt_to_phys(socfpga_secondary_startup),
- (sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
+ (sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
flush_cache_all();
smp_wmb();
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
-unsigned long cpu1start_addr;
+unsigned long socfpga_cpu1start_addr;
static struct map_desc scu_io_desc __initdata = {
.virtual = SOCFPGA_SCU_VIRT_BASE,
np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
if (of_property_read_u32(np, "cpu1-start-addr",
- (u32 *) &cpu1start_addr))
+ (u32 *) &socfpga_cpu1start_addr))
pr_err("SMP: Need cpu1-start-addr in device tree.\n");
sys_manager_base_addr = of_iomap(np, 0);
/* Disable SDRAM0 accesses */
"1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
/* Power down SDRAM0 */
- " str %4, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
+ " str %4, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
/* Disable SDRAM1 accesses */
" strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
/* Power down SDRAM1 */
- " strne %4, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
+ " strne %4, [%1, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
/* Reset CPU */
" str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
git.samba.org / sfrench / cifs-2.6.git / commitdiff