Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Radim Krčmář:
 "PPC:

   - Close a hole which could possibly lead to the host timebase getting
     out of sync.

   - Three fixes relating to PTEs and TLB entries for radix guests.

   - Fix a bug which could lead to an interrupt never getting delivered
     to the guest, if it is pending for a guest vCPU when the vCPU gets
     offlined.

  s390:

   - Fix false negatives in VSIE validity check (Cc stable)

  x86:

   - Fix time drift of VMX preemption timer when a guest uses LAPIC
     timer in periodic mode (Cc stable)

   - Unconditionally expose CPUID.IA32_ARCH_CAPABILITIES to allow
     migration from hosts that don't need retpoline mitigation (Cc
     stable)

   - Fix guest crashes on reboot by properly coupling CR4.OSXSAVE and
     CPUID.OSXSAVE (Cc stable)

   - Report correct RIP after Hyper-V hypercall #UD (introduced in
     -rc6)"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: x86: fix #UD address of failed Hyper-V hypercalls
  kvm: x86: IA32_ARCH_CAPABILITIES is always supported
  KVM: x86: Update cpuid properly when CR4.OSXAVE or CR4.PKE is changed
  x86/kvm: fix LAPIC timer drift when guest uses periodic mode
  KVM: s390: vsie: fix < 8k check for the itdba
  KVM: PPC: Book 3S HV: Do ptesync in radix guest exit path
  KVM: PPC: Book3S HV: XIVE: Resend re-routed interrupts on CPU priority change
  KVM: PPC: Book3S HV: Make radix clear pte when unmapping
  KVM: PPC: Book3S HV: Make radix use correct tlbie sequence in kvmppc_radix_tlbie_page
  KVM: PPC: Book3S HV: Snapshot timebase offset on guest entry

diff --combined arch/x86/kvm/cpuid.c
index ced851169730a0cd3910d05baae61293d1f56a4f,beadfe6e68936edd5123d6f756b44aac2cc5a2a1..9bffb5228f31670b790051c8aa329c2692c8ad92
--- 1/arch/x86/kvm/cpuid.c
--- 2/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@@ -379,7 -379,7 +379,7 @@@ static inline int __do_cpuid_ent(struc
  
        /* cpuid 0x80000008.ebx */
        const u32 kvm_cpuid_8000_0008_ebx_x86_features =
 -              F(IBPB) | F(IBRS);
 +              F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD);
  
        /* cpuid 0xC0000001.edx */
        const u32 kvm_cpuid_C000_0001_edx_x86_features =
@@@ -407,7 -407,7 +407,7 @@@
  
        /* cpuid 7.0.edx*/
        const u32 kvm_cpuid_7_0_edx_x86_features =
 -              F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
 +              F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SSBD) |
                F(ARCH_CAPABILITIES);
  
        /* all calls to cpuid_count() should be made on the same cpu */
@@@ -495,6 -495,11 +495,11 @@@
                                entry->ecx &= ~F(PKU);
                        entry->edx &= kvm_cpuid_7_0_edx_x86_features;
                        cpuid_mask(&entry->edx, CPUID_7_EDX);
+                       /*
+                        * We emulate ARCH_CAPABILITIES in software even
+                        * if the host doesn't support it.
+                        */
+                       entry->edx |= F(ARCH_CAPABILITIES);
                } else {
                        entry->ebx = 0;
                        entry->ecx = 0;
@@@ -647,20 -652,13 +652,20 @@@
                        g_phys_as = phys_as;
                entry->eax = g_phys_as | (virt_as << 8);
                entry->edx = 0;
 -              /* IBRS and IBPB aren't necessarily present in hardware cpuid */
 -              if (boot_cpu_has(X86_FEATURE_IBPB))
 -                      entry->ebx |= F(IBPB);
 -              if (boot_cpu_has(X86_FEATURE_IBRS))
 -                      entry->ebx |= F(IBRS);
 +              /*
 +               * IBRS, IBPB and VIRT_SSBD aren't necessarily present in
 +               * hardware cpuid
 +               */
 +              if (boot_cpu_has(X86_FEATURE_AMD_IBPB))
 +                      entry->ebx |= F(AMD_IBPB);
 +              if (boot_cpu_has(X86_FEATURE_AMD_IBRS))
 +                      entry->ebx |= F(AMD_IBRS);
 +              if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 +                      entry->ebx |= F(VIRT_SSBD);
                entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
                cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
 +              if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 +                      entry->ebx |= F(VIRT_SSBD);
                break;
        }
        case 0x80000019:

diff --combined arch/x86/kvm/x86.c
index 22a183aac1c63f333efb446f1376d1ac09b85cd0,b7618b30b7d6219d841776c31e83dab207103957..71e7cda6d01430bca8ef226238589ab0e830d6c9
--- 1/arch/x86/kvm/x86.c
--- 2/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@@ -1061,7 -1061,6 +1061,7 @@@ static u32 emulated_msrs[] = 
        MSR_SMI_COUNT,
        MSR_PLATFORM_INFO,
        MSR_MISC_FEATURES_ENABLES,
 +      MSR_AMD64_VIRT_SPEC_CTRL,
  };
  
  static unsigned num_emulated_msrs;
@@@ -2907,7 -2906,7 +2907,7 @@@ int kvm_vm_ioctl_check_extension(struc
                 * fringe case that is not enabled except via specific settings
                 * of the module parameters.
                 */
 -              r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
 +              r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
                break;
        case KVM_CAP_VAPIC:
                r = !kvm_x86_ops->cpu_has_accelerated_tpr();
@@@ -4607,8 -4606,14 +4607,8 @@@ static void kvm_init_msr_list(void
        num_msrs_to_save = j;
  
        for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
 -              switch (emulated_msrs[i]) {
 -              case MSR_IA32_SMBASE:
 -                      if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
 -                              continue;
 -                      break;
 -              default:
 -                      break;
 -              }
 +              if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
 +                      continue;
  
                if (j < i)
                        emulated_msrs[j] = emulated_msrs[i];
@@@ -6671,11 -6676,8 +6671,8 @@@ int kvm_emulate_hypercall(struct kvm_vc
        unsigned long nr, a0, a1, a2, a3, ret;
        int op_64_bit;
  
-       if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
-               if (!kvm_hv_hypercall(vcpu))
-                       return 0;
-               goto out;
-       }
+       if (kvm_hv_hypercall_enabled(vcpu->kvm))
+               return kvm_hv_hypercall(vcpu);
  
        nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
        a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
@@@ -6696,7 -6698,7 +6693,7 @@@
  
        if (kvm_x86_ops->get_cpl(vcpu) != 0) {
                ret = -KVM_EPERM;
-               goto out_error;
+               goto out;
        }
  
        switch (nr) {
@@@ -6716,12 -6718,11 +6713,11 @@@
                ret = -KVM_ENOSYS;
                break;
        }
- out_error:
+ out:
        if (!op_64_bit)
                ret = (u32)ret;
        kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
  
- out:
        ++vcpu->stat.hypercalls;
        return kvm_skip_emulated_instruction(vcpu);
  }
@@@ -7980,6 -7981,7 +7976,7 @@@ static int __set_sregs(struct kvm_vcpu 
  {
        struct msr_data apic_base_msr;
        int mmu_reset_needed = 0;
+       int cpuid_update_needed = 0;
        int pending_vec, max_bits, idx;
        struct desc_ptr dt;
        int ret = -EINVAL;
@@@ -8018,8 -8020,10 +8015,10 @@@
        vcpu->arch.cr0 = sregs->cr0;
  
        mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
+       cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
+                               (X86_CR4_OSXSAVE | X86_CR4_PKE));
        kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
-       if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
+       if (cpuid_update_needed)
                kvm_update_cpuid(vcpu);
  
        idx = srcu_read_lock(&vcpu->kvm->srcu);