Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 8 Feb 2020 22:04:19 +0000 (14:04 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 8 Feb 2020 22:04:19 +0000 (14:04 -0800)
Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms:

   - Nvidia: Fuse support for Tegra194, continued memory controller
     pieces for Tegra30

   - NXP/FSL: Refactorings of QuickEngine drivers to support
     ARM/ARM64/PPC

   - NXP/FSL: i.MX8MP SoC driver pieces

   - TI Keystone: ring accelerator driver

   - Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.

   - Xilinx ZynqMP: feature checking interface for firmware. Mailbox
     communication for power management

   - Overall support patch set for cpuidle on more complex hierarchies
     (PSCI-based)

  and misc cleanups, refactorings of Marvell, TI, other platforms"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits)
  drivers: soc: xilinx: Use mailbox IPI callback
  dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox
  drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists
  MAINTAINERS: Add brcmstb PCIe controller entry
  soc/tegra: fuse: Unmap registers once they are not needed anymore
  soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
  soc/tegra: fuse: Warn if straps are not ready
  soc/tegra: fuse: Cache values of straps and Chip ID registers
  memory: tegra30-emc: Correct error message for timed out auto calibration
  memory: tegra30-emc: Firm up hardware programming sequence
  memory: tegra30-emc: Firm up suspend/resume sequence
  soc/tegra: regulators: Do nothing if voltage is unchanged
  memory: tegra: Correct reset value of xusb_hostr
  soc/tegra: fuse: Add APB DMA dependency for Tegra20
  bus: tegra-aconnect: Remove PM_CLK dependency
  dt-bindings: mediatek: add MT6765 power dt-bindings
  soc: mediatek: cmdq: delete not used define
  memory: tegra: Add support for the Tegra194 memory controller
  memory: tegra: Only include support for enabled SoCs
  memory: tegra: Support DVFS on Tegra186 and later
  ...

13 files changed:
1  2 
MAINTAINERS
arch/arm64/boot/dts/qcom/msm8916.dtsi
arch/powerpc/platforms/83xx/km83xx.c
arch/powerpc/platforms/85xx/twr_p102x.c
drivers/bus/ti-sysc.c
drivers/firmware/xilinx/zynqmp.c
drivers/net/wan/fsl_ucc_hdlc.c
drivers/of/base.c
drivers/soc/tegra/fuse/fuse-tegra.c
drivers/soc/tegra/fuse/tegra-apbmisc.c
drivers/tty/serial/ucc_uart.c
include/linux/cpuhotplug.h
include/linux/firmware/xlnx-zynqmp.h

diff --combined MAINTAINERS
index 6d81608967688bb4f79fa4ce8db39129cfe76bb8,06d15ec37dbd593686a0edf9a9bc82e5faa3fdb7..e7874c4d83f097852542bd1f9d5ee3bb2a13e60d
@@@ -317,45 -317,45 +317,45 @@@ ACP
  M:    "Rafael J. Wysocki" <rjw@rjwysocki.net>
  M:    Len Brown <lenb@kernel.org>
  L:    linux-acpi@vger.kernel.org
 +S:    Supported
  W:    https://01.org/linux-acpi
 -Q:    https://patchwork.kernel.org/project/linux-acpi/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
 +Q:    https://patchwork.kernel.org/project/linux-acpi/list/
  B:    https://bugzilla.kernel.org
 -S:    Supported
 +F:    Documentation/ABI/testing/configfs-acpi
 +F:    Documentation/ABI/testing/sysfs-bus-acpi
 +F:    Documentation/firmware-guide/acpi/
  F:    drivers/acpi/
 +F:    drivers/pci/*/*acpi*
 +F:    drivers/pci/*acpi*
  F:    drivers/pnp/pnpacpi/
 +F:    include/acpi/
  F:    include/linux/acpi.h
  F:    include/linux/fwnode.h
 -F:    include/acpi/
 -F:    Documentation/firmware-guide/acpi/
 -F:    Documentation/ABI/testing/sysfs-bus-acpi
 -F:    Documentation/ABI/testing/configfs-acpi
 -F:    drivers/pci/*acpi*
 -F:    drivers/pci/*/*acpi*
  F:    tools/power/acpi/
  
  ACPI APEI
  M:    "Rafael J. Wysocki" <rjw@rjwysocki.net>
  M:    Len Brown <lenb@kernel.org>
 -L:    linux-acpi@vger.kernel.org
  R:    James Morse <james.morse@arm.com>
  R:    Tony Luck <tony.luck@intel.com>
  R:    Borislav Petkov <bp@alien8.de>
 +L:    linux-acpi@vger.kernel.org
  F:    drivers/acpi/apei/
  
  ACPI COMPONENT ARCHITECTURE (ACPICA)
  M:    Robert Moore <robert.moore@intel.com>
 -M:    Erik Schmauss <erik.schmauss@intel.com>
 +M:    Erik Kaneda <erik.kaneda@intel.com>
  M:    "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
  L:    linux-acpi@vger.kernel.org
  L:    devel@acpica.org
 +S:    Supported
  W:    https://acpica.org/
  W:    https://github.com/acpica/acpica/
 -Q:    https://patchwork.kernel.org/project/linux-acpi/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
 +Q:    https://patchwork.kernel.org/project/linux-acpi/list/
  B:    https://bugzilla.kernel.org
  B:    https://bugs.acpica.org
 -S:    Supported
  F:    drivers/acpi/acpica/
  F:    include/acpi/
  F:    tools/power/acpi/
  ACPI FAN DRIVER
  M:    Zhang Rui <rui.zhang@intel.com>
  L:    linux-acpi@vger.kernel.org
 +S:    Supported
  W:    https://01.org/linux-acpi
  B:    https://bugzilla.kernel.org
 -S:    Supported
  F:    drivers/acpi/fan.c
  
  ACPI FOR ARM64 (ACPI/arm64)
@@@ -389,26 -389,26 +389,26 @@@ M:      Len Brown <lenb@kernel.org
  R:    Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  R:    Mika Westerberg <mika.westerberg@linux.intel.com>
  L:    linux-acpi@vger.kernel.org
 -Q:    https://patchwork.kernel.org/project/linux-acpi/list/
 +S:    Supported
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
 +Q:    https://patchwork.kernel.org/project/linux-acpi/list/
  B:    https://bugzilla.kernel.org
 -S:    Supported
  F:    drivers/acpi/pmic/
  
  ACPI THERMAL DRIVER
  M:    Zhang Rui <rui.zhang@intel.com>
  L:    linux-acpi@vger.kernel.org
 +S:    Supported
  W:    https://01.org/linux-acpi
  B:    https://bugzilla.kernel.org
 -S:    Supported
  F:    drivers/acpi/*thermal*
  
  ACPI VIDEO DRIVER
  M:    Zhang Rui <rui.zhang@intel.com>
  L:    linux-acpi@vger.kernel.org
 +S:    Supported
  W:    https://01.org/linux-acpi
  B:    https://bugzilla.kernel.org
 -S:    Supported
  F:    drivers/acpi/acpi_video.c
  
  ACPI WMI DRIVER
@@@ -674,14 -674,6 +674,14 @@@ S:       Maintaine
  F:    Documentation/i2c/busses/i2c-ali1563.rst
  F:    drivers/i2c/busses/i2c-ali1563.c
  
 +ALL SENSORS DLH SERIES PRESSURE SENSORS DRIVER
 +M:    Tomislav Denis <tomislav.denis@avl.com>
 +W:    http://www.allsensors.com/
 +S:    Maintained
 +L:    linux-iio@vger.kernel.org
 +F:    drivers/iio/pressure/dlhl60d.c
 +F:    Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
 +
  ALLEGRO DVT VIDEO IP CORE DRIVER
  M:    Michael Tretter <m.tretter@pengutronix.de>
  R:    Pengutronix Kernel Team <kernel@pengutronix.de>
@@@ -702,14 -694,6 +702,14 @@@ L:       linux-crypto@vger.kernel.or
  S:    Maintained
  F:    drivers/crypto/allwinner/
  
 +ALLWINNER THERMAL DRIVER
 +M:    Vasily Khoruzhick <anarsoul@gmail.com>
 +M:    Yangtao Li <tiny.windzz@gmail.com>
 +L:    linux-pm@vger.kernel.org
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
 +F:    drivers/thermal/sun8i_thermal.c
 +
  ALLWINNER VPU DRIVER
  M:    Maxime Ripard <mripard@kernel.org>
  M:    Paul Kocialkowski <paul.kocialkowski@bootlin.com>
@@@ -736,13 -720,13 +736,13 @@@ F:      Documentation/devicetree/bindings/i2
  F:    drivers/i2c/busses/i2c-altera.c
  
  ALTERA MAILBOX DRIVER
 -M:    Ley Foon Tan <lftan@altera.com>
 +M:    Ley Foon Tan <ley.foon.tan@intel.com>
  L:    nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
  S:    Maintained
  F:    drivers/mailbox/mailbox-altera.c
  
  ALTERA PIO DRIVER
 -M:    Tien Hock Loh <thloh@altera.com>
 +M:    Joyce Ooi <joyce.ooi@intel.com>
  L:    linux-gpio@vger.kernel.org
  S:    Maintained
  F:    drivers/gpio/gpio-altera.c
@@@ -787,8 -771,6 +787,8 @@@ F: drivers/thermal/thermal_mmio.
  
  AMAZON ETHERNET DRIVERS
  M:    Netanel Belgazal <netanel@amazon.com>
 +M:    Arthur Kiyanovski <akiyano@amazon.com>
 +R:    Guy Tzalik <gtzalik@amazon.com>
  R:    Saeed Bishara <saeedb@amazon.com>
  R:    Zorik Machulsky <zorik@amazon.com>
  L:    netdev@vger.kernel.org
@@@ -807,6 -789,7 +807,6 @@@ F: include/uapi/rdma/efa-abi.
  
  AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER
  M:    Tom Lendacky <thomas.lendacky@amd.com>
 -M:    Gary Hook <gary.hook@amd.com>
  L:    linux-crypto@vger.kernel.org
  S:    Supported
  F:    drivers/crypto/ccp/
@@@ -915,14 -898,6 +915,14 @@@ S:       Supporte
  F:    drivers/iio/dac/ad5758.c
  F:    Documentation/devicetree/bindings/iio/dac/ad5758.txt
  
 +ANALOG DEVICES INC AD7091R5 DRIVER
 +M:    Beniamin Bia <beniamin.bia@analog.com>
 +L:    linux-iio@vger.kernel.org
 +W:    http://ez.analog.com/community/linux-device-drivers
 +S:    Supported
 +F:    drivers/iio/adc/ad7091r5.c
 +F:    Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml
 +
  ANALOG DEVICES INC AD7124 DRIVER
  M:    Stefan Popa <stefan.popa@analog.com>
  L:    linux-iio@vger.kernel.org
@@@ -1000,15 -975,6 +1000,15 @@@ W:     http://ez.analog.com/community/linux
  F:    drivers/iio/imu/adis16460.c
  F:    Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
  
 +ANALOG DEVICES INC ADM1177 DRIVER
 +M:    Beniamin Bia <beniamin.bia@analog.com>
 +M:    Michael Hennerich <Michael.Hennerich@analog.com>
 +L:    linux-hwmon@vger.kernel.org
 +W:    http://ez.analog.com/community/linux-device-drivers
 +S:    Supported
 +F:    drivers/hwmon/adm1177.c
 +F:    Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml
 +
  ANALOG DEVICES INC ADP5061 DRIVER
  M:    Stefan Popa <stefan.popa@analog.com>
  L:    linux-pm@vger.kernel.org
@@@ -1077,7 -1043,7 +1077,7 @@@ S:      Supporte
  F:    Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9523
  F:    Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350
  F:    drivers/iio/*/ad*
 -F:    drivers/iio/adc/ltc2497*
 +F:    drivers/iio/adc/ltc249*
  X:    drivers/iio/*/adjd*
  F:    drivers/staging/iio/*/ad*
  
@@@ -1439,7 -1405,7 +1439,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
  
  ARM/ACTIONS SEMI ARCHITECTURE
  M:    Andreas Färber <afaerber@suse.de>
 -R:    Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 +M:    Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
  N:    owl
@@@ -2092,7 -2058,6 +2092,7 @@@ F:      drivers/rtc/rtc-pl031.
  F:    drivers/watchdog/coh901327_wdt.c
  F:    Documentation/devicetree/bindings/arm/ste-*
  F:    Documentation/devicetree/bindings/arm/ux500/
 +F:    Documentation/devicetree/bindings/arm/ux500.yaml
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
  
  ARM/NUVOTON NPCM ARCHITECTURE
@@@ -2275,7 -2240,6 +2275,7 @@@ L:      linux-rockchip@lists.infradead.or
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
  S:    Maintained
  F:    Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
 +F:    Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
  F:    arch/arm/boot/dts/rk3*
  F:    arch/arm/boot/dts/rv1108*
  F:    arch/arm/mach-rockchip/
@@@ -2728,14 -2692,6 +2728,14 @@@ S:    Maintaine
  F:    drivers/pinctrl/aspeed/
  F:    Documentation/devicetree/bindings/pinctrl/aspeed,*
  
 +ASPEED SCU INTERRUPT CONTROLLER DRIVER
 +M:    Eddie James <eajames@linux.ibm.com>
 +L:    linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt
 +F:    drivers/irqchip/irq-aspeed-scu-ic.c
 +F:    include/dt-bindings/interrupt-controller/aspeed-scu-ic.h
 +
  ASPEED VIDEO ENGINE DRIVER
  M:    Eddie James <eajames@linux.ibm.com>
  L:    linux-media@vger.kernel.org
@@@ -3133,13 -3089,6 +3133,13 @@@ S:    Supporte
  F:    drivers/net/bonding/
  F:    include/uapi/linux/if_bonding.h
  
 +BOSCH SENSORTEC BMA400 ACCELEROMETER IIO DRIVER
 +M:    Dan Robertson <dan@dlrobertson.com>
 +L:    linux-iio@vger.kernel.org
 +S:    Maintained
 +F:    drivers/iio/accel/bma400*
 +F:    Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
 +
  BPF (Safe dynamic programs and tools)
  M:    Alexei Starovoitov <ast@kernel.org>
  M:    Daniel Borkmann <daniel@iogearbox.net>
@@@ -3199,7 -3148,7 +3199,7 @@@ S:      Maintaine
  F:    arch/mips/net/
  
  BPF JIT for NFP NICs
 -M:    Jakub Kicinski <jakub.kicinski@netronome.com>
 +M:    Jakub Kicinski <kuba@kernel.org>
  L:    netdev@vger.kernel.org
  L:    bpf@vger.kernel.org
  S:    Supported
@@@ -3289,6 -3238,8 +3289,8 @@@ S:      Maintaine
  N:    bcm2711
  N:    bcm2835
  F:    drivers/staging/vc04_services
+ F:    Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+ F:    drivers/pci/controller/pcie-brcmstb.c
  
  BROADCOM BCM47XX MIPS ARCHITECTURE
  M:    Hauke Mehrtens <hauke@hauke-m.de>
@@@ -3344,6 -3295,8 +3346,8 @@@ F:      drivers/bus/brcmstb_gisb.
  F:    arch/arm/mm/cache-b15-rac.c
  F:    arch/arm/include/asm/hardware/cache-b15-rac.h
  N:    brcmstb
+ F:    Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+ F:    drivers/pci/controller/pcie-brcmstb.c
  
  BROADCOM BMIPS CPUFREQ DRIVER
  M:    Markus Mayer <mmayer@broadcom.com>
@@@ -4479,10 -4432,13 +4483,10 @@@ F:   drivers/net/wireless/st/cw1200
  
  CX18 VIDEO4LINUX DRIVER
  M:    Andy Walls <awalls@md.metrocast.net>
 -L:    ivtv-devel@ivtvdriver.org (subscribers-only)
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  W:    https://linuxtv.org
 -W:    http://www.ivtvdriver.org/index.php/Cx18
  S:    Maintained
 -F:    Documentation/media/v4l-drivers/cx18*
  F:    drivers/media/pci/cx18/
  F:    include/uapi/linux/ivtv*
  
@@@ -4894,7 -4850,6 +4898,7 @@@ S:      Supporte
  F:    net/core/devlink.c
  F:    include/net/devlink.h
  F:    include/uapi/linux/devlink.h
 +F:    Documentation/networking/devlink
  
  DIALOG SEMICONDUCTOR DRIVERS
  M:    Support Opensource <support.opensource@diasemi.com>
@@@ -5023,24 -4978,6 +5027,24 @@@ F:    Documentation/driver-api/dma-buf.rs
  K:    dma_(buf|fence|resv)
  T:    git git://anongit.freedesktop.org/drm/drm-misc
  
 +DMA-BUF HEAPS FRAMEWORK
 +M:    Sumit Semwal <sumit.semwal@linaro.org>
 +R:    Andrew F. Davis <afd@ti.com>
 +R:    Benjamin Gaignard <benjamin.gaignard@linaro.org>
 +R:    Liam Mark <lmark@codeaurora.org>
 +R:    Laura Abbott <labbott@redhat.com>
 +R:    Brian Starkey <Brian.Starkey@arm.com>
 +R:    John Stultz <john.stultz@linaro.org>
 +S:    Maintained
 +L:    linux-media@vger.kernel.org
 +L:    dri-devel@lists.freedesktop.org
 +L:    linaro-mm-sig@lists.linaro.org (moderated for non-subscribers)
 +F:    include/uapi/linux/dma-heap.h
 +F:    include/linux/dma-heap.h
 +F:    drivers/dma-buf/dma-heap.c
 +F:    drivers/dma-buf/heaps/*
 +T:    git git://anongit.freedesktop.org/drm/drm-misc
 +
  DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
  M:    Vinod Koul <vkoul@kernel.org>
  L:    dmaengine@vger.kernel.org
@@@ -5246,12 -5183,6 +5250,12 @@@ T:    git git://anongit.freedesktop.org/dr
  S:    Maintained
  F:    drivers/gpu/drm/bochs/
  
 +DRM DRIVER FOR BOE HIMAX8279D PANELS
 +M:    Jerry Han <hanxu5@huaqin.corp-partner.google.com>
 +S:    Maintained
 +F:    drivers/gpu/drm/panel/panel-boe-himax8279d.c
 +F:    Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt
 +
  DRM DRIVER FOR FARADAY TVE200 TV ENCODER
  M:    Linus Walleij <linus.walleij@linaro.org>
  T:    git git://anongit.freedesktop.org/drm/drm-misc
@@@ -5407,12 -5338,6 +5411,12 @@@ S:    Maintaine
  F:    drivers/gpu/drm/tiny/st7735r.c
  F:    Documentation/devicetree/bindings/display/sitronix,st7735r.txt
  
 +DRM DRIVER FOR SONY ACX424AKP PANELS
 +M:    Linus Walleij <linus.walleij@linaro.org>
 +T:    git git://anongit.freedesktop.org/drm/drm-misc
 +S:    Maintained
 +F:    drivers/gpu/drm/panel/panel-sony-acx424akp.c
 +
  DRM DRIVER FOR ST-ERICSSON MCDE
  M:    Linus Walleij <linus.walleij@linaro.org>
  T:    git git://anongit.freedesktop.org/drm/drm-misc
@@@ -5485,6 -5410,7 +5489,6 @@@ F:      include/linux/vga
  DRM DRIVERS AND MISC GPU PATCHES
  M:    Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
  M:    Maxime Ripard <mripard@kernel.org>
 -M:    Sean Paul <sean@poorly.run>
  W:    https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html
  S:    Maintained
  T:    git git://anongit.freedesktop.org/drm/drm-misc
@@@ -6231,12 -6157,6 +6235,12 @@@ M:    Maxim Levitsky <maximlevitsky@gmail.
  S:    Maintained
  F:    drivers/media/rc/ene_ir.*
  
 +EPAPR HYPERVISOR BYTE CHANNEL DEVICE DRIVER
 +M:    Laurentiu Tudor <laurentiu.tudor@nxp.com>
 +L:    linuxppc-dev@lists.ozlabs.org
 +S:    Maintained
 +F:    drivers/tty/ehv_bytechan.c
 +
  EPSON S1D13XXX FRAMEBUFFER DRIVER
  M:    Kristoffer Ericson <kristoffer.ericson@gmail.com>
  S:    Maintained
@@@ -6279,7 -6199,6 +6283,7 @@@ ETHERNET PHY LIBRAR
  M:    Andrew Lunn <andrew@lunn.ch>
  M:    Florian Fainelli <f.fainelli@gmail.com>
  M:    Heiner Kallweit <hkallweit1@gmail.com>
 +R:    Russell King <linux@armlinux.org.uk>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    Documentation/ABI/testing/sysfs-class-net-phydev
@@@ -6485,7 -6404,6 +6489,7 @@@ F:      fs/
  F:    include/linux/fs.h
  F:    include/linux/fs_types.h
  F:    include/uapi/linux/fs.h
 +F:    include/uapi/linux/openat2.h
  
  FINTEK F75375S HARDWARE MONITOR AND FAN CONTROLLER DRIVER
  M:    Riku Voipio <riku.voipio@iki.fi>
@@@ -6904,7 -6822,7 +6908,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
  S:    Maintained
  F:    fs/fuse/
  F:    include/uapi/linux/fuse.h
 -F:    Documentation/filesystems/fuse.txt
 +F:    Documentation/filesystems/fuse.rst
  
  FUTEX SUBSYSTEM
  M:    Thomas Gleixner <tglx@linutronix.de>
@@@ -7379,7 -7297,6 +7383,7 @@@ F:      drivers/hwtracing
  HARDWARE SPINLOCK CORE
  M:    Ohad Ben-Cohen <ohad@wizery.com>
  M:    Bjorn Andersson <bjorn.andersson@linaro.org>
 +R:    Baolin Wang <baolin.wang7@gmail.com>
  L:    linux-remoteproc@vger.kernel.org
  S:    Maintained
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git hwspinlock-next
@@@ -7583,12 -7500,6 +7587,12 @@@ S:    Supporte
  F:    drivers/scsi/hisi_sas/
  F:    Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
  
 +HISILICON V3XX SPI NOR FLASH Controller Driver
 +M:    John Garry <john.garry@huawei.com>
 +W:    http://www.hisilicon.com
 +S:    Maintained
 +F:    drivers/spi/spi-hisi-sfc-v3xx.c
 +
  HISILICON QM AND ZIP Controller DRIVER
  M:    Zhou Wang <wangzhou1@hisilicon.com>
  L:    linux-crypto@vger.kernel.org
@@@ -7659,8 -7570,9 +7663,8 @@@ S:      Orpha
  F:    drivers/net/usb/hso.c
  
  HSR NETWORK PROTOCOL
 -M:    Arvid Brodin <arvid.brodin@alten.se>
  L:    netdev@vger.kernel.org
 -S:    Maintained
 +S:    Orphan
  F:    net/hsr/
  
  HT16K33 LED CONTROLLER DRIVER
@@@ -7815,7 -7727,9 +7819,7 @@@ M:      Jean Delvare <jdelvare@suse.com
  L:    linux-i2c@vger.kernel.org
  S:    Maintained
  F:    Documentation/i2c/busses/i2c-parport.rst
 -F:    Documentation/i2c/busses/i2c-parport-light.rst
  F:    drivers/i2c/busses/i2c-parport.c
 -F:    drivers/i2c/busses/i2c-parport-light.c
  
  I2C SUBSYSTEM
  M:    Wolfram Sang <wsa@the-dreams.de>
@@@ -7929,10 -7843,10 +7933,10 @@@ F:   Documentation/devicetree/bindings/i3
  F:    drivers/i3c/master/dw*
  
  I3C DRIVER FOR CADENCE I3C MASTER IP
 -M:      Przemysław Gaj <pgaj@cadence.com>
 -S:      Maintained
 -F:      Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt
 -F:      drivers/i3c/master/i3c-master-cdns.c
 +M:    Przemysław Gaj <pgaj@cadence.com>
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt
 +F:    drivers/i3c/master/i3c-master-cdns.c
  
  IA64 (Itanium) PLATFORM
  M:    Tony Luck <tony.luck@intel.com>
@@@ -8196,7 -8110,8 +8200,7 @@@ F:      Documentation/devicetree/bindings/au
  F:    drivers/auxdisplay/img-ascii-lcd.c
  
  IMGTEC IR DECODER DRIVER
 -M:    James Hogan <jhogan@kernel.org>
 -S:    Maintained
 +S:    Orphan
  F:    drivers/media/rc/img-ir/
  
  IMON SOUNDGRAPH USB IR RECEIVER
@@@ -8437,6 -8352,7 +8441,6 @@@ S:      Maintaine
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
  F:    drivers/gpio/gpio-ich.c
  F:    drivers/gpio/gpio-intel-mid.c
 -F:    drivers/gpio/gpio-lynxpoint.c
  F:    drivers/gpio/gpio-merrifield.c
  F:    drivers/gpio/gpio-ml-ioh.c
  F:    drivers/gpio/gpio-pch.c
@@@ -8467,14 -8383,6 +8471,14 @@@ Q:    https://patchwork.kernel.org/project
  S:    Supported
  F:    drivers/dma/ioat*
  
 +INTEL IADX DRIVER
 +M:    Dave Jiang <dave.jiang@intel.com>
 +L:    dmaengine@vger.kernel.org
 +S:    Supported
 +F:    drivers/dma/idxd/*
 +F:    include/uapi/linux/idxd.h
 +F:    include/linux/idxd.h
 +
  INTEL IDLE DRIVER
  M:    Jacob Pan <jacob.jun.pan@linux.intel.com>
  M:    Len Brown <lenb@kernel.org>
@@@ -8656,12 -8564,6 +8660,12 @@@ S:    Maintaine
  F:    arch/x86/include/asm/intel_telemetry.h
  F:    drivers/platform/x86/intel_telemetry*
  
 +INTEL UNCORE FREQUENCY CONTROL
 +M:    Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
 +L:    platform-driver-x86@vger.kernel.org
 +S:    Maintained
 +F:    drivers/platform/x86/intel-uncore-frequency.c
 +
  INTEL VIRTUAL BUTTON DRIVER
  M:    AceLan Kao <acelan.kao@canonical.com>
  L:    platform-driver-x86@vger.kernel.org
@@@ -8669,7 -8571,7 +8673,7 @@@ S:      Maintaine
  F:    drivers/platform/x86/intel-vbtn.c
  
  INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy)
 -M:    Stanislaw Gruszka <sgruszka@redhat.com>
 +M:    Stanislaw Gruszka <stf_xl@wp.pl>
  L:    linux-wireless@vger.kernel.org
  S:    Supported
  F:    drivers/net/wireless/intel/iwlegacy/
@@@ -8907,12 -8809,10 +8911,12 @@@ L:   isdn4linux@listserv.isdn4linux.de (s
  L:    netdev@vger.kernel.org
  W:    http://www.isdn4linux.de
  S:    Maintained
 -F:    drivers/isdn/mISDN
 -F:    drivers/isdn/hardware
 +F:    drivers/isdn/mISDN/
 +F:    drivers/isdn/hardware/
 +F:    drivers/isdn/Kconfig
 +F:    drivers/isdn/Makefile
  
 -ISDN/CAPI SUBSYSTEM
 +ISDN/CMTP OVER BLUETOOTH
  M:    Karsten Keil <isdn@linux-pingi.de>
  L:    isdn4linux@listserv.isdn4linux.de (subscribers-only)
  L:    netdev@vger.kernel.org
@@@ -8920,6 -8820,7 +8924,6 @@@ W:      http://www.isdn4linux.d
  S:    Odd Fixes
  F:    Documentation/isdn/
  F:    drivers/isdn/capi/
 -F:    drivers/staging/isdn/
  F:    net/bluetooth/cmtp/
  F:    include/linux/isdn/
  F:    include/uapi/linux/isdn/
@@@ -8943,9 -8844,10 +8947,9 @@@ F:     drivers/media/tuners/it913x
  
  IVTV VIDEO4LINUX DRIVER
  M:    Andy Walls <awalls@md.metrocast.net>
 -L:    ivtv-devel@ivtvdriver.org (subscribers-only)
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
 -W:    http://www.ivtvdriver.org
 +W:    https://linuxtv.org
  S:    Maintained
  F:    Documentation/media/v4l-drivers/ivtv*
  F:    drivers/media/pci/ivtv/
@@@ -9232,7 -9134,7 +9236,7 @@@ F:      arch/x86/include/uapi/asm/svm.
  F:    arch/x86/include/asm/kvm*
  F:    arch/x86/include/asm/pvclock-abi.h
  F:    arch/x86/include/asm/svm.h
 -F:    arch/x86/include/asm/vmx.h
 +F:    arch/x86/include/asm/vmx*.h
  F:    arch/x86/kernel/kvm.c
  F:    arch/x86/kernel/kvmclock.c
  
@@@ -9681,7 -9583,6 +9685,7 @@@ LINUX KERNEL DUMP TEST MODULE (LKDTM
  M:    Kees Cook <keescook@chromium.org>
  S:    Maintained
  F:    drivers/misc/lkdtm/*
 +F:    tools/testing/selftests/lkdtm/*
  
  LINUX KERNEL MEMORY CONSISTENCY MODEL (LKMM)
  M:    Alan Stern <stern@rowland.harvard.edu>
@@@ -9990,7 -9891,7 +9994,7 @@@ S:      Maintaine
  F:    drivers/net/dsa/mv88e6xxx/
  F:    include/linux/platform_data/mv88e6xxx.h
  F:    Documentation/devicetree/bindings/net/dsa/marvell.txt
 -F:    Documentation/networking/devlink-params-mv88e6xxx.txt
 +F:    Documentation/networking/devlink/mv88e6xxx.rst
  
  MARVELL ARMADA DRM SUPPORT
  M:    Russell King <linux@armlinux.org.uk>
@@@ -10060,7 -9961,8 +10064,7 @@@ F:    drivers/net/ethernet/marvell/mvneta.
  
  MARVELL MWIFIEX WIRELESS DRIVER
  M:    Amitkumar Karwar <amitkarwar@gmail.com>
 -M:    Nishant Sarmukadam <nishants@marvell.com>
 -M:    Ganapathi Bhat <gbhat@marvell.com>
 +M:    Ganapathi Bhat <ganapathi.bhat@nxp.com>
  M:    Xinming Hu <huxinming820@gmail.com>
  L:    linux-wireless@vger.kernel.org
  S:    Maintained
@@@ -10099,16 -10001,6 +10103,16 @@@ M: Jerin Jacob <jerinj@marvell.com
  L:    netdev@vger.kernel.org
  S:    Supported
  F:    drivers/net/ethernet/marvell/octeontx2/af/
 +F:    Documentation/networking/device_drivers/marvell/octeontx2.rst
 +
 +MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER
 +M:    Sunil Goutham <sgoutham@marvell.com>
 +M:    Geetha sowjanya <gakula@marvell.com>
 +M:    Subbaraya Sundeep <sbhatta@marvell.com>
 +M:    hariprasad <hkelam@marvell.com>
 +L:    netdev@vger.kernel.org
 +S:    Supported
 +F:    drivers/net/ethernet/marvell/octeontx2/nic/
  
  MATROX FRAMEBUFFER DRIVER
  L:    linux-fbdev@vger.kernel.org
@@@ -10391,7 -10283,7 +10395,7 @@@ L:   linux-media@vger.kernel.or
  L:    linux-renesas-soc@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  S:    Supported
 -F:    Documentation/devicetree/bindings/media/renesas,ceu.txt
 +F:    Documentation/devicetree/bindings/media/renesas,ceu.yaml
  F:    drivers/media/platform/renesas-ceu.c
  F:    include/media/drv-intf/renesas-ceu.h
  
@@@ -10429,7 -10321,7 +10433,7 @@@ L:   linux-media@vger.kernel.or
  L:    linux-renesas-soc@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  S:    Supported
 -F:    Documentation/devicetree/bindings/media/renesas,csi2.txt
 +F:    Documentation/devicetree/bindings/media/renesas,csi2.yaml
  F:    Documentation/devicetree/bindings/media/renesas,vin.txt
  F:    drivers/media/platform/rcar-vin/
  
@@@ -11112,6 -11004,7 +11116,6 @@@ F:   drivers/usb/image/microtek.
  MIPS
  M:    Ralf Baechle <ralf@linux-mips.org>
  M:    Paul Burton <paulburton@kernel.org>
 -M:    James Hogan <jhogan@kernel.org>
  L:    linux-mips@vger.kernel.org
  W:    http://www.linux-mips.org/
  T:    git git://git.linux-mips.org/pub/scm/ralf/linux.git
@@@ -11252,13 -11145,6 +11256,13 @@@ S: Maintaine
  F:    Documentation/driver-api/serial/moxa-smartio.rst
  F:    drivers/tty/mxser.*
  
 +MONOLITHIC POWER SYSTEM PMIC DRIVER
 +M:    Saravanan Sekar <sravanhome@gmail.com>
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/regulator/mpq7920.yaml
 +F:    drivers/regulator/mpq7920.c
 +F:    drivers/regulator/mpq7920.h
 +
  MR800 AVERMEDIA USB FM RADIO DRIVER
  M:    Alexey Klimov <klimov.linux@gmail.com>
  L:    linux-media@vger.kernel.org
@@@ -11502,7 -11388,7 +11506,7 @@@ F:   Documentation/networking/net_failove
  
  NETEM NETWORK EMULATOR
  M:    Stephen Hemminger <stephen@networkplumber.org>
 -L:    netem@lists.linux-foundation.org (moderated for non-subscribers)
 +L:    netdev@vger.kernel.org
  S:    Maintained
  F:    net/sched/sch_netem.c
  
@@@ -11547,7 -11433,7 +11551,7 @@@ F:   include/uapi/linux/netrom.
  F:    net/netrom/
  
  NETRONOME ETHERNET DRIVERS
 -M:    Jakub Kicinski <jakub.kicinski@netronome.com>
 +M:    Jakub Kicinski <kuba@kernel.org>
  L:    oss-drivers@netronome.com
  S:    Maintained
  F:    drivers/net/ethernet/netronome/
@@@ -11576,8 -11462,8 +11580,8 @@@ M:   "David S. Miller" <davem@davemloft.n
  L:    netdev@vger.kernel.org
  W:    http://www.linuxfoundation.org/en/Net
  Q:    http://patchwork.ozlabs.org/project/netdev/list/
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
  S:    Odd Fixes
  F:    Documentation/devicetree/bindings/net/
  F:    drivers/net/
@@@ -11615,12 -11501,11 +11619,12 @@@ F:        drivers/net/dsa
  
  NETWORKING [GENERAL]
  M:    "David S. Miller" <davem@davemloft.net>
 +M:    Jakub Kicinski <kuba@kernel.org>
  L:    netdev@vger.kernel.org
  W:    http://www.linuxfoundation.org/en/Net
  Q:    http://patchwork.ozlabs.org/project/netdev/list/
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
  B:    mailto:netdev@vger.kernel.org
  S:    Maintained
  F:    net/
@@@ -11665,7 -11550,7 +11669,7 @@@ M:   "David S. Miller" <davem@davemloft.n
  M:    Alexey Kuznetsov <kuznet@ms2.inr.ac.ru>
  M:    Hideaki YOSHIFUJI <yoshfuji@linux-ipv6.org>
  L:    netdev@vger.kernel.org
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
  S:    Maintained
  F:    net/ipv4/
  F:    net/ipv6/
@@@ -11690,18 -11575,6 +11694,18 @@@ F: net/ipv6/calipso.
  F:    net/netfilter/xt_CONNSECMARK.c
  F:    net/netfilter/xt_SECMARK.c
  
 +NETWORKING [MPTCP]
 +M:    Mat Martineau <mathew.j.martineau@linux.intel.com>
 +M:    Matthieu Baerts <matthieu.baerts@tessares.net>
 +L:    netdev@vger.kernel.org
 +L:    mptcp@lists.01.org
 +W:    https://github.com/multipath-tcp/mptcp_net-next/wiki
 +B:    https://github.com/multipath-tcp/mptcp_net-next/issues
 +S:    Maintained
 +F:    include/net/mptcp.h
 +F:    net/mptcp/
 +F:    tools/testing/selftests/net/mptcp/
 +
  NETWORKING [TCP]
  M:    Eric Dumazet <edumazet@google.com>
  L:    netdev@vger.kernel.org
@@@ -11720,7 -11593,7 +11724,7 @@@ M:   Boris Pismenny <borisp@mellanox.com
  M:    Aviad Yehezkel <aviadye@mellanox.com>
  M:    John Fastabend <john.fastabend@gmail.com>
  M:    Daniel Borkmann <daniel@iogearbox.net>
 -M:    Jakub Kicinski <jakub.kicinski@netronome.com>
 +M:    Jakub Kicinski <kuba@kernel.org>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    net/tls/*
@@@ -11732,7 -11605,7 +11736,7 @@@ L:   linux-wireless@vger.kernel.or
  Q:    http://patchwork.kernel.org/project/linux-wireless/list/
  
  NETDEVSIM
 -M:    Jakub Kicinski <jakub.kicinski@netronome.com>
 +M:    Jakub Kicinski <kuba@kernel.org>
  S:    Maintained
  F:    drivers/net/netdevsim/*
  
@@@ -11809,7 -11682,7 +11813,7 @@@ F:   Documentation/scsi/NinjaSCSI.tx
  F:    drivers/scsi/nsp32*
  
  NIOS2 ARCHITECTURE
 -M:    Ley Foon Tan <lftan@altera.com>
 +M:    Ley Foon Tan <ley.foon.tan@intel.com>
  L:    nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git
  S:    Maintained
@@@ -12560,7 -12433,7 +12564,7 @@@ L:   linux-crypto@vger.kernel.or
  S:    Maintained
  F:    kernel/padata.c
  F:    include/linux/padata.h
 -F:    Documentation/padata.txt
 +F:    Documentation/core-api/padata.rst
  
  PAGE POOL
  M:    Jesper Dangaard Brouer <hawk@kernel.org>
@@@ -12576,13 -12449,6 +12580,13 @@@ L: platform-driver-x86@vger.kernel.or
  S:    Maintained
  F:    drivers/platform/x86/panasonic-laptop.c
  
 +PARALLAX PING IIO SENSOR DRIVER
 +M:    Andreas Klinger <ak@it-klinger.de>
 +L:    linux-iio@vger.kernel.org
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml
 +F:    drivers/iio/proximity/ping.c
 +
  PARALLEL LCD/KEYPAD PANEL DRIVER
  M:    Willy Tarreau <willy@haproxy.com>
  M:    Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
@@@ -12700,7 -12566,7 +12704,7 @@@ F:   Documentation/devicetree/bindings/pc
  F:    drivers/pci/controller/pci-aardvark.c
  
  PCI DRIVER FOR ALTERA PCIE IP
 -M:    Ley Foon Tan <lftan@altera.com>
 +M:    Ley Foon Tan <ley.foon.tan@intel.com>
  L:    rfi@lists.rocketboards.org (moderated for non-subscribers)
  L:    linux-pci@vger.kernel.org
  S:    Supported
@@@ -12720,7 -12586,7 +12724,7 @@@ M:   Rob Herring <robh@kernel.org
  L:    linux-pci@vger.kernel.org
  L:    linux-arm-kernel@lists.infradead.org
  S:    Maintained
 -F:    Documentation/devicetree/bindings/pci/versatile.txt
 +F:    Documentation/devicetree/bindings/pci/versatile.yaml
  F:    drivers/pci/controller/pci-versatile.c
  
  PCI DRIVER FOR ARMADA 8K
@@@ -12753,7 -12619,7 +12757,7 @@@ M:   Will Deacon <will@kernel.org
  L:    linux-pci@vger.kernel.org
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
 -F:    Documentation/devicetree/bindings/pci/host-generic-pci.txt
 +F:    Documentation/devicetree/bindings/pci/host-generic-pci.yaml
  F:    drivers/pci/controller/pci-host-common.c
  F:    drivers/pci/controller/pci-host-generic.c
  
@@@ -12879,7 -12745,7 +12883,7 @@@ S:   Supporte
  F:    Documentation/PCI/pci-error-recovery.rst
  
  PCI MSI DRIVER FOR ALTERA MSI IP
 -M:    Ley Foon Tan <lftan@altera.com>
 +M:    Ley Foon Tan <ley.foon.tan@intel.com>
  L:    rfi@lists.rocketboards.org (moderated for non-subscribers)
  L:    linux-pci@vger.kernel.org
  S:    Supported
@@@ -12915,7 -12781,7 +12919,7 @@@ F:   arch/x86/kernel/early-quirks.
  
  PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
  M:    Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
 -R:    Andrew Murray <andrew.murray@arm.com>
 +R:    Andrew Murray <amurray@thegoodpenguin.co.uk>
  L:    linux-pci@vger.kernel.org
  Q:    http://patchwork.ozlabs.org/project/linux-pci/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
@@@ -13280,11 -13146,6 +13284,11 @@@ S: Maintaine
  F:    drivers/iio/chemical/pms7003.c
  F:    Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml
  
 +PLX DMA DRIVER
 +M:    Logan Gunthorpe <logang@deltatee.com>
 +S:    Maintained
 +F:    drivers/dma/plx_dma.c
 +
  PMBUS HARDWARE MONITORING DRIVERS
  M:    Guenter Roeck <linux@roeck-us.net>
  L:    linux-hwmon@vger.kernel.org
@@@ -13336,6 -13197,11 +13340,6 @@@ T:  git git://github.com/intel/pm-grap
  S:    Supported
  F:    tools/power/pm-graph
  
 -PNP SUPPORT
 -M:    "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
 -S:    Maintained
 -F:    drivers/pnp/
 -
  PNI RM3100 IIO DRIVER
  M:    Song Qiang <songqiang1304521@gmail.com>
  L:    linux-iio@vger.kernel.org
@@@ -13343,11 -13209,6 +13347,11 @@@ S: Maintaine
  F:    drivers/iio/magnetometer/rm3100*
  F:    Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt
  
 +PNP SUPPORT
 +M:    "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
 +S:    Maintained
 +F:    drivers/pnp/
 +
  POSIX CLOCKS and TIMERS
  M:    Thomas Gleixner <tglx@linutronix.de>
  L:    linux-kernel@vger.kernel.org
@@@ -13355,8 -13216,6 +13359,8 @@@ T:   git git://git.kernel.org/pub/scm/lin
  S:    Maintained
  F:    fs/timerfd.c
  F:    include/linux/timer*
 +F:    include/linux/time_namespace.h
 +F:    kernel/time_namespace.c
  F:    kernel/time/*timer*
  
  POWER MANAGEMENT CORE
@@@ -13792,13 -13651,6 +13796,13 @@@ T: git git://git.kernel.org/pub/scm/lin
  S:    Supported
  F:    drivers/net/wireless/ath/ath10k/
  
 +QUALCOMM ATHEROS ATH11K WIRELESS DRIVER
 +M:    Kalle Valo <kvalo@codeaurora.org>
 +L:    ath11k@lists.infradead.org
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
 +S:    Supported
 +F:    drivers/net/wireless/ath/ath11k/
 +
  QUALCOMM ATHEROS ATH9K WIRELESS DRIVER
  M:    QCA ath9k Development <ath9k-devel@qca.qualcomm.com>
  L:    linux-wireless@vger.kernel.org
@@@ -13821,14 -13673,6 +13825,14 @@@ S: Maintaine
  F:    Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
  F:    drivers/cpufreq/qcom-cpufreq-nvmem.c
  
 +QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
 +M:    Niklas Cassel <nks@flawful.org>
 +L:    linux-pm@vger.kernel.org
 +L:    linux-arm-msm@vger.kernel.org
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
 +F:    drivers/power/avs/qcom-cpr.c
 +
  QUALCOMM EMAC GIGABIT ETHERNET DRIVER
  M:    Timur Tabi <timur@kernel.org>
  L:    netdev@vger.kernel.org
@@@ -13837,6 -13681,7 +13841,6 @@@ F:   drivers/net/ethernet/qualcomm/emac
  
  QUALCOMM ETHQOS ETHERNET DRIVER
  M:    Vinod Koul <vkoul@kernel.org>
 -M:    Niklas Cassel <niklas.cassel@linaro.org>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@@ -13978,7 -13823,7 +13982,7 @@@ S:   Maintaine
  F:    arch/mips/ralink
  
  RALINK RT2X00 WIRELESS LAN DRIVER
 -M:    Stanislaw Gruszka <sgruszka@redhat.com>
 +M:    Stanislaw Gruszka <stf_xl@wp.pl>
  M:    Helmut Schaa <helmut.schaa@googlemail.com>
  L:    linux-wireless@vger.kernel.org
  S:    Maintained
@@@ -14105,6 -13950,7 +14109,6 @@@ F:   include/linux/platform_data/rtc-
  F:    tools/testing/selftests/rtc/
  
  REALTEK AUDIO CODECS
 -M:    Bard Liao <bardliao@realtek.com>
  M:    Oder Chiou <oder_chiou@realtek.com>
  S:    Maintained
  F:    sound/soc/codecs/rt*
@@@ -14277,7 -14123,6 +14281,7 @@@ M:   Paul Walmsley <paul.walmsley@sifive.
  M:    Palmer Dabbelt <palmer@dabbelt.com>
  M:    Albert Ou <aou@eecs.berkeley.edu>
  L:    linux-riscv@lists.infradead.org
 +P:    Documentation/riscv/patch-acceptance.rst
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
  S:    Supported
  F:    arch/riscv/
@@@ -14292,12 -14137,6 +14296,12 @@@ F: drivers/hid/hid-roccat
  F:    include/linux/hid-roccat*
  F:    Documentation/ABI/*/sysfs-driver-hid-roccat*
  
 +ROCKCHIP ISP V1 DRIVER
 +M:    Helen Koike <helen.koike@collabora.com>
 +L:    linux-media@vger.kernel.org
 +S:    Maintained
 +F:    drivers/staging/media/rkisp1/
 +
  ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
  M:    Jacob Chen <jacob-chen@iotwrt.com>
  M:    Ezequiel Garcia <ezequiel@collabora.com>
@@@ -14669,7 -14508,7 +14673,7 @@@ F:   drivers/media/i2c/s5k5baf.
  SAMSUNG S5P Security SubSystem (SSS) DRIVER
  M:    Krzysztof Kozlowski <krzk@kernel.org>
  M:    Vladimir Zapolskiy <vz@mleia.com>
 -M:    Kamil Konieczny <k.konieczny@partner.samsung.com>
 +M:    Kamil Konieczny <k.konieczny@samsung.com>
  L:    linux-crypto@vger.kernel.org
  L:    linux-samsung-soc@vger.kernel.org
  S:    Maintained
@@@ -14711,6 -14550,8 +14715,6 @@@ F:   include/linux/platform_data/spi-s3c6
  
  SAMSUNG SXGBE DRIVERS
  M:    Byungho An <bh74.an@samsung.com>
 -M:    Girish K S <ks.giri@samsung.com>
 -M:    Vipul Pandya <vipul.pandya@samsung.com>
  S:    Supported
  L:    netdev@vger.kernel.org
  F:    drivers/net/ethernet/samsung/sxgbe/
@@@ -14945,8 -14786,8 +14949,8 @@@ S:   Maintaine
  F:    drivers/mmc/host/sdhci-omap.c
  
  SECURE ENCRYPTING DEVICE (SED) OPAL DRIVER
 -M:    Scott Bauer <scott.bauer@intel.com>
  M:    Jonathan Derrick <jonathan.derrick@intel.com>
 +M:    Revanth Rajashekar <revanth.rajashekar@intel.com>
  L:    linux-block@vger.kernel.org
  S:    Supported
  F:    block/sed*
@@@ -14981,7 -14822,6 +14985,7 @@@ F:   include/uapi/linux/selinux_netlink.
  F:    security/selinux/
  F:    scripts/selinux/
  F:    Documentation/admin-guide/LSM/SELinux.rst
 +F:    Documentation/ABI/obsolete/sysfs-selinux-disable
  
  SENSABLE PHANTOM
  M:    Jiri Slaby <jirislaby@gmail.com>
@@@ -15208,8 -15048,11 +15212,8 @@@ F:  drivers/video/fbdev/sm712
  F:    Documentation/fb/sm712fb.rst
  
  SIMPLE FIRMWARE INTERFACE (SFI)
 -M:    Len Brown <lenb@kernel.org>
 -L:    sfi-devel@simplefirmware.org
  W:    http://simplefirmware.org/
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-sfi-2.6.git
 -S:    Supported
 +S:    Obsolete
  F:    arch/x86/platform/sfi/
  F:    drivers/sfi/
  F:    include/linux/sfi*.h
@@@ -15929,18 -15772,8 +15933,18 @@@ M: Jose Abreu <joabreu@synopsys.com
  L:    netdev@vger.kernel.org
  W:    http://www.stlinux.com
  S:    Supported
 +F:    Documentation/networking/device_drivers/stmicro/
  F:    drivers/net/ethernet/stmicro/stmmac/
  
 +EXTRA BOOT CONFIG
 +M:    Masami Hiramatsu <mhiramat@kernel.org>
 +S:    Maintained
 +F:    lib/bootconfig.c
 +F:    fs/proc/bootconfig.c
 +F:    include/linux/bootconfig.h
 +F:    tools/bootconfig/*
 +F:    Documentation/admin-guide/bootconfig.rst
 +
  SUN3/3X
  M:    Sam Creasey <sammy@sammy.net>
  W:    http://sammy.net/sun3/
@@@ -16148,6 -15981,7 +16152,7 @@@ F:   drivers/firmware/arm_scpi.
  F:    drivers/firmware/arm_scmi/
  F:    drivers/reset/reset-scmi.c
  F:    include/linux/sc[mp]i_protocol.h
+ F:    include/trace/events/scmi.h
  
  SYSTEM RESET/SHUTDOWN DRIVERS
  M:    Sebastian Reichel <sre@kernel.org>
@@@ -16511,15 -16345,12 +16516,15 @@@ F:        Documentation/devicetree/bindings/th
  
  THERMAL/CPU_COOLING
  M:    Amit Daniel Kachhap <amit.kachhap@gmail.com>
 +M:    Daniel Lezcano <daniel.lezcano@linaro.org>
  M:    Viresh Kumar <viresh.kumar@linaro.org>
  M:    Javi Merino <javi.merino@kernel.org>
  L:    linux-pm@vger.kernel.org
  S:    Supported
  F:    Documentation/driver-api/thermal/cpu-cooling-api.rst
 -F:    drivers/thermal/cpu_cooling.c
 +F:    Documentation/driver-api/thermal/cpu-idle-cooling.rst
 +F:    drivers/thermal/cpufreq_cooling.c
 +F:    drivers/thermal/cpuidle_cooling.c
  F:    include/linux/cpu_cooling.h
  
  THERMAL DRIVER FOR AMLOGIC SOCS
@@@ -16546,7 -16377,6 +16551,7 @@@ M:   Andreas Noever <andreas.noever@gmail
  M:    Michael Jamet <michael.jamet@intel.com>
  M:    Mika Westerberg <mika.westerberg@linux.intel.com>
  M:    Yehezkel Bernat <YehezkelShB@gmail.com>
 +L:    linux-usb@vger.kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git
  S:    Maintained
  F:    Documentation/admin-guide/thunderbolt.rst
@@@ -16747,7 -16577,6 +16752,7 @@@ Q:   http://patchwork.linuxtv.org/project
  S:    Maintained
  F:    drivers/media/platform/ti-vpe/
  F:    Documentation/devicetree/bindings/media/ti,vpe.yaml
 +      Documentation/devicetree/bindings/media/ti,cal.yaml
  
  TI WILINK WIRELESS DRIVERS
  L:    linux-wireless@vger.kernel.org
@@@ -16777,7 -16606,7 +16782,7 @@@ F:   kernel/time/ntp.
  F:    tools/testing/selftests/timers/
  
  TIPC NETWORK LAYER
 -M:    Jon Maloy <jon.maloy@ericsson.com>
 +M:    Jon Maloy <jmaloy@redhat.com>
  M:    Ying Xue <ying.xue@windriver.com>
  L:    netdev@vger.kernel.org (core kernel code)
  L:    tipc-discussion@lists.sourceforge.net (user apps, general discussion)
@@@ -17550,7 -17379,7 +17555,7 @@@ F:   drivers/mtd/nand/raw/vf610_nfc.
  VFAT/FAT/MSDOS FILESYSTEM
  M:    OGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
  S:    Maintained
 -F:    Documentation/filesystems/vfat.txt
 +F:    Documentation/filesystems/vfat.rst
  F:    fs/fat/
  
  VFIO DRIVER
@@@ -17673,7 -17502,6 +17678,7 @@@ F:   net/vmw_vsock/diag.
  F:    net/vmw_vsock/af_vsock_tap.c
  F:    net/vmw_vsock/virtio_transport_common.c
  F:    net/vmw_vsock/virtio_transport.c
 +F:    net/vmw_vsock/vsock_loopback.c
  F:    drivers/net/vsockmon.c
  F:    drivers/vhost/vsock.c
  F:    tools/testing/vsock/
@@@ -18044,14 -17872,6 +18049,14 @@@ L: linux-gpio@vger.kernel.or
  S:    Maintained
  F:    drivers/gpio/gpio-ws16c48.c
  
 +WIREGUARD SECURE NETWORK TUNNEL
 +M:    Jason A. Donenfeld <Jason@zx2c4.com>
 +S:    Maintained
 +F:    drivers/net/wireguard/
 +F:    tools/testing/selftests/wireguard/
 +L:    wireguard@lists.zx2c4.com
 +L:    netdev@vger.kernel.org
 +
  WISTRON LAPTOP BUTTON DRIVER
  M:    Miloslav Trmac <mitr@volny.cz>
  S:    Maintained
@@@ -18115,8 -17935,8 +18120,8 @@@ F:   Documentation/core-api/workqueue.rs
  X-POWERS AXP288 PMIC DRIVERS
  M:    Hans de Goede <hdegoede@redhat.com>
  S:    Maintained
 -N:    axp288
  F:    drivers/acpi/pmic/intel_pmic_xpower.c
 +N:    axp288
  
  X-POWERS MULTIFUNCTION PMIC DEVICE DRIVERS
  M:    Chen-Yu Tsai <wens@csie.org>
@@@ -18227,7 -18047,7 +18232,7 @@@ XDP (eXpress Data Path
  M:    Alexei Starovoitov <ast@kernel.org>
  M:    Daniel Borkmann <daniel@iogearbox.net>
  M:    David S. Miller <davem@davemloft.net>
 -M:    Jakub Kicinski <jakub.kicinski@netronome.com>
 +M:    Jakub Kicinski <kuba@kernel.org>
  M:    Jesper Dangaard Brouer <hawk@kernel.org>
  M:    John Fastabend <john.fastabend@gmail.com>
  L:    netdev@vger.kernel.org
index a6a2ac88f042b4f1232d137d6937ef3ae6c476fd,282c36c8fa3b55028b72eb8fc005d2ca2f129cb7..9f31064f2374e3110b2761ef58e49d8c414f81dd
                        reg = <0x0>;
                        next-level-cache = <&L2_0>;
                        enable-method = "psci";
-                       cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&apcs>;
                        operating-points-v2 = <&cpu_opp_table>;
                        #cooling-cells = <2>;
+                       power-domains = <&CPU_PD0>;
+                       power-domain-names = "psci";
                };
  
                CPU1: cpu@1 {
                        reg = <0x1>;
                        next-level-cache = <&L2_0>;
                        enable-method = "psci";
-                       cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&apcs>;
                        operating-points-v2 = <&cpu_opp_table>;
                        #cooling-cells = <2>;
+                       power-domains = <&CPU_PD1>;
+                       power-domain-names = "psci";
                };
  
                CPU2: cpu@2 {
                        reg = <0x2>;
                        next-level-cache = <&L2_0>;
                        enable-method = "psci";
-                       cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&apcs>;
                        operating-points-v2 = <&cpu_opp_table>;
                        #cooling-cells = <2>;
+                       power-domains = <&CPU_PD2>;
+                       power-domain-names = "psci";
                };
  
                CPU3: cpu@3 {
                        reg = <0x3>;
                        next-level-cache = <&L2_0>;
                        enable-method = "psci";
-                       cpu-idle-states = <&CPU_SLEEP_0>;
                        clocks = <&apcs>;
                        operating-points-v2 = <&cpu_opp_table>;
                        #cooling-cells = <2>;
+                       power-domains = <&CPU_PD3>;
+                       power-domain-names = "psci";
                };
  
                L2_0: l2-cache {
                                min-residency-us = <2000>;
                                local-timer-stop;
                        };
+                       CLUSTER_RET: cluster-retention {
+                               compatible = "domain-idle-state";
+                               arm,psci-suspend-param = <0x41000012>;
+                               entry-latency-us = <500>;
+                               exit-latency-us = <500>;
+                               min-residency-us = <2000>;
+                       };
+                       CLUSTER_PWRDN: cluster-gdhs {
+                               compatible = "domain-idle-state";
+                               arm,psci-suspend-param = <0x41000032>;
+                               entry-latency-us = <2000>;
+                               exit-latency-us = <2000>;
+                               min-residency-us = <6000>;
+                       };
                };
        };
  
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
+               CPU_PD0: cpu-pd0 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&CPU_SLEEP_0>;
+               };
+               CPU_PD1: cpu-pd1 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&CPU_SLEEP_0>;
+               };
+               CPU_PD2: cpu-pd2 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&CPU_SLEEP_0>;
+               };
+               CPU_PD3: cpu-pd3 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+                       domain-idle-states = <&CPU_SLEEP_0>;
+               };
+               CLUSTER_PD: cluster-pd {
+                       #power-domain-cells = <0>;
+                       domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
+               };
        };
  
        pmu {
                        compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
                        reg = <0xb011000 0x1000>;
                        #mbox-cells = <1>;
 -                      clocks = <&a53pll>;
 +                      clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
 +                      clock-names = "pll", "aux";
                        #clock-cells = <0>;
                };
  
                        nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
                        nvmem-cell-names = "calib", "calib_sel";
                        #qcom,sensors = <5>;
 +                      interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 +                      interrupt-names = "uplow";
                        #thermal-sensor-cells = <1>;
                };
  
index b0d5471f620d395dbd899747ebb360811b0bd001,3d89569e9e712c958d6db3211c9de2b8ab773d79..ada42f03915acca0dc55d5afcea0b901015c4552
@@@ -34,7 -34,6 +34,6 @@@
  #include <sysdev/fsl_soc.h>
  #include <sysdev/fsl_pci.h>
  #include <soc/fsl/qe/qe.h>
- #include <soc/fsl/qe/qe_ic.h>
  
  #include "mpc83xx.h"
  
@@@ -64,7 -63,7 +63,7 @@@ static void quirk_mpc8360e_qe_enet10(vo
                return;
        }
  
 -      base = ioremap(res.start, res.end - res.start + 1);
 +      base = ioremap(res.start, resource_size(&res));
  
        /*
         * set output delay adjustments to default values according
@@@ -178,7 -177,7 +177,7 @@@ define_machine(mpc83xx_km) 
        .name           = "mpc83xx-km-platform",
        .probe          = mpc83xx_km_probe,
        .setup_arch     = mpc83xx_km_setup_arch,
-       .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
+       .init_IRQ       = mpc83xx_ipic_init_IRQ,
        .get_irq        = ipic_get_irq,
        .restart        = mpc83xx_restart,
        .time_init      = mpc83xx_time_init,
index b301ef9d6ce756613a42c2518e3443231ce67a17,9abb1e9f73c40fa8235a36f0b6cb72c559aff470..eaec099b4077172940233fa0d1de4ae75e689bba
@@@ -19,7 -19,6 +19,6 @@@
  #include <asm/udbg.h>
  #include <asm/mpic.h>
  #include <soc/fsl/qe/qe.h>
- #include <soc/fsl/qe/qe_ic.h>
  
  #include <sysdev/fsl_soc.h>
  #include <sysdev/fsl_pci.h>
@@@ -31,26 -30,12 +30,12 @@@ static void __init twr_p1025_pic_init(v
  {
        struct mpic *mpic;
  
- #ifdef CONFIG_QUICC_ENGINE
-       struct device_node *np;
- #endif
        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
                        MPIC_SINGLE_DEST_CPU,
                        0, 256, " OpenPIC  ");
  
        BUG_ON(mpic == NULL);
        mpic_init(mpic);
- #ifdef CONFIG_QUICC_ENGINE
-       np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-       if (np) {
-               qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-                               qe_ic_cascade_high_mpic);
-               of_node_put(np);
-       } else
-               pr_err("Could not find qe-ic node\n");
- #endif
  }
  
  /* ************************************************************************
   */
  static void __init twr_p1025_setup_arch(void)
  {
 -#ifdef CONFIG_QUICC_ENGINE
 -      struct device_node *np;
 -#endif
 -
        if (ppc_md.progress)
                ppc_md.progress("twr_p1025_setup_arch()", 0);
  
@@@ -73,7 -62,6 +58,7 @@@
  #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
        if (machine_is(twr_p1025)) {
                struct ccsr_guts __iomem *guts;
 +              struct device_node *np;
  
                np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
                if (np) {
diff --combined drivers/bus/ti-sysc.c
index ccb44fe790a71ebbc5ccfa07216cbffaad29d6bd,c915ac30079531aba65cec5615db62b92def6866..f702c85c81b657ec5e0dfe0712ab32e309028fa0
@@@ -343,12 -343,6 +343,12 @@@ static int sysc_get_clocks(struct sysc 
                return -EINVAL;
        }
  
 +      /* Always add a slot for main clocks fck and ick even if unused */
 +      if (!nr_fck)
 +              ddata->nr_clocks++;
 +      if (!nr_ick)
 +              ddata->nr_clocks++;
 +
        ddata->clocks = devm_kcalloc(ddata->dev,
                                     ddata->nr_clocks, sizeof(*ddata->clocks),
                                     GFP_KERNEL);
@@@ -427,7 -421,7 +427,7 @@@ static int sysc_enable_opt_clocks(struc
        struct clk *clock;
        int i, error;
  
 -      if (!ddata->clocks)
 +      if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
                return 0;
  
        for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
@@@ -461,7 -455,7 +461,7 @@@ static void sysc_disable_opt_clocks(str
        struct clk *clock;
        int i;
  
 -      if (!ddata->clocks)
 +      if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
                return;
  
        for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
@@@ -479,7 -473,7 +479,7 @@@ static void sysc_clkdm_deny_idle(struc
  {
        struct ti_sysc_platform_data *pdata;
  
-       if (ddata->legacy_mode)
+       if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
                return;
  
        pdata = dev_get_platdata(ddata->dev);
@@@ -491,7 -485,7 +491,7 @@@ static void sysc_clkdm_allow_idle(struc
  {
        struct ti_sysc_platform_data *pdata;
  
-       if (ddata->legacy_mode)
+       if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
                return;
  
        pdata = dev_get_platdata(ddata->dev);
@@@ -509,10 -503,8 +509,8 @@@ static int sysc_init_resets(struct sys
  {
        ddata->rsts =
                devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
-       if (IS_ERR(ddata->rsts))
-               return PTR_ERR(ddata->rsts);
  
-       return 0;
+       return PTR_ERR_OR_ZERO(ddata->rsts);
  }
  
  /**
@@@ -1216,10 -1208,6 +1214,6 @@@ static const struct sysc_revision_quir
        /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
        SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
                   SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
-       SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
-                  SYSC_QUIRK_LEGACY_IDLE),
-       SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
-                  SYSC_QUIRK_LEGACY_IDLE),
        SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
                   SYSC_QUIRK_LEGACY_IDLE),
        SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
        /* Quirks that need to be set based on detected module */
        SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff,
                   SYSC_MODULE_QUIRK_AESS),
+       SYSC_QUIRK("dcan", 0x48480000, 0x20, -1, -1, 0xa3170504, 0xffffffff,
+                  SYSC_QUIRK_CLKDM_NOAUTO),
+       SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -1, 0x500a0200, 0xffffffff,
+                  SYSC_QUIRK_CLKDM_NOAUTO),
+       SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -1, 0x500a0200, 0xffffffff,
+                  SYSC_QUIRK_CLKDM_NOAUTO),
        SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
                   SYSC_MODULE_QUIRK_HDQ1W),
        SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
index 74d9f13d72c45f4c1c9052d044b70d0c341ba53a,0137bf328e54c5c8408cd02243701ca293e6b46e..ecc339d846deba4f802ee741ca7e729c4fb748f7
@@@ -26,6 -26,9 +26,9 @@@
  
  static const struct zynqmp_eemi_ops *eemi_ops_tbl;
  
+ static bool feature_check_enabled;
+ static u32 zynqmp_pm_features[PM_API_MAX];
  static const struct mfd_cell firmware_devs[] = {
        {
                .name = "zynqmp_power_controller",
@@@ -44,12 -47,12 +47,14 @@@ static int zynqmp_pm_ret_code(u32 ret_s
        case XST_PM_SUCCESS:
        case XST_PM_DOUBLE_REQ:
                return 0;
+       case XST_PM_NO_FEATURE:
+               return -ENOTSUPP;
        case XST_PM_NO_ACCESS:
                return -EACCES;
        case XST_PM_ABORT_SUSPEND:
                return -ECANCELED;
 +      case XST_PM_MULT_USER:
 +              return -EUSERS;
        case XST_PM_INTERNAL:
        case XST_PM_CONFLICT:
        case XST_PM_INVALID_NODE:
@@@ -128,6 -131,39 +133,39 @@@ static noinline int do_fw_call_hvc(u64 
        return zynqmp_pm_ret_code((enum pm_ret_status)res.a0);
  }
  
+ /**
+  * zynqmp_pm_feature() - Check weather given feature is supported or not
+  * @api_id:           API ID to check
+  *
+  * Return: Returns status, either success or error+reason
+  */
+ static int zynqmp_pm_feature(u32 api_id)
+ {
+       int ret;
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       u64 smc_arg[2];
+       if (!feature_check_enabled)
+               return 0;
+       /* Return value if feature is already checked */
+       if (zynqmp_pm_features[api_id] != PM_FEATURE_UNCHECKED)
+               return zynqmp_pm_features[api_id];
+       smc_arg[0] = PM_SIP_SVC | PM_FEATURE_CHECK;
+       smc_arg[1] = api_id;
+       ret = do_fw_call(smc_arg[0], smc_arg[1], 0, ret_payload);
+       if (ret) {
+               zynqmp_pm_features[api_id] = PM_FEATURE_INVALID;
+               return PM_FEATURE_INVALID;
+       }
+       zynqmp_pm_features[api_id] = ret_payload[1];
+       return zynqmp_pm_features[api_id];
+ }
  /**
   * zynqmp_pm_invoke_fn() - Invoke the system-level platform management layer
   *                       caller function depending on the configuration
@@@ -162,6 -198,9 +200,9 @@@ int zynqmp_pm_invoke_fn(u32 pm_api_id, 
         */
        u64 smc_arg[4];
  
+       if (zynqmp_pm_feature(pm_api_id) == PM_FEATURE_INVALID)
+               return -ENOTSUPP;
        smc_arg[0] = PM_SIP_SVC | pm_api_id;
        smc_arg[1] = ((u64)arg1 << 32) | arg0;
        smc_arg[2] = ((u64)arg3 << 32) | arg2;
@@@ -717,6 -756,8 +758,8 @@@ static int zynqmp_firmware_probe(struc
                np = of_find_compatible_node(NULL, NULL, "xlnx,versal");
                if (!np)
                        return 0;
+               feature_check_enabled = true;
        }
        of_node_put(np);
  
index 3998cac49d7f13986a539b6daaa30fa656f4420b,f029eaa7cfc0c01e861462bab190207973dce309..9edd94679283d4fe5267dcbb01a1ef80b1419710
@@@ -73,7 -73,7 +73,7 @@@ static struct ucc_tdm_info utdm_primary
        },
  };
  
 -static struct ucc_tdm_info utdm_info[MAX_HDLC_NUM];
 +static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
  
  static int uhdlc_init(struct ucc_hdlc_private *priv)
  {
@@@ -84,8 -84,8 +84,8 @@@
        int ret, i;
        void *bd_buffer;
        dma_addr_t bd_dma_addr;
-       u32 riptr;
-       u32 tiptr;
+       s32 riptr;
+       s32 tiptr;
        u32 gumr;
  
        ut_info = priv->ut_info;
        priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
                                ALIGNMENT_OF_UCC_HDLC_PRAM);
  
-       if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
+       if (priv->ucc_pram_offset < 0) {
                dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
                ret = -ENOMEM;
                goto free_tx_bd;
  
        /* Alloc riptr, tiptr */
        riptr = qe_muram_alloc(32, 32);
-       if (IS_ERR_VALUE(riptr)) {
+       if (riptr < 0) {
                dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
                ret = -ENOMEM;
                goto free_tx_skbuff;
        }
  
        tiptr = qe_muram_alloc(32, 32);
-       if (IS_ERR_VALUE(tiptr)) {
+       if (tiptr < 0) {
                dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
                ret = -ENOMEM;
                goto free_riptr;
        }
+       if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
+               dev_err(priv->dev, "MURAM allocation out of addressable range\n");
+               ret = -ENOMEM;
+               goto free_tiptr;
+       }
  
        /* Set RIPTR, TIPTR */
        iowrite16be(riptr, &priv->ucc_pram->riptr);
@@@ -623,8 -628,8 +628,8 @@@ static int ucc_hdlc_poll(struct napi_st
  
        if (howmany < budget) {
                napi_complete_done(napi, howmany);
-               qe_setbits32(priv->uccf->p_uccm,
-                            (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
+               qe_setbits_be32(priv->uccf->p_uccm,
+                               (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
        }
  
        return howmany;
@@@ -635,9 -640,11 +640,9 @@@ static irqreturn_t ucc_hdlc_irq_handler
        struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
        struct net_device *dev = priv->ndev;
        struct ucc_fast_private *uccf;
 -      struct ucc_tdm_info *ut_info;
        u32 ucce;
        u32 uccm;
  
 -      ut_info = priv->ut_info;
        uccf = priv->uccf;
  
        ucce = ioread32be(uccf->p_ucce);
@@@ -730,8 -737,8 +735,8 @@@ static int uhdlc_open(struct net_devic
  
  static void uhdlc_memclean(struct ucc_hdlc_private *priv)
  {
-       qe_muram_free(priv->ucc_pram->riptr);
-       qe_muram_free(priv->ucc_pram->tiptr);
+       qe_muram_free(ioread16be(&priv->ucc_pram->riptr));
+       qe_muram_free(ioread16be(&priv->ucc_pram->tiptr));
  
        if (priv->rx_bd_base) {
                dma_free_coherent(priv->dev,
@@@ -870,6 -877,7 +875,6 @@@ static void resume_clk_config(struct uc
  static int uhdlc_suspend(struct device *dev)
  {
        struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
 -      struct ucc_tdm_info *ut_info;
        struct ucc_fast __iomem *uf_regs;
  
        if (!priv)
        netif_device_detach(priv->ndev);
        napi_disable(&priv->napi);
  
 -      ut_info = priv->ut_info;
        uf_regs = priv->uf_regs;
  
        /* backup gumr guemr*/
@@@ -913,7 -922,7 +918,7 @@@ static int uhdlc_resume(struct device *
        struct ucc_fast __iomem *uf_regs;
        struct ucc_fast_private *uccf;
        struct ucc_fast_info *uf_info;
 -      int ret, i;
 +      int i;
        u32 cecr_subblock;
        u16 bd_status;
  
  
        /* Write to QE CECR, UCCx channel to Stop Transmission */
        cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 -      ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
 -                         (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 +      qe_issue_cmd(QE_STOP_TX, cecr_subblock,
 +                   (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
  
        /* Set UPSMR normal mode */
        iowrite32be(0, &uf_regs->upsmr);
  
        /* init parameter base */
        cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 -      ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
 -                         QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
 +      qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
 +                   QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
  
        priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
                                qe_muram_addr(priv->ucc_pram_offset);
@@@ -1035,7 -1044,7 +1040,7 @@@ static const struct dev_pm_ops uhdlc_pm
  #define HDLC_PM_OPS NULL
  
  #endif
 -static void uhdlc_tx_timeout(struct net_device *ndev)
 +static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue)
  {
        netdev_err(ndev, "%s\n", __func__);
  }
diff --combined drivers/of/base.c
index 8d173fb3552a11174c490522dfd53bbce8e04e58,614f0c674995566b839f0066bd32d6c4d76167ba..ae03b1218b06e5f5da9111fecf09cd30ca3d8691
@@@ -135,38 -135,115 +135,38 @@@ int __weak of_node_to_nid(struct device
  }
  #endif
  
 -/*
 - * Assumptions behind phandle_cache implementation:
 - *   - phandle property values are in a contiguous range of 1..n
 - *
 - * If the assumptions do not hold, then
 - *   - the phandle lookup overhead reduction provided by the cache
 - *     will likely be less
 - */
 +#define OF_PHANDLE_CACHE_BITS 7
 +#define OF_PHANDLE_CACHE_SZ   BIT(OF_PHANDLE_CACHE_BITS)
  
 -static struct device_node **phandle_cache;
 -static u32 phandle_cache_mask;
 +static struct device_node *phandle_cache[OF_PHANDLE_CACHE_SZ];
  
 -/*
 - * Caller must hold devtree_lock.
 - */
 -static void __of_free_phandle_cache(void)
 +static u32 of_phandle_cache_hash(phandle handle)
  {
 -      u32 cache_entries = phandle_cache_mask + 1;
 -      u32 k;
 -
 -      if (!phandle_cache)
 -              return;
 -
 -      for (k = 0; k < cache_entries; k++)
 -              of_node_put(phandle_cache[k]);
 -
 -      kfree(phandle_cache);
 -      phandle_cache = NULL;
 +      return hash_32(handle, OF_PHANDLE_CACHE_BITS);
  }
  
 -int of_free_phandle_cache(void)
 -{
 -      unsigned long flags;
 -
 -      raw_spin_lock_irqsave(&devtree_lock, flags);
 -
 -      __of_free_phandle_cache();
 -
 -      raw_spin_unlock_irqrestore(&devtree_lock, flags);
 -
 -      return 0;
 -}
 -#if !defined(CONFIG_MODULES)
 -late_initcall_sync(of_free_phandle_cache);
 -#endif
 -
  /*
   * Caller must hold devtree_lock.
   */
 -void __of_free_phandle_cache_entry(phandle handle)
 +void __of_phandle_cache_inv_entry(phandle handle)
  {
 -      phandle masked_handle;
 +      u32 handle_hash;
        struct device_node *np;
  
        if (!handle)
                return;
  
 -      masked_handle = handle & phandle_cache_mask;
 +      handle_hash = of_phandle_cache_hash(handle);
  
 -      if (phandle_cache) {
 -              np = phandle_cache[masked_handle];
 -              if (np && handle == np->phandle) {
 -                      of_node_put(np);
 -                      phandle_cache[masked_handle] = NULL;
 -              }
 -      }
 -}
 -
 -void of_populate_phandle_cache(void)
 -{
 -      unsigned long flags;
 -      u32 cache_entries;
 -      struct device_node *np;
 -      u32 phandles = 0;
 -
 -      raw_spin_lock_irqsave(&devtree_lock, flags);
 -
 -      __of_free_phandle_cache();
 -
 -      for_each_of_allnodes(np)
 -              if (np->phandle && np->phandle != OF_PHANDLE_ILLEGAL)
 -                      phandles++;
 -
 -      if (!phandles)
 -              goto out;
 -
 -      cache_entries = roundup_pow_of_two(phandles);
 -      phandle_cache_mask = cache_entries - 1;
 -
 -      phandle_cache = kcalloc(cache_entries, sizeof(*phandle_cache),
 -                              GFP_ATOMIC);
 -      if (!phandle_cache)
 -              goto out;
 -
 -      for_each_of_allnodes(np)
 -              if (np->phandle && np->phandle != OF_PHANDLE_ILLEGAL) {
 -                      of_node_get(np);
 -                      phandle_cache[np->phandle & phandle_cache_mask] = np;
 -              }
 -
 -out:
 -      raw_spin_unlock_irqrestore(&devtree_lock, flags);
 +      np = phandle_cache[handle_hash];
 +      if (np && handle == np->phandle)
 +              phandle_cache[handle_hash] = NULL;
  }
  
  void __init of_core_init(void)
  {
        struct device_node *np;
  
 -      of_populate_phandle_cache();
  
        /* Create the kset, and register existing nodes */
        mutex_lock(&of_mutex);
                pr_err("failed to register existing nodes\n");
                return;
        }
 -      for_each_of_allnodes(np)
 +      for_each_of_allnodes(np) {
                __of_attach_node_sysfs(np);
 +              if (np->phandle && !phandle_cache[of_phandle_cache_hash(np->phandle)])
 +                      phandle_cache[of_phandle_cache_hash(np->phandle)] = np;
 +      }
        mutex_unlock(&of_mutex);
  
        /* Symlink in /proc as required by userspace ABI */
@@@ -415,6 -489,42 +415,42 @@@ int of_cpu_node_to_id(struct device_nod
  }
  EXPORT_SYMBOL(of_cpu_node_to_id);
  
+ /**
+  * of_get_cpu_state_node - Get CPU's idle state node at the given index
+  *
+  * @cpu_node: The device node for the CPU
+  * @index: The index in the list of the idle states
+  *
+  * Two generic methods can be used to describe a CPU's idle states, either via
+  * a flattened description through the "cpu-idle-states" binding or via the
+  * hierarchical layout, using the "power-domains" and the "domain-idle-states"
+  * bindings. This function check for both and returns the idle state node for
+  * the requested index.
+  *
+  * In case an idle state node is found at @index, the refcount is incremented
+  * for it, so call of_node_put() on it when done. Returns NULL if not found.
+  */
+ struct device_node *of_get_cpu_state_node(struct device_node *cpu_node,
+                                         int index)
+ {
+       struct of_phandle_args args;
+       int err;
+       err = of_parse_phandle_with_args(cpu_node, "power-domains",
+                                       "#power-domain-cells", 0, &args);
+       if (!err) {
+               struct device_node *state_node =
+                       of_parse_phandle(args.np, "domain-idle-states", index);
+               of_node_put(args.np);
+               if (state_node)
+                       return state_node;
+       }
+       return of_parse_phandle(cpu_node, "cpu-idle-states", index);
+ }
+ EXPORT_SYMBOL(of_get_cpu_state_node);
  /**
   * __of_device_is_compatible() - Check if the node matches given constraints
   * @device: pointer to node
@@@ -1161,24 -1271,36 +1197,24 @@@ struct device_node *of_find_node_by_pha
  {
        struct device_node *np = NULL;
        unsigned long flags;
 -      phandle masked_handle;
 +      u32 handle_hash;
  
        if (!handle)
                return NULL;
  
 +      handle_hash = of_phandle_cache_hash(handle);
 +
        raw_spin_lock_irqsave(&devtree_lock, flags);
  
 -      masked_handle = handle & phandle_cache_mask;
 -
 -      if (phandle_cache) {
 -              if (phandle_cache[masked_handle] &&
 -                  handle == phandle_cache[masked_handle]->phandle)
 -                      np = phandle_cache[masked_handle];
 -              if (np && of_node_check_flag(np, OF_DETACHED)) {
 -                      WARN_ON(1); /* did not uncache np on node removal */
 -                      of_node_put(np);
 -                      phandle_cache[masked_handle] = NULL;
 -                      np = NULL;
 -              }
 -      }
 +      if (phandle_cache[handle_hash] &&
 +          handle == phandle_cache[handle_hash]->phandle)
 +              np = phandle_cache[handle_hash];
  
        if (!np) {
                for_each_of_allnodes(np)
                        if (np->phandle == handle &&
                            !of_node_check_flag(np, OF_DETACHED)) {
 -                              if (phandle_cache) {
 -                                      /* will put when removed from cache */
 -                                      of_node_get(np);
 -                                      phandle_cache[masked_handle] = np;
 -                              }
 +                              phandle_cache[handle_hash] = np;
                                break;
                        }
        }
index 606abbe55bbaf717e9f5db1a6339ba707bed8990,110cc00717bc0639ed9c15620935e430236c8f7a..802717b9f6a3b175e7618d715399582b12eb97e9
@@@ -49,6 -49,9 +49,9 @@@ static struct tegra_fuse *fuse = &(stru
  };
  
  static const struct of_device_id tegra_fuse_match[] = {
+ #ifdef CONFIG_ARCH_TEGRA_194_SOC
+       { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
+ #endif
  #ifdef CONFIG_ARCH_TEGRA_186_SOC
        { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
  #endif
@@@ -408,7 -411,7 +411,7 @@@ static int __init tegra_init_fuse(void
                }
        }
  
 -      fuse->base = ioremap_nocache(regs.start, resource_size(&regs));
 +      fuse->base = ioremap(regs.start, resource_size(&regs));
        if (!fuse->base) {
                pr_err("failed to map FUSE registers\n");
                return -ENXIO;
index a2fd6ccd48f92447d8eb27f27304365e79e500ae,4a737f15e4018405bf3f09d6b32a81fb82ffc37d..089d9340564bde665720442ed4008c19a341d3a2
  #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT       \
        (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
  
- static void __iomem *apbmisc_base;
- static void __iomem *strapping_base;
  static bool long_ram_code;
+ static u32 strapping;
+ static u32 chipid;
  
  u32 tegra_read_chipid(void)
  {
-       if (!apbmisc_base) {
-               WARN(1, "Tegra Chip ID not yet available\n");
-               return 0;
-       }
+       WARN(!chipid, "Tegra ABP MISC not yet available\n");
  
-       return readl_relaxed(apbmisc_base + 4);
+       return chipid;
  }
  
  u8 tegra_get_chip_id(void)
  
  u32 tegra_read_straps(void)
  {
-       if (strapping_base)
-               return readl_relaxed(strapping_base);
-       else
-               return 0;
+       WARN(!chipid, "Tegra ABP MISC not yet available\n");
+       return strapping;
  }
  
  u32 tegra_read_ram_code(void)
@@@ -63,6 -59,7 +59,7 @@@
  static const struct of_device_id apbmisc_match[] __initconst = {
        { .compatible = "nvidia,tegra20-apbmisc", },
        { .compatible = "nvidia,tegra186-misc", },
+       { .compatible = "nvidia,tegra194-misc", },
        {},
  };
  
@@@ -103,6 -100,7 +100,7 @@@ void __init tegra_init_revision(void
  
  void __init tegra_init_apbmisc(void)
  {
+       void __iomem *apbmisc_base, *strapping_base;
        struct resource apbmisc, straps;
        struct device_node *np;
  
                        apbmisc.flags = IORESOURCE_MEM;
  
                        /* strapping options */
-                       if (tegra_get_chip_id() == TEGRA124) {
+                       if (of_machine_is_compatible("nvidia,tegra124")) {
                                straps.start = 0x7000e864;
                                straps.end = 0x7000e867;
                        } else {
                }
        }
  
 -      apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
 +      apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc));
-       if (!apbmisc_base)
+       if (!apbmisc_base) {
                pr_err("failed to map APBMISC registers\n");
+       } else {
+               chipid = readl_relaxed(apbmisc_base + 4);
+               iounmap(apbmisc_base);
+       }
  
 -      strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
 +      strapping_base = ioremap(straps.start, resource_size(&straps));
-       if (!strapping_base)
+       if (!strapping_base) {
                pr_err("failed to map strapping options registers\n");
+       } else {
+               strapping = readl_relaxed(strapping_base);
+               iounmap(strapping_base);
+       }
  
        long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
  }
index 2e151a4c222b984ab72139a4538e11d3da65d825,afc2a5d69202c118799f4c607e90f1ae6e0b0832..3c8c662c69e2509a12f2f3bbb666522335d42807
  #include <soc/fsl/qe/ucc_slow.h>
  
  #include <linux/firmware.h>
- #include <asm/reg.h>
+ #include <soc/fsl/cpm.h>
+ #ifdef CONFIG_PPC32
+ #include <asm/reg.h> /* mfspr, SPRN_SVR */
+ #endif
  
  /*
   * The GUMR flag for Soft UART.  This would normally be defined in qe.h,
@@@ -257,11 -261,11 +261,11 @@@ static unsigned int qe_uart_tx_empty(st
        struct qe_bd *bdp = qe_port->tx_bd_base;
  
        while (1) {
-               if (in_be16(&bdp->status) & BD_SC_READY)
+               if (qe_ioread16be(&bdp->status) & BD_SC_READY)
                        /* This BD is not done, so return "not done" */
                        return 0;
  
-               if (in_be16(&bdp->status) & BD_SC_WRAP)
+               if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
                        /*
                         * This BD is done and it's the last one, so return
                         * "done"
@@@ -307,7 -311,7 +311,7 @@@ static void qe_uart_stop_tx(struct uart
        struct uart_qe_port *qe_port =
                container_of(port, struct uart_qe_port, port);
  
-       clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+       qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
  }
  
  /*
@@@ -332,18 -336,20 +336,18 @@@ static int qe_uart_tx_pump(struct uart_
        struct uart_port *port = &qe_port->port;
        struct circ_buf *xmit = &port->state->xmit;
  
 -      bdp = qe_port->rx_cur;
 -
        /* Handle xon/xoff */
        if (port->x_char) {
                /* Pick next descriptor and fill from buffer */
                bdp = qe_port->tx_cur;
  
-               p = qe2cpu_addr(bdp->buf, qe_port);
+               p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
  
                *p++ = port->x_char;
-               out_be16(&bdp->length, 1);
-               setbits16(&bdp->status, BD_SC_READY);
+               qe_iowrite16be(1, &bdp->length);
+               qe_setbits_be16(&bdp->status, BD_SC_READY);
                /* Get next BD. */
-               if (in_be16(&bdp->status) & BD_SC_WRAP)
+               if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
                        bdp = qe_port->tx_bd_base;
                else
                        bdp++;
        /* Pick next descriptor and fill from buffer */
        bdp = qe_port->tx_cur;
  
-       while (!(in_be16(&bdp->status) & BD_SC_READY) &&
+       while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
               (xmit->tail != xmit->head)) {
                count = 0;
-               p = qe2cpu_addr(bdp->buf, qe_port);
+               p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
                while (count < qe_port->tx_fifosize) {
                        *p++ = xmit->buf[xmit->tail];
                        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
                                break;
                }
  
-               out_be16(&bdp->length, count);
-               setbits16(&bdp->status, BD_SC_READY);
+               qe_iowrite16be(count, &bdp->length);
+               qe_setbits_be16(&bdp->status, BD_SC_READY);
  
                /* Get next BD. */
-               if (in_be16(&bdp->status) & BD_SC_WRAP)
+               if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
                        bdp = qe_port->tx_bd_base;
                else
                        bdp++;
@@@ -412,12 -418,12 +416,12 @@@ static void qe_uart_start_tx(struct uar
                container_of(port, struct uart_qe_port, port);
  
        /* If we currently are transmitting, then just return */
-       if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
+       if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
                return;
  
        /* Otherwise, pump the port and start transmission */
        if (qe_uart_tx_pump(qe_port))
-               setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+               qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
  }
  
  /*
@@@ -428,7 -434,7 +432,7 @@@ static void qe_uart_stop_rx(struct uart
        struct uart_qe_port *qe_port =
                container_of(port, struct uart_qe_port, port);
  
-       clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+       qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
  }
  
  /* Start or stop sending  break signal
@@@ -467,14 -473,14 +471,14 @@@ static void qe_uart_int_rx(struct uart_
         */
        bdp = qe_port->rx_cur;
        while (1) {
-               status = in_be16(&bdp->status);
+               status = qe_ioread16be(&bdp->status);
  
                /* If this one is empty, then we assume we've read them all */
                if (status & BD_SC_EMPTY)
                        break;
  
                /* get number of characters, and check space in RX buffer */
-               i = in_be16(&bdp->length);
+               i = qe_ioread16be(&bdp->length);
  
                /* If we don't have enough room in RX buffer for the entire BD,
                 * then we try later, which will be the next RX interrupt.
                }
  
                /* get pointer */
-               cp = qe2cpu_addr(bdp->buf, qe_port);
+               cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
  
                /* loop through the buffer */
                while (i-- > 0) {
@@@ -505,9 -511,10 +509,10 @@@ error_return
                }
  
                /* This BD is ready to be used again. Clear status. get next */
-               clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
-                       BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
-               if (in_be16(&bdp->status) & BD_SC_WRAP)
+               qe_clrsetbits_be16(&bdp->status,
+                                  BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
+                                  BD_SC_EMPTY);
+               if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
                        bdp = qe_port->rx_bd_base;
                else
                        bdp++;
@@@ -549,7 -556,9 +554,7 @@@ handle_error
        /* Overrun does not affect the current character ! */
        if (status & BD_SC_OV)
                tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 -#ifdef SUPPORT_SYSRQ
        port->sysrq = 0;
 -#endif
        goto error_return;
  }
  
@@@ -564,8 -573,8 +569,8 @@@ static irqreturn_t qe_uart_int(int irq
        u16 events;
  
        /* Clear the interrupts */
-       events = in_be16(&uccp->ucce);
-       out_be16(&uccp->ucce, events);
+       events = qe_ioread16be(&uccp->ucce);
+       qe_iowrite16be(events, &uccp->ucce);
  
        if (events & UCC_UART_UCCE_BRKE)
                uart_handle_break(&qe_port->port);
@@@ -596,17 -605,17 +601,17 @@@ static void qe_uart_initbd(struct uart_
        bdp = qe_port->rx_bd_base;
        qe_port->rx_cur = qe_port->rx_bd_base;
        for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
-               out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
-               out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
-               out_be16(&bdp->length, 0);
+               qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+               qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+               qe_iowrite16be(0, &bdp->length);
                bd_virt += qe_port->rx_fifosize;
                bdp++;
        }
  
        /* */
-       out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
-       out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
-       out_be16(&bdp->length, 0);
+       qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+       qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+       qe_iowrite16be(0, &bdp->length);
  
        /* Set the physical address of the host memory
         * buffers in the buffer descriptors, and the
        qe_port->tx_cur = qe_port->tx_bd_base;
        bdp = qe_port->tx_bd_base;
        for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
-               out_be16(&bdp->status, BD_SC_INTRPT);
-               out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
-               out_be16(&bdp->length, 0);
+               qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
+               qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+               qe_iowrite16be(0, &bdp->length);
                bd_virt += qe_port->tx_fifosize;
                bdp++;
        }
  
        /* Loopback requires the preamble bit to be set on the first TX BD */
  #ifdef LOOPBACK
-       setbits16(&qe_port->tx_cur->status, BD_SC_P);
+       qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
  #endif
  
-       out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
-       out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
-       out_be16(&bdp->length, 0);
+       qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
+       qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+       qe_iowrite16be(0, &bdp->length);
  }
  
  /*
@@@ -653,78 -662,74 +658,74 @@@ static void qe_uart_init_ucc(struct uar
        ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  
        /* Program the UCC UART parameter RAM */
-       out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
-       out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
-       out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
-       out_be16(&uccup->maxidl, 0x10);
-       out_be16(&uccup->brkcr, 1);
-       out_be16(&uccup->parec, 0);
-       out_be16(&uccup->frmec, 0);
-       out_be16(&uccup->nosec, 0);
-       out_be16(&uccup->brkec, 0);
-       out_be16(&uccup->uaddr[0], 0);
-       out_be16(&uccup->uaddr[1], 0);
-       out_be16(&uccup->toseq, 0);
+       qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
+       qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
+       qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
+       qe_iowrite16be(0x10, &uccup->maxidl);
+       qe_iowrite16be(1, &uccup->brkcr);
+       qe_iowrite16be(0, &uccup->parec);
+       qe_iowrite16be(0, &uccup->frmec);
+       qe_iowrite16be(0, &uccup->nosec);
+       qe_iowrite16be(0, &uccup->brkec);
+       qe_iowrite16be(0, &uccup->uaddr[0]);
+       qe_iowrite16be(0, &uccup->uaddr[1]);
+       qe_iowrite16be(0, &uccup->toseq);
        for (i = 0; i < 8; i++)
-               out_be16(&uccup->cchars[i], 0xC000);
-       out_be16(&uccup->rccm, 0xc0ff);
+               qe_iowrite16be(0xC000, &uccup->cchars[i]);
+       qe_iowrite16be(0xc0ff, &uccup->rccm);
  
        /* Configure the GUMR registers for UART */
        if (soft_uart) {
                /* Soft-UART requires a 1X multiplier for TX */
-               clrsetbits_be32(&uccp->gumr_l,
-                       UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
-                       UCC_SLOW_GUMR_L_RDCR_MASK,
-                       UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
-                       UCC_SLOW_GUMR_L_RDCR_16);
-               clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
-                       UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+               qe_clrsetbits_be32(&uccp->gumr_l,
+                                  UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+                                  UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
+               qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
+                                  UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
        } else {
-               clrsetbits_be32(&uccp->gumr_l,
-                       UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
-                       UCC_SLOW_GUMR_L_RDCR_MASK,
-                       UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
-                       UCC_SLOW_GUMR_L_RDCR_16);
-               clrsetbits_be32(&uccp->gumr_h,
-                       UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
-                       UCC_SLOW_GUMR_H_RFW);
+               qe_clrsetbits_be32(&uccp->gumr_l,
+                                  UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+                                  UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
+               qe_clrsetbits_be32(&uccp->gumr_h,
+                                  UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
+                                  UCC_SLOW_GUMR_H_RFW);
        }
  
  #ifdef LOOPBACK
-       clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
-               UCC_SLOW_GUMR_L_DIAG_LOOP);
-       clrsetbits_be32(&uccp->gumr_h,
-               UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
-               UCC_SLOW_GUMR_H_CDS);
+       qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+                          UCC_SLOW_GUMR_L_DIAG_LOOP);
+       qe_clrsetbits_be32(&uccp->gumr_h,
+                          UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
+                          UCC_SLOW_GUMR_H_CDS);
  #endif
  
        /* Disable rx interrupts  and clear all pending events.  */
-       out_be16(&uccp->uccm, 0);
-       out_be16(&uccp->ucce, 0xffff);
-       out_be16(&uccp->udsr, 0x7e7e);
+       qe_iowrite16be(0, &uccp->uccm);
+       qe_iowrite16be(0xffff, &uccp->ucce);
+       qe_iowrite16be(0x7e7e, &uccp->udsr);
  
        /* Initialize UPSMR */
-       out_be16(&uccp->upsmr, 0);
+       qe_iowrite16be(0, &uccp->upsmr);
  
        if (soft_uart) {
-               out_be16(&uccup->supsmr, 0x30);
-               out_be16(&uccup->res92, 0);
-               out_be32(&uccup->rx_state, 0);
-               out_be32(&uccup->rx_cnt, 0);
-               out_8(&uccup->rx_bitmark, 0);
-               out_8(&uccup->rx_length, 10);
-               out_be32(&uccup->dump_ptr, 0x4000);
-               out_8(&uccup->rx_temp_dlst_qe, 0);
-               out_be32(&uccup->rx_frame_rem, 0);
-               out_8(&uccup->rx_frame_rem_size, 0);
+               qe_iowrite16be(0x30, &uccup->supsmr);
+               qe_iowrite16be(0, &uccup->res92);
+               qe_iowrite32be(0, &uccup->rx_state);
+               qe_iowrite32be(0, &uccup->rx_cnt);
+               qe_iowrite8(0, &uccup->rx_bitmark);
+               qe_iowrite8(10, &uccup->rx_length);
+               qe_iowrite32be(0x4000, &uccup->dump_ptr);
+               qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
+               qe_iowrite32be(0, &uccup->rx_frame_rem);
+               qe_iowrite8(0, &uccup->rx_frame_rem_size);
                /* Soft-UART requires TX to be 1X */
-               out_8(&uccup->tx_mode,
-                       UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
-               out_be16(&uccup->tx_state, 0);
-               out_8(&uccup->resD4, 0);
-               out_be16(&uccup->resD5, 0);
+               qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
+                           &uccup->tx_mode);
+               qe_iowrite16be(0, &uccup->tx_state);
+               qe_iowrite8(0, &uccup->resD4);
+               qe_iowrite16be(0, &uccup->resD5);
  
                /* Set UART mode.
                 * Enable receive and transmit.
                 * ...
                 * 6.Receiver must use 16x over sampling
                 */
-               clrsetbits_be32(&uccp->gumr_l,
-                       UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
-                       UCC_SLOW_GUMR_L_RDCR_MASK,
-                       UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
-                       UCC_SLOW_GUMR_L_RDCR_16);
+               qe_clrsetbits_be32(&uccp->gumr_l,
+                                  UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+                                  UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
  
-               clrsetbits_be32(&uccp->gumr_h,
-                       UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
-                       UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
-                       UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
+               qe_clrsetbits_be32(&uccp->gumr_h,
+                                  UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
+                                  UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
  
  #ifdef LOOPBACK
-               clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
-                               UCC_SLOW_GUMR_L_DIAG_LOOP);
-               clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
-                         UCC_SLOW_GUMR_H_CDS);
+               qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+                                  UCC_SLOW_GUMR_L_DIAG_LOOP);
+               qe_clrbits_be32(&uccp->gumr_h,
+                               UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
  #endif
  
                cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
@@@ -796,7 -798,7 +794,7 @@@ static int qe_uart_startup(struct uart_
        }
  
        /* Startup rx-int */
-       setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+       qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
        ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  
        return 0;
@@@ -832,7 -834,7 +830,7 @@@ static void qe_uart_shutdown(struct uar
  
        /* Stop uarts */
        ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
-       clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
+       qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
  
        /* Shut them really down and reinit buffer descriptors */
        ucc_slow_graceful_stop_tx(qe_port->us_private);
@@@ -852,9 -854,9 +850,9 @@@ static void qe_uart_set_termios(struct 
        struct ucc_slow __iomem *uccp = qe_port->uccp;
        unsigned int baud;
        unsigned long flags;
-       u16 upsmr = in_be16(&uccp->upsmr);
+       u16 upsmr = qe_ioread16be(&uccp->upsmr);
        struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
-       u16 supsmr = in_be16(&uccup->supsmr);
+       u16 supsmr = qe_ioread16be(&uccup->supsmr);
        u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
  
        /* Character length programmed into the mode register is the
        /* Update the per-port timeout. */
        uart_update_timeout(port, termios->c_cflag, baud);
  
-       out_be16(&uccp->upsmr, upsmr);
+       qe_iowrite16be(upsmr, &uccp->upsmr);
        if (soft_uart) {
-               out_be16(&uccup->supsmr, supsmr);
-               out_8(&uccup->rx_length, char_length);
+               qe_iowrite16be(supsmr, &uccup->supsmr);
+               qe_iowrite8(char_length, &uccup->rx_length);
  
                /* Soft-UART requires a 1X multiplier for TX */
                qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
@@@ -1097,6 -1099,8 +1095,8 @@@ static const struct uart_ops qe_uart_po
        .verify_port    = qe_uart_verify_port,
  };
  
+ #ifdef CONFIG_PPC32
  /*
   * Obtain the SOC model number and revision level
   *
@@@ -1184,70 -1188,86 +1184,86 @@@ static void uart_firmware_cont(const st
        release_firmware(fw);
  }
  
- static int ucc_uart_probe(struct platform_device *ofdev)
+ static int soft_uart_init(struct platform_device *ofdev)
  {
        struct device_node *np = ofdev->dev.of_node;
-       const unsigned int *iprop;      /* Integer OF properties */
-       const char *sprop;      /* String OF properties */
-       struct uart_qe_port *qe_port = NULL;
-       struct resource res;
+       struct qe_firmware_info *qe_fw_info;
        int ret;
  
-       /*
-        * Determine if we need Soft-UART mode
-        */
        if (of_find_property(np, "soft-uart", NULL)) {
                dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
                soft_uart = 1;
+       } else {
+               return 0;
        }
  
-       /*
-        * If we are using Soft-UART, determine if we need to upload the
-        * firmware, too.
-        */
-       if (soft_uart) {
-               struct qe_firmware_info *qe_fw_info;
-               qe_fw_info = qe_get_firmware_info();
-               /* Check if the firmware has been uploaded. */
-               if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
-                       firmware_loaded = 1;
-               } else {
-                       char filename[32];
-                       unsigned int soc;
-                       unsigned int rev_h;
-                       unsigned int rev_l;
-                       soc = soc_info(&rev_h, &rev_l);
-                       if (!soc) {
-                               dev_err(&ofdev->dev, "unknown CPU model\n");
-                               return -ENXIO;
-                       }
-                       sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
-                               soc, rev_h, rev_l);
-                       dev_info(&ofdev->dev, "waiting for firmware %s\n",
-                               filename);
+       qe_fw_info = qe_get_firmware_info();
  
-                       /*
-                        * We call request_firmware_nowait instead of
-                        * request_firmware so that the driver can load and
-                        * initialize the ports without holding up the rest of
-                        * the kernel.  If hotplug support is enabled in the
-                        * kernel, then we use it.
-                        */
-                       ret = request_firmware_nowait(THIS_MODULE,
-                               FW_ACTION_HOTPLUG, filename, &ofdev->dev,
-                               GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
-                       if (ret) {
-                               dev_err(&ofdev->dev,
-                                       "could not load firmware %s\n",
-                                       filename);
-                               return ret;
-                       }
+       /* Check if the firmware has been uploaded. */
+       if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
+               firmware_loaded = 1;
+       } else {
+               char filename[32];
+               unsigned int soc;
+               unsigned int rev_h;
+               unsigned int rev_l;
+               soc = soc_info(&rev_h, &rev_l);
+               if (!soc) {
+                       dev_err(&ofdev->dev, "unknown CPU model\n");
+                       return -ENXIO;
+               }
+               sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
+                       soc, rev_h, rev_l);
+               dev_info(&ofdev->dev, "waiting for firmware %s\n",
+                        filename);
+               /*
+                * We call request_firmware_nowait instead of
+                * request_firmware so that the driver can load and
+                * initialize the ports without holding up the rest of
+                * the kernel.  If hotplug support is enabled in the
+                * kernel, then we use it.
+                */
+               ret = request_firmware_nowait(THIS_MODULE,
+                                             FW_ACTION_HOTPLUG, filename, &ofdev->dev,
+                                             GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
+               if (ret) {
+                       dev_err(&ofdev->dev,
+                               "could not load firmware %s\n",
+                               filename);
+                       return ret;
                }
        }
+       return 0;
+ }
+ #else /* !CONFIG_PPC32 */
+ static int soft_uart_init(struct platform_device *ofdev)
+ {
+       return 0;
+ }
+ #endif
+ static int ucc_uart_probe(struct platform_device *ofdev)
+ {
+       struct device_node *np = ofdev->dev.of_node;
+       const char *sprop;      /* String OF properties */
+       struct uart_qe_port *qe_port = NULL;
+       struct resource res;
+       u32 val;
+       int ret;
+       /*
+        * Determine if we need Soft-UART mode
+        */
+       ret = soft_uart_init(ofdev);
+       if (ret)
+               return ret;
  
        qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
        if (!qe_port) {
  
        /* Get the UCC number (device ID) */
        /* UCCs are numbered 1-7 */
-       iprop = of_get_property(np, "cell-index", NULL);
-       if (!iprop) {
-               iprop = of_get_property(np, "device-id", NULL);
-               if (!iprop) {
-                       dev_err(&ofdev->dev, "UCC is unspecified in "
-                               "device tree\n");
+       if (of_property_read_u32(np, "cell-index", &val)) {
+               if (of_property_read_u32(np, "device-id", &val)) {
+                       dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
                        ret = -EINVAL;
                        goto out_free;
                }
        }
  
-       if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
-               dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
+       if (val < 1 || val > UCC_MAX_NUM) {
+               dev_err(&ofdev->dev, "no support for UCC%u\n", val);
                ret = -ENODEV;
                goto out_free;
        }
-       qe_port->ucc_num = *iprop - 1;
+       qe_port->ucc_num = val - 1;
  
        /*
         * In the future, we should not require the BRG to be specified in the
        }
  
        /* Get the port number, numbered 0-3 */
-       iprop = of_get_property(np, "port-number", NULL);
-       if (!iprop) {
+       if (of_property_read_u32(np, "port-number", &val)) {
                dev_err(&ofdev->dev, "missing port-number in device tree\n");
                ret = -EINVAL;
                goto out_free;
        }
-       qe_port->port.line = *iprop;
+       qe_port->port.line = val;
        if (qe_port->port.line >= UCC_MAX_UART) {
                dev_err(&ofdev->dev, "port-number must be 0-%u\n",
                        UCC_MAX_UART - 1);
                }
        }
  
-       iprop = of_get_property(np, "brg-frequency", NULL);
-       if (!iprop) {
+       if (of_property_read_u32(np, "brg-frequency", &val)) {
                dev_err(&ofdev->dev,
                       "missing brg-frequency in device tree\n");
                ret = -EINVAL;
                goto out_np;
        }
  
-       if (*iprop)
-               qe_port->port.uartclk = *iprop;
+       if (val)
+               qe_port->port.uartclk = val;
        else {
+               if (!IS_ENABLED(CONFIG_PPC32)) {
+                       dev_err(&ofdev->dev,
+                               "invalid brg-frequency in device tree\n");
+                       ret = -EINVAL;
+                       goto out_np;
+               }
                /*
                 * Older versions of U-Boot do not initialize the brg-frequency
                 * property, so in this case we assume the BRG frequency is
                 * half the QE bus frequency.
                 */
-               iprop = of_get_property(np, "bus-frequency", NULL);
-               if (!iprop) {
+               if (of_property_read_u32(np, "bus-frequency", &val)) {
                        dev_err(&ofdev->dev,
                                "missing QE bus-frequency in device tree\n");
                        ret = -EINVAL;
                        goto out_np;
                }
-               if (*iprop)
-                       qe_port->port.uartclk = *iprop / 2;
+               if (val)
+                       qe_port->port.uartclk = val / 2;
                else {
                        dev_err(&ofdev->dev,
                                "invalid QE bus-frequency in device tree\n");
index def48a5836700cc4d02b5a78b960fc4ef6d02cc7,01f04ed6ad927425e9c26b20677254755d09f8f8..d37c17e68268c60e3a66df1c00ad36bc25ad0d9d
@@@ -59,7 -59,6 +59,7 @@@ enum cpuhp_state 
        CPUHP_IOMMU_INTEL_DEAD,
        CPUHP_LUSTRE_CFS_DEAD,
        CPUHP_AP_ARM_CACHE_B15_RAC_DEAD,
 +      CPUHP_PADATA_DEAD,
        CPUHP_WORKQUEUE_PREP,
        CPUHP_POWER_NUMA_PREPARE,
        CPUHP_HRTIMERS_PREPARE,
@@@ -96,6 -95,7 +96,7 @@@
        CPUHP_AP_OFFLINE,
        CPUHP_AP_SCHED_STARTING,
        CPUHP_AP_RCUTREE_DYING,
+       CPUHP_AP_CPU_PM_STARTING,
        CPUHP_AP_IRQ_GIC_STARTING,
        CPUHP_AP_IRQ_HIP04_STARTING,
        CPUHP_AP_IRQ_ARMADA_XP_STARTING,
index 1b9549d02544b073d66d4612a7107e7bd58274d7,e72eccf6972155f33cee0eb821af46bb8c42d9c8..2cd12ebd6826bb149d5ee9cc6b62c857843a59c5
  #define       ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  #define       ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  
+ /* Feature check status */
+ #define PM_FEATURE_INVALID            -1
+ #define PM_FEATURE_UNCHECKED          0
  /*
   * Firmware FPGA Manager flags
   * XILINX_ZYNQMP_PM_FPGA_FULL:        FPGA full reconfiguration
@@@ -78,18 -82,20 +82,21 @@@ enum pm_api_id 
        PM_CLOCK_GETRATE,
        PM_CLOCK_SETPARENT,
        PM_CLOCK_GETPARENT,
+       PM_FEATURE_CHECK = 63,
+       PM_API_MAX,
  };
  
  /* PMU-FW return status codes */
  enum pm_ret_status {
        XST_PM_SUCCESS = 0,
+       XST_PM_NO_FEATURE = 19,
        XST_PM_INTERNAL = 2000,
        XST_PM_CONFLICT,
        XST_PM_NO_ACCESS,
        XST_PM_INVALID_NODE,
        XST_PM_DOUBLE_REQ,
        XST_PM_ABORT_SUSPEND,
 +      XST_PM_MULT_USER = 2008,
  };
  
  enum pm_ioctl_id {
@@@ -108,7 -114,6 +115,7 @@@ enum pm_query_id 
        PM_QID_CLOCK_GET_PARENTS,
        PM_QID_CLOCK_GET_ATTRIBUTES,
        PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 +      PM_QID_CLOCK_GET_MAX_DIVISOR,
  };
  
  enum zynqmp_pm_reset_action {