Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed...

* clk-ingenic-fixes:
  :  - Ingenic i2s bit update and allow UDC clk to gate
  clk: ingenic: Add missing flag for UDC clock
  clk: ingenic: Fix incorrect data for the i2s clock

* clk-max9485:
  :  - Maxim 9485 Programmable Clock Generator
  clk: Add driver for MAX9485
  dts: clk: add devicetree bindings for MAX9485

* clk-pxa-32k-pll:
  :  - Expose 32 kHz PLL on PXA SoCs
  clk: pxa: export 32kHz PLL

* clk-aspeed:
  :  - Fix name of aspeed SDC clk define to have only one 'CLK'
  clk: aspeed: Fix SDCLK name

* clk-imx6sll-gpio:
  :  - imx6sll GPIO clk gate support
  clk: imx6sll: add GPIO LPCGs