clk: zynqmp: Add support for get max divider

To achieve best possible rate, maximum limit of divider is required
while computation. Get maximum supported divisor from firmware. To
maintain backward compatibility assign maximum possible value(0xFFFF)
if query for max divisor is not successful.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lkml.kernel.org/r/1575527759-26452-5-git-send-email-rajan.vaja@xilinx.com
Acked-by: Michal Simek <michal.simek@xilinx.com>
[sboyd@kernel.org: Remove else return and just return]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d27092cbe5816318d481fab783db062c2..da6903197fc767c1d998ee30b75186daa5dfe8a6 100644 (file)
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -41,6 +41,7 @@ struct zynqmp_clk_divider {
        bool is_frac;
        u32 clk_id;
        u32 div_type;
+       u16 max_div;
 };
 
 static inline int zynqmp_divider_get_val(unsigned long parent_rate,
@@ -175,6 +176,35 @@ static const struct clk_ops zynqmp_clk_divider_ops = {
        .set_rate = zynqmp_clk_divider_set_rate,
 };
 
+/**
+ * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
+ * @clk_id:            Id of clock
+ * @type:              Divider type
+ *
+ * Return: Maximum divisor of a clock if query data is successful
+ *        U16_MAX in case of query data is not success
+ */
+u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
+{
+       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+       struct zynqmp_pm_query_data qdata = {0};
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       int ret;
+
+       qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
+       qdata.arg1 = clk_id;
+       qdata.arg2 = type;
+       ret = eemi_ops->query_data(qdata, ret_payload);
+       /*
+        * To maintain backward compatibility return maximum possible value
+        * (0xFFFF) if query for max divisor is not successful.
+        */
+       if (ret)
+               return U16_MAX;
+
+       return ret_payload[1];
+}
+
 /**
  * zynqmp_clk_register_divider() - Register a divider clock
  * @name:              Name of this clock
@@ -215,6 +245,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
        div->clk_id = clk_id;
        div->div_type = nodes->type;
 
+       /*
+        * To achieve best possible rate, maximum limit of divider is required
+        * while computation.
+        */
+       div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);
+
        hw = &div->hw;
        ret = clk_hw_register(NULL, hw);
        if (ret) {

diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 1827d30e86f16447a85f4d06f67040609e4cc9c3..1b9549d02544b073d66d4612a7107e7bd58274d7 100644 (file)
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -108,6 +108,7 @@ enum pm_query_id {
        PM_QID_CLOCK_GET_PARENTS,
        PM_QID_CLOCK_GET_ATTRIBUTES,
        PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
+       PM_QID_CLOCK_GET_MAX_DIVISOR,
 };
 
 enum zynqmp_pm_reset_action {