ASoC: rt5645: add micbias power control select.
authorBard Liao <bardliao@realtek.com>
Wed, 3 Jan 2018 12:39:02 +0000 (13:39 +0100)
committerMark Brown <broonie@kernel.org>
Thu, 4 Jan 2018 12:09:12 +0000 (12:09 +0000)
We need to set a corresponding control bit before powering micbias up.

Signed-off-by: Bard Liao <bardliao@realtek.com>
[hdegoede@redhat.com: Remove 2 unused variable declarations]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/rt5645.c
sound/soc/codecs/rt5645.h

index 6f6da0abe220a2337b4b9738f352e37d9fa53b06..fbaf36aeb587f9bf1809a2135884bb4e7529ac33 100644 (file)
@@ -1943,6 +1943,56 @@ static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
        return 0;
 }
 
        return 0;
 }
 
+static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
+               struct snd_kcontrol *k, int  event)
+{
+       struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+       switch (event) {
+       case SND_SOC_DAPM_PRE_PMU:
+               snd_soc_update_bits(codec, RT5645_GEN_CTRL2,
+                       RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
+                       RT5645_MICBIAS1_POW_CTRL_SEL_M);
+               break;
+
+       case SND_SOC_DAPM_POST_PMD:
+               snd_soc_update_bits(codec, RT5645_GEN_CTRL2,
+                       RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
+                       RT5645_MICBIAS1_POW_CTRL_SEL_A);
+               break;
+
+       default:
+               return 0;
+       }
+
+       return 0;
+}
+
+static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
+               struct snd_kcontrol *k, int  event)
+{
+       struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+       switch (event) {
+       case SND_SOC_DAPM_PRE_PMU:
+               snd_soc_update_bits(codec, RT5645_GEN_CTRL2,
+                       RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
+                       RT5645_MICBIAS2_POW_CTRL_SEL_M);
+               break;
+
+       case SND_SOC_DAPM_POST_PMD:
+               snd_soc_update_bits(codec, RT5645_GEN_CTRL2,
+                       RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
+                       RT5645_MICBIAS2_POW_CTRL_SEL_A);
+               break;
+
+       default:
+               return 0;
+       }
+
+       return 0;
+}
+
 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
        SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
                RT5645_PWR_LDO2_BIT, 0, NULL, 0),
 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
        SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
                RT5645_PWR_LDO2_BIT, 0, NULL, 0),
@@ -1981,9 +2031,11 @@ static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
        /* Input Side */
        /* micbias */
        SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
        /* Input Side */
        /* micbias */
        SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
-                       RT5645_PWR_MB1_BIT, 0, NULL, 0),
+                       RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
+                       SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
        SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
        SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
-                       RT5645_PWR_MB2_BIT, 0, NULL, 0),
+                       RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
+                       SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
        /* Input Lines */
        SND_SOC_DAPM_INPUT("DMIC L1"),
        SND_SOC_DAPM_INPUT("DMIC R1"),
        /* Input Lines */
        SND_SOC_DAPM_INPUT("DMIC L1"),
        SND_SOC_DAPM_INPUT("DMIC R1"),
index cfc5f97549eb656b9b861a612e0d60b40c2e93be..940325b28c299daa7d3b2b4dafda5e059a85b679 100644 (file)
@@ -2117,6 +2117,12 @@ enum {
 #define RT5645_RXDC_SRC_STO                    (0x0 << 7)
 #define RT5645_RXDC_SRC_MONO                   (0x1 << 7)
 #define RT5645_RXDC_SRC_SFT                    (7)
 #define RT5645_RXDC_SRC_STO                    (0x0 << 7)
 #define RT5645_RXDC_SRC_MONO                   (0x1 << 7)
 #define RT5645_RXDC_SRC_SFT                    (7)
+#define RT5645_MICBIAS1_POW_CTRL_SEL_MASK      (0x1 << 5)
+#define RT5645_MICBIAS1_POW_CTRL_SEL_A         (0x0 << 5)
+#define RT5645_MICBIAS1_POW_CTRL_SEL_M         (0x1 << 5)
+#define RT5645_MICBIAS2_POW_CTRL_SEL_MASK      (0x1 << 4)
+#define RT5645_MICBIAS2_POW_CTRL_SEL_A         (0x0 << 4)
+#define RT5645_MICBIAS2_POW_CTRL_SEL_M         (0x1 << 4)
 #define RT5645_RXDP2_SEL_MASK                  (0x1 << 3)
 #define RT5645_RXDP2_SEL_IF2                   (0x0 << 3)
 #define RT5645_RXDP2_SEL_ADC                   (0x1 << 3)
 #define RT5645_RXDP2_SEL_MASK                  (0x1 << 3)
 #define RT5645_RXDP2_SEL_IF2                   (0x0 << 3)
 #define RT5645_RXDP2_SEL_ADC                   (0x1 << 3)