Merge tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linux

author Linus Torvalds <torvalds@linux-foundation.org>

Thu, 16 Nov 2017 04:42:10 +0000 (20:42 -0800)

committer Linus Torvalds <torvalds@linux-foundation.org>

Thu, 16 Nov 2017 04:42:10 +0000 (20:42 -0800)
author Linus Torvalds <torvalds@linux-foundation.org>
Thu, 16 Nov 2017 04:42:10 +0000 (20:42 -0800)
committer Linus Torvalds <torvalds@linux-foundation.org>
Thu, 16 Nov 2017 04:42:10 +0000 (20:42 -0800)
diff --combined Documentation/admin-guide/kernel-parameters.txt

index 00bb04972612c858c32299b8a379663c6946132a,b24108f2a438d83ca88622ff51fca2279c8d8639..5ab1089d1422b47dd36c68151f70fae081ab369b
--- 1/Documentation/admin-guide/kernel-parameters.txt
--- 2/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@@ -314,7 -314,7 +314,7 @@@
         amijoy.map=     [HW,JOY] Amiga joystick support
                         Map of devices attached to JOY0DAT and JOY1DAT
                         Format: <a>,<b>
- -                      See also Documentation/input/joystick.txt
+ +                      See also Documentation/input/joydev/joystick.rst
   
         analog.map=     [HW,JOY] Analog joystick and gamepad support
                         Specifies type or capabilities of an analog joystick
@@@ -439,7 -439,7 +439,7 @@@
         bttv.card=      [HW,V4L] bttv (bt848 + bt878 based grabber cards)
         bttv.radio=     Most important insmod options are available as
                         kernel args too.
- -      bttv.pll=       See Documentation/video4linux/bttv/Insmod-options
+ +      bttv.pll=       See Documentation/media/v4l-drivers/bttv.rst
         bttv.tuner=
   
         bulk_remove=off [PPC]  This parameter disables the use of the pSeries
@@@ -641,8 -641,8 +641,8 @@@
                 For now, only VisioBraille is supported.
   
         consoleblank=   [KNL] The console blank (screen saver) timeout in
- -                      seconds. Defaults to 10*60 = 10mins. A value of 0
- -                      disables the blank timer.
+ +                      seconds. A value of 0 disables the blank timer.
+ +                       Defaults to 0.
   
         coredump_filter=
                         [KNL] Change the default value for
@@@ -709,9 -709,6 +709,9 @@@
                         It will be ignored when crashkernel=X,high is not used
                         or memory reserved is below 4G.
   
+ +      crossrelease_fullstack
+ +                      [KNL] Allow to record full stack trace in cross-release
+ +
         cryptomgr.notests
                           [KNL] Disable crypto self-tests
   
@@@ -727,7 -724,7 +727,7 @@@
         db9.dev[2|3]=   [HW,JOY] Multisystem joystick support via parallel port
                         (one device per port)
                         Format: <port#>,<type>
- -                      See also Documentation/input/joystick-parport.txt
+ +                      See also Documentation/input/devices/joystick-parport.rst
   
         ddebug_query=   [KNL,DYNAMIC_DEBUG] Enable debug messages at early boot
                         time. See
@@@ -857,7 -854,7 +857,7 @@@
                         The filter can be disabled or changed to another
                         driver later using sysfs.
   
-       drm_kms_helper.edid_firmware=[<connector>:]<file>[,[<connector>:]<file>]
+       drm.edid_firmware=[<connector>:]<file>[,[<connector>:]<file>]
                         Broken monitors, graphic adapters, KVMs and EDIDless
                         panels may send no or incorrect EDID data sets.
                         This parameter allows to specify an EDID data sets
@@@ -1223,7 -1220,7 +1223,7 @@@
                         [HW,JOY] Multisystem joystick and NES/SNES/PSX pad
                         support via parallel port (up to 5 devices per port)
                         Format: <port#>,<pad1>,<pad2>,<pad3>,<pad4>,<pad5>
- -                      See also Documentation/input/joystick-parport.txt
+ +                      See also Documentation/input/devices/joystick-parport.rst
   
         gamma=          [HW,DRM]
   
@@@ -1716,13 -1713,6 +1716,13 @@@
         irqaffinity=    [SMP] Set the default irq affinity mask
                         The argument is a cpu list, as described above.
   
+ +      irqchip.gicv2_force_probe=
+ +                      [ARM, ARM64]
+ +                      Format: <bool>
+ +                      Force the kernel to look for the second 4kB page
+ +                      of a GICv2 controller even if the memory range
+ +                      exposed by the device tree is too small.
+ +
         irqfixup        [HW]
                         When an interrupt is not handled search all handlers
                         for it. Intended to get systems with badly broken
@@@ -1737,33 -1727,20 +1737,33 @@@
         isapnp=         [ISAPNP]
                         Format: <RDP>,<reset>,<pci_scan>,<verbosity>
   
- -      isolcpus=       [KNL,SMP] Isolate CPUs from the general scheduler.
- -                      The argument is a cpu list, as described above.
+ +      isolcpus=       [KNL,SMP] Isolate a given set of CPUs from disturbance.
+ +                      [Deprecated - use cpusets instead]
+ +                      Format: [flag-list,]<cpu-list>
+ +
+ +                      Specify one or more CPUs to isolate from disturbances
+ +                      specified in the flag list (default: domain):
+ +
+ +                      nohz
+ +                        Disable the tick when a single task runs.
+ +                      domain
+ +                        Isolate from the general SMP balancing and scheduling
+ +                        algorithms. Note that performing domain isolation this way
+ +                        is irreversible: it's not possible to bring back a CPU to
+ +                        the domains once isolated through isolcpus. It's strongly
+ +                        advised to use cpusets instead to disable scheduler load
+ +                        balancing through the "cpuset.sched_load_balance" file.
+ +                        It offers a much more flexible interface where CPUs can
+ +                        move in and out of an isolated set anytime.
+ +
+ +                        You can move a process onto or off an "isolated" CPU via
+ +                        the CPU affinity syscalls or cpuset.
+ +                        <cpu number> begins at 0 and the maximum value is
+ +                        "number of CPUs in system - 1".
+ +
+ +                      The format of <cpu-list> is described above.
   
- -                      This option can be used to specify one or more CPUs
- -                      to isolate from the general SMP balancing and scheduling
- -                      algorithms. You can move a process onto or off an
- -                      "isolated" CPU via the CPU affinity syscalls or cpuset.
- -                      <cpu number> begins at 0 and the maximum value is
- -                      "number of CPUs in system - 1".
   
- -                      This option is the preferred way to isolate CPUs. The
- -                      alternative -- manually setting the CPU mask of all
- -                      tasks in the system -- can cause problems and
- -                      suboptimal load balancer performance.
   
         iucv=           [HW,NET]
   
@@@ -1789,7 -1766,7 +1789,7 @@@
                                 ivrs_acpihid[00:14.5]=AMD0020:0
   
         js=             [HW,JOY] Analog joystick
- -                      See Documentation/input/joystick.txt.
+ +                      See Documentation/input/joydev/joystick.rst.
   
         nokaslr         [KNL]
                         When CONFIG_RANDOMIZE_BASE is set, this disables
@@@ -1864,6 -1841,13 +1864,6 @@@
                         Built with CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y,
                         the default is off.
   
- -      kmemcheck=      [X86] Boot-time kmemcheck enable/disable/one-shot mode
- -                      Valid arguments: 0, 1, 2
- -                      kmemcheck=0 (disabled)
- -                      kmemcheck=1 (enabled)
- -                      kmemcheck=2 (one-shot mode)
- -                      Default: 2 (one-shot mode)
- -
         kvm.ignore_msrs=[KVM] Ignore guest accesses to unhandled MSRs.
                         Default is 0 (don't ignore, but inject #GP)
   
@@@ -2264,10 -2248,10 +2264,10 @@@
                         s2idle  - Suspend-To-Idle
                         shallow - Power-On Suspend or equivalent (if supported)
                         deep    - Suspend-To-RAM or equivalent (if supported)
- -                      See Documentation/power/states.txt.
+ +                      See Documentation/admin-guide/pm/sleep-states.rst.
   
         meye.*=         [HW] Set MotionEye Camera parameters
- -                      See Documentation/video4linux/meye.txt.
+ +                      See Documentation/media/v4l-drivers/meye.rst.
   
         mfgpt_irq=      [IA-32] Specify the IRQ to use for the
                         Multi-Function General Purpose Timers on AMD Geode
@@@ -2564,9 -2548,6 +2564,9 @@@
   
         noalign         [KNL,ARM]
   
+ +      noaltinstr      [S390] Disables alternative instructions patching
+ +                      (CPU alternatives feature).
+ +
         noapic          [SMP,APIC] Tells the kernel to not make use of any
                         IOAPICs that may be present in the system.
   
@@@ -3153,7 -3134,7 +3153,7 @@@
   
         plip=           [PPT,NET] Parallel port network link
                         Format: { parport<nr> | timid | 0 }
- -                      See also Documentation/parport.txt.
+ +                      See also Documentation/admin-guide/parport.rst.
   
         pmtmr=          [X86] Manual setup of pmtmr I/O Port.
                         Override pmtimer IOPort with a hex value.
@@@ -3558,9 -3539,6 +3558,9 @@@
         rcutorture.stall_cpu_holdoff= [KNL]
                         Time to wait (s) after boot before inducing stall.
   
+ +      rcutorture.stall_cpu_irqsoff= [KNL]
+ +                      Disable interrupts while stalling if set.
+ +
         rcutorture.stat_interval= [KNL]
                         Time (s) between statistics printk()s.
   
@@@ -3907,12 -3885,6 +3907,12 @@@
                         [KNL] Should the soft-lockup detector generate panics.
                         Format: <integer>
   
+ +                      A nonzero value instructs the soft-lockup detector
+ +                      to panic the machine when a soft-lockup occurs. This
+ +                      is also controlled by CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC
+ +                      which is the respective build-time switch to that
+ +                      functionality.
+ +
         softlockup_all_cpu_backtrace=
                         [KNL] Should the soft-lockup detector generate
                         backtraces on all cpus.
@@@ -4222,15 -4194,12 +4222,15 @@@
                         Used to run time disable IRQ_TIME_ACCOUNTING on any
                         platforms where RDTSC is slow and this accounting
                         can add overhead.
+ +                      [x86] unstable: mark the TSC clocksource as unstable, this
+ +                      marks the TSC unconditionally unstable at bootup and
+ +                      avoids any further wobbles once the TSC watchdog notices.
   
         turbografx.map[2|3]=    [HW,JOY]
                         TurboGraFX parallel port interface
                         Format:
                         <port#>,<js1>,<js2>,<js3>,<js4>,<js5>,<js6>,<js7>
- -                      See also Documentation/input/joystick-parport.txt
+ +                      See also Documentation/input/devices/joystick-parport.rst
   
         udbg-immortal   [PPC] When debugging early kernel crashes that
                         happen after console_init() and before a proper
diff --combined Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

index b7faa6f6a326070423cc68019657a479197dbade,013e76b348ba68a595fdd36ad8efdf3aa6ffc5b1..50cc72ee11689ccc99f54252b0c1a442362b9569
--- 1/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
--- 2/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@@ -40,15 -40,19 +40,19 @@@ CEC. It is one end of the pipeline
   
   Required properties:
     - compatible: value must be one of:
+     * allwinner,sun4i-a10-hdmi
       * allwinner,sun5i-a10s-hdmi
+     * allwinner,sun6i-a31-hdmi
     - reg: base address and size of memory-mapped region
     - interrupts: interrupt associated to this IP
     - clocks: phandles to the clocks feeding the HDMI encoder
       * ahb: the HDMI interface clock
       * mod: the HDMI module clock
+     * ddc: the HDMI ddc clock (A31 only)
       * pll-0: the first video PLL
       * pll-1: the second video PLL
     - clock-names: the clock names mentioned above
+   - resets: phandle to the reset control for the HDMI encoder (A31 only)
     - dmas: phandles to the DMA channels used by the HDMI encoder
       * ddc-tx: The channel for DDC transmission
       * ddc-rx: The channel for DDC reception
@@@ -83,9 -87,11 +87,11 @@@ The TCON acts as a timing controller fo
   
   Required properties:
    - compatible: value must be either:
+    * allwinner,sun4i-a10-tcon
      * allwinner,sun5i-a13-tcon
      * allwinner,sun6i-a31-tcon
      * allwinner,sun6i-a31s-tcon
+    * allwinner,sun7i-a20-tcon
      * allwinner,sun8i-a33-tcon
      * allwinner,sun8i-v3s-tcon
    - reg: base address and size of memory-mapped region
@@@ -150,8 -156,10 +156,10 @@@ system
   
   Required properties:
     - compatible: value must be one of:
+     * allwinner,sun4i-a10-display-backend
       * allwinner,sun5i-a13-display-backend
       * allwinner,sun6i-a31-display-backend
+     * allwinner,sun7i-a20-display-backend
       * allwinner,sun8i-a33-display-backend
     - reg: base address and size of the memory-mapped region.
     - interrupts: interrupt associated to this IP
@@@ -182,8 -190,10 +190,10 @@@ deinterlacing and color space conversio
   
   Required properties:
     - compatible: value must be one of:
+     * allwinner,sun4i-a10-display-frontend
       * allwinner,sun5i-a13-display-frontend
       * allwinner,sun6i-a31-display-frontend
+     * allwinner,sun7i-a20-display-frontend
       * allwinner,sun8i-a33-display-frontend
     - reg: base address and size of the memory-mapped region.
     - interrupts: interrupt associated to this IP
@@@ -228,10 -238,12 +238,12 @@@ extra node
   
   Required properties:
     - compatible: value must be one of:
+     * allwinner,sun4i-a10-display-engine
       * allwinner,sun5i-a10s-display-engine
       * allwinner,sun5i-a13-display-engine
       * allwinner,sun6i-a31-display-engine
       * allwinner,sun6i-a31s-display-engine
+     * allwinner,sun7i-a20-display-engine
       * allwinner,sun8i-a33-display-engine
       * allwinner,sun8i-v3s-display-engine
   
@@@ -266,7 -278,7 +278,7 @@@ connector 
         };
   };
   
- -hdmi: hdmi@01c16000 {
+ +hdmi: hdmi@1c16000 {
         compatible = "allwinner,sun5i-a10s-hdmi";
         reg = <0x01c16000 0x1000>;
         interrupts = <58>;
@@@ -305,7 -317,7 +317,7 @@@
         };
   };
   
- -tve0: tv-encoder@01c0a000 {
+ +tve0: tv-encoder@1c0a000 {
         compatible = "allwinner,sun4i-a10-tv-encoder";
         reg = <0x01c0a000 0x1000>;
         clocks = <&ahb_gates 34>;
diff --combined Documentation/devicetree/bindings/vendor-prefixes.txt

index 0f295a4798ad3de79de775573fb7cd5770de1e2e,6cf1dc5bc77ed4a38a19385dcbeac5541b21c3a0..1db9dbef3e5618cf037f9235c2e2b06fac27570b
--- 1/Documentation/devicetree/bindings/vendor-prefixes.txt
--- 2/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@@ -83,7 -83,6 +83,7 @@@ davicom       DAVICOM Semiconductor, Inc
   delta Delta Electronics, Inc.
   denx  Denx Software Engineering
   devantech     Devantech, Ltd.
+ +dh    DH electronics GmbH
   digi  Digi International Inc.
   digilent      Diglent, Inc.
   dioo  Dioo Microcircuit Co., Ltd
@@@ -138,7 -137,6 +138,7 @@@ gw Gateworks Corporatio
   hannstar      HannStar Display Corporation
   haoyu Haoyu Microelectronic Co. Ltd.
   hardkernel    Hardkernel Co., Ltd
+ +hideep        HiDeep Inc.
   himax Himax Technologies, Inc.
   hisilicon     Hisilicon Limited.
   hit   Hitachi Ltd.
@@@ -231,14 -229,12 +231,14 @@@ netlogic        Broadcom Corporation (formerl
   netron-dy     Netron DY
   netxeon               Shenzhen Netxeon Technology CO., LTD
   nexbox        Nexbox
+ +nextthing     Next Thing Co.
   newhaven      Newhaven Display International
   ni    National Instruments
   nintendo      Nintendo
   nlt   NLT Technologies, Ltd.
   nokia Nokia
   nordic        Nordic Semiconductor
+ +nutsboard     NutsBoard
   nuvoton       Nuvoton Technology Corporation
   nvd   New Vision Display
   nvidia        NVIDIA
@@@ -249,11 -245,10 +249,12 @@@ olimex  OLIMEX Ltd
   onion Onion Corporation
   onnn  ON Semiconductor Corp.
   ontat On Tat Industrial Company
+ +opalkelly     Opal Kelly Incorporated
   opencores     OpenCores.org
+ +openrisc      OpenRISC.io
   option        Option NV
   ORCL  Oracle Corporation
+ orisetech     Orise Technology
   ortustech     Ortus Technology Co., Ltd.
   ovti  OmniVision Technologies
   oxsemi        Oxford Semiconductor, Ltd.
@@@ -302,7 -297,6 +303,7 @@@ sensirion  Sensirion A
   sff   Small Form Factor Committee
   sgx   SGX Sensortech
   sharp Sharp Corporation
+ +shimafuji     Shimafuji Electric, Inc.
   si-en Si-En Technology Ltd.
   sigma Sigma Designs, Inc.
   sii   Seiko Instruments, Inc.
@@@ -324,7 -318,6 +325,7 @@@ solomon        Solomon Systech Limite
   sony  Sony Corporation
   spansion      Spansion Inc.
   sprd  Spreadtrum Communications Inc.
+ +sst   Silicon Storage Technology, Inc.
   st    STMicroelectronics
   starry        Starry Electronic Technology (ShenZhen) Co., LTD
   startek       Startek
@@@ -346,7 -339,6 +347,7 @@@ thine      THine Electronics, Inc
   ti    Texas Instruments
   tianma        Tianma Micro-electronics Co., Ltd.
   tlm   Trusted Logic Mobility
+ +tmt   Tecon Microprocessor Technologies, LLC.
   topeet  Topeet
   toradex       Toradex AG
   toshiba       Toshiba Corporation
diff --combined MAINTAINERS

index 1c453f9cce817651706f5582661afa8d1b618be3,6e1f94b4ed26352b14b0a561b13424d92755336a..d32726746a8830c805f1a2e0a6c2270cd2038a7b
--- 1/MAINTAINERS
--- 2/MAINTAINERS
+++ b/MAINTAINERS
@@@ -527,6 -527,11 +527,6 @@@ W:        http://ez.analog.com/community/linux
   S:    Supported
   F:    drivers/input/misc/adxl34x.c
   
- -AEDSP16 DRIVER
- -M:    Riccardo Facchetti <fizban@tin.it>
- -S:    Maintained
- -F:    sound/oss/aedsp16.c
- -
   AF9013 MEDIA DRIVER
   M:    Antti Palosaari <crope@iki.fi>
   L:    linux-media@vger.kernel.org
@@@ -695,9 -700,9 +695,9 @@@ F: include/linux/altera_uart.
   F:    include/linux/altera_jtaguart.h
   
   AMAZON ETHERNET DRIVERS
- -M:    Netanel Belgazal <netanel@annapurnalabs.com>
- -R:    Saeed Bishara <saeed@annapurnalabs.com>
- -R:    Zorik Machulsky <zorik@annapurnalabs.com>
+ +M:    Netanel Belgazal <netanel@amazon.com>
+ +R:    Saeed Bishara <saeedb@amazon.com>
+ +R:    Zorik Machulsky <zorik@amazon.com>
   L:    netdev@vger.kernel.org
   S:    Supported
   F:    Documentation/networking/ena.txt
@@@ -754,8 -759,6 +754,6 @@@ F: drivers/gpu/drm/amd/amdkfd
   F:    drivers/gpu/drm/amd/include/cik_structs.h
   F:    drivers/gpu/drm/amd/include/kgd_kfd_interface.h
   F:    drivers/gpu/drm/amd/include/vi_structs.h
- F:    drivers/gpu/drm/radeon/radeon_kfd.c
- F:    drivers/gpu/drm/radeon/radeon_kfd.h
   F:    include/uapi/linux/kfd_ioctl.h
   
   AMD SEATTLE DEVICE TREE SUPPORT
@@@ -868,7 -871,7 +866,7 @@@ F: drivers/android
   F:    drivers/staging/android/
   
   ANDROID GOLDFISH RTC DRIVER
- -M:    Miodrag Dinic <miodrag.dinic@imgtec.com>
+ +M:    Miodrag Dinic <miodrag.dinic@mips.com>
   S:    Supported
   F:    Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
   F:    drivers/rtc/rtc-goldfish.c
@@@ -1956,14 -1959,6 +1954,14 @@@ M:    Lennert Buytenhek <kernel@wantstofly
   L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
   S:    Maintained
   
+ +ARM/TEGRA HDMI CEC SUBSYSTEM SUPPORT
+ +M:    Hans Verkuil <hans.verkuil@cisco.com>
+ +L:    linux-tegra@vger.kernel.org
+ +L:    linux-media@vger.kernel.org
+ +S:    Maintained
+ +F:    drivers/media/platform/tegra-cec/
+ +F:    Documentation/devicetree/bindings/media/tegra-cec.txt
+ +
   ARM/TETON BGA MACHINE SUPPORT
   M:    "Mark F. Brown" <mark.brown314@gmail.com>
   L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -2032,7 -2027,6 +2030,7 @@@ M:      Masahiro Yamada <yamada.masahiro@soc
   L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
   S:    Maintained
+ +F:    Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
   F:    arch/arm/boot/dts/uniphier*
   F:    arch/arm/include/asm/hardware/cache-uniphier.h
   F:    arch/arm/mach-uniphier/
@@@ -2040,7 -2034,6 +2038,7 @@@ F:      arch/arm/mm/cache-uniphier.
   F:    arch/arm64/boot/dts/socionext/
   F:    drivers/bus/uniphier-system-bus.c
   F:    drivers/clk/uniphier/
+ +F:    drivers/gpio/gpio-uniphier.c
   F:    drivers/i2c/busses/i2c-uniphier*
   F:    drivers/irqchip/irq-uniphier-aidet.c
   F:    drivers/pinctrl/uniphier/
@@@ -2252,7 -2245,7 +2250,7 @@@ F:      include/linux/dmaengine.
   F:    include/linux/async_tx.h
   
   AT24 EEPROM DRIVER
- -M:    Wolfram Sang <wsa@the-dreams.de>
+ +M:    Bartosz Golaszewski <brgl@bgdev.pl>
   L:    linux-i2c@vger.kernel.org
   S:    Maintained
   F:    drivers/misc/eeprom/at24.c
@@@ -2567,12 -2560,10 +2565,12 @@@ S:   Maintaine
   F:    drivers/net/hamradio/baycom*
   
   BCACHE (BLOCK LAYER CACHE)
+ +M:    Michael Lyle <mlyle@lyle.org>
   M:    Kent Overstreet <kent.overstreet@gmail.com>
   L:    linux-bcache@vger.kernel.org
   W:    http://bcache.evilpiepirate.org
- -S:    Orphan
+ +C:    irc://irc.oftc.net/bcache
+ +S:    Maintained
   F:    drivers/md/bcache/
   
   BDISP ST MEDIA DRIVER
@@@ -2720,7 -2711,6 +2718,7 @@@ L:      linux-kernel@vger.kernel.or
   S:    Supported
   F:    arch/x86/net/bpf_jit*
   F:    Documentation/networking/filter.txt
+ +F:    Documentation/bpf/
   F:    include/linux/bpf*
   F:    include/linux/filter.h
   F:    include/uapi/linux/bpf*
@@@ -2733,7 -2723,7 +2731,7 @@@ F:      net/core/filter.
   F:    net/sched/act_bpf.c
   F:    net/sched/cls_bpf.c
   F:    samples/bpf/
- -F:    tools/net/bpf*
+ +F:    tools/bpf/
   F:    tools/testing/selftests/bpf/
   
   BROADCOM B44 10/100 ETHERNET DRIVER
@@@ -2904,15 -2894,7 +2902,15 @@@ S:    Supporte
   F:    drivers/gpio/gpio-brcmstb.c
   F:    Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
   
+ +BROADCOM BRCMSTB USB2 and USB3 PHY DRIVER
+ +M:    Al Cooper <alcooperx@gmail.com>
+ +L:    linux-kernel@vger.kernel.org
+ +L:    bcm-kernel-feedback-list@broadcom.com
+ +S:    Maintained
+ +F:    drivers/phy/broadcom/phy-brcm-usb*
+ +
   BROADCOM GENET ETHERNET DRIVER
+ +M:    Doug Berger <opendmb@gmail.com>
   M:    Florian Fainelli <f.fainelli@gmail.com>
   L:    netdev@vger.kernel.org
   S:    Supported
@@@ -3098,6 -3080,7 +3096,6 @@@ F:      arch/c6x
   
   CA8210 IEEE-802.15.4 RADIO DRIVER
   M:    Harry Morris <h.morris@cascoda.com>
- -M:    linuxdev@cascoda.com
   L:    linux-wpan@vger.kernel.org
   W:    https://github.com/Cascoda/ca8210-linux.git
   S:    Maintained
@@@ -3272,15 -3255,6 +3270,15 @@@ F:    include/uapi/linux/cec.
   F:    include/uapi/linux/cec-funcs.h
   F:    Documentation/devicetree/bindings/media/cec.txt
   
+ +CEC GPIO DRIVER
+ +M:    Hans Verkuil <hans.verkuil@cisco.com>
+ +L:    linux-media@vger.kernel.org
+ +T:    git git://linuxtv.org/media_tree.git
+ +W:    http://linuxtv.org
+ +S:    Supported
+ +F:    drivers/media/platform/cec-gpio/
+ +F:    Documentation/devicetree/bindings/media/cec-gpio.txt
+ +
   CELL BROADBAND ENGINE ARCHITECTURE
   M:    Arnd Bergmann <arnd@arndb.de>
   L:    linuxppc-dev@lists.ozlabs.org
@@@ -3353,22 -3327,17 +3351,22 @@@ S:   Maintaine
   F:    drivers/auxdisplay/cfag12864bfb.c
   F:    include/linux/cfag12864b.h
   
- -CFG80211 and NL80211
+ +802.11 (including CFG80211/NL80211)
   M:    Johannes Berg <johannes@sipsolutions.net>
   L:    linux-wireless@vger.kernel.org
   W:    http://wireless.kernel.org/
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
   S:    Maintained
+ +F:    net/wireless/
   F:    include/uapi/linux/nl80211.h
+ +F:    include/linux/ieee80211.h
+ +F:    include/net/wext.h
   F:    include/net/cfg80211.h
- -F:    net/wireless/*
- -X:    net/wireless/wext*
+ +F:    include/net/iw_handler.h
+ +F:    include/net/ieee80211_radiotap.h
+ +F:    Documentation/driver-api/80211/cfg80211.rst
+ +F:    Documentation/networking/regulatory.txt
   
   CHAR and MISC DRIVERS
   M:    Arnd Bergmann <arnd@arndb.de>
@@@ -3444,7 -3413,7 +3442,7 @@@ F:      drivers/scsi/snic
   CISCO VIC ETHERNET NIC DRIVER
   M:    Christian Benvenuti <benve@cisco.com>
   M:    Govindarajulu Varadarajan <_govind@gmx.com>
- -M:    Neel Patel <neepatel@cisco.com>
+ +M:    Parvi Kaustubhi <pkaustub@cisco.com>
   S:    Supported
   F:    drivers/net/ethernet/cisco/enic/
   
@@@ -3473,8 -3442,7 +3471,8 @@@ M:      Thomas Gleixner <tglx@linutronix.de
   L:    linux-kernel@vger.kernel.org
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
   S:    Supported
- -F:    drivers/clocksource
+ +F:    drivers/clocksource/
+ +F:    Documentation/devicetree/bindings/timer/
   
   CMPC ACPI DRIVER
   M:    Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
@@@ -3495,7 -3463,7 +3493,7 @@@ COCCINELLE/Semantic Patches (SmPL
   M:    Julia Lawall <Julia.Lawall@lip6.fr>
   M:    Gilles Muller <Gilles.Muller@lip6.fr>
   M:    Nicolas Palix <nicolas.palix@imag.fr>
- -M:    Michal Marek <mmarek@suse.com>
+ +M:    Michal Marek <michal.lkml@markovi.net>
   L:    cocci@systeme.lip6.fr (moderated for non-subscribers)
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild.git misc
   W:    http://coccinelle.lip6.fr/
@@@ -3609,7 -3577,7 +3607,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
   S:    Maintained
   F:    Documentation/cgroup-v1/cpusets.txt
   F:    include/linux/cpuset.h
- -F:    kernel/cpuset.c
+ +F:    kernel/cgroup/cpuset.c
   
   CONTROL GROUP - MEMORY RESOURCE CONTROLLER (MEMCG)
   M:    Johannes Weiner <hannes@cmpxchg.org>
@@@ -3666,8 -3634,6 +3664,8 @@@ F:      drivers/cpufreq/arm_big_little_dt.
   
   CPU POWER MONITORING SUBSYSTEM
   M:    Thomas Renninger <trenn@suse.com>
+ +M:    Shuah Khan <shuahkh@osg.samsung.com>
+ +M:    Shuah Khan <shuah@kernel.org>
   L:    linux-pm@vger.kernel.org
   S:    Maintained
   F:    tools/power/cpupower/
@@@ -4123,8 -4089,6 +4121,8 @@@ T:      git git://git.kernel.org/pub/scm/lin
   T:    quilt http://people.redhat.com/agk/patches/linux/editing/
   S:    Maintained
   F:    Documentation/device-mapper/
+ +F:    drivers/md/Makefile
+ +F:    drivers/md/Kconfig
   F:    drivers/md/dm*
   F:    drivers/md/persistent-data/
   F:    include/linux/device-mapper.h
@@@ -4268,7 -4232,7 +4266,7 @@@ S:      Maintaine
   F:    drivers/dma/
   F:    include/linux/dmaengine.h
   F:    Documentation/devicetree/bindings/dma/
- -F:    Documentation/dmaengine/
+ +F:    Documentation/driver-api/dmaengine/
   T:    git git://git.infradead.org/users/vkoul/slave-dma.git
   
   DMA MAPPING HELPERS
@@@ -4400,6 -4364,12 +4398,12 @@@ T:    git git://anongit.freedesktop.org/dr
   S:    Maintained
   F:    drivers/gpu/drm/bochs/
   
+ DRM DRIVER FOR FARADAY TVE200 TV ENCODER
+ M:    Linus Walleij <linus.walleij@linaro.org>
+ T:    git git://anongit.freedesktop.org/drm/drm-misc
+ S:    Maintained
+ F:    drivers/gpu/drm/tve200/
+ 
   DRM DRIVER FOR INTEL I810 VIDEO CARDS
   S:    Orphan / Obsolete
   F:    drivers/gpu/drm/i810/
@@@ -4543,7 -4513,7 +4547,7 @@@ L:      dri-devel@lists.freedesktop.or
   S:    Supported
   F:    drivers/gpu/drm/sun4i/
   F:    Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
- T:    git git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git
+ T:    git git://anongit.freedesktop.org/drm/drm-misc
   
   DRM DRIVERS FOR AMLOGIC SOCS
   M:    Neil Armstrong <narmstrong@baylibre.com>
@@@ -4727,7 -4697,7 +4731,7 @@@ T:      git git://anongit.freedesktop.org/dr
   DRM PANEL DRIVERS
   M:    Thierry Reding <thierry.reding@gmail.com>
   L:    dri-devel@lists.freedesktop.org
- T:    git git://anongit.freedesktop.org/tegra/linux.git
+ T:    git git://anongit.freedesktop.org/drm/drm-misc
   S:    Maintained
   F:    drivers/gpu/drm/drm_panel.c
   F:    drivers/gpu/drm/panel/
@@@ -4940,19 -4910,13 +4944,19 @@@ L:   linux-edac@vger.kernel.or
   S:    Maintained
   F:    drivers/edac/highbank*
   
- -EDAC-CAVIUM
+ +EDAC-CAVIUM OCTEON
   M:    Ralf Baechle <ralf@linux-mips.org>
   M:    David Daney <david.daney@cavium.com>
   L:    linux-edac@vger.kernel.org
   L:    linux-mips@linux-mips.org
   S:    Supported
   F:    drivers/edac/octeon_edac*
+ +
+ +EDAC-CAVIUM THUNDERX
+ +M:    David Daney <david.daney@cavium.com>
+ +M:    Jan Glauber <jglauber@cavium.com>
+ +L:    linux-edac@vger.kernel.org
+ +S:    Supported
   F:    drivers/edac/thunderx_edac*
   
   EDAC-CORE
@@@ -5253,7 -5217,8 +5257,7 @@@ F:      fs/ext4
   
   Extended Verification Module (EVM)
   M:    Mimi Zohar <zohar@linux.vnet.ibm.com>
- -L:    linux-ima-devel@lists.sourceforge.net
- -L:    linux-security-module@vger.kernel.org
+ +L:    linux-integrity@vger.kernel.org
   S:    Supported
   F:    security/integrity/evm/
   
@@@ -5495,6 -5460,7 +5499,7 @@@ F:      drivers/net/wan/sdla.
   
   FRAMEBUFFER LAYER
   M:    Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+ L:    dri-devel@lists.freedesktop.org
   L:    linux-fbdev@vger.kernel.org
   T:    git git://github.com/bzolnier/linux.git
   Q:    http://patchwork.kernel.org/project/linux-fbdev/list/
@@@ -5508,7 -5474,7 +5513,7 @@@ F:      include/uapi/linux/fb.
   
   FREESCALE CAAM (Cryptographic Acceleration and Assurance Module) DRIVER
   M:    Horia Geantă <horia.geanta@nxp.com>
- -M:    Dan Douglass <dan.douglass@nxp.com>
+ +M:    Aymen Sghaier <aymen.sghaier@nxp.com>
   L:    linux-crypto@vger.kernel.org
   S:    Maintained
   F:    drivers/crypto/caam/
@@@ -5688,7 -5654,6 +5693,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
   S:    Supported
   F:    fs/crypto/
   F:    include/linux/fscrypt*.h
+ +F:    Documentation/filesystems/fscrypt.rst
   
   FUJITSU FR-V (FRV) PORT
   S:    Orphan
@@@ -6282,13 -6247,6 +6287,13 @@@ S:    Maintaine
   F:    drivers/net/ethernet/hisilicon/
   F:    Documentation/devicetree/bindings/net/hisilicon*.txt
   
+ +HISILICON PMU DRIVER
+ +M:    Shaokun Zhang <zhangshaokun@hisilicon.com>
+ +W:    http://www.hisilicon.com
+ +S:    Supported
+ +F:    drivers/perf/hisilicon
+ +F:    Documentation/perf/hisi-pmu.txt
+ +
   HISILICON ROCE DRIVER
   M:    Lijun Ou <oulijun@huawei.com>
   M:    Wei Hu(Xavier) <xavier.huwei@huawei.com>
@@@ -6718,7 -6676,7 +6723,7 @@@ F:      include/net/ieee802154_netdev.
   F:    Documentation/networking/ieee802154.txt
   
   IFE PROTOCOL
- -M:    Yotam Gigi <yotamg@mellanox.com>
+ +M:    Yotam Gigi <yotam.gi@gmail.com>
   M:    Jamal Hadi Salim <jhs@mojatatu.com>
   F:    net/ife
   F:    include/net/ife.h
@@@ -6780,7 -6738,7 +6785,7 @@@ S:      Maintaine
   F:    drivers/usb/atm/ueagle-atm.c
   
   IMGTEC ASCII LCD DRIVER
- -M:    Paul Burton <paul.burton@imgtec.com>
+ +M:    Paul Burton <paul.burton@mips.com>
   S:    Maintained
   F:    Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
   F:    drivers/auxdisplay/img-ascii-lcd.c
@@@ -6822,6 -6780,8 +6827,6 @@@ F:      drivers/ipack
   
   INFINIBAND SUBSYSTEM
   M:    Doug Ledford <dledford@redhat.com>
- -M:    Sean Hefty <sean.hefty@intel.com>
- -M:    Hal Rosenstock <hal.rosenstock@gmail.com>
   L:    linux-rdma@vger.kernel.org
   W:    http://www.openfabrics.org/
   Q:    http://patchwork.kernel.org/project/linux-rdma/list/
@@@ -6886,7 -6846,9 +6891,7 @@@ L:      linux-crypto@vger.kernel.or
   INTEGRITY MEASUREMENT ARCHITECTURE (IMA)
   M:    Mimi Zohar <zohar@linux.vnet.ibm.com>
   M:    Dmitry Kasatkin <dmitry.kasatkin@gmail.com>
- -L:    linux-ima-devel@lists.sourceforge.net
- -L:    linux-ima-user@lists.sourceforge.net
- -L:    linux-security-module@vger.kernel.org
+ +L:    linux-integrity@vger.kernel.org
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
   S:    Supported
   F:    security/integrity/ima/
@@@ -7476,8 -7438,10 +7481,8 @@@ F:     mm/kasan
   F:    scripts/Makefile.kasan
   
   KCONFIG
- -M:    "Yann E. MORIN" <yann.morin.1998@free.fr>
   L:    linux-kbuild@vger.kernel.org
- -T:    git git://gitorious.org/linux-kconfig/linux-kconfig
- -S:    Maintained
+ +S:    Orphan
   F:    Documentation/kbuild/kconfig-language.txt
   F:    scripts/kconfig/
   
@@@ -7506,7 -7470,7 +7511,7 @@@ F:      fs/autofs4
   
   KERNEL BUILD + files below scripts/ (unless maintained elsewhere)
   M:    Masahiro Yamada <yamada.masahiro@socionext.com>
- -M:    Michal Marek <mmarek@suse.com>
+ +M:    Michal Marek <michal.lkml@markovi.net>
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
   L:    linux-kbuild@vger.kernel.org
   S:    Maintained
@@@ -7667,7 -7631,8 +7672,7 @@@ F:      kernel/kexec
   
   KEYS-ENCRYPTED
   M:    Mimi Zohar <zohar@linux.vnet.ibm.com>
- -M:    David Safford <safford@us.ibm.com>
- -L:    linux-security-module@vger.kernel.org
+ +L:    linux-integrity@vger.kernel.org
   L:    keyrings@vger.kernel.org
   S:    Supported
   F:    Documentation/security/keys/trusted-encrypted.rst
@@@ -7675,8 -7640,9 +7680,8 @@@ F:      include/keys/encrypted-type.
   F:    security/keys/encrypted-keys/
   
   KEYS-TRUSTED
- -M:    David Safford <safford@us.ibm.com>
   M:    Mimi Zohar <zohar@linux.vnet.ibm.com>
- -L:    linux-security-module@vger.kernel.org
+ +L:    linux-integrity@vger.kernel.org
   L:    keyrings@vger.kernel.org
   S:    Supported
   F:    Documentation/security/keys/trusted-encrypted.rst
@@@ -7709,6 -7675,16 +7714,6 @@@ F:     include/linux/kdb.
   F:    include/linux/kgdb.h
   F:    kernel/debug/
   
- -KMEMCHECK
- -M:    Vegard Nossum <vegardno@ifi.uio.no>
- -M:    Pekka Enberg <penberg@kernel.org>
- -S:    Maintained
- -F:    Documentation/dev-tools/kmemcheck.rst
- -F:    arch/x86/include/asm/kmemcheck.h
- -F:    arch/x86/mm/kmemcheck/
- -F:    include/linux/kmemcheck.h
- -F:    mm/kmemcheck.c
- -
   KMEMLEAK
   M:    Catalin Marinas <catalin.marinas@arm.com>
   S:    Maintained
@@@ -7774,11 -7750,6 +7779,11 @@@ S:    Maintaine
   F:    Documentation/scsi/53c700.txt
   F:    drivers/scsi/53c700*
   
+ +LEAKING_ADDRESSES
+ +M:    Tobin C. Harding <me@tobin.cc>
+ +S:    Maintained
+ +F:    scripts/leaking_addresses.pl
+ +
   LED SUBSYSTEM
   M:    Richard Purdie <rpurdie@rpsys.net>
   M:    Jacek Anaszewski <jacek.anaszewski@gmail.com>
@@@ -8242,7 -8213,6 +8247,7 @@@ F:      Documentation/networking/mac80211-in
   F:    include/net/mac80211.h
   F:    net/mac80211/
   F:    drivers/net/wireless/mac80211_hwsim.[ch]
+ +F:    Documentation/networking/mac80211_hwsim/README
   
   MAILBOX API
   M:    Jassi Brar <jassisinghbrar@gmail.com>
@@@ -8778,7 -8748,7 +8783,7 @@@ Q:      http://patchwork.ozlabs.org/project/
   F:    drivers/net/ethernet/mellanox/mlxsw/
   
   MELLANOX FIRMWARE FLASH LIBRARY (mlxfw)
- -M:    Yotam Gigi <yotamg@mellanox.com>
+ +M:    mlxsw@mellanox.com
   L:    netdev@vger.kernel.org
   S:    Supported
   W:    http://www.mellanox.com
@@@ -9028,7 -8998,7 +9033,7 @@@ F:      Documentation/mips
   F:    arch/mips/
   
   MIPS BOSTON DEVELOPMENT BOARD
- -M:    Paul Burton <paul.burton@imgtec.com>
+ +M:    Paul Burton <paul.burton@mips.com>
   L:    linux-mips@linux-mips.org
   S:    Maintained
   F:    Documentation/devicetree/bindings/clock/img,boston-clock.txt
@@@ -9038,7 -9008,7 +9043,7 @@@ F:      drivers/clk/imgtec/clk-boston.
   F:    include/dt-bindings/clock/boston-clock.h
   
   MIPS GENERIC PLATFORM
- -M:    Paul Burton <paul.burton@imgtec.com>
+ +M:    Paul Burton <paul.burton@mips.com>
   L:    linux-mips@linux-mips.org
   S:    Supported
   F:    arch/mips/generic/
@@@ -9054,7 -9024,7 +9059,7 @@@ F:      drivers/*/*loongson1
   F:    drivers/*/*/*loongson1*
   
   MIPS RINT INSTRUCTION EMULATION
- -M:    Aleksandar Markovic <aleksandar.markovic@imgtec.com>
+ +M:    Aleksandar Markovic <aleksandar.markovic@mips.com>
   L:    linux-mips@linux-mips.org
   S:    Supported
   F:    arch/mips/math-emu/sp_rint.c
@@@ -9234,6 -9204,12 +9239,6 @@@ F:     include/linux/dt-bindings/mux
   F:    include/linux/mux/
   F:    drivers/mux/
   
- -MULTISOUND SOUND DRIVER
- -M:    Andrew Veliath <andrewtv@usa.net>
- -S:    Maintained
- -F:    Documentation/sound/oss/MultiSound
- -F:    sound/oss/msnd*
- -
   MULTITECH MULTIPORT CARD (ISICOM)
   S:    Orphan
   F:    drivers/tty/isicom.c
@@@ -9437,7 -9413,6 +9442,7 @@@ M:      Florian Fainelli <f.fainelli@gmail.c
   S:    Maintained
   F:    net/dsa/
   F:    include/net/dsa.h
+ +F:    include/linux/dsa/
   F:    drivers/net/dsa/
   
   NETWORKING [GENERAL]
@@@ -9458,8 -9433,8 +9463,8 @@@ F:      include/uapi/linux/in.
   F:    include/uapi/linux/net.h
   F:    include/uapi/linux/netdevice.h
   F:    include/uapi/linux/net_namespace.h
- -F:    tools/net/
   F:    tools/testing/selftests/net/
+ +F:    lib/net_utils.c
   F:    lib/random32.c
   
   NETWORKING [IPSEC]
@@@ -10061,11 -10036,7 +10066,11 @@@ T: git git://github.com/openrisc/linux.
   L:    openrisc@lists.librecores.org
   W:    http://openrisc.io
   S:    Maintained
+ +F:    Documentation/devicetree/bindings/openrisc/
+ +F:    Documentation/openrisc/
   F:    arch/openrisc/
+ +F:    drivers/irqchip/irq-ompic.c
+ +F:    drivers/irqchip/irq-or1k-*
   
   OPENVSWITCH
   M:    Pravin Shelar <pshelar@nicira.com>
@@@ -10083,7 -10054,7 +10088,7 @@@ M:   Stephen Boyd <sboyd@codeaurora.org
   L:    linux-pm@vger.kernel.org
   S:    Maintained
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git
- -F:    drivers/base/power/opp/
+ +F:    drivers/opp/
   F:    include/linux/pm_opp.h
   F:    Documentation/power/opp.txt
   F:    Documentation/devicetree/bindings/opp/
@@@ -10370,6 -10341,7 +10375,6 @@@ F:   drivers/pci/host/vmd.
   
   PCI DRIVER FOR MICROSEMI SWITCHTEC
   M:    Kurt Schwemmer <kurt.schwemmer@microsemi.com>
- -M:    Stephen Bates <stephen.bates@microsemi.com>
   M:    Logan Gunthorpe <logang@deltatee.com>
   L:    linux-pci@vger.kernel.org
   S:    Maintained
@@@ -10434,7 -10406,6 +10439,7 @@@ F:   drivers/pci/dwc/*keystone
   
   PCI ENDPOINT SUBSYSTEM
   M:    Kishon Vijay Abraham I <kishon@ti.com>
+ +M:    Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
   L:    linux-pci@vger.kernel.org
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git
   S:    Supported
@@@ -10486,15 -10457,6 +10491,15 @@@ F: include/linux/pci
   F:    arch/x86/pci/
   F:    arch/x86/kernel/quirks.c
   
+ +PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
+ +M:    Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ +L:    linux-pci@vger.kernel.org
+ +Q:    http://patchwork.ozlabs.org/project/linux-pci/list/
+ +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
+ +S:    Supported
+ +F:    drivers/pci/host/
+ +F:    drivers/pci/dwc/
+ +
   PCIE DRIVER FOR AXIS ARTPEC
   M:    Niklas Cassel <niklas.cassel@axis.com>
   M:    Jesper Nilsson <jesper.nilsson@axis.com>
@@@ -10514,6 -10476,7 +10519,6 @@@ F:   drivers/pci/host/pci-thunder-
   
   PCIE DRIVER FOR HISILICON
   M:    Zhou Wang <wangzhou1@hisilicon.com>
- -M:    Gabriele Paoloni <gabriele.paoloni@huawei.com>
   L:    linux-pci@vger.kernel.org
   S:    Maintained
   F:    Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@@ -10527,14 -10490,6 +10532,14 @@@ S: Maintaine
   F:    Documentation/devicetree/bindings/pci/pcie-kirin.txt
   F:    drivers/pci/dwc/pcie-kirin.c
   
+ +PCIE DRIVER FOR HISILICON STB
+ +M:    Jianguo Sun <sunjianguo1@huawei.com>
+ +M:    Shawn Guo <shawn.guo@linaro.org>
+ +L:    linux-pci@vger.kernel.org
+ +S:    Maintained
+ +F:    Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
+ +F:    drivers/pci/dwc/pcie-histb.c
+ +
   PCIE DRIVER FOR MEDIATEK
   M:    Ryder Lee <ryder.lee@mediatek.com>
   L:    linux-pci@vger.kernel.org
@@@ -10558,13 -10513,6 +10563,13 @@@ S: Maintaine
   F:    Documentation/devicetree/bindings/pci/rockchip-pcie.txt
   F:    drivers/pci/host/pcie-rockchip.c
   
+ +PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
+ +M:    Linus Walleij <linus.walleij@linaro.org>
+ +L:    linux-pci@vger.kernel.org
+ +S:    Maintained
+ +F:    Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
+ +F:    drivers/pci/host/pci-v3-semi.c
+ +
   PCIE DRIVER FOR ST SPEAR13XX
   M:    Pratyush Anand <pratyush.anand@gmail.com>
   L:    linux-pci@vger.kernel.org
@@@ -10740,9 -10688,10 +10745,9 @@@ S:  Maintaine
   F:    drivers/pinctrl/spear/
   
   PISTACHIO SOC SUPPORT
- -M:    James Hartley <james.hartley@imgtec.com>
- -M:    Ionela Voinescu <ionela.voinescu@imgtec.com>
+ +M:    James Hartley <james.hartley@sondrel.com>
   L:    linux-mips@linux-mips.org
- -S:    Maintained
+ +S:    Odd Fixes
   F:    arch/mips/pistachio/
   F:    arch/mips/include/asm/mach-pistachio/
   F:    arch/mips/boot/dts/img/pistachio*
@@@ -10946,7 -10895,7 +10951,7 @@@ S:   Maintaine
   F:    drivers/block/ps3vram.c
   
   PSAMPLE PACKET SAMPLING SUPPORT:
- -M:    Yotam Gigi <yotamg@mellanox.com>
+ +M:    Yotam Gigi <yotam.gi@gmail.com>
   S:    Maintained
   F:    net/psample
   F:    include/net/psample.h
@@@ -11089,6 -11038,7 +11094,6 @@@ F:   drivers/mtd/nand/pxa3xx_nand.
   
   QAT DRIVER
   M:    Giovanni Cabiddu <giovanni.cabiddu@intel.com>
- -M:    Salvatore Benedetto <salvatore.benedetto@intel.com>
   L:    qat-linux@intel.com
   S:    Supported
   F:    drivers/crypto/qat/
@@@ -11136,7 -11086,6 +11141,7 @@@ F:   drivers/net/ethernet/qlogic/qede
   
   QLOGIC QL4xxx RDMA DRIVER
   M:    Ram Amrani <Ram.Amrani@cavium.com>
+ +M:    Michal Kalderon <Michal.Kalderon@cavium.com>
   M:    Ariel Elior <Ariel.Elior@cavium.com>
   L:    linux-rdma@vger.kernel.org
   S:    Supported
@@@ -11549,7 -11498,6 +11554,7 @@@ T:   git git://git.kernel.org/pub/scm/lin
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
   S:    Maintained
   F:    Documentation/rfkill.txt
+ +F:    Documentation/ABI/stable/sysfs-class-rfkill
   F:    net/rfkill/
   
   RHASHTABLE
@@@ -11571,16 -11519,6 +11576,16 @@@ S: Maintaine
   F:    drivers/mtd/nand/r852.c
   F:    drivers/mtd/nand/r852.h
   
+ +RISC-V ARCHITECTURE
+ +M:    Palmer Dabbelt <palmer@sifive.com>
+ +M:    Albert Ou <albert@sifive.com>
+ +L:    patches@groups.riscv.org
+ +T:    git https://github.com/riscv/riscv-linux
+ +S:    Supported
+ +F:    arch/riscv/
+ +K:    riscv
+ +N:    riscv
+ +
   ROCCAT DRIVERS
   M:    Stefan Achatz <erazor_de@users.sourceforge.net>
   W:    http://sourceforge.net/projects/roccat/
@@@ -11589,13 -11527,6 +11594,13 @@@ F: drivers/hid/hid-roccat
   F:    include/linux/hid-roccat*
   F:    Documentation/ABI/*/sysfs-driver-hid-roccat*
   
+ +ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER
+ +M:    Jacob chen <jacob2.chen@rock-chips.com>
+ +L:    linux-media@vger.kernel.org
+ +S:    Maintained
+ +F:    drivers/media/platform/rockchip/rga/
+ +F:    Documentation/devicetree/bindings/media/rockchip-rga.txt
+ +
   ROCKER DRIVER
   M:    Jiri Pirko <jiri@resnulli.us>
   L:    netdev@vger.kernel.org
@@@ -11840,7 -11771,7 +11845,7 @@@ L:   linux-crypto@vger.kernel.or
   L:    linux-samsung-soc@vger.kernel.org
   S:    Maintained
   F:    drivers/crypto/exynos-rng.c
- -F:    Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt
+ +F:    Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt
   
   SAMSUNG FRAMEBUFFER DRIVER
   M:    Jingoo Han <jingoohan1@gmail.com>
@@@ -12123,15 -12054,10 +12128,15 @@@ L:        linux-mmc@vger.kernel.or
   S:    Maintained
   F:    drivers/mmc/host/sdhci-spear.c
   
+ +SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) TI OMAP DRIVER
+ +M:    Kishon Vijay Abraham I <kishon@ti.com>
+ +L:    linux-mmc@vger.kernel.org
+ +S:    Maintained
+ +F:    drivers/mmc/host/sdhci-omap.c
+ +
   SECURE ENCRYPTING DEVICE (SED) OPAL DRIVER
   M:    Scott Bauer <scott.bauer@intel.com>
   M:    Jonathan Derrick <jonathan.derrick@intel.com>
- -M:    Rafael Antognolli <rafael.antognolli@intel.com>
   L:    linux-block@vger.kernel.org
   S:    Supported
   F:    block/sed*
@@@ -12532,10 -12458,7 +12537,10 @@@ M: Shaohua Li <shli@kernel.org
   L:    linux-raid@vger.kernel.org
   T:    git git://git.kernel.org/pub/scm/linux/kernel/git/shli/md.git
   S:    Supported
- -F:    drivers/md/
+ +F:    drivers/md/Makefile
+ +F:    drivers/md/Kconfig
+ +F:    drivers/md/md*
+ +F:    drivers/md/raid*
   F:    include/linux/raid/
   F:    include/uapi/linux/raid/
   
@@@ -12745,13 -12668,6 +12750,13 @@@ L: stable@vger.kernel.or
   S:    Supported
   F:    Documentation/process/stable-kernel-rules.rst
   
+ +STAGING - ATOMISP DRIVER
+ +M:    Alan Cox <alan@linux.intel.com>
+ +M:    Sakari Ailus <sakari.ailus@linux.intel.com>
+ +L:    linux-media@vger.kernel.org
+ +S:    Maintained
+ +F:    drivers/staging/media/atomisp/
+ +
   STAGING - COMEDI
   M:    Ian Abbott <abbotti@mev.co.uk>
   M:    H Hartley Sweeten <hsweeten@visionengravers.com>
@@@ -12995,16 -12911,9 +13000,16 @@@ F: arch/arc/plat-axs10
   F:    arch/arc/boot/dts/ax*
   F:    Documentation/devicetree/bindings/arc/axs10*
   
+ +SYNOPSYS DESIGNWARE APB GPIO DRIVER
+ +M:    Hoan Tran <hotran@apm.com>
+ +L:    linux-gpio@vger.kernel.org
+ +S:    Maintained
+ +F:    drivers/gpio/gpio-dwapb.c
+ +F:    Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
+ +
   SYNOPSYS DESIGNWARE DMAC DRIVER
   M:    Viresh Kumar <vireshk@kernel.org>
- -M:    Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ +R:    Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   S:    Maintained
   F:    include/linux/dma/dw.h
   F:    include/linux/platform_data/dma-dw.h
@@@ -13387,15 -13296,6 +13392,15 @@@ M: Mika Westerberg <mika.westerberg@lin
   M:    Yehezkel Bernat <yehezkel.bernat@intel.com>
   S:    Maintained
   F:    drivers/thunderbolt/
+ +F:    include/linux/thunderbolt.h
+ +
+ +THUNDERBOLT NETWORK DRIVER
+ +M:    Michael Jamet <michael.jamet@intel.com>
+ +M:    Mika Westerberg <mika.westerberg@linux.intel.com>
+ +M:    Yehezkel Bernat <yehezkel.bernat@intel.com>
+ +L:    netdev@vger.kernel.org
+ +S:    Maintained
+ +F:    drivers/net/thunderbolt.c
   
   THUNDERX GPIO DRIVER
   M:    David Daney <david.daney@cavium.com>
@@@ -13704,14 -13604,23 +13709,14 @@@ F:        drivers/platform/x86/toshiba-wmi.
   
   TPM DEVICE DRIVER
   M:    Peter Huewe <peterhuewe@gmx.de>
- -M:    Marcel Selhorst <tpmdd@selhorst.net>
   M:    Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
   R:    Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
- -W:    http://tpmdd.sourceforge.net
- -L:    tpmdd-devel@lists.sourceforge.net (moderated for non-subscribers)
- -Q:    https://patchwork.kernel.org/project/tpmdd-devel/list/
+ +L:    linux-integrity@vger.kernel.org
+ +Q:    https://patchwork.kernel.org/project/linux-integrity/list/
   T:    git git://git.infradead.org/users/jjs/linux-tpmdd.git
   S:    Maintained
   F:    drivers/char/tpm/
   
- -TPM IBM_VTPM DEVICE DRIVER
- -M:    Ashley Lai <ashleydlai@gmail.com>
- -W:    http://tpmdd.sourceforge.net
- -L:    tpmdd-devel@lists.sourceforge.net (moderated for non-subscribers)
- -S:    Maintained
- -F:    drivers/char/tpm/tpm_ibmvtpm*
- -
   TRACING
   M:    Steven Rostedt <rostedt@goodmis.org>
   M:    Ingo Molnar <mingo@redhat.com>
@@@ -13852,7 -13761,7 +13857,7 @@@ UDRAW TABLE
   M:    Bastien Nocera <hadess@hadess.net>
   L:    linux-input@vger.kernel.org
   S:    Maintained
- -F:    drivers/hid/hid-udraw.c
+ +F:    drivers/hid/hid-udraw-ps3.c
   
   UFS FILESYSTEM
   M:    Evgeniy Dushistov <dushistov@mail.ru>
@@@ -14375,15 -14284,12 +14380,15 @@@ S:        Maintaine
   F:    include/linux/virtio_vsock.h
   F:    include/uapi/linux/virtio_vsock.h
   F:    include/uapi/linux/vsockmon.h
+ +F:    include/uapi/linux/vm_sockets_diag.h
+ +F:    net/vmw_vsock/diag.c
   F:    net/vmw_vsock/af_vsock_tap.c
   F:    net/vmw_vsock/virtio_transport_common.c
   F:    net/vmw_vsock/virtio_transport.c
   F:    drivers/net/vsockmon.c
   F:    drivers/vhost/vsock.c
   F:    drivers/vhost/vsock.h
+ +F:    tools/testing/vsock/
   
   VIRTIO CONSOLE DRIVER
   M:    Amit Shah <amit@kernel.org>
@@@ -14424,7 -14330,6 +14429,7 @@@ L:   virtualization@lists.linux-foundatio
   L:    kvm@vger.kernel.org
   S:    Supported
   F:    drivers/s390/virtio/
+ +F:    arch/s390/include/uapi/asm/virtio-ccw.h
   
   VIRTIO GPU DRIVER
   M:    David Airlie <airlied@linux.ie>
@@@ -14647,6 -14552,7 +14652,6 @@@ L:   wil6210@qca.qualcomm.co
   S:    Supported
   W:    http://wireless.kernel.org/en/users/Drivers/wil6210
   F:    drivers/net/wireless/ath/wil6210/
- -F:    include/uapi/linux/wil6210_uapi.h
   
   WIMAX STACK
   M:    Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
@@@ -14697,7 -14603,6 +14702,7 @@@ F:   Documentation/devicetree/bindings/ex
   F:    Documentation/devicetree/bindings/regulator/arizona-regulator.txt
   F:    Documentation/devicetree/bindings/mfd/arizona.txt
   F:    Documentation/devicetree/bindings/mfd/wm831x.txt
+ +F:    Documentation/devicetree/bindings/sound/wlf,arizona.txt
   F:    arch/arm/mach-s3c64xx/mach-crag6410*
   F:    drivers/clk/clk-wm83*.c
   F:    drivers/extcon/extcon-arizona.c
diff --combined drivers/gpu/drm/Makefile

index 8ce07039bb898aae62333bc22a8f6e5878d8c789,81ff793366231ff0ed1d294873dc99675e4b336d..e9500844333e1652fed9b0325d322a3c260da08a
--- 1/drivers/gpu/drm/Makefile
--- 2/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   
   # Makefile for the drm device driver.  This driver provides support for the
   # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
@@@ -18,7 -17,7 +18,7 @@@ drm-y       :=        drm_auth.o drm_bufs.o dr
                 drm_encoder.o drm_mode_object.o drm_property.o \
                 drm_plane.o drm_color_mgmt.o drm_print.o \
                 drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \
-               drm_syncobj.o
+               drm_syncobj.o drm_lease.o
   
   drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
   drm-$(CONFIG_DRM_VM) += drm_vm.o
@@@ -29,6 -28,7 +29,7 @@@ drm-$(CONFIG_DRM_PANEL) += drm_panel.
   drm-$(CONFIG_OF) += drm_of.o
   drm-$(CONFIG_AGP) += drm_agpsupport.o
   drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
+ drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
   
   drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
                 drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
@@@ -37,7 -37,6 +38,6 @@@
                 drm_scdc_helper.o drm_gem_framebuffer_helper.o
   
   drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o
- drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
   drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o
   drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o
   drm_kms_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
@@@ -45,14 -44,13 +45,13 @@@
   obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
   obj-$(CONFIG_DRM_DEBUG_MM_SELFTEST) += selftests/
   
- CFLAGS_drm_trace_points.o := -I$(src)
- 
   obj-$(CONFIG_DRM)     += drm.o
   obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
   obj-$(CONFIG_DRM_ARM) += arm/
   obj-$(CONFIG_DRM_TTM) += ttm/
   obj-$(CONFIG_DRM_TDFX)        += tdfx/
   obj-$(CONFIG_DRM_R128)        += r128/
+ obj-y                 += amd/lib/
   obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
   obj-$(CONFIG_DRM_RADEON)+= radeon/
   obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
@@@ -101,3 -99,4 +100,4 @@@ obj-$(CONFIG_DRM_ZTE)       += zte
   obj-$(CONFIG_DRM_MXSFB)       += mxsfb/
   obj-$(CONFIG_DRM_TINYDRM) += tinydrm/
   obj-$(CONFIG_DRM_PL111) += pl111/
+ obj-$(CONFIG_DRM_TVE200) += tve200/
diff --combined drivers/gpu/drm/amd/amdgpu/Makefile

index 567b0377e1e21e1b36a8dd09137d4ad5a9799b65,ef9a3b6d7b6236beb3b6ce796297f2b72eeb594b..7fc42e0777705fd6597fb7631aca09f60d9dcf35
--- 1/drivers/gpu/drm/amd/amdgpu/Makefile
--- 2/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   #
   # Makefile for the drm device driver.  This driver provides support for the
   # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
@@@ -26,7 -25,7 +26,7 @@@ amdgpu-y += amdgpu_device.o amdgpu_kms.
         amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
         amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
         amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
-       amdgpu_queue_mgr.o amdgpu_vf_error.o
+       amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o
   
   # add asic specific block
   amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
@@@ -134,5 -133,3 +134,3 @@@ include $(FULL_AMD_PATH)/powerplay/Make
   amdgpu-y += $(AMD_POWERPLAY_FILES)
   
   obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
- 
- CFLAGS_amdgpu_trace_points.o := -I$(src)
diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

index cd664832f9e8c7e45895ddeb43bba487f15b4471,f7fceb63413c9b1c0769a85d38116ba15e43f2e4..6c78623e13863c6773d9dd4f7c4444de045f9f2b
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@@ -25,6 -25,7 +25,7 @@@
    *    Jerome Glisse <glisse@freedesktop.org>
    */
   #include <linux/pagemap.h>
+ #include <linux/sync_file.h>
   #include <drm/drmP.h>
   #include <drm/amdgpu_drm.h>
   #include <drm/drm_syncobj.h>
@@@ -89,12 -90,14 +90,14 @@@ static int amdgpu_cs_parser_init(struc
                 goto free_chunk;
         }
   
+       mutex_lock(&p->ctx->lock);
+ 
         /* get chunks */
         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
         if (copy_from_user(chunk_array, chunk_array_user,
                            sizeof(uint64_t)*cs->in.num_chunks)) {
                 ret = -EFAULT;
-               goto put_ctx;
+               goto free_chunk;
         }
   
         p->nchunks = cs->in.num_chunks;
@@@ -102,7 -105,7 +105,7 @@@
                             GFP_KERNEL);
         if (!p->chunks) {
                 ret = -ENOMEM;
-               goto put_ctx;
+               goto free_chunk;
         }
   
         for (i = 0; i < p->nchunks; i++) {
@@@ -169,6 -172,11 +172,11 @@@
         if (ret)
                 goto free_all_kdata;
   
+       if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
+               ret = -ECANCELED;
+               goto free_all_kdata;
+       }
+ 
         if (p->uf_entry.robj)
                 p->job->uf_addr = uf_offset;
         kfree(chunk_array);
@@@ -182,8 -190,6 +190,6 @@@ free_partial_kdata
         kfree(p->chunks);
         p->chunks = NULL;
         p->nchunks = 0;
- put_ctx:
-       amdgpu_ctx_put(p->ctx);
   free_chunk:
         kfree(chunk_array);
   
@@@ -473,11 -479,16 +479,16 @@@ static int amdgpu_cs_list_validate(stru
                         return -EPERM;
   
                 /* Check if we have user pages and nobody bound the BO already */
-               if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
-                       size_t size = sizeof(struct page *);
- 
-                       size *= bo->tbo.ttm->num_pages;
-                       memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
+               if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
+                   lobj->user_pages) {
+                       amdgpu_ttm_placement_from_domain(bo,
+                                                        AMDGPU_GEM_DOMAIN_CPU);
+                       r = ttm_bo_validate(&bo->tbo, &bo->placement, true,
+                                           false);
+                       if (r)
+                               return r;
+                       amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
+                                                    lobj->user_pages);
                         binding_userptr = true;
                 }
   
@@@ -502,7 -513,6 +513,6 @@@ static int amdgpu_cs_parser_bos(struct 
         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
         struct amdgpu_bo_list_entry *e;
         struct list_head duplicates;
-       bool need_mmap_lock = false;
         unsigned i, tries = 10;
         int r;
   
@@@ -510,9 -520,9 +520,9 @@@
   
         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
         if (p->bo_list) {
-               need_mmap_lock = p->bo_list->first_userptr !=
-                       p->bo_list->num_entries;
                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
+               if (p->bo_list->first_userptr != p->bo_list->num_entries)
+                       p->mn = amdgpu_mn_get(p->adev);
         }
   
         INIT_LIST_HEAD(&duplicates);
@@@ -521,9 -531,6 +531,6 @@@
         if (p->uf_entry.robj)
                 list_add(&p->uf_entry.tv.head, &p->validated);
   
-       if (need_mmap_lock)
-               down_read(&current->mm->mmap_sem);
- 
         while (1) {
                 struct list_head need_pages;
                 unsigned i;
@@@ -543,22 -550,25 +550,24 @@@
                 INIT_LIST_HEAD(&need_pages);
                 for (i = p->bo_list->first_userptr;
                      i < p->bo_list->num_entries; ++i) {
+                       struct amdgpu_bo *bo;
   
                         e = &p->bo_list->array[i];
+                       bo = e->robj;
   
-                       if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
+                       if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
                                  &e->user_invalidated) && e->user_pages) {
   
                                 /* We acquired a page array, but somebody
                                  * invalidated it. Free it and try again
                                  */
                                 release_pages(e->user_pages,
-                                             e->robj->tbo.ttm->num_pages);
- -                                            bo->tbo.ttm->num_pages,
- -                                            false);
++                                            bo->tbo.ttm->num_pages);
                                 kvfree(e->user_pages);
                                 e->user_pages = NULL;
                         }
   
-                       if (e->robj->tbo.ttm->state != tt_bound &&
+                       if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
                             !e->user_pages) {
                                 list_del(&e->tv.head);
                                 list_add(&e->tv.head, &need_pages);
@@@ -635,9 -645,6 +644,6 @@@
   
         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
                                      p->bytes_moved_vis);
-       fpriv->vm.last_eviction_counter =
-               atomic64_read(&p->adev->num_evictions);
- 
         if (p->bo_list) {
                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
@@@ -678,9 -685,6 +684,6 @@@ error_validate
   
   error_free_pages:
   
-       if (need_mmap_lock)
-               up_read(&current->mm->mmap_sem);
- 
         if (p->bo_list) {
                 for (i = p->bo_list->first_userptr;
                      i < p->bo_list->num_entries; ++i) {
@@@ -690,7 -694,8 +693,7 @@@
                                 continue;
   
                         release_pages(e->user_pages,
- -                                    e->robj->tbo.ttm->num_pages,
- -                                    false);
+ +                                    e->robj->tbo.ttm->num_pages);
                         kvfree(e->user_pages);
                 }
         }
@@@ -705,7 -710,8 +708,8 @@@ static int amdgpu_cs_sync_rings(struct 
   
         list_for_each_entry(e, &p->validated, tv.head) {
                 struct reservation_object *resv = e->robj->tbo.resv;
-               r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+               r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+                                    amdgpu_bo_explicit_sync(e->robj));
   
                 if (r)
                         return r;
@@@ -726,11 -732,7 +730,7 @@@ static void amdgpu_cs_parser_fini(struc
   {
         unsigned i;
   
-       if (!error)
-               ttm_eu_fence_buffer_objects(&parser->ticket,
-                                           &parser->validated,
-                                           parser->fence);
-       else if (backoff)
+       if (error && backoff)
                 ttm_eu_backoff_reservation(&parser->ticket,
                                            &parser->validated);
   
@@@ -740,8 -742,10 +740,10 @@@
   
         dma_fence_put(parser->fence);
   
-       if (parser->ctx)
+       if (parser->ctx) {
+               mutex_unlock(&parser->ctx->lock);
                 amdgpu_ctx_put(parser->ctx);
+       }
         if (parser->bo_list)
                 amdgpu_bo_list_put(parser->bo_list);
   
@@@ -766,10 -770,6 +768,6 @@@ static int amdgpu_bo_vm_update_pte(stru
         if (r)
                 return r;
   
-       r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
-       if (r)
-               return r;
- 
         r = amdgpu_vm_clear_freed(adev, vm, NULL);
         if (r)
                 return r;
@@@ -823,7 -823,13 +821,13 @@@
   
         }
   
-       r = amdgpu_vm_clear_moved(adev, vm, &p->job->sync);
+       r = amdgpu_vm_handle_moved(adev, vm);
+       if (r)
+               return r;
+ 
+       r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);
+       if (r)
+               return r;
   
         if (amdgpu_vm_debug && p->bo_list) {
                 /* Invalidate all BOs to test for userspace bugs */
@@@ -833,7 -839,7 +837,7 @@@
                         if (!bo)
                                 continue;
   
-                       amdgpu_vm_bo_invalidate(adev, bo);
+                       amdgpu_vm_bo_invalidate(adev, bo, false);
                 }
         }
   
@@@ -846,19 -852,63 +850,63 @@@ static int amdgpu_cs_ib_vm_chunk(struc
         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
         struct amdgpu_vm *vm = &fpriv->vm;
         struct amdgpu_ring *ring = p->job->ring;
-       int i, r;
+       int r;
   
         /* Only for UVD/VCE VM emulation */
-       if (ring->funcs->parse_cs) {
-               for (i = 0; i < p->job->num_ibs; i++) {
-                       r = amdgpu_ring_parse_cs(ring, p, i);
+       if (p->job->ring->funcs->parse_cs) {
+               unsigned i, j;
+ 
+               for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
+                       struct drm_amdgpu_cs_chunk_ib *chunk_ib;
+                       struct amdgpu_bo_va_mapping *m;
+                       struct amdgpu_bo *aobj = NULL;
+                       struct amdgpu_cs_chunk *chunk;
+                       struct amdgpu_ib *ib;
+                       uint64_t offset;
+                       uint8_t *kptr;
+ 
+                       chunk = &p->chunks[i];
+                       ib = &p->job->ibs[j];
+                       chunk_ib = chunk->kdata;
+ 
+                       if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
+                               continue;
+ 
+                       r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
+                                                  &aobj, &m);
+                       if (r) {
+                               DRM_ERROR("IB va_start is invalid\n");
+                               return r;
+                       }
+ 
+                       if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
+                           (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
+                               DRM_ERROR("IB va_start+ib_bytes is invalid\n");
+                               return -EINVAL;
+                       }
+ 
+                       /* the IB should be reserved at this point */
+                       r = amdgpu_bo_kmap(aobj, (void **)&kptr);
+                       if (r) {
+                               return r;
+                       }
+ 
+                       offset = m->start * AMDGPU_GPU_PAGE_SIZE;
+                       kptr += chunk_ib->va_start - offset;
+ 
+                       memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
+                       amdgpu_bo_kunmap(aobj);
+ 
+                       r = amdgpu_ring_parse_cs(ring, p, j);
                         if (r)
                                 return r;
+ 
+                       j++;
                 }
         }
   
         if (p->job->vm) {
-               p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
+               p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
   
                 r = amdgpu_bo_vm_update_pte(p);
                 if (r)
@@@ -920,54 -970,18 +968,18 @@@ static int amdgpu_cs_ib_fill(struct amd
   
                 parser->job->ring = ring;
   
-               if (ring->funcs->parse_cs) {
-                       struct amdgpu_bo_va_mapping *m;
-                       struct amdgpu_bo *aobj = NULL;
-                       uint64_t offset;
-                       uint8_t *kptr;
- 
-                       m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
-                                                  &aobj);
-                       if (!aobj) {
-                               DRM_ERROR("IB va_start is invalid\n");
-                               return -EINVAL;
-                       }
- 
-                       if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
-                           (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
-                               DRM_ERROR("IB va_start+ib_bytes is invalid\n");
-                               return -EINVAL;
-                       }
- 
-                       /* the IB should be reserved at this point */
-                       r = amdgpu_bo_kmap(aobj, (void **)&kptr);
-                       if (r) {
-                               return r;
-                       }
- 
-                       offset = m->start * AMDGPU_GPU_PAGE_SIZE;
-                       kptr += chunk_ib->va_start - offset;
- 
-                       r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
-                       if (r) {
-                               DRM_ERROR("Failed to get ib !\n");
-                               return r;
-                       }
- 
-                       memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
-                       amdgpu_bo_kunmap(aobj);
-               } else {
-                       r =  amdgpu_ib_get(adev, vm, 0, ib);
-                       if (r) {
-                               DRM_ERROR("Failed to get ib !\n");
-                               return r;
-                       }
- 
+               r =  amdgpu_ib_get(adev, vm,
+                                       ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
+                                       ib);
+               if (r) {
+                       DRM_ERROR("Failed to get ib !\n");
+                       return r;
                 }
   
                 ib->gpu_addr = chunk_ib->va_start;
                 ib->length_dw = chunk_ib->ib_bytes / 4;
                 ib->flags = chunk_ib->flags;
+ 
                 j++;
         }
   
@@@ -977,7 -991,7 +989,7 @@@
             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
                 return -EINVAL;
   
-       return 0;
+       return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
   }
   
   static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
@@@ -1131,14 -1145,31 +1143,31 @@@ static int amdgpu_cs_submit(struct amdg
         struct amdgpu_ring *ring = p->job->ring;
         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
         struct amdgpu_job *job;
+       unsigned i;
+       uint64_t seq;
+ 
         int r;
   
+       amdgpu_mn_lock(p->mn);
+       if (p->bo_list) {
+               for (i = p->bo_list->first_userptr;
+                    i < p->bo_list->num_entries; ++i) {
+                       struct amdgpu_bo *bo = p->bo_list->array[i].robj;
+ 
+                       if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
+                               amdgpu_mn_unlock(p->mn);
+                               return -ERESTARTSYS;
+                       }
+               }
+       }
+ 
         job = p->job;
         p->job = NULL;
   
         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
         if (r) {
                 amdgpu_job_free(job);
+               amdgpu_mn_unlock(p->mn);
                 return r;
         }
   
@@@ -1146,21 -1177,36 +1175,36 @@@
         job->fence_ctx = entity->fence_context;
         p->fence = dma_fence_get(&job->base.s_fence->finished);
   
+       r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
+       if (r) {
+               dma_fence_put(p->fence);
+               dma_fence_put(&job->base.s_fence->finished);
+               amdgpu_job_free(job);
+               amdgpu_mn_unlock(p->mn);
+               return r;
+       }
+ 
         amdgpu_cs_post_dependencies(p);
   
-       cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
-       job->uf_sequence = cs->out.handle;
+       cs->out.handle = seq;
+       job->uf_sequence = seq;
+ 
         amdgpu_job_free_resources(job);
+       amdgpu_ring_priority_get(job->ring,
+                                amd_sched_get_job_priority(&job->base));
   
         trace_amdgpu_cs_ioctl(job);
         amd_sched_entity_push_job(&job->base);
+ 
+       ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
+       amdgpu_mn_unlock(p->mn);
+ 
         return 0;
   }
   
   int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
   {
         struct amdgpu_device *adev = dev->dev_private;
-       struct amdgpu_fpriv *fpriv = filp->driver_priv;
         union drm_amdgpu_cs *cs = data;
         struct amdgpu_cs_parser parser = {};
         bool reserved_buffers = false;
@@@ -1168,8 -1214,6 +1212,6 @@@
   
         if (!adev->accel_working)
                 return -EBUSY;
-       if (amdgpu_kms_vram_lost(adev, fpriv))
-               return -ENODEV;
   
         parser.adev = adev;
         parser.filp = filp;
@@@ -1180,6 -1224,10 +1222,10 @@@
                 goto out;
         }
   
+       r = amdgpu_cs_ib_fill(adev, &parser);
+       if (r)
+               goto out;
+ 
         r = amdgpu_cs_parser_bos(&parser, data);
         if (r) {
                 if (r == -ENOMEM)
@@@ -1190,9 -1238,6 +1236,6 @@@
         }
   
         reserved_buffers = true;
-       r = amdgpu_cs_ib_fill(adev, &parser);
-       if (r)
-               goto out;
   
         r = amdgpu_cs_dependencies(adev, &parser);
         if (r) {
@@@ -1228,16 -1273,12 +1271,12 @@@ int amdgpu_cs_wait_ioctl(struct drm_dev
   {
         union drm_amdgpu_wait_cs *wait = data;
         struct amdgpu_device *adev = dev->dev_private;
-       struct amdgpu_fpriv *fpriv = filp->driver_priv;
         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
         struct amdgpu_ring *ring = NULL;
         struct amdgpu_ctx *ctx;
         struct dma_fence *fence;
         long r;
   
-       if (amdgpu_kms_vram_lost(adev, fpriv))
-               return -ENODEV;
- 
         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
         if (ctx == NULL)
                 return -EINVAL;
@@@ -1255,6 -1296,8 +1294,8 @@@
                 r = PTR_ERR(fence);
         else if (fence) {
                 r = dma_fence_wait_timeout(fence, true, timeout);
+               if (r > 0 && fence->error)
+                       r = fence->error;
                 dma_fence_put(fence);
         } else
                 r = 1;
@@@ -1302,6 -1345,62 +1343,62 @@@ static struct dma_fence *amdgpu_cs_get_
         return fence;
   }
   
+ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+                                   struct drm_file *filp)
+ {
+       struct amdgpu_device *adev = dev->dev_private;
+       union drm_amdgpu_fence_to_handle *info = data;
+       struct dma_fence *fence;
+       struct drm_syncobj *syncobj;
+       struct sync_file *sync_file;
+       int fd, r;
+ 
+       fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
+       if (IS_ERR(fence))
+               return PTR_ERR(fence);
+ 
+       switch (info->in.what) {
+       case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
+               r = drm_syncobj_create(&syncobj, 0, fence);
+               dma_fence_put(fence);
+               if (r)
+                       return r;
+               r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
+               drm_syncobj_put(syncobj);
+               return r;
+ 
+       case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
+               r = drm_syncobj_create(&syncobj, 0, fence);
+               dma_fence_put(fence);
+               if (r)
+                       return r;
+               r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+               drm_syncobj_put(syncobj);
+               return r;
+ 
+       case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
+               fd = get_unused_fd_flags(O_CLOEXEC);
+               if (fd < 0) {
+                       dma_fence_put(fence);
+                       return fd;
+               }
+ 
+               sync_file = sync_file_create(fence);
+               dma_fence_put(fence);
+               if (!sync_file) {
+                       put_unused_fd(fd);
+                       return -ENOMEM;
+               }
+ 
+               fd_install(fd, sync_file->file);
+               info->out.handle = fd;
+               return 0;
+ 
+       default:
+               return -EINVAL;
+       }
+ }
+ 
   /**
    * amdgpu_cs_wait_all_fence - wait on all fences to signal
    *
@@@ -1336,6 -1435,9 +1433,9 @@@ static int amdgpu_cs_wait_all_fences(st
   
                 if (r == 0)
                         break;
+ 
+               if (fence->error)
+                       return fence->error;
         }
   
         memset(wait, 0, sizeof(*wait));
@@@ -1381,6 -1483,7 +1481,7 @@@ static int amdgpu_cs_wait_any_fence(str
                         array[i] = fence;
                 } else { /* NULL, the fence has been already signaled */
                         r = 1;
+                       first = i;
                         goto out;
                 }
         }
@@@ -1395,7 -1498,7 +1496,7 @@@ out
         wait->out.status = (r > 0);
         wait->out.first_signaled = first;
         /* set return value 0 to indicate success */
-       r = 0;
+       r = array[first]->error;
   
   err_free_fence_array:
         for (i = 0; i < fence_count; i++)
@@@ -1416,15 -1519,12 +1517,12 @@@ int amdgpu_cs_wait_fences_ioctl(struct 
                                 struct drm_file *filp)
   {
         struct amdgpu_device *adev = dev->dev_private;
-       struct amdgpu_fpriv *fpriv = filp->driver_priv;
         union drm_amdgpu_wait_fences *wait = data;
         uint32_t fence_count = wait->in.fence_count;
         struct drm_amdgpu_fence *fences_user;
         struct drm_amdgpu_fence *fences;
         int r;
   
-       if (amdgpu_kms_vram_lost(adev, fpriv))
-               return -ENODEV;
         /* Get the fences from userspace */
         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
                         GFP_KERNEL);
@@@ -1460,78 -1560,36 +1558,36 @@@ err_free_fences
    * virtual memory address. Returns allocation structure when found, NULL
    * otherwise.
    */
- struct amdgpu_bo_va_mapping *
- amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
-                      uint64_t addr, struct amdgpu_bo **bo)
+ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+                          uint64_t addr, struct amdgpu_bo **bo,
+                          struct amdgpu_bo_va_mapping **map)
   {
+       struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
+       struct amdgpu_vm *vm = &fpriv->vm;
         struct amdgpu_bo_va_mapping *mapping;
-       unsigned i;
- 
-       if (!parser->bo_list)
-               return NULL;
- 
-       addr /= AMDGPU_GPU_PAGE_SIZE;
- 
-       for (i = 0; i < parser->bo_list->num_entries; i++) {
-               struct amdgpu_bo_list_entry *lobj;
- 
-               lobj = &parser->bo_list->array[i];
-               if (!lobj->bo_va)
-                       continue;
- 
-               list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
-                       if (mapping->start > addr ||
-                           addr > mapping->last)
-                               continue;
- 
-                       *bo = lobj->bo_va->base.bo;
-                       return mapping;
-               }
- 
-               list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
-                       if (mapping->start > addr ||
-                           addr > mapping->last)
-                               continue;
- 
-                       *bo = lobj->bo_va->base.bo;
-                       return mapping;
-               }
-       }
- 
-       return NULL;
- }
- 
- /**
-  * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
-  *
-  * @parser: command submission parser context
-  *
-  * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
-  */
- int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
- {
-       unsigned i;
         int r;
   
-       if (!parser->bo_list)
-               return 0;
+       addr /= AMDGPU_GPU_PAGE_SIZE;
   
-       for (i = 0; i < parser->bo_list->num_entries; i++) {
-               struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
+       mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
+       if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
+               return -EINVAL;
   
-               r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
-               if (unlikely(r))
-                       return r;
+       *bo = mapping->bo_va->base.bo;
+       *map = mapping;
   
-               if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
-                       continue;
+       /* Double check that the BO is reserved by this CS */
+       if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
+               return -EINVAL;
   
-               bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-               amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
-               r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
-               if (unlikely(r))
+       if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
+               (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+               amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
+               r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,
+                                   false);
+               if (r)
                         return r;
         }
   
-       return 0;
+       return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem);
   }
diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

index 303b5e099a98e6c3f6fe355f520ca61b133a6534,fb9f88ef6059f2a6e8d65a62f4ebe40d45d4331b..bd5b8065c32e86fcf4e71c25779cffee2939d203
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@@ -168,6 -168,32 +168,32 @@@ int amdgpu_fence_emit(struct amdgpu_rin
         return 0;
   }
   
+ /**
+  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
+  *
+  * @ring: ring the fence is associated with
+  * @s: resulting sequence number
+  *
+  * Emits a fence command on the requested ring (all asics).
+  * Used For polling fence.
+  * Returns 0 on success, -ENOMEM on failure.
+  */
+ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
+ {
+       uint32_t seq;
+ 
+       if (!s)
+               return -EINVAL;
+ 
+       seq = ++ring->fence_drv.sync_seq;
+       amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
+                              seq, AMDGPU_FENCE_FLAG_INT);
+ 
+       *s = seq;
+ 
+       return 0;
+ }
+ 
   /**
    * amdgpu_fence_schedule_fallback - schedule fallback check
    *
@@@ -260,7 -286,7 +286,7 @@@ static void amdgpu_fence_fallback(unsig
    */
   int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
   {
- -      uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
+ +      uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
         struct dma_fence *fence, **ptr;
         int r;
   
@@@ -281,6 -307,30 +307,30 @@@
         return r;
   }
   
+ /**
+  * amdgpu_fence_wait_polling - busy wait for givn sequence number
+  *
+  * @ring: ring index the fence is associated with
+  * @wait_seq: sequence number to wait
+  * @timeout: the timeout for waiting in usecs
+  *
+  * Wait for all fences on the requested ring to signal (all asics).
+  * Returns left time if no timeout, 0 or minus if timeout.
+  */
+ signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
+                                     uint32_t wait_seq,
+                                     signed long timeout)
+ {
+       uint32_t seq;
+ 
+       do {
+               seq = amdgpu_fence_read(ring);
+               udelay(5);
+               timeout -= 5;
+       } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
+ 
+       return timeout > 0 ? timeout : 0;
+ }
   /**
    * amdgpu_fence_count_emitted - get the count of emitted fences
    *
@@@ -300,7 -350,7 +350,7 @@@ unsigned amdgpu_fence_count_emitted(str
         amdgpu_fence_process(ring);
         emitted = 0x100000000ull;
         emitted -= atomic_read(&ring->fence_drv.last_seq);
- -      emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
+ +      emitted += READ_ONCE(ring->fence_drv.sync_seq);
         return lower_32_bits(emitted);
   }
   
@@@ -641,6 -691,19 +691,19 @@@ static int amdgpu_debugfs_fence_info(st
                            atomic_read(&ring->fence_drv.last_seq));
                 seq_printf(m, "Last emitted        0x%08x\n",
                            ring->fence_drv.sync_seq);
+ 
+               if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
+                       continue;
+ 
+               /* set in CP_VMID_PREEMPT and preemption occurred */
+               seq_printf(m, "Last preempted      0x%08x\n",
+                          le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
+               /* set in CP_VMID_RESET and reset occurred */
+               seq_printf(m, "Last reset          0x%08x\n",
+                          le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
+               /* Both preemption and reset occurred */
+               seq_printf(m, "Last both           0x%08x\n",
+                          le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
         }
         return 0;
   }
diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

index 0bda8f2a188ab017fb353f07cb13cc42b91c6e15,fb72edc4c0263659f39fa778995a14c40afcce79..a418df1b942274579e4da7a767e0138d95c38c90
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@@ -44,11 -44,12 +44,12 @@@ void amdgpu_gem_object_free(struct drm_
   }
   
   int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
-                               int alignment, u32 initial_domain,
-                               u64 flags, bool kernel,
-                               struct drm_gem_object **obj)
+                            int alignment, u32 initial_domain,
+                            u64 flags, bool kernel,
+                            struct reservation_object *resv,
+                            struct drm_gem_object **obj)
   {
-       struct amdgpu_bo *robj;
+       struct amdgpu_bo *bo;
         int r;
   
         *obj = NULL;
@@@ -59,7 -60,7 +60,7 @@@
   
   retry:
         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
-                            flags, NULL, NULL, 0, &robj);
+                            flags, NULL, resv, 0, &bo);
         if (r) {
                 if (r != -ERESTARTSYS) {
                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
@@@ -71,7 -72,7 +72,7 @@@
                 }
                 return r;
         }
-       *obj = &robj->gem_base;
+       *obj = &bo->gem_base;
   
         return 0;
   }
@@@ -112,7 -113,17 +113,17 @@@ int amdgpu_gem_object_open(struct drm_g
         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
         struct amdgpu_vm *vm = &fpriv->vm;
         struct amdgpu_bo_va *bo_va;
+       struct mm_struct *mm;
         int r;
+ 
+       mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
+       if (mm && mm != current->mm)
+               return -EPERM;
+ 
+       if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
+           abo->tbo.resv != vm->root.base.bo->tbo.resv)
+               return -EPERM;
+ 
         r = amdgpu_bo_reserve(abo, false);
         if (r)
                 return r;
@@@ -127,35 -138,6 +138,6 @@@
         return 0;
   }
   
- static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo)
- {
-       /* if anything is swapped out don't swap it in here,
-          just abort and wait for the next CS */
-       if (!amdgpu_bo_gpu_accessible(bo))
-               return -ERESTARTSYS;
- 
-       if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
-               return -ERESTARTSYS;
- 
-       return 0;
- }
- 
- static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev,
-                               struct amdgpu_vm *vm,
-                               struct list_head *list)
- {
-       struct ttm_validate_buffer *entry;
- 
-       list_for_each_entry(entry, list, head) {
-               struct amdgpu_bo *bo =
-                       container_of(entry->bo, struct amdgpu_bo, tbo);
-               if (amdgpu_gem_vm_check(NULL, bo))
-                       return false;
-       }
- 
-       return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL);
- }
- 
   void amdgpu_gem_object_close(struct drm_gem_object *obj,
                              struct drm_file *file_priv)
   {
@@@ -165,13 -147,14 +147,14 @@@
         struct amdgpu_vm *vm = &fpriv->vm;
   
         struct amdgpu_bo_list_entry vm_pd;
-       struct list_head list;
+       struct list_head list, duplicates;
         struct ttm_validate_buffer tv;
         struct ww_acquire_ctx ticket;
         struct amdgpu_bo_va *bo_va;
         int r;
   
         INIT_LIST_HEAD(&list);
+       INIT_LIST_HEAD(&duplicates);
   
         tv.bo = &bo->tbo;
         tv.shared = true;
@@@ -179,7 -162,7 +162,7 @@@
   
         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
   
-       r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
+       r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
         if (r) {
                 dev_err(adev->dev, "leaking bo va because "
                         "we fail to reserve bo (%d)\n", r);
@@@ -189,7 -172,7 +172,7 @@@
         if (bo_va && --bo_va->ref_count == 0) {
                 amdgpu_vm_bo_rmv(adev, bo_va);
   
-               if (amdgpu_gem_vm_ready(adev, vm, &list)) {
+               if (amdgpu_vm_ready(vm)) {
                         struct dma_fence *fence = NULL;
   
                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
@@@ -214,18 -197,24 +197,24 @@@ int amdgpu_gem_create_ioctl(struct drm_
                             struct drm_file *filp)
   {
         struct amdgpu_device *adev = dev->dev_private;
+       struct amdgpu_fpriv *fpriv = filp->driver_priv;
+       struct amdgpu_vm *vm = &fpriv->vm;
         union drm_amdgpu_gem_create *args = data;
+       uint64_t flags = args->in.domain_flags;
         uint64_t size = args->in.bo_size;
+       struct reservation_object *resv = NULL;
         struct drm_gem_object *gobj;
         uint32_t handle;
-       bool kernel = false;
         int r;
   
         /* reject invalid gem flags */
-       if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-                                     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-                                     AMDGPU_GEM_CREATE_CPU_GTT_USWC |
-                                     AMDGPU_GEM_CREATE_VRAM_CLEARED))
+       if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+                     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+                     AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+                     AMDGPU_GEM_CREATE_VRAM_CLEARED |
+                     AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+                     AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+ 
                 return -EINVAL;
   
         /* reject invalid gem domains */
@@@ -240,7 -229,7 +229,7 @@@
         /* create a gem object to contain this object in */
         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
-               kernel = true;
+               flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
                         size = size << AMDGPU_GDS_SHIFT;
                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
@@@ -252,10 -241,25 +241,25 @@@
         }
         size = roundup(size, PAGE_SIZE);
   
+       if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
+               r = amdgpu_bo_reserve(vm->root.base.bo, false);
+               if (r)
+                       return r;
+ 
+               resv = vm->root.base.bo->tbo.resv;
+       }
+ 
         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
                                      (u32)(0xffffffff & args->in.domains),
-                                    args->in.domain_flags,
-                                    kernel, &gobj);
+                                    flags, false, resv, &gobj);
+       if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
+               if (!r) {
+                       struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
+ 
+                       abo->parent = amdgpu_bo_ref(vm->root.base.bo);
+               }
+               amdgpu_bo_unreserve(vm->root.base.bo);
+       }
         if (r)
                 return r;
   
@@@ -297,9 -301,8 +301,8 @@@ int amdgpu_gem_userptr_ioctl(struct drm
         }
   
         /* create a gem object to contain this object in */
-       r = amdgpu_gem_object_create(adev, args->size, 0,
-                                    AMDGPU_GEM_DOMAIN_CPU, 0,
-                                    0, &gobj);
+       r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
+                                    0, 0, NULL, &gobj);
         if (r)
                 return r;
   
@@@ -317,8 -320,6 +320,6 @@@
         }
   
         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
-               down_read(&current->mm->mmap_sem);
- 
                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
                                                  bo->tbo.ttm->pages);
                 if (r)
@@@ -333,8 -334,6 +334,6 @@@
                 amdgpu_bo_unreserve(bo);
                 if (r)
                         goto free_pages;
- 
-               up_read(&current->mm->mmap_sem);
         }
   
         r = drm_gem_handle_create(filp, gobj, &handle);
@@@ -347,7 -346,7 +346,7 @@@
         return 0;
   
   free_pages:
- -      release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
+ +      release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
   
   unlock_mmap_sem:
         up_read(&current->mm->mmap_sem);
@@@ -511,10 -510,10 +510,10 @@@ static void amdgpu_gem_va_update_vm(str
                                     struct list_head *list,
                                     uint32_t operation)
   {
-       int r = -ERESTARTSYS;
+       int r;
   
-       if (!amdgpu_gem_vm_ready(adev, vm, list))
-               goto error;
+       if (!amdgpu_vm_ready(vm))
+               return;
   
         r = amdgpu_vm_update_directories(adev, vm);
         if (r)
@@@ -551,7 -550,7 +550,7 @@@ int amdgpu_gem_va_ioctl(struct drm_devi
         struct amdgpu_bo_list_entry vm_pd;
         struct ttm_validate_buffer tv;
         struct ww_acquire_ctx ticket;
-       struct list_head list;
+       struct list_head list, duplicates;
         uint64_t va_flags;
         int r = 0;
   
@@@ -580,13 -579,9 +579,9 @@@
                         args->operation);
                 return -EINVAL;
         }
-       if ((args->operation == AMDGPU_VA_OP_MAP) ||
-           (args->operation == AMDGPU_VA_OP_REPLACE)) {
-               if (amdgpu_kms_vram_lost(adev, fpriv))
-                       return -ENODEV;
-       }
   
         INIT_LIST_HEAD(&list);
+       INIT_LIST_HEAD(&duplicates);
         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
                 gobj = drm_gem_object_lookup(filp, args->handle);
@@@ -603,7 -598,7 +598,7 @@@
   
         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
   
-       r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
+       r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
         if (r)
                 goto error_unref;
   
@@@ -669,6 -664,7 +664,7 @@@ error_unref
   int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
                         struct drm_file *filp)
   {
+       struct amdgpu_device *adev = dev->dev_private;
         struct drm_amdgpu_gem_op *args = data;
         struct drm_gem_object *gobj;
         struct amdgpu_bo *robj;
@@@ -716,6 -712,9 +712,9 @@@
                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
   
+               if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
+                       amdgpu_vm_bo_invalidate(adev, robj, true);
+ 
                 amdgpu_bo_unreserve(robj);
                 break;
         default:
@@@ -745,8 -744,7 +744,7 @@@ int amdgpu_mode_dumb_create(struct drm_
         r = amdgpu_gem_object_create(adev, args->size, 0,
                                      AMDGPU_GEM_DOMAIN_VRAM,
                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
-                                    ttm_bo_type_device,
-                                    &gobj);
+                                    false, NULL, &gobj);
         if (r)
                 return -ENOMEM;
   
@@@ -788,11 -786,11 +786,11 @@@ static int amdgpu_debugfs_gem_bo_info(i
         seq_printf(m, "\t0x%08x: %12ld byte %s",
                    id, amdgpu_bo_size(bo), placement);
   
- -      offset = ACCESS_ONCE(bo->tbo.mem.start);
+ +      offset = READ_ONCE(bo->tbo.mem.start);
         if (offset != AMDGPU_BO_INVALID_OFFSET)
                 seq_printf(m, " @ 0x%010Lx", offset);
   
- -      pin_count = ACCESS_ONCE(bo->pin_count);
+ +      pin_count = READ_ONCE(bo->pin_count);
         if (pin_count)
                 seq_printf(m, " pin count %d", pin_count);
         seq_printf(m, "\n");
diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

index 34c99a3c8d2d697d1123f6bb062632b5e09e6951,213988f336eddeba7f19816f4dde80f2a272d134..f337c316ec2c656a823230b355250929715db327
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
   #define _AMDGPU_TRACE_H_
   
@@@ -15,62 -14,6 +15,6 @@@
   #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
          job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
   
- TRACE_EVENT(amdgpu_ttm_tt_populate,
-           TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address),
-           TP_ARGS(adev, dma_address, phys_address),
-           TP_STRUCT__entry(
-                               __field(uint16_t, domain)
-                               __field(uint8_t, bus)
-                               __field(uint8_t, slot)
-                               __field(uint8_t, func)
-                               __field(uint64_t, dma)
-                               __field(uint64_t, phys)
-                           ),
-           TP_fast_assign(
-                          __entry->domain = pci_domain_nr(adev->pdev->bus);
-                          __entry->bus = adev->pdev->bus->number;
-                          __entry->slot = PCI_SLOT(adev->pdev->devfn);
-                          __entry->func = PCI_FUNC(adev->pdev->devfn);
-                          __entry->dma = dma_address;
-                          __entry->phys = phys_address;
-                          ),
-           TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx",
-                     (unsigned)__entry->domain,
-                     (unsigned)__entry->bus,
-                     (unsigned)__entry->slot,
-                     (unsigned)__entry->func,
-                     (unsigned long long)__entry->dma,
-                     (unsigned long long)__entry->phys)
- );
- 
- TRACE_EVENT(amdgpu_ttm_tt_unpopulate,
-           TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address),
-           TP_ARGS(adev, dma_address, phys_address),
-           TP_STRUCT__entry(
-                               __field(uint16_t, domain)
-                               __field(uint8_t, bus)
-                               __field(uint8_t, slot)
-                               __field(uint8_t, func)
-                               __field(uint64_t, dma)
-                               __field(uint64_t, phys)
-                           ),
-           TP_fast_assign(
-                          __entry->domain = pci_domain_nr(adev->pdev->bus);
-                          __entry->bus = adev->pdev->bus->number;
-                          __entry->slot = PCI_SLOT(adev->pdev->devfn);
-                          __entry->func = PCI_FUNC(adev->pdev->devfn);
-                          __entry->dma = dma_address;
-                          __entry->phys = phys_address;
-                          ),
-           TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx",
-                     (unsigned)__entry->domain,
-                     (unsigned)__entry->bus,
-                     (unsigned)__entry->slot,
-                     (unsigned)__entry->func,
-                     (unsigned long long)__entry->dma,
-                     (unsigned long long)__entry->phys)
- );
- 
   TRACE_EVENT(amdgpu_mm_rreg,
             TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
             TP_ARGS(did, reg, value),
@@@ -474,5 -417,5 +418,5 @@@ TRACE_EVENT(amdgpu_ttm_bo_move
   
   /* This part must be outside protection */
   #undef TRACE_INCLUDE_PATH
- #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu
   #include <trace/define_trace.h>
diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c

index 89680d554ed8320c9fcc3485d38539607b48fa80,9ec96b9e85d169fdd793733ea48d020cb2f7a92c..b160b958e5fe2b12326a63655d046b92c62c21e6
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
@@@ -1,5 -1,23 +1,24 @@@
+ +// SPDX-License-Identifier: GPL-2.0
   /* Copyright Red Hat Inc 2010.
+  *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+  * and/or sell copies of the Software, and to permit persons to whom the
+  * Software is furnished to do so, subject to the following conditions:
+  *
+  * The above copyright notice and this permission notice shall be included in
+  * all copies or substantial portions of the Software.
+  *
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  *
    * Author : Dave Airlie <airlied@redhat.com>
    */
   #include <drm/drmP.h>
diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index d792959fac43b9e43dc7950f424744f69a702236,1f036af85ba6bd1eb03fee9392966252fff800c5..ad5bf86ee8a31911e1bf014b2f354f39a88fd337
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@@ -42,7 -42,9 +42,9 @@@
   #include <linux/swap.h>
   #include <linux/pagemap.h>
   #include <linux/debugfs.h>
+ #include <linux/iommu.h>
   #include "amdgpu.h"
+ #include "amdgpu_object.h"
   #include "amdgpu_trace.h"
   #include "bif/bif_4_1_d.h"
   
@@@ -208,7 -210,7 +210,7 @@@ static void amdgpu_evict_flags(struct t
                 placement->num_busy_placement = 1;
                 return;
         }
-       abo = container_of(bo, struct amdgpu_bo, tbo);
+       abo = ttm_to_amdgpu_bo(bo);
         switch (bo->mem.mem_type) {
         case TTM_PL_VRAM:
                 if (adev->mman.buffer_funcs &&
@@@ -256,7 -258,7 +258,7 @@@ gtt
   
   static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
   {
-       struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
+       struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
   
         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
                 return -EPERM;
@@@ -288,97 -290,177 +290,177 @@@ static uint64_t amdgpu_mm_node_addr(str
         return addr;
   }
   
- static int amdgpu_move_blit(struct ttm_buffer_object *bo,
-                           bool evict, bool no_wait_gpu,
-                           struct ttm_mem_reg *new_mem,
-                           struct ttm_mem_reg *old_mem)
+ /**
+  * amdgpu_find_mm_node - Helper function finds the drm_mm_node
+  *  corresponding to @offset. It also modifies the offset to be
+  *  within the drm_mm_node returned
+  */
+ static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
+                                              unsigned long *offset)
   {
-       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
-       struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+       struct drm_mm_node *mm_node = mem->mm_node;
   
-       struct drm_mm_node *old_mm, *new_mm;
-       uint64_t old_start, old_size, new_start, new_size;
-       unsigned long num_pages;
-       struct dma_fence *fence = NULL;
-       int r;
+       while (*offset >= (mm_node->size << PAGE_SHIFT)) {
+               *offset -= (mm_node->size << PAGE_SHIFT);
+               ++mm_node;
+       }
+       return mm_node;
+ }
   
-       BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
+ /**
+  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
+  *
+  * The function copies @size bytes from {src->mem + src->offset} to
+  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
+  * move and different for a BO to BO copy.
+  *
+  * @f: Returns the last fence if multiple jobs are submitted.
+  */
+ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+                              struct amdgpu_copy_mem *src,
+                              struct amdgpu_copy_mem *dst,
+                              uint64_t size,
+                              struct reservation_object *resv,
+                              struct dma_fence **f)
+ {
+       struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+       struct drm_mm_node *src_mm, *dst_mm;
+       uint64_t src_node_start, dst_node_start, src_node_size,
+                dst_node_size, src_page_offset, dst_page_offset;
+       struct dma_fence *fence = NULL;
+       int r = 0;
+       const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
+                                       AMDGPU_GPU_PAGE_SIZE);
   
         if (!ring->ready) {
                 DRM_ERROR("Trying to move memory with ring turned off.\n");
                 return -EINVAL;
         }
   
-       old_mm = old_mem->mm_node;
-       old_size = old_mm->size;
-       old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
+       src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
+       src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
+                                            src->offset;
+       src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
+       src_page_offset = src_node_start & (PAGE_SIZE - 1);
   
-       new_mm = new_mem->mm_node;
-       new_size = new_mm->size;
-       new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
+       dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
+       dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
+                                            dst->offset;
+       dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
+       dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
   
-       num_pages = new_mem->num_pages;
         mutex_lock(&adev->mman.gtt_window_lock);
-       while (num_pages) {
-               unsigned long cur_pages = min(min(old_size, new_size),
-                                             (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
-               uint64_t from = old_start, to = new_start;
+ 
+       while (size) {
+               unsigned long cur_size;
+               uint64_t from = src_node_start, to = dst_node_start;
                 struct dma_fence *next;
   
-               if (old_mem->mem_type == TTM_PL_TT &&
-                   !amdgpu_gtt_mgr_is_allocated(old_mem)) {
-                       r = amdgpu_map_buffer(bo, old_mem, cur_pages,
-                                             old_start, 0, ring, &from);
+               /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
+                * begins at an offset, then adjust the size accordingly
+                */
+               cur_size = min3(min(src_node_size, dst_node_size), size,
+                               GTT_MAX_BYTES);
+               if (cur_size + src_page_offset > GTT_MAX_BYTES ||
+                   cur_size + dst_page_offset > GTT_MAX_BYTES)
+                       cur_size -= max(src_page_offset, dst_page_offset);
+ 
+               /* Map only what needs to be accessed. Map src to window 0 and
+                * dst to window 1
+                */
+               if (src->mem->mem_type == TTM_PL_TT &&
+                   !amdgpu_gtt_mgr_is_allocated(src->mem)) {
+                       r = amdgpu_map_buffer(src->bo, src->mem,
+                                       PFN_UP(cur_size + src_page_offset),
+                                       src_node_start, 0, ring,
+                                       &from);
                         if (r)
                                 goto error;
+                       /* Adjust the offset because amdgpu_map_buffer returns
+                        * start of mapped page
+                        */
+                       from += src_page_offset;
                 }
   
-               if (new_mem->mem_type == TTM_PL_TT &&
-                   !amdgpu_gtt_mgr_is_allocated(new_mem)) {
-                       r = amdgpu_map_buffer(bo, new_mem, cur_pages,
-                                             new_start, 1, ring, &to);
+               if (dst->mem->mem_type == TTM_PL_TT &&
+                   !amdgpu_gtt_mgr_is_allocated(dst->mem)) {
+                       r = amdgpu_map_buffer(dst->bo, dst->mem,
+                                       PFN_UP(cur_size + dst_page_offset),
+                                       dst_node_start, 1, ring,
+                                       &to);
                         if (r)
                                 goto error;
+                       to += dst_page_offset;
                 }
   
-               r = amdgpu_copy_buffer(ring, from, to,
-                                      cur_pages * PAGE_SIZE,
-                                      bo->resv, &next, false, true);
+               r = amdgpu_copy_buffer(ring, from, to, cur_size,
+                                      resv, &next, false, true);
                 if (r)
                         goto error;
   
                 dma_fence_put(fence);
                 fence = next;
   
-               num_pages -= cur_pages;
-               if (!num_pages)
+               size -= cur_size;
+               if (!size)
                         break;
   
-               old_size -= cur_pages;
-               if (!old_size) {
-                       old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
-                       old_size = old_mm->size;
+               src_node_size -= cur_size;
+               if (!src_node_size) {
+                       src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
+                                                            src->mem);
+                       src_node_size = (src_mm->size << PAGE_SHIFT);
                 } else {
-                       old_start += cur_pages * PAGE_SIZE;
+                       src_node_start += cur_size;
+                       src_page_offset = src_node_start & (PAGE_SIZE - 1);
                 }
- 
-               new_size -= cur_pages;
-               if (!new_size) {
-                       new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
-                       new_size = new_mm->size;
+               dst_node_size -= cur_size;
+               if (!dst_node_size) {
+                       dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
+                                                            dst->mem);
+                       dst_node_size = (dst_mm->size << PAGE_SHIFT);
                 } else {
-                       new_start += cur_pages * PAGE_SIZE;
+                       dst_node_start += cur_size;
+                       dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
                 }
         }
+ error:
         mutex_unlock(&adev->mman.gtt_window_lock);
+       if (f)
+               *f = dma_fence_get(fence);
+       dma_fence_put(fence);
+       return r;
+ }
+ 
+ 
+ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
+                           bool evict, bool no_wait_gpu,
+                           struct ttm_mem_reg *new_mem,
+                           struct ttm_mem_reg *old_mem)
+ {
+       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
+       struct amdgpu_copy_mem src, dst;
+       struct dma_fence *fence = NULL;
+       int r;
+ 
+       src.bo = bo;
+       dst.bo = bo;
+       src.mem = old_mem;
+       dst.mem = new_mem;
+       src.offset = 0;
+       dst.offset = 0;
+ 
+       r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
+                                      new_mem->num_pages << PAGE_SHIFT,
+                                      bo->resv, &fence);
+       if (r)
+               goto error;
   
         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
         dma_fence_put(fence);
         return r;
   
   error:
-       mutex_unlock(&adev->mman.gtt_window_lock);
- 
         if (fence)
                 dma_fence_wait(fence, false);
         dma_fence_put(fence);
@@@ -483,7 -565,7 +565,7 @@@ static int amdgpu_bo_move(struct ttm_bu
         int r;
   
         /* Can't move a pinned BO */
-       abo = container_of(bo, struct amdgpu_bo, tbo);
+       abo = ttm_to_amdgpu_bo(bo);
         if (WARN_ON_ONCE(abo->pin_count > 0))
                 return -EINVAL;
   
@@@ -581,13 -663,12 +663,12 @@@ static void amdgpu_ttm_io_mem_free(stru
   static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
                                            unsigned long page_offset)
   {
-       struct drm_mm_node *mm = bo->mem.mm_node;
-       uint64_t size = mm->size;
-       uint64_t offset = page_offset;
+       struct drm_mm_node *mm;
+       unsigned long offset = (page_offset << PAGE_SHIFT);
   
-       page_offset = do_div(offset, size);
-       mm += offset;
-       return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
+       mm = amdgpu_find_mm_node(&bo->mem, &offset);
+       return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
+               (offset >> PAGE_SHIFT);
   }
   
   /*
@@@ -608,6 -689,7 +689,7 @@@ struct amdgpu_ttm_tt 
         spinlock_t              guptasklock;
         struct list_head        guptasks;
         atomic_t                mmu_invalidations;
+       uint32_t                last_set_pages;
         struct list_head        list;
   };
   
@@@ -621,6 -703,8 +703,8 @@@ int amdgpu_ttm_tt_get_user_pages(struc
         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
                 flags |= FOLL_WRITE;
   
+       down_read(&current->mm->mmap_sem);
+ 
         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
                 /* check that we only use anonymous memory
                    to prevent problems with writeback */
@@@ -628,8 -712,10 +712,10 @@@
                 struct vm_area_struct *vma;
   
                 vma = find_vma(gtt->usermm, gtt->userptr);
-               if (!vma || vma->vm_file || vma->vm_end < end)
+               if (!vma || vma->vm_file || vma->vm_end < end) {
+                       up_read(&current->mm->mmap_sem);
                         return -EPERM;
+               }
         }
   
         do {
@@@ -656,42 -742,44 +742,44 @@@
   
         } while (pinned < ttm->num_pages);
   
+       up_read(&current->mm->mmap_sem);
         return 0;
   
   release_pages:
- -      release_pages(pages, pinned, 0);
+ +      release_pages(pages, pinned);
+       up_read(&current->mm->mmap_sem);
         return r;
   }
   
- static void amdgpu_trace_dma_map(struct ttm_tt *ttm)
+ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
   {
-       struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
         unsigned i;
   
-       if (unlikely(trace_amdgpu_ttm_tt_populate_enabled())) {
-               for (i = 0; i < ttm->num_pages; i++) {
-                       trace_amdgpu_ttm_tt_populate(
-                               adev,
-                               gtt->ttm.dma_address[i],
-                               page_to_phys(ttm->pages[i]));
-               }
+       gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
+       for (i = 0; i < ttm->num_pages; ++i) {
+               if (ttm->pages[i])
+                       put_page(ttm->pages[i]);
+ 
+               ttm->pages[i] = pages ? pages[i] : NULL;
         }
   }
   
- static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm)
+ void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
   {
-       struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
         unsigned i;
   
-       if (unlikely(trace_amdgpu_ttm_tt_unpopulate_enabled())) {
-               for (i = 0; i < ttm->num_pages; i++) {
-                       trace_amdgpu_ttm_tt_unpopulate(
-                               adev,
-                               gtt->ttm.dma_address[i],
-                               page_to_phys(ttm->pages[i]));
-               }
+       for (i = 0; i < ttm->num_pages; ++i) {
+               struct page *page = ttm->pages[i];
+ 
+               if (!page)
+                       continue;
+ 
+               if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
+                       set_page_dirty(page);
+ 
+               mark_page_accessed(page);
         }
   }
   
@@@ -721,8 -809,6 +809,6 @@@ static int amdgpu_ttm_tt_pin_userptr(st
         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
                                          gtt->ttm.dma_address, ttm->num_pages);
   
-       amdgpu_trace_dma_map(ttm);
- 
         return 0;
   
   release_sg:
@@@ -734,7 -820,6 +820,6 @@@ static void amdgpu_ttm_tt_unpin_userptr
   {
         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
-       struct sg_page_iter sg_iter;
   
         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
         enum dma_data_direction direction = write ?
@@@ -747,16 -832,7 +832,7 @@@
         /* free the sg table and pages again */
         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
   
-       for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
-               struct page *page = sg_page_iter_page(&sg_iter);
-               if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
-                       set_page_dirty(page);
- 
-               mark_page_accessed(page);
-               put_page(page);
-       }
- 
-       amdgpu_trace_dma_unmap(ttm);
+       amdgpu_ttm_tt_mark_user_pages(ttm);
   
         sg_free_table(ttm->sg);
   }
@@@ -818,7 -894,6 +894,6 @@@ int amdgpu_ttm_bind(struct ttm_buffer_o
         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
         struct ttm_tt *ttm = bo->ttm;
         struct ttm_mem_reg tmp;
- 
         struct ttm_placement placement;
         struct ttm_place placements;
         int r;
@@@ -834,7 -909,8 +909,8 @@@
         placement.busy_placement = &placements;
         placements.fpfn = 0;
         placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
-       placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
+       placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
+               TTM_PL_FLAG_TT;
   
         r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
         if (unlikely(r))
@@@ -941,8 -1017,6 +1017,6 @@@ static int amdgpu_ttm_tt_populate(struc
   {
         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
-       unsigned i;
-       int r;
         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
   
         if (ttm->state != tt_unpopulated)
@@@ -962,52 -1036,26 +1036,26 @@@
                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
                                                  gtt->ttm.dma_address, ttm->num_pages);
                 ttm->state = tt_unbound;
-               r = 0;
-               goto trace_mappings;
+               return 0;
         }
   
   #ifdef CONFIG_SWIOTLB
         if (swiotlb_nr_tbl()) {
-               r = ttm_dma_populate(&gtt->ttm, adev->dev);
-               goto trace_mappings;
+               return ttm_dma_populate(&gtt->ttm, adev->dev);
         }
   #endif
   
-       r = ttm_pool_populate(ttm);
-       if (r) {
-               return r;
-       }
- 
-       for (i = 0; i < ttm->num_pages; i++) {
-               gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
-                                                      0, PAGE_SIZE,
-                                                      PCI_DMA_BIDIRECTIONAL);
-               if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
-                       while (i--) {
-                               pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
-                                              PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-                               gtt->ttm.dma_address[i] = 0;
-                       }
-                       ttm_pool_unpopulate(ttm);
-                       return -EFAULT;
-               }
-       }
- 
-       r = 0;
- trace_mappings:
-       if (likely(!r))
-               amdgpu_trace_dma_map(ttm);
-       return r;
+       return ttm_populate_and_map_pages(adev->dev, &gtt->ttm);
   }
   
   static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
   {
         struct amdgpu_device *adev;
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
-       unsigned i;
         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
   
         if (gtt && gtt->userptr) {
+               amdgpu_ttm_tt_set_user_pages(ttm, NULL);
                 kfree(ttm->sg);
                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
                 return;
@@@ -1018,8 -1066,6 +1066,6 @@@
   
         adev = amdgpu_ttm_adev(ttm->bdev);
   
-       amdgpu_trace_dma_unmap(ttm);
- 
   #ifdef CONFIG_SWIOTLB
         if (swiotlb_nr_tbl()) {
                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
@@@ -1027,14 -1073,7 +1073,7 @@@
         }
   #endif
   
-       for (i = 0; i < ttm->num_pages; i++) {
-               if (gtt->ttm.dma_address[i]) {
-                       pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
-                                      PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-               }
-       }
- 
-       ttm_pool_unpopulate(ttm);
+       ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
   }
   
   int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
@@@ -1051,6 -1090,7 +1090,7 @@@
         spin_lock_init(&gtt->guptasklock);
         INIT_LIST_HEAD(&gtt->guptasks);
         atomic_set(&gtt->mmu_invalidations, 0);
+       gtt->last_set_pages = 0;
   
         return 0;
   }
@@@ -1103,6 -1143,16 +1143,16 @@@ bool amdgpu_ttm_tt_userptr_invalidated(
         return prev_invalidated != *last_invalidated;
   }
   
+ bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
+ {
+       struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ 
+       if (gtt == NULL || !gtt->userptr)
+               return false;
+ 
+       return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
+ }
+ 
   bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
   {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@@ -1143,9 -1193,6 +1193,6 @@@ static bool amdgpu_ttm_bo_eviction_valu
         unsigned long num_pages = bo->mem.num_pages;
         struct drm_mm_node *node = bo->mem.mm_node;
   
-       if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
-               return ttm_bo_eviction_valuable(bo, place);
- 
         switch (bo->mem.mem_type) {
         case TTM_PL_TT:
                 return true;
@@@ -1160,7 -1207,7 +1207,7 @@@
                         num_pages -= node->size;
                         ++node;
                 }
-               break;
+               return false;
   
         default:
                 break;
@@@ -1173,9 -1220,9 +1220,9 @@@ static int amdgpu_ttm_access_memory(str
                                     unsigned long offset,
                                     void *buf, int len, int write)
   {
-       struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
+       struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
-       struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
+       struct drm_mm_node *nodes;
         uint32_t value = 0;
         int ret = 0;
         uint64_t pos;
@@@ -1184,10 -1231,7 +1231,7 @@@
         if (bo->mem.mem_type != TTM_PL_VRAM)
                 return -EIO;
   
-       while (offset >= (nodes->size << PAGE_SHIFT)) {
-               offset -= nodes->size << PAGE_SHIFT;
-               ++nodes;
-       }
+       nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
         pos = (nodes->start << PAGE_SHIFT) + offset;
   
         while (len && pos < adev->mc.mc_vram_size) {
@@@ -1202,14 -1246,14 +1246,14 @@@
                 }
   
                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
-               WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
-               WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
+               WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
+               WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
                 if (!write || mask != 0xffffffff)
-                       value = RREG32(mmMM_DATA);
+                       value = RREG32_NO_KIQ(mmMM_DATA);
                 if (write) {
                         value &= ~mask;
                         value |= (*(uint32_t *)buf << shift) & mask;
-                       WREG32(mmMM_DATA, value);
+                       WREG32_NO_KIQ(mmMM_DATA, value);
                 }
                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
                 if (!write) {
@@@ -1286,6 -1330,15 +1330,15 @@@ int amdgpu_ttm_init(struct amdgpu_devic
         /* Change the size here instead of the init above so only lpfn is affected */
         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
   
+       /*
+        *The reserved vram for firmware must be pinned to the specified
+        *place on the VRAM, so reserve it early.
+        */
+       r = amdgpu_fw_reserve_vram_init(adev);
+       if (r) {
+               return r;
+       }
+ 
         r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
                                     AMDGPU_GEM_DOMAIN_VRAM,
                                     &adev->stolen_vga_memory,
@@@ -1510,7 -1563,8 +1563,8 @@@ int amdgpu_copy_buffer(struct amdgpu_ri
         job->vm_needs_flush = vm_needs_flush;
         if (resv) {
                 r = amdgpu_sync_resv(adev, &job->sync, resv,
-                                    AMDGPU_FENCE_OWNER_UNDEFINED);
+                                    AMDGPU_FENCE_OWNER_UNDEFINED,
+                                    false);
                 if (r) {
                         DRM_ERROR("sync failed (%d).\n", r);
                         goto error_free;
@@@ -1557,8 -1611,8 +1611,8 @@@ int amdgpu_fill_buffer(struct amdgpu_b
                        struct dma_fence **fence)
   {
         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-       /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/
-       uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
+       uint32_t max_bytes = 8 *
+                       adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
   
         struct drm_mm_node *mm_node;
@@@ -1590,8 -1644,8 +1644,8 @@@
                 ++mm_node;
         }
   
-       /* 10 double words for each SDMA_OP_PTEPDE cmd */
-       num_dw = num_loops * 10;
+       /* num of dwords for each SDMA_OP_PTEPDE cmd */
+       num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
   
         /* for IB padding */
         num_dw += 64;
@@@ -1602,7 -1656,7 +1656,7 @@@
   
         if (resv) {
                 r = amdgpu_sync_resv(adev, &job->sync, resv,
-                                    AMDGPU_FENCE_OWNER_UNDEFINED);
+                                    AMDGPU_FENCE_OWNER_UNDEFINED, false);
                 if (r) {
                         DRM_ERROR("sync failed (%d).\n", r);
                         goto error_free;
@@@ -1697,9 -1751,9 +1751,9 @@@ static ssize_t amdgpu_ttm_vram_read(str
                         return result;
   
                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
-               WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
-               WREG32(mmMM_INDEX_HI, *pos >> 31);
-               value = RREG32(mmMM_DATA);
+               WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
+               WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
+               value = RREG32_NO_KIQ(mmMM_DATA);
                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
   
                 r = put_user(value, (uint32_t *)buf);
@@@ -1715,10 -1769,50 +1769,50 @@@
         return result;
   }
   
+ static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
+                                   size_t size, loff_t *pos)
+ {
+       struct amdgpu_device *adev = file_inode(f)->i_private;
+       ssize_t result = 0;
+       int r;
+ 
+       if (size & 0x3 || *pos & 0x3)
+               return -EINVAL;
+ 
+       if (*pos >= adev->mc.mc_vram_size)
+               return -ENXIO;
+ 
+       while (size) {
+               unsigned long flags;
+               uint32_t value;
+ 
+               if (*pos >= adev->mc.mc_vram_size)
+                       return result;
+ 
+               r = get_user(value, (uint32_t *)buf);
+               if (r)
+                       return r;
+ 
+               spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+               WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
+               WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
+               WREG32_NO_KIQ(mmMM_DATA, value);
+               spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+ 
+               result += 4;
+               buf += 4;
+               *pos += 4;
+               size -= 4;
+       }
+ 
+       return result;
+ }
+ 
   static const struct file_operations amdgpu_ttm_vram_fops = {
         .owner = THIS_MODULE,
         .read = amdgpu_ttm_vram_read,
-       .llseek = default_llseek
+       .write = amdgpu_ttm_vram_write,
+       .llseek = default_llseek,
   };
   
   #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
@@@ -1770,6 -1864,53 +1864,53 @@@ static const struct file_operations amd
   
   #endif
   
+ static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
+                                  size_t size, loff_t *pos)
+ {
+       struct amdgpu_device *adev = file_inode(f)->i_private;
+       int r;
+       uint64_t phys;
+       struct iommu_domain *dom;
+ 
+       // always return 8 bytes
+       if (size != 8)
+               return -EINVAL;
+ 
+       // only accept page addresses
+       if (*pos & 0xFFF)
+               return -EINVAL;
+ 
+       dom = iommu_get_domain_for_dev(adev->dev);
+       if (dom)
+               phys = iommu_iova_to_phys(dom, *pos);
+       else
+               phys = *pos;
+ 
+       r = copy_to_user(buf, &phys, 8);
+       if (r)
+               return -EFAULT;
+ 
+       return 8;
+ }
+ 
+ static const struct file_operations amdgpu_ttm_iova_fops = {
+       .owner = THIS_MODULE,
+       .read = amdgpu_iova_to_phys_read,
+       .llseek = default_llseek
+ };
+ 
+ static const struct {
+       char *name;
+       const struct file_operations *fops;
+       int domain;
+ } ttm_debugfs_entries[] = {
+       { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
+ #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
+       { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
+ #endif
+       { "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
+ };
+ 
   #endif
   
   static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
@@@ -1780,22 -1921,21 +1921,21 @@@
         struct drm_minor *minor = adev->ddev->primary;
         struct dentry *ent, *root = minor->debugfs_root;
   
-       ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
-                                 adev, &amdgpu_ttm_vram_fops);
-       if (IS_ERR(ent))
-               return PTR_ERR(ent);
-       i_size_write(ent->d_inode, adev->mc.mc_vram_size);
-       adev->mman.vram = ent;
- 
- #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
-       ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
-                                 adev, &amdgpu_ttm_gtt_fops);
-       if (IS_ERR(ent))
-               return PTR_ERR(ent);
-       i_size_write(ent->d_inode, adev->mc.gart_size);
-       adev->mman.gtt = ent;
+       for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
+               ent = debugfs_create_file(
+                               ttm_debugfs_entries[count].name,
+                               S_IFREG | S_IRUGO, root,
+                               adev,
+                               ttm_debugfs_entries[count].fops);
+               if (IS_ERR(ent))
+                       return PTR_ERR(ent);
+               if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
+                       i_size_write(ent->d_inode, adev->mc.mc_vram_size);
+               else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
+                       i_size_write(ent->d_inode, adev->mc.gart_size);
+               adev->mman.debugfs_entries[count] = ent;
+       }
   
- #endif
         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
   
   #ifdef CONFIG_SWIOTLB
@@@ -1805,7 -1945,6 +1945,6 @@@
   
         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
   #else
- 
         return 0;
   #endif
   }
@@@ -1813,14 -1952,9 +1952,9 @@@
   static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
   {
   #if defined(CONFIG_DEBUG_FS)
+       unsigned i;
   
-       debugfs_remove(adev->mman.vram);
-       adev->mman.vram = NULL;
- 
- #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
-       debugfs_remove(adev->mman.gtt);
-       adev->mman.gtt = NULL;
- #endif
- 
+       for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
+               debugfs_remove(adev->mman.debugfs_entries[i]);
   #endif
   }
diff --combined drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

index 62cd16a23921279f8205e6f58b463f3f9bf97152,2581543b35a79318ded40c3171b93183c0d4492d..920910ac8663a97bfc6354b0ad5f178285cc6d43
--- 1/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@@ -38,6 -38,8 +38,8 @@@
   #include "vi.h"
   
   static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
+ static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+ 
   static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
   static int uvd_v6_0_start(struct amdgpu_device *adev);
   static void uvd_v6_0_stop(struct amdgpu_device *adev);
@@@ -47,6 -49,18 +49,18 @@@ static int uvd_v6_0_set_clockgating_sta
   static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
                                  bool enable);
   
+ /**
+ * uvd_v6_0_enc_support - get encode support status
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns the current hardware encode support status
+ */
+ static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
+ {
+       return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
+ }
+ 
   /**
    * uvd_v6_0_ring_get_rptr - get read pointer
    *
@@@ -61,6 -75,22 +75,22 @@@ static uint64_t uvd_v6_0_ring_get_rptr(
         return RREG32(mmUVD_RBC_RB_RPTR);
   }
   
+ /**
+  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
+  *
+  * @ring: amdgpu_ring pointer
+  *
+  * Returns the current hardware enc read pointer
+  */
+ static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+       struct amdgpu_device *adev = ring->adev;
+ 
+       if (ring == &adev->uvd.ring_enc[0])
+               return RREG32(mmUVD_RB_RPTR);
+       else
+               return RREG32(mmUVD_RB_RPTR2);
+ }
   /**
    * uvd_v6_0_ring_get_wptr - get write pointer
    *
@@@ -75,6 -105,23 +105,23 @@@ static uint64_t uvd_v6_0_ring_get_wptr(
         return RREG32(mmUVD_RBC_RB_WPTR);
   }
   
+ /**
+  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
+  *
+  * @ring: amdgpu_ring pointer
+  *
+  * Returns the current hardware enc write pointer
+  */
+ static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+       struct amdgpu_device *adev = ring->adev;
+ 
+       if (ring == &adev->uvd.ring_enc[0])
+               return RREG32(mmUVD_RB_WPTR);
+       else
+               return RREG32(mmUVD_RB_WPTR2);
+ }
+ 
   /**
    * uvd_v6_0_ring_set_wptr - set write pointer
    *
@@@ -89,15 -136,248 +136,252 @@@ static void uvd_v6_0_ring_set_wptr(stru
         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
   }
   
+ /**
+  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
+  *
+  * @ring: amdgpu_ring pointer
+  *
+  * Commits the enc write pointer to the hardware
+  */
+ static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+       struct amdgpu_device *adev = ring->adev;
+ 
+       if (ring == &adev->uvd.ring_enc[0])
+               WREG32(mmUVD_RB_WPTR,
+                       lower_32_bits(ring->wptr));
+       else
+               WREG32(mmUVD_RB_WPTR2,
+                       lower_32_bits(ring->wptr));
+ }
+ 
+ /**
+  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
+  *
+  * @ring: the engine to test on
+  *
+  */
+ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
+ {
+       struct amdgpu_device *adev = ring->adev;
+       uint32_t rptr = amdgpu_ring_get_rptr(ring);
+       unsigned i;
+       int r;
+ 
+       r = amdgpu_ring_alloc(ring, 16);
+       if (r) {
+               DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
+                         ring->idx, r);
+               return r;
+       }
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
+       amdgpu_ring_commit(ring);
+ 
+       for (i = 0; i < adev->usec_timeout; i++) {
+               if (amdgpu_ring_get_rptr(ring) != rptr)
+                       break;
+               DRM_UDELAY(1);
+       }
+ 
+       if (i < adev->usec_timeout) {
+               DRM_INFO("ring test on %d succeeded in %d usecs\n",
+                        ring->idx, i);
+       } else {
+               DRM_ERROR("amdgpu: ring %d test failed\n",
+                         ring->idx);
+               r = -ETIMEDOUT;
+       }
+ 
+       return r;
+ }
+ 
+ /**
+  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
+  *
+  * @adev: amdgpu_device pointer
+  * @ring: ring we should submit the msg to
+  * @handle: session handle to use
+  * @fence: optional fence to return
+  *
+  * Open up a stream for HW test
+  */
+ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+                                      struct dma_fence **fence)
+ {
+       const unsigned ib_size_dw = 16;
+       struct amdgpu_job *job;
+       struct amdgpu_ib *ib;
+       struct dma_fence *f = NULL;
+       uint64_t dummy;
+       int i, r;
+ 
+       r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+       if (r)
+               return r;
+ 
+       ib = &job->ibs[0];
+       dummy = ib->gpu_addr + 1024;
+ 
+       ib->length_dw = 0;
+       ib->ptr[ib->length_dw++] = 0x00000018;
+       ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+       ib->ptr[ib->length_dw++] = handle;
+       ib->ptr[ib->length_dw++] = 0x00010000;
+       ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+       ib->ptr[ib->length_dw++] = dummy;
+ 
+       ib->ptr[ib->length_dw++] = 0x00000014;
+       ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+       ib->ptr[ib->length_dw++] = 0x0000001c;
+       ib->ptr[ib->length_dw++] = 0x00000001;
+       ib->ptr[ib->length_dw++] = 0x00000000;
+ 
+       ib->ptr[ib->length_dw++] = 0x00000008;
+       ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
+ 
+       for (i = ib->length_dw; i < ib_size_dw; ++i)
+               ib->ptr[i] = 0x0;
+ 
+       r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+       job->fence = dma_fence_get(f);
+       if (r)
+               goto err;
+ 
+       amdgpu_job_free(job);
+       if (fence)
+               *fence = dma_fence_get(f);
+       dma_fence_put(f);
+       return 0;
+ 
+ err:
+       amdgpu_job_free(job);
+       return r;
+ }
+ 
+ /**
+  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
+  *
+  * @adev: amdgpu_device pointer
+  * @ring: ring we should submit the msg to
+  * @handle: session handle to use
+  * @fence: optional fence to return
+  *
+  * Close up a stream for HW test or if userspace failed to do so
+  */
+ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+                                       uint32_t handle,
+                                       bool direct, struct dma_fence **fence)
+ {
+       const unsigned ib_size_dw = 16;
+       struct amdgpu_job *job;
+       struct amdgpu_ib *ib;
+       struct dma_fence *f = NULL;
+       uint64_t dummy;
+       int i, r;
+ 
+       r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+       if (r)
+               return r;
+ 
+       ib = &job->ibs[0];
+       dummy = ib->gpu_addr + 1024;
+ 
+       ib->length_dw = 0;
+       ib->ptr[ib->length_dw++] = 0x00000018;
+       ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+       ib->ptr[ib->length_dw++] = handle;
+       ib->ptr[ib->length_dw++] = 0x00010000;
+       ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+       ib->ptr[ib->length_dw++] = dummy;
+ 
+       ib->ptr[ib->length_dw++] = 0x00000014;
+       ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+       ib->ptr[ib->length_dw++] = 0x0000001c;
+       ib->ptr[ib->length_dw++] = 0x00000001;
+       ib->ptr[ib->length_dw++] = 0x00000000;
+ 
+       ib->ptr[ib->length_dw++] = 0x00000008;
+       ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
+ 
+       for (i = ib->length_dw; i < ib_size_dw; ++i)
+               ib->ptr[i] = 0x0;
+ 
+       if (direct) {
+               r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+               job->fence = dma_fence_get(f);
+               if (r)
+                       goto err;
+ 
+               amdgpu_job_free(job);
+       } else {
+               r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
+                                     AMDGPU_FENCE_OWNER_UNDEFINED, &f);
+               if (r)
+                       goto err;
+       }
+ 
+       if (fence)
+               *fence = dma_fence_get(f);
+       dma_fence_put(f);
+       return 0;
+ 
+ err:
+       amdgpu_job_free(job);
+       return r;
+ }
+ 
+ /**
+  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
+  *
+  * @ring: the engine to test on
+  *
+  */
+ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+       struct dma_fence *fence = NULL;
+       long r;
+ 
+       r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
+       if (r) {
+               DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
+               goto error;
+       }
+ 
+       r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
+       if (r) {
+               DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
+               goto error;
+       }
+ 
+       r = dma_fence_wait_timeout(fence, false, timeout);
+       if (r == 0) {
+               DRM_ERROR("amdgpu: IB test timed out.\n");
+               r = -ETIMEDOUT;
+       } else if (r < 0) {
+               DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+       } else {
+               DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
+               r = 0;
+       }
+ error:
+       dma_fence_put(fence);
+       return r;
+ }
   static int uvd_v6_0_early_init(void *handle)
   {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   
+ +      if (!(adev->flags & AMD_IS_APU) &&
+ +          (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
+ +              return -ENOENT;
+ +
         uvd_v6_0_set_ring_funcs(adev);
+ 
+       if (uvd_v6_0_enc_support(adev)) {
+               adev->uvd.num_enc_rings = 2;
+               uvd_v6_0_set_enc_ring_funcs(adev);
+       }
+ 
         uvd_v6_0_set_irq_funcs(adev);
   
         return 0;
@@@ -106,7 -386,7 +390,7 @@@
   static int uvd_v6_0_sw_init(void *handle)
   {
         struct amdgpu_ring *ring;
-       int r;
+       int i, r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   
         /* UVD TRAP */
@@@ -114,10 -394,31 +398,31 @@@
         if (r)
                 return r;
   
+       /* UVD ENC TRAP */
+       if (uvd_v6_0_enc_support(adev)) {
+               for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
+                       if (r)
+                               return r;
+               }
+       }
+ 
         r = amdgpu_uvd_sw_init(adev);
         if (r)
                 return r;
   
+       if (uvd_v6_0_enc_support(adev)) {
+               struct amd_sched_rq *rq;
+               ring = &adev->uvd.ring_enc[0];
+               rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
+               r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
+                                         rq, amdgpu_sched_jobs);
+               if (r) {
+                       DRM_ERROR("Failed setting up UVD ENC run queue.\n");
+                       return r;
+               }
+       }
+ 
         r = amdgpu_uvd_resume(adev);
         if (r)
                 return r;
@@@ -125,19 -426,38 +430,38 @@@
         ring = &adev->uvd.ring;
         sprintf(ring->name, "uvd");
         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+       if (r)
+               return r;
+ 
+       if (uvd_v6_0_enc_support(adev)) {
+               for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                       ring = &adev->uvd.ring_enc[i];
+                       sprintf(ring->name, "uvd_enc%d", i);
+                       r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+                       if (r)
+                               return r;
+               }
+       }
   
         return r;
   }
   
   static int uvd_v6_0_sw_fini(void *handle)
   {
-       int r;
+       int i, r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   
         r = amdgpu_uvd_suspend(adev);
         if (r)
                 return r;
   
+       if (uvd_v6_0_enc_support(adev)) {
+               amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
+ 
+               for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+                       amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+       }
+ 
         return amdgpu_uvd_sw_fini(adev);
   }
   
@@@ -153,7 -473,7 +477,7 @@@ static int uvd_v6_0_hw_init(void *handl
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         struct amdgpu_ring *ring = &adev->uvd.ring;
         uint32_t tmp;
-       int r;
+       int i, r;
   
         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
@@@ -193,9 -513,25 +517,25 @@@
   
         amdgpu_ring_commit(ring);
   
+       if (uvd_v6_0_enc_support(adev)) {
+               for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                       ring = &adev->uvd.ring_enc[i];
+                       ring->ready = true;
+                       r = amdgpu_ring_test_ring(ring);
+                       if (r) {
+                               ring->ready = false;
+                               goto done;
+                       }
+               }
+       }
+ 
   done:
-       if (!r)
-               DRM_INFO("UVD initialized successfully.\n");
+       if (!r) {
+               if (uvd_v6_0_enc_support(adev))
+                       DRM_INFO("UVD and UVD ENC initialized successfully.\n");
+               else
+                       DRM_INFO("UVD initialized successfully.\n");
+       }
   
         return r;
   }
@@@ -512,6 -848,22 +852,22 @@@ static int uvd_v6_0_start(struct amdgpu
   
         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
   
+       if (uvd_v6_0_enc_support(adev)) {
+               ring = &adev->uvd.ring_enc[0];
+               WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+               WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+               WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
+               WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+               WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
+ 
+               ring = &adev->uvd.ring_enc[1];
+               WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+               WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+               WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
+               WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+               WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
+       }
+ 
         return 0;
   }
   
@@@ -574,6 -926,26 +930,26 @@@ static void uvd_v6_0_ring_emit_fence(st
         amdgpu_ring_write(ring, 2);
   }
   
+ /**
+  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
+  *
+  * @ring: amdgpu_ring pointer
+  * @fence: fence to emit
+  *
+  * Write enc a fence and a trap command to the ring.
+  */
+ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+                       u64 seq, unsigned flags)
+ {
+       WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+ 
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
+       amdgpu_ring_write(ring, addr);
+       amdgpu_ring_write(ring, upper_32_bits(addr));
+       amdgpu_ring_write(ring, seq);
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
+ }
+ 
   /**
    * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
    *
@@@ -665,6 -1037,24 +1041,24 @@@ static void uvd_v6_0_ring_emit_ib(struc
         amdgpu_ring_write(ring, ib->length_dw);
   }
   
+ /**
+  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
+  *
+  * @ring: amdgpu_ring pointer
+  * @ib: indirect buffer to execute
+  *
+  * Write enc ring commands to execute the indirect buffer
+  */
+ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
+               struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+ {
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
+       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+       amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+       amdgpu_ring_write(ring, ib->length_dw);
+ }
+ 
   static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                          unsigned vm_id, uint64_t pd_addr)
   {
@@@ -716,6 -1106,33 +1110,33 @@@ static void uvd_v6_0_ring_emit_pipeline
         amdgpu_ring_write(ring, 0xE);
   }
   
+ static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ {
+       uint32_t seq = ring->fence_drv.sync_seq;
+       uint64_t addr = ring->fence_drv.gpu_addr;
+ 
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
+       amdgpu_ring_write(ring, lower_32_bits(addr));
+       amdgpu_ring_write(ring, upper_32_bits(addr));
+       amdgpu_ring_write(ring, seq);
+ }
+ 
+ static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
+ {
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
+ }
+ 
+ static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+         unsigned int vm_id, uint64_t pd_addr)
+ {
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
+       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, pd_addr >> 12);
+ 
+       amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
+       amdgpu_ring_write(ring, vm_id);
+ }
+ 
   static bool uvd_v6_0_is_idle(void *handle)
   {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@@ -823,8 -1240,31 +1244,31 @@@ static int uvd_v6_0_process_interrupt(s
                                       struct amdgpu_irq_src *source,
                                       struct amdgpu_iv_entry *entry)
   {
+       bool int_handled = true;
         DRM_DEBUG("IH: UVD TRAP\n");
-       amdgpu_fence_process(&adev->uvd.ring);
+ 
+       switch (entry->src_id) {
+       case 124:
+               amdgpu_fence_process(&adev->uvd.ring);
+               break;
+       case 119:
+               if (likely(uvd_v6_0_enc_support(adev)))
+                       amdgpu_fence_process(&adev->uvd.ring_enc[0]);
+               else
+                       int_handled = false;
+               break;
+       case 120:
+               if (likely(uvd_v6_0_enc_support(adev)))
+                       amdgpu_fence_process(&adev->uvd.ring_enc[1]);
+               else
+                       int_handled = false;
+               break;
+       }
+ 
+       if (false == int_handled)
+                       DRM_ERROR("Unhandled interrupt: %d %d\n",
+                         entry->src_id, entry->src_data[0]);
+ 
         return 0;
   }
   
@@@ -1151,6 -1591,33 +1595,33 @@@ static const struct amdgpu_ring_funcs u
         .end_use = amdgpu_uvd_ring_end_use,
   };
   
+ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
+       .type = AMDGPU_RING_TYPE_UVD_ENC,
+       .align_mask = 0x3f,
+       .nop = HEVC_ENC_CMD_NO_OP,
+       .support_64bit_ptrs = false,
+       .get_rptr = uvd_v6_0_enc_ring_get_rptr,
+       .get_wptr = uvd_v6_0_enc_ring_get_wptr,
+       .set_wptr = uvd_v6_0_enc_ring_set_wptr,
+       .emit_frame_size =
+               4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
+               6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
+               5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
+               1, /* uvd_v6_0_enc_ring_insert_end */
+       .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
+       .emit_ib = uvd_v6_0_enc_ring_emit_ib,
+       .emit_fence = uvd_v6_0_enc_ring_emit_fence,
+       .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
+       .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
+       .test_ring = uvd_v6_0_enc_ring_test_ring,
+       .test_ib = uvd_v6_0_enc_ring_test_ib,
+       .insert_nop = amdgpu_ring_insert_nop,
+       .insert_end = uvd_v6_0_enc_ring_insert_end,
+       .pad_ib = amdgpu_ring_generic_pad_ib,
+       .begin_use = amdgpu_uvd_ring_begin_use,
+       .end_use = amdgpu_uvd_ring_end_use,
+ };
+ 
   static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
   {
         if (adev->asic_type >= CHIP_POLARIS10) {
@@@ -1162,6 -1629,16 +1633,16 @@@
         }
   }
   
+ static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ {
+       int i;
+ 
+       for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+               adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
+ 
+       DRM_INFO("UVD ENC is enabled in VM mode\n");
+ }
+ 
   static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
         .set = uvd_v6_0_set_interrupt_state,
         .process = uvd_v6_0_process_interrupt,
@@@ -1169,7 -1646,11 +1650,11 @@@
   
   static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
   {
-       adev->uvd.irq.num_types = 1;
+       if (uvd_v6_0_enc_support(adev))
+               adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
+       else
+               adev->uvd.irq.num_types = 1;
+ 
         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
   }
   
diff --combined drivers/gpu/drm/amd/powerplay/Makefile

index 72d5f50508b60f431f1f1248e67b631813839859,68b417ac94ddb4db2890270446bdf87cf4a67165..8c55c6e254d99eb008231587bb21beb29c09a450
--- 1/drivers/gpu/drm/amd/powerplay/Makefile
--- 2/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@@ -1,16 -1,14 +1,15 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   
   subdir-ccflags-y += \
                 -I$(FULL_AMD_PATH)/powerplay/inc/  \
                 -I$(FULL_AMD_PATH)/include/asic_reg  \
                 -I$(FULL_AMD_PATH)/include  \
                 -I$(FULL_AMD_PATH)/powerplay/smumgr\
-               -I$(FULL_AMD_PATH)/powerplay/hwmgr \
-               -I$(FULL_AMD_PATH)/powerplay/eventmgr
+               -I$(FULL_AMD_PATH)/powerplay/hwmgr
   
   AMD_PP_PATH = ../powerplay
   
- PP_LIBS = smumgr hwmgr eventmgr
+ PP_LIBS = smumgr hwmgr
   
   AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(PP_LIBS)))
   
diff --combined drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

index d13fdadbbf9e8fbb19fa0b1807b10fb005cd8e0a,dc4bbcfe12439ae00ad92eb73fd9258ca6b89eea..824fb6fe54ae97dc2a1768f49141ee6ff0ce3a49
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@@ -1,16 -1,16 +1,17 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   #
   # Makefile for the 'hw manager' sub-component of powerplay.
   # It provides the hardware management services for the driver.
   
- HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
+ HARDWARE_MGR = hwmgr.o processpptables.o \
                 hardwaremanager.o pp_acpi.o cz_hwmgr.o \
                 cz_clockpowergating.o pppcielanes.o\
                 process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
                 smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
                 smu7_clockpowergating.o \
                 vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
-               vega10_thermal.o pp_overdriver.o rv_hwmgr.o
+               vega10_thermal.o rv_hwmgr.o pp_psm.o\
+               pp_overdriver.o
   
   AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
   
diff --combined drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c

index e0766c5e3d74776d28e4b9dbde76a406aaf9a12f,8ba75d43fba6c2767d15834eb385a4a0f8d8506d..67fae834bc6788680eddd50b8f55a737f4b013ab
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
@@@ -1,1264 -1,1252 +1,1253 @@@
+ +// SPDX-License-Identifier: GPL-2.0
   #include "pp_overdriver.h"
   #include <linux/errno.h>
   
- struct phm_fuses_default vega10_fuses_default[] = {
-       {"0000001000010011111010101001010011011110000011100100100101100100",0x00003C96,0xFFFFE226,0x00000656,0x00002203,0xFFFFF201,0x000003FF,0x00002203,0xFFFFF201,0x000003FF},
-       {"0000001000010011111010101001010011011110000010100001100010000100",0x00003CC5,0xFFFFE23A,0x0000064E,0x00002258,0xFFFFF1F7,0x000003FC,0x00002258,0xFFFFF1F7,0x000003FC},
-       {"0000001000010011111010101001010011011110000011100011000110100100",0x00003CAF,0xFFFFE36E,0x00000602,0x00001E98,0xFFFFF569,0x00000357,0x00001E98,0xFFFFF569,0x00000357},
-       {"0000001000010011111010101001010011011110001011000001000101000100",0x0000391A,0xFFFFE548,0x000005C9,0x00001B98,0xFFFFF707,0x00000324,0x00001B98,0xFFFFF707,0x00000324},
-       {"0000001000010011111010101001010011011110001011000001100011000100",0x00003821,0xFFFFE674,0x00000597,0x00002196,0xFFFFF361,0x000003C0,0x00002196,0xFFFFF361,0x000003C0},
-       {"0000001000010011111010101001010011011110001001100011100010000100",0x000044A2,0xFFFFDCB7,0x00000738,0x0000325C,0xFFFFE6A7,0x000005E6,0x0000325C,0xFFFFE6A7,0x000005E6},
-       {"0000001000010011111010101001010011011110000010000010100100100100",0x00004057,0xFFFFE1CF,0x0000063C,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD},
-       {"0000001000010011111010101001010011011110001010000100100100100100",0x00003FD0,0xFFFFDF0F,0x000006E5,0x0000267C,0xFFFFEE2D,0x000004AB,0x0000267C,0xFFFFEE2D,0x000004AB},
-       {"0000001000010011111010101001010011011110001010000000100100000100",0x00003F13,0xFFFFE010,0x000006AD,0x000020E7,0xFFFFF266,0x000003EC,0x000020E7,0xFFFFF266,0x000003EC},
-       {"0000001000010011111010101001010011011110000010000010000001000100",0x00004088,0xFFFFDFAB,0x000006B6,0x0000252B,0xFFFFEFDB,0x00000458,0x0000252B,0xFFFFEFDB,0x00000458},
-       {"0000001000010011111010101001010011011110001010000011100010000100",0x00003EF6,0xFFFFE017,0x000006AA,0x00001F67,0xFFFFF369,0x000003BE,0x00001F67,0xFFFFF369,0x000003BE},
-       {"0000001000010011111010101001010011011110001011000010000110000100",0x00003CDD,0xFFFFE2A7,0x0000063C,0x000026C6,0xFFFFEF38,0x00000478,0x000026C6,0xFFFFEF38,0x00000478},
-       {"0000001000010011111010101001010011011110000100000101000100100100",0x00003FA8,0xFFFFDF02,0x000006F0,0x000027FE,0xFFFFECF6,0x000004EA,0x000027FE,0xFFFFECF6,0x000004EA},
-       {"0000001000010011111010101001010011011110001001100011100011000100",0x00004670,0xFFFFDC40,0x00000742,0x00003A7A,0xFFFFE1A7,0x000006B6,0x00003A7A,0xFFFFE1A7,0x000006B6},
-       {"0000001000010011111010101001010011011110001011000011000000100100",0x00003CDC,0xFFFFE18C,0x00000683,0x00002A69,0xFFFFEBE7,0x00000515,0x00002A69,0xFFFFEBE7,0x00000515},
-       {"0000001000010011111010101001010011011110000011100011100011000100",0x00003CEC,0xFFFFE38E,0x00000601,0x00002752,0xFFFFEFA7,0x00000453,0x00002752,0xFFFFEFA7,0x00000453},
-       {"0000001000010011111010101001010011011110001011000001000100100100",0x000037D0,0xFFFFE634,0x000005A7,0x00001CD2,0xFFFFF644,0x00000348,0x00001CD2,0xFFFFF644,0x00000348},
-       {"0000001000010011111010101001010011011110001010000011100101100100",0x00003DF5,0xFFFFE0A5,0x00000698,0x00001FD5,0xFFFFF30E,0x000003D1,0x00001FD5,0xFFFFF30E,0x000003D1},
-       {"0000001000010011111010101001010011011110000010000010100011000100",0x00004201,0xFFFFE03E,0x00000688,0x00003206,0xFFFFE852,0x0000058A,0x00003206,0xFFFFE852,0x0000058A},
-       {"0000001000010011111010101001010011011110001011000001100001100100",0x00003BED,0xFFFFE2F5,0x00000638,0x0000270D,0xFFFFEED0,0x0000048E,0x0000270D,0xFFFFEED0,0x0000048E},
-       {"0000001000010011111010101001010011011110000010100001100100000100",0x00003E82,0xFFFFE1BE,0x00000654,0x000025FB,0xFFFFEFFA,0x00000448,0x000025FB,0xFFFFEFFA,0x00000448},
-       {"0000001000010011111010101001010011011110001011000100000011000100",0x00003962,0xFFFFE4B9,0x000005EF,0x00002385,0xFFFFF156,0x00000423,0x00002385,0xFFFFF156,0x00000423},
-       {"0000001000010011111010101001010011011110001011000000100101000100",0x00003D88,0xFFFFE21A,0x00000655,0x0000295A,0xFFFFED68,0x000004C4,0x0000295A,0xFFFFED68,0x000004C4},
-       {"0000001000010011111010101001010011011110001011000001000100000100",0x00003AA4,0xFFFFE4A3,0x000005E0,0x000022EF,0xFFFFF250,0x000003EB,0x000022EF,0xFFFFF250,0x000003EB},
-       {"0000001000010011111010101001010011011110000011100010100110100100",0x00003D97,0xFFFFE30D,0x0000060D,0x0000205D,0xFFFFF45D,0x00000380,0x0000205D,0xFFFFF45D,0x00000380},
-       {"0000001000010011111010101001010011011110001011000100000010100100",0x000039B6,0xFFFFE446,0x00000605,0x00002325,0xFFFFF16C,0x0000041F,0x00002325,0xFFFFF16C,0x0000041F},
-       {"0000001000010011111010101001010011011110001001100011100100000100",0x0000457E,0xFFFFDCF6,0x00000722,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E},
-       {"0000001000010011111010101001010011011110000010100001100100100100",0x00003FB8,0xFFFFE101,0x00000670,0x00002787,0xFFFFEEF5,0x00000471,0x00002787,0xFFFFEEF5,0x00000471},
-       {"0000001000010011111010101001010011011110000011100011100010100100",0x00003BB2,0xFFFFE430,0x000005EA,0x000024A5,0xFFFFF162,0x00000409,0x000024A5,0xFFFFF162,0x00000409},
-       {"0000001000010011111010101001010011011110000010000010000101000100",0x00003EC5,0xFFFFE1BD,0x0000064F,0x000022F0,0xFFFFF227,0x000003E8,0x000022F0,0xFFFFF227,0x000003E8},
-       {"0000001000010011111010101001010011011110001011000011000101100100",0x000038A7,0xFFFFE59F,0x000005C1,0x000021CC,0xFFFFF2DF,0x000003D9,0x000021CC,0xFFFFF2DF,0x000003D9},
-       {"0000001000010011111010101001010011011110001100100100000110000100",0x00002995,0xFFFFEF7A,0x0000044C,0x00001552,0xFFFFFB5D,0x00000292,0x00001552,0xFFFFFB5D,0x00000292},
-       {"0000001000010011111010101001010011011110001011000100000001100100",0x00003B26,0xFFFFE2D3,0x00000649,0x000023B4,0xFFFFF09B,0x00000449,0x000023B4,0xFFFFF09B,0x00000449},
-       {"0000001000010011111010101001010011011110000010000001000100100100",0x000040D2,0xFFFFE00A,0x00000696,0x000022DA,0xFFFFF1E9,0x000003F2,0x000022DA,0xFFFFF1E9,0x000003F2},
-       {"0000001000010011111010101001010011011110001011000011100100100100",0x00003C98,0xFFFFE365,0x00000618,0x00002D5D,0xFFFFEB3A,0x0000051D,0x00002D5D,0xFFFFEB3A,0x0000051D},
-       {"0000001000010011111010101001010011011110001011000001000010100100",0x00003BBD,0xFFFFE37E,0x00000617,0x0000252E,0xFFFFF06E,0x00000441,0x0000252E,0xFFFFF06E,0x00000441},
-       {"0000001000010011111010101001010011011110001001100010100100100100",0x00004363,0xFFFFDF7A,0x000006A0,0x000031F5,0xFFFFE880,0x0000057B,0x000031F5,0xFFFFE880,0x0000057B},
-       {"0000001000010011111010101001010011011110000011100011100001000100",0x00003CFC,0xFFFFE2AF,0x0000062E,0x0000212A,0xFFFFF335,0x000003BF,0x0000212A,0xFFFFF335,0x000003BF},
-       {"0000001000010011111010101001010011011110000111000100100100100100",0x0000252D,0xFFFFF31B,0x000003C3,0x00001A1A,0xFFFFF882,0x00000325,0x00001A1A,0xFFFFF882,0x00000325},
-       {"0000001000010011111010101001010011011110000010100010100110100100",0x00003FE2,0xFFFFDFEF,0x000006AC,0x000025A2,0xFFFFEF84,0x00000462,0x000025A2,0xFFFFEF84,0x00000462},
-       {"0000001000010011111010101001010011011110000010000010000011100100",0x000040A5,0xFFFFE13B,0x0000065B,0x00002C13,0xFFFFEC75,0x000004D7,0x00002C13,0xFFFFEC75,0x000004D7},
-       {"0000001000010011111010101001010011011110000011100100100010100100",0x00003E42,0xFFFFE1B3,0x00000657,0x0000221D,0xFFFFF273,0x000003DE,0x0000221D,0xFFFFF273,0x000003DE},
-       {"0000001000010011111010101001010011011110000010100010000011100100",0x00003E7F,0xFFFFE255,0x00000638,0x00002D30,0xFFFFEB8A,0x00000503,0x00002D30,0xFFFFEB8A,0x00000503},
-       {"0000001000010011111010101001010011011110001011000010100111000100",0x00003E56,0xFFFFE16D,0x00000670,0x000028DC,0xFFFFEDA0,0x000004BA,0x000028DC,0xFFFFEDA0,0x000004BA},
-       {"0000001000010011111010101001010011011110001001100011000010100100",0x000044AD,0xFFFFDE24,0x000006DD,0x000031AD,0xFFFFE850,0x00000585,0x000031AD,0xFFFFE850,0x00000585},
-       {"0000001000010011111010101001010011011110001011000010000011100100",0x00003AF3,0xFFFFE5B0,0x000005A6,0x00002CF6,0xFFFFEC75,0x000004DD,0x00002CF6,0xFFFFEC75,0x000004DD},
-       {"0000001000010011111010101001010011011110000010100010000010000100",0x00003E66,0xFFFFE19E,0x0000065B,0x00002332,0xFFFFF1B9,0x000003FD,0x00002332,0xFFFFF1B9,0x000003FD},
-       {"0000001000010011111010101001010011011110000010000010100010000100",0x00003FB4,0xFFFFE0A5,0x00000686,0x0000253E,0xFFFFF02E,0x00000444,0x0000253E,0xFFFFF02E,0x00000444},
-       {"0000001000010011111010101001010011011110001010000001100010100100",0x00003E28,0xFFFFE14D,0x0000066E,0x00001FE2,0xFFFFF39A,0x000003B1,0x00001FE2,0xFFFFF39A,0x000003B1},
-       {"0000001000010011111010101001010011011110001011000000100100000100",0x000039E6,0xFFFFE44B,0x000005FE,0x0000210C,0xFFFFF2F4,0x000003DA,0x0000210C,0xFFFFF2F4,0x000003DA},
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-       {"0000001000010011111100001111111010011001000111000011000101100100",0x00003444,0xFFFFE98A,0x00000517,0x000020FD,0xFFFFF43F,0x0000039D,0x000020FD,0xFFFFF43F,0x0000039D},
-       {"0000001000010011111100001111111010011001001010000000100011100100",0x00002987,0xFFFFEFA1,0x0000044B,0x00001B06,0xFFFFF788,0x0000033C,0x00001B06,0xFFFFF788,0x0000033C},
-       {"0000001000010011111100001111111010011001001011000010100011100100",0x0000311D,0xFFFFED20,0x00000474,0x000025DA,0xFFFFF223,0x000003F0,0x000025DA,0xFFFFF223,0x000003F0},
-       {"0000001000010011111100001111111010011001001011000001000100100100",0x000032A2,0xFFFFEA0A,0x0000050D,0x00001D48,0xFFFFF659,0x0000034A,0x00001D48,0xFFFFF659,0x0000034A},
-       {"0000001000010011111100001111111010011001001000100000100011100100",0x00003110,0xFFFFE9EA,0x00000529,0x00001786,0xFFFFF958,0x000002DB,0x00001786,0xFFFFF958,0x000002DB},
-       {"0000001000010011111100001111111010011001001010000010000110100100",0x000027F2,0xFFFFF174,0x000003F7,0x00001C7A,0xFFFFF72A,0x00000348,0x00001C7A,0xFFFFF72A,0x00000348},
-       {"0000001000010011111100001111111010011001000111000001000011100100",0x000031DB,0xFFFFEA7D,0x000004FB,0x000019C4,0xFFFFF8B1,0x000002E6,0x000019C4,0xFFFFF8B1,0x000002E6},
-       {"0000001000010011111100001111111010011001001011000001000100000100",0x00003158,0xFFFFEAAC,0x000004FA,0x00001BC1,0xFFFFF737,0x0000032B,0x00001BC1,0xFFFFF737,0x0000032B},
-       {"0000001000010011111100001111111010011001001100000001000011000100",0x00002F36,0xFFFFEBF9,0x000004CA,0x00001A2A,0xFFFFF83F,0x00000303,0x00001A2A,0xFFFFF83F,0x00000303},
-       {"0000001000010011111100001111111010011001001100100011100010100100",0x000032B4,0xFFFFEA72,0x000004FA,0x000021FF,0xFFFFF378,0x000003C5,0x000021FF,0xFFFFF378,0x000003C5},
-       {"0000001000010011111100001111111010011001001100000011000101100100",0x00003262,0xFFFFEAFA,0x000004DF,0x00002441,0xFFFFF237,0x000003F6,0x00002441,0xFFFFF237,0x000003F6},
-       {"0000001000010011111100001111111010011001001100000011100100100100",0x0000336A,0xFFFFEAFB,0x000004D1,0x00002746,0xFFFFF0B8,0x0000042B,0x00002746,0xFFFFF0B8,0x0000042B},
-       {"0000001000010011111100001111111010011001000110100100000010000100",0x000032E5,0xFFFFE923,0x00000541,0x00001DF0,0xFFFFF552,0x00000380,0x00001DF0,0xFFFFF552,0x00000380},
-       {"0000001000010011111100001111111010011001001100000100000001100100",0x000035D1,0xFFFFE80B,0x0000055F,0x00002780,0xFFFFEF74,0x0000046F,0x00002780,0xFFFFEF74,0x0000046F},
-       {"0000001000010011111100001111111010011001001100000010100010100100",0x000033EC,0xFFFFEA48,0x000004F4,0x0000269F,0xFFFFF0D8,0x0000042A,0x0000269F,0xFFFFF0D8,0x0000042A},
-       {"0000001000010011111100001111111010011001001100100011100010000100",0x000030C4,0xFFFFEB39,0x000004E2,0x00001B44,0xFFFFF7AA,0x00000318,0x00001B44,0xFFFFF7AA,0x00000318},
-       {"0000001000010011111100001111111010011001001010000001000101000100",0x00002926,0xFFFFF0AF,0x0000040E,0x0000194E,0xFFFFF959,0x000002E2,0x0000194E,0xFFFFF959,0x000002E2},
-       {"0000001000010011111100001111111010011001001011000001000011000100",0x00003141,0xFFFFEAAF,0x000004F6,0x00001864,0xFFFFF97C,0x000002C6,0x00001864,0xFFFFF97C,0x000002C6},
-       {"0000001000010011111100001111111010011001001100000001000001100100",0x000030B2,0xFFFFEB7C,0x000004DB,0x000022CE,0xFFFFF2B5,0x000003F0,0x000022CE,0xFFFFF2B5,0x000003F0},
-       {"0000001000010011111100001111111010011001001100000001100101000100",0x0000318C,0xFFFFEAC7,0x000004F6,0x00002113,0xFFFFF3CA,0x000003BD,0x00002113,0xFFFFF3CA,0x000003BD},
-       {"0000001000010011111100001111111010011001001011100001000100000100",0x00002FD2,0xFFFFEB8F,0x000004D9,0x00001996,0xFFFFF89F,0x000002F1,0x00001996,0xFFFFF89F,0x000002F1},
-       {"0000001000010011111100001111111010011001000110100010100010100100",0x0000310D,0xFFFFEB25,0x000004E7,0x00001F67,0xFFFFF4EF,0x0000038E,0x00001F67,0xFFFFF4EF,0x0000038E},
-       {"0000001000010011111100001111111010011001001010100100100101100100",0x00002BBC,0xFFFFEE68,0x00000477,0x00002050,0xFFFFF41D,0x000003C8,0x00002050,0xFFFFF41D,0x000003C8},
-       {"0000001000010011111100001111111010011001001100000010000100000100",0x00003096,0xFFFFECED,0x00000486,0x000024C9,0xFFFFF278,0x000003E7,0x000024C9,0xFFFFF278,0x000003E7},
-       {"0000001000010011111100001111111010011001001011000001000010100100",0x00003401,0xFFFFE8F1,0x0000053C,0x00001E75,0xFFFFF55C,0x00000376,0x00001E75,0xFFFFF55C,0x00000376},
-       {"0000001000010011111100001111111010011001001100000010100001000100",0x0000319E,0xFFFFEAB1,0x000004F8,0x00001EA3,0xFFFFF567,0x00000378,0x00001EA3,0xFFFFF567,0x00000378},
-       {"0000001000010011111100001111111010011001001100100010100101100100",0x000030FD,0xFFFFEB4C,0x000004DB,0x00001CA6,0xFFFFF6E8,0x00000335,0x00001CA6,0xFFFFF6E8,0x00000335},
-       {"0000001000010011111100001111111010011001001011100100000010100100",0x000030D6,0xFFFFEB1A,0x000004E4,0x00001A0D,0xFFFFF87D,0x000002EF,0x00001A0D,0xFFFFF87D,0x000002EF},
-       {"0000001000010011111100001111111010011001001011000010000100100100",0x0000324B,0xFFFFEB17,0x000004D9,0x00002225,0xFFFFF3A8,0x000003BA,0x00002225,0xFFFFF3A8,0x000003BA},
-       {"0000001000010011111100001111111010011001001010000100000010000100",0x00002A00,0xFFFFF02E,0x00000424,0x00001E21,0xFFFFF61D,0x0000036C,0x00001E21,0xFFFFF61D,0x0000036C},
-       {"0000001000010011111100001111111010011001001010100100100010100100",0x000029CF,0xFFFFEF53,0x00000457,0x00001B11,0xFFFFF772,0x0000033D,0x00001B11,0xFFFFF772,0x0000033D},
-       {"0000001000010011111100001111111010011001000110100011000010100100",0x000032A1,0xFFFFEA63,0x000004FB,0x00001F83,0xFFFFF516,0x0000037E,0x00001F83,0xFFFFF516,0x0000037E},
-       {"0000001000010011111100001111111010011001001011100010000011000100",0x0000305C,0xFFFFEC14,0x000004B5,0x00001D0B,0xFFFFF6ED,0x00000332,0x00001D0B,0xFFFFF6ED,0x00000332},
-       {"0000001000010011111100001111111010011001001011000001000001100100",0x00003467,0xFFFFE8D5,0x00000543,0x0000243F,0xFFFFF190,0x00000418,0x0000243F,0xFFFFF190,0x00000418},
-       {"0000001000010011111100001111111010011001001010100010000001100100",0x00002796,0xFFFFF133,0x00000409,0x00001903,0xFFFFF91C,0x000002FC,0x00001903,0xFFFFF91C,0x000002FC},
-       {"0000001000010011111100001111111010011001001100000010000101100100",0x000031F6,0xFFFFEAB7,0x000004F5,0x000022B9,0xFFFFF2D0,0x000003E6,0x000022B9,0xFFFFF2D0,0x000003E6},
-       {"0000001000010011111100001111111010011001001011100101000100000100",0x00003196,0xFFFFEA76,0x00000503,0x00001CC5,0xFFFFF67D,0x0000034A,0x00001CC5,0xFFFFF67D,0x0000034A},
-       {"0000001000010011111100001111111010011001001100100001000101000100",0x00002F9E,0xFFFFEAD9,0x00000505,0x000017C1,0xFFFFF93D,0x000002DF,0x000017C1,0xFFFFF93D,0x000002DF},
-       {"0000001000010011111100001111111010011001001011100010000100100100",0x00002FBC,0xFFFFEC75,0x000004A8,0x00001D6D,0xFFFFF6AC,0x0000033D,0x00001D6D,0xFFFFF6AC,0x0000033D},
-       {"0000001000010011111100001111111010011001001011000011100010100100",0x00003541,0xFFFFE921,0x00000524,0x00002662,0xFFFFF0CB,0x0000042B,0x00002662,0xFFFFF0CB,0x0000042B},
-       {"0000001000010011111100001111111010011001001010100010000110100100",0x00002953,0xFFFFEF76,0x00000459,0x00001C05,0xFFFFF6A0,0x00000368,0x00001C05,0xFFFFF6A0,0x00000368},
-       {"0000001000010011111100001111111010011001001011000100100100100100",0x000034BC,0xFFFFE8DD,0x00000536,0x0000210E,0xFFFFF3F4,0x000003A8,0x0000210E,0xFFFFF3F4,0x000003A8},
-       {"0000001000010011111100001111111010011001001011000010100110100100",0x000034BE,0xFFFFE916,0x0000052F,0x000024A1,0xFFFFF1A6,0x00000410,0x000024A1,0xFFFFF1A6,0x00000410},
-       {"0000001000010011111100001111111010011001001100000100100101100100",0x000037B5,0xFFFFE7A9,0x0000055B,0x000028A1,0xFFFFEF51,0x00000467,0x000028A1,0xFFFFEF51,0x00000467},
-       {"0000001000010011111100001111111010011001001100000001000100000100",0x00002FC5,0xFFFFEBBE,0x000004D1,0x00001BA5,0xFFFFF757,0x00000328,0x00001BA5,0xFFFFF757,0x00000328},
-       {"0000001000010011111100001111111010011001001100000100000010100100",0x000033CB,0xFFFFE944,0x0000052B,0x00001FBE,0xFFFFF4B1,0x0000038C,0x00001FBE,0xFFFFF4B1,0x0000038C},
-       {"0000001000010011111100001111111010011001001100000001100001000100",0x000030AE,0xFFFFEBA0,0x000004D3,0x00002268,0xFFFFF316,0x000003DD,0x00002268,0xFFFFF316,0x000003DD},
-       {"0000001000010011111100001111111010011001001011000010000010100100",0x00002F90,0xFFFFEC5A,0x000004B0,0x00001C3A,0xFFFFF752,0x00000323,0x00001C3A,0xFFFFF752,0x00000323},
-       {"0000001000010011111100001111111010011001001011100011100011100100",0x00003113,0xFFFFEB91,0x000004C8,0x00001E3C,0xFFFFF623,0x0000034E,0x00001E3C,0xFFFFF623,0x0000034E},
-       {"0000001000010011111100001111111010011001001100100011100110000100",0x0000330B,0xFFFFE94B,0x00000539,0x000020E7,0xFFFFF37E,0x000003CD,0x000020E7,0xFFFFF37E,0x000003CD},
-       {"0000001000010011111100001111111010011001001011100010100001100100",0x000031D1,0xFFFFEACB,0x000004ED,0x00001E82,0xFFFFF5B2,0x00000365,0x00001E82,0xFFFFF5B2,0x00000365},
-       {"0000001000010011111100001111111010011001001010100011100110000100",0x00002CD5,0xFFFFEDC1,0x0000048D,0x000020F8,0xFFFFF3C1,0x000003D1,0x000020F8,0xFFFFF3C1,0x000003D1},
-       { NULL            ,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000}
+ static const struct phm_fuses_default vega10_fuses_default[] = {
+       { 0x0213EA94DE0E4964, 0x00003C96, 0xFFFFE226, 0x00000656, 0x00002203, 0xFFFFF201, 0x000003FF, 0x00002203, 0xFFFFF201, 0x000003FF },
+       { 0x0213EA94DE0A1884, 0x00003CC5, 0xFFFFE23A, 0x0000064E, 0x00002258, 0xFFFFF1F7, 0x000003FC, 0x00002258, 0xFFFFF1F7, 0x000003FC },
+       { 0x0213EA94DE0E31A4, 0x00003CAF, 0xFFFFE36E, 0x00000602, 0x00001E98, 0xFFFFF569, 0x00000357, 0x00001E98, 0xFFFFF569, 0x00000357 },
+       { 0x0213EA94DE2C1144, 0x0000391A, 0xFFFFE548, 0x000005C9, 0x00001B98, 0xFFFFF707, 0x00000324, 0x00001B98, 0xFFFFF707, 0x00000324 },
+       { 0x0213EA94DE2C18C4, 0x00003821, 0xFFFFE674, 0x00000597, 0x00002196, 0xFFFFF361, 0x000003C0, 0x00002196, 0xFFFFF361, 0x000003C0 },
+       { 0x0213EA94DE263884, 0x000044A2, 0xFFFFDCB7, 0x00000738, 0x0000325C, 0xFFFFE6A7, 0x000005E6, 0x0000325C, 0xFFFFE6A7, 0x000005E6 },
+       { 0x0213EA94DE082924, 0x00004057, 0xFFFFE1CF, 0x0000063C, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00002E2E, 0xFFFFEB62, 0x000004FD },
+       { 0x0213EA94DE284924, 0x00003FD0, 0xFFFFDF0F, 0x000006E5, 0x0000267C, 0xFFFFEE2D, 0x000004AB, 0x0000267C, 0xFFFFEE2D, 0x000004AB },
+       { 0x0213EA94DE280904, 0x00003F13, 0xFFFFE010, 0x000006AD, 0x000020E7, 0xFFFFF266, 0x000003EC, 0x000020E7, 0xFFFFF266, 0x000003EC },
+       { 0x0213EA94DE082044, 0x00004088, 0xFFFFDFAB, 0x000006B6, 0x0000252B, 0xFFFFEFDB, 0x00000458, 0x0000252B, 0xFFFFEFDB, 0x00000458 },
+       { 0x0213EA94DE283884, 0x00003EF6, 0xFFFFE017, 0x000006AA, 0x00001F67, 0xFFFFF369, 0x000003BE, 0x00001F67, 0xFFFFF369, 0x000003BE },
+       { 0x0213EA94DE2C2184, 0x00003CDD, 0xFFFFE2A7, 0x0000063C, 0x000026C6, 0xFFFFEF38, 0x00000478, 0x000026C6, 0xFFFFEF38, 0x00000478 },
+       { 0x0213EA94DE105124, 0x00003FA8, 0xFFFFDF02, 0x000006F0, 0x000027FE, 0xFFFFECF6, 0x000004EA, 0x000027FE, 0xFFFFECF6, 0x000004EA },
+       { 0x0213EA94DE2638C4, 0x00004670, 0xFFFFDC40, 0x00000742, 0x00003A7A, 0xFFFFE1A7, 0x000006B6, 0x00003A7A, 0xFFFFE1A7, 0x000006B6 },
+       { 0x0213EA94DE2C3024, 0x00003CDC, 0xFFFFE18C, 0x00000683, 0x00002A69, 0xFFFFEBE7, 0x00000515, 0x00002A69, 0xFFFFEBE7, 0x00000515 },
+       { 0x0213EA94DE0E38C4, 0x00003CEC, 0xFFFFE38E, 0x00000601, 0x00002752, 0xFFFFEFA7, 0x00000453, 0x00002752, 0xFFFFEFA7, 0x00000453 },
+       { 0x0213EA94DE2C1124, 0x000037D0, 0xFFFFE634, 0x000005A7, 0x00001CD2, 0xFFFFF644, 0x00000348, 0x00001CD2, 0xFFFFF644, 0x00000348 },
+       { 0x0213EA94DE283964, 0x00003DF5, 0xFFFFE0A5, 0x00000698, 0x00001FD5, 0xFFFFF30E, 0x000003D1, 0x00001FD5, 0xFFFFF30E, 0x000003D1 },
+       { 0x0213EA94DE0828C4, 0x00004201, 0xFFFFE03E, 0x00000688, 0x00003206, 0xFFFFE852, 0x0000058A, 0x00003206, 0xFFFFE852, 0x0000058A },
+       { 0x0213EA94DE2C1864, 0x00003BED, 0xFFFFE2F5, 0x00000638, 0x0000270D, 0xFFFFEED0, 0x0000048E, 0x0000270D, 0xFFFFEED0, 0x0000048E },
+       { 0x0213EA94DE0A1904, 0x00003E82, 0xFFFFE1BE, 0x00000654, 0x000025FB, 0xFFFFEFFA, 0x00000448, 0x000025FB, 0xFFFFEFFA, 0x00000448 },
+       { 0x0213EA94DE2C40C4, 0x00003962, 0xFFFFE4B9, 0x000005EF, 0x00002385, 0xFFFFF156, 0x00000423, 0x00002385, 0xFFFFF156, 0x00000423 },
+       { 0x0213EA94DE2C0944, 0x00003D88, 0xFFFFE21A, 0x00000655, 0x0000295A, 0xFFFFED68, 0x000004C4, 0x0000295A, 0xFFFFED68, 0x000004C4 },
+       { 0x0213EA94DE2C1104, 0x00003AA4, 0xFFFFE4A3, 0x000005E0, 0x000022EF, 0xFFFFF250, 0x000003EB, 0x000022EF, 0xFFFFF250, 0x000003EB },
+       { 0x0213EA94DE0E29A4, 0x00003D97, 0xFFFFE30D, 0x0000060D, 0x0000205D, 0xFFFFF45D, 0x00000380, 0x0000205D, 0xFFFFF45D, 0x00000380 },
+       { 0x0213EA94DE2C40A4, 0x000039B6, 0xFFFFE446, 0x00000605, 0x00002325, 0xFFFFF16C, 0x0000041F, 0x00002325, 0xFFFFF16C, 0x0000041F },
+       { 0x0213EA94DE263904, 0x0000457E, 0xFFFFDCF6, 0x00000722, 0x00003972, 0xFFFFE27B, 0x0000068E, 0x00003972, 0xFFFFE27B, 0x0000068E },
+       { 0x0213EA94DE0A1924, 0x00003FB8, 0xFFFFE101, 0x00000670, 0x00002787, 0xFFFFEEF5, 0x00000471, 0x00002787, 0xFFFFEEF5, 0x00000471 },
+       { 0x0213EA94DE0E38A4, 0x00003BB2, 0xFFFFE430, 0x000005EA, 0x000024A5, 0xFFFFF162, 0x00000409, 0x000024A5, 0xFFFFF162, 0x00000409 },
+       { 0x0213EA94DE082144, 0x00003EC5, 0xFFFFE1BD, 0x0000064F, 0x000022F0, 0xFFFFF227, 0x000003E8, 0x000022F0, 0xFFFFF227, 0x000003E8 },
+       { 0x0213EA94DE2C3164, 0x000038A7, 0xFFFFE59F, 0x000005C1, 0x000021CC, 0xFFFFF2DF, 0x000003D9, 0x000021CC, 0xFFFFF2DF, 0x000003D9 },
+       { 0x0213EA94DE324184, 0x00002995, 0xFFFFEF7A, 0x0000044C, 0x00001552, 0xFFFFFB5D, 0x00000292, 0x00001552, 0xFFFFFB5D, 0x00000292 },
+       { 0x0213EA94DE2C4064, 0x00003B26, 0xFFFFE2D3, 0x00000649, 0x000023B4, 0xFFFFF09B, 0x00000449, 0x000023B4, 0xFFFFF09B, 0x00000449 },
+       { 0x0213EA94DE081124, 0x000040D2, 0xFFFFE00A, 0x00000696, 0x000022DA, 0xFFFFF1E9, 0x000003F2, 0x000022DA, 0xFFFFF1E9, 0x000003F2 },
+       { 0x0213EA94DE2C3924, 0x00003C98, 0xFFFFE365, 0x00000618, 0x00002D5D, 0xFFFFEB3A, 0x0000051D, 0x00002D5D, 0xFFFFEB3A, 0x0000051D },
+       { 0x0213EA94DE2C10A4, 0x00003BBD, 0xFFFFE37E, 0x00000617, 0x0000252E, 0xFFFFF06E, 0x00000441, 0x0000252E, 0xFFFFF06E, 0x00000441 },
+       { 0x0213EA94DE262924, 0x00004363, 0xFFFFDF7A, 0x000006A0, 0x000031F5, 0xFFFFE880, 0x0000057B, 0x000031F5, 0xFFFFE880, 0x0000057B },
+       { 0x0213EA94DE0E3844, 0x00003CFC, 0xFFFFE2AF, 0x0000062E, 0x0000212A, 0xFFFFF335, 0x000003BF, 0x0000212A, 0xFFFFF335, 0x000003BF },
+       { 0x0213EA94DE1C4924, 0x0000252D, 0xFFFFF31B, 0x000003C3, 0x00001A1A, 0xFFFFF882, 0x00000325, 0x00001A1A, 0xFFFFF882, 0x00000325 },
+       { 0x0213EA94DE0A29A4, 0x00003FE2, 0xFFFFDFEF, 0x000006AC, 0x000025A2, 0xFFFFEF84, 0x00000462, 0x000025A2, 0xFFFFEF84, 0x00000462 },
+       { 0x0213EA94DE0820E4, 0x000040A5, 0xFFFFE13B, 0x0000065B, 0x00002C13, 0xFFFFEC75, 0x000004D7, 0x00002C13, 0xFFFFEC75, 0x000004D7 },
+       { 0x0213EA94DE0E48A4, 0x00003E42, 0xFFFFE1B3, 0x00000657, 0x0000221D, 0xFFFFF273, 0x000003DE, 0x0000221D, 0xFFFFF273, 0x000003DE },
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+       { 0x0213EA94DE263944, 0x0000430F, 0xFFFFDDFB, 0x000006FC, 0x00002D4D, 0xFFFFEA55, 0x00000540, 0x00002D4D, 0xFFFFEA55, 0x00000540 },
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+       { 0x0213EA94DE0E2084, 0x00003978, 0xFFFFE611, 0x00000592, 0x00001C36, 0xFFFFF771, 0x00000302, 0x00001C36, 0xFFFFF771, 0x00000302 },
+       { 0x0213EA94DE262164, 0x000044DF, 0xFFFFDDAB, 0x000006F2, 0x00002CEA, 0xFFFFEB47, 0x00000507, 0x00002CEA, 0xFFFFEB47, 0x00000507 },
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+       { 0x0213EA94DE281124, 0x00003FB3, 0xFFFFE052, 0x00000693, 0x000020AC, 0xFFFFF311, 0x000003C6, 0x000020AC, 0xFFFFF311, 0x000003C6 },
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+       { 0x0213F0FE99101124, 0x00002E0F, 0xFFFFECA7, 0x000004AE, 0x00001DC6, 0xFFFFF5BF, 0x0000036A, 0x00001DC6, 0xFFFFF5BF, 0x0000036A },
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+       { 0x0213EA94DE044884, 0x0000312D, 0xFFFFEA39, 0x00000515, 0x00001948, 0xFFFFF800, 0x00000318, 0x00001948, 0xFFFFF800, 0x00000318 },
+       { 0x0213EA94DE062084, 0x00003611, 0xFFFFE8D7, 0x00000533, 0x00001929, 0xFFFFF965, 0x000002D2, 0x00001929, 0xFFFFF965, 0x000002D2 },
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+       { 0x0213F0FE99181944, 0x000026CB, 0xFFFFF1FB, 0x000003E4, 0x000017CC, 0xFFFFFA25, 0x000002C8, 0x000017CC, 0xFFFFFA25, 0x000002C8 },
+       { 0x0213EA94DE0608C4, 0x00003274, 0xFFFFEA39, 0x0000050C, 0x00001B20, 0xFFFFF7C1, 0x00000314, 0x00001B20, 0xFFFFF7C1, 0x00000314 },
+       { 0x0213F0FD42D82924, 0x0000280B, 0xFFFFF283, 0x000003B5, 0x000018D0, 0xFFFFF992, 0x000002EC, 0x000018D0, 0xFFFFF992, 0x000002EC },
+       { 0x0213F0FE99062104, 0x000033AB, 0xFFFFEB1B, 0x000004C4, 0x00001FEE, 0xFFFFF53A, 0x00000378, 0x00001FEE, 0xFFFFF53A, 0x00000378 },
+       { 0x0213F0FE990A3964, 0x00002F79, 0xFFFFEB0C, 0x000004FA, 0x00001E57, 0xFFFFF4BF, 0x0000039B, 0x00001E57, 0xFFFFF4BF, 0x0000039B },
+       { 0x0213F0FE990448E4, 0x00003487, 0xFFFFE8F2, 0x00000539, 0x0000185B, 0xFFFFF9AE, 0x000002BA, 0x0000185B, 0xFFFFF9AE, 0x000002BA },
+       { 0x0213F0FE990A18A4, 0x00003500, 0xFFFFE793, 0x0000058A, 0x00001AA2, 0xFFFFF792, 0x0000031D, 0x00001AA2, 0xFFFFF792, 0x0000031D },
+       { 0x0213F0FE99081164, 0x00003943, 0xFFFFE54D, 0x000005D9, 0x00001BC8, 0xFFFFF6E0, 0x00000339, 0x00001BC8, 0xFFFFF6E0, 0x00000339 },
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+       { 0x0213F0FD42D83084, 0x00002BA4, 0xFFFFEE8D, 0x0000046A, 0x0000198C, 0xFFFFF88E, 0x00000307, 0x0000198C, 0xFFFFF88E, 0x00000307 },
+       { 0x0213F0FD42D218E4, 0x00003D30, 0xFFFFE2F6, 0x0000062A, 0x000025DC, 0xFFFFF074, 0x00000435, 0x000025DC, 0xFFFFF074, 0x00000435 },
+       { 0x0213F0FD42D83964, 0x00002CD6, 0xFFFFED79, 0x0000049B, 0x000016D0, 0xFFFFFA53, 0x000002BB, 0x000016D0, 0xFFFFFA53, 0x000002BB },
+       { 0x0213F0FE99163164, 0x00002484, 0xFFFFF3BD, 0x000003A0, 0x000015B8, 0xFFFFFB6B, 0x000002A4, 0x000015B8, 0xFFFFFB6B, 0x000002A4 },
+       { 0x0213F0FE990E3944, 0x000038AE, 0xFFFFE6D1, 0x00000587, 0x00001A2A, 0xFFFFF8F1, 0x000002D4, 0x00001A2A, 0xFFFFF8F1, 0x000002D4 },
+       { 0x0213F0FE99044944, 0x000036FD, 0xFFFFE76C, 0x00000576, 0x00001EE4, 0xFFFFF58D, 0x00000361, 0x00001EE4, 0xFFFFF58D, 0x00000361 },
+       { 0x0213F0FD42D830A4, 0x00002BCF, 0xFFFFEF28, 0x00000448, 0x00001B93, 0xFFFFF7BA, 0x00000327, 0x00001B93, 0xFFFFF7BA, 0x00000327 },
+       { 0x0213F0FE99062884, 0x00003834, 0xFFFFE818, 0x0000053B, 0x00001AFE, 0xFFFFF85C, 0x000002F3, 0x00001AFE, 0xFFFFF85C, 0x000002F3 },
+       { 0x0213F0FE993231A4, 0x00002EF7, 0xFFFFEBFC, 0x000004CE, 0x00001897, 0xFFFFF8EF, 0x000002EC, 0x00001897, 0xFFFFF8EF, 0x000002EC },
+       { 0x0213F0FE992C18C4, 0x000035BD, 0xFFFFE8BB, 0x0000053B, 0x00001F22, 0xFFFFF561, 0x00000373, 0x00001F22, 0xFFFFF561, 0x00000373 },
+       { 0x0213F0FE99183984, 0x00002D42, 0xFFFFEE1D, 0x00000478, 0x000016F0, 0xFFFFFAAE, 0x000002B3, 0x000016F0, 0xFFFFFAAE, 0x000002B3 },
+       { 0x0213EA94DE045124, 0x00002F98, 0xFFFFEB3C, 0x000004F0, 0x00001903, 0xFFFFF818, 0x00000319, 0x00001903, 0xFFFFF818, 0x00000319 },
+       { 0x0213F0FD42D42144, 0x00004081, 0xFFFFDF13, 0x000006F3, 0x00002A6D, 0xFFFFEC1B, 0x00000509, 0x00002A6D, 0xFFFFEC1B, 0x00000509 },
+       { 0x0213EA94DE040904, 0x00002D68, 0xFFFFED21, 0x00000498, 0x00001FF6, 0xFFFFF427, 0x000003B0, 0x00001FF6, 0xFFFFF427, 0x000003B0 },
+       { 0x0213F0FE99023884, 0x00003243, 0xFFFFEA5C, 0x000004FD, 0x000020FB, 0xFFFFF39E, 0x000003C0, 0x000020FB, 0xFFFFF39E, 0x000003C0 },
+       { 0x0213F0FD42D848A4, 0x00002F20, 0xFFFFEC19, 0x000004C6, 0x00001748, 0xFFFFF99F, 0x000002DA, 0x00001748, 0xFFFFF99F, 0x000002DA },
+       { 0x0213F0FE99103984, 0x00002D68, 0xFFFFED21, 0x00000498, 0x00001A43, 0xFFFFF843, 0x000002F9, 0x00001A43, 0xFFFFF843, 0x000002F9 },
+       { 0x0213F0FE990220A4, 0x0000396E, 0xFFFFE616, 0x000005A9, 0x00001A51, 0xFFFFF850, 0x000002FA, 0x00001A51, 0xFFFFF850, 0x000002FA },
+       { 0x0213F0FE99043144, 0x0000305C, 0xFFFFED4B, 0x0000046C, 0x00001CF9, 0xFFFFF7BA, 0x00000304, 0x00001CF9, 0xFFFFF7BA, 0x00000304 },
+       { 0x0213F0FD42DA4164, 0x0000343C, 0xFFFFE869, 0x00000559, 0x00001CE2, 0xFFFFF614, 0x00000359, 0x00001CE2, 0xFFFFF614, 0x00000359 },
+       { 0x0213F0FE99183964, 0x00002782, 0xFFFFF1FE, 0x000003D9, 0x000015DC, 0xFFFFFB8B, 0x00000290, 0x000015DC, 0xFFFFFB8B, 0x00000290 },
+       { 0x0213F0FE991818C4, 0x00002B9C, 0xFFFFEF63, 0x00000443, 0x00001369, 0xFFFFFD51, 0x00000244, 0x00001369, 0xFFFFFD51, 0x00000244 },
+       { 0x0213F0FE990A2084, 0x000035F8, 0xFFFFE743, 0x00000592, 0x000018D8, 0xFFFFF8EE, 0x000002E4, 0x000018D8, 0xFFFFF8EE, 0x000002E4 },
+       { 0x0213EA94DE062844, 0x00002B72, 0xFFFFEF1E, 0x0000043C, 0x00002647, 0xFFFFF092, 0x0000043E, 0x00002647, 0xFFFFF092, 0x0000043E },
+       { 0x0213F0FE99102184, 0x00002EC9, 0xFFFFEC5F, 0x000004B8, 0x000018B6, 0xFFFFF936, 0x000002D8, 0x000018B6, 0xFFFFF936, 0x000002D8 },
+       { 0x0213F0FE99064084, 0x000038A7, 0xFFFFE6AC, 0x00000589, 0x00001C42, 0xFFFFF70B, 0x00000329, 0x00001C42, 0xFFFFF70B, 0x00000329 },
+       { 0x0213F0FE993008A4, 0x00002F6B, 0xFFFFEBF6, 0x000004CF, 0x000018AE, 0xFFFFF928, 0x000002E3, 0x000018AE, 0xFFFFF928, 0x000002E3 },
+       { 0x0213F0FD42DA5104, 0x000029CD, 0xFFFFEEE1, 0x00000459, 0x00001AB5, 0xFFFFF76F, 0x00000324, 0x00001AB5, 0xFFFFF76F, 0x00000324 },
+       { 0x0213EA94DE0638C4, 0x00003921, 0xFFFFE71D, 0x00000577, 0x00001646, 0xFFFFFB24, 0x00000293, 0x00001646, 0xFFFFFB24, 0x00000293 },
+       { 0x0213EA94DE044164, 0x00003940, 0xFFFFE521, 0x000005E8, 0x00001947, 0xFFFFF839, 0x0000030D, 0x00001947, 0xFFFFF839, 0x0000030D },
+       { 0x0213F0FD42D24164, 0x00003DCA, 0xFFFFE211, 0x00000659, 0x0000250E, 0xFFFFF072, 0x00000443, 0x0000250E, 0xFFFFF072, 0x00000443 },
+       { 0x0213F0FE990C0904, 0x00002E95, 0xFFFFEC20, 0x000004C9, 0x000015B4, 0xFFFFFAD3, 0x0000029D, 0x000015B4, 0xFFFFFAD3, 0x0000029D },
+       { 0x0213F0FE99041084, 0x00002C11, 0xFFFFEE6E, 0x00000468, 0x00001901, 0xFFFFF924, 0x000002E7, 0x00001901, 0xFFFFF924, 0x000002E7 },
+       { 0x0213EA94DE062104, 0x0000293F, 0xFFFFF158, 0x000003E6, 0x0000183F, 0xFFFFF9F6, 0x000002D2, 0x0000183F, 0xFFFFF9F6, 0x000002D2 },
+       { 0x0213F0FE990E1104, 0x00002A67, 0xFFFFEF34, 0x0000043E, 0x00001C6F, 0xFFFFF6F1, 0x0000032B, 0x00001C6F, 0xFFFFF6F1, 0x0000032B },
+       { 0x0213EA94DE065124, 0x00002F8D, 0xFFFFEB77, 0x000004DA, 0x00001C0D, 0xFFFFF627, 0x00000365, 0x00001C0D, 0xFFFFF627, 0x00000365 },
+       { 0x0213F0FE990C38C4, 0x00003476, 0xFFFFEA5B, 0x000004E7, 0x00001DBF, 0xFFFFF6C7, 0x00000333, 0x00001DBF, 0xFFFFF6C7, 0x00000333 },
+       { 0x0213F0FE990E0944, 0x00003336, 0xFFFFE92F, 0x00000546, 0x00001614, 0xFFFFFAE0, 0x00000296, 0x00001614, 0xFFFFFAE0, 0x00000296 },
+       { 0x0213F0FE99162164, 0x00002513, 0xFFFFF323, 0x000003BC, 0x000016DB, 0xFFFFFA79, 0x000002CD, 0x000016DB, 0xFFFFFA79, 0x000002CD },
+       { 0x0213F0FE990A2944, 0x000035A7, 0xFFFFE78E, 0x00000584, 0x00001B0D, 0xFFFFF77D, 0x0000031F, 0x00001B0D, 0xFFFFF77D, 0x0000031F },
+       { 0x0213F0FE993238E4, 0x00003171, 0xFFFFEB98, 0x000004C6, 0x00001C76, 0xFFFFF71F, 0x0000032F, 0x00001C76, 0xFFFFF71F, 0x0000032F },
+       { 0x0213F0FD42DA1084, 0x00002C52, 0xFFFFED2E, 0x000004A7, 0x00002182, 0xFFFFF2F4, 0x000003E4, 0x00002182, 0xFFFFF2F4, 0x000003E4 },
+       { 0x0213F0FE99102924, 0x000032E1, 0xFFFFEB39, 0x000004D0, 0x00001B55, 0xFFFFF859, 0x000002FA, 0x00001B55, 0xFFFFF859, 0x000002FA },
+       { 0x0213F0FE991848A4, 0x000029B6, 0xFFFFEFF7, 0x00000430, 0x0000151B, 0xFFFFFBC6, 0x0000027F, 0x0000151B, 0xFFFFFBC6, 0x0000027F },
+       { 0x0213F0FD42DA1964, 0x00002FF7, 0xFFFFEB67, 0x000004DA, 0x000020E9, 0xFFFFF363, 0x000003CE, 0x000020E9, 0xFFFFF363, 0x000003CE },
+       { 0x0213F0FD42DA5124, 0x00003CDD, 0xFFFFE2B2, 0x00000649, 0x00001B18, 0xFFFFF739, 0x00000329, 0x00001B18, 0xFFFFF739, 0x00000329 },
+       { 0x0213F0FE990628A4, 0x00003C82, 0xFFFFE5C6, 0x0000058E, 0x00001F3F, 0xFFFFF5AD, 0x00000361, 0x00001F3F, 0xFFFFF5AD, 0x00000361 },
+       { 0x0213F0FD42DC4084, 0x0000319B, 0xFFFFEA15, 0x0000051B, 0x00001CC9, 0xFFFFF62E, 0x00000358, 0x00001CC9, 0xFFFFF62E, 0x00000358 },
+       { 0x0213EA94DE0638E4, 0x000032B6, 0xFFFFEB2B, 0x000004D6, 0x000018E0, 0xFFFFF966, 0x000002DE, 0x000018E0, 0xFFFFF966, 0x000002DE },
+       { 0x0213EA94DE023984, 0x0000300A, 0xFFFFEBA6, 0x000004D1, 0x00001CFD, 0xFFFFF5F6, 0x0000036D, 0x00001CFD, 0xFFFFF5F6, 0x0000036D },
+       { 0x0213F0FD42D82984, 0x000026A9, 0xFFFFF15D, 0x00000400, 0x00001561, 0xFFFFFB1F, 0x000002A0, 0x00001561, 0xFFFFFB1F, 0x000002A0 },
+       { 0x0213F0FE990E5124, 0x00003123, 0xFFFFEAD2, 0x000004FA, 0x000018CB, 0xFFFFF8F5, 0x000002EC, 0x000018CB, 0xFFFFF8F5, 0x000002EC },
+       { 0x0213F0FE991840C4, 0x00003577, 0xFFFFE935, 0x00000533, 0x000016CD, 0xFFFFFB44, 0x00000289, 0x000016CD, 0xFFFFFB44, 0x00000289 },
+       { 0x0213F0FE99282184, 0x00002875, 0xFFFFF170, 0x000003F3, 0x00001567, 0xFFFFFBD5, 0x00000289, 0x00001567, 0xFFFFFBD5, 0x00000289 },
+       { 0x0213F0FE99084084, 0x00003AE2, 0xFFFFE538, 0x000005C1, 0x00001CB4, 0xFFFFF6A3, 0x0000033C, 0x00001CB4, 0xFFFFF6A3, 0x0000033C },
+       { 0x0213F0FE990C38E4, 0x000031DF, 0xFFFFEC2A, 0x000004A3, 0x00001EF0, 0xFFFFF626, 0x00000352, 0x00001EF0, 0xFFFFF626, 0x00000352 },
+       { 0x0213F0FD42D25144, 0x00004A6A, 0xFFFFDB15, 0x00000758, 0x000027F3, 0xFFFFEEEE, 0x00000479, 0x000027F3, 0xFFFFEEEE, 0x00000479 },
+       { 0x0213EA94DE063904, 0x00002BB9, 0xFFFFEF5D, 0x00000433, 0x00001589, 0xFFFFFB57, 0x00000295, 0x00001589, 0xFFFFFB57, 0x00000295 },
+       { 0x0213F0FE99042164, 0x000033A0, 0xFFFFE98F, 0x00000528, 0x00001CB4, 0xFFFFF706, 0x0000032D, 0x00001CB4, 0xFFFFF706, 0x0000032D },
+       { 0x0213F0FE99163064, 0x0000248E, 0xFFFFF380, 0x000003AC, 0x000016EA, 0xFFFFFA6C, 0x000002CE, 0x000016EA, 0xFFFFFA6C, 0x000002CE },
+       { 0x0213F0FE990221A4, 0x00002FE2, 0xFFFFEB2F, 0x000004E9, 0x00001D4E, 0xFFFFF56B, 0x00000380, 0x00001D4E, 0xFFFFF56B, 0x00000380 },
+       { 0x0213F0FE990A2884, 0x00003283, 0xFFFFE9E7, 0x0000051D, 0x00000694, 0xFFFFFD32, 0x000003C3, 0x00000694, 0xFFFFFD32, 0x000003C3 },
+       { 0x0213F0FD42D850C4, 0x00002EE4, 0xFFFFEBFD, 0x000004D3, 0x0000151A, 0xFFFFFAF6, 0x000002A4, 0x0000151A, 0xFFFFFAF6, 0x000002A4 },
+       { 0x0213F0FD42DC18E4, 0x0000302D, 0xFFFFEB7F, 0x000004DA, 0x00001E6D, 0xFFFFF54B, 0x00000380, 0x00001E6D, 0xFFFFF54B, 0x00000380 },
+       { 0x0213F0FD42DA50C4, 0x000033DA, 0xFFFFE7FB, 0x0000057F, 0x00001DED, 0xFFFFF50E, 0x0000038D, 0x00001DED, 0xFFFFF50E, 0x0000038D },
+       { 0x0213F0FE992C4084, 0x000030B5, 0xFFFFEBB8, 0x000004C4, 0x00001C3F, 0xFFFFF726, 0x0000032A, 0x00001C3F, 0xFFFFF726, 0x0000032A },
+       { 0x0213F0FE990831C4, 0x00003BBD, 0xFFFFE55C, 0x000005B8, 0x000019DB, 0xFFFFF8BB, 0x000002EF, 0x000019DB, 0xFFFFF8BB, 0x000002EF },
+       { 0x0213F0FE990E3884, 0x00002964, 0xFFFFF051, 0x0000040E, 0x000025CD, 0xFFFFF11B, 0x0000041F, 0x000025CD, 0xFFFFF11B, 0x0000041F },
+       { 0x0213F0FD42DC4884, 0x000033F5, 0xFFFFE863, 0x00000560, 0x00001BCE, 0xFFFFF689, 0x0000034B, 0x00001BCE, 0xFFFFF689, 0x0000034B },
+       { 0x0213F0FE990A2864, 0x00003294, 0xFFFFE924, 0x00000548, 0x00001D41, 0xFFFFF580, 0x0000037D, 0x00001D41, 0xFFFFF580, 0x0000037D },
+       { 0x0213F0FD42DC39A4, 0x000034FB, 0xFFFFE7FE, 0x0000056D, 0x00001CB1, 0xFFFFF635, 0x00000357, 0x00001CB1, 0xFFFFF635, 0x00000357 },
+       { 0x0213F0FE990A10A4, 0x00002E28, 0xFFFFEBB9, 0x000004E0, 0x00001B20, 0xFFFFF6E3, 0x0000033C, 0x00001B20, 0xFFFFF6E3, 0x0000033C },
+       { 0x0213F0FD42DA1904, 0x00002799, 0xFFFFF0F4, 0x000003FC, 0x00001C9D, 0xFFFFF6A1, 0x00000345, 0x00001C9D, 0xFFFFF6A1, 0x00000345 },
+       { 0x0213F0FE99064104, 0x00003AEA, 0xFFFFE5DB, 0x0000059D, 0x00001B61, 0xFFFFF7F0, 0x00000301, 0x00001B61, 0xFFFFF7F0, 0x00000301 },
+       { 0x0213EA94DE041984, 0x000031F6, 0xFFFFEAB8, 0x000004F3, 0x00001D90, 0xFFFFF622, 0x00000359, 0x00001D90, 0xFFFFF622, 0x00000359 },
+       { 0x0213F0FE990C4064, 0x000031B8, 0xFFFFEA61, 0x0000050F, 0x0000199D, 0xFFFFF87C, 0x000002FD, 0x0000199D, 0xFFFFF87C, 0x000002FD },
+       { 0x0213F0FD42D23144, 0x00004514, 0xFFFFDDFF, 0x000006F6, 0x000022CD, 0xFFFFF29F, 0x000003D9, 0x000022CD, 0xFFFFF29F, 0x000003D9 },
+       { 0x0213EA94DE043164, 0x00002F30, 0xFFFFECB8, 0x000004A0, 0x00001B07, 0xFFFFF7E2, 0x00000313, 0x00001B07, 0xFFFFF7E2, 0x00000313 },
+       { 0x0213F0FD42DC30A4, 0x0000383B, 0xFFFFE702, 0x00000581, 0x00001A08, 0xFFFFF8CA, 0x000002E2, 0x00001A08, 0xFFFFF8CA, 0x000002E2 },
+       { 0x0213F0FE99022164, 0x00002CC5, 0xFFFFEDF8, 0x00000465, 0x00001F47, 0xFFFFF4B2, 0x00000393, 0x00001F47, 0xFFFFF4B2, 0x00000393 },
+       { 0x0213F0FE991621C4, 0x00002304, 0xFFFFF453, 0x00000384, 0x0000170A, 0xFFFFFA3F, 0x000002CE, 0x0000170A, 0xFFFFFA3F, 0x000002CE },
+       { 0x0213F0FE990A5124, 0x0000337E, 0xFFFFE850, 0x0000056E, 0x00001BDD, 0xFFFFF668, 0x00000353, 0x00001BDD, 0xFFFFF668, 0x00000353 },
+       { 0x0213F0FE990E4924, 0x00002E2F, 0xFFFFEC9B, 0x000004AE, 0x00001C4D, 0xFFFFF6D3, 0x00000338, 0x00001C4D, 0xFFFFF6D3, 0x00000338 },
+       { 0x0213EA94DE061124, 0x00002DDD, 0xFFFFEDA4, 0x00000477, 0x00002010, 0xFFFFF4BB, 0x00000390, 0x00002010, 0xFFFFF4BB, 0x00000390 },
+       { 0x0213F0FD42DA48E4, 0x0000290C, 0xFFFFEF61, 0x00000445, 0x00002133, 0xFFFFF324, 0x000003D8, 0x00002133, 0xFFFFF324, 0x000003D8 },
+       { 0x0213F0FE99062924, 0x0000371E, 0xFFFFE8D5, 0x00000524, 0x00001C3A, 0xFFFFF7AE, 0x00000314, 0x00001C3A, 0xFFFFF7AE, 0x00000314 },
+       { 0x0213F0FD42D838E4, 0x00002A58, 0xFFFFF007, 0x00000429, 0x000018A6, 0xFFFFF98F, 0x000002E1, 0x000018A6, 0xFFFFF98F, 0x000002E1 },
+       { 0x0213F0FE99023084, 0x00002FED, 0xFFFFEC48, 0x000004AA, 0x00001E9D, 0xFFFFF584, 0x00000370, 0x00001E9D, 0xFFFFF584, 0x00000370 },
+       { 0x0213F0FE99181884, 0x00002829, 0xFFFFF15F, 0x000003F7, 0x0000157E, 0xFFFFFBD4, 0x00000282, 0x0000157E, 0xFFFFFBD4, 0x00000282 },
+       { 0x0213F0FE99101924, 0x000030CF, 0xFFFFEB8D, 0x000004CE, 0x00001A4C, 0xFFFFF868, 0x000002F7, 0x00001A4C, 0xFFFFF868, 0x000002F7 },
+       { 0x0213F0FD42DA2084, 0x00002C8F, 0xFFFFEDD2, 0x0000047D, 0x00001CCE, 0xFFFFF6A1, 0x00000343, 0x00001CCE, 0xFFFFF6A1, 0x00000343 },
+       { 0x0213F0FE99182164, 0x00002A84, 0xFFFFEFBA, 0x0000043E, 0x000015EF, 0xFFFFFB4B, 0x0000029E, 0x000015EF, 0xFFFFFB4B, 0x0000029E },
+       { 0x0213F0FE990C28A4, 0x000034CA, 0xFFFFEA08, 0x000004FF, 0x00001C19, 0xFFFFF7ED, 0x00000309, 0x00001C19, 0xFFFFF7ED, 0x00000309 },
+       { 0x0213F0FE991639A4, 0x00002187, 0xFFFFF4B0, 0x0000037E, 0x0000154A, 0xFFFFFB0C, 0x000002AE, 0x0000154A, 0xFFFFFB0C, 0x000002AE },
+       { 0x0213F0FD42DA3844, 0x00002F4F, 0xFFFFEB3C, 0x000004F8, 0x0000181F, 0xFFFFF92D, 0x000002DF, 0x0000181F, 0xFFFFF92D, 0x000002DF },
+       { 0x0213F0FE990410E4, 0x0000290C, 0xFFFFF0B1, 0x000003FC, 0x00001DB0, 0xFFFFF636, 0x00000355, 0x00001DB0, 0xFFFFF636, 0x00000355 },
+       { 0x0213F0FE990A1064, 0x000034C1, 0xFFFFE888, 0x0000055A, 0x000019BF, 0xFFFFF881, 0x000002FB, 0x000019BF, 0xFFFFF881, 0x000002FB },
+       { 0x0213F0FD42DC18C4, 0x00003139, 0xFFFFEA98, 0x00000504, 0x000019F2, 0xFFFFF820, 0x0000030B, 0x000019F2, 0xFFFFF820, 0x0000030B },
+       { 0x0213F0FD42D83144, 0x00002CAC, 0xFFFFEEB2, 0x00000458, 0x0000152C, 0xFFFFFBEF, 0x0000027B, 0x0000152C, 0xFFFFFBEF, 0x0000027B },
+       { 0x0213F0FE992C38E4, 0x00003577, 0xFFFFE99C, 0x0000050D, 0x00001E64, 0xFFFFF679, 0x0000033F, 0x00001E64, 0xFFFFF679, 0x0000033F },
+       { 0x0213F0FD42DA4104, 0x0000263A, 0xFFFFF1E4, 0x000003D4, 0x00001F68, 0xFFFFF4ED, 0x00000386, 0x00001F68, 0xFFFFF4ED, 0x00000386 },
+       { 0x0213F0FD42D81984, 0x00002CE9, 0xFFFFED63, 0x00000497, 0x00001810, 0xFFFFF94D, 0x000002E3, 0x00001810, 0xFFFFF94D, 0x000002E3 },
+       { 0x0213EA94DE044104, 0x0000318A, 0xFFFFEAC8, 0x000004F5, 0x0000195C, 0xFFFFF896, 0x000002FB, 0x0000195C, 0xFFFFF896, 0x000002FB },
+       { 0x0213F0FD42D83904, 0x00002C41, 0xFFFFEEC6, 0x0000045D, 0x000017DD, 0xFFFFFA16, 0x000002CB, 0x000017DD, 0xFFFFFA16, 0x000002CB },
+       { 0x0213F0FE990231A4, 0x00002DD4, 0xFFFFEC98, 0x000004AD, 0x00001BD7, 0xFFFFF69F, 0x00000347, 0x00001BD7, 0xFFFFF69F, 0x00000347 },
+       { 0x0213F0FD42DA3944, 0x00003351, 0xFFFFE9B2, 0x0000051A, 0x00001CA1, 0xFFFFF6A4, 0x00000341, 0x00001CA1, 0xFFFFF6A4, 0x00000341 },
+       { 0x0213F0FE99021104, 0x0000322D, 0xFFFFE9BE, 0x00000527, 0x00001CF9, 0xFFFFF5EB, 0x00000366, 0x00001CF9, 0xFFFFF5EB, 0x00000366 },
+       { 0x0213F0FE990C28C4, 0x00003678, 0xFFFFE9A8, 0x00000503, 0x00001AD4, 0xFFFFF8F6, 0x000002E3, 0x00001AD4, 0xFFFFF8F6, 0x000002E3 },
+       { 0x0213F0FE99161924, 0x0000260E, 0xFFFFF2C1, 0x000003CA, 0x00001139, 0xFFFFFE48, 0x00000236, 0x00001139, 0xFFFFFE48, 0x00000236 },
+       { 0x0213F0FE990A2164, 0x000033D3, 0xFFFFE872, 0x00000565, 0x00001B72, 0xFFFFF713, 0x00000332, 0x00001B72, 0xFFFFF713, 0x00000332 },
+       { 0x0213F0FE99323844, 0x0000309B, 0xFFFFEB42, 0x000004E4, 0x00001918, 0xFFFFF8C8, 0x000002F2, 0x00001918, 0xFFFFF8C8, 0x000002F2 },
+       { 0x0213F0FE99182864, 0x000028B8, 0xFFFFF105, 0x00000402, 0x000018BB, 0xFFFFF9BC, 0x000002D3, 0x000018BB, 0xFFFFF9BC, 0x000002D3 },
+       { 0x0213F0FE990A1884, 0x00003123, 0xFFFFE9D1, 0x00000534, 0x00001B19, 0xFFFFF6FE, 0x0000033C, 0x00001B19, 0xFFFFF6FE, 0x0000033C },
+       { 0x0213F0FE99022144, 0x00003216, 0xFFFFEA8E, 0x000004F6, 0x00001F72, 0xFFFFF4CE, 0x0000038B, 0x00001F72, 0xFFFFF4CE, 0x0000038B },
+       { 0x0213F0FE99162964, 0x00002564, 0xFFFFF32D, 0x000003B6, 0x00001685, 0xFFFFFADB, 0x000002BB, 0x00001685, 0xFFFFFADB, 0x000002BB },
+       { 0x0213F0FD42DA2924, 0x00002E60, 0xFFFFED13, 0x00000497, 0x00001CA5, 0xFFFFF6B9, 0x00000346, 0x00001CA5, 0xFFFFF6B9, 0x00000346 },
+       { 0x0213F0FE990E39A4, 0x0000336D, 0xFFFFE934, 0x0000053B, 0x00001B3E, 0xFFFFF763, 0x00000327, 0x00001B3E, 0xFFFFF763, 0x00000327 },
+       { 0x0213F0FE99101084, 0x0000274A, 0xFFFFF119, 0x000003FA, 0x00001D75, 0xFFFFF5CD, 0x0000036F, 0x00001D75, 0xFFFFF5CD, 0x0000036F },
+       { 0x0213F0FD42DA2164, 0x0000366B, 0xFFFFE70A, 0x0000059A, 0x00001ED8, 0xFFFFF501, 0x00000389, 0x00001ED8, 0xFFFFF501, 0x00000389 },
+       { 0x0213F0FE99223964, 0x00003164, 0xFFFFEAB4, 0x000004FA, 0x00001C52, 0xFFFFF6E0, 0x00000336, 0x00001C52, 0xFFFFF6E0, 0x00000336 },
+       { 0x0213F0FD42D23064, 0x00004224, 0xFFFFDF7F, 0x000006C1, 0x00002A52, 0xFFFFED5E, 0x000004BB, 0x00002A52, 0xFFFFED5E, 0x000004BB },
+       { 0x0213F0FE99102864, 0x000030E3, 0xFFFFEB07, 0x000004ED, 0x00001FD3, 0xFFFFF46D, 0x000003A1, 0x00001FD3, 0xFFFFF46D, 0x000003A1 },
+       { 0x0213F0FD42D82884, 0x00002AEB, 0xFFFFEF1B, 0x00000454, 0x00001829, 0xFFFFF995, 0x000002DD, 0x00001829, 0xFFFFF995, 0x000002DD },
+       { 0x0213F0FD42DC50E4, 0x0000346B, 0xFFFFE7A2, 0x0000058B, 0x000020C5, 0xFFFFF2E8, 0x000003EC, 0x000020C5, 0xFFFFF2E8, 0x000003EC },
+       { 0x0213F0FD42DC4164, 0x000039CF, 0xFFFFE5D7, 0x000005A9, 0x00001D66, 0xFFFFF5D6, 0x00000366, 0x00001D66, 0xFFFFF5D6, 0x00000366 },
+       { 0x0213F0FE990418E4, 0x000034AC, 0xFFFFE9AE, 0x00000515, 0x00001A28, 0xFFFFF904, 0x000002DC, 0x00001A28, 0xFFFFF904, 0x000002DC },
+       { 0x0213F0FD42DC2084, 0x00002D68, 0xFFFFED21, 0x00000498, 0x00001C6F, 0xFFFFF686, 0x0000034C, 0x00001C6F, 0xFFFFF686, 0x0000034C },
+       { 0x0213F0FE990820C4, 0x0000328B, 0xFFFFEBA1, 0x000004B4, 0x00001DA3, 0xFFFFF683, 0x00000349, 0x00001DA3, 0xFFFFF683, 0x00000349 },
+       { 0x0213F0FE991828C4, 0x000027DC, 0xFFFFF295, 0x000003BF, 0x000019C1, 0xFFFFF98E, 0x000002E8, 0x000019C1, 0xFFFFF98E, 0x000002E8 },
+       { 0x0213F0FE99184084, 0x00002756, 0xFFFFF1D7, 0x000003DF, 0x000015D9, 0xFFFFFB51, 0x00000298, 0x000015D9, 0xFFFFFB51, 0x00000298 },
+       { 0x0213F0FE99083884, 0x00003526, 0xFFFFE907, 0x00000526, 0x000017AB, 0xFFFFFA12, 0x000002AB, 0x000017AB, 0xFFFFFA12, 0x000002AB },
+       { 0x0213F0FD42DA18E4, 0x0000351B, 0xFFFFE8B7, 0x00000540, 0x00001A86, 0xFFFFF821, 0x00000303, 0x00001A86, 0xFFFFF821, 0x00000303 },
+       { 0x0213F0FE99164144, 0x000024B2, 0xFFFFF34E, 0x000003B1, 0x000018E2, 0xFFFFF926, 0x000002FC, 0x000018E2, 0xFFFFF926, 0x000002FC },
+       { 0x0213F0FD42D828A4, 0x00002F36, 0xFFFFED5D, 0x00000486, 0x0000157A, 0xFFFFFB85, 0x00000293, 0x0000157A, 0xFFFFFB85, 0x00000293 },
+       { 0x0213F0FD42DC50C4, 0x00003A6E, 0xFFFFE456, 0x000005FD, 0x00001F68, 0xFFFFF3D1, 0x000003C3, 0x00001F68, 0xFFFFF3D1, 0x000003C3 },
+       { 0x0213F0FE990A31A4, 0x00002BC3, 0xFFFFED2D, 0x000004A7, 0x00001C3F, 0xFFFFF609, 0x00000364, 0x00001C3F, 0xFFFFF609, 0x00000364 },
+       { 0x0213F0FE990E2084, 0x000032E1, 0xFFFFEA83, 0x000004F6, 0x00001B37, 0xFFFFF842, 0x000002F5, 0x00001B37, 0xFFFFF842, 0x000002F5 },
+       { 0x0213F0FD42D83184, 0x000028E3, 0xFFFFF07F, 0x00000412, 0x00001676, 0xFFFFFA68, 0x000002BE, 0x00001676, 0xFFFFFA68, 0x000002BE },
+       { 0x0213F0FD42D21104, 0x0000444C, 0xFFFFDDAD, 0x00000712, 0x00002634, 0xFFFFEF89, 0x0000046C, 0x00002634, 0xFFFFEF89, 0x0000046C },
+       { 0x0213F0FE990418C4, 0x00003121, 0xFFFFEBBB, 0x000004C6, 0x00001C98, 0xFFFFF72B, 0x0000032D, 0x00001C98, 0xFFFFF72B, 0x0000032D },
+       { 0x0213F0FD42D840A4, 0x00002C31, 0xFFFFEDC4, 0x00000490, 0x0000162D, 0xFFFFFA8E, 0x000002B4, 0x0000162D, 0xFFFFFA8E, 0x000002B4 },
+       { 0x0213F0FD42DA18C4, 0x00002749, 0xFFFFF112, 0x000003FC, 0x00001C85, 0xFFFFF6B8, 0x00000342, 0x00001C85, 0xFFFFF6B8, 0x00000342 },
+       { 0x0213F0FE99044104, 0x00003159, 0xFFFFEB99, 0x000004C2, 0x00001BD0, 0xFFFFF7CA, 0x00000307, 0x00001BD0, 0xFFFFF7CA, 0x00000307 },
+       { 0x0213F0FE99164164, 0x00002610, 0xFFFFF1FD, 0x000003EC, 0x000016BE, 0xFFFFFA53, 0x000002CB, 0x000016BE, 0xFFFFFA53, 0x000002CB },
+       { 0x0213F0FE99023184, 0x000037B5, 0xFFFFE63D, 0x000005B5, 0x00002285, 0xFFFFF25D, 0x000003F7, 0x00002285, 0xFFFFF25D, 0x000003F7 },
+       { 0x0213F0FE990A28A4, 0x00002FEE, 0xFFFFEB47, 0x000004EF, 0x00001CBE, 0xFFFFF64E, 0x00000358, 0x00001CBE, 0xFFFFF64E, 0x00000358 },
+       { 0x0213F0FE99105104, 0x00002E90, 0xFFFFEC48, 0x000004C0, 0x00001A47, 0xFFFFF7D1, 0x0000031A, 0x00001A47, 0xFFFFF7D1, 0x0000031A },
+       { 0x0213F0FD42DA4084, 0x000034AB, 0xFFFFE84A, 0x00000559, 0x00001A72, 0xFFFFF79A, 0x0000031C, 0x00001A72, 0xFFFFF79A, 0x0000031C },
+       { 0x0213F0FE99183884, 0x00002F7B, 0xFFFFECFC, 0x0000049C, 0x00001814, 0xFFFFFA22, 0x000002C2, 0x00001814, 0xFFFFFA22, 0x000002C2 },
+       { 0x0213F0FE99021964, 0x00003618, 0xFFFFE709, 0x00000596, 0x00001EBF, 0xFFFFF482, 0x000003A5, 0x00001EBF, 0xFFFFF482, 0x000003A5 },
+       { 0x0213EA94DE024904, 0x0000341B, 0xFFFFE8B2, 0x0000054F, 0x00001D26, 0xFFFFF578, 0x00000388, 0x00001D26, 0xFFFFF578, 0x00000388 },
+       { 0x0213F0FE99102144, 0x000030F6, 0xFFFFEB89, 0x000004CD, 0x000019C0, 0xFFFFF8CC, 0x000002E6, 0x000019C0, 0xFFFFF8CC, 0x000002E6 },
+       { 0x0213F0FE992841A4, 0x00002B76, 0xFFFFEF6C, 0x00000444, 0x00001563, 0xFFFFFBBE, 0x0000028D, 0x00001563, 0xFFFFFBBE, 0x0000028D },
+       { 0x0213F0FD42D81864, 0x00002BA2, 0xFFFFEE31, 0x0000047F, 0x00001A3D, 0xFFFFF7F3, 0x00000320, 0x00001A3D, 0xFFFFF7F3, 0x00000320 },
+       { 0x0213F0FE992C48E4, 0x00003545, 0xFFFFE87A, 0x0000054A, 0x00001B5A, 0xFFFFF7B0, 0x0000030C, 0x00001B5A, 0xFFFFF7B0, 0x0000030C },
+       { 0x0213EA94DE042944, 0x00003879, 0xFFFFE73F, 0x00000578, 0x00001649, 0xFFFFFB57, 0x00000283, 0x00001649, 0xFFFFFB57, 0x00000283 },
+       { 0x0213F0FD42D840C4, 0x00002772, 0xFFFFF0F1, 0x00000410, 0x0000142F, 0xFFFFFBCF, 0x00000287, 0x0000142F, 0xFFFFFBCF, 0x00000287 },
+       { 0x0213F0FD42DA3184, 0x00003228, 0xFFFFE98E, 0x00000535, 0x00001F48, 0xFFFFF495, 0x00000399, 0x00001F48, 0xFFFFF495, 0x00000399 },
+       { 0x0213F0FE990E40E4, 0x00002887, 0xFFFFF119, 0x000003E8, 0x000021AA, 0xFFFFF3F5, 0x000003A5, 0x000021AA, 0xFFFFF3F5, 0x000003A5 },
+       { 0x0213F0FD42DA28A4, 0x0000301F, 0xFFFFEBB2, 0x000004D2, 0x00001C02, 0xFFFFF736, 0x0000032B, 0x00001C02, 0xFFFFF736, 0x0000032B },
+       { 0x0213F0FE991820A4, 0x00002E13, 0xFFFFEE3F, 0x00000468, 0x000016AC, 0xFFFFFB32, 0x0000029E, 0x000016AC, 0xFFFFFB32, 0x0000029E },
+       { 0x0213F0FE99044924, 0x00003478, 0xFFFFE8F9, 0x00000538, 0x00001DAB, 0xFFFFF645, 0x00000345, 0x00001DAB, 0xFFFFF645, 0x00000345 },
+       { 0x0213F0FE990608C4, 0x000030C6, 0xFFFFEB6C, 0x000004D4, 0x0000184A, 0xFFFFF934, 0x000002E1, 0x0000184A, 0xFFFFF934, 0x000002E1 },
+       { 0x0213F0FE990A2044, 0x00002F1B, 0xFFFFEBD3, 0x000004D3, 0x000019E7, 0xFFFFF813, 0x0000030D, 0x000019E7, 0xFFFFF813, 0x0000030D },
+       { 0x0213F0FE99023904, 0x00003214, 0xFFFFEAE9, 0x000004E0, 0x0000178F, 0xFFFFFA1C, 0x000002B1, 0x0000178F, 0xFFFFFA1C, 0x000002B1 },
+       { 0x0213F0FD42DC3144, 0x0000399C, 0xFFFFE738, 0x0000055E, 0x00001EA1, 0xFFFFF5E7, 0x0000035A, 0x00001EA1, 0xFFFFF5E7, 0x0000035A },
+       { 0x0213F0FE990650C4, 0x00003A01, 0xFFFFE5B2, 0x000005B6, 0x00001D95, 0xFFFFF5D2, 0x0000036A, 0x00001D95, 0xFFFFF5D2, 0x0000036A },
+       { 0x0213F0FE99043884, 0x0000310D, 0xFFFFEB78, 0x000004D0, 0x00001C06, 0xFFFFF76E, 0x0000031A, 0x00001C06, 0xFFFFF76E, 0x0000031A },
+       { 0x0213F0FE99063864, 0x00003CD1, 0xFFFFE42F, 0x000005EB, 0x00001933, 0xFFFFF91F, 0x000002D4, 0x00001933, 0xFFFFF91F, 0x000002D4 },
+       { 0x0213F0FD42DA3164, 0x00003119, 0xFFFFEB1B, 0x000004E1, 0x00001FC7, 0xFFFFF46A, 0x000003A2, 0x00001FC7, 0xFFFFF46A, 0x000003A2 },
+       { 0x0213EA94DE0648A4, 0x0000390D, 0xFFFFE566, 0x000005D8, 0x00001EC6, 0xFFFFF4DC, 0x00000391, 0x00001EC6, 0xFFFFF4DC, 0x00000391 },
+       { 0x0213F0FD42DA10C4, 0x00003446, 0xFFFFE858, 0x00000561, 0x00001FDB, 0xFFFFF3FF, 0x000003B9, 0x00001FDB, 0xFFFFF3FF, 0x000003B9 },
+       { 0x0213F0FE99044904, 0x000032BA, 0xFFFFEA07, 0x00000511, 0x00001B25, 0xFFFFF7C9, 0x0000030D, 0x00001B25, 0xFFFFF7C9, 0x0000030D },
+       { 0x0213F0FE990E1864, 0x00002CCF, 0xFFFFEDE5, 0x00000478, 0x00001BC8, 0xFFFFF761, 0x00000326, 0x00001BC8, 0xFFFFF761, 0x00000326 },
+       { 0x0213F0FE99062984, 0x0000400E, 0xFFFFE1CB, 0x00000652, 0x00001AF8, 0xFFFFF7B9, 0x00000312, 0x00001AF8, 0xFFFFF7B9, 0x00000312 },
+       { 0x0213F0FE990408E4, 0x00002F24, 0xFFFFEC2A, 0x000004C7, 0x00001B94, 0xFFFFF748, 0x00000333, 0x00001B94, 0xFFFFF748, 0x00000333 },
+       { 0x0213F0FD42D21924, 0x00003FDA, 0xFFFFE1C1, 0x0000064B, 0x00002427, 0xFFFFF180, 0x0000040C, 0x00002427, 0xFFFFF180, 0x0000040C },
+       { 0x0213F0FE990A18C4, 0x00002F6B, 0xFFFFEBA7, 0x000004DD, 0x00001C25, 0xFFFFF6C1, 0x00000344, 0x00001C25, 0xFFFFF6C1, 0x00000344 },
+       { 0x0213F0FE99182104, 0x00002A53, 0xFFFFF0EE, 0x00000402, 0x000017C6, 0xFFFFFAA0, 0x000002BF, 0x000017C6, 0xFFFFFAA0, 0x000002BF },
+       { 0x0213F0FE99105144, 0x000031F4, 0xFFFFEA34, 0x00000517, 0x000016FF, 0xFFFFFA4E, 0x000002AC, 0x000016FF, 0xFFFFFA4E, 0x000002AC },
+       { 0x0213F0FE99322144, 0x00002E24, 0xFFFFED46, 0x00000489, 0x00001712, 0xFFFFFA5D, 0x000002AC, 0x00001712, 0xFFFFFA5D, 0x000002AC },
+       { 0x0213F0FE99182824, 0x000028CD, 0xFFFFF0E3, 0x0000040E, 0x00001606, 0xFFFFFB37, 0x000002A4, 0x00001606, 0xFFFFFB37, 0x000002A4 },
+       { 0x0213F0FE990220C4, 0x00003184, 0xFFFFEB88, 0x000004C3, 0x000018DA, 0xFFFFF939, 0x000002DB, 0x000018DA, 0xFFFFF939, 0x000002DB },
+       { 0x0213F0FE99162124, 0x0000239B, 0xFFFFF470, 0x00000386, 0x00001714, 0xFFFFFA9F, 0x000002C8, 0x00001714, 0xFFFFFA9F, 0x000002C8 },
+       { 0x0213F0FD42DC38E4, 0x00003641, 0xFFFFE92B, 0x00000515, 0x00001BE2, 0xFFFFF795, 0x0000031B, 0x00001BE2, 0xFFFFF795, 0x0000031B },
+       { 0x0213F0FE992C1144, 0x00003278, 0xFFFFEA17, 0x00000510, 0x00001B71, 0xFFFFF778, 0x0000031D, 0x00001B71, 0xFFFFF778, 0x0000031D },
+       { 0x0213F0FE99062844, 0x000035B9, 0xFFFFE8DA, 0x0000052D, 0x00001A6A, 0xFFFFF83B, 0x000002FF, 0x00001A6A, 0xFFFFF83B, 0x000002FF },
+       { 0x0213F0FE990E18C4, 0x00002E5E, 0xFFFFED32, 0x0000048B, 0x00001E7D, 0xFFFFF60E, 0x0000034E, 0x00001E7D, 0xFFFFF60E, 0x0000034E },
+       { 0x0213F0FE991019A4, 0x00003178, 0xFFFFEA52, 0x00000513, 0x00001AD0, 0xFFFFF793, 0x0000031F, 0x00001AD0, 0xFFFFF793, 0x0000031F },
+       { 0x0213F0FD42D44104, 0x00003A2C, 0xFFFFE346, 0x00000641, 0x000023D0, 0xFFFFF0CE, 0x00000433, 0x000023D0, 0xFFFFF0CE, 0x00000433 },
+       { 0x0213F0FD42D818C4, 0x000028FD, 0xFFFFF02A, 0x0000042B, 0x0000152B, 0xFFFFFB90, 0x00000289, 0x0000152B, 0xFFFFFB90, 0x00000289 },
+       { 0x0213F0FE990E3084, 0x000030DE, 0xFFFFEBDF, 0x000004BE, 0x00001CDC, 0xFFFFF747, 0x0000031C, 0x00001CDC, 0xFFFFF747, 0x0000031C },
+       { 0x0213F0FE99021944, 0x000036CB, 0xFFFFE6EE, 0x00000596, 0x00002096, 0xFFFFF3C2, 0x000003BB, 0x00002096, 0xFFFFF3C2, 0x000003BB },
+       { 0x0213F0FE990C48C4, 0x00003172, 0xFFFFEAC1, 0x000004F4, 0x00001C87, 0xFFFFF6CD, 0x00000337, 0x00001C87, 0xFFFFF6CD, 0x00000337 },
+       { 0x0213F0FD42D24864, 0x00004A18, 0xFFFFDB34, 0x00000758, 0x0000213C, 0xFFFFF3A2, 0x000003AC, 0x0000213C, 0xFFFFF3A2, 0x000003AC },
+       { 0x0213F0FE99022104, 0x000031F3, 0xFFFFEB73, 0x000004C6, 0x00001B23, 0xFFFFF7CB, 0x0000031A, 0x00001B23, 0xFFFFF7CB, 0x0000031A },
+       { 0x0213F0FE990A2924, 0x000031C0, 0xFFFFEABA, 0x000004F7, 0x00001A5A, 0xFFFFF845, 0x000002FF, 0x00001A5A, 0xFFFFF845, 0x000002FF },
+       { 0x0213F0FE99104944, 0x00003B77, 0xFFFFE3B3, 0x00000623, 0x00001BCA, 0xFFFFF6F8, 0x00000333, 0x00001BCA, 0xFFFFF6F8, 0x00000333 },
+       { 0x0213F0FE990A3944, 0x000035AF, 0xFFFFE76D, 0x00000588, 0x00001C16, 0xFFFFF6AB, 0x00000341, 0x00001C16, 0xFFFFF6AB, 0x00000341 },
+       { 0x0213EA94DE0438C4, 0x000032AD, 0xFFFFEA8E, 0x000004F8, 0x00001A3A, 0xFFFFF832, 0x0000030E, 0x00001A3A, 0xFFFFF832, 0x0000030E },
+       { 0x0213F0FE99104884, 0x00002E92, 0xFFFFEBD2, 0x000004DA, 0x00001E04, 0xFFFFF51E, 0x0000038A, 0x00001E04, 0xFFFFF51E, 0x0000038A },
+       { 0x0213F0FD42D440A4, 0x00003E57, 0xFFFFE0F7, 0x0000068F, 0x000021F1, 0xFFFFF1C6, 0x00000411, 0x000021F1, 0xFFFFF1C6, 0x00000411 },
+       { 0x0213F0FE990821A4, 0x00003598, 0xFFFFE8BB, 0x00000535, 0x00001B62, 0xFFFFF764, 0x00000326, 0x00001B62, 0xFFFFF764, 0x00000326 },
+       { 0x0213F0FE990A3884, 0x00002B15, 0xFFFFEDEC, 0x00000487, 0x00001E8B, 0xFFFFF4AB, 0x0000039F, 0x00001E8B, 0xFFFFF4AB, 0x0000039F },
+       { 0x0213EA94DE060904, 0x0000267E, 0xFFFFF1A7, 0x000003E1, 0x000021C1, 0xFFFFF2E9, 0x000003EA, 0x000021C1, 0xFFFFF2E9, 0x000003EA },
+       { 0x0213EA94DE0239A4, 0x00002ED7, 0xFFFFEC88, 0x000004A6, 0x00001DEC, 0xFFFFF57C, 0x00000378, 0x00001DEC, 0xFFFFF57C, 0x00000378 },
+       { 0x0213EA94DE0441A4, 0x00003365, 0xFFFFE946, 0x00000536, 0x000019E9, 0xFFFFF7E0, 0x0000031D, 0x000019E9, 0xFFFFF7E0, 0x0000031D },
+       { 0x0213F0FE991818E4, 0x000029A4, 0xFFFFF0FD, 0x000003FE, 0x0000163F, 0xFFFFFB68, 0x00000299, 0x0000163F, 0xFFFFFB68, 0x00000299 },
+       { 0x0213EA94DE021904, 0x0000348D, 0xFFFFE9F7, 0x00000509, 0x000017A0, 0xFFFFFA59, 0x000002B6, 0x000017A0, 0xFFFFFA59, 0x000002B6 },
+       { 0x0213F0FE990610C4, 0x00003144, 0xFFFFEB23, 0x000004D9, 0x00001C9B, 0xFFFFF664, 0x00000351, 0x00001C9B, 0xFFFFF664, 0x00000351 },
+       { 0x0213EA94DE0620E4, 0x00002E95, 0xFFFFEE1A, 0x00000463, 0x00001707, 0xFFFFFAB7, 0x000002B3, 0x00001707, 0xFFFFFAB7, 0x000002B3 },
+       { 0x0213F0FD42D41864, 0x0000489C, 0xFFFFDA43, 0x000007AC, 0x00002866, 0xFFFFED6B, 0x000004D0, 0x00002866, 0xFFFFED6B, 0x000004D0 },
+       { 0x0213F0FE99161844, 0x00002895, 0xFFFFF10A, 0x0000040A, 0x000013E9, 0xFFFFFC9F, 0x0000026E, 0x000013E9, 0xFFFFFC9F, 0x0000026E },
+       { 0x0213F0FE99061964, 0x000033A0, 0xFFFFE9B1, 0x00000510, 0x00001D96, 0xFFFFF5AE, 0x0000036F, 0x00001D96, 0xFFFFF5AE, 0x0000036F },
+       { 0x0213F0FE99083984, 0x0000327C, 0xFFFFEAEA, 0x000004DD, 0x00001D45, 0xFFFFF649, 0x00000356, 0x00001D45, 0xFFFFF649, 0x00000356 },
+       { 0x0213EA94DE0248A4, 0x000031DF, 0xFFFFE9AB, 0x0000052F, 0x000019C8, 0xFFFFF7B7, 0x00000321, 0x000019C8, 0xFFFFF7B7, 0x00000321 },
+       { 0x0213F0FE991640A4, 0x00002BCC, 0xFFFFEEF4, 0x0000045C, 0x000015CD, 0xFFFFFB58, 0x0000029E, 0x000015CD, 0xFFFFFB58, 0x0000029E },
+       { 0x0213F0FE990638E4, 0x00003534, 0xFFFFEA10, 0x000004EB, 0x00001BB6, 0xFFFFF7B9, 0x00000314, 0x00001BB6, 0xFFFFF7B9, 0x00000314 },
+       { 0x0213F0FE99041984, 0x00002F4F, 0xFFFFEC35, 0x000004B9, 0x0000205D, 0xFFFFF47F, 0x00000392, 0x0000205D, 0xFFFFF47F, 0x00000392 },
+       { 0x0213F0FE990C20A4, 0x00003295, 0xFFFFEB1C, 0x000004D6, 0x000019C1, 0xFFFFF931, 0x000002D5, 0x000019C1, 0xFFFFF931, 0x000002D5 },
+       { 0x0213F0FE99024144, 0x00003557, 0xFFFFE7F7, 0x00000568, 0x00002342, 0xFFFFF1F9, 0x00000405, 0x00002342, 0xFFFFF1F9, 0x00000405 },
+       { 0x0213F0FE990450C4, 0x00003487, 0xFFFFE872, 0x0000055D, 0x000019D7, 0xFFFFF823, 0x0000030C, 0x000019D7, 0xFFFFF823, 0x0000030C },
+       { 0x0213F0FE992C3944, 0x0000378F, 0xFFFFE7A6, 0x00000566, 0x00001875, 0xFFFFFA04, 0x000002AF, 0x00001875, 0xFFFFFA04, 0x000002AF },
+       { 0x0213EA94DE0230E4, 0x00002A67, 0xFFFFF157, 0x000003DD, 0x000017BD, 0xFFFFFA53, 0x000002D1, 0x000017BD, 0xFFFFFA53, 0x000002D1 },
+       { 0x0213F0FD42D220E4, 0x000030B5, 0xFFFFEB32, 0x000004D9, 0x00002129, 0xFFFFF38A, 0x000003BB, 0x00002129, 0xFFFFF38A, 0x000003BB },
+       { 0x0213F0FE990610A4, 0x00003786, 0xFFFFE703, 0x00000584, 0x00001D63, 0xFFFFF5DC, 0x00000367, 0x00001D63, 0xFFFFF5DC, 0x00000367 },
+       { 0x0213F0FD42DA20C4, 0x0000346A, 0xFFFFE93E, 0x0000052C, 0x00001B27, 0xFFFFF79D, 0x0000031F, 0x00001B27, 0xFFFFF79D, 0x0000031F },
+       { 0x0213F0FE990E3024, 0x0000294E, 0xFFFFF0A5, 0x00000409, 0x00001928, 0xFFFFF93B, 0x000002E6, 0x00001928, 0xFFFFF93B, 0x000002E6 },
+       { 0x0213F0FD42D410C4, 0x00003E09, 0xFFFFE0FF, 0x00000694, 0x000025A0, 0xFFFFEF0F, 0x0000048F, 0x000025A0, 0xFFFFEF0F, 0x0000048F },
+       { 0x0213F0FE990A2964, 0x00003197, 0xFFFFEA06, 0x00000520, 0x00001B42, 0xFFFFF73B, 0x0000032A, 0x00001B42, 0xFFFFF73B, 0x0000032A },
+       { 0x0213F0FE99161864, 0x000022CB, 0xFFFFF3FC, 0x000003A3, 0x00001449, 0xFFFFFBD0, 0x00000297, 0x00001449, 0xFFFFFBD0, 0x00000297 },
+       { 0x0213F0FD42D82944, 0x00002A79, 0xFFFFEFD2, 0x00000433, 0x00001585, 0xFFFFFB92, 0x0000028E, 0x00001585, 0xFFFFFB92, 0x0000028E },
+       { 0x0213F0FE990C4184, 0x00003249, 0xFFFFEA92, 0x000004F4, 0x000019CB, 0xFFFFF8CF, 0x000002E1, 0x000019CB, 0xFFFFF8CF, 0x000002E1 },
+       { 0x0213EA94DE0218A4, 0x00002CEA, 0xFFFFEE46, 0x00000463, 0x00001A5E, 0xFFFFF83C, 0x0000030D, 0x00001A5E, 0xFFFFF83C, 0x0000030D },
+       { 0x0213F0FD42DC5144, 0x00003AE2, 0xFFFFE422, 0x00000600, 0x00001C65, 0xFFFFF62F, 0x0000034B, 0x00001C65, 0xFFFFF62F, 0x0000034B },
+       { 0x0213F0FE99181184, 0x000026A0, 0xFFFFF1C2, 0x000003F8, 0x000010E5, 0xFFFFFE56, 0x0000022A, 0x000010E5, 0xFFFFFE56, 0x0000022A },
+       { 0x0213F0FE992829A4, 0x00002A7B, 0xFFFFF063, 0x00000417, 0x000016FC, 0xFFFFFAD7, 0x000002B1, 0x000016FC, 0xFFFFFAD7, 0x000002B1 },
+       { 0x0213F0FE993210C4, 0x00003092, 0xFFFFEAB9, 0x00000507, 0x00001AE3, 0xFFFFF783, 0x00000323, 0x00001AE3, 0xFFFFF783, 0x00000323 },
+       { 0x0213F0FE990438E4, 0x00003265, 0xFFFFEBE8, 0x000004AA, 0x00001D65, 0xFFFFF73F, 0x00000321, 0x00001D65, 0xFFFFF73F, 0x00000321 },
+       { 0x0213EA94DE023084, 0x00002F14, 0xFFFFECC2, 0x000004A4, 0x00001A8D, 0xFFFFF7F3, 0x0000031D, 0x00001A8D, 0xFFFFF7F3, 0x0000031D },
+       { 0x0213F0FD42DC10E4, 0x000035FB, 0xFFFFE6D3, 0x000005AC, 0x00001B19, 0xFFFFF712, 0x00000338, 0x00001B19, 0xFFFFF712, 0x00000338 },
+       { 0x0213F0FD42DA2124, 0x00003519, 0xFFFFE8CC, 0x0000053A, 0x00001A0F, 0xFFFFF86E, 0x000002F5, 0x00001A0F, 0xFFFFF86E, 0x000002F5 },
+       { 0x0213F0FE992C2144, 0x0000364C, 0xFFFFE879, 0x00000541, 0x00001A42, 0xFFFFF8BA, 0x000002E2, 0x00001A42, 0xFFFFF8BA, 0x000002E2 },
+       { 0x0213EA94DE0218C4, 0x000029BA, 0xFFFFF09A, 0x00000408, 0x00001986, 0xFFFFF8D9, 0x000002FE, 0x00001986, 0xFFFFF8D9, 0x000002FE },
+       { 0x0213F0FD42DA38E4, 0x00003507, 0xFFFFE961, 0x00000518, 0x00001B79, 0xFFFFF775, 0x00000325, 0x00001B79, 0xFFFFF775, 0x00000325 },
+       { 0x0213F0FD42DC3184, 0x00003AD5, 0xFFFFE415, 0x00000613, 0x00001CB4, 0xFFFFF66D, 0x00000348, 0x00001CB4, 0xFFFFF66D, 0x00000348 },
+       { 0x0213F0FE991640E4, 0x000023D1, 0xFFFFF42B, 0x0000038F, 0x00001546, 0xFFFFFBA0, 0x0000029F, 0x00001546, 0xFFFFFBA0, 0x0000029F },
+       { 0x0213F0FE990A1924, 0x0000399E, 0xFFFFE518, 0x000005E7, 0x00001990, 0xFFFFF871, 0x000002FB, 0x00001990, 0xFFFFF871, 0x000002FB },
+       { 0x0213F0FD42D82964, 0x00002EDE, 0xFFFFEC93, 0x000004B8, 0x0000152C, 0xFFFFFBB3, 0x0000027E, 0x0000152C, 0xFFFFFBB3, 0x0000027E },
+       { 0x0213EA94DE042964, 0x00003140, 0xFFFFEBC9, 0x000004BB, 0x000016BE, 0xFFFFFB0A, 0x00000288, 0x000016BE, 0xFFFFFB0A, 0x00000288 },
+       { 0x0213F0FE99064064, 0x000030F6, 0xFFFFEB89, 0x000004CD, 0x0000185D, 0xFFFFF95A, 0x000002D9, 0x0000185D, 0xFFFFF95A, 0x000002D9 },
+       { 0x0213F0FE99023844, 0x0000389C, 0xFFFFE65A, 0x000005A2, 0x0000195D, 0xFFFFF8C8, 0x000002E8, 0x0000195D, 0xFFFFF8C8, 0x000002E8 },
+       { 0x0213F0FE99042104, 0x0000362B, 0xFFFFE9EC, 0x000004F6, 0x00001605, 0xFFFFFC1C, 0x00000263, 0x00001605, 0xFFFFFC1C, 0x00000263 },
+       { 0x0213F0FE992A1964, 0x00002946, 0xFFFFF04F, 0x00000426, 0x000015BA, 0xFFFFFB2F, 0x000002A3, 0x000015BA, 0xFFFFFB2F, 0x000002A3 },
+       { 0x0213F0FE99082184, 0x0000368E, 0xFFFFE837, 0x0000054A, 0x000017D7, 0xFFFFF9EB, 0x000002BA, 0x000017D7, 0xFFFFF9EB, 0x000002BA },
+       { 0x0213F0FD42DA2844, 0x00002E74, 0xFFFFEBE8, 0x000004DA, 0x00001DD6, 0xFFFFF57E, 0x00000379, 0x00001DD6, 0xFFFFF57E, 0x00000379 },
+       { 0x0213F0FE99041944, 0x0000322D, 0xFFFFEAA8, 0x000004F5, 0x00001B55, 0xFFFFF7DD, 0x0000030B, 0x00001B55, 0xFFFFF7DD, 0x0000030B },
+       { 0x0213F0FE99181904, 0x00002A29, 0xFFFFF07B, 0x00000416, 0x00001671, 0xFFFFFB3E, 0x0000029F, 0x00001671, 0xFFFFFB3E, 0x0000029F },
+       { 0x0213F0FD42DA2104, 0x000030F6, 0xFFFFEB89, 0x000004CD, 0x00001815, 0xFFFFF9AE, 0x000002C9, 0x00001815, 0xFFFFF9AE, 0x000002C9 },
+       { 0x0213F0FE990E10E4, 0x0000265F, 0xFFFFF1CB, 0x000003D5, 0x00001ED2, 0xFFFFF539, 0x0000037A, 0x00001ED2, 0xFFFFF539, 0x0000037A },
+       { 0x0213F0FE99162184, 0x000027A8, 0xFFFFF10D, 0x00000413, 0x000014B5, 0xFFFFFBA1, 0x00000299, 0x000014B5, 0xFFFFFBA1, 0x00000299 },
+       { 0x0213F0FE99043064, 0x00002CEE, 0xFFFFEDF6, 0x00000476, 0x00001A99, 0xFFFFF83E, 0x00000305, 0x00001A99, 0xFFFFF83E, 0x00000305 },
+       { 0x0213F0FE990640C4, 0x0000346C, 0xFFFFEA17, 0x000004EF, 0x00001D38, 0xFFFFF69F, 0x0000033D, 0x00001D38, 0xFFFFF69F, 0x0000033D },
+       { 0x0213F0FD42DA2944, 0x00002DBB, 0xFFFFED35, 0x00000490, 0x000018C1, 0xFFFFF930, 0x000002DA, 0x000018C1, 0xFFFFF930, 0x000002DA },
+       { 0x0213F0FE99042924, 0x000038DF, 0xFFFFE8A7, 0x0000051E, 0x00001B59, 0xFFFFF915, 0x000002D3, 0x00001B59, 0xFFFFF915, 0x000002D3 },
+       { 0x0213F0FE99080944, 0x00003384, 0xFFFFE979, 0x00000524, 0x00001AF3, 0xFFFFF74C, 0x0000032F, 0x00001AF3, 0xFFFFF74C, 0x0000032F },
+       { 0x0213F0FE99181864, 0x0000258B, 0xFFFFF2AE, 0x000003CB, 0x0000190C, 0xFFFFF93E, 0x000002EF, 0x0000190C, 0xFFFFF93E, 0x000002EF },
+       { 0x0213F0FE99103884, 0x000034F1, 0xFFFFE84B, 0x0000055E, 0x00001CB8, 0xFFFFF670, 0x0000034A, 0x00001CB8, 0xFFFFF670, 0x0000034A },
+       { 0x0213F0FE990C2104, 0x000030FB, 0xFFFFECD2, 0x00000488, 0x00001BF4, 0xFFFFF821, 0x00000302, 0x00001BF4, 0xFFFFF821, 0x00000302 },
+       { 0x0213F0FE99063044, 0x000036A6, 0xFFFFE815, 0x00000556, 0x000018FD, 0xFFFFF925, 0x000002DF, 0x000018FD, 0xFFFFF925, 0x000002DF },
+       { 0x0213EA94DE023044, 0x0000302A, 0xFFFFEB79, 0x000004E0, 0x00001C11, 0xFFFFF694, 0x00000358, 0x00001C11, 0xFFFFF694, 0x00000358 },
+       { 0x0213F0FE99181124, 0x00002555, 0xFFFFF2C4, 0x000003CB, 0x000017E3, 0xFFFFFA1F, 0x000002CB, 0x000017E3, 0xFFFFFA1F, 0x000002CB },
+       { 0x0213F0FE990A3164, 0x000032A3, 0xFFFFE933, 0x00000544, 0x000019D3, 0xFFFFF81A, 0x00000306, 0x000019D3, 0xFFFFF81A, 0x00000306 },
+       { 0x0213F0FD42D85104, 0x00002B91, 0xFFFFED81, 0x000004A9, 0x0000158B, 0xFFFFFAB9, 0x000002AC, 0x0000158B, 0xFFFFFAB9, 0x000002AC },
+       { 0x0213F0FE990E20C4, 0x00003537, 0xFFFFE912, 0x0000052C, 0x00001C8A, 0xFFFFF754, 0x0000031B, 0x00001C8A, 0xFFFFF754, 0x0000031B },
+       { 0x0213EA94DE063184, 0x000032E1, 0xFFFFEA5A, 0x000004F9, 0x000017B4, 0xFFFFF9D9, 0x000002C2, 0x000017B4, 0xFFFFF9D9, 0x000002C2 },
+       { 0x0213F0FD42D210C4, 0x00003B76, 0xFFFFE330, 0x00000636, 0x000026FB, 0xFFFFEF06, 0x00000481, 0x000026FB, 0xFFFFEF06, 0x00000481 },
+       { 0x0213F0FE99042144, 0x0000320C, 0xFFFFEB84, 0x000004C3, 0x00001A3A, 0xFFFFF8E9, 0x000002DF, 0x00001A3A, 0xFFFFF8E9, 0x000002DF },
+       { 0x0213F0FE99023984, 0x0000317D, 0xFFFFEA1F, 0x00000515, 0x00002100, 0xFFFFF31B, 0x000003DD, 0x00002100, 0xFFFFF31B, 0x000003DD },
+       { 0x0213F0FD42D43164, 0x00003DCB, 0xFFFFE0B4, 0x000006B4, 0x00002160, 0xFFFFF269, 0x000003F0, 0x00002160, 0xFFFFF269, 0x000003F0 },
+       { 0x0213F0FE991618C4, 0x00002737, 0xFFFFF218, 0x000003E1, 0x000015B5, 0xFFFFFB8F, 0x0000029C, 0x000015B5, 0xFFFFFB8F, 0x0000029C },
+       { 0x0213EA94DE023184, 0x0000318F, 0xFFFFEB3F, 0x000004D8, 0x00001938, 0xFFFFF8E9, 0x000002EB, 0x00001938, 0xFFFFF8E9, 0x000002EB },
+       { 0x0213F0FE991048C4, 0x000031BD, 0xFFFFE9DE, 0x00000527, 0x000018A7, 0xFFFFF8CA, 0x000002ED, 0x000018A7, 0xFFFFF8CA, 0x000002ED },
+       { 0x0213F0FD42DA3884, 0x00002F77, 0xFFFFEC2F, 0x000004B4, 0x00001D25, 0xFFFFF61B, 0x0000035D, 0x00001D25, 0xFFFFF61B, 0x0000035D },
+       { 0x0213F0FE990E4904, 0x00002CCA, 0xFFFFEDB3, 0x0000047C, 0x00001FBD, 0xFFFFF4A7, 0x00000391, 0x00001FBD, 0xFFFFF4A7, 0x00000391 },
+       { 0x0213F0FD42D438A4, 0x00003FF6, 0xFFFFE058, 0x000006A2, 0x000024CD, 0xFFFFF026, 0x00000452, 0x000024CD, 0xFFFFF026, 0x00000452 },
+       { 0x0213F0FE990A38E4, 0x00003161, 0xFFFFEAC8, 0x000004F3, 0x00001BB6, 0xFFFFF72A, 0x0000032B, 0x00001BB6, 0xFFFFF72A, 0x0000032B },
+       { 0x0213F0FD42D838A4, 0x00002EA0, 0xFFFFECA6, 0x000004B7, 0x000018C2, 0xFFFFF94E, 0x000002E1, 0x000018C2, 0xFFFFF94E, 0x000002E1 },
+       { 0x0213F0FE99182184, 0x00002F62, 0xFFFFEC9E, 0x000004B8, 0x00001531, 0xFFFFFBCD, 0x00000285, 0x00001531, 0xFFFFFBCD, 0x00000285 },
+       { 0x0213F0FE990440A4, 0x00003013, 0xFFFFEBD6, 0x000004C2, 0x00001B01, 0xFFFFF802, 0x000002FF, 0x00001B01, 0xFFFFF802, 0x000002FF },
+       { 0x0213F0FE99183064, 0x00002972, 0xFFFFF08D, 0x00000417, 0x00001A32, 0xFFFFF8A4, 0x00000305, 0x00001A32, 0xFFFFF8A4, 0x00000305 },
+       { 0x0213F0FD42D820E4, 0x00002E95, 0xFFFFED94, 0x00000487, 0x00001529, 0xFFFFFC26, 0x00000271, 0x00001529, 0xFFFFFC26, 0x00000271 },
+       { 0x0213F0FE990A1084, 0x00002D6A, 0xFFFFEC79, 0x000004C1, 0x00001AE2, 0xFFFFF725, 0x00000337, 0x00001AE2, 0xFFFFF725, 0x00000337 },
+       { 0x0213F0FE99021884, 0x000036B4, 0xFFFFE704, 0x00000591, 0x00001E7E, 0xFFFFF51C, 0x00000383, 0x00001E7E, 0xFFFFF51C, 0x00000383 },
+       { 0x0213F0FE99041844, 0x00002A6F, 0xFFFFEF70, 0x00000443, 0x00001BAA, 0xFFFFF752, 0x00000336, 0x00001BAA, 0xFFFFF752, 0x00000336 },
+       { 0x0213F0FE99183944, 0x00002C66, 0xFFFFEF5F, 0x0000043A, 0x000019F7, 0xFFFFF931, 0x000002EC, 0x000019F7, 0xFFFFF931, 0x000002EC },
+       { 0x0213EA94DE0631C4, 0x00003852, 0xFFFFE6AB, 0x00000590, 0x000019C1, 0xFFFFF8B1, 0x000002E5, 0x000019C1, 0xFFFFF8B1, 0x000002E5 },
+       { 0x0213F0FD42DA3124, 0x00003521, 0xFFFFE932, 0x00000523, 0x000018A9, 0xFFFFF96B, 0x000002D0, 0x000018A9, 0xFFFFF96B, 0x000002D0 },
+       { 0x0213F0FE99062164, 0x000031B9, 0xFFFFEB36, 0x000004D0, 0x00001D65, 0xFFFFF612, 0x0000035D, 0x00001D65, 0xFFFFF612, 0x0000035D },
+       { 0x0213F0FD42D41064, 0x00003ED0, 0xFFFFE135, 0x00000679, 0x00002351, 0xFFFFF0FE, 0x00000433, 0x00002351, 0xFFFFF0FE, 0x00000433 },
+       { 0x0213F0FE990A20E4, 0x000033ED, 0xFFFFE91A, 0x00000541, 0x00001C93, 0xFFFFF6A0, 0x0000034A, 0x00001C93, 0xFFFFF6A0, 0x0000034A },
+       { 0x0213EA94DE021844, 0x0000356F, 0xFFFFE8F7, 0x00000530, 0x000016BF, 0xFFFFFA85, 0x000002AB, 0x000016BF, 0xFFFFFA85, 0x000002AB },
+       { 0x0213F0FE991840E4, 0x00002304, 0xFFFFF4F3, 0x00000364, 0x000017CC, 0xFFFFFA41, 0x000002CA, 0x000017CC, 0xFFFFFA41, 0x000002CA },
+       { 0x0213F0FE99161164, 0x00002887, 0xFFFFEFD7, 0x00000450, 0x00001474, 0xFFFFFB94, 0x00000299, 0x00001474, 0xFFFFFB94, 0x00000299 },
+       { 0x0213F0FE99063064, 0x00003D0B, 0xFFFFE416, 0x000005EF, 0x00001C7E, 0xFFFFF71D, 0x00000325, 0x00001C7E, 0xFFFFF71D, 0x00000325 },
+       { 0x0213F0FE990810E4, 0x00003185, 0xFFFFEAFA, 0x000004E4, 0x00001A12, 0xFFFFF83C, 0x00000303, 0x00001A12, 0xFFFFF83C, 0x00000303 },
+       { 0x0213F0FE990A1944, 0x00003032, 0xFFFFEAE6, 0x000004FC, 0x00001B2A, 0xFFFFF73F, 0x0000032B, 0x00001B2A, 0xFFFFF73F, 0x0000032B },
+       { 0x0213F0FD42D838C4, 0x00002691, 0xFFFFF22D, 0x000003D6, 0x00001700, 0xFFFFFA6E, 0x000002C0, 0x00001700, 0xFFFFFA6E, 0x000002C0 },
+       { 0x0213F0FE990218A4, 0x00002B2F, 0xFFFFEEC4, 0x0000044B, 0x0000215F, 0xFFFFF33F, 0x000003D2, 0x0000215F, 0xFFFFF33F, 0x000003D2 },
+       { 0x0213F0FE990A4184, 0x000034AA, 0xFFFFE706, 0x000005B1, 0x00001B28, 0xFFFFF6B5, 0x00000349, 0x00001B28, 0xFFFFF6B5, 0x00000349 },
+       { 0x0213F0FD42DA2964, 0x0000307E, 0xFFFFEB38, 0x000004E6, 0x00001A22, 0xFFFFF83F, 0x00000300, 0x00001A22, 0xFFFFF83F, 0x00000300 },
+       { 0x0213F0FE990618A4, 0x000038D6, 0xFFFFE6D8, 0x0000057C, 0x00001B24, 0xFFFFF7E4, 0x00000307, 0x00001B24, 0xFFFFF7E4, 0x00000307 },
+       { 0x0213F0FE99183044, 0x00002757, 0xFFFFF1E8, 0x000003DD, 0x000017F5, 0xFFFFFA15, 0x000002C8, 0x000017F5, 0xFFFFFA15, 0x000002C8 },
+       { 0x0213F0FE99083184, 0x000031FC, 0xFFFFEB3E, 0x000004CE, 0x00001B4C, 0xFFFFF7AD, 0x00000319, 0x00001B4C, 0xFFFFF7AD, 0x00000319 },
+       { 0x0213F0FE99301864, 0x00002933, 0xFFFFF073, 0x0000040E, 0x00001C3C, 0xFFFFF701, 0x0000033C, 0x00001C3C, 0xFFFFF701, 0x0000033C },
+       { 0x0213F0FD42D218A4, 0x000040BB, 0xFFFFE066, 0x0000069A, 0x0000257F, 0xFFFFF08A, 0x00000435, 0x0000257F, 0xFFFFF08A, 0x00000435 },
+       { 0x0213F0FE991010A4, 0x0000305B, 0xFFFFEB9B, 0x000004CB, 0x00001996, 0xFFFFF846, 0x00000308, 0x00001996, 0xFFFFF846, 0x00000308 },
+       { 0x0213F0FE99064884, 0x000039C0, 0xFFFFE5D3, 0x000005B0, 0x00001A8D, 0xFFFFF7DA, 0x00000313, 0x00001A8D, 0xFFFFF7DA, 0x00000313 },
+       { 0x0213EA94DE0210A4, 0x00002E23, 0xFFFFED3F, 0x0000048F, 0x0000189D, 0xFFFFF94C, 0x000002DE, 0x0000189D, 0xFFFFF94C, 0x000002DE },
+       { 0x0213EA94DE021984, 0x0000332B, 0xFFFFE9F1, 0x00000516, 0x000018E6, 0xFFFFF8FE, 0x000002EC, 0x000018E6, 0xFFFFF8FE, 0x000002EC },
+       { 0x0213F0FE990838C4, 0x000034A0, 0xFFFFEA44, 0x000004E4, 0x00001ECD, 0xFFFFF5B4, 0x00000364, 0x00001ECD, 0xFFFFF5B4, 0x00000364 },
+       { 0x0213F0FD42D24104, 0x0000448C, 0xFFFFDF34, 0x000006A8, 0x0000231C, 0xFFFFF286, 0x000003D9, 0x0000231C, 0xFFFFF286, 0x000003D9 },
+       { 0x0213EA94DE062144, 0x00002D8C, 0xFFFFEE65, 0x00000456, 0x000018B1, 0xFFFFF9C8, 0x000002C8, 0x000018B1, 0xFFFFF9C8, 0x000002C8 },
+       { 0x0213F0FE99061904, 0x00003527, 0xFFFFE9BF, 0x000004FD, 0x00001D23, 0xFFFFF69F, 0x00000342, 0x00001D23, 0xFFFFF69F, 0x00000342 },
+       { 0x0213F0FD42DC38A4, 0x00002C51, 0xFFFFEDC3, 0x00000483, 0x00001BE0, 0xFFFFF720, 0x0000032D, 0x00001BE0, 0xFFFFF720, 0x0000032D },
+       { 0x0213F0FE990A3044, 0x00002C6C, 0xFFFFECEB, 0x000004B7, 0x00001C86, 0xFFFFF5E7, 0x00000371, 0x00001C86, 0xFFFFF5E7, 0x00000371 },
+       { 0x0213F0FE99045144, 0x000037CF, 0xFFFFE6BE, 0x00000599, 0x000018CD, 0xFFFFF967, 0x000002C7, 0x000018CD, 0xFFFFF967, 0x000002C7 },
+       { 0x0213F0FE99103164, 0x00002E6F, 0xFFFFED1D, 0x0000048E, 0x00001ADC, 0xFFFFF7F4, 0x0000030E, 0x00001ADC, 0xFFFFF7F4, 0x0000030E },
+       { 0x0213F0FD42D42984, 0x00003FF3, 0xFFFFDF13, 0x000006F9, 0x000025BF, 0xFFFFEEEE, 0x00000497, 0x000025BF, 0xFFFFEEEE, 0x00000497 },
+       { 0x0213F0FD42DC5104, 0x00004135, 0xFFFFDF97, 0x000006CC, 0x00001D52, 0xFFFFF541, 0x00000383, 0x00001D52, 0xFFFFF541, 0x00000383 },
+       { 0x0213F0FD42DC20E4, 0x00002EA9, 0xFFFFEDDB, 0x0000045F, 0x0000197C, 0xFFFFF8E1, 0x000002F0, 0x0000197C, 0xFFFFF8E1, 0x000002F0 },
+       { 0x0213EA94DE043084, 0x0000345C, 0xFFFFE922, 0x00000532, 0x00001922, 0xFFFFF8C7, 0x000002F1, 0x00001922, 0xFFFFF8C7, 0x000002F1 },
+       { 0x0213F0FE99064124, 0x000035C4, 0xFFFFE8FE, 0x00000521, 0x00001C87, 0xFFFFF6F3, 0x00000330, 0x00001C87, 0xFFFFF6F3, 0x00000330 },
+       { 0x0213F0FD42D83164, 0x00002888, 0xFFFFF08A, 0x0000041E, 0x0000150F, 0xFFFFFB87, 0x00000291, 0x0000150F, 0xFFFFFB87, 0x00000291 },
+       { 0x0213F0FE990A1124, 0x000035E9, 0xFFFFE657, 0x000005CC, 0x00001BD6, 0xFFFFF664, 0x00000355, 0x00001BD6, 0xFFFFF664, 0x00000355 },
+       { 0x0213F0FE991648E4, 0x00002F94, 0xFFFFEBD0, 0x000004E5, 0x00001333, 0xFFFFFCA7, 0x00000266, 0x00001333, 0xFFFFFCA7, 0x00000266 },
+       { 0x0213F0FE99181964, 0x000029E7, 0xFFFFF009, 0x00000433, 0x0000144A, 0xFFFFFC37, 0x0000027D, 0x0000144A, 0xFFFFFC37, 0x0000027D },
+       { 0x0213F0FE992C1944, 0x00003418, 0xFFFFE979, 0x00000521, 0x00001D33, 0xFFFFF66B, 0x0000034A, 0x00001D33, 0xFFFFF66B, 0x0000034A },
+       { 0x0213EA94DE0440E4, 0x00003656, 0xFFFFE79D, 0x0000057A, 0x000017C2, 0xFFFFF992, 0x000002D4, 0x000017C2, 0xFFFFF992, 0x000002D4 },
+       { 0x0213F0FE990C40C4, 0x00002EB2, 0xFFFFECFE, 0x00000493, 0x00001F2A, 0xFFFFF543, 0x0000037B, 0x00001F2A, 0xFFFFF543, 0x0000037B },
+       { 0x0213F0FE99021124, 0x00002FC1, 0xFFFFEB3F, 0x000004E8, 0x00001CD0, 0xFFFFF5F7, 0x00000364, 0x00001CD0, 0xFFFFF5F7, 0x00000364 },
+       { 0x0213F0FE990C1124, 0x0000307B, 0xFFFFEB66, 0x000004DE, 0x00001953, 0xFFFFF8ED, 0x000002E4, 0x00001953, 0xFFFFF8ED, 0x000002E4 },
+       { 0x0213F0FD42DA1884, 0x00002CAA, 0xFFFFED07, 0x000004AC, 0x0000251C, 0xFFFFF086, 0x0000044D, 0x0000251C, 0xFFFFF086, 0x0000044D },
+       { 0x0213EA94DE043944, 0x00002C94, 0xFFFFEE5F, 0x0000045B, 0x000018D7, 0xFFFFF900, 0x000002EB, 0x000018D7, 0xFFFFF900, 0x000002EB },
+       { 0x0213F0FE99021864, 0x000031F1, 0xFFFFE9BE, 0x0000052E, 0x00001DDF, 0xFFFFF558, 0x00000380, 0x00001DDF, 0xFFFFF558, 0x00000380 },
+       { 0x0213F0FE990E50C4, 0x00002603, 0xFFFFF1E9, 0x000003DA, 0x00001B37, 0xFFFFF75A, 0x0000032F, 0x00001B37, 0xFFFFF75A, 0x0000032F },
+       { 0x0213F0FD42DA3044, 0x00003992, 0xFFFFE4F9, 0x000005EB, 0x00001775, 0xFFFFF9B8, 0x000002C2, 0x00001775, 0xFFFFF9B8, 0x000002C2 },
+       { 0x0213F0FE99184964, 0x000029DA, 0xFFFFF052, 0x0000041F, 0x000016E2, 0xFFFFFA99, 0x000002BB, 0x000016E2, 0xFFFFFA99, 0x000002BB },
+       { 0x0213F0FE99101064, 0x00002FF2, 0xFFFFEB8F, 0x000004DF, 0x00001AF6, 0xFFFFF7A1, 0x00000321, 0x00001AF6, 0xFFFFF7A1, 0x00000321 },
+       { 0x0213F0FE991608E4, 0x00002590, 0xFFFFF222, 0x000003EE, 0x0000130B, 0xFFFFFCC9, 0x00000268, 0x0000130B, 0xFFFFFCC9, 0x00000268 },
+       { 0x0213F0FE99024064, 0x000038A2, 0xFFFFE65F, 0x000005A2, 0x000018B1, 0xFFFFF917, 0x000002E1, 0x000018B1, 0xFFFFF917, 0x000002E1 },
+       { 0x0213F0FD42DC48E4, 0x000035FD, 0xFFFFE73C, 0x0000058D, 0x00001BB3, 0xFFFFF6E1, 0x00000337, 0x00001BB3, 0xFFFFF6E1, 0x00000337 },
+       { 0x0213F0FE991038C4, 0x00002AB7, 0xFFFFEF98, 0x00000429, 0x00001F35, 0xFFFFF539, 0x0000037C, 0x00001F35, 0xFFFFF539, 0x0000037C },
+       { 0x0213F0FE990A0944, 0x000034BA, 0xFFFFE73D, 0x000005A6, 0x000018A6, 0xFFFFF888, 0x000002FB, 0x000018A6, 0xFFFFF888, 0x000002FB },
+       { 0x0213F0FE99063844, 0x000032EA, 0xFFFFEA78, 0x000004F4, 0x00001AB6, 0xFFFFF812, 0x00000308, 0x00001AB6, 0xFFFFF812, 0x00000308 },
+       { 0x0213F0FE990C3044, 0x00002BE9, 0xFFFFEE9A, 0x00000457, 0x00001942, 0xFFFFF8D2, 0x000002F2, 0x00001942, 0xFFFFF8D2, 0x000002F2 },
+       { 0x0213F0FE99105124, 0x00002FAB, 0xFFFFEB76, 0x000004E1, 0x00001DCA, 0xFFFFF57D, 0x00000378, 0x00001DCA, 0xFFFFF57D, 0x00000378 },
+       { 0x0213F0FE992E2844, 0x0000330A, 0xFFFFE9E1, 0x0000051B, 0x00001CC4, 0xFFFFF6DF, 0x00000335, 0x00001CC4, 0xFFFFF6DF, 0x00000335 },
+       { 0x0213F0FE991828A4, 0x000027D8, 0xFFFFF276, 0x000003BF, 0x0000178A, 0xFFFFFABF, 0x000002B5, 0x0000178A, 0xFFFFFABF, 0x000002B5 },
+       { 0x0213F0FD42DC3864, 0x0000340A, 0xFFFFE86D, 0x00000562, 0x00001B85, 0xFFFFF719, 0x0000032F, 0x00001B85, 0xFFFFF719, 0x0000032F },
+       { 0x0213EA94DE063084, 0x00003879, 0xFFFFE73F, 0x00000578, 0x0000161C, 0xFFFFFB6B, 0x00000281, 0x0000161C, 0xFFFFFB6B, 0x00000281 },
+       { 0x0213F0FE99184064, 0x00002879, 0xFFFFF0F8, 0x0000040A, 0x00001749, 0xFFFFFA37, 0x000002CC, 0x00001749, 0xFFFFFA37, 0x000002CC },
+       { 0x0213F0FE99043964, 0x00002C3A, 0xFFFFEEA0, 0x0000044F, 0x00001D57, 0xFFFFF6C2, 0x00000332, 0x00001D57, 0xFFFFF6C2, 0x00000332 },
+       { 0x0213EA94DE021964, 0x000035BB, 0xFFFFE90D, 0x0000052A, 0x000017D9, 0xFFFFF9F5, 0x000002C3, 0x000017D9, 0xFFFFF9F5, 0x000002C3 },
+       { 0x0213EA94DE041124, 0x000031F1, 0xFFFFEAD4, 0x000004ED, 0x00001F10, 0xFFFFF539, 0x0000037D, 0x00001F10, 0xFFFFF539, 0x0000037D },
+       { 0x0213F0FE99102824, 0x00002A1A, 0xFFFFEFAD, 0x00000430, 0x00001D47, 0xFFFFF62F, 0x0000035E, 0x00001D47, 0xFFFFF62F, 0x0000035E },
+       { 0x0213F0FE99164924, 0x00002AF0, 0xFFFFEEDC, 0x00000465, 0x0000145F, 0xFFFFFBEB, 0x00000281, 0x0000145F, 0xFFFFFBEB, 0x00000281 },
+       { 0x0213F0FE99183164, 0x00002657, 0xFFFFF2E0, 0x000003B6, 0x00001664, 0xFFFFFB37, 0x000002A2, 0x00001664, 0xFFFFFB37, 0x000002A2 },
+       { 0x0213F0FD42D03864, 0x00003183, 0xFFFFE9F1, 0x0000052B, 0x00002020, 0xFFFFF3CE, 0x000003C1, 0x00002020, 0xFFFFF3CE, 0x000003C1 },
+       { 0x0213F0FD42C628E4, 0x00003240, 0xFFFFEB65, 0x000004C7, 0x00002425, 0xFFFFF245, 0x000003F3, 0x00002425, 0xFFFFF245, 0x000003F3 },
+       { 0x0213EA94DE321104, 0x000023D0, 0xFFFFF400, 0x00000397, 0x00001345, 0xFFFFFD6B, 0x00000241, 0x00001345, 0xFFFFFD6B, 0x00000241 },
+       { 0x0213F0FD42CE38A4, 0x00003440, 0xFFFFE872, 0x0000055B, 0x00002247, 0xFFFFF296, 0x000003E8, 0x00002247, 0xFFFFF296, 0x000003E8 },
+       { 0x0213F0FD42D04904, 0x00003275, 0xFFFFE970, 0x00000538, 0x00001F94, 0xFFFFF429, 0x000003AD, 0x00001F94, 0xFFFFF429, 0x000003AD },
+       { 0x0213F0FD42C640A4, 0x00003918, 0xFFFFE5DA, 0x000005B6, 0x000024FC, 0xFFFFF106, 0x00000426, 0x000024FC, 0xFFFFF106, 0x00000426 },
+       { 0x0213EA94DE062044, 0x0000334B, 0xFFFFEA39, 0x000004FD, 0x00001983, 0xFFFFF8F6, 0x000002E2, 0x00001983, 0xFFFFF8F6, 0x000002E2 },
+       { 0x0213F0FD42C64984, 0x00003B59, 0xFFFFE4D0, 0x000005DA, 0x00002605, 0xFFFFF090, 0x00000439, 0x00002605, 0xFFFFF090, 0x00000439 },
+       { 0x0213F0FD42D03124, 0x00003251, 0xFFFFEA46, 0x00000511, 0x00002781, 0xFFFFEF84, 0x00000470, 0x00002781, 0xFFFFEF84, 0x00000470 },
+       { 0x0213F0FD42CA3164, 0x00003304, 0xFFFFE926, 0x00000542, 0x00001EE9, 0xFFFFF4E4, 0x0000038B, 0x00001EE9, 0xFFFFF4E4, 0x0000038B },
+       { 0x0213F0FD42CC38C4, 0x00002F4C, 0xFFFFEC0C, 0x000004C4, 0x00001E49, 0xFFFFF578, 0x00000374, 0x00001E49, 0xFFFFF578, 0x00000374 },
+       { 0x0213EA94DE1C2164, 0x00002034, 0xFFFFF692, 0x0000034C, 0x000014B8, 0xFFFFFC5B, 0x00000294, 0x000014B8, 0xFFFFFC5B, 0x00000294 },
+       { 0x0213F0FD42CE4924, 0x0000385F, 0xFFFFE513, 0x000005F3, 0x000024E7, 0xFFFFF053, 0x00000450, 0x000024E7, 0xFFFFF053, 0x00000450 },
+       { 0x0213EA94DE1C40E4, 0x00001D70, 0xFFFFF821, 0x0000030F, 0x00001541, 0xFFFFFBB4, 0x000002B0, 0x00001541, 0xFFFFFBB4, 0x000002B0 },
+       { 0x0213F0FD42D02084, 0x000034EB, 0xFFFFE7FF, 0x00000575, 0x000019B4, 0xFFFFF836, 0x00000308, 0x000019B4, 0xFFFFF836, 0x00000308 },
+       { 0x0213F0FD42D050E4, 0x000037C9, 0xFFFFE5D4, 0x000005CD, 0x000026A1, 0xFFFFEF0C, 0x00000491, 0x000026A1, 0xFFFFEF0C, 0x00000491 },
+       { 0x0213EA94DE121944, 0x00002918, 0xFFFFF148, 0x000003E9, 0x00001A49, 0xFFFFF94C, 0x000002CF, 0x00001A49, 0xFFFFF94C, 0x000002CF },
+       { 0x0213F0FD42CA4064, 0x00002F90, 0xFFFFEAB5, 0x00000514, 0x00001707, 0xFFFFF9C7, 0x000002C4, 0x00001707, 0xFFFFF9C7, 0x000002C4 },
+       { 0x0213EA94DE062064, 0x0000327E, 0xFFFFEA99, 0x000004F4, 0x0000194F, 0xFFFFF929, 0x000002DC, 0x0000194F, 0xFFFFF929, 0x000002DC },
+       { 0x0213F0FD42C64084, 0x0000326F, 0xFFFFE9CF, 0x00000519, 0x00002240, 0xFFFFF299, 0x000003E7, 0x00002240, 0xFFFFF299, 0x000003E7 },
+       { 0x0213EA94DE321124, 0x000022FB, 0xFFFFF4C6, 0x00000371, 0x00001506, 0xFFFFFC73, 0x00000265, 0x00001506, 0xFFFFFC73, 0x00000265 },
+       { 0x0213F0FD42CA3924, 0x00003AD6, 0xFFFFE470, 0x000005FE, 0x00001F03, 0xFFFFF4F3, 0x00000387, 0x00001F03, 0xFFFFF4F3, 0x00000387 },
+       { 0x0213EA94DE201124, 0x00001F11, 0xFFFFF756, 0x00000332, 0x00001666, 0xFFFFFB8A, 0x000002B2, 0x00001666, 0xFFFFFB8A, 0x000002B2 },
+       { 0x0213EA94DE0238A4, 0x00002A5F, 0xFFFFEFA7, 0x00000430, 0x00001943, 0xFFFFF8C6, 0x000002F7, 0x00001943, 0xFFFFF8C6, 0x000002F7 },
+       { 0x0213EA94DE1650E4, 0x0000235E, 0xFFFFF3B4, 0x000003B3, 0x00001489, 0xFFFFFBCF, 0x0000029B, 0x00001489, 0xFFFFFBCF, 0x0000029B },
+       { 0x0213F0FD42CC38A4, 0x00003570, 0xFFFFE780, 0x0000058D, 0x00001B1D, 0xFFFFF767, 0x00000325, 0x00001B1D, 0xFFFFF767, 0x00000325 },
+       { 0x0213EA94DE042064, 0x00003678, 0xFFFFE7C3, 0x00000569, 0x00001831, 0xFFFFF98E, 0x000002C8, 0x00001831, 0xFFFFF98E, 0x000002C8 },
+       { 0x0213EA94DE201864, 0x000020B9, 0xFFFFF625, 0x0000035A, 0x000015C5, 0xFFFFFB8A, 0x000002B5, 0x000015C5, 0xFFFFFB8A, 0x000002B5 },
+       { 0x0213F0FD42C63184, 0x00003985, 0xFFFFE529, 0x000005DD, 0x00002165, 0xFFFFF351, 0x000003C5, 0x00002165, 0xFFFFF351, 0x000003C5 },
+       { 0x0213F0FD42D02064, 0x0000322A, 0xFFFFE99D, 0x00000535, 0x000019A1, 0xFFFFF844, 0x00000305, 0x000019A1, 0xFFFFF844, 0x00000305 },
+       { 0x0213F0FD42D05104, 0x000033ED, 0xFFFFE834, 0x00000571, 0x00002094, 0xFFFFF33A, 0x000003DB, 0x00002094, 0xFFFFF33A, 0x000003DB },
+       { 0x0213EA94DE2040C4, 0x00001D10, 0xFFFFF84D, 0x0000030B, 0x00001659, 0xFFFFFB0A, 0x000002CB, 0x00001659, 0xFFFFFB0A, 0x000002CB },
+       { 0x0213EA94DE1C1124, 0x0000210F, 0xFFFFF644, 0x00000355, 0x00001A4A, 0xFFFFF90F, 0x00000310, 0x00001A4A, 0xFFFFF90F, 0x00000310 },
+       { 0x0213EA94DE164164, 0x00001CA8, 0xFFFFF813, 0x00000316, 0x00001440, 0xFFFFFC1C, 0x0000029D, 0x00001440, 0xFFFFFC1C, 0x0000029D },
+       { 0x0213EA94DE3210C4, 0x00002864, 0xFFFFF15A, 0x000003FA, 0x0000137F, 0xFFFFFD43, 0x00000248, 0x0000137F, 0xFFFFFD43, 0x00000248 },
+       { 0x0213F0FD42D04184, 0x00002CDB, 0xFFFFECFD, 0x000004A7, 0x00002472, 0xFFFFF0E1, 0x00000437, 0x00002472, 0xFFFFF0E1, 0x00000437 },
+       { 0x0213F0FD42CC5104, 0x00003348, 0xFFFFE8CA, 0x00000554, 0x00001E91, 0xFFFFF4D4, 0x00000392, 0x00001E91, 0xFFFFF4D4, 0x00000392 },
+       { 0x0213F0FD42C64944, 0x00003989, 0xFFFFE4BB, 0x000005F8, 0x00001ACB, 0xFFFFF780, 0x00000319, 0x00001ACB, 0xFFFFF780, 0x00000319 },
+       { 0x0213F0FD42CA2104, 0x00003238, 0xFFFFEA09, 0x0000051E, 0x00001F08, 0xFFFFF4F4, 0x0000038C, 0x00001F08, 0xFFFFF4F4, 0x0000038C },
+       { 0x0213EA94DE120904, 0x00002453, 0xFFFFF3B0, 0x0000038D, 0x00001AED, 0xFFFFF8A2, 0x000002EA, 0x00001AED, 0xFFFFF8A2, 0x000002EA },
+       { 0x0213EA94DE1C3024, 0x00002459, 0xFFFFF409, 0x000003A8, 0x000017B5, 0xFFFFFA53, 0x000002E1, 0x000017B5, 0xFFFFFA53, 0x000002E1 },
+       { 0x0213EA94DE021184, 0x0000310D, 0xFFFFEB78, 0x000004D0, 0x00001DC9, 0xFFFFF5D5, 0x00000368, 0x00001DC9, 0xFFFFF5D5, 0x00000368 },
+       { 0x0213EA94DE023104, 0x000031BF, 0xFFFFECA3, 0x00000498, 0x00001DC9, 0xFFFFF717, 0x00000336, 0x00001DC9, 0xFFFFF717, 0x00000336 },
+       { 0x0213F0FD42CE2104, 0x00003896, 0xFFFFE5DD, 0x000005C5, 0x000023E2, 0xFFFFF1A1, 0x00000416, 0x000023E2, 0xFFFFF1A1, 0x00000416 },
+       { 0x0213EA94DE323904, 0x000023CB, 0xFFFFF4C8, 0x00000372, 0x00001C33, 0xFFFFF7D5, 0x0000032A, 0x00001C33, 0xFFFFF7D5, 0x0000032A },
+       { 0x0213F0FD42D020C4, 0x00002F6B, 0xFFFFEBF0, 0x000004CE, 0x00001C89, 0xFFFFF689, 0x0000034D, 0x00001C89, 0xFFFFF689, 0x0000034D },
+       { 0x0213F0FD42CE3904, 0x00003E72, 0xFFFFE211, 0x0000065D, 0x0000218D, 0xFFFFF309, 0x000003DC, 0x0000218D, 0xFFFFF309, 0x000003DC },
+       { 0x0213EA94DE022084, 0x00002612, 0xFFFFF2C3, 0x000003AD, 0x000019F7, 0xFFFFF891, 0x000002FE, 0x000019F7, 0xFFFFF891, 0x000002FE },
+       { 0x0213EA94DE164184, 0x0000205D, 0xFFFFF59F, 0x00000372, 0x000012E6, 0xFFFFFD0A, 0x00000270, 0x000012E6, 0xFFFFFD0A, 0x00000270 },
+       { 0x0213F0FD42CA2124, 0x00002ECB, 0xFFFFEC47, 0x000004BD, 0x00001936, 0xFFFFF8D9, 0x000002E4, 0x00001936, 0xFFFFF8D9, 0x000002E4 },
+       { 0x0213EA94DE064904, 0x00002BDB, 0xFFFFEE6D, 0x00000458, 0x00001852, 0xFFFFF943, 0x000002D9, 0x00001852, 0xFFFFF943, 0x000002D9 },
+       { 0x0213EA94DE124904, 0x00003387, 0xFFFFE958, 0x00000534, 0x00001932, 0xFFFFF8FA, 0x000002E4, 0x00001932, 0xFFFFF8FA, 0x000002E4 },
+       { 0x0213EA94DE0208C4, 0x00002E3C, 0xFFFFED26, 0x00000495, 0x00001858, 0xFFFFF990, 0x000002D1, 0x00001858, 0xFFFFF990, 0x000002D1 },
+       { 0x0213EA94DE022964, 0x000033B8, 0xFFFFEA5C, 0x000004F9, 0x00001BD1, 0xFFFFF76A, 0x0000032E, 0x00001BD1, 0xFFFFF76A, 0x0000032E },
+       { 0x0213EA94DE062984, 0x00002BCE, 0xFFFFEEE9, 0x00000443, 0x00001982, 0xFFFFF90D, 0x000002DF, 0x00001982, 0xFFFFF90D, 0x000002DF },
+       { 0x0213F0FD42D048E4, 0x00003495, 0xFFFFE7D9, 0x0000057B, 0x00001D2A, 0xFFFFF5A5, 0x00000372, 0x00001D2A, 0xFFFFF5A5, 0x00000372 },
+       { 0x0213F0FD42CA38E4, 0x000034B1, 0xFFFFE88D, 0x00000556, 0x00002014, 0xFFFFF43A, 0x000003AA, 0x00002014, 0xFFFFF43A, 0x000003AA },
+       { 0x0213F0FD42CC3124, 0x00002F96, 0xFFFFEC84, 0x000004AD, 0x000024A2, 0xFFFFF1CE, 0x0000040A, 0x000024A2, 0xFFFFF1CE, 0x0000040A },
+       { 0x0213EA94DE161064, 0x0000203B, 0xFFFFF640, 0x00000359, 0x000014EC, 0xFFFFFC14, 0x0000029C, 0x000014EC, 0xFFFFFC14, 0x0000029C },
+       { 0x0213F0FD42D02984, 0x000034E2, 0xFFFFE7B8, 0x00000582, 0x00001938, 0xFFFFF872, 0x000002FA, 0x00001938, 0xFFFFF872, 0x000002FA },
+       { 0x0213EA94DE063124, 0x00002AC7, 0xFFFFF0C1, 0x000003F5, 0x00002268, 0xFFFFF39C, 0x000003C9, 0x00002268, 0xFFFFF39C, 0x000003C9 },
+       { 0x0213F0FD42C63144, 0x000036F6, 0xFFFFE77F, 0x00000571, 0x000027D9, 0xFFFFEF6F, 0x00000461, 0x000027D9, 0xFFFFEF6F, 0x00000461 },
+       { 0x0213EA94DE123124, 0x00002BAB, 0xFFFFF018, 0x00000419, 0x00002126, 0xFFFFF4E2, 0x0000038F, 0x00002126, 0xFFFFF4E2, 0x0000038F },
+       { 0x0213EA94DE323924, 0x000028C4, 0xFFFFF161, 0x000003F8, 0x0000180C, 0xFFFFFA4B, 0x000002C8, 0x0000180C, 0xFFFFFA4B, 0x000002C8 },
+       { 0x0213F0FD42CA2864, 0x00002F48, 0xFFFFEB62, 0x000004EE, 0x00001912, 0xFFFFF8C8, 0x000002EA, 0x00001912, 0xFFFFF8C8, 0x000002EA },
+       { 0x0213F0FD42CE2864, 0x000032DF, 0xFFFFE911, 0x00000545, 0x00001F06, 0xFFFFF485, 0x0000039C, 0x00001F06, 0xFFFFF485, 0x0000039C },
+       { 0x0213F0FD42D04144, 0x000035B8, 0xFFFFE74F, 0x00000590, 0x00001FD7, 0xFFFFF410, 0x000003AF, 0x00001FD7, 0xFFFFF410, 0x000003AF },
+       { 0x0213F0FD42D050C4, 0x00003608, 0xFFFFE6D7, 0x000005A9, 0x000024A6, 0xFFFFF075, 0x00000450, 0x000024A6, 0xFFFFF075, 0x00000450 },
+       { 0x0213F0FD42CA3884, 0x000030AB, 0xFFFFEAED, 0x000004F5, 0x000019EE, 0xFFFFF84E, 0x000002FC, 0x000019EE, 0xFFFFF84E, 0x000002FC },
+       { 0x0213EA94DE0620C4, 0x000030C6, 0xFFFFEC92, 0x0000049E, 0x000019BB, 0xFFFFF8F1, 0x000002F3, 0x000019BB, 0xFFFFF8F1, 0x000002F3 },
+       { 0x0213F0FD42C630A4, 0x00003B27, 0xFFFFE544, 0x000005C1, 0x00002697, 0xFFFFF072, 0x00000438, 0x00002697, 0xFFFFF072, 0x00000438 },
+       { 0x0213EA94DE1248E4, 0x00002F23, 0xFFFFEC48, 0x000004B9, 0x0000199A, 0xFFFFF8CF, 0x000002E9, 0x0000199A, 0xFFFFF8CF, 0x000002E9 },
+       { 0x0213EA94DE0629A4, 0x00002BD7, 0xFFFFEEAC, 0x00000450, 0x00001991, 0xFFFFF8F4, 0x000002E2, 0x00001991, 0xFFFFF8F4, 0x000002E2 },
+       { 0x0213EA94DE022024, 0x00003210, 0xFFFFEB24, 0x000004DE, 0x00001BDF, 0xFFFFF744, 0x00000333, 0x00001BDF, 0xFFFFF744, 0x00000333 },
+       { 0x0213EA94DE244144, 0x00002DDC, 0xFFFFED0D, 0x000004AC, 0x000019D0, 0xFFFFF869, 0x0000030F, 0x000019D0, 0xFFFFF869, 0x0000030F },
+       { 0x0213EA94DE203964, 0x000023E6, 0xFFFFF40C, 0x000003A9, 0x000014EB, 0xFFFFFBC4, 0x000002AF, 0x000014EB, 0xFFFFFBC4, 0x000002AF },
+       { 0x0213F0FD42CA29A4, 0x000030CE, 0xFFFFE9A5, 0x0000053C, 0x00001C45, 0xFFFFF60E, 0x0000035D, 0x00001C45, 0xFFFFF60E, 0x0000035D },
+       { 0x0213EA94DE161084, 0x00001E89, 0xFFFFF73A, 0x00000337, 0x0000157C, 0xFFFFFBC0, 0x000002AA, 0x0000157C, 0xFFFFFBC0, 0x000002AA },
+       { 0x0213F0FD42D04124, 0x000036C6, 0xFFFFE6CF, 0x000005A1, 0x00002457, 0xFFFFF11D, 0x0000042D, 0x00002457, 0xFFFFF11D, 0x0000042D },
+       { 0x0213EA94DE321944, 0x00002815, 0xFFFFF19A, 0x000003F2, 0x000016D2, 0xFFFFFB40, 0x00000299, 0x000016D2, 0xFFFFFB40, 0x00000299 },
+       { 0x0213EA94DE1C19A4, 0x00001FE2, 0xFFFFF660, 0x00000354, 0x000015A7, 0xFFFFFB47, 0x000002C1, 0x000015A7, 0xFFFFFB47, 0x000002C1 },
+       { 0x0213EA94DE161964, 0x00002114, 0xFFFFF634, 0x00000356, 0x000016C1, 0xFFFFFB43, 0x000002B8, 0x000016C1, 0xFFFFFB43, 0x000002B8 },
+       { 0x0213F0FD42CC28C4, 0x000028E3, 0xFFFFF075, 0x00000414, 0x0000203C, 0xFFFFF438, 0x000003B3, 0x0000203C, 0xFFFFF438, 0x000003B3 },
+       { 0x0213EA94DE1C3924, 0x00001EEB, 0xFFFFF7BB, 0x0000031A, 0x00001580, 0xFFFFFBD7, 0x000002AD, 0x00001580, 0xFFFFFBD7, 0x000002AD },
+       { 0x0213EA94DE2408C4, 0x00002BB2, 0xFFFFEE72, 0x00000470, 0x0000192C, 0xFFFFF91E, 0x000002E7, 0x0000192C, 0xFFFFF91E, 0x000002E7 },
+       { 0x0213EA94DE0650E4, 0x00003A3D, 0xFFFFE49D, 0x000005F5, 0x00001A3B, 0xFFFFF7B1, 0x00000320, 0x00001A3B, 0xFFFFF7B1, 0x00000320 },
+       { 0x0213F0FD42CE3164, 0x00002E93, 0xFFFFEC5A, 0x000004B4, 0x000025EB, 0xFFFFF03C, 0x0000044A, 0x000025EB, 0xFFFFF03C, 0x0000044A },
+       { 0x0213F0FD42CA20C4, 0x0000331F, 0xFFFFE97A, 0x00000531, 0x00001A06, 0xFFFFF850, 0x000002FD, 0x00001A06, 0xFFFFF850, 0x000002FD },
+       { 0x0213F0FD42C63964, 0x00003937, 0xFFFFE5A0, 0x000005C7, 0x0000235E, 0xFFFFF234, 0x000003F2, 0x0000235E, 0xFFFFF234, 0x000003F2 },
+       { 0x0213EA94DE1E3924, 0x00001DD0, 0xFFFFF80E, 0x00000319, 0x000015C7, 0xFFFFFB91, 0x000002BC, 0x000015C7, 0xFFFFFB91, 0x000002BC },
+       { 0x0213F0FD42D03964, 0x00003328, 0xFFFFE905, 0x0000054A, 0x00002054, 0xFFFFF3BF, 0x000003C0, 0x00002054, 0xFFFFF3BF, 0x000003C0 },
+       { 0x0213F0FD42CC1104, 0x00002FE5, 0xFFFFEA65, 0x00000520, 0x0000188B, 0xFFFFF8A7, 0x000002F5, 0x0000188B, 0xFFFFF8A7, 0x000002F5 },
+       { 0x0213F0FD42CA38A4, 0x00002ED3, 0xFFFFEC51, 0x000004B9, 0x00001888, 0xFFFFF96A, 0x000002CA, 0x00001888, 0xFFFFF96A, 0x000002CA },
+       { 0x0213F0FD42D03084, 0x00002FCC, 0xFFFFEB60, 0x000004EA, 0x00001F8D, 0xFFFFF436, 0x000003B4, 0x00001F8D, 0xFFFFF436, 0x000003B4 },
+       { 0x0213F0FD42CE4084, 0x0000329F, 0xFFFFE8F7, 0x0000054F, 0x000023DB, 0xFFFFF0EE, 0x0000043A, 0x000023DB, 0xFFFFF0EE, 0x0000043A },
+       { 0x0213EA94DE0438A4, 0x000030B5, 0xFFFFEBB8, 0x000004C4, 0x00001AFD, 0xFFFFF781, 0x00000329, 0x00001AFD, 0xFFFFF781, 0x00000329 },
+       { 0x0213EA94DE1E19A4, 0x00001BBF, 0xFFFFF8E2, 0x000002F7, 0x00001722, 0xFFFFFA85, 0x000002DB, 0x00001722, 0xFFFFFA85, 0x000002DB },
+       { 0x0213EA94DE022044, 0x000030E4, 0xFFFFEBE6, 0x000004BB, 0x00001C80, 0xFFFFF6E1, 0x0000033E, 0x00001C80, 0xFFFFF6E1, 0x0000033E },
+       { 0x0213EA94DE122944, 0x000030E2, 0xFFFFECD0, 0x00000492, 0x00001CE0, 0xFFFFF753, 0x0000032F, 0x00001CE0, 0xFFFFF753, 0x0000032F },
+       { 0x0213EA94DE322864, 0x00002513, 0xFFFFF323, 0x000003BC, 0x00001965, 0xFFFFF93C, 0x000002F0, 0x00001965, 0xFFFFF93C, 0x000002F0 },
+       { 0x0213EA94DE1610A4, 0x00002147, 0xFFFFF585, 0x0000037A, 0x000014CC, 0xFFFFFC3B, 0x00000296, 0x000014CC, 0xFFFFFC3B, 0x00000296 },
+       { 0x0213EA94DE322124, 0x00002507, 0xFFFFF432, 0x0000038A, 0x00001890, 0xFFFFFA61, 0x000002C6, 0x00001890, 0xFFFFFA61, 0x000002C6 },
+       { 0x0213EA94DE0638A4, 0x0000339B, 0xFFFFEA7D, 0x000004F0, 0x0000191E, 0xFFFFF944, 0x000002DF, 0x0000191E, 0xFFFFF944, 0x000002DF },
+       { 0x0213F0FD42CC28A4, 0x00002842, 0xFFFFF043, 0x00000427, 0x00001988, 0xFFFFF892, 0x000002F7, 0x00001988, 0xFFFFF892, 0x000002F7 },
+       { 0x0213F0FD42C618A4, 0x0000389D, 0xFFFFE5D8, 0x000005BF, 0x00001EE1, 0xFFFFF4EF, 0x00000387, 0x00001EE1, 0xFFFFF4EF, 0x00000387 },
+       { 0x0213F0FD42CE3184, 0x0000396D, 0xFFFFE4D7, 0x000005F2, 0x000020DA, 0xFFFFF34E, 0x000003CD, 0x000020DA, 0xFFFFF34E, 0x000003CD },
+       { 0x0213F0FD42CA3104, 0x0000355F, 0xFFFFE85A, 0x0000055F, 0x0000281F, 0xFFFFEF28, 0x0000047D, 0x0000281F, 0xFFFFEF28, 0x0000047D },
+       { 0x0213EA94DE1C50E4, 0x00002284, 0xFFFFF46E, 0x00000399, 0x00001498, 0xFFFFFBE3, 0x0000029C, 0x00001498, 0xFFFFFBE3, 0x0000029C },
+       { 0x0213EA94DE023944, 0x000031B6, 0xFFFFEB42, 0x000004D9, 0x00001F54, 0xFFFFF4D2, 0x00000399, 0x00001F54, 0xFFFFF4D2, 0x00000399 },
+       { 0x0213F0FD42C63064, 0x000035CE, 0xFFFFE79D, 0x00000578, 0x00001C78, 0xFFFFF68C, 0x00000344, 0x00001C78, 0xFFFFF68C, 0x00000344 },
+       { 0x0213EA94DE1E4964, 0x00001C0A, 0xFFFFF81B, 0x00000318, 0x00001492, 0xFFFFFBCC, 0x000002A5, 0x00001492, 0xFFFFFBCC, 0x000002A5 },
+       { 0x0213EA94DE022184, 0x00003492, 0xFFFFE95C, 0x00000526, 0x00001A97, 0xFFFFF81B, 0x0000030B, 0x00001A97, 0xFFFFF81B, 0x0000030B },
+       { 0x0213EA94DE163164, 0x00001E89, 0xFFFFF7D0, 0x0000031A, 0x000017A5, 0xFFFFFA99, 0x000002D9, 0x000017A5, 0xFFFFFA99, 0x000002D9 },
+       { 0x0213F0FD42CA48C4, 0x00002DCC, 0xFFFFEBE0, 0x000004DE, 0x000019BA, 0xFFFFF7F5, 0x0000030D, 0x000019BA, 0xFFFFF7F5, 0x0000030D },
+       { 0x0213EA94DE042984, 0x000030EF, 0xFFFFEBC1, 0x000004C0, 0x00001AA9, 0xFFFFF814, 0x0000030A, 0x00001AA9, 0xFFFFF814, 0x0000030A },
+       { 0x0213EA94DE245124, 0x00002EA3, 0xFFFFEBF6, 0x000004D8, 0x00001DCF, 0xFFFFF521, 0x00000399, 0x00001DCF, 0xFFFFF521, 0x00000399 },
+       { 0x0213EA94DE324164, 0x00002B5F, 0xFFFFEEA1, 0x0000046C, 0x000017EB, 0xFFFFF9C9, 0x000002D4, 0x000017EB, 0xFFFFF9C9, 0x000002D4 },
+       { 0x0213EA94DE024104, 0x00002C63, 0xFFFFEE82, 0x00000455, 0x00002268, 0xFFFFF29D, 0x000003F6, 0x00002268, 0xFFFFF29D, 0x000003F6 },
+       { 0x0213EA94DE121904, 0x00002B1A, 0xFFFFF016, 0x0000041C, 0x000019AA, 0xFFFFF988, 0x000002D2, 0x000019AA, 0xFFFFF988, 0x000002D2 },
+       { 0x0213F0FD42CA2964, 0x0000332F, 0xFFFFE934, 0x0000053B, 0x00001E47, 0xFFFFF566, 0x00000374, 0x00001E47, 0xFFFFF566, 0x00000374 },
+       { 0x0213F0FD42CA48E4, 0x00002995, 0xFFFFEEC1, 0x00000465, 0x0000178F, 0xFFFFF995, 0x000002C5, 0x0000178F, 0xFFFFF995, 0x000002C5 },
+       { 0x0213EA94DE201884, 0x00001C2E, 0xFFFFF932, 0x000002E9, 0x000015C2, 0xFFFFFBC5, 0x000002AD, 0x000015C2, 0xFFFFFBC5, 0x000002AD },
+       { 0x0213F0FD42C640E4, 0x00003B08, 0xFFFFE4E8, 0x000005D8, 0x0000209D, 0xFFFFF444, 0x00000398, 0x0000209D, 0xFFFFF444, 0x00000398 },
+       { 0x0213EA94DE0450E4, 0x00002F1F, 0xFFFFEB74, 0x000004EB, 0x00001F4C, 0xFFFFF3D4, 0x000003CE, 0x00001F4C, 0xFFFFF3D4, 0x000003CE },
+       { 0x0213EA94DE043884, 0x00003415, 0xFFFFE89F, 0x00000553, 0x0000186B, 0xFFFFF8E1, 0x000002EF, 0x0000186B, 0xFFFFF8E1, 0x000002EF },
+       { 0x0213F0FD42CC10C4, 0x00003441, 0xFFFFE779, 0x0000059D, 0x000019EA, 0xFFFFF7B2, 0x0000031F, 0x000019EA, 0xFFFFF7B2, 0x0000031F },
+       { 0x0213EA94DE164064, 0x00002174, 0xFFFFF546, 0x00000378, 0x00001456, 0xFFFFFC5F, 0x00000284, 0x00001456, 0xFFFFFC5F, 0x00000284 },
+       { 0x0213F0FD42CE40C4, 0x00003788, 0xFFFFE61E, 0x000005BF, 0x00001DF4, 0xFFFFF562, 0x00000374, 0x00001DF4, 0xFFFFF562, 0x00000374 },
+       { 0x0213EA94DE1E1844, 0x00001C41, 0xFFFFF8C1, 0x000002FC, 0x0000171E, 0xFFFFFA93, 0x000002DE, 0x0000171E, 0xFFFFFA93, 0x000002DE },
+       { 0x0213F0FD42CA3864, 0x00002B15, 0xFFFFEDEC, 0x00000487, 0x000017E4, 0xFFFFF934, 0x000002DF, 0x000017E4, 0xFFFFF934, 0x000002DF },
+       { 0x0213F0FD42CC3144, 0x0000327A, 0xFFFFEA71, 0x000004FF, 0x00001D96, 0xFFFFF63B, 0x00000351, 0x00001D96, 0xFFFFF63B, 0x00000351 },
+       { 0x0213EA94DE1E4064, 0x000023C6, 0xFFFFF3E5, 0x000003B6, 0x000014DE, 0xFFFFFC29, 0x00000294, 0x000014DE, 0xFFFFFC29, 0x00000294 },
+       { 0x0213EA94DE164944, 0x00001F96, 0xFFFFF5FA, 0x00000364, 0x00001397, 0xFFFFFC9D, 0x0000027D, 0x00001397, 0xFFFFFC9D, 0x0000027D },
+       { 0x0213EA94DE063144, 0x00002B51, 0xFFFFEFB5, 0x00000420, 0x00001ACA, 0xFFFFF824, 0x0000030D, 0x00001ACA, 0xFFFFF824, 0x0000030D },
+       { 0x0213EA94DE1E4944, 0x000020DB, 0xFFFFF55B, 0x0000037C, 0x0000153D, 0xFFFFFB5F, 0x000002BA, 0x0000153D, 0xFFFFFB5F, 0x000002BA },
+       { 0x0213EA94DE0221A4, 0x000030BB, 0xFFFFEBDA, 0x000004BC, 0x00001B0E, 0xFFFFF7A8, 0x0000031E, 0x00001B0E, 0xFFFFF7A8, 0x0000031E },
+       { 0x0213F0FD42C62904, 0x000033C4, 0xFFFFEA41, 0x000004FA, 0x000022C6, 0xFFFFF363, 0x000003BC, 0x000022C6, 0xFFFFF363, 0x000003BC },
+       { 0x0213EA94DE240924, 0x00002D47, 0xFFFFEE01, 0x00000477, 0x000021CD, 0xFFFFF36E, 0x000003D6, 0x000021CD, 0xFFFFF36E, 0x000003D6 },
+       { 0x0213EA94DE1E31A4, 0x00001E7B, 0xFFFFF733, 0x00000339, 0x00001668, 0xFFFFFB29, 0x000002BF, 0x00001668, 0xFFFFFB29, 0x000002BF },
+       { 0x0213F0FD42CA2984, 0x00002F7E, 0xFFFFEAFF, 0x000004FC, 0x000018D4, 0xFFFFF8BE, 0x000002E8, 0x000018D4, 0xFFFFF8BE, 0x000002E8 },
+       { 0x0213EA94DE3238A4, 0x00002635, 0xFFFFF2E1, 0x000003BC, 0x000017A4, 0xFFFFFA67, 0x000002C3, 0x000017A4, 0xFFFFFA67, 0x000002C3 },
+       { 0x0213EA94DE1230A4, 0x000026CA, 0xFFFFF2C1, 0x000003B2, 0x00001C3E, 0xFFFFF7AE, 0x0000031F, 0x00001C3E, 0xFFFFF7AE, 0x0000031F },
+       { 0x0213EA94DE1C1064, 0x00002550, 0xFFFFF380, 0x000003B5, 0x000019F5, 0xFFFFF8E7, 0x00000313, 0x000019F5, 0xFFFFF8E7, 0x00000313 },
+       { 0x0213F0FD42CA4904, 0x00002FBC, 0xFFFFEAF8, 0x000004FA, 0x000018CC, 0xFFFFF8C6, 0x000002E8, 0x000018CC, 0xFFFFF8C6, 0x000002E8 },
+       { 0x0213F0FD42D018E4, 0x00002FCC, 0xFFFFEB60, 0x000004EA, 0x00001EFF, 0xFFFFF4DA, 0x0000038F, 0x00001EFF, 0xFFFFF4DA, 0x0000038F },
+       { 0x0213EA94DE164084, 0x000023E6, 0xFFFFF413, 0x000003A1, 0x00001544, 0xFFFFFC16, 0x0000028B, 0x00001544, 0xFFFFFC16, 0x0000028B },
+       { 0x0213F0FD42CE3024, 0x00003251, 0xFFFFEAA2, 0x000004F5, 0x000025B0, 0xFFFFF0DF, 0x00000431, 0x000025B0, 0xFFFFF0DF, 0x00000431 },
+       { 0x0213F0FD42D03984, 0x00002F6F, 0xFFFFEB67, 0x000004E6, 0x00002275, 0xFFFFF249, 0x000003FB, 0x00002275, 0xFFFFF249, 0x000003FB },
+       { 0x0213EA94DE322964, 0x00002597, 0xFFFFF34A, 0x000003B1, 0x00001BCC, 0xFFFFF822, 0x0000031A, 0x00001BCC, 0xFFFFF822, 0x0000031A },
+       { 0x0213F0FD42C63864, 0x00003B1D, 0xFFFFE40E, 0x0000060D, 0x00001F61, 0xFFFFF470, 0x0000039F, 0x00001F61, 0xFFFFF470, 0x0000039F },
+       { 0x0213F0FD42C64144, 0x0000379F, 0xFFFFE6DB, 0x0000058C, 0x00002460, 0xFFFFF170, 0x00000415, 0x00002460, 0xFFFFF170, 0x00000415 },
+       { 0x0213EA94DE165144, 0x00002442, 0xFFFFF2FB, 0x000003D9, 0x00001414, 0xFFFFFBDC, 0x000002A2, 0x00001414, 0xFFFFFBDC, 0x000002A2 },
+       { 0x0213EA94DE0240C4, 0x00003270, 0xFFFFEA0D, 0x0000051C, 0x00001AFD, 0xFFFFF783, 0x00000328, 0x00001AFD, 0xFFFFF783, 0x00000328 },
+       { 0x0213EA94DE161104, 0x00001B23, 0xFFFFF94B, 0x000002EB, 0x000015F1, 0xFFFFFB82, 0x000002B4, 0x000015F1, 0xFFFFFB82, 0x000002B4 },
+       { 0x0213EA94DE323844, 0x000026AE, 0xFFFFF21A, 0x000003DB, 0x00001827, 0xFFFFFA10, 0x000002C8, 0x00001827, 0xFFFFFA10, 0x000002C8 },
+       { 0x0213F0FD42CA4884, 0x00002DCF, 0xFFFFEBD8, 0x000004DB, 0x00001A75, 0xFFFFF719, 0x0000033A, 0x00001A75, 0xFFFFF719, 0x0000033A },
+       { 0x0213F0FD42CE40E4, 0x00003983, 0xFFFFE500, 0x000005EA, 0x000022A6, 0xFFFFF25F, 0x000003F1, 0x000022A6, 0xFFFFF25F, 0x000003F1 },
+       { 0x0213EA94DE1218C4, 0x00002AD5, 0xFFFFF07A, 0x00000406, 0x000019FB, 0xFFFFF961, 0x000002D8, 0x000019FB, 0xFFFFF961, 0x000002D8 },
+       { 0x0213F0FD42CA39A4, 0x00002A43, 0xFFFFEE43, 0x00000474, 0x00001D65, 0xFFFFF538, 0x00000387, 0x00001D65, 0xFFFFF538, 0x00000387 },
+       { 0x0213F0FD42C62084, 0x0000311E, 0xFFFFEAF8, 0x000004E8, 0x00001959, 0xFFFFF8E4, 0x000002DC, 0x00001959, 0xFFFFF8E4, 0x000002DC },
+       { 0x0213F0FD42D031A4, 0x0000339A, 0xFFFFE8A7, 0x00000559, 0x00001A04, 0xFFFFF7E5, 0x00000311, 0x00001A04, 0xFFFFF7E5, 0x00000311 },
+       { 0x0213EA94DE204144, 0x000021B3, 0xFFFFF50F, 0x00000389, 0x00001470, 0xFFFFFBF7, 0x000002A5, 0x00001470, 0xFFFFFBF7, 0x000002A5 },
+       { 0x0213EA94DE021884, 0x00003417, 0xFFFFE9A6, 0x0000051D, 0x000018A4, 0xFFFFF984, 0x000002CF, 0x000018A4, 0xFFFFF984, 0x000002CF },
+       { 0x0213EA94DE202984, 0x00001FED, 0xFFFFF6A2, 0x00000347, 0x00001639, 0xFFFFFB59, 0x000002BB, 0x00001639, 0xFFFFFB59, 0x000002BB },
+       { 0x0213EA94DE1218A4, 0x000032D2, 0xFFFFEB18, 0x000004DC, 0x00001A01, 0xFFFFF95E, 0x000002CF, 0x00001A01, 0xFFFFF95E, 0x000002CF },
+       { 0x0213F0FD42D04084, 0x00003147, 0xFFFFEA3B, 0x00000518, 0x0000241D, 0xFFFFF11C, 0x00000431, 0x0000241D, 0xFFFFF11C, 0x00000431 },
+       { 0x0213EA94DE1C0904, 0x00001D44, 0xFFFFF7E7, 0x0000031A, 0x0000153F, 0xFFFFFBBC, 0x000002A9, 0x0000153F, 0xFFFFFBBC, 0x000002A9 },
+       { 0x0213F0FD42CC4104, 0x00003690, 0xFFFFE6E3, 0x000005A4, 0x000018DE, 0xFFFFF908, 0x000002DD, 0x000018DE, 0xFFFFF908, 0x000002DD },
+       { 0x0213F0FD42CC2184, 0x00003561, 0xFFFFE6F8, 0x000005AB, 0x000018B5, 0xFFFFF8A0, 0x000002F3, 0x000018B5, 0xFFFFF8A0, 0x000002F3 },
+       { 0x0213EA94DE323124, 0x000028F4, 0xFFFFF23A, 0x000003CE, 0x00001BC6, 0xFFFFF881, 0x00000311, 0x00001BC6, 0xFFFFF881, 0x00000311 },
+       { 0x0213F0FD42D03184, 0x000035D7, 0xFFFFE71C, 0x0000059B, 0x00001D49, 0xFFFFF5C8, 0x00000368, 0x00001D49, 0xFFFFF5C8, 0x00000368 },
+       { 0x0213F0FD42CE18A4, 0x0000397E, 0xFFFFE4CB, 0x000005F4, 0x00001989, 0xFFFFF844, 0x000002FD, 0x00001989, 0xFFFFF844, 0x000002FD },
+       { 0x0213F0FD42C62064, 0x00003BAB, 0xFFFFE332, 0x0000063F, 0x00001A69, 0xFFFFF7B9, 0x00000312, 0x00001A69, 0xFFFFF7B9, 0x00000312 },
+       { 0x0213F0FD42D03064, 0x00002F26, 0xFFFFEB82, 0x000004E8, 0x00001D7D, 0xFFFFF590, 0x00000379, 0x00001D7D, 0xFFFFF590, 0x00000379 },
+       { 0x0213EA94DE0631A4, 0x00002FDC, 0xFFFFEBE0, 0x000004C3, 0x00001940, 0xFFFFF8CC, 0x000002EE, 0x00001940, 0xFFFFF8CC, 0x000002EE },
+       { 0x0213EA94DE1C08E4, 0x000021B2, 0xFFFFF558, 0x00000379, 0x00001643, 0xFFFFFB1C, 0x000002C3, 0x00001643, 0xFFFFFB1C, 0x000002C3 },
+       { 0x0213EA94DE321904, 0x00002897, 0xFFFFF181, 0x000003F7, 0x00001990, 0xFFFFF994, 0x000002E2, 0x00001990, 0xFFFFF994, 0x000002E2 },
+       { 0x0213EA94DE1E0924, 0x00001D19, 0xFFFFF829, 0x0000031A, 0x00001558, 0xFFFFFBCA, 0x000002AF, 0x00001558, 0xFFFFFBCA, 0x000002AF },
+       { 0x0213EA94DE043144, 0x00003311, 0xFFFFEAD9, 0x000004E1, 0x00001BDC, 0xFFFFF79E, 0x0000031D, 0x00001BDC, 0xFFFFF79E, 0x0000031D },
+       { 0x0213EA94DE1E29C4, 0x00001E54, 0xFFFFF740, 0x00000333, 0x000016A1, 0xFFFFFAF0, 0x000002C4, 0x000016A1, 0xFFFFFAF0, 0x000002C4 },
+       { 0x0213F0FD42CE3964, 0x00003266, 0xFFFFE9A8, 0x00000527, 0x00002307, 0xFFFFF219, 0x000003FC, 0x00002307, 0xFFFFF219, 0x000003FC },
+       { 0x0213EA94DE321144, 0x00001D1F, 0xFFFFF82B, 0x000002F0, 0x000013F0, 0xFFFFFD0B, 0x0000024E, 0x000013F0, 0xFFFFFD0B, 0x0000024E },
+       { 0x0213F0FD42C648A4, 0x0000312E, 0xFFFFEA67, 0x00000502, 0x0000222A, 0xFFFFF253, 0x000003F9, 0x0000222A, 0xFFFFF253, 0x000003F9 },
+       { 0x0213F0FD42CA4124, 0x000032B2, 0xFFFFE9AD, 0x00000523, 0x00001E97, 0xFFFFF527, 0x0000037F, 0x00001E97, 0xFFFFF527, 0x0000037F },
+       { 0x0213EA94DE1640E4, 0x00001F6A, 0xFFFFF6FC, 0x00000338, 0x0000164B, 0xFFFFFB2C, 0x000002C2, 0x0000164B, 0xFFFFFB2C, 0x000002C2 },
+       { 0x0213EA94DE0228C4, 0x00002603, 0xFFFFF386, 0x00000392, 0x00001EE0, 0xFFFFF601, 0x00000369, 0x00001EE0, 0xFFFFF601, 0x00000369 },
+       { 0x0213EA94DE201164, 0x00001D0C, 0xFFFFF803, 0x00000317, 0x00001345, 0xFFFFFD52, 0x00000260, 0x00001345, 0xFFFFFD52, 0x00000260 },
+       { 0x0213F0FD42CC1884, 0x0000327A, 0xFFFFE8E5, 0x0000055C, 0x00001680, 0xFFFFFA2D, 0x000002B2, 0x00001680, 0xFFFFFA2D, 0x000002B2 },
+       { 0x0213F0FD42CA3964, 0x000032B8, 0xFFFFE91A, 0x0000054A, 0x00001BAB, 0xFFFFF6EC, 0x00000338, 0x00001BAB, 0xFFFFF6EC, 0x00000338 },
+       { 0x0213F0FD42CC3044, 0x00002F79, 0xFFFFEB63, 0x000004EF, 0x000017BB, 0xFFFFF9B1, 0x000002CA, 0x000017BB, 0xFFFFF9B1, 0x000002CA },
+       { 0x0213EA94DE0438E4, 0x00002AE5, 0xFFFFEFCB, 0x0000041D, 0x0000214A, 0xFFFFF3A7, 0x000003C7, 0x0000214A, 0xFFFFF3A7, 0x000003C7 },
+       { 0x0213EA94DE322064, 0x0000212C, 0xFFFFF5BC, 0x0000034F, 0x000017ED, 0xFFFFFA4C, 0x000002C1, 0x000017ED, 0xFFFFFA4C, 0x000002C1 },
+       { 0x0213EA94DE121124, 0x00002BE7, 0xFFFFEF40, 0x0000043C, 0x00001AE2, 0xFFFFF8CF, 0x000002E3, 0x00001AE2, 0xFFFFF8CF, 0x000002E3 },
+       { 0x0213F0FD42D05144, 0x000032DC, 0xFFFFE90F, 0x00000549, 0x00002A2D, 0xFFFFECC9, 0x000004ED, 0x00002A2D, 0xFFFFECC9, 0x000004ED },
+       { 0x0213EA94DE1618A4, 0x00001DE3, 0xFFFFF80D, 0x00000319, 0x000016FA, 0xFFFFFB42, 0x000002BC, 0x000016FA, 0xFFFFFB42, 0x000002BC },
+       { 0x0213EA94DE1E2844, 0x00001F1B, 0xFFFFF6DE, 0x00000346, 0x00001502, 0xFFFFFC23, 0x00000298, 0x00001502, 0xFFFFFC23, 0x00000298 },
+       { 0x0213EA94DE061864, 0x00003203, 0xFFFFEA87, 0x000004FE, 0x0000194E, 0xFFFFF8E3, 0x000002EC, 0x0000194E, 0xFFFFF8E3, 0x000002EC },
+       { 0x0213F0FD42D02144, 0x0000337A, 0xFFFFE8DD, 0x00000551, 0x00001E3C, 0xFFFFF534, 0x00000385, 0x00001E3C, 0xFFFFF534, 0x00000385 },
+       { 0x0213F0FD42CA4864, 0x000036F6, 0xFFFFE62A, 0x000005C5, 0x000023C0, 0xFFFFF117, 0x00000435, 0x000023C0, 0xFFFFF117, 0x00000435 },
+       { 0x0213F0FD42CC2144, 0x00003125, 0xFFFFEA4E, 0x0000051A, 0x00001E6C, 0xFFFFF503, 0x0000038E, 0x00001E6C, 0xFFFFF503, 0x0000038E },
+       { 0x0213EA94DE1C08A4, 0x00001CD4, 0xFFFFF82D, 0x0000030E, 0x0000156D, 0xFFFFFB64, 0x000002B8, 0x0000156D, 0xFFFFFB64, 0x000002B8 },
+       { 0x0213EA94DE0240A4, 0x00002F14, 0xFFFFEC46, 0x000004B8, 0x000017F1, 0xFFFFF977, 0x000002D2, 0x000017F1, 0xFFFFF977, 0x000002D2 },
+       { 0x0213EA94DE0640A4, 0x000031F1, 0xFFFFEAD4, 0x000004ED, 0x0000184C, 0xFFFFF983, 0x000002D4, 0x0000184C, 0xFFFFF983, 0x000002D4 },
+       { 0x0213F0FD42D04984, 0x00002EA9, 0xFFFFEBD7, 0x000004D5, 0x0000288D, 0xFFFFEDDB, 0x000004C0, 0x0000288D, 0xFFFFEDDB, 0x000004C0 },
+       { 0x0213F0FD42CA3984, 0x0000335F, 0xFFFFE82C, 0x00000579, 0x00001DBF, 0xFFFFF512, 0x0000038C, 0x00001DBF, 0xFFFFF512, 0x0000038C },
+       { 0x0213EA94DE201184, 0x0000224F, 0xFFFFF4B5, 0x00000391, 0x0000138C, 0xFFFFFCC3, 0x0000027A, 0x0000138C, 0xFFFFFCC3, 0x0000027A },
+       { 0x0213EA94DE1240A4, 0x0000320D, 0xFFFFEACD, 0x000004F5, 0x00001976, 0xFFFFF913, 0x000002E2, 0x00001976, 0xFFFFF913, 0x000002E2 },
+       { 0x0213EA94DE202104, 0x00001BEB, 0xFFFFF99C, 0x000002E4, 0x000016A4, 0xFFFFFB77, 0x000002C3, 0x000016A4, 0xFFFFFB77, 0x000002C3 },
+       { 0x0213EA94DE063044, 0x0000396E, 0xFFFFE616, 0x000005A9, 0x000018F4, 0xFFFFF91A, 0x000002E3, 0x000018F4, 0xFFFFF91A, 0x000002E3 },
+       { 0x0213EA94DE022864, 0x00003251, 0xFFFFEA8E, 0x000004FA, 0x000018EF, 0xFFFFF910, 0x000002E4, 0x000018EF, 0xFFFFF910, 0x000002E4 },
+       { 0x0213EA94DE1C1924, 0x00001DAF, 0xFFFFF857, 0x0000030D, 0x00001915, 0xFFFFF9D8, 0x000002F7, 0x00001915, 0xFFFFF9D8, 0x000002F7 },
+       { 0x0213EA94DE2041A4, 0x000025B6, 0xFFFFF26B, 0x000003E5, 0x00001531, 0xFFFFFB68, 0x000002AF, 0x00001531, 0xFFFFFB68, 0x000002AF },
+       { 0x0213EA94DE061884, 0x00002B2E, 0xFFFFEF2E, 0x00000440, 0x00001968, 0xFFFFF91A, 0x000002DF, 0x00001968, 0xFFFFF91A, 0x000002DF },
+       { 0x0213EA94DE1C2064, 0x00002305, 0xFFFFF528, 0x00000377, 0x000018A4, 0xFFFFF9EB, 0x000002F0, 0x000018A4, 0xFFFFF9EB, 0x000002F0 },
+       { 0x0213F0FD42CA40C4, 0x000032A1, 0xFFFFE992, 0x0000052E, 0x00001A55, 0xFFFFF826, 0x000002FE, 0x00001A55, 0xFFFFF826, 0x000002FE },
+       { 0x0213EA94DE042184, 0x00002CCD, 0xFFFFEE35, 0x00000462, 0x00001B09, 0xFFFFF7E6, 0x0000030F, 0x00001B09, 0xFFFFF7E6, 0x0000030F },
+       { 0x0213EA94DE323084, 0x00002602, 0xFFFFF2CF, 0x000003C5, 0x000016EE, 0xFFFFFAD4, 0x000002B4, 0x000016EE, 0xFFFFFAD4, 0x000002B4 },
+       { 0x0213F0FD42D01964, 0x00003370, 0xFFFFE891, 0x00000560, 0x000017F0, 0xFFFFF930, 0x000002DF, 0x000017F0, 0xFFFFF930, 0x000002DF },
+       { 0x0213F0FD42CA1884, 0x00002EDC, 0xFFFFEB6D, 0x000004EC, 0x000016E6, 0xFFFFF9ED, 0x000002BC, 0x000016E6, 0xFFFFF9ED, 0x000002BC },
+       { 0x0213EA94DE1228C4, 0x00002A05, 0xFFFFF13D, 0x000003F0, 0x00002065, 0xFFFFF57B, 0x00000378, 0x00002065, 0xFFFFF57B, 0x00000378 },
+       { 0x0213F0FD42CE2044, 0x00002F8A, 0xFFFFEB6E, 0x000004E4, 0x00001E3E, 0xFFFFF50E, 0x0000038D, 0x00001E3E, 0xFFFFF50E, 0x0000038D },
+       { 0x0213F0FD42CA3044, 0x00002BB5, 0xFFFFED6A, 0x000004A1, 0x000017BF, 0xFFFFF937, 0x000002E5, 0x000017BF, 0xFFFFF937, 0x000002E5 },
+       { 0x0213EA94DE201964, 0x0000202C, 0xFFFFF6CE, 0x0000033F, 0x000015EE, 0xFFFFFB83, 0x000002B9, 0x000015EE, 0xFFFFFB83, 0x000002B9 },
+       { 0x0213EA94DE022884, 0x00002C0C, 0xFFFFEF10, 0x0000043F, 0x00001A73, 0xFFFFF83E, 0x0000030C, 0x00001A73, 0xFFFFF83E, 0x0000030C },
+       { 0x0213EA94DE324104, 0x0000234F, 0xFFFFF460, 0x00000385, 0x000018C3, 0xFFFFF9A5, 0x000002DD, 0x000018C3, 0xFFFFF9A5, 0x000002DD },
+       { 0x0213F0FD42CE1904, 0x00003679, 0xFFFFE704, 0x00000595, 0x00002177, 0xFFFFF31A, 0x000003D7, 0x00002177, 0xFFFFF31A, 0x000003D7 },
+       { 0x0213F0FD42CA2924, 0x00003008, 0xFFFFEBB8, 0x000004D5, 0x000024FF, 0xFFFFF112, 0x00000430, 0x000024FF, 0xFFFFF112, 0x00000430 },
+       { 0x0213F0FD42C641A4, 0x00003848, 0xFFFFE6A3, 0x00000594, 0x00002958, 0xFFFFEE37, 0x000004A0, 0x00002958, 0xFFFFEE37, 0x000004A0 },
+       { 0x0213F0FD42CC1924, 0x00002FDF, 0xFFFFEB08, 0x000004FD, 0x00001D77, 0xFFFFF58B, 0x0000037A, 0x00001D77, 0xFFFFF58B, 0x0000037A },
+       { 0x0213EA94DE063064, 0x00002EC8, 0xFFFFED41, 0x00000481, 0x00001949, 0xFFFFF91C, 0x000002DF, 0x00001949, 0xFFFFF91C, 0x000002DF },
+       { 0x0213F0FD42D041A4, 0x000037C1, 0xFFFFE5BA, 0x000005D7, 0x0000252C, 0xFFFFF023, 0x00000460, 0x0000252C, 0xFFFFF023, 0x00000460 },
+       { 0x0213F0FD42CE2944, 0x00003716, 0xFFFFE70C, 0x0000058A, 0x000028CC, 0xFFFFEE57, 0x0000049D, 0x000028CC, 0xFFFFEE57, 0x0000049D },
+       { 0x0213F0FD42CA40E4, 0x000033D1, 0xFFFFE8E8, 0x00000547, 0x00001AB1, 0xFFFFF7E5, 0x00000309, 0x00001AB1, 0xFFFFF7E5, 0x00000309 },
+       { 0x0213F0FD42CC2944, 0x00002D72, 0xFFFFED65, 0x0000048E, 0x00001E0D, 0xFFFFF5A7, 0x00000370, 0x00001E0D, 0xFFFFF5A7, 0x00000370 },
+       { 0x0213EA94DE1C39A4, 0x00002292, 0xFFFFF49F, 0x00000393, 0x000017F4, 0xFFFFF9CD, 0x000002F5, 0x000017F4, 0xFFFFF9CD, 0x000002F5 },
+       { 0x0213EA94DE243044, 0x000026EE, 0xFFFFF18C, 0x000003F7, 0x000018A7, 0xFFFFF95A, 0x000002E5, 0x000018A7, 0xFFFFF95A, 0x000002E5 },
+       { 0x0213EA94DE042164, 0x00002F62, 0xFFFFEC9B, 0x000004A4, 0x0000194E, 0xFFFFF932, 0x000002D9, 0x0000194E, 0xFFFFF932, 0x000002D9 },
+       { 0x0213EA94DE1E3984, 0x00001CE8, 0xFFFFF7FA, 0x0000031C, 0x000014CE, 0xFFFFFBD4, 0x000002AB, 0x000014CE, 0xFFFFFBD4, 0x000002AB },
+       { 0x0213EA94DE1210E4, 0x00002E5A, 0xFFFFEDAB, 0x0000047C, 0x00001A82, 0xFFFFF8F7, 0x000002DE, 0x00001A82, 0xFFFFF8F7, 0x000002DE },
+       { 0x0213F0FD42CC30E4, 0x00003057, 0xFFFFEC34, 0x000004B9, 0x00002296, 0xFFFFF342, 0x000003D0, 0x00002296, 0xFFFFF342, 0x000003D0 },
+       { 0x0213EA94DE0418A4, 0x00002B0F, 0xFFFFEF58, 0x00000434, 0x00001BFD, 0xFFFFF721, 0x00000330, 0x00001BFD, 0xFFFFF721, 0x00000330 },
+       { 0x0213EA94DE2010A4, 0x00001F01, 0xFFFFF751, 0x0000032F, 0x00001502, 0xFFFFFC3E, 0x00000296, 0x00001502, 0xFFFFFC3E, 0x00000296 },
+       { 0x0213F0FD42CA3064, 0x00002FF4, 0xFFFFEAE2, 0x00000503, 0x00001B36, 0xFFFFF736, 0x00000330, 0x00001B36, 0xFFFFF736, 0x00000330 },
+       { 0x0213F0FD42CE2064, 0x00003762, 0xFFFFE5AB, 0x000005DE, 0x000018CB, 0xFFFFF896, 0x000002F4, 0x000018CB, 0xFFFFF896, 0x000002F4 },
+       { 0x0213F0FD42CC2064, 0x00002890, 0xFFFFEF92, 0x00000445, 0x0000191D, 0xFFFFF86F, 0x00000302, 0x0000191D, 0xFFFFF86F, 0x00000302 },
+       { 0x0213EA94DE043064, 0x00002F76, 0xFFFFEC0E, 0x000004BF, 0x00001F7D, 0xFFFFF41A, 0x000003C0, 0x00001F7D, 0xFFFFF41A, 0x000003C0 },
+       { 0x0213EA94DE1E08A4, 0x00001D55, 0xFFFFF7F8, 0x0000031E, 0x000015DF, 0xFFFFFB79, 0x000002B7, 0x000015DF, 0xFFFFFB79, 0x000002B7 },
+       { 0x0213EA94DE204924, 0x00001FE9, 0xFFFFF64A, 0x00000353, 0x000019E8, 0xFFFFF882, 0x0000032A, 0x000019E8, 0xFFFFF882, 0x0000032A },
+       { 0x0213EA94DE063964, 0x000030B5, 0xFFFFEBB8, 0x000004C4, 0x00001857, 0xFFFFF968, 0x000002D8, 0x00001857, 0xFFFFF968, 0x000002D8 },
+       { 0x0213F0FD42CA28C4, 0x00003398, 0xFFFFE9A3, 0x00000524, 0x00001FF9, 0xFFFFF458, 0x000003AD, 0x00001FF9, 0xFFFFF458, 0x000003AD },
+       { 0x0213F0FD42CE2964, 0x00003897, 0xFFFFE5BD, 0x000005C8, 0x00002519, 0xFFFFF0BA, 0x00000438, 0x00002519, 0xFFFFF0BA, 0x00000438 },
+       { 0x0213F0FD42D04064, 0x00003234, 0xFFFFE9B1, 0x00000530, 0x000022CC, 0xFFFFF20E, 0x00000409, 0x000022CC, 0xFFFFF20E, 0x00000409 },
+       { 0x0213EA94DE205104, 0x00001FD2, 0xFFFFF641, 0x00000354, 0x000017C9, 0xFFFFF9C0, 0x000002FB, 0x000017C9, 0xFFFFF9C0, 0x000002FB },
+       { 0x0213F0FD42CE48E4, 0x00003234, 0xFFFFE946, 0x0000053D, 0x00002267, 0xFFFFF1F5, 0x0000040D, 0x00002267, 0xFFFFF1F5, 0x0000040D },
+       { 0x0213EA94DE2029A4, 0x00002330, 0xFFFFF474, 0x00000399, 0x00001490, 0xFFFFFC67, 0x00000288, 0x00001490, 0xFFFFFC67, 0x00000288 },
+       { 0x0213F0FD42D03924, 0x000032A3, 0xFFFFE9EB, 0x0000051B, 0x0000234D, 0xFFFFF23C, 0x000003F7, 0x0000234D, 0xFFFFF23C, 0x000003F7 },
+       { 0x0213EA94DE200904, 0x0000217E, 0xFFFFF53A, 0x00000384, 0x00001511, 0xFFFFFBF5, 0x0000029E, 0x00001511, 0xFFFFFBF5, 0x0000029E },
+       { 0x0213F0FD42CE50E4, 0x0000384F, 0xFFFFE562, 0x000005E2, 0x0000295A, 0xFFFFED53, 0x000004D3, 0x0000295A, 0xFFFFED53, 0x000004D3 },
+       { 0x0213F0FD42D05124, 0x00003315, 0xFFFFE8D1, 0x00000552, 0x000025D1, 0xFFFFEFAF, 0x00000471, 0x000025D1, 0xFFFFEFAF, 0x00000471 },
+       { 0x0213F0FD42C64924, 0x00004183, 0xFFFFDF61, 0x000006DA, 0x0000193C, 0xFFFFF88F, 0x000002EC, 0x0000193C, 0xFFFFF88F, 0x000002EC },
+       { 0x0213EA94DE242164, 0x00002DFC, 0xFFFFEDF2, 0x0000047A, 0x00001755, 0xFFFFFAC2, 0x000002AC, 0x00001755, 0xFFFFFAC2, 0x000002AC },
+       { 0x0213F0FD42CA31A4, 0x000033FE, 0xFFFFE774, 0x0000059F, 0x00001E70, 0xFFFFF492, 0x000003A0, 0x00001E70, 0xFFFFF492, 0x000003A0 },
+       { 0x0213F0FD42C629A4, 0x000040D7, 0xFFFFDFB8, 0x000006CE, 0x00001AC8, 0xFFFFF773, 0x0000031D, 0x00001AC8, 0xFFFFF773, 0x0000031D },
+       { 0x0213EA94DE1E1164, 0x00001D02, 0xFFFFF803, 0x00000322, 0x000015FE, 0xFFFFFB71, 0x000002BB, 0x000015FE, 0xFFFFFB71, 0x000002BB },
+       { 0x0213F0FD42D02884, 0x00002EB0, 0xFFFFEC31, 0x000004C4, 0x00001B3C, 0xFFFFF73B, 0x00000330, 0x00001B3C, 0xFFFFF73B, 0x00000330 },
+       { 0x0213F0FD42CA4984, 0x00002D9F, 0xFFFFECBF, 0x000004A8, 0x000022B0, 0xFFFFF23C, 0x000003F9, 0x000022B0, 0xFFFFF23C, 0x000003F9 },
+       { 0x0213F0FD42CC18E4, 0x00002C6A, 0xFFFFEDAC, 0x00000488, 0x00002419, 0xFFFFF159, 0x00000427, 0x00002419, 0xFFFFF159, 0x00000427 },
+       { 0x0213EA94DE1210A4, 0x00002991, 0xFFFFF06C, 0x0000040E, 0x00001AA9, 0xFFFFF8D0, 0x000002E1, 0x00001AA9, 0xFFFFF8D0, 0x000002E1 },
+       { 0x0213EA94DE123904, 0x00002F8E, 0xFFFFED1B, 0x00000493, 0x00001DE4, 0xFFFFF69C, 0x00000347, 0x00001DE4, 0xFFFFF69C, 0x00000347 },
+       { 0x0213EA94DE204184, 0x00002136, 0xFFFFF540, 0x0000037C, 0x000014FF, 0xFFFFFB83, 0x000002B2, 0x000014FF, 0xFFFFFB83, 0x000002B2 },
+       { 0x0213EA94DE0618E4, 0x0000354C, 0xFFFFE97D, 0x0000051A, 0x00001906, 0xFFFFF965, 0x000002DD, 0x00001906, 0xFFFFF965, 0x000002DD },
+       { 0x0213F0FD42C620C4, 0x0000348B, 0xFFFFE94D, 0x0000051F, 0x0000285B, 0xFFFFEF1A, 0x00000473, 0x0000285B, 0xFFFFEF1A, 0x00000473 },
+       { 0x0213EA94DE3218A4, 0x000026E6, 0xFFFFF24E, 0x000003D6, 0x0000141F, 0xFFFFFCCE, 0x00000260, 0x0000141F, 0xFFFFFCCE, 0x00000260 },
+       { 0x0213F0FD42C64164, 0x00003CED, 0xFFFFE2A5, 0x0000064E, 0x00002060, 0xFFFFF3E0, 0x000003B0, 0x00002060, 0xFFFFF3E0, 0x000003B0 },
+       { 0x0213EA94DE021084, 0x000029D4, 0xFFFFEFF7, 0x00000426, 0x00001976, 0xFFFFF8E1, 0x000002EE, 0x00001976, 0xFFFFF8E1, 0x000002EE },
+       { 0x0213F0FD42CA40A4, 0x00003767, 0xFFFFE601, 0x000005CC, 0x00001D22, 0xFFFFF5F4, 0x00000361, 0x00001D22, 0xFFFFF5F4, 0x00000361 },
+       { 0x0213F0FD42C650C4, 0x00003CE8, 0xFFFFE2E8, 0x00000637, 0x0000232C, 0xFFFFF1E7, 0x00000405, 0x0000232C, 0xFFFFF1E7, 0x00000405 },
+       { 0x0213EA94DE201064, 0x000023A8, 0xFFFFF4CD, 0x00000386, 0x00001944, 0xFFFFF983, 0x00000300, 0x00001944, 0xFFFFF983, 0x00000300 },
+       { 0x0213F0FD42CC30A4, 0x00003451, 0xFFFFE8B9, 0x00000551, 0x00001AD7, 0xFFFFF7BF, 0x00000318, 0x00001AD7, 0xFFFFF7BF, 0x00000318 },
+       { 0x0213F0FD42CE2984, 0x0000381B, 0xFFFFE5A0, 0x000005D0, 0x00001E0F, 0xFFFFF521, 0x00000382, 0x00001E0F, 0xFFFFF521, 0x00000382 },
+       { 0x0213EA94DE2038C4, 0x000023A4, 0xFFFFF4A6, 0x00000394, 0x0000171F, 0xFFFFFABB, 0x000002D9, 0x0000171F, 0xFFFFFABB, 0x000002D9 },
+       { 0x0213F0FD42C620A4, 0x00003C2B, 0xFFFFE447, 0x000005F0, 0x0000207F, 0xFFFFF44E, 0x0000039A, 0x0000207F, 0xFFFFF44E, 0x0000039A },
+       { 0x0213F0FD42CC3984, 0x00002F07, 0xFFFFEB70, 0x000004E9, 0x00001765, 0xFFFFF9A5, 0x000002C6, 0x00001765, 0xFFFFF9A5, 0x000002C6 },
+       { 0x0213F0FD42C62984, 0x00003A01, 0xFFFFE4E0, 0x000005E7, 0x0000227A, 0xFFFFF292, 0x000003E5, 0x0000227A, 0xFFFFF292, 0x000003E5 },
+       { 0x0213F0FD42CE20A4, 0x0000376E, 0xFFFFE686, 0x000005A6, 0x00001FCF, 0xFFFFF43B, 0x000003A8, 0x00001FCF, 0xFFFFF43B, 0x000003A8 },
+       { 0x0213F0FFEF5A4984, 0x0000485F, 0xFFFFDCC1, 0x00000713, 0x00002CF8, 0xFFFFEC45, 0x000004DA, 0x00002CF8, 0xFFFFEC45, 0x000004DA },
+       { 0x0213F0FFEF5C3184, 0x0000331C, 0xFFFFE8FF, 0x00000541, 0x00002366, 0xFFFFF19D, 0x00000411, 0x00002366, 0xFFFFF19D, 0x00000411 },
+       { 0x0213F0FFEF643864, 0x00003CF3, 0xFFFFE15A, 0x00000694, 0x00002FB3, 0xFFFFE827, 0x000005B9, 0x00002FB3, 0xFFFFE827, 0x000005B9 },
+       { 0x0213EA94DE321104, 0x000023F3, 0xFFFFF3EA, 0x0000039A, 0x00001345, 0xFFFFFD6B, 0x00000241, 0x00001345, 0xFFFFFD6B, 0x00000241 },
+       { 0x0213F0FFEF5C28A4, 0x000038C0, 0xFFFFE58A, 0x000005CC, 0x000023CA, 0xFFFFF1AA, 0x00000408, 0x000023CA, 0xFFFFF1AA, 0x00000408 },
+       { 0x0213F0FFEF662944, 0x00004976, 0xFFFFDD6A, 0x000006D7, 0x000033C6, 0xFFFFE8EB, 0x0000054D, 0x000033C6, 0xFFFFE8EB, 0x0000054D },
+       { 0x0213F0FFEF644904, 0x00004049, 0xFFFFDF6D, 0x000006D8, 0x00003129, 0xFFFFE716, 0x000005E9, 0x00003129, 0xFFFFE716, 0x000005E9 },
+       { 0x0213F0FFEF661164, 0x000046C2, 0xFFFFDCEB, 0x0000071C, 0x00002E6D, 0xFFFFEA8F, 0x0000052E, 0x00002E6D, 0xFFFFEA8F, 0x0000052E },
+       { 0x0213F0FFEF6238A4, 0x00004080, 0xFFFFE1E1, 0x0000063A, 0x0000396D, 0xFFFFE40A, 0x0000062C, 0x0000396D, 0xFFFFE40A, 0x0000062C },
+       { 0x0213F0FFEF5E2124, 0x00003DE0, 0xFFFFE358, 0x0000060C, 0x00002AA2, 0xFFFFEDBF, 0x000004A0, 0x00002AA2, 0xFFFFEDBF, 0x000004A0 },
+       { 0x0213F0FFEF5E3144, 0x00003FC0, 0xFFFFE2A1, 0x0000061A, 0x000027D8, 0xFFFFEFEC, 0x0000043A, 0x000027D8, 0xFFFFEFEC, 0x0000043A },
+       { 0x0213F0FFEF661924, 0x00003FBF, 0xFFFFE2F5, 0x00000603, 0x000032D7, 0xFFFFE900, 0x00000552, 0x000032D7, 0xFFFFE900, 0x00000552 },
+       { 0x0213F0FFEF5C10E4, 0x000035EE, 0xFFFFE6CA, 0x000005A2, 0x0000247C, 0xFFFFF088, 0x00000446, 0x0000247C, 0xFFFFF088, 0x00000446 },
+       { 0x0213F0FFEF643884, 0x000039C8, 0xFFFFE3AE, 0x0000062A, 0x000028AF, 0xFFFFED24, 0x000004DF, 0x000028AF, 0xFFFFED24, 0x000004DF },
+       { 0x0213F0FFEF5C2884, 0x00003BDE, 0xFFFFE33B, 0x00000632, 0x00001B6C, 0xFFFFF720, 0x00000326, 0x00001B6C, 0xFFFFF720, 0x00000326 },
+       { 0x0213F0FFEF7210A4, 0x00003818, 0xFFFFE57D, 0x000005D4, 0x000020EF, 0xFFFFF327, 0x000003CE, 0x000020EF, 0xFFFFF327, 0x000003CE },
+       { 0x0213F0FFEF5E19A4, 0x000038DA, 0xFFFFE561, 0x000005D3, 0x0000297D, 0xFFFFED6D, 0x000004C5, 0x0000297D, 0xFFFFED6D, 0x000004C5 },
+       { 0x0213F0FFEF684884, 0x000027AC, 0xFFFFF0CE, 0x00000417, 0x00001F5F, 0xFFFFF484, 0x000003B2, 0x00001F5F, 0xFFFFF484, 0x000003B2 },
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+       { 0x0213F0FFEF600904, 0x000039E5, 0xFFFFE31F, 0x00000657, 0x00001D23, 0xFFFFF51F, 0x00000386, 0x00001D23, 0xFFFFF51F, 0x00000386 },
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+       { 0x0213EA94DE201864, 0x0000215C, 0xFFFFF5B6, 0x0000036D, 0x000015C5, 0xFFFFFB8A, 0x000002B5, 0x000015C5, 0xFFFFFB8A, 0x000002B5 },
+       { 0x0213F0FFEF683984, 0x00002FAF, 0xFFFFEC27, 0x000004CA, 0x00002184, 0xFFFFF39C, 0x000003CD, 0x00002184, 0xFFFFF39C, 0x000003CD },
+       { 0x0213F0FFEF5E10C4, 0x00004ACE, 0xFFFFD9A3, 0x000007BC, 0x00001A5D, 0xFFFFF7F6, 0x000002FC, 0x00001A5D, 0xFFFFF7F6, 0x000002FC },
+       { 0x0213F0FFEF5A3044, 0x00003763, 0xFFFFE797, 0x0000055F, 0x000029B5, 0xFFFFEEA1, 0x00000474, 0x000029B5, 0xFFFFEEA1, 0x00000474 },
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+       { 0x0213F0FFEF604164, 0x000041C9, 0xFFFFDE33, 0x0000071E, 0x0000199D, 0xFFFFF808, 0x000002F9, 0x0000199D, 0xFFFFF808, 0x000002F9 },
+       { 0x0213F0FFEF641164, 0x0000474A, 0xFFFFD96E, 0x00000802, 0x00002A30, 0xFFFFEB57, 0x0000053F, 0x00002A30, 0xFFFFEB57, 0x0000053F },
+       { 0x0213F0FFEF5C31C4, 0x0000312F, 0xFFFFEA6A, 0x00000508, 0x000029D3, 0xFFFFED38, 0x000004D3, 0x000029D3, 0xFFFFED38, 0x000004D3 },
+       { 0x0213F0FFEF7210C4, 0x00003BD6, 0xFFFFE2E7, 0x00000644, 0x00002093, 0xFFFFF37B, 0x000003BD, 0x00002093, 0xFFFFF37B, 0x000003BD },
+       { 0x0213F0FFEF6840E4, 0x00002F94, 0xFFFFECD4, 0x000004A3, 0x00002196, 0xFFFFF40B, 0x000003B5, 0x00002196, 0xFFFFF40B, 0x000003B5 },
+       { 0x0213F0FFEF5E1944, 0x0000369B, 0xFFFFE762, 0x00000571, 0x00002726, 0xFFFFEF99, 0x00000459, 0x00002726, 0xFFFFEF99, 0x00000459 },
+       { 0x0213F0FFEF642064, 0x00003F57, 0xFFFFDF47, 0x000006F4, 0x00002E5F, 0xFFFFE8AE, 0x000005AB, 0x00002E5F, 0xFFFFE8AE, 0x000005AB },
+       { 0x0213EA94DE0A40C4, 0x00004313, 0xFFFFDD81, 0x0000072D, 0x00002468, 0xFFFFF068, 0x00000440, 0x00002468, 0xFFFFF068, 0x00000440 },
+       { 0x0213F0FFEF683044, 0x00002A35, 0xFFFFEFA8, 0x00000441, 0x00001F3F, 0xFFFFF4F3, 0x000003A0, 0x00001F3F, 0xFFFFF4F3, 0x000003A0 },
+       { 0x0213F0FFEF6630A4, 0x00003E33, 0xFFFFE4B0, 0x000005AF, 0x00002802, 0xFFFFF092, 0x00000412, 0x00002802, 0xFFFFF092, 0x00000412 },
+       { 0x0213EA94DE323904, 0x00002815, 0xFFFFF20E, 0x000003DD, 0x00001C33, 0xFFFFF7D5, 0x0000032A, 0x00001C33, 0xFFFFF7D5, 0x0000032A },
+       { 0x0213F0FFEF5A2184, 0x00003CC2, 0xFFFFE43E, 0x000005DE, 0x00002C16, 0xFFFFECED, 0x000004BA, 0x00002C16, 0xFFFFECED, 0x000004BA },
+       { 0x0213F0FFEF5C4084, 0x00003CFA, 0xFFFFE1EE, 0x00000673, 0x00001F7D, 0xFFFFF402, 0x000003AE, 0x00001F7D, 0xFFFFF402, 0x000003AE },
+       { 0x0213F0FFEF622104, 0x0000486E, 0xFFFFDD43, 0x000006EE, 0x000036F0, 0xFFFFE609, 0x000005D5, 0x000036F0, 0xFFFFE609, 0x000005D5 },
+       { 0x0213F0FFEF5C4964, 0x000039FE, 0xFFFFE41F, 0x00000613, 0x0000266C, 0xFFFFEF35, 0x0000047D, 0x0000266C, 0xFFFFEF35, 0x0000047D },
+       { 0x0213EA94DE123124, 0x00002EA4, 0xFFFFEE3B, 0x00000462, 0x00002126, 0xFFFFF4E2, 0x0000038F, 0x00002126, 0xFFFFF4E2, 0x0000038F },
+       { 0x0213F0FFEF683944, 0x00002D2E, 0xFFFFEE7B, 0x00000462, 0x0000229D, 0xFFFFF363, 0x000003D4, 0x0000229D, 0xFFFFF363, 0x000003D4 },
+       { 0x0213F0FFEF5E2844, 0x0000375C, 0xFFFFE695, 0x0000059D, 0x00002319, 0xFFFFF237, 0x000003EE, 0x00002319, 0xFFFFF237, 0x000003EE },
+       { 0x0213F0FFEF7250C4, 0x00004522, 0xFFFFDC71, 0x0000075E, 0x0000247E, 0xFFFFF0A0, 0x0000043C, 0x0000247E, 0xFFFFF0A0, 0x0000043C },
+       { 0x0213EA94DE1248E4, 0x00002E58, 0xFFFFECB9, 0x000004A9, 0x0000199A, 0xFFFFF8CF, 0x000002E9, 0x0000199A, 0xFFFFF8CF, 0x000002E9 },
+       { 0x0213F0FFEF6438E4, 0x00003791, 0xFFFFE5FE, 0x000005B6, 0x000029F5, 0xFFFFED0D, 0x000004CD, 0x000029F5, 0xFFFFED0D, 0x000004CD },
+       { 0x0213EA94DE244144, 0x00002E9E, 0xFFFFEC8D, 0x000004C1, 0x000019D0, 0xFFFFF869, 0x0000030F, 0x000019D0, 0xFFFFF869, 0x0000030F },
+       { 0x0213EA94DE203964, 0x0000237C, 0xFFFFF435, 0x000003A6, 0x000014EB, 0xFFFFFBC4, 0x000002AF, 0x000014EB, 0xFFFFFBC4, 0x000002AF },
+       { 0x0213F0FFEF662924, 0x00003FE5, 0xFFFFE4A2, 0x000005A0, 0x00003416, 0xFFFFE995, 0x00000523, 0x00003416, 0xFFFFE995, 0x00000523 },
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+       { 0x0213F0FFEF684904, 0x00002D77, 0xFFFFED79, 0x00000494, 0x00002196, 0xFFFFF352, 0x000003DE, 0x00002196, 0xFFFFF352, 0x000003DE },
+       { 0x0213F0FFEF5C20C4, 0x00003750, 0xFFFFE6AC, 0x00000596, 0x00002524, 0xFFFFF0B5, 0x00000431, 0x00002524, 0xFFFFF0B5, 0x00000431 },
+       { 0x0213EA94DE122944, 0x00002896, 0xFFFFF1BB, 0x000003D9, 0x00001CE0, 0xFFFFF753, 0x0000032F, 0x00001CE0, 0xFFFFF753, 0x0000032F },
+       { 0x0213F0FFEF641984, 0x00003CA7, 0xFFFFE0F7, 0x000006B1, 0x00002CB8, 0xFFFFE9AB, 0x00000587, 0x00002CB8, 0xFFFFE9AB, 0x00000587 },
+       { 0x0213EA94DE322864, 0x00002513, 0xFFFFF323, 0x000003BC, 0x00001965, 0xFFFFF93C, 0x000002F0, 0x00001965, 0xFFFFF93C, 0x000002F0 },
+       { 0x0213F0FFEF662164, 0x00003914, 0xFFFFE683, 0x00000586, 0x00003120, 0xFFFFE9A6, 0x00000543, 0x00003120, 0xFFFFE9A6, 0x00000543 },
+       { 0x0213F0FFEF643904, 0x000040D0, 0xFFFFE007, 0x000006AC, 0x00002B9E, 0xFFFFEBF5, 0x000004FB, 0x00002B9E, 0xFFFFEBF5, 0x000004FB },
+       { 0x0213F0FFEF5A4884, 0x00004412, 0xFFFFDF5F, 0x000006A9, 0x00002A9E, 0xFFFFEDCE, 0x00000498, 0x00002A9E, 0xFFFFEDCE, 0x00000498 },
+       { 0x0213F0FFEF624884, 0x000042A6, 0xFFFFDFEF, 0x00000696, 0x00002E65, 0xFFFFEAAE, 0x00000529, 0x00002E65, 0xFFFFEAAE, 0x00000529 },
+       { 0x0213EA94DE322124, 0x000022E8, 0xFFFFF565, 0x0000035F, 0x00001890, 0xFFFFFA61, 0x000002C6, 0x00001890, 0xFFFFFA61, 0x000002C6 },
+       { 0x0213F0FFEF6239A4, 0x00004637, 0xFFFFDDD8, 0x000006E9, 0x0000349D, 0xFFFFE6C8, 0x000005C7, 0x0000349D, 0xFFFFE6C8, 0x000005C7 },
+       { 0x0213EA94DE263904, 0x00004686, 0xFFFFDC58, 0x0000073D, 0x00003972, 0xFFFFE27B, 0x0000068E, 0x00003972, 0xFFFFE27B, 0x0000068E },
+       { 0x0213F0FFEF6808E4, 0x00002B35, 0xFFFFEE9C, 0x0000046C, 0x00001F5B, 0xFFFFF4A3, 0x000003A9, 0x00001F5B, 0xFFFFF4A3, 0x000003A9 },
+       { 0x0213F0FFEF724144, 0x00003AC9, 0xFFFFE3B2, 0x0000061B, 0x000023A1, 0xFFFFF170, 0x0000040F, 0x000023A1, 0xFFFFF170, 0x0000040F },
+       { 0x0213F0FFEF5E1884, 0x00003C50, 0xFFFFE37E, 0x00000617, 0x0000218F, 0xFFFFF339, 0x000003C4, 0x0000218F, 0xFFFFF339, 0x000003C4 },
+       { 0x0213F0FFEF663044, 0x00003793, 0xFFFFE761, 0x0000055D, 0x000029C7, 0xFFFFEE03, 0x00000496, 0x000029C7, 0xFFFFEE03, 0x00000496 },
+       { 0x0213F0FFEF6438A4, 0x000040B5, 0xFFFFDF78, 0x000006DA, 0x00002DED, 0xFFFFEA20, 0x00000551, 0x00002DED, 0xFFFFEA20, 0x00000551 },
+       { 0x0213F0FFEF601144, 0x000039D6, 0xFFFFE37D, 0x0000063C, 0x00001AED, 0xFFFFF6E2, 0x00000331, 0x00001AED, 0xFFFFF6E2, 0x00000331 },
+       { 0x0213F0FFEF662144, 0x0000431F, 0xFFFFE09B, 0x0000066A, 0x00002BDF, 0xFFFFED93, 0x00000496, 0x00002BDF, 0xFFFFED93, 0x00000496 },
+       { 0x0213F0FFEF623864, 0x00004887, 0xFFFFDC65, 0x00000721, 0x00003669, 0xFFFFE5C4, 0x000005E9, 0x00003669, 0xFFFFE5C4, 0x000005E9 },
+       { 0x0213F0FFEF640924, 0x00004120, 0xFFFFDDAE, 0x00000748, 0x0000303B, 0xFFFFE70D, 0x000005FC, 0x0000303B, 0xFFFFE70D, 0x000005FC },
+       { 0x0213F0FFEF5E28A4, 0x0000415D, 0xFFFFE0BE, 0x0000067B, 0x00002FA7, 0xFFFFEA28, 0x00000538, 0x00002FA7, 0xFFFFEA28, 0x00000538 },
+       { 0x0213F0FFEF681904, 0x00002B12, 0xFFFFEFF9, 0x00000428, 0x00001DDA, 0xFFFFF693, 0x00000356, 0x00001DDA, 0xFFFFF693, 0x00000356 },
+       { 0x0213F0FFEF5E3184, 0x00003ED3, 0xFFFFE28D, 0x0000062D, 0x00002B00, 0xFFFFED4E, 0x000004B3, 0x00002B00, 0xFFFFED4E, 0x000004B3 },
+       { 0x0213F0FFEF6250A4, 0x00004218, 0xFFFFE039, 0x0000068F, 0x00002F84, 0xFFFFEA0C, 0x00000541, 0x00002F84, 0xFFFFEA0C, 0x00000541 },
+       { 0x0213F0FFEF5A3844, 0x00003FF5, 0xFFFFE2A3, 0x00000617, 0x00003017, 0xFFFFEA7A, 0x00000520, 0x00003017, 0xFFFFEA7A, 0x00000520 },
+       { 0x0213F0FFEF5A08A4, 0x00004304, 0xFFFFDFCC, 0x0000069E, 0x00002E0C, 0xFFFFEB51, 0x00000505, 0x00002E0C, 0xFFFFEB51, 0x00000505 },
+       { 0x0213F0FFEF641944, 0x00003D3A, 0xFFFFE17F, 0x00000687, 0x0000284C, 0xFFFFED83, 0x000004CD, 0x0000284C, 0xFFFFED83, 0x000004CD },
+       { 0x0213F0FFEF5E40A4, 0x000042F5, 0xFFFFDF76, 0x000006B2, 0x000027B6, 0xFFFFEF72, 0x00000455, 0x000027B6, 0xFFFFEF72, 0x00000455 },
+       { 0x0213F0FFEF5C38C4, 0x00004267, 0xFFFFDF29, 0x000006D5, 0x0000298F, 0xFFFFEDBD, 0x000004AC, 0x0000298F, 0xFFFFEDBD, 0x000004AC },
+       { 0x0213EA94DE240924, 0x0000303E, 0xFFFFEC00, 0x000004CB, 0x000021CD, 0xFFFFF36E, 0x000003D6, 0x000021CD, 0xFFFFF36E, 0x000003D6 },
+       { 0x0213F0FFEF5E28C4, 0x00003127, 0xFFFFEBDB, 0x000004A6, 0x00002E95, 0xFFFFEB78, 0x000004F3, 0x00002E95, 0xFFFFEB78, 0x000004F3 },
+       { 0x0213EA94DE1C1064, 0x00002655, 0xFFFFF2D9, 0x000003CF, 0x000019F5, 0xFFFFF8E7, 0x00000313, 0x000019F5, 0xFFFFF8E7, 0x00000313 },
+       { 0x0213EA94DE164084, 0x00002372, 0xFFFFF449, 0x0000039B, 0x00001544, 0xFFFFFC16, 0x0000028B, 0x00001544, 0xFFFFFC16, 0x0000028B },
+       { 0x0213F0FFEF6628C4, 0x0000348E, 0xFFFFEB20, 0x000004B2, 0x00002BE8, 0xFFFFEE80, 0x00000467, 0x00002BE8, 0xFFFFEE80, 0x00000467 },
+       { 0x0213F0FFEF5E1104, 0x00004092, 0xFFFFE073, 0x0000069B, 0x00002061, 0xFFFFF403, 0x000003A0, 0x00002061, 0xFFFFF403, 0x000003A0 },
+       { 0x0213F0FFEF7220E4, 0x000039D1, 0xFFFFE55D, 0x000005CC, 0x000025CB, 0xFFFFF0C0, 0x00000428, 0x000025CB, 0xFFFFF0C0, 0x00000428 },
+       { 0x0213F0FFEF5E4884, 0x000042AA, 0xFFFFDF68, 0x000006C2, 0x0000290B, 0xFFFFEE78, 0x00000485, 0x0000290B, 0xFFFFEE78, 0x00000485 },
+       { 0x0213F0FFEF7218C4, 0x0000356F, 0xFFFFE7AC, 0x0000056E, 0x00001BE8, 0xFFFFF6E3, 0x0000032A, 0x00001BE8, 0xFFFFF6E3, 0x0000032A },
+       { 0x0213F0FFEF5E1144, 0x00003525, 0xFFFFE7FF, 0x0000055D, 0x0000242C, 0xFFFFF12E, 0x0000041D, 0x0000242C, 0xFFFFF12E, 0x0000041D },
+       { 0x0213F0FFEF5C48C4, 0x00003360, 0xFFFFE895, 0x00000550, 0x00002175, 0xFFFFF29E, 0x000003E9, 0x00002175, 0xFFFFF29E, 0x000003E9 },
+       { 0x0213F0FFEF6440A4, 0x00003C94, 0xFFFFE1C4, 0x0000067E, 0x00002E28, 0xFFFFE964, 0x0000057F, 0x00002E28, 0xFFFFE964, 0x0000057F },
+       { 0x0213F0FFEF724124, 0x0000431C, 0xFFFFDE4B, 0x000006FF, 0x00002270, 0xFFFFF268, 0x000003E5, 0x00002270, 0xFFFFF268, 0x000003E5 },
+       { 0x0213EA94DE1218C4, 0x00002B67, 0xFFFFF01D, 0x00000414, 0x000019FB, 0xFFFFF961, 0x000002D8, 0x000019FB, 0xFFFFF961, 0x000002D8 },
+       { 0x0213F0FFEF5E3984, 0x0000400B, 0xFFFFE13D, 0x0000066F, 0x000024F3, 0xFFFFF125, 0x00000417, 0x000024F3, 0xFFFFF125, 0x00000417 },
+       { 0x0213F0FFEF5A20A4, 0x00004460, 0xFFFFE00E, 0x0000067B, 0x000023DF, 0xFFFFF2E6, 0x000003BB, 0x000023DF, 0xFFFFF2E6, 0x000003BB },
+       { 0x0213F0FFEF641864, 0x00003AFB, 0xFFFFE2C5, 0x00000650, 0x00002D46, 0xFFFFE9C4, 0x00000571, 0x00002D46, 0xFFFFE9C4, 0x00000571 },
+       { 0x0213F0FFEF622924, 0x00005482, 0xFFFFD5BC, 0x0000081A, 0x00003250, 0xFFFFE961, 0x00000541, 0x00003250, 0xFFFFE961, 0x00000541 },
+       { 0x0213F0FFEF5C2944, 0x00003D27, 0xFFFFE2FA, 0x00000632, 0x00002A4D, 0xFFFFED6A, 0x000004BB, 0x00002A4D, 0xFFFFED6A, 0x000004BB },
+       { 0x0213F0FFEF6018A4, 0x00003E03, 0xFFFFE142, 0x00000690, 0x00001E08, 0xFFFFF555, 0x0000036C, 0x00001E08, 0xFFFFF555, 0x0000036C },
+       { 0x0213F0FFEF5C2064, 0x000031B5, 0xFFFFE97D, 0x00000535, 0x0000232E, 0xFFFFF166, 0x00000422, 0x0000232E, 0xFFFFF166, 0x00000422 },
+       { 0x0213F0FFEF5E18E4, 0x00003753, 0xFFFFE724, 0x00000575, 0x0000281A, 0xFFFFEF1A, 0x0000046B, 0x0000281A, 0xFFFFEF1A, 0x0000046B },
+       { 0x0213EA94DE204144, 0x00002071, 0xFFFFF5C9, 0x0000036F, 0x00001470, 0xFFFFFBF7, 0x000002A5, 0x00001470, 0xFFFFFBF7, 0x000002A5 },
+       { 0x0213F0FFEF683144, 0x00002799, 0xFFFFF223, 0x000003CF, 0x00001CD3, 0xFFFFF74A, 0x00000333, 0x00001CD3, 0xFFFFF74A, 0x00000333 },
+       { 0x0213F0FFEF6610C4, 0x000040DF, 0xFFFFE11C, 0x00000664, 0x000031D4, 0xFFFFE8BC, 0x0000056F, 0x000031D4, 0xFFFFE8BC, 0x0000056F },
+       { 0x0213F0FFEF6440C4, 0x00003A4D, 0xFFFFE3A6, 0x00000627, 0x00002871, 0xFFFFEDA0, 0x000004C0, 0x00002871, 0xFFFFEDA0, 0x000004C0 },
+       { 0x0213F0FFEF681984, 0x00002AF9, 0xFFFFEED7, 0x00000464, 0x0000219B, 0xFFFFF368, 0x000003D6, 0x0000219B, 0xFFFFF368, 0x000003D6 },
+       { 0x0213EA94DE323124, 0x000026D5, 0xFFFFF36C, 0x000003A3, 0x00001BC6, 0xFFFFF881, 0x00000311, 0x00001BC6, 0xFFFFF881, 0x00000311 },
+       { 0x0213F0FFEF5E2044, 0x0000325D, 0xFFFFEA07, 0x0000050B, 0x000026D1, 0xFFFFEFB3, 0x0000045A, 0x000026D1, 0xFFFFEFB3, 0x0000045A },
+       { 0x0213F0FFEF682864, 0x00002F75, 0xFFFFEC64, 0x000004BE, 0x00001EEB, 0xFFFFF559, 0x00000386, 0x00001EEB, 0xFFFFF559, 0x00000386 },
+       { 0x0213F0FFEF5A38A4, 0x00003C2F, 0xFFFFE541, 0x000005A3, 0x000025B6, 0xFFFFF16F, 0x000003FA, 0x000025B6, 0xFFFFF16F, 0x000003FA },
+       { 0x0213F0FFEF684924, 0x00002BC2, 0xFFFFEE89, 0x0000046A, 0x00001D04, 0xFFFFF651, 0x00000361, 0x00001D04, 0xFFFFF651, 0x00000361 },
+       { 0x0213F0FFEF6829A4, 0x00002DD0, 0xFFFFED40, 0x0000049F, 0x00001C8C, 0xFFFFF6B3, 0x00000353, 0x00001C8C, 0xFFFFF6B3, 0x00000353 },
+       { 0x0213EA94DE1C08E4, 0x000021ED, 0xFFFFF530, 0x00000380, 0x00001643, 0xFFFFFB1C, 0x000002C3, 0x00001643, 0xFFFFFB1C, 0x000002C3 },
+       { 0x0213EA94DE321904, 0x000028C7, 0xFFFFF160, 0x000003FD, 0x00001990, 0xFFFFF994, 0x000002E2, 0x00001990, 0xFFFFF994, 0x000002E2 },
+       { 0x0213F0FFEF6610A4, 0x0000431C, 0xFFFFDF9D, 0x000006A3, 0x000034A6, 0xFFFFE6B0, 0x000005C9, 0x000034A6, 0xFFFFE6B0, 0x000005C9 },
+       { 0x0213EA94DE2630A4, 0x00004115, 0xFFFFE0D6, 0x00000667, 0x000031AD, 0xFFFFE850, 0x00000585, 0x000031AD, 0xFFFFE850, 0x00000585 },
+       { 0x0213F0FFEF643924, 0x0000424A, 0xFFFFDEEC, 0x000006E1, 0x0000346A, 0xFFFFE5EA, 0x00000602, 0x0000346A, 0xFFFFE5EA, 0x00000602 },
+       { 0x0213F0FFEF661984, 0x00004990, 0xFFFFDAFA, 0x00000771, 0x00002A9C, 0xFFFFED37, 0x000004BC, 0x00002A9C, 0xFFFFED37, 0x000004BC },
+       { 0x0213F0FFEF6428A4, 0x00003858, 0xFFFFE568, 0x000005D2, 0x00003030, 0xFFFFE8B0, 0x0000058E, 0x00003030, 0xFFFFE8B0, 0x0000058E },
+       { 0x0213F0FFEF684164, 0x00001EDC, 0xFFFFF6CD, 0x00000322, 0x00001FCA, 0xFFFFF4BD, 0x0000039E, 0x00001FCA, 0xFFFFF4BD, 0x0000039E },
+       { 0x0213F0FFEF662124, 0x00004C88, 0xFFFFDBA3, 0x0000071B, 0x000030C4, 0xFFFFEAFD, 0x000004F7, 0x000030C4, 0xFFFFEAFD, 0x000004F7 },
+       { 0x0213F0FFEF680904, 0x00002B9A, 0xFFFFEE41, 0x0000047D, 0x00002131, 0xFFFFF344, 0x000003E5, 0x00002131, 0xFFFFF344, 0x000003E5 },
+       { 0x0213F0FFEF623984, 0x00003E4B, 0xFFFFE33C, 0x000005FA, 0x00003877, 0xFFFFE437, 0x0000062E, 0x00003877, 0xFFFFE437, 0x0000062E },
+       { 0x0213EA94DE322064, 0x00002376, 0xFFFFF444, 0x0000038A, 0x000017ED, 0xFFFFFA4C, 0x000002C1, 0x000017ED, 0xFFFFFA4C, 0x000002C1 },
+       { 0x0213F0FFEF661084, 0x00004517, 0xFFFFDDF4, 0x000006F2, 0x000030DC, 0xFFFFE8EF, 0x00000571, 0x000030DC, 0xFFFFE8EF, 0x00000571 },
+       { 0x0213F0FFEF681944, 0x0000270C, 0xFFFFF1F3, 0x000003DF, 0x0000207B, 0xFFFFF474, 0x000003AD, 0x0000207B, 0xFFFFF474, 0x000003AD },
+       { 0x0213F0FFEF645144, 0x00004086, 0xFFFFDF39, 0x000006E3, 0x00002A24, 0xFFFFEC2B, 0x000004FF, 0x00002A24, 0xFFFFEC2B, 0x000004FF },
+       { 0x0213F0FFEF5C3124, 0x00003BDE, 0xFFFFE45E, 0x000005EB, 0x00002CD5, 0xFFFFEC45, 0x000004DD, 0x00002CD5, 0xFFFFEC45, 0x000004DD },
+       { 0x0213F0FFEF7230E4, 0x00003803, 0xFFFFE714, 0x00000579, 0x0000288A, 0xFFFFEF21, 0x0000046B, 0x0000288A, 0xFFFFEF21, 0x0000046B },
+       { 0x0213F0FFEF601104, 0x00003F50, 0xFFFFE002, 0x000006CD, 0x00001AD4, 0xFFFFF72E, 0x0000031F, 0x00001AD4, 0xFFFFF72E, 0x0000031F },
+       { 0x0213F0FFEF6820E4, 0x00002968, 0xFFFFF100, 0x00000402, 0x00001FB5, 0xFFFFF57C, 0x0000037F, 0x00001FB5, 0xFFFFF57C, 0x0000037F },
+       { 0x0213F0FFEF662104, 0x00004283, 0xFFFFE2A7, 0x000005F5, 0x00003165, 0xFFFFEB0C, 0x000004EC, 0x00003165, 0xFFFFEB0C, 0x000004EC },
+       { 0x0213F0FFEF6431A4, 0x00004253, 0xFFFFDDA8, 0x00000732, 0x00002E5C, 0xFFFFE90A, 0x00000593, 0x00002E5C, 0xFFFFE90A, 0x00000593 },
+       { 0x0213F0FFEF5C50A4, 0x00003551, 0xFFFFE756, 0x0000058D, 0x000029A7, 0xFFFFED0C, 0x000004DE, 0x000029A7, 0xFFFFED0C, 0x000004DE },
+       { 0x0213F0FFEF6428C4, 0x00003728, 0xFFFFE604, 0x000005C4, 0x00002832, 0xFFFFEE64, 0x00000493, 0x00002832, 0xFFFFEE64, 0x00000493 },
+       { 0x0213F0FFEF623964, 0x00004796, 0xFFFFDCC8, 0x00000715, 0x000032AB, 0xFFFFE848, 0x0000057C, 0x000032AB, 0xFFFFE848, 0x0000057C },
+       { 0x0213F0FFEF6210C4, 0x000049DF, 0xFFFFDB24, 0x0000075F, 0x00003076, 0xFFFFE967, 0x0000055C, 0x00003076, 0xFFFFE967, 0x0000055C },
+       { 0x0213F0FFEF721104, 0x00003F13, 0xFFFFE099, 0x000006A8, 0x00002279, 0xFFFFF226, 0x000003F3, 0x00002279, 0xFFFFF226, 0x000003F3 },
+       { 0x0213F0FFEF6430A4, 0x00003E03, 0xFFFFE19F, 0x00000674, 0x00002D66, 0xFFFFEAA7, 0x00000537, 0x00002D66, 0xFFFFEAA7, 0x00000537 },
+       { 0x0213F0FFEF5C4104, 0x000037DA, 0xFFFFE63F, 0x000005A7, 0x00002543, 0xFFFFF0A0, 0x00000431, 0x00002543, 0xFFFFF0A0, 0x00000431 },
+       { 0x0213F0FFEF624944, 0x00003D82, 0xFFFFE3F5, 0x000005D9, 0x0000332F, 0xFFFFE834, 0x00000577, 0x0000332F, 0xFFFFE834, 0x00000577 },
+       { 0x0213EA94DE1228C4, 0x00002915, 0xFFFFF1E0, 0x000003D4, 0x00002065, 0xFFFFF57B, 0x00000378, 0x00002065, 0xFFFFF57B, 0x00000378 },
+       { 0x0213F0FFEF5E4904, 0x000036FC, 0xFFFFE72D, 0x00000577, 0x00002811, 0xFFFFEF30, 0x00000464, 0x00002811, 0xFFFFEF30, 0x00000464 },
+       { 0x0213F0FFEF623184, 0x00004767, 0xFFFFDD30, 0x000006FD, 0x00003703, 0xFFFFE564, 0x000005F8, 0x00003703, 0xFFFFE564, 0x000005F8 },
+       { 0x0213F0FFEF603184, 0x00003094, 0xFFFFEAA9, 0x000004F5, 0x000022E7, 0xFFFFF200, 0x000003FB, 0x000022E7, 0xFFFFF200, 0x000003FB },
+       { 0x0213F0FFEF641144, 0x00003EF0, 0xFFFFDF83, 0x000006ED, 0x00002A27, 0xFFFFEB7C, 0x00000537, 0x00002A27, 0xFFFFEB7C, 0x00000537 },
+       { 0x0213F0FFEF681124, 0x0000243C, 0xFFFFF358, 0x000003AC, 0x00001DC4, 0xFFFFF5E9, 0x00000372, 0x00001DC4, 0xFFFFF5E9, 0x00000372 },
+       { 0x0213F0FFEF722144, 0x0000284B, 0xFFFFF036, 0x0000040F, 0x00001FCD, 0xFFFFF445, 0x00000395, 0x00001FCD, 0xFFFFF445, 0x00000395 },
+       { 0x0213F0FFEF6840C4, 0x00002611, 0xFFFFF285, 0x000003C7, 0x00001CFE, 0xFFFFF6A0, 0x00000355, 0x00001CFE, 0xFFFFF6A0, 0x00000355 },
+       { 0x0213EA94DE1C39A4, 0x00002292, 0xFFFFF49F, 0x00000393, 0x000017F4, 0xFFFFF9CD, 0x000002F5, 0x000017F4, 0xFFFFF9CD, 0x000002F5 },
+       { 0x0213F0FFEF5E38A4, 0x000037F3, 0xFFFFE68D, 0x00000590, 0x00002443, 0xFFFFF1AD, 0x000003FA, 0x00002443, 0xFFFFF1AD, 0x000003FA },
+       { 0x0213F0FFEF682144, 0x00002C01, 0xFFFFEF3F, 0x00000444, 0x0000210A, 0xFFFFF475, 0x000003A7, 0x0000210A, 0xFFFFF475, 0x000003A7 },
+       { 0x0213EA94DE1210E4, 0x00002C0E, 0xFFFFEF0F, 0x00000446, 0x00001A82, 0xFFFFF8F7, 0x000002DE, 0x00001A82, 0xFFFFF8F7, 0x000002DE },
+       { 0x0213F0FFEF5E20C4, 0x00003FA6, 0xFFFFE20A, 0x0000063F, 0x00002E29, 0xFFFFEB21, 0x00000510, 0x00002E29, 0xFFFFEB21, 0x00000510 },
+       { 0x0213F0FFEF5C2164, 0x00003BCD, 0xFFFFE31B, 0x0000063C, 0x000019AF, 0xFFFFF83D, 0x000002F8, 0x000019AF, 0xFFFFF83D, 0x000002F8 },
+       { 0x0213F0FFEF664164, 0x000044C8, 0xFFFFDF08, 0x000006B0, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00002E2E, 0xFFFFEB62, 0x000004FD },
+       { 0x0213F0FFEF5C1884, 0x00003790, 0xFFFFE571, 0x000005E3, 0x00002042, 0xFFFFF35D, 0x000003CF, 0x00002042, 0xFFFFF35D, 0x000003CF },
+       { 0x0213F0FFEF6050E4, 0x000038AC, 0xFFFFE46C, 0x00000609, 0x0000215E, 0xFFFFF22D, 0x00000403, 0x0000215E, 0xFFFFF22D, 0x00000403 },
+       { 0x0213F0FFEF5E29A4, 0x00003A1E, 0xFFFFE536, 0x000005C9, 0x000024F3, 0xFFFFF11A, 0x0000041B, 0x000024F3, 0xFFFFF11A, 0x0000041B },
+       { 0x0213F0FFEF6650E4, 0x0000431A, 0xFFFFDF1B, 0x000006C5, 0x00002F34, 0xFFFFEA02, 0x00000545, 0x00002F34, 0xFFFFEA02, 0x00000545 },
+       { 0x0213F0FFEF641904, 0x000042DC, 0xFFFFDE28, 0x0000070C, 0x00003B53, 0xFFFFE0EA, 0x000006E2, 0x00003B53, 0xFFFFE0EA, 0x000006E2 },
+       { 0x0213F0FFEF683164, 0x0000264B, 0xFFFFF29A, 0x000003C4, 0x000021D0, 0xFFFFF3CE, 0x000003C4, 0x000021D0, 0xFFFFF3CE, 0x000003C4 },
+       { 0x0213F0FFEF5A4064, 0x00004225, 0xFFFFE0E8, 0x00000665, 0x00002B53, 0xFFFFED89, 0x0000049F, 0x00002B53, 0xFFFFED89, 0x0000049F },
+       { 0x0213EA94DE204924, 0x00001FCC, 0xFFFFF63F, 0x00000358, 0x000019E8, 0xFFFFF882, 0x0000032A, 0x000019E8, 0xFFFFF882, 0x0000032A },
+       { 0x0213F0FFEF6240A4, 0x000045E0, 0xFFFFDDD0, 0x000006ED, 0x00003193, 0xFFFFE8BD, 0x00000572, 0x00003193, 0xFFFFE8BD, 0x00000572 },
+       { 0x0213F0FFEF683924, 0x000024FC, 0xFFFFF366, 0x000003A6, 0x00001FE8, 0xFFFFF509, 0x00000394, 0x00001FE8, 0xFFFFF509, 0x00000394 },
+       { 0x0213F0FFEF5C4884, 0x0000378F, 0xFFFFE54B, 0x000005F1, 0x00001C9B, 0xFFFFF5C7, 0x00000368, 0x00001C9B, 0xFFFFF5C7, 0x00000368 },
+       { 0x0213F0FFEF6418A4, 0x00003CF3, 0xFFFFE15A, 0x00000694, 0x00002CDD, 0xFFFFEA44, 0x00000557, 0x00002CDD, 0xFFFFEA44, 0x00000557 },
+       { 0x0213EA94DE200904, 0x000021EC, 0xFFFFF4F4, 0x0000038F, 0x00001511, 0xFFFFFBF5, 0x0000029E, 0x00001511, 0xFFFFFBF5, 0x0000029E },
+       { 0x0213F0FFEF6010A4, 0x00003C8A, 0xFFFFE1C1, 0x00000685, 0x000019C7, 0xFFFFF7E2, 0x00000301, 0x000019C7, 0xFFFFF7E2, 0x00000301 },
+       { 0x0213F0FFEF5E2064, 0x00003908, 0xFFFFE5C7, 0x000005B3, 0x00002793, 0xFFFFEF46, 0x00000465, 0x00002793, 0xFFFFEF46, 0x00000465 },
+       { 0x0213F0FFEF605104, 0x000040A3, 0xFFFFDE61, 0x00000725, 0x00002077, 0xFFFFF2CE, 0x000003E8, 0x00002077, 0xFFFFF2CE, 0x000003E8 },
+       { 0x0213F0FFEF664144, 0x00003DCA, 0xFFFFE34D, 0x00000608, 0x00002D66, 0xFFFFEBDF, 0x000004E8, 0x00002D66, 0xFFFFEBDF, 0x000004E8 },
+       { 0x0213F0FFEF5E50C4, 0x00003085, 0xFFFFEB70, 0x000004C8, 0x000029B1, 0xFFFFEDD9, 0x000004A5, 0x000029B1, 0xFFFFEDD9, 0x000004A5 },
+       { 0x0213EA94DE083884, 0x00004C73, 0xFFFFD676, 0x0000086C, 0x0000280A, 0xFFFFED89, 0x000004C2, 0x0000280A, 0xFFFFED89, 0x000004C2 },
+       { 0x0213EA94DE242164, 0x00002CE5, 0xFFFFEE8C, 0x00000466, 0x00001755, 0xFFFFFAC2, 0x000002AC, 0x00001755, 0xFFFFFAC2, 0x000002AC },
+       { 0x0213F0FFEF621124, 0x0000489F, 0xFFFFDBF1, 0x0000073E, 0x0000332D, 0xFFFFE786, 0x000005AD, 0x0000332D, 0xFFFFE786, 0x000005AD },
+       { 0x0213F0FFEF602864, 0x00003D09, 0xFFFFE193, 0x00000689, 0x00001E82, 0xFFFFF4C0, 0x00000386, 0x00001E82, 0xFFFFF4C0, 0x00000386 },
+       { 0x0213F0FFEF644104, 0x00003E4C, 0xFFFFE131, 0x00000689, 0x00002F4E, 0xFFFFE925, 0x0000057B, 0x00002F4E, 0xFFFFE925, 0x0000057B },
+       { 0x0213F0FFEF5A4084, 0x00003B31, 0xFFFFE53F, 0x000005B3, 0x0000248A, 0xFFFFF211, 0x000003DF, 0x0000248A, 0xFFFFF211, 0x000003DF },
+       { 0x0213F0FFEF644124, 0x000038DD, 0xFFFFE54A, 0x000005C9, 0x00002B6D, 0xFFFFEBDF, 0x00000502, 0x00002B6D, 0xFFFFEBDF, 0x00000502 },
+       { 0x0213F0FFEF684064, 0x00002698, 0xFFFFF1A8, 0x000003F2, 0x00002163, 0xFFFFF34B, 0x000003E3, 0x00002163, 0xFFFFF34B, 0x000003E3 },
+       { 0x0213EA94DE201064, 0x000023A8, 0xFFFFF4CD, 0x00000386, 0x00001944, 0xFFFFF983, 0x00000300, 0x00001944, 0xFFFFF983, 0x00000300 },
+       { 0x0213F0FFEF6418C4, 0x00003EAF, 0xFFFFE0C3, 0x000006A0, 0x000030AB, 0xFFFFE829, 0x000005A6, 0x000030AB, 0xFFFFE829, 0x000005A6 },
+       { 0x0213F0FFEF684944, 0x00002E89, 0xFFFFECA6, 0x000004B6, 0x00001FA0, 0xFFFFF4A8, 0x000003A3, 0x00001FA0, 0xFFFFF4A8, 0x000003A3 },
+       { 0x0213F0FFEF6828A4, 0x000028A4, 0xFFFFF112, 0x00000402, 0x00001F7C, 0xFFFFF545, 0x0000038A, 0x00001F7C, 0xFFFFF545, 0x0000038A },
+       { 0x0213F0FFEF6650A4, 0x00004135, 0xFFFFDFA2, 0x000006C5, 0x0000324C, 0xFFFFE7AA, 0x000005AF, 0x0000324C, 0xFFFFE7AA, 0x000005AF },
+       { 0x0213EA94DE2038C4, 0x00002012, 0xFFFFF693, 0x00000352, 0x0000171F, 0xFFFFFABB, 0x000002D9, 0x0000171F, 0xFFFFFABB, 0x000002D9 },
+       { 0x0213F0FFEF643084, 0x00003D7C, 0xFFFFE1BC, 0x00000671, 0x00002A45, 0xFFFFEC84, 0x000004EC, 0x00002A45, 0xFFFFEC84, 0x000004EC },
+       { 0x0213F0FFEF723064, 0x00004172, 0xFFFFDF58, 0x000006DA, 0x00002504, 0xFFFFF0A6, 0x00000431, 0x00002504, 0xFFFFF0A6, 0x00000431 },
+       { 0x0213F0FE99281944, 0x000029C7, 0xFFFFF087, 0x00000414, 0x00001DCB, 0xFFFFF675, 0x0000035F, 0x00001DCB, 0xFFFFF675, 0x0000035F },
+       { 0x0213F0FE992A29A4, 0x000027F0, 0xFFFFF05A, 0x00000432, 0x00001707, 0xFFFFFA0E, 0x000002D1, 0x00001707, 0xFFFFFA0E, 0x000002D1 },
+       { 0x0213F0FE99222144, 0x00003279, 0xFFFFE9F7, 0x00000511, 0x00001B5E, 0xFFFFF787, 0x00000317, 0x00001B5E, 0xFFFFF787, 0x00000317 },
+       { 0x0213F0FE99322184, 0x000030A5, 0xFFFFEABC, 0x000004FF, 0x000019D1, 0xFFFFF83C, 0x00000304, 0x000019D1, 0xFFFFF83C, 0x00000304 },
+       { 0x0213F0FE99282844, 0x0000283B, 0xFFFFF122, 0x00000402, 0x000019C2, 0xFFFFF8E9, 0x000002FB, 0x000019C2, 0xFFFFF8E9, 0x000002FB },
+       { 0x0213F0FE992C2084, 0x00003376, 0xFFFFE9E1, 0x00000510, 0x000021A7, 0xFFFFF39F, 0x000003BF, 0x000021A7, 0xFFFFF39F, 0x000003BF },
+       { 0x0213F0FE993218C4, 0x000031D2, 0xFFFFEA9C, 0x000004FC, 0x00001F66, 0xFFFFF4E4, 0x00000390, 0x00001F66, 0xFFFFF4E4, 0x00000390 },
+       { 0x0213F0FE991A3864, 0x00003006, 0xFFFFEB18, 0x000004F2, 0x000019B3, 0xFFFFF84E, 0x00000301, 0x000019B3, 0xFFFFF84E, 0x00000301 },
+       { 0x0213F0FE993039A4, 0x0000364F, 0xFFFFE81F, 0x00000556, 0x00002AC9, 0xFFFFED87, 0x000004BD, 0x00002AC9, 0xFFFFED87, 0x000004BD },
+       { 0x0213F0FE992E3844, 0x00003043, 0xFFFFEBAE, 0x000004CD, 0x00001B0C, 0xFFFFF7ED, 0x0000030C, 0x00001B0C, 0xFFFFF7ED, 0x0000030C },
+       { 0x0213F0FE993048A4, 0x000037CE, 0xFFFFE69E, 0x00000596, 0x0000276B, 0xFFFFEF65, 0x0000046E, 0x0000276B, 0xFFFFEF65, 0x0000046E },
+       { 0x0213F0FE992C3104, 0x00003063, 0xFFFFED5E, 0x0000046F, 0x000024AE, 0xFFFFF2C4, 0x000003D8, 0x000024AE, 0xFFFFF2C4, 0x000003D8 },
+       { 0x0213F0FE992E08A4, 0x00002F5D, 0xFFFFEBDC, 0x000004D3, 0x00001EDB, 0xFFFFF50F, 0x0000038E, 0x00001EDB, 0xFFFFF50F, 0x0000038E },
+       { 0x0213F0FE992E48A4, 0x00003148, 0xFFFFEA9A, 0x000004FB, 0x0000192D, 0xFFFFF8E9, 0x000002DF, 0x0000192D, 0xFFFFF8E9, 0x000002DF },
+       { 0x0213F0FE992C2064, 0x00003682, 0xFFFFE7E4, 0x0000055C, 0x0000250E, 0xFFFFF150, 0x0000041A, 0x0000250E, 0xFFFFF150, 0x0000041A },
+       { 0x0213F0FE992A2084, 0x0000284E, 0xFFFFF15A, 0x000003F8, 0x00001CE2, 0xFFFFF6F9, 0x0000034F, 0x00001CE2, 0xFFFFF6F9, 0x0000034F },
+       { 0x0213F0FE993018A4, 0x00003171, 0xFFFFEAE9, 0x000004ED, 0x00001F40, 0xFFFFF513, 0x00000384, 0x00001F40, 0xFFFFF513, 0x00000384 },
+       { 0x0213F0FE99323044, 0x000031BD, 0xFFFFEA64, 0x0000050A, 0x00001EFD, 0xFFFFF4F7, 0x00000390, 0x00001EFD, 0xFFFFF4F7, 0x00000390 },
+       { 0x0213F0FE992E50E4, 0x00003050, 0xFFFFEB29, 0x000004EA, 0x000019B3, 0xFFFFF878, 0x000002F9, 0x000019B3, 0xFFFFF878, 0x000002F9 },
+       { 0x0213F0FE992C1904, 0x00003400, 0xFFFFE9A0, 0x0000051A, 0x00002460, 0xFFFFF1DA, 0x00000409, 0x00002460, 0xFFFFF1DA, 0x00000409 },
+       { 0x0213F0FE992C4884, 0x000034A1, 0xFFFFE86F, 0x00000558, 0x0000255D, 0xFFFFF09E, 0x00000443, 0x0000255D, 0xFFFFF09E, 0x00000443 },
+       { 0x0213F0FE992E48E4, 0x00003103, 0xFFFFEAD7, 0x000004F0, 0x00001896, 0xFFFFF95A, 0x000002CC, 0x00001896, 0xFFFFF95A, 0x000002CC },
+       { 0x0213F0FE993018E4, 0x00003120, 0xFFFFEB9E, 0x000004CB, 0x000021E8, 0xFFFFF3A2, 0x000003C1, 0x000021E8, 0xFFFFF3A2, 0x000003C1 },
+       { 0x0213F0FE991C50E4, 0x00003558, 0xFFFFE812, 0x00000565, 0x0000256E, 0xFFFFF097, 0x00000447, 0x0000256E, 0xFFFFF097, 0x00000447 },
+       { 0x0213F0FE991A2844, 0x00002DA8, 0xFFFFECA8, 0x000004B7, 0x0000180B, 0xFFFFF96D, 0x000002D8, 0x0000180B, 0xFFFFF96D, 0x000002D8 },
+       { 0x0213F0FE992E3064, 0x00003232, 0xFFFFEA66, 0x000004FF, 0x00001DDE, 0xFFFFF5FE, 0x0000035A, 0x00001DDE, 0xFFFFF5FE, 0x0000035A },
+       { 0x0213F0FE993050E4, 0x000034D2, 0xFFFFE89F, 0x00000548, 0x0000246C, 0xFFFFF17F, 0x00000418, 0x0000246C, 0xFFFFF17F, 0x00000418 },
+       { 0x0213F0FE99304904, 0x000033EC, 0xFFFFE954, 0x0000052A, 0x00002323, 0xFFFFF279, 0x000003EE, 0x00002323, 0xFFFFF279, 0x000003EE },
+       { 0x0213F0FE99303884, 0x000033AA, 0xFFFFE955, 0x0000052D, 0x0000229F, 0xFFFFF2B2, 0x000003E7, 0x0000229F, 0xFFFFF2B2, 0x000003E7 },
+       { 0x0213F0FE99324964, 0x00003258, 0xFFFFE9AA, 0x0000052A, 0x00001D5F, 0xFFFFF5D1, 0x0000036B, 0x00001D5F, 0xFFFFF5D1, 0x0000036B },
+       { 0x0213F0FE993029A4, 0x0000323A, 0xFFFFEA5F, 0x00000504, 0x00002108, 0xFFFFF3D5, 0x000003BA, 0x00002108, 0xFFFFF3D5, 0x000003BA },
+       { 0x0213F0FE992C2184, 0x00003216, 0xFFFFEA6B, 0x000004FF, 0x00001D6E, 0xFFFFF640, 0x00000350, 0x00001D6E, 0xFFFFF640, 0x00000350 },
+       { 0x0213F0FE993210E4, 0x000030C5, 0xFFFFEAC4, 0x000004FC, 0x00001924, 0xFFFFF8C2, 0x000002EE, 0x00001924, 0xFFFFF8C2, 0x000002EE },
+       { 0x0213F0FE99305104, 0x000032BB, 0xFFFFE9F1, 0x00000515, 0x00002211, 0xFFFFF31B, 0x000003D5, 0x00002211, 0xFFFFF31B, 0x000003D5 },
+       { 0x0213F0FE993048C4, 0x0000352C, 0xFFFFE85B, 0x00000553, 0x00002410, 0xFFFFF1B4, 0x0000040F, 0x00002410, 0xFFFFF1B4, 0x0000040F },
+       { 0x0213F0FE992238C4, 0x000036A0, 0xFFFFE7E8, 0x0000055D, 0x00002901, 0xFFFFEEB8, 0x00000489, 0x00002901, 0xFFFFEEB8, 0x00000489 },
+       { 0x0213F0FE992C3044, 0x00003340, 0xFFFFE9D9, 0x00000516, 0x00002332, 0xFFFFF27A, 0x000003F0, 0x00002332, 0xFFFFF27A, 0x000003F0 },
+       { 0x0213F0FE991A38A4, 0x00003564, 0xFFFFE86D, 0x0000054E, 0x00002613, 0xFFFFF07C, 0x00000444, 0x00002613, 0xFFFFF07C, 0x00000444 },
+       { 0x0213F0FE99280904, 0x00002AD1, 0xFFFFEF0B, 0x0000045C, 0x00001DEA, 0xFFFFF5C8, 0x00000381, 0x00001DEA, 0xFFFFF5C8, 0x00000381 },
+       { 0x0213F0FE992220E4, 0x000035B0, 0xFFFFE846, 0x00000555, 0x000027BE, 0xFFFFEF5D, 0x00000474, 0x000027BE, 0xFFFFEF5D, 0x00000474 },
+       { 0x0213F0FE992238A4, 0x000032C4, 0xFFFFEA48, 0x00000502, 0x000022C6, 0xFFFFF2DF, 0x000003DE, 0x000022C6, 0xFFFFF2DF, 0x000003DE },
+       { 0x0213F0FE993008C4, 0x00003036, 0xFFFFEB0D, 0x000004F9, 0x00001FE8, 0xFFFFF41A, 0x000003BC, 0x00001FE8, 0xFFFFF41A, 0x000003BC },
+       { 0x0213F0FE991A0904, 0x000030F8, 0xFFFFEA13, 0x00000524, 0x00001B6A, 0xFFFFF6C9, 0x0000034A, 0x00001B6A, 0xFFFFF6C9, 0x0000034A },
+       { 0x0213F0FE993010A4, 0x00002EE2, 0xFFFFEC0C, 0x000004CB, 0x00001A39, 0xFFFFF814, 0x0000030F, 0x00001A39, 0xFFFFF814, 0x0000030F },
+       { 0x0213F0FE991C3184, 0x00003457, 0xFFFFE924, 0x0000052A, 0x00001E9D, 0xFFFFF59C, 0x00000363, 0x00001E9D, 0xFFFFF59C, 0x00000363 },
+       { 0x0213F0FE99322844, 0x000030BF, 0xFFFFEB18, 0x000004ED, 0x00001D37, 0xFFFFF636, 0x0000035C, 0x00001D37, 0xFFFFF636, 0x0000035C },
+       { 0x0213F0FE992E4084, 0x000031AF, 0xFFFFEA75, 0x000004FE, 0x000019F2, 0xFFFFF87A, 0x000002F0, 0x000019F2, 0xFFFFF87A, 0x000002F0 },
+       { 0x0213F0FE99302884, 0x00003642, 0xFFFFE85B, 0x00000547, 0x00002975, 0xFFFFEE98, 0x0000048B, 0x00002975, 0xFFFFEE98, 0x0000048B },
+       { 0x0213F0FE992E2884, 0x00002E8B, 0xFFFFED1E, 0x0000048E, 0x000019C1, 0xFFFFF917, 0x000002D6, 0x000019C1, 0xFFFFF917, 0x000002D6 },
+       { 0x0213F0FE993241A4, 0x000033D9, 0xFFFFE8E1, 0x00000548, 0x0000224B, 0xFFFFF298, 0x000003F4, 0x0000224B, 0xFFFFF298, 0x000003F4 },
+       { 0x0213F0FE992E28C4, 0x000032BC, 0xFFFFEB0F, 0x000004D6, 0x00002488, 0xFFFFF240, 0x000003F2, 0x00002488, 0xFFFFF240, 0x000003F2 },
+       { 0x0213F0FE99304944, 0x000035FD, 0xFFFFE838, 0x00000553, 0x00002762, 0xFFFFEFBC, 0x00000460, 0x00002762, 0xFFFFEFBC, 0x00000460 },
+       { 0x0213F0FE992818A4, 0x0000268B, 0xFFFFF263, 0x000003D1, 0x00001914, 0xFFFFF977, 0x000002E8, 0x00001914, 0xFFFFF977, 0x000002E8 },
+       { 0x0213F0FE992C3184, 0x0000330B, 0xFFFFEA1E, 0x00000505, 0x000020B1, 0xFFFFF44D, 0x0000039E, 0x000020B1, 0xFFFFF44D, 0x0000039E },
+       { 0x0213F0FE99222084, 0x0000326E, 0xFFFFEA26, 0x00000508, 0x00001C17, 0xFFFFF722, 0x00000328, 0x00001C17, 0xFFFFF722, 0x00000328 },
+       { 0x0213F0FE992A31A4, 0x00002A3F, 0xFFFFEEE8, 0x0000046D, 0x00001B2B, 0xFFFFF737, 0x0000034D, 0x00001B2B, 0xFFFFF737, 0x0000034D },
+       { 0x0213F0FE992C4064, 0x00003732, 0xFFFFE765, 0x00000574, 0x00002A6D, 0xFFFFEDA8, 0x000004B7, 0x00002A6D, 0xFFFFEDA8, 0x000004B7 },
+       { 0x0213F0FE99300924, 0x000034D3, 0xFFFFE827, 0x00000569, 0x000027AA, 0xFFFFEEE7, 0x00000492, 0x000027AA, 0xFFFFEEE7, 0x00000492 },
+       { 0x0213F0FE992E40C4, 0x00003306, 0xFFFFEA39, 0x000004FC, 0x00001DCC, 0xFFFFF655, 0x00000344, 0x00001DCC, 0xFFFFF655, 0x00000344 },
+       { 0x0213F0FE99282044, 0x00002A48, 0xFFFFEFCA, 0x00000439, 0x00001DED, 0xFFFFF60D, 0x00000375, 0x00001DED, 0xFFFFF60D, 0x00000375 },
+       { 0x0213F0FE993038C4, 0x000033A3, 0xFFFFEA36, 0x000004F9, 0x0000247C, 0xFFFFF21F, 0x000003F4, 0x0000247C, 0xFFFFF21F, 0x000003F4 },
+       { 0x0213F0FE992C3164, 0x0000311B, 0xFFFFEB76, 0x000004D1, 0x00001EB1, 0xFFFFF5B6, 0x00000366, 0x00001EB1, 0xFFFFF5B6, 0x00000366 },
+       { 0x0213F0FE99324164, 0x00003307, 0xFFFFE97F, 0x0000052A, 0x00001E76, 0xFFFFF54D, 0x0000037C, 0x00001E76, 0xFFFFF54D, 0x0000037C },
+       { 0x0213F0FE991C2144, 0x0000344B, 0xFFFFE9C5, 0x00000509, 0x000020D6, 0xFFFFF486, 0x0000038F, 0x000020D6, 0xFFFFF486, 0x0000038F },
+       { 0x0213F0FE992C3144, 0x000034B9, 0xFFFFEA0B, 0x000004F7, 0x000027B3, 0xFFFFF057, 0x0000043A, 0x000027B3, 0xFFFFF057, 0x0000043A },
+       { 0x0213F0FE99301964, 0x00003360, 0xFFFFE984, 0x00000527, 0x00002238, 0xFFFFF2EE, 0x000003E0, 0x00002238, 0xFFFFF2EE, 0x000003E0 },
+       { 0x0213F0FE99302124, 0x0000315C, 0xFFFFEC05, 0x000004B1, 0x000023C8, 0xFFFFF2CC, 0x000003DE, 0x000023C8, 0xFFFFF2CC, 0x000003DE },
+       { 0x0213F0FE992C2864, 0x0000389B, 0xFFFFE6D5, 0x00000582, 0x00002C6C, 0xFFFFEC92, 0x000004DE, 0x00002C6C, 0xFFFFEC92, 0x000004DE },
+       { 0x0213F0FE992E1124, 0x00003058, 0xFFFFEB30, 0x000004E6, 0x000019B5, 0xFFFFF88B, 0x000002F1, 0x000019B5, 0xFFFFF88B, 0x000002F1 },
+       { 0x0213F0FE992E0904, 0x00002F69, 0xFFFFEB4A, 0x000004F1, 0x00001B82, 0xFFFFF6EC, 0x00000341, 0x00001B82, 0xFFFFF6EC, 0x00000341 },
+       { 0x0213F0FE991A18E4, 0x000031EB, 0xFFFFEA64, 0x00000508, 0x00002059, 0xFFFFF427, 0x000003B0, 0x00002059, 0xFFFFF427, 0x000003B0 },
+       { 0x0213F0FE99224124, 0x000033E2, 0xFFFFE94D, 0x0000052A, 0x000020BF, 0xFFFFF40B, 0x000003AB, 0x000020BF, 0xFFFFF40B, 0x000003AB },
+       { 0x0213F0FE99283184, 0x00002AF9, 0xFFFFEFE9, 0x00000427, 0x00001F72, 0xFFFFF57A, 0x00000383, 0x00001F72, 0xFFFFF57A, 0x00000383 },
+       { 0x0213F0FE992C2824, 0x00003282, 0xFFFFEA88, 0x000004FA, 0x00002561, 0xFFFFF126, 0x0000042B, 0x00002561, 0xFFFFF126, 0x0000042B },
+       { 0x0213F0FE993010E4, 0x0000308A, 0xFFFFEB5D, 0x000004E0, 0x00001E83, 0xFFFFF577, 0x00000378, 0x00001E83, 0xFFFFF577, 0x00000378 },
+       { 0x0213F0FE99324884, 0x0000336E, 0xFFFFE8C8, 0x00000553, 0x0000217C, 0xFFFFF2E1, 0x000003EB, 0x0000217C, 0xFFFFF2E1, 0x000003EB },
+       { 0x0213F0FE991A2164, 0x000034A9, 0xFFFFE838, 0x00000561, 0x000020CE, 0xFFFFF38A, 0x000003C7, 0x000020CE, 0xFFFFF38A, 0x000003C7 },
+       { 0x0213F0FE99222184, 0x00003152, 0xFFFFE9EB, 0x00000522, 0x00001755, 0xFFFFF9A9, 0x000002C6, 0x00001755, 0xFFFFF9A9, 0x000002C6 },
+       { 0x0213F0FE99281884, 0x0000286E, 0xFFFFF136, 0x000003FD, 0x00001BAB, 0xFFFFF7C3, 0x0000032C, 0x00001BAB, 0xFFFFF7C3, 0x0000032C },
+       { 0x0213F0FE99300944, 0x0000316B, 0xFFFFEA02, 0x00000528, 0x00002247, 0xFFFFF24E, 0x00000408, 0x00002247, 0xFFFFF24E, 0x00000408 },
+       { 0x0213F0FE992C08E4, 0x000034CF, 0xFFFFE83D, 0x00000562, 0x00002458, 0xFFFFF130, 0x00000430, 0x00002458, 0xFFFFF130, 0x00000430 },
+       { 0x0213F0FE992C2984, 0x00003352, 0xFFFFE9D1, 0x00000515, 0x0000212A, 0xFFFFF3DC, 0x000003B4, 0x0000212A, 0xFFFFF3DC, 0x000003B4 },
+       { 0x0213F0FE992840A4, 0x00002946, 0xFFFFF09B, 0x00000415, 0x00001DC9, 0xFFFFF650, 0x00000366, 0x00001DC9, 0xFFFFF650, 0x00000366 },
+       { 0x0213F0FE99301124, 0x00003080, 0xFFFFEB47, 0x000004E1, 0x00001BD5, 0xFFFFF73B, 0x00000329, 0x00001BD5, 0xFFFFF73B, 0x00000329 },
+       { 0x0213F0FE991A1884, 0x00002FBD, 0xFFFFEB7B, 0x000004DD, 0x000017FC, 0xFFFFF99E, 0x000002C7, 0x000017FC, 0xFFFFF99E, 0x000002C7 },
+       { 0x0213F0FE99281124, 0x00002A28, 0xFFFFF032, 0x0000041F, 0x00001B19, 0xFFFFF83A, 0x00000312, 0x00001B19, 0xFFFFF83A, 0x00000312 },
+       { 0x0213F0FE992240C4, 0x00003420, 0xFFFFE936, 0x00000530, 0x000023C2, 0xFFFFF203, 0x00000406, 0x000023C2, 0xFFFFF203, 0x00000406 },
+       { 0x0213F0FE99301144, 0x00002F7C, 0xFFFFEBBA, 0x000004D1, 0x0000185D, 0xFFFFF975, 0x000002CA, 0x0000185D, 0xFFFFF975, 0x000002CA },
+       { 0x0213F0FE992E2044, 0x00002C51, 0xFFFFEE3B, 0x0000046F, 0x000019AA, 0xFFFFF8DD, 0x000002ED, 0x000019AA, 0xFFFFF8DD, 0x000002ED },
+       { 0x0213F0FE991A4144, 0x000033D6, 0xFFFFE8F2, 0x0000053D, 0x00001D73, 0xFFFFF5FB, 0x0000035B, 0x00001D73, 0xFFFFF5FB, 0x0000035B },
+       { 0x0213F0FE99323084, 0x000031D9, 0xFFFFEAF7, 0x000004E4, 0x00001EBD, 0xFFFFF5A6, 0x00000368, 0x00001EBD, 0xFFFFF5A6, 0x00000368 },
+       { 0x0213F0FE991A20A4, 0x00003386, 0xFFFFE9CE, 0x00000515, 0x00002422, 0xFFFFF1F3, 0x00000405, 0x00002422, 0xFFFFF1F3, 0x00000405 },
+       { 0x0213F0FE992C50E4, 0x000032FB, 0xFFFFE9BC, 0x00000520, 0x00002301, 0xFFFFF267, 0x000003F7, 0x00002301, 0xFFFFF267, 0x000003F7 },
+       { 0x0213F0FE99322924, 0x000032C2, 0xFFFFEAC0, 0x000004EA, 0x0000250F, 0xFFFFF1A2, 0x00000413, 0x0000250F, 0xFFFFF1A2, 0x00000413 },
+       { 0x0213F0FE991C2944, 0x00003722, 0xFFFFE8A6, 0x00000527, 0x000026E4, 0xFFFFF0F5, 0x0000041C, 0x000026E4, 0xFFFFF0F5, 0x0000041C },
+       { 0x0213F0FE992C48C4, 0x000035A4, 0xFFFFE822, 0x00000558, 0x000022F2, 0xFFFFF288, 0x000003E8, 0x000022F2, 0xFFFFF288, 0x000003E8 },
+       { 0x0213F0FE99280924, 0x00002CD1, 0xFFFFEDC6, 0x0000048C, 0x00001EAF, 0xFFFFF53D, 0x00000396, 0x00001EAF, 0xFFFFF53D, 0x00000396 },
+       { 0x0213F0FE99301164, 0x00003156, 0xFFFFEA60, 0x0000050B, 0x00001BBC, 0xFFFFF704, 0x00000335, 0x00001BBC, 0xFFFFF704, 0x00000335 },
+       { 0x0213F0FE992C5104, 0x000034A1, 0xFFFFE8C0, 0x00000544, 0x00002528, 0xFFFFF105, 0x0000042C, 0x00002528, 0xFFFFF105, 0x0000042C },
+       { 0x0213F0FE99323064, 0x000032CE, 0xFFFFE9D3, 0x00000520, 0x000021FF, 0xFFFFF2FD, 0x000003E4, 0x000021FF, 0xFFFFF2FD, 0x000003E4 },
+       { 0x0213F0FE991A50A4, 0x000034A0, 0xFFFFE823, 0x0000056D, 0x0000256F, 0xFFFFF047, 0x0000045A, 0x0000256F, 0xFFFFF047, 0x0000045A },
+       { 0x0213F0FE99303944, 0x00003109, 0xFFFFEBD6, 0x000004BF, 0x000022D4, 0xFFFFF32D, 0x000003D0, 0x000022D4, 0xFFFFF32D, 0x000003D0 },
+       { 0x0213F0FE992C1164, 0x000030B7, 0xFFFFEAF0, 0x000004F3, 0x00001AEC, 0xFFFFF7A9, 0x0000031B, 0x00001AEC, 0xFFFFF7A9, 0x0000031B },
+       { 0x0213F0FE992C39A4, 0x00003078, 0xFFFFEBA4, 0x000004CF, 0x00001E7A, 0xFFFFF5AF, 0x0000036B, 0x00001E7A, 0xFFFFF5AF, 0x0000036B },
+       { 0x0213F0FE99304124, 0x00003442, 0xFFFFE998, 0x00000518, 0x000025EA, 0xFFFFF0F3, 0x0000042B, 0x000025EA, 0xFFFFF0F3, 0x0000042B },
+       { 0x0213F0FE993021A4, 0x000031CB, 0xFFFFEA80, 0x00000501, 0x000020A3, 0xFFFFF403, 0x000003B2, 0x000020A3, 0xFFFFF403, 0x000003B2 },
+       { 0x0213F0FE992A2984, 0x00002947, 0xFFFFF018, 0x00000433, 0x00001BA5, 0xFFFFF75C, 0x00000340, 0x00001BA5, 0xFFFFF75C, 0x00000340 },
+       { 0x0213F0FE992C3984, 0x000033F9, 0xFFFFE99D, 0x00000518, 0x00002231, 0xFFFFF358, 0x000003C5, 0x00002231, 0xFFFFF358, 0x000003C5 },
+       { 0x0213F0FE99321124, 0x00003131, 0xFFFFEA45, 0x00000513, 0x00001973, 0xFFFFF85E, 0x00000301, 0x00001973, 0xFFFFF85E, 0x00000301 },
+       { 0x0213F0FE991C29A4, 0x00003571, 0xFFFFE8AC, 0x00000539, 0x00002049, 0xFFFFF49C, 0x0000038D, 0x00002049, 0xFFFFF49C, 0x0000038D },
+       { 0x0213F0FE992E3864, 0x0000309E, 0xFFFFEB1D, 0x000004E8, 0x000019ED, 0xFFFFF86E, 0x000002F8, 0x000019ED, 0xFFFFF86E, 0x000002F8 },
+       { 0x0213F0FE99302984, 0x00003091, 0xFFFFEB9B, 0x000004CC, 0x00001D2C, 0xFFFFF6A2, 0x0000033D, 0x00001D2C, 0xFFFFF6A2, 0x0000033D },
+       { 0x0213F0FE993008E4, 0x00003069, 0xFFFFEAFD, 0x000004F8, 0x00001E82, 0xFFFFF51C, 0x0000038D, 0x00001E82, 0xFFFFF51C, 0x0000038D },
+       { 0x0213F0FE992210A4, 0x00003459, 0xFFFFE7F2, 0x00000572, 0x00001DA7, 0xFFFFF552, 0x0000037F, 0x00001DA7, 0xFFFFF552, 0x0000037F },
+       { 0x0213F0FE99321104, 0x0000304B, 0xFFFFEAFB, 0x000004F4, 0x0000191E, 0xFFFFF8BD, 0x000002EE, 0x0000191E, 0xFFFFF8BD, 0x000002EE },
+       { 0x0213F0FE993020C4, 0x0000346E, 0xFFFFEA07, 0x000004FD, 0x00002767, 0xFFFFF058, 0x00000440, 0x00002767, 0xFFFFF058, 0x00000440 },
+       { 0x0213F0FE992E3084, 0x000030B5, 0xFFFFEBC1, 0x000004C1, 0x00001B3C, 0xFFFFF818, 0x000002FD, 0x00001B3C, 0xFFFFF818, 0x000002FD },
+       { 0x0213F0FE99300904, 0x0000321F, 0xFFFFE9EA, 0x00000524, 0x00002380, 0xFFFFF1C2, 0x0000041A, 0x00002380, 0xFFFFF1C2, 0x0000041A },
+       { 0x0213F0FE992E3044, 0x000030DF, 0xFFFFEB37, 0x000004E2, 0x00001E3C, 0xFFFFF5BB, 0x00000369, 0x00001E3C, 0xFFFFF5BB, 0x00000369 },
+       { 0x0213F0FE992848A4, 0x000027E0, 0xFFFFF0E2, 0x00000416, 0x00001A6A, 0xFFFFF820, 0x00000321, 0x00001A6A, 0xFFFFF820, 0x00000321 },
+       { 0x0213F0FE991A1084, 0x00002FA1, 0xFFFFEB63, 0x000004E7, 0x0000196B, 0xFFFFF880, 0x000002FB, 0x0000196B, 0xFFFFF880, 0x000002FB },
+       { 0x0213F0FE991C1084, 0x0000310C, 0xFFFFEAAF, 0x000004FC, 0x000019EF, 0xFFFFF850, 0x000002FD, 0x000019EF, 0xFFFFF850, 0x000002FD },
+       { 0x0213F0FE99323904, 0x0000334A, 0xFFFFEA07, 0x0000050B, 0x00002380, 0xFFFFF26F, 0x000003F0, 0x00002380, 0xFFFFF26F, 0x000003F0 },
+       { 0x0213F0FE99302944, 0x00002FF9, 0xFFFFECDC, 0x00000492, 0x00002297, 0xFFFFF394, 0x000003BF, 0x00002297, 0xFFFFF394, 0x000003BF },
+       { 0x0213F0FE992C2164, 0x0000354B, 0xFFFFE894, 0x00000546, 0x000024C4, 0xFFFFF16C, 0x0000041B, 0x000024C4, 0xFFFFF16C, 0x0000041B },
+       { 0x0213F0FE99220924, 0x00003245, 0xFFFFE92F, 0x00000544, 0x00001829, 0xFFFFF8F1, 0x000002EA, 0x00001829, 0xFFFFF8F1, 0x000002EA },
+       { 0x0213F0FE992E4884, 0x0000302F, 0xFFFFEB51, 0x000004E3, 0x0000199F, 0xFFFFF894, 0x000002F4, 0x0000199F, 0xFFFFF894, 0x000002F4 },
+       { 0x0213F0FE992E18C4, 0x00002F54, 0xFFFFEC86, 0x000004A6, 0x00001A6F, 0xFFFFF891, 0x000002EC, 0x00001A6F, 0xFFFFF891, 0x000002EC },
+       { 0x0213F0FE99284164, 0x00002908, 0xFFFFF0D8, 0x0000040A, 0x00001C9B, 0xFFFFF729, 0x00000342, 0x00001C9B, 0xFFFFF729, 0x00000342 },
+       { 0x0213F0FE99302964, 0x000031D9, 0xFFFFEB40, 0x000004D7, 0x000023F5, 0xFFFFF259, 0x000003F4, 0x000023F5, 0xFFFFF259, 0x000003F4 },
+       { 0x0213F0FE993048E4, 0x000034C8, 0xFFFFE8C6, 0x0000053F, 0x00002313, 0xFFFFF280, 0x000003EC, 0x00002313, 0xFFFFF280, 0x000003EC },
+       { 0x0213F0FE993050C4, 0x000037D1, 0xFFFFE6A1, 0x0000059C, 0x00002C6A, 0xFFFFEBFF, 0x00000504, 0x00002C6A, 0xFFFFEBFF, 0x00000504 },
+       { 0x0213F0FE99321964, 0x000030E9, 0xFFFFEA6B, 0x0000050F, 0x00001A2D, 0xFFFFF7DF, 0x00000316, 0x00001A2D, 0xFFFFF7DF, 0x00000316 },
+       { 0x0213F0FE99302084, 0x0000323D, 0xFFFFEA95, 0x000004F4, 0x00001ED2, 0xFFFFF584, 0x0000036C, 0x00001ED2, 0xFFFFF584, 0x0000036C },
+       { 0x0213F0FE992C3024, 0x000033D6, 0xFFFFE9DB, 0x00000510, 0x000027A7, 0xFFFFEFC7, 0x0000045E, 0x000027A7, 0xFFFFEFC7, 0x0000045E },
+       { 0x0213F0FE991C3164, 0x00003444, 0xFFFFE98A, 0x00000517, 0x000020FD, 0xFFFFF43F, 0x0000039D, 0x000020FD, 0xFFFFF43F, 0x0000039D },
+       { 0x0213F0FE992808E4, 0x00002987, 0xFFFFEFA1, 0x0000044B, 0x00001B06, 0xFFFFF788, 0x0000033C, 0x00001B06, 0xFFFFF788, 0x0000033C },
+       { 0x0213F0FE992C28E4, 0x0000311D, 0xFFFFED20, 0x00000474, 0x000025DA, 0xFFFFF223, 0x000003F0, 0x000025DA, 0xFFFFF223, 0x000003F0 },
+       { 0x0213F0FE992C1124, 0x000032A2, 0xFFFFEA0A, 0x0000050D, 0x00001D48, 0xFFFFF659, 0x0000034A, 0x00001D48, 0xFFFFF659, 0x0000034A },
+       { 0x0213F0FE992208E4, 0x00003110, 0xFFFFE9EA, 0x00000529, 0x00001786, 0xFFFFF958, 0x000002DB, 0x00001786, 0xFFFFF958, 0x000002DB },
+       { 0x0213F0FE992821A4, 0x000027F2, 0xFFFFF174, 0x000003F7, 0x00001C7A, 0xFFFFF72A, 0x00000348, 0x00001C7A, 0xFFFFF72A, 0x00000348 },
+       { 0x0213F0FE991C10E4, 0x000031DB, 0xFFFFEA7D, 0x000004FB, 0x000019C4, 0xFFFFF8B1, 0x000002E6, 0x000019C4, 0xFFFFF8B1, 0x000002E6 },
+       { 0x0213F0FE992C1104, 0x00003158, 0xFFFFEAAC, 0x000004FA, 0x00001BC1, 0xFFFFF737, 0x0000032B, 0x00001BC1, 0xFFFFF737, 0x0000032B },
+       { 0x0213F0FE993010C4, 0x00002F36, 0xFFFFEBF9, 0x000004CA, 0x00001A2A, 0xFFFFF83F, 0x00000303, 0x00001A2A, 0xFFFFF83F, 0x00000303 },
+       { 0x0213F0FE993238A4, 0x000032B4, 0xFFFFEA72, 0x000004FA, 0x000021FF, 0xFFFFF378, 0x000003C5, 0x000021FF, 0xFFFFF378, 0x000003C5 },
+       { 0x0213F0FE99303164, 0x00003262, 0xFFFFEAFA, 0x000004DF, 0x00002441, 0xFFFFF237, 0x000003F6, 0x00002441, 0xFFFFF237, 0x000003F6 },
+       { 0x0213F0FE99303924, 0x0000336A, 0xFFFFEAFB, 0x000004D1, 0x00002746, 0xFFFFF0B8, 0x0000042B, 0x00002746, 0xFFFFF0B8, 0x0000042B },
+       { 0x0213F0FE991A4084, 0x000032E5, 0xFFFFE923, 0x00000541, 0x00001DF0, 0xFFFFF552, 0x00000380, 0x00001DF0, 0xFFFFF552, 0x00000380 },
+       { 0x0213F0FE99304064, 0x000035D1, 0xFFFFE80B, 0x0000055F, 0x00002780, 0xFFFFEF74, 0x0000046F, 0x00002780, 0xFFFFEF74, 0x0000046F },
+       { 0x0213F0FE993028A4, 0x000033EC, 0xFFFFEA48, 0x000004F4, 0x0000269F, 0xFFFFF0D8, 0x0000042A, 0x0000269F, 0xFFFFF0D8, 0x0000042A },
+       { 0x0213F0FE99323884, 0x000030C4, 0xFFFFEB39, 0x000004E2, 0x00001B44, 0xFFFFF7AA, 0x00000318, 0x00001B44, 0xFFFFF7AA, 0x00000318 },
+       { 0x0213F0FE99281144, 0x00002926, 0xFFFFF0AF, 0x0000040E, 0x0000194E, 0xFFFFF959, 0x000002E2, 0x0000194E, 0xFFFFF959, 0x000002E2 },
+       { 0x0213F0FE992C10C4, 0x00003141, 0xFFFFEAAF, 0x000004F6, 0x00001864, 0xFFFFF97C, 0x000002C6, 0x00001864, 0xFFFFF97C, 0x000002C6 },
+       { 0x0213F0FE99301064, 0x000030B2, 0xFFFFEB7C, 0x000004DB, 0x000022CE, 0xFFFFF2B5, 0x000003F0, 0x000022CE, 0xFFFFF2B5, 0x000003F0 },
+       { 0x0213F0FE99301944, 0x0000318C, 0xFFFFEAC7, 0x000004F6, 0x00002113, 0xFFFFF3CA, 0x000003BD, 0x00002113, 0xFFFFF3CA, 0x000003BD },
+       { 0x0213F0FE992E1104, 0x00002FD2, 0xFFFFEB8F, 0x000004D9, 0x00001996, 0xFFFFF89F, 0x000002F1, 0x00001996, 0xFFFFF89F, 0x000002F1 },
+       { 0x0213F0FE991A28A4, 0x0000310D, 0xFFFFEB25, 0x000004E7, 0x00001F67, 0xFFFFF4EF, 0x0000038E, 0x00001F67, 0xFFFFF4EF, 0x0000038E },
+       { 0x0213F0FE992A4964, 0x00002BBC, 0xFFFFEE68, 0x00000477, 0x00002050, 0xFFFFF41D, 0x000003C8, 0x00002050, 0xFFFFF41D, 0x000003C8 },
+       { 0x0213F0FE99302104, 0x00003096, 0xFFFFECED, 0x00000486, 0x000024C9, 0xFFFFF278, 0x000003E7, 0x000024C9, 0xFFFFF278, 0x000003E7 },
+       { 0x0213F0FE992C10A4, 0x00003401, 0xFFFFE8F1, 0x0000053C, 0x00001E75, 0xFFFFF55C, 0x00000376, 0x00001E75, 0xFFFFF55C, 0x00000376 },
+       { 0x0213F0FE99302844, 0x0000319E, 0xFFFFEAB1, 0x000004F8, 0x00001EA3, 0xFFFFF567, 0x00000378, 0x00001EA3, 0xFFFFF567, 0x00000378 },
+       { 0x0213F0FE99322964, 0x000030FD, 0xFFFFEB4C, 0x000004DB, 0x00001CA6, 0xFFFFF6E8, 0x00000335, 0x00001CA6, 0xFFFFF6E8, 0x00000335 },
+       { 0x0213F0FE992E40A4, 0x000030D6, 0xFFFFEB1A, 0x000004E4, 0x00001A0D, 0xFFFFF87D, 0x000002EF, 0x00001A0D, 0xFFFFF87D, 0x000002EF },
+       { 0x0213F0FE992C2124, 0x0000324B, 0xFFFFEB17, 0x000004D9, 0x00002225, 0xFFFFF3A8, 0x000003BA, 0x00002225, 0xFFFFF3A8, 0x000003BA },
+       { 0x0213F0FE99284084, 0x00002A00, 0xFFFFF02E, 0x00000424, 0x00001E21, 0xFFFFF61D, 0x0000036C, 0x00001E21, 0xFFFFF61D, 0x0000036C },
+       { 0x0213F0FE992A48A4, 0x000029CF, 0xFFFFEF53, 0x00000457, 0x00001B11, 0xFFFFF772, 0x0000033D, 0x00001B11, 0xFFFFF772, 0x0000033D },
+       { 0x0213F0FE991A30A4, 0x000032A1, 0xFFFFEA63, 0x000004FB, 0x00001F83, 0xFFFFF516, 0x0000037E, 0x00001F83, 0xFFFFF516, 0x0000037E },
+       { 0x0213F0FE992E20C4, 0x0000305C, 0xFFFFEC14, 0x000004B5, 0x00001D0B, 0xFFFFF6ED, 0x00000332, 0x00001D0B, 0xFFFFF6ED, 0x00000332 },
+       { 0x0213F0FE992C1064, 0x00003467, 0xFFFFE8D5, 0x00000543, 0x0000243F, 0xFFFFF190, 0x00000418, 0x0000243F, 0xFFFFF190, 0x00000418 },
+       { 0x0213F0FE992A2064, 0x00002796, 0xFFFFF133, 0x00000409, 0x00001903, 0xFFFFF91C, 0x000002FC, 0x00001903, 0xFFFFF91C, 0x000002FC },
+       { 0x0213F0FE99302164, 0x000031F6, 0xFFFFEAB7, 0x000004F5, 0x000022B9, 0xFFFFF2D0, 0x000003E6, 0x000022B9, 0xFFFFF2D0, 0x000003E6 },
+       { 0x0213F0FE992E5104, 0x00003196, 0xFFFFEA76, 0x00000503, 0x00001CC5, 0xFFFFF67D, 0x0000034A, 0x00001CC5, 0xFFFFF67D, 0x0000034A },
+       { 0x0213F0FE99321144, 0x00002F9E, 0xFFFFEAD9, 0x00000505, 0x000017C1, 0xFFFFF93D, 0x000002DF, 0x000017C1, 0xFFFFF93D, 0x000002DF },
+       { 0x0213F0FE992E2124, 0x00002FBC, 0xFFFFEC75, 0x000004A8, 0x00001D6D, 0xFFFFF6AC, 0x0000033D, 0x00001D6D, 0xFFFFF6AC, 0x0000033D },
+       { 0x0213F0FE992C38A4, 0x00003541, 0xFFFFE921, 0x00000524, 0x00002662, 0xFFFFF0CB, 0x0000042B, 0x00002662, 0xFFFFF0CB, 0x0000042B },
+       { 0x0213F0FE992A21A4, 0x00002953, 0xFFFFEF76, 0x00000459, 0x00001C05, 0xFFFFF6A0, 0x00000368, 0x00001C05, 0xFFFFF6A0, 0x00000368 },
+       { 0x0213F0FE992C4924, 0x000034BC, 0xFFFFE8DD, 0x00000536, 0x0000210E, 0xFFFFF3F4, 0x000003A8, 0x0000210E, 0xFFFFF3F4, 0x000003A8 },
+       { 0x0213F0FE992C29A4, 0x000034BE, 0xFFFFE916, 0x0000052F, 0x000024A1, 0xFFFFF1A6, 0x00000410, 0x000024A1, 0xFFFFF1A6, 0x00000410 },
+       { 0x0213F0FE99304964, 0x000037B5, 0xFFFFE7A9, 0x0000055B, 0x000028A1, 0xFFFFEF51, 0x00000467, 0x000028A1, 0xFFFFEF51, 0x00000467 },
+       { 0x0213F0FE99301104, 0x00002FC5, 0xFFFFEBBE, 0x000004D1, 0x00001BA5, 0xFFFFF757, 0x00000328, 0x00001BA5, 0xFFFFF757, 0x00000328 },
+       { 0x0213F0FE993040A4, 0x000033CB, 0xFFFFE944, 0x0000052B, 0x00001FBE, 0xFFFFF4B1, 0x0000038C, 0x00001FBE, 0xFFFFF4B1, 0x0000038C },
+       { 0x0213F0FE99301844, 0x000030AE, 0xFFFFEBA0, 0x000004D3, 0x00002268, 0xFFFFF316, 0x000003DD, 0x00002268, 0xFFFFF316, 0x000003DD },
+       { 0x0213F0FE992C20A4, 0x00002F90, 0xFFFFEC5A, 0x000004B0, 0x00001C3A, 0xFFFFF752, 0x00000323, 0x00001C3A, 0xFFFFF752, 0x00000323 },
+       { 0x0213F0FE992E38E4, 0x00003113, 0xFFFFEB91, 0x000004C8, 0x00001E3C, 0xFFFFF623, 0x0000034E, 0x00001E3C, 0xFFFFF623, 0x0000034E },
+       { 0x0213F0FE99323984, 0x0000330B, 0xFFFFE94B, 0x00000539, 0x000020E7, 0xFFFFF37E, 0x000003CD, 0x000020E7, 0xFFFFF37E, 0x000003CD },
+       { 0x0213F0FE992E2864, 0x000031D1, 0xFFFFEACB, 0x000004ED, 0x00001E82, 0xFFFFF5B2, 0x00000365, 0x00001E82, 0xFFFFF5B2, 0x00000365 },
+       { 0x0213F0FE992A3984, 0x00002CD5, 0xFFFFEDC1, 0x0000048D, 0x000020F8, 0xFFFFF3C1, 0x000003D1, 0x000020F8, 0xFFFFF3C1, 0x000003D1 },
+       { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
   };
   
   int pp_override_get_default_fuse_value(uint64_t key,
-                       struct phm_fuses_default list[],
                         struct phm_fuses_default *result)
   {
+       const struct phm_fuses_default *list = vega10_fuses_default;
         uint32_t i;
-       uint64_t temp_serial_numer;
-       uint32_t bit;
-       const char *temp;
   
-       for (i = 0; list[i].key != NULL; i++) {
-               temp = list[i].key;
-               temp_serial_numer = 0;
-               do {
-                       bit = *temp=='1'? 1 : 0;
-                       temp_serial_numer = (temp_serial_numer <<1 ) | bit;
-                       temp++;
-               } while (*temp);
- 
-               if (key == temp_serial_numer) {
+       for (i = 0; list[i].key != 0; i++) {
+               if (key == list[i].key) {
                         result->key =  list[i].key;
                         result->VFT2_m1 = list[i].VFT2_m1;
                         result->VFT2_m2 = list[i].VFT2_m2;
diff --combined drivers/gpu/drm/amd/powerplay/smumgr/Makefile

index e7ad45297b1d489d444b5b845e2aa0c3e02858a8,b24b0f203a51575667fc55486f111caf7e9eb634..30d3089d7dbafdc45ce9b666edb4a65916ab029d
--- 1/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
--- 2/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
@@@ -1,11 -1,10 +1,11 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   #
   # Makefile for the 'smu manager' sub-component of powerplay.
   # It provides the smu management services for the driver.
   
- SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
-         polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
-         smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
+ SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o \
+         polaris10_smumgr.o iceland_smumgr.o \
+         smu7_smumgr.o vega10_smumgr.o rv_smumgr.o ci_smumgr.o
   
   AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
   
diff --combined drivers/gpu/drm/amd/scheduler/gpu_scheduler.c

index a25f6c72f219358c9b436a714cf9ec658b8bcaf9,e4d3b4ec4e92c23891e728fb6cbd3ea9ec7639f2..92ec663fdada40de6d5cdea15b95504427ea6300
--- 1/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
--- 2/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@@ -133,6 -133,7 +133,7 @@@ int amd_sched_entity_init(struct amd_gp
         entity->rq = rq;
         entity->sched = sched;
   
+       spin_lock_init(&entity->rq_lock);
         spin_lock_init(&entity->queue_lock);
         r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL);
         if (r)
@@@ -187,7 -188,7 +188,7 @@@ static bool amd_sched_entity_is_ready(s
         if (kfifo_is_empty(&entity->job_queue))
                 return false;
   
- -      if (ACCESS_ONCE(entity->dependency))
+ +      if (READ_ONCE(entity->dependency))
                 return false;
   
         return true;
@@@ -204,18 -205,38 +205,38 @@@
   void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
                            struct amd_sched_entity *entity)
   {
-       struct amd_sched_rq *rq = entity->rq;
+       int r;
   
         if (!amd_sched_entity_is_initialized(sched, entity))
                 return;
- 
         /**
          * The client will not queue more IBs during this fini, consume existing
-        * queued IBs
+        * queued IBs or discard them on SIGKILL
         */
-       wait_event(sched->job_scheduled, amd_sched_entity_is_idle(entity));
+       if ((current->flags & PF_SIGNALED) && current->exit_code == SIGKILL)
+               r = -ERESTARTSYS;
+       else
+               r = wait_event_killable(sched->job_scheduled,
+                                       amd_sched_entity_is_idle(entity));
+       amd_sched_entity_set_rq(entity, NULL);
+       if (r) {
+               struct amd_sched_job *job;
+ 
+               /* Park the kernel for a moment to make sure it isn't processing
+                * our enity.
+                */
+               kthread_park(sched->thread);
+               kthread_unpark(sched->thread);
+               while (kfifo_out(&entity->job_queue, &job, sizeof(job))) {
+                       struct amd_sched_fence *s_fence = job->s_fence;
+                       amd_sched_fence_scheduled(s_fence);
+                       dma_fence_set_error(&s_fence->finished, -ESRCH);
+                       amd_sched_fence_finished(s_fence);
+                       dma_fence_put(&s_fence->finished);
+                       sched->ops->free_job(job);
+               }
   
-       amd_sched_rq_remove_entity(rq, entity);
+       }
         kfifo_free(&entity->job_queue);
   }
   
@@@ -236,6 -257,24 +257,24 @@@ static void amd_sched_entity_clear_dep(
         dma_fence_put(f);
   }
   
+ void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
+                            struct amd_sched_rq *rq)
+ {
+       if (entity->rq == rq)
+               return;
+ 
+       spin_lock(&entity->rq_lock);
+ 
+       if (entity->rq)
+               amd_sched_rq_remove_entity(entity->rq, entity);
+ 
+       entity->rq = rq;
+       if (rq)
+               amd_sched_rq_add_entity(rq, entity);
+ 
+       spin_unlock(&entity->rq_lock);
+ }
+ 
   bool amd_sched_dependency_optimized(struct dma_fence* fence,
                                     struct amd_sched_entity *entity)
   {
@@@ -293,7 -332,7 +332,7 @@@ static bool amd_sched_entity_add_depend
   }
   
   static struct amd_sched_job *
- amd_sched_entity_pop_job(struct amd_sched_entity *entity)
+ amd_sched_entity_peek_job(struct amd_sched_entity *entity)
   {
         struct amd_gpu_scheduler *sched = entity->sched;
         struct amd_sched_job *sched_job;
@@@ -333,14 -372,15 +372,15 @@@ static bool amd_sched_entity_in(struct 
         /* first job wakes up scheduler */
         if (first) {
                 /* Add the entity to the run queue */
+               spin_lock(&entity->rq_lock);
                 amd_sched_rq_add_entity(entity->rq, entity);
+               spin_unlock(&entity->rq_lock);
                 amd_sched_wakeup(sched);
         }
         return added;
   }
   
- /* job_finish is called after hw fence signaled, and
-  * the job had already been deleted from ring_mirror_list
+ /* job_finish is called after hw fence signaled
    */
   static void amd_sched_job_finish(struct work_struct *work)
   {
@@@ -366,6 -406,7 +406,7 @@@
                         schedule_delayed_work(&next->work_tdr, sched->timeout);
         }
         spin_unlock(&sched->job_list_lock);
+       dma_fence_put(&s_job->s_fence->finished);
         sched->ops->free_job(s_job);
   }
   
@@@ -381,6 -422,9 +422,9 @@@ static void amd_sched_job_begin(struct 
   {
         struct amd_gpu_scheduler *sched = s_job->sched;
   
+       dma_fence_add_callback(&s_job->s_fence->finished, &s_job->finish_cb,
+                              amd_sched_job_finish_cb);
+ 
         spin_lock(&sched->job_list_lock);
         list_add_tail(&s_job->node, &sched->ring_mirror_list);
         if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
@@@ -473,8 -517,6 +517,6 @@@ void amd_sched_entity_push_job(struct a
         struct amd_sched_entity *entity = sched_job->s_entity;
   
         trace_amd_sched_job(sched_job);
-       dma_fence_add_callback(&sched_job->s_fence->finished, &sched_job->finish_cb,
-                              amd_sched_job_finish_cb);
         wait_event(entity->sched->job_scheduled,
                    amd_sched_entity_in(sched_job));
   }
@@@ -545,6 -587,7 +587,7 @@@ static void amd_sched_process_job(struc
                 container_of(cb, struct amd_sched_fence, cb);
         struct amd_gpu_scheduler *sched = s_fence->sched;
   
+       dma_fence_get(&s_fence->finished);
         atomic_dec(&sched->hw_rq_count);
         amd_sched_fence_finished(s_fence);
   
@@@ -585,7 -628,7 +628,7 @@@ static int amd_sched_main(void *param
                 if (!entity)
                         continue;
   
-               sched_job = amd_sched_entity_pop_job(entity);
+               sched_job = amd_sched_entity_peek_job(entity);
                 if (!sched_job)
                         continue;
   
@@@ -596,6 -639,7 +639,7 @@@
   
                 fence = sched->ops->run_job(sched_job);
                 amd_sched_fence_scheduled(s_fence);
+ 
                 if (fence) {
                         s_fence->parent = dma_fence_get(fence);
                         r = dma_fence_add_callback(fence, &s_fence->cb,
diff --combined drivers/gpu/drm/armada/Makefile

index 1ab4cf863bf7731853e0aad0fafbc22fa14b9e6d,a18f156c8b663627ee250a2f9e2867688bafb163..ecf25cf9f9f59a222700ab9cd72ca2776cc66bed
--- 1/drivers/gpu/drm/armada/Makefile
--- 2/drivers/gpu/drm/armada/Makefile
+++ b/drivers/gpu/drm/armada/Makefile
@@@ -1,9 -1,6 +1,7 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   armada-y      := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \
                    armada_gem.o armada_overlay.o armada_trace.o
   armada-y      += armada_510.o
   armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o
   
   obj-$(CONFIG_DRM_ARMADA) := armada.o
- 
- CFLAGS_armada_trace.o := -I$(src)
diff --combined drivers/gpu/drm/armada/armada_trace.h

index 1e9f55fc8735dcd67c8c5c39f5590d45c54124b0,be245a24610f06d6a71d878695b7209c4cf3ef2c..8dbfea7a00fe328fe953dae40720e5be97c935c7
--- 1/drivers/gpu/drm/armada/armada_trace.h
--- 2/drivers/gpu/drm/armada/armada_trace.h
+++ b/drivers/gpu/drm/armada/armada_trace.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #if !defined(ARMADA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
   #define ARMADA_TRACE_H
   
@@@ -63,5 -62,5 +63,5 @@@ TRACE_EVENT(armada_ovl_plane_work
   
   /* This part must be outside protection */
   #undef TRACE_INCLUDE_PATH
- #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/armada
   #include <trace/define_trace.h>
diff --combined drivers/gpu/drm/bridge/Makefile

index 60dab87e4783cf35f38bcccbe5152fefbe56d5df,e3d5eb031f18f4221244ce9db17fd92c8b51087d..373eb28f31edbc4f262d3f3dd163a7e9643928fe
--- 1/drivers/gpu/drm/bridge/Makefile
--- 2/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
   obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
   obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
@@@ -7,6 -6,7 +7,7 @@@ obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-pt
   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
   obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
   obj-$(CONFIG_DRM_SII902X) += sii902x.o
+ obj-$(CONFIG_DRM_SII9234) += sii9234.o
   obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
   obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
   obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
diff --combined drivers/gpu/drm/drm_trace.h

index a8370775ed50680951e0ff8b2376f41cdd51b032,16c64d067e675ac510eafceb61ee0c264702325c..baccc63db106b7e1a59175df4befa8cde36aaaca
--- 1/drivers/gpu/drm/drm_trace.h
--- 2/drivers/gpu/drm/drm_trace.h
+++ b/drivers/gpu/drm/drm_trace.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #if !defined(_DRM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
   #define _DRM_TRACE_H_
   
@@@ -62,5 -61,5 +62,5 @@@ TRACE_EVENT(drm_vblank_event_delivered
   
   /* This part must be outside protection */
   #undef TRACE_INCLUDE_PATH
- #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm
   #include <trace/define_trace.h>
diff --combined drivers/gpu/drm/etnaviv/Makefile

index ab3f551831d7cb30d115babc8e96db02f3237685,15c3bfa89a79c3b93db7969a4d17fc94018d4851..1281c8d4fae52e3d17de6f2b536f1af67e2acd2c
--- 1/drivers/gpu/drm/etnaviv/Makefile
--- 2/drivers/gpu/drm/etnaviv/Makefile
+++ b/drivers/gpu/drm/etnaviv/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   etnaviv-y := \
         etnaviv_buffer.o \
         etnaviv_cmd_parser.o \
@@@ -11,6 -10,7 +11,7 @@@
         etnaviv_gpu.o \
         etnaviv_iommu_v2.o \
         etnaviv_iommu.o \
-       etnaviv_mmu.o
+       etnaviv_mmu.o \
+       etnaviv_perfmon.o
   
   obj-$(CONFIG_DRM_ETNAVIV)     += etnaviv.o
diff --combined drivers/gpu/drm/etnaviv/etnaviv_gem.c

index bcc8c2d7c7c9c6e77b37b96ee3fd62e1da7f2270,5884ab623e0a22b36b38e9ec02ea4d3a7abba96f..daee3f1196df831b131ad1c229c25fba2d8364b5
--- 1/drivers/gpu/drm/etnaviv/etnaviv_gem.c
--- 2/drivers/gpu/drm/etnaviv/etnaviv_gem.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
@@@ -704,25 -704,6 +704,6 @@@ int etnaviv_gem_new_handle(struct drm_d
         return ret;
   }
   
- struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev,
-               u32 size, u32 flags)
- {
-       struct drm_gem_object *obj;
-       int ret;
- 
-       obj = __etnaviv_gem_new(dev, size, flags);
-       if (IS_ERR(obj))
-               return obj;
- 
-       ret = etnaviv_gem_obj_add(dev, obj);
-       if (ret < 0) {
-               drm_gem_object_put_unlocked(obj);
-               return ERR_PTR(ret);
-       }
- 
-       return obj;
- }
- 
   int etnaviv_gem_new_private(struct drm_device *dev, size_t size, u32 flags,
         struct reservation_object *robj, const struct etnaviv_gem_ops *ops,
         struct etnaviv_gem_object **res)
@@@ -779,7 -760,7 +760,7 @@@ static struct page **etnaviv_gem_userpt
         up_read(&mm->mmap_sem);
   
         if (ret < 0) {
- -              release_pages(pvec, pinned, 0);
+ +              release_pages(pvec, pinned);
                 kvfree(pvec);
                 return ERR_PTR(ret);
         }
@@@ -852,7 -833,7 +833,7 @@@ static int etnaviv_gem_userptr_get_page
                 }
         }
   
- -      release_pages(pvec, pinned, 0);
+ +      release_pages(pvec, pinned);
         kvfree(pvec);
   
         work = kmalloc(sizeof(*work), GFP_KERNEL);
@@@ -886,7 -867,7 +867,7 @@@ static void etnaviv_gem_userptr_release
         if (etnaviv_obj->pages) {
                 int npages = etnaviv_obj->base.size >> PAGE_SHIFT;
   
- -              release_pages(etnaviv_obj->pages, npages, 0);
+ +              release_pages(etnaviv_obj->pages, npages);
                 kvfree(etnaviv_obj->pages);
         }
         put_task_struct(etnaviv_obj->userptr.task);
diff --combined drivers/gpu/drm/etnaviv/etnaviv_gpu.c

index 4b152e0d31a658970f6d7f5387f88d2a299fcbce,8197e1d6ed112e6fbe5cd328178d523187f7819e..e19cbe05da2a31ca9456d2476e388167aedee219
--- 1/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
--- 2/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@@ -25,6 -25,7 +25,7 @@@
   #include "etnaviv_gpu.h"
   #include "etnaviv_gem.h"
   #include "etnaviv_mmu.h"
+ #include "etnaviv_perfmon.h"
   #include "common.xml.h"
   #include "state.xml.h"
   #include "state_hi.xml.h"
@@@ -420,9 -421,10 +421,10 @@@ static void etnaviv_gpu_update_clock(st
                              gpu->base_rate_shader >> gpu->freq_scale);
         } else {
                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
-               u32 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
-                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
+               u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
   
+               clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
+               clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
                 etnaviv_gpu_load_clock(gpu, clock);
         }
   }
@@@ -433,24 -435,14 +435,14 @@@ static int etnaviv_hw_reset(struct etna
         unsigned long timeout;
         bool failed = true;
   
-       /* TODO
-        *
-        * - clock gating
-        * - puls eater
-        * - what about VG?
-        */
- 
         /* We hope that the GPU resets in under one second */
         timeout = jiffies + msecs_to_jiffies(1000);
   
         while (time_is_after_jiffies(timeout)) {
                 /* enable clock */
-               etnaviv_gpu_update_clock(gpu);
- 
-               control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
- 
-               /* Wait for stable clock.  Vivante's code waited for 1ms */
-               usleep_range(1000, 10000);
+               unsigned int fscale = 1 << (6 - gpu->freq_scale);
+               control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
+               etnaviv_gpu_load_clock(gpu, control);
   
                 /* isolate the GPU. */
                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
@@@ -461,7 -453,7 +453,7 @@@
                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
   
                 /* wait for reset. */
-               msleep(1);
+               usleep_range(10, 20);
   
                 /* reset soft reset bit. */
                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
@@@ -490,6 -482,10 +482,10 @@@
                         continue;
                 }
   
+               /* disable debug registers, as they are not normally needed */
+               control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+               gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
+ 
                 failed = false;
                 break;
         }
@@@ -721,7 -717,7 +717,7 @@@ int etnaviv_gpu_init(struct etnaviv_gp
         }
   
         /* Create buffer: */
-       gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0);
+       gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0, 0);
         if (!gpu->buffer) {
                 ret = -ENOMEM;
                 dev_err(gpu->dev, "could not create command buffer\n");
@@@ -739,10 -735,9 +735,9 @@@
         /* Setup event management */
         spin_lock_init(&gpu->event_spinlock);
         init_completion(&gpu->event_free);
-       for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
-               gpu->event[i].used = false;
+       bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
+       for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
                 complete(&gpu->event_free);
-       }
   
         /* Now program the hardware */
         mutex_lock(&gpu->lock);
@@@ -926,7 -921,7 +921,7 @@@ static void recover_worker(struct work_
         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
                                                recover_work);
         unsigned long flags;
-       unsigned int i;
+       unsigned int i = 0;
   
         dev_err(gpu->dev, "hangcheck recover!\n");
   
@@@ -945,14 -940,12 +940,12 @@@
   
         /* complete all events, the GPU won't do it after the reset */
         spin_lock_irqsave(&gpu->event_spinlock, flags);
-       for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
-               if (!gpu->event[i].used)
-                       continue;
+       for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) {
                 dma_fence_signal(gpu->event[i].fence);
                 gpu->event[i].fence = NULL;
-               gpu->event[i].used = false;
                 complete(&gpu->event_free);
         }
+       bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
         gpu->completed_fence = gpu->active_fence;
   
@@@ -975,9 -968,9 +968,9 @@@ static void hangcheck_timer_reset(struc
                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
   }
   
- -static void hangcheck_handler(unsigned long data)
+ +static void hangcheck_handler(struct timer_list *t)
   {
- -      struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
+ +      struct etnaviv_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
         u32 fence = gpu->completed_fence;
         bool progress = false;
   
@@@ -1140,30 -1133,45 +1133,45 @@@ int etnaviv_gpu_fence_sync_obj(struct e
    * event management:
    */
   
- static unsigned int event_alloc(struct etnaviv_gpu *gpu)
+ static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
+       unsigned int *events)
   {
-       unsigned long ret, flags;
-       unsigned int i, event = ~0U;
+       unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
+       unsigned i, acquired = 0;
   
-       ret = wait_for_completion_timeout(&gpu->event_free,
-                                         msecs_to_jiffies(10 * 10000));
-       if (!ret)
-               dev_err(gpu->dev, "wait_for_completion_timeout failed");
+       for (i = 0; i < nr_events; i++) {
+               unsigned long ret;
   
-       spin_lock_irqsave(&gpu->event_spinlock, flags);
+               ret = wait_for_completion_timeout(&gpu->event_free, timeout);
   
-       /* find first free event */
-       for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
-               if (gpu->event[i].used == false) {
-                       gpu->event[i].used = true;
-                       event = i;
-                       break;
+               if (!ret) {
+                       dev_err(gpu->dev, "wait_for_completion_timeout failed");
+                       goto out;
                 }
+ 
+               acquired++;
+               timeout = ret;
+       }
+ 
+       spin_lock_irqsave(&gpu->event_spinlock, flags);
+ 
+       for (i = 0; i < nr_events; i++) {
+               int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
+ 
+               events[i] = event;
+               memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
+               set_bit(event, gpu->event_bitmap);
         }
   
         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
   
-       return event;
+       return 0;
+ 
+ out:
+       for (i = 0; i < acquired; i++)
+               complete(&gpu->event_free);
+ 
+       return -EBUSY;
   }
   
   static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
@@@ -1172,12 -1180,12 +1180,12 @@@
   
         spin_lock_irqsave(&gpu->event_spinlock, flags);
   
-       if (gpu->event[event].used == false) {
+       if (!test_bit(event, gpu->event_bitmap)) {
                 dev_warn(gpu->dev, "event %u is already marked as free",
                          event);
                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
         } else {
-               gpu->event[event].used = false;
+               clear_bit(event, gpu->event_bitmap);
                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
   
                 complete(&gpu->event_free);
@@@ -1311,12 -1319,71 +1319,71 @@@ void etnaviv_gpu_pm_put(struct etnaviv_
         pm_runtime_put_autosuspend(gpu->dev);
   }
   
+ static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
+       struct etnaviv_event *event, unsigned int flags)
+ {
+       const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
+       unsigned int i;
+ 
+       for (i = 0; i < cmdbuf->nr_pmrs; i++) {
+               const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i;
+ 
+               if (pmr->flags == flags)
+                       etnaviv_perfmon_process(gpu, pmr);
+       }
+ }
+ 
+ static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
+       struct etnaviv_event *event)
+ {
+       u32 val;
+ 
+       /* disable clock gating */
+       val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
+       val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
+       gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
+ 
+       /* enable debug register */
+       val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+       val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+       gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
+ 
+       sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
+ }
+ 
+ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
+       struct etnaviv_event *event)
+ {
+       const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
+       unsigned int i;
+       u32 val;
+ 
+       sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
+ 
+       for (i = 0; i < cmdbuf->nr_pmrs; i++) {
+               const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i;
+ 
+               *pmr->bo_vma = pmr->sequence;
+       }
+ 
+       /* disable debug register */
+       val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+       val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+       gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
+ 
+       /* enable clock gating */
+       val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
+       val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
+       gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
+ }
+ 
+ 
   /* add bo's to gpu's ring, and kick gpu: */
   int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
   {
         struct dma_fence *fence;
-       unsigned int event, i;
+       unsigned int i, nr_events = 1, event[3];
         int ret;
   
         ret = etnaviv_gpu_pm_get_sync(gpu);
@@@ -1332,10 -1399,19 +1399,19 @@@
          *
          */
   
-       event = event_alloc(gpu);
-       if (unlikely(event == ~0U)) {
-               DRM_ERROR("no free event\n");
-               ret = -EBUSY;
+       /*
+        * if there are performance monitor requests we need to have
+        * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
+        *   requests.
+        * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
+        *   and update the sequence number for userspace.
+        */
+       if (cmdbuf->nr_pmrs)
+               nr_events = 3;
+ 
+       ret = event_alloc(gpu, nr_events, event);
+       if (ret) {
+               DRM_ERROR("no free events\n");
                 goto out_pm_put;
         }
   
@@@ -1343,12 -1419,14 +1419,14 @@@
   
         fence = etnaviv_gpu_fence_alloc(gpu);
         if (!fence) {
-               event_free(gpu, event);
+               for (i = 0; i < nr_events; i++)
+                       event_free(gpu, event[i]);
+ 
                 ret = -ENOMEM;
                 goto out_unlock;
         }
   
-       gpu->event[event].fence = fence;
+       gpu->event[event[0]].fence = fence;
         submit->fence = dma_fence_get(fence);
         gpu->active_fence = submit->fence->seqno;
   
@@@ -1358,7 -1436,19 +1436,19 @@@
                 gpu->lastctx = cmdbuf->ctx;
         }
   
-       etnaviv_buffer_queue(gpu, event, cmdbuf);
+       if (cmdbuf->nr_pmrs) {
+               gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
+               gpu->event[event[1]].cmdbuf = cmdbuf;
+               etnaviv_sync_point_queue(gpu, event[1]);
+       }
+ 
+       etnaviv_buffer_queue(gpu, event[0], cmdbuf);
+ 
+       if (cmdbuf->nr_pmrs) {
+               gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
+               gpu->event[event[2]].cmdbuf = cmdbuf;
+               etnaviv_sync_point_queue(gpu, event[2]);
+       }
   
         cmdbuf->fence = fence;
         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
@@@ -1394,6 -1484,24 +1484,24 @@@ out_pm_put
         return ret;
   }
   
+ static void etnaviv_process_sync_point(struct etnaviv_gpu *gpu,
+       struct etnaviv_event *event)
+ {
+       u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
+ 
+       event->sync_point(gpu, event);
+       etnaviv_gpu_start_fe(gpu, addr + 2, 2);
+ }
+ 
+ static void sync_point_worker(struct work_struct *work)
+ {
+       struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
+                                              sync_point_work);
+ 
+       etnaviv_process_sync_point(gpu, &gpu->event[gpu->sync_point_event]);
+       event_free(gpu, gpu->sync_point_event);
+ }
+ 
   /*
    * Init/Cleanup:
    */
@@@ -1440,7 -1548,15 +1548,15 @@@ static irqreturn_t irq_handler(int irq
   
                         dev_dbg(gpu->dev, "event %u\n", event);
   
+                       if (gpu->event[event].sync_point) {
+                               gpu->sync_point_event = event;
+                               etnaviv_queue_work(gpu->drm, &gpu->sync_point_work);
+                       }
+ 
                         fence = gpu->event[event].fence;
+                       if (!fence)
+                               continue;
+ 
                         gpu->event[event].fence = NULL;
                         dma_fence_signal(fence);
   
@@@ -1645,10 -1761,12 +1761,11 @@@ static int etnaviv_gpu_bind(struct devi
   
         INIT_LIST_HEAD(&gpu->active_cmd_list);
         INIT_WORK(&gpu->retire_work, retire_worker);
+       INIT_WORK(&gpu->sync_point_work, sync_point_worker);
         INIT_WORK(&gpu->recover_work, recover_worker);
         init_waitqueue_head(&gpu->fence_event);
   
- -      setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler,
- -                             (unsigned long)gpu);
+ +      timer_setup(&gpu->hangcheck_timer, hangcheck_handler, TIMER_DEFERRABLE);
   
         priv->gpu[priv->num_gpus++] = gpu;
   
diff --combined drivers/gpu/drm/i915/Makefile

index 2e034efc4d6d84b60d273fd78e205721f2d057b4,6c3b0481ef82906afda59b32d95150dbd977d6d8..2acf3b3c5f9d186f3fe8421cba23e87d1c0032cd
--- 1/drivers/gpu/drm/i915/Makefile
--- 2/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   #
   # Makefile for the drm device driver.  This driver provides support for the
   # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
@@@ -48,6 -47,7 +48,7 @@@ i915-y += i915_cmd_parser.o 
           i915_gem_tiling.o \
           i915_gem_timeline.o \
           i915_gem_userptr.o \
+         i915_gemfs.o \
           i915_trace_points.o \
           i915_vma.o \
           intel_breadcrumbs.o \
@@@ -60,9 -60,11 +61,11 @@@
   
   # general-purpose microcontroller (GuC) support
   i915-y += intel_uc.o \
+         intel_uc_fw.o \
+         intel_guc.o \
           intel_guc_ct.o \
           intel_guc_log.o \
-         intel_guc_loader.o \
+         intel_guc_fw.o \
           intel_huc.o \
           i915_guc_submission.o
   
@@@ -140,7 -142,8 +143,8 @@@ i915-y += i915_perf.o 
           i915_oa_bxt.o \
           i915_oa_kblgt2.o \
           i915_oa_kblgt3.o \
-         i915_oa_glk.o
+         i915_oa_glk.o \
+         i915_oa_cflgt2.o
   
   ifeq ($(CONFIG_DRM_I915_GVT),y)
   i915-y += intel_gvt.o
@@@ -151,5 -154,3 +155,3 @@@ endi
   i915-y += intel_lpe_audio.o
   
   obj-$(CONFIG_DRM_I915) += i915.o
- 
- CFLAGS_i915_trace_points.o := -I$(src)
diff --combined drivers/gpu/drm/i915/i915_drv.c

index f124de3a0668d5f02f3b0015bdacd4c78177f8cc,3db5851756f060fd23241aa4dd448f4d71530368..960d3d8b95b8e5d647b85b2baed7b2c5b68d83cf
--- 1/drivers/gpu/drm/i915/i915_drv.c
--- 2/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -58,12 -58,12 +58,12 @@@ static unsigned int i915_load_fail_coun
   
   bool __i915_inject_load_failure(const char *func, int line)
   {
-       if (i915_load_fail_count >= i915.inject_load_failure)
+       if (i915_load_fail_count >= i915_modparams.inject_load_failure)
                 return false;
   
-       if (++i915_load_fail_count == i915.inject_load_failure) {
+       if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
-                        i915.inject_load_failure, func, line);
+                        i915_modparams.inject_load_failure, func, line);
                 return true;
         }
   
@@@ -106,8 -106,8 +106,8 @@@ __i915_printk(struct drm_i915_private *
   
   static bool i915_error_injected(struct drm_i915_private *dev_priv)
   {
-       return i915.inject_load_failure &&
-              i915_load_fail_count == i915.inject_load_failure;
+       return i915_modparams.inject_load_failure &&
+              i915_load_fail_count == i915_modparams.inject_load_failure;
   }
   
   #define i915_load_error(dev_priv, fmt, ...)                                \
@@@ -239,7 -239,8 +239,8 @@@ static void intel_detect_pch(struct drm
                                 dev_priv->pch_type = PCH_KBP;
                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
-                                       !IS_KABYLAKE(dev_priv));
+                                       !IS_KABYLAKE(dev_priv) &&
+                                       !IS_COFFEELAKE(dev_priv));
                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_CNP;
                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
@@@ -320,7 -321,7 +321,7 @@@ static int i915_getparam(struct drm_dev
                 value = USES_PPGTT(dev_priv);
                 break;
         case I915_PARAM_HAS_SEMAPHORES:
-               value = i915.semaphores;
+               value = i915_modparams.semaphores;
                 break;
         case I915_PARAM_HAS_SECURE_BATCHES:
                 value = capable(CAP_SYS_ADMIN);
@@@ -339,7 -340,8 +340,8 @@@
                         return -ENODEV;
                 break;
         case I915_PARAM_HAS_GPU_RESET:
-               value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
+               value = i915_modparams.enable_hangcheck &&
+                       intel_has_gpu_reset(dev_priv);
                 if (value && intel_has_reset_engine(dev_priv))
                         value = 2;
                 break;
@@@ -365,9 -367,18 +367,18 @@@
                 value = i915_gem_mmap_gtt_version();
                 break;
         case I915_PARAM_HAS_SCHEDULER:
-               value = dev_priv->engine[RCS] &&
-                       dev_priv->engine[RCS]->schedule;
+               value = 0;
+               if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
+                       value |= I915_SCHEDULER_CAP_ENABLED;
+                       value |= I915_SCHEDULER_CAP_PRIORITY;
+ 
+                       if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
+                           i915_modparams.enable_execlists &&
+                           !i915_modparams.enable_guc_submission)
+                               value |= I915_SCHEDULER_CAP_PREEMPTION;
+               }
                 break;
+ 
         case I915_PARAM_MMAP_VERSION:
                 /* Remember to bump this if the version changes! */
         case I915_PARAM_HAS_GEM:
@@@ -604,9 -615,10 +615,10 @@@ static void i915_gem_fini(struct drm_i9
         intel_uc_fini_hw(dev_priv);
         i915_gem_cleanup_engines(dev_priv);
         i915_gem_contexts_fini(dev_priv);
-       i915_gem_cleanup_userptr(dev_priv);
         mutex_unlock(&dev_priv->drm.struct_mutex);
   
+       i915_gem_cleanup_userptr(dev_priv);
+ 
         i915_gem_drain_freed_objects(dev_priv);
   
         WARN_ON(!list_empty(&dev_priv->contexts.list));
@@@ -868,6 -880,10 +880,10 @@@ static int i915_driver_init_early(struc
         memcpy(device_info, match_info, sizeof(*device_info));
         device_info->device_id = dev_priv->drm.pdev->device;
   
+       BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+                    sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+       device_info->platform_mask = BIT(device_info->platform);
+ 
         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
         device_info->gen_mask = BIT(device_info->gen - 1);
   
@@@ -1001,6 -1017,8 +1017,8 @@@ static int i915_driver_init_mmio(struc
   
         intel_uncore_init(dev_priv);
   
+       intel_uc_init_mmio(dev_priv);
+ 
         ret = intel_engines_init_mmio(dev_priv);
         if (ret)
                 goto err_uncore;
@@@ -1030,9 -1048,9 +1048,9 @@@ static void i915_driver_cleanup_mmio(st
   
   static void intel_sanitize_options(struct drm_i915_private *dev_priv)
   {
-       i915.enable_execlists =
+       i915_modparams.enable_execlists =
                 intel_sanitize_enable_execlists(dev_priv,
-                                               i915.enable_execlists);
+                                               i915_modparams.enable_execlists);
   
         /*
          * i915.enable_ppgtt is read-only, so do an early pass to validate the
@@@ -1040,12 -1058,15 +1058,15 @@@
          * do this now so that we can print out any log messages once rather
          * than every time we check intel_enable_ppgtt().
          */
-       i915.enable_ppgtt =
-               intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
-       DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
+       i915_modparams.enable_ppgtt =
+               intel_sanitize_enable_ppgtt(dev_priv,
+                                           i915_modparams.enable_ppgtt);
+       DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
   
-       i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
-       DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
+       i915_modparams.semaphores =
+               intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
+       DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
+                        yesno(i915_modparams.semaphores));
   
         intel_uc_sanitize_options(dev_priv);
   
@@@ -1276,7 -1297,7 +1297,7 @@@ int i915_driver_load(struct pci_dev *pd
         int ret;
   
         /* Enable nuclear pageflip on ILK+ */
-       if (!i915.nuclear_pageflip && match_info->gen < 5)
+       if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
                 driver.driver_features &= ~DRIVER_ATOMIC;
   
         ret = -ENOMEM;
@@@ -1304,7 -1325,7 +1325,7 @@@
          * becaue the HDA driver may require us to enable the audio power
          * domain during system suspend.
          */
- -      pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
+ +      dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
   
         ret = i915_driver_init_early(dev_priv, ent);
         if (ret < 0)
@@@ -1340,7 -1361,7 +1361,7 @@@
   
         intel_runtime_pm_enable(dev_priv);
   
-       dev_priv->ipc_enabled = false;
+       intel_init_ipc(dev_priv);
   
         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
                 DRM_INFO("DRM_I915_DEBUG enabled\n");
@@@ -1571,7 -1592,7 +1592,7 @@@ static int i915_drm_suspend_late(struc
   
         intel_display_set_init_power(dev_priv, false);
   
-       fw_csr = !IS_GEN9_LP(dev_priv) &&
+       fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
         /*
          * In case of firmware assisted context save/restore don't manually
@@@ -2061,11 -2082,14 +2082,14 @@@ static int i915_pm_resume(struct devic
   /* freeze: before creating the hibernation_image */
   static int i915_pm_freeze(struct device *kdev)
   {
+       struct drm_device *dev = &kdev_to_i915(kdev)->drm;
         int ret;
   
-       ret = i915_pm_suspend(kdev);
-       if (ret)
-               return ret;
+       if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
+               ret = i915_drm_suspend(dev);
+               if (ret)
+                       return ret;
+       }
   
         ret = i915_gem_freeze(kdev_to_i915(kdev));
         if (ret)
@@@ -2076,11 -2100,14 +2100,14 @@@
   
   static int i915_pm_freeze_late(struct device *kdev)
   {
+       struct drm_device *dev = &kdev_to_i915(kdev)->drm;
         int ret;
   
-       ret = i915_pm_suspend_late(kdev);
-       if (ret)
-               return ret;
+       if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
+               ret = i915_drm_suspend_late(dev, true);
+               if (ret)
+                       return ret;
+       }
   
         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
         if (ret)
@@@ -2476,7 -2503,7 +2503,7 @@@ static int intel_runtime_suspend(struc
         struct drm_i915_private *dev_priv = to_i915(dev);
         int ret;
   
-       if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+       if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled())))
                 return -ENODEV;
   
         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
@@@ -2518,12 -2545,12 +2545,12 @@@
         intel_uncore_suspend(dev_priv);
   
         enable_rpm_wakeref_asserts(dev_priv);
-       WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
+       WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
   
         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
   
-       dev_priv->pm.suspended = true;
+       dev_priv->runtime_pm.suspended = true;
   
         /*
          * FIXME: We really should find a document that references the arguments
@@@ -2569,11 -2596,11 +2596,11 @@@ static int intel_runtime_resume(struct 
   
         DRM_DEBUG_KMS("Resuming device\n");
   
-       WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
+       WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
         disable_rpm_wakeref_asserts(dev_priv);
   
         intel_opregion_notify_adapter(dev_priv, PCI_D0);
-       dev_priv->pm.suspended = false;
+       dev_priv->runtime_pm.suspended = false;
         if (intel_uncore_unclaimed_mmio(dev_priv))
                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
   
@@@ -2608,6 -2635,8 +2635,8 @@@
         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
                 intel_hpd_init(dev_priv);
   
+       intel_enable_ipc(dev_priv);
+ 
         enable_rpm_wakeref_asserts(dev_priv);
   
         if (ret)
diff --combined drivers/gpu/drm/i915/i915_gem.c

index dc1faa49687d148876b1089e517af3e66e110d6a,94b23fcbc989d35e3e24467c32f53ff3839cfc29..3a140eedfc83079b734c39cea63b85932d002159
--- 1/drivers/gpu/drm/i915/i915_gem.c
--- 2/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@@ -35,6 -35,7 +35,7 @@@
   #include "intel_drv.h"
   #include "intel_frontbuffer.h"
   #include "intel_mocs.h"
+ #include "i915_gemfs.h"
   #include <linux/dma-fence-array.h>
   #include <linux/kthread.h>
   #include <linux/reservation.h>
@@@ -55,7 -56,7 +56,7 @@@ static bool cpu_write_needs_clflush(str
         if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
                 return true;
   
-       return obj->pin_display;
+       return obj->pin_global; /* currently in use by HW, keep flushed */
   }
   
   static int
@@@ -161,8 -162,7 +162,7 @@@ i915_gem_get_aperture_ioctl(struct drm_
         return 0;
   }
   
- static struct sg_table *
- i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
+ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
   {
         struct address_space *mapping = obj->base.filp->f_mapping;
         drm_dma_handle_t *phys;
@@@ -170,19 -170,20 +170,20 @@@
         struct scatterlist *sg;
         char *vaddr;
         int i;
+       int err;
   
         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
-               return ERR_PTR(-EINVAL);
+               return -EINVAL;
   
         /* Always aligning to the object size, allows a single allocation
          * to handle all possible callers, and given typical object sizes,
          * the alignment of the buddy allocation will naturally match.
          */
         phys = drm_pci_alloc(obj->base.dev,
-                            obj->base.size,
+                            roundup_pow_of_two(obj->base.size),
                              roundup_pow_of_two(obj->base.size));
         if (!phys)
-               return ERR_PTR(-ENOMEM);
+               return -ENOMEM;
   
         vaddr = phys->vaddr;
         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
@@@ -191,7 -192,7 +192,7 @@@
   
                 page = shmem_read_mapping_page(mapping, i);
                 if (IS_ERR(page)) {
-                       st = ERR_CAST(page);
+                       err = PTR_ERR(page);
                         goto err_phys;
                 }
   
@@@ -208,13 -209,13 +209,13 @@@
   
         st = kmalloc(sizeof(*st), GFP_KERNEL);
         if (!st) {
-               st = ERR_PTR(-ENOMEM);
+               err = -ENOMEM;
                 goto err_phys;
         }
   
         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
                 kfree(st);
-               st = ERR_PTR(-ENOMEM);
+               err = -ENOMEM;
                 goto err_phys;
         }
   
@@@ -226,11 -227,15 +227,15 @@@
         sg_dma_len(sg) = obj->base.size;
   
         obj->phys_handle = phys;
-       return st;
+ 
+       __i915_gem_object_set_pages(obj, st, sg->length);
+ 
+       return 0;
   
   err_phys:
         drm_pci_free(obj->base.dev, phys);
-       return st;
+ 
+       return err;
   }
   
   static void __start_cpu_write(struct drm_i915_gem_object *obj)
@@@ -353,7 -358,7 +358,7 @@@ static lon
   i915_gem_object_wait_fence(struct dma_fence *fence,
                            unsigned int flags,
                            long timeout,
-                          struct intel_rps_client *rps)
+                          struct intel_rps_client *rps_client)
   {
         struct drm_i915_gem_request *rq;
   
@@@ -386,11 -391,11 +391,11 @@@
          * forcing the clocks too high for the whole system, we only allow
          * each client to waitboost once in a busy period.
          */
-       if (rps) {
+       if (rps_client) {
                 if (INTEL_GEN(rq->i915) >= 6)
-                       gen6_rps_boost(rq, rps);
+                       gen6_rps_boost(rq, rps_client);
                 else
-                       rps = NULL;
+                       rps_client = NULL;
         }
   
         timeout = i915_wait_request(rq, flags, timeout);
@@@ -406,7 -411,7 +411,7 @@@ static lon
   i915_gem_object_wait_reservation(struct reservation_object *resv,
                                  unsigned int flags,
                                  long timeout,
-                                struct intel_rps_client *rps)
+                                struct intel_rps_client *rps_client)
   {
         unsigned int seq = __read_seqcount_begin(&resv->seq);
         struct dma_fence *excl;
@@@ -425,7 -430,7 +430,7 @@@
                 for (i = 0; i < count; i++) {
                         timeout = i915_gem_object_wait_fence(shared[i],
                                                              flags, timeout,
-                                                            rps);
+                                                            rps_client);
                         if (timeout < 0)
                                 break;
   
@@@ -442,7 -447,8 +447,8 @@@
         }
   
         if (excl && timeout >= 0) {
-               timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
+               timeout = i915_gem_object_wait_fence(excl, flags, timeout,
+                                                    rps_client);
                 prune_fences = timeout >= 0;
         }
   
@@@ -538,7 -544,7 +544,7 @@@ in
   i915_gem_object_wait(struct drm_i915_gem_object *obj,
                      unsigned int flags,
                      long timeout,
-                    struct intel_rps_client *rps)
+                    struct intel_rps_client *rps_client)
   {
         might_sleep();
   #if IS_ENABLED(CONFIG_LOCKDEP)
@@@ -550,7 -556,7 +556,7 @@@
   
         timeout = i915_gem_object_wait_reservation(obj->resv,
                                                    flags, timeout,
-                                                  rps);
+                                                  rps_client);
         return timeout < 0 ? timeout : 0;
   }
   
@@@ -558,7 -564,7 +564,7 @@@ static struct intel_rps_client *to_rps_
   {
         struct drm_i915_file_private *fpriv = file->driver_priv;
   
-       return &fpriv->rps;
+       return &fpriv->rps_client;
   }
   
   static int
@@@ -694,10 -700,10 +700,10 @@@ flush_write_domain(struct drm_i915_gem_
   
         switch (obj->base.write_domain) {
         case I915_GEM_DOMAIN_GTT:
-               if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
+               if (!HAS_LLC(dev_priv)) {
                         intel_runtime_pm_get(dev_priv);
                         spin_lock_irq(&dev_priv->uncore.lock);
-                       POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+                       POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
                         spin_unlock_irq(&dev_priv->uncore.lock);
                         intel_runtime_pm_put(dev_priv);
                 }
@@@ -1013,17 -1019,20 +1019,20 @@@ gtt_user_read(struct io_mapping *mappin
               loff_t base, int offset,
               char __user *user_data, int length)
   {
-       void *vaddr;
+       void __iomem *vaddr;
         unsigned long unwritten;
   
         /* We can use the cpu mem copy function because this is X86. */
-       vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
-       unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
+       vaddr = io_mapping_map_atomic_wc(mapping, base);
+       unwritten = __copy_to_user_inatomic(user_data,
+                                           (void __force *)vaddr + offset,
+                                           length);
         io_mapping_unmap_atomic(vaddr);
         if (unwritten) {
-               vaddr = (void __force *)
-                       io_mapping_map_wc(mapping, base, PAGE_SIZE);
-               unwritten = copy_to_user(user_data, vaddr + offset, length);
+               vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
+               unwritten = copy_to_user(user_data,
+                                        (void __force *)vaddr + offset,
+                                        length);
                 io_mapping_unmap(vaddr);
         }
         return unwritten;
@@@ -1047,7 -1056,9 +1056,9 @@@ i915_gem_gtt_pread(struct drm_i915_gem_
   
         intel_runtime_pm_get(i915);
         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
-                                      PIN_MAPPABLE | PIN_NONBLOCK);
+                                      PIN_MAPPABLE |
+                                      PIN_NONFAULT |
+                                      PIN_NONBLOCK);
         if (!IS_ERR(vma)) {
                 node.start = i915_ggtt_offset(vma);
                 node.allocated = false;
@@@ -1189,18 -1200,18 +1200,18 @@@ ggtt_write(struct io_mapping *mapping
            loff_t base, int offset,
            char __user *user_data, int length)
   {
-       void *vaddr;
+       void __iomem *vaddr;
         unsigned long unwritten;
   
         /* We can use the cpu mem copy function because this is X86. */
-       vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
-       unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
+       vaddr = io_mapping_map_atomic_wc(mapping, base);
+       unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
                                                       user_data, length);
         io_mapping_unmap_atomic(vaddr);
         if (unwritten) {
-               vaddr = (void __force *)
-                       io_mapping_map_wc(mapping, base, PAGE_SIZE);
-               unwritten = copy_from_user(vaddr + offset, user_data, length);
+               vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
+               unwritten = copy_from_user((void __force *)vaddr + offset,
+                                          user_data, length);
                 io_mapping_unmap(vaddr);
         }
   
@@@ -1229,9 -1240,27 +1240,27 @@@ i915_gem_gtt_pwrite_fast(struct drm_i91
         if (ret)
                 return ret;
   
-       intel_runtime_pm_get(i915);
+       if (i915_gem_object_has_struct_page(obj)) {
+               /*
+                * Avoid waking the device up if we can fallback, as
+                * waking/resuming is very slow (worst-case 10-100 ms
+                * depending on PCI sleeps and our own resume time).
+                * This easily dwarfs any performance advantage from
+                * using the cache bypass of indirect GGTT access.
+                */
+               if (!intel_runtime_pm_get_if_in_use(i915)) {
+                       ret = -EFAULT;
+                       goto out_unlock;
+               }
+       } else {
+               /* No backing pages, no fallback, we must force GGTT access */
+               intel_runtime_pm_get(i915);
+       }
+ 
         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
-                                      PIN_MAPPABLE | PIN_NONBLOCK);
+                                      PIN_MAPPABLE |
+                                      PIN_NONFAULT |
+                                      PIN_NONBLOCK);
         if (!IS_ERR(vma)) {
                 node.start = i915_ggtt_offset(vma);
                 node.allocated = false;
@@@ -1244,7 -1273,7 +1273,7 @@@
         if (IS_ERR(vma)) {
                 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
                 if (ret)
-                       goto out_unlock;
+                       goto out_rpm;
                 GEM_BUG_ON(!node.allocated);
         }
   
@@@ -1307,8 -1336,9 +1336,9 @@@ out_unpin
         } else {
                 i915_vma_unpin(vma);
         }
- out_unlock:
+ out_rpm:
         intel_runtime_pm_put(i915);
+ out_unlock:
         mutex_unlock(&i915->drm.struct_mutex);
         return ret;
   }
@@@ -1524,6 -1554,8 +1554,8 @@@ static void i915_gem_object_bump_inacti
         struct list_head *list;
         struct i915_vma *vma;
   
+       GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+ 
         list_for_each_entry(vma, &obj->vma_list, obj_link) {
                 if (!i915_vma_is_ggtt(vma))
                         break;
@@@ -1538,8 -1570,10 +1570,10 @@@
         }
   
         i915 = to_i915(obj->base.dev);
+       spin_lock(&i915->mm.obj_lock);
         list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
-       list_move_tail(&obj->global_link, list);
+       list_move_tail(&obj->mm.link, list);
+       spin_unlock(&i915->mm.obj_lock);
   }
   
   /**
@@@ -1902,22 -1936,27 +1936,27 @@@ int i915_gem_fault(struct vm_fault *vmf
         if (ret)
                 goto err_unpin;
   
-       ret = i915_vma_get_fence(vma);
+       ret = i915_vma_pin_fence(vma);
         if (ret)
                 goto err_unpin;
   
-       /* Mark as being mmapped into userspace for later revocation */
-       assert_rpm_wakelock_held(dev_priv);
-       if (list_empty(&obj->userfault_link))
-               list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
- 
         /* Finally, remap it using the new GTT offset */
         ret = remap_io_mapping(area,
                                area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
                                (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
                                min_t(u64, vma->size, area->vm_end - area->vm_start),
                                &ggtt->mappable);
+       if (ret)
+               goto err_fence;
   
+       /* Mark as being mmapped into userspace for later revocation */
+       assert_rpm_wakelock_held(dev_priv);
+       if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)
+               list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
+       GEM_BUG_ON(!obj->userfault_count);
+ 
+ err_fence:
+       i915_vma_unpin_fence(vma);
   err_unpin:
         __i915_vma_unpin(vma);
   err_unlock:
@@@ -1969,6 -2008,25 +2008,25 @@@ err
         return ret;
   }
   
+ static void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
+ {
+       struct i915_vma *vma;
+ 
+       GEM_BUG_ON(!obj->userfault_count);
+ 
+       obj->userfault_count = 0;
+       list_del(&obj->userfault_link);
+       drm_vma_node_unmap(&obj->base.vma_node,
+                          obj->base.dev->anon_inode->i_mapping);
+ 
+       list_for_each_entry(vma, &obj->vma_list, obj_link) {
+               if (!i915_vma_is_ggtt(vma))
+                       break;
+ 
+               i915_vma_unset_userfault(vma);
+       }
+ }
+ 
   /**
    * i915_gem_release_mmap - remove physical page mappings
    * @obj: obj in question
@@@ -1999,12 -2057,10 +2057,10 @@@ i915_gem_release_mmap(struct drm_i915_g
         lockdep_assert_held(&i915->drm.struct_mutex);
         intel_runtime_pm_get(i915);
   
-       if (list_empty(&obj->userfault_link))
+       if (!obj->userfault_count)
                 goto out;
   
-       list_del_init(&obj->userfault_link);
-       drm_vma_node_unmap(&obj->base.vma_node,
-                          obj->base.dev->anon_inode->i_mapping);
+       __i915_gem_object_release_mmap(obj);
   
         /* Ensure that the CPU's PTE are revoked and there are not outstanding
          * memory transactions from userspace before we return. The TLB
@@@ -2032,11 -2088,8 +2088,8 @@@ void i915_gem_runtime_suspend(struct dr
          */
   
         list_for_each_entry_safe(obj, on,
-                                &dev_priv->mm.userfault_list, userfault_link) {
-               list_del_init(&obj->userfault_link);
-               drm_vma_node_unmap(&obj->base.vma_node,
-                                  obj->base.dev->anon_inode->i_mapping);
-       }
+                                &dev_priv->mm.userfault_list, userfault_link)
+               __i915_gem_object_release_mmap(obj);
   
         /* The fence will be lost when the device powers down. If any were
          * in use by hardware (i.e. they are pinned), we should not be powering
@@@ -2059,7 -2112,7 +2112,7 @@@
                 if (!reg->vma)
                         continue;
   
-               GEM_BUG_ON(!list_empty(&reg->vma->obj->userfault_link));
+               GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
                 reg->dirty = true;
         }
   }
@@@ -2164,7 -2217,7 +2217,7 @@@ void __i915_gem_object_invalidate(struc
         struct address_space *mapping;
   
         lockdep_assert_held(&obj->mm.lock);
-       GEM_BUG_ON(obj->mm.pages);
+       GEM_BUG_ON(i915_gem_object_has_pages(obj));
   
         switch (obj->mm.madv) {
         case I915_MADV_DONTNEED:
@@@ -2214,22 -2267,21 +2267,23 @@@ static void __i915_gem_object_reset_pag
         struct radix_tree_iter iter;
         void __rcu **slot;
   
+ +      rcu_read_lock();
         radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
                 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
+ +      rcu_read_unlock();
   }
   
   void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
                                  enum i915_mm_subclass subclass)
   {
+       struct drm_i915_private *i915 = to_i915(obj->base.dev);
         struct sg_table *pages;
   
         if (i915_gem_object_has_pinned_pages(obj))
                 return;
   
         GEM_BUG_ON(obj->bind_count);
-       if (!READ_ONCE(obj->mm.pages))
+       if (!i915_gem_object_has_pages(obj))
                 return;
   
         /* May be called by shrinker from within get_pages() (on another bo) */
@@@ -2243,6 -2295,10 +2297,10 @@@
         pages = fetch_and_zero(&obj->mm.pages);
         GEM_BUG_ON(!pages);
   
+       spin_lock(&i915->mm.obj_lock);
+       list_del(&obj->mm.link);
+       spin_unlock(&i915->mm.obj_lock);
+ 
         if (obj->mm.mapping) {
                 void *ptr;
   
@@@ -2260,6 -2316,8 +2318,8 @@@
         if (!IS_ERR(pages))
                 obj->ops->put_pages(obj, pages);
   
+       obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
+ 
   unlock:
         mutex_unlock(&obj->mm.lock);
   }
@@@ -2290,8 -2348,7 +2350,7 @@@ static bool i915_sg_trim(struct sg_tabl
         return true;
   }
   
- static struct sg_table *
- i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
+ static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
   {
         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
         const unsigned long page_count = obj->base.size / PAGE_SIZE;
@@@ -2302,7 -2359,8 +2361,8 @@@
         struct sgt_iter sgt_iter;
         struct page *page;
         unsigned long last_pfn = 0;     /* suppress gcc warning */
-       unsigned int max_segment;
+       unsigned int max_segment = i915_sg_segment_size();
+       unsigned int sg_page_sizes;
         gfp_t noreclaim;
         int ret;
   
@@@ -2313,18 -2371,14 +2373,14 @@@
         GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
         GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
   
-       max_segment = swiotlb_max_segment();
-       if (!max_segment)
-               max_segment = rounddown(UINT_MAX, PAGE_SIZE);
- 
         st = kmalloc(sizeof(*st), GFP_KERNEL);
         if (st == NULL)
-               return ERR_PTR(-ENOMEM);
+               return -ENOMEM;
   
   rebuild_st:
         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
                 kfree(st);
-               return ERR_PTR(-ENOMEM);
+               return -ENOMEM;
         }
   
         /* Get the list of pages out of our struct file.  They'll be pinned
@@@ -2338,6 -2392,7 +2394,7 @@@
   
         sg = st->sgl;
         st->nents = 0;
+       sg_page_sizes = 0;
         for (i = 0; i < page_count; i++) {
                 const unsigned int shrink[] = {
                         I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE,
@@@ -2390,8 -2445,10 +2447,10 @@@
                 if (!i ||
                     sg->length >= max_segment ||
                     page_to_pfn(page) != last_pfn + 1) {
-                       if (i)
+                       if (i) {
+                               sg_page_sizes |= sg->length;
                                 sg = sg_next(sg);
+                       }
                         st->nents++;
                         sg_set_page(sg, page, PAGE_SIZE, 0);
                 } else {
@@@ -2402,8 -2459,10 +2461,10 @@@
                 /* Check that the i965g/gm workaround works. */
                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
         }
-       if (sg) /* loop terminated early; short sg table */
+       if (sg) { /* loop terminated early; short sg table */
+               sg_page_sizes |= sg->length;
                 sg_mark_end(sg);
+       }
   
         /* Trim unused sg entries to avoid wasting memory. */
         i915_sg_trim(st);
@@@ -2432,7 -2491,9 +2493,9 @@@
         if (i915_gem_object_needs_bit17_swizzle(obj))
                 i915_gem_object_do_bit_17_swizzle(obj, st);
   
-       return st;
+       __i915_gem_object_set_pages(obj, st, sg_page_sizes);
+ 
+       return 0;
   
   err_sg:
         sg_mark_end(sg);
@@@ -2453,12 -2514,17 +2516,17 @@@ err_pages
         if (ret == -ENOSPC)
                 ret = -ENOMEM;
   
-       return ERR_PTR(ret);
+       return ret;
   }
   
   void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
-                                struct sg_table *pages)
+                                struct sg_table *pages,
+                                unsigned int sg_page_sizes)
   {
+       struct drm_i915_private *i915 = to_i915(obj->base.dev);
+       unsigned long supported = INTEL_INFO(i915)->page_sizes;
+       int i;
+ 
         lockdep_assert_held(&obj->mm.lock);
   
         obj->mm.get_page.sg_pos = pages->sgl;
@@@ -2467,30 -2533,48 +2535,48 @@@
         obj->mm.pages = pages;
   
         if (i915_gem_object_is_tiled(obj) &&
-           to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+           i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
                 GEM_BUG_ON(obj->mm.quirked);
                 __i915_gem_object_pin_pages(obj);
                 obj->mm.quirked = true;
         }
+ 
+       GEM_BUG_ON(!sg_page_sizes);
+       obj->mm.page_sizes.phys = sg_page_sizes;
+ 
+       /*
+        * Calculate the supported page-sizes which fit into the given
+        * sg_page_sizes. This will give us the page-sizes which we may be able
+        * to use opportunistically when later inserting into the GTT. For
+        * example if phys=2G, then in theory we should be able to use 1G, 2M,
+        * 64K or 4K pages, although in practice this will depend on a number of
+        * other factors.
+        */
+       obj->mm.page_sizes.sg = 0;
+       for_each_set_bit(i, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) {
+               if (obj->mm.page_sizes.phys & ~0u << i)
+                       obj->mm.page_sizes.sg |= BIT(i);
+       }
+       GEM_BUG_ON(!HAS_PAGE_SIZES(i915, obj->mm.page_sizes.sg));
+ 
+       spin_lock(&i915->mm.obj_lock);
+       list_add(&obj->mm.link, &i915->mm.unbound_list);
+       spin_unlock(&i915->mm.obj_lock);
   }
   
   static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
   {
-       struct sg_table *pages;
- 
-       GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
+       int err;
   
         if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
                 return -EFAULT;
         }
   
-       pages = obj->ops->get_pages(obj);
-       if (unlikely(IS_ERR(pages)))
-               return PTR_ERR(pages);
+       err = obj->ops->get_pages(obj);
+       GEM_BUG_ON(!err && IS_ERR_OR_NULL(obj->mm.pages));
   
-       __i915_gem_object_set_pages(obj, pages);
-       return 0;
+       return err;
   }
   
   /* Ensure that the associated pages are gathered from the backing storage
@@@ -2508,7 -2592,9 +2594,9 @@@ int __i915_gem_object_get_pages(struct 
         if (err)
                 return err;
   
-       if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
+       if (unlikely(!i915_gem_object_has_pages(obj))) {
+               GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
+ 
                 err = ____i915_gem_object_get_pages(obj);
                 if (err)
                         goto unlock;
@@@ -2591,7 -2677,9 +2679,9 @@@ void *i915_gem_object_pin_map(struct dr
         type &= ~I915_MAP_OVERRIDE;
   
         if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
-               if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
+               if (unlikely(!i915_gem_object_has_pages(obj))) {
+                       GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
+ 
                         ret = ____i915_gem_object_get_pages(obj);
                         if (ret)
                                 goto err_unlock;
@@@ -2601,7 -2689,7 +2691,7 @@@
                 atomic_inc(&obj->mm.pages_pin_count);
                 pinned = false;
         }
-       GEM_BUG_ON(!obj->mm.pages);
+       GEM_BUG_ON(!i915_gem_object_has_pages(obj));
   
         ptr = page_unpack_bits(obj->mm.mapping, &has_type);
         if (ptr && has_type != type) {
@@@ -2656,7 -2744,7 +2746,7 @@@ i915_gem_object_pwrite_gtt(struct drm_i
          * allows it to avoid the cost of retrieving a page (either swapin
          * or clearing-before-use) before it is overwritten.
          */
-       if (READ_ONCE(obj->mm.pages))
+       if (i915_gem_object_has_pages(obj))
                 return -ENODEV;
   
         if (obj->mm.madv != I915_MADV_WILLNEED)
@@@ -2800,7 -2888,17 +2890,17 @@@ i915_gem_reset_prepare_engine(struct in
   {
         struct drm_i915_gem_request *request = NULL;
   
-       /* Prevent the signaler thread from updating the request
+       /*
+        * During the reset sequence, we must prevent the engine from
+        * entering RC6. As the context state is undefined until we restart
+        * the engine, if it does enter RC6 during the reset, the state
+        * written to the powercontext is undefined and so we may lose
+        * GPU state upon resume, i.e. fail to restart after a reset.
+        */
+       intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
+ 
+       /*
+        * Prevent the signaler thread from updating the request
          * state (by calling dma_fence_signal) as we are processing
          * the reset. The write from the GPU of the seqno is
          * asynchronous and the signaler thread may see a different
@@@ -2811,7 -2909,8 +2911,8 @@@
          */
         kthread_park(engine->breadcrumbs.signaler);
   
-       /* Prevent request submission to the hardware until we have
+       /*
+        * Prevent request submission to the hardware until we have
          * completed the reset in i915_gem_reset_finish(). If a request
          * is completed by one engine, it may then queue a request
          * to a second via its engine->irq_tasklet *just* as we are
@@@ -2819,8 -2918,8 +2920,8 @@@
          * Turning off the engine->irq_tasklet until the reset is over
          * prevents the race.
          */
-       tasklet_kill(&engine->irq_tasklet);
-       tasklet_disable(&engine->irq_tasklet);
+       tasklet_kill(&engine->execlists.irq_tasklet);
+       tasklet_disable(&engine->execlists.irq_tasklet);
   
         if (engine->irq_seqno_barrier)
                 engine->irq_seqno_barrier(engine);
@@@ -2999,8 -3098,10 +3100,10 @@@ void i915_gem_reset(struct drm_i915_pri
   
   void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
   {
-       tasklet_enable(&engine->irq_tasklet);
+       tasklet_enable(&engine->execlists.irq_tasklet);
         kthread_unpark(engine->breadcrumbs.signaler);
+ 
+       intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
   }
   
   void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
@@@ -3017,10 -3118,16 +3120,16 @@@
   }
   
   static void nop_submit_request(struct drm_i915_gem_request *request)
+ {
+       dma_fence_set_error(&request->fence, -EIO);
+ 
+       i915_gem_request_submit(request);
+ }
+ 
+ static void nop_complete_submit_request(struct drm_i915_gem_request *request)
   {
         unsigned long flags;
   
-       GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error));
         dma_fence_set_error(&request->fence, -EIO);
   
         spin_lock_irqsave(&request->engine->timeline->lock, flags);
@@@ -3029,81 -3136,59 +3138,59 @@@
         spin_unlock_irqrestore(&request->engine->timeline->lock, flags);
   }
   
- static void engine_set_wedged(struct intel_engine_cs *engine)
+ void i915_gem_set_wedged(struct drm_i915_private *i915)
   {
-       struct drm_i915_gem_request *request;
-       unsigned long flags;
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
   
-       /* We need to be sure that no thread is running the old callback as
-        * we install the nop handler (otherwise we would submit a request
-        * to hardware that will never complete). In order to prevent this
-        * race, we wait until the machine is idle before making the swap
-        * (using stop_machine()).
+       /*
+        * First, stop submission to hw, but do not yet complete requests by
+        * rolling the global seqno forward (since this would complete requests
+        * for which we haven't set the fence error to EIO yet).
          */
-       engine->submit_request = nop_submit_request;
- 
-       /* Mark all executing requests as skipped */
-       spin_lock_irqsave(&engine->timeline->lock, flags);
-       list_for_each_entry(request, &engine->timeline->requests, link)
-               if (!i915_gem_request_completed(request))
-                       dma_fence_set_error(&request->fence, -EIO);
-       spin_unlock_irqrestore(&engine->timeline->lock, flags);
+       for_each_engine(engine, i915, id)
+               engine->submit_request = nop_submit_request;
   
         /*
-        * Clear the execlists queue up before freeing the requests, as those
-        * are the ones that keep the context and ringbuffer backing objects
-        * pinned in place.
+        * Make sure no one is running the old callback before we proceed with
+        * cancelling requests and resetting the completion tracking. Otherwise
+        * we might submit a request to the hardware which never completes.
          */
+       synchronize_rcu();
   
-       if (i915.enable_execlists) {
-               struct execlist_port *port = engine->execlist_port;
-               unsigned long flags;
-               unsigned int n;
- 
-               spin_lock_irqsave(&engine->timeline->lock, flags);
- 
-               for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
-                       i915_gem_request_put(port_request(&port[n]));
-               memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
-               engine->execlist_queue = RB_ROOT;
-               engine->execlist_first = NULL;
- 
-               spin_unlock_irqrestore(&engine->timeline->lock, flags);
+       for_each_engine(engine, i915, id) {
+               /* Mark all executing requests as skipped */
+               engine->cancel_requests(engine);
   
-               /* The port is checked prior to scheduling a tasklet, but
-                * just in case we have suspended the tasklet to do the
-                * wedging make sure that when it wakes, it decides there
-                * is no work to do by clearing the irq_posted bit.
+               /*
+                * Only once we've force-cancelled all in-flight requests can we
+                * start to complete all requests.
                  */
-               clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+               engine->submit_request = nop_complete_submit_request;
         }
   
-       /* Mark all pending requests as complete so that any concurrent
-        * (lockless) lookup doesn't try and wait upon the request as we
-        * reset it.
+       /*
+        * Make sure no request can slip through without getting completed by
+        * either this call here to intel_engine_init_global_seqno, or the one
+        * in nop_complete_submit_request.
          */
-       intel_engine_init_global_seqno(engine,
-                                      intel_engine_last_submit(engine));
- }
+       synchronize_rcu();
   
- static int __i915_gem_set_wedged_BKL(void *data)
- {
-       struct drm_i915_private *i915 = data;
-       struct intel_engine_cs *engine;
-       enum intel_engine_id id;
+       for_each_engine(engine, i915, id) {
+               unsigned long flags;
   
-       for_each_engine(engine, i915, id)
-               engine_set_wedged(engine);
+               /* Mark all pending requests as complete so that any concurrent
+                * (lockless) lookup doesn't try and wait upon the request as we
+                * reset it.
+                */
+               spin_lock_irqsave(&engine->timeline->lock, flags);
+               intel_engine_init_global_seqno(engine,
+                                              intel_engine_last_submit(engine));
+               spin_unlock_irqrestore(&engine->timeline->lock, flags);
+       }
   
         set_bit(I915_WEDGED, &i915->gpu_error.flags);
         wake_up_all(&i915->gpu_error.reset_queue);
- 
-       return 0;
- }
- 
- void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
- {
-       stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
   }
   
   bool i915_gem_unset_wedged(struct drm_i915_private *i915)
@@@ -3267,11 -3352,11 +3354,11 @@@ void i915_gem_close_object(struct drm_g
                 struct i915_gem_context *ctx = lut->ctx;
                 struct i915_vma *vma;
   
+               GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF));
                 if (ctx->file_priv != fpriv)
                         continue;
   
                 vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
- 
                 GEM_BUG_ON(vma->obj != obj);
   
                 /* We allow the process to have multiple handles to the same
@@@ -3385,24 -3470,12 +3472,12 @@@ static int wait_for_timeline(struct i91
         return 0;
   }
   
- static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
- {
-       return wait_for(intel_engine_is_idle(engine), timeout_ms);
- }
- 
   static int wait_for_engines(struct drm_i915_private *i915)
   {
-       struct intel_engine_cs *engine;
-       enum intel_engine_id id;
- 
-       for_each_engine(engine, i915, id) {
-               if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
-                       i915_gem_set_wedged(i915);
-                       return -EIO;
-               }
- 
-               GEM_BUG_ON(intel_engine_get_seqno(engine) !=
-                          intel_engine_last_submit(engine));
+       if (wait_for(intel_engines_are_idle(i915), 50)) {
+               DRM_ERROR("Failed to idle engines, declaring wedged!\n");
+               i915_gem_set_wedged(i915);
+               return -EIO;
         }
   
         return 0;
@@@ -3452,7 -3525,7 +3527,7 @@@ static void __i915_gem_object_flush_for
   
   void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
   {
-       if (!READ_ONCE(obj->pin_display))
+       if (!READ_ONCE(obj->pin_global))
                 return;
   
         mutex_lock(&obj->base.dev->struct_mutex);
@@@ -3819,10 -3892,10 +3894,10 @@@ i915_gem_object_pin_to_display_plane(st
   
         lockdep_assert_held(&obj->base.dev->struct_mutex);
   
-       /* Mark the pin_display early so that we account for the
+       /* Mark the global pin early so that we account for the
          * display coherency whilst setting up the cache domains.
          */
-       obj->pin_display++;
+       obj->pin_global++;
   
         /* The display engine is not coherent with the LLC cache on gen6.  As
          * a result, we make sure that the pinning that is about to occur is
@@@ -3838,7 -3911,7 +3913,7 @@@
                                               I915_CACHE_WT : I915_CACHE_NONE);
         if (ret) {
                 vma = ERR_PTR(ret);
-               goto err_unpin_display;
+               goto err_unpin_global;
         }
   
         /* As the user may map the buffer once pinned in the display plane
@@@ -3869,7 -3942,7 +3944,7 @@@
                 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
         }
         if (IS_ERR(vma))
-               goto err_unpin_display;
+               goto err_unpin_global;
   
         vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
   
@@@ -3884,8 -3957,8 +3959,8 @@@
   
         return vma;
   
- err_unpin_display:
-       obj->pin_display--;
+ err_unpin_global:
+       obj->pin_global--;
         return vma;
   }
   
@@@ -3894,10 -3967,10 +3969,10 @@@ i915_gem_object_unpin_from_display_plan
   {
         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
   
-       if (WARN_ON(vma->obj->pin_display == 0))
+       if (WARN_ON(vma->obj->pin_global == 0))
                 return;
   
-       if (--vma->obj->pin_display == 0)
+       if (--vma->obj->pin_global == 0)
                 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
   
         /* Bump the LRU to try and avoid premature eviction whilst flipping  */
@@@ -4016,42 -4089,47 +4091,47 @@@ i915_gem_object_ggtt_pin(struct drm_i91
   
         lockdep_assert_held(&obj->base.dev->struct_mutex);
   
+       if (!view && flags & PIN_MAPPABLE) {
+               /* If the required space is larger than the available
+                * aperture, we will not able to find a slot for the
+                * object and unbinding the object now will be in
+                * vain. Worse, doing so may cause us to ping-pong
+                * the object in and out of the Global GTT and
+                * waste a lot of cycles under the mutex.
+                */
+               if (obj->base.size > dev_priv->ggtt.mappable_end)
+                       return ERR_PTR(-E2BIG);
+ 
+               /* If NONBLOCK is set the caller is optimistically
+                * trying to cache the full object within the mappable
+                * aperture, and *must* have a fallback in place for
+                * situations where we cannot bind the object. We
+                * can be a little more lax here and use the fallback
+                * more often to avoid costly migrations of ourselves
+                * and other objects within the aperture.
+                *
+                * Half-the-aperture is used as a simple heuristic.
+                * More interesting would to do search for a free
+                * block prior to making the commitment to unbind.
+                * That caters for the self-harm case, and with a
+                * little more heuristics (e.g. NOFAULT, NOEVICT)
+                * we could try to minimise harm to others.
+                */
+               if (flags & PIN_NONBLOCK &&
+                   obj->base.size > dev_priv->ggtt.mappable_end / 2)
+                       return ERR_PTR(-ENOSPC);
+       }
+ 
         vma = i915_vma_instance(obj, vm, view);
         if (unlikely(IS_ERR(vma)))
                 return vma;
   
         if (i915_vma_misplaced(vma, size, alignment, flags)) {
-               if (flags & PIN_NONBLOCK &&
-                   (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
-                       return ERR_PTR(-ENOSPC);
+               if (flags & PIN_NONBLOCK) {
+                       if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
+                               return ERR_PTR(-ENOSPC);
   
-               if (flags & PIN_MAPPABLE) {
-                       /* If the required space is larger than the available
-                        * aperture, we will not able to find a slot for the
-                        * object and unbinding the object now will be in
-                        * vain. Worse, doing so may cause us to ping-pong
-                        * the object in and out of the Global GTT and
-                        * waste a lot of cycles under the mutex.
-                        */
-                       if (vma->fence_size > dev_priv->ggtt.mappable_end)
-                               return ERR_PTR(-E2BIG);
- 
-                       /* If NONBLOCK is set the caller is optimistically
-                        * trying to cache the full object within the mappable
-                        * aperture, and *must* have a fallback in place for
-                        * situations where we cannot bind the object. We
-                        * can be a little more lax here and use the fallback
-                        * more often to avoid costly migrations of ourselves
-                        * and other objects within the aperture.
-                        *
-                        * Half-the-aperture is used as a simple heuristic.
-                        * More interesting would to do search for a free
-                        * block prior to making the commitment to unbind.
-                        * That caters for the self-harm case, and with a
-                        * little more heuristics (e.g. NOFAULT, NOEVICT)
-                        * we could try to minimise harm to others.
-                        */
-                       if (flags & PIN_NONBLOCK &&
+                       if (flags & PIN_MAPPABLE &&
                             vma->fence_size > dev_priv->ggtt.mappable_end / 2)
                                 return ERR_PTR(-ENOSPC);
                 }
@@@ -4232,7 -4310,7 +4312,7 @@@ i915_gem_madvise_ioctl(struct drm_devic
         if (err)
                 goto out;
   
-       if (obj->mm.pages &&
+       if (i915_gem_object_has_pages(obj) &&
             i915_gem_object_is_tiled(obj) &&
             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
                 if (obj->mm.madv == I915_MADV_WILLNEED) {
@@@ -4251,7 -4329,8 +4331,8 @@@
                 obj->mm.madv = args->madv;
   
         /* if the object is no longer attached, discard its backing storage */
-       if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
+       if (obj->mm.madv == I915_MADV_DONTNEED &&
+           !i915_gem_object_has_pages(obj))
                 i915_gem_object_truncate(obj);
   
         args->retained = obj->mm.madv != __I915_MADV_PURGED;
@@@ -4277,8 -4356,6 +4358,6 @@@ void i915_gem_object_init(struct drm_i9
   {
         mutex_init(&obj->mm.lock);
   
-       INIT_LIST_HEAD(&obj->global_link);
-       INIT_LIST_HEAD(&obj->userfault_link);
         INIT_LIST_HEAD(&obj->vma_list);
         INIT_LIST_HEAD(&obj->lut_list);
         INIT_LIST_HEAD(&obj->batch_pool_link);
@@@ -4308,6 -4385,30 +4387,30 @@@ static const struct drm_i915_gem_object
         .pwrite = i915_gem_object_pwrite_gtt,
   };
   
+ static int i915_gem_object_create_shmem(struct drm_device *dev,
+                                       struct drm_gem_object *obj,
+                                       size_t size)
+ {
+       struct drm_i915_private *i915 = to_i915(dev);
+       unsigned long flags = VM_NORESERVE;
+       struct file *filp;
+ 
+       drm_gem_private_object_init(dev, obj, size);
+ 
+       if (i915->mm.gemfs)
+               filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
+                                                flags);
+       else
+               filp = shmem_file_setup("i915", size, flags);
+ 
+       if (IS_ERR(filp))
+               return PTR_ERR(filp);
+ 
+       obj->filp = filp;
+ 
+       return 0;
+ }
+ 
   struct drm_i915_gem_object *
   i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
   {
@@@ -4332,7 -4433,7 +4435,7 @@@
         if (obj == NULL)
                 return ERR_PTR(-ENOMEM);
   
-       ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
+       ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size);
         if (ret)
                 goto fail;
   
@@@ -4409,13 -4510,14 +4512,14 @@@ static void __i915_gem_free_objects(str
   {
         struct drm_i915_gem_object *obj, *on;
   
-       mutex_lock(&i915->drm.struct_mutex);
         intel_runtime_pm_get(i915);
-       llist_for_each_entry(obj, freed, freed) {
+       llist_for_each_entry_safe(obj, on, freed, freed) {
                 struct i915_vma *vma, *vn;
   
                 trace_i915_gem_object_destroy(obj);
   
+               mutex_lock(&i915->drm.struct_mutex);
+ 
                 GEM_BUG_ON(i915_gem_object_is_active(obj));
                 list_for_each_entry_safe(vma, vn,
                                          &obj->vma_list, obj_link) {
@@@ -4426,16 -4528,24 +4530,24 @@@
                 GEM_BUG_ON(!list_empty(&obj->vma_list));
                 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
   
-               list_del(&obj->global_link);
-       }
-       intel_runtime_pm_put(i915);
-       mutex_unlock(&i915->drm.struct_mutex);
+               /* This serializes freeing with the shrinker. Since the free
+                * is delayed, first by RCU then by the workqueue, we want the
+                * shrinker to be able to free pages of unreferenced objects,
+                * or else we may oom whilst there are plenty of deferred
+                * freed objects.
+                */
+               if (i915_gem_object_has_pages(obj)) {
+                       spin_lock(&i915->mm.obj_lock);
+                       list_del_init(&obj->mm.link);
+                       spin_unlock(&i915->mm.obj_lock);
+               }
   
-       cond_resched();
+               mutex_unlock(&i915->drm.struct_mutex);
   
-       llist_for_each_entry_safe(obj, on, freed, freed) {
                 GEM_BUG_ON(obj->bind_count);
+               GEM_BUG_ON(obj->userfault_count);
                 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
+               GEM_BUG_ON(!list_empty(&obj->lut_list));
   
                 if (obj->ops->release)
                         obj->ops->release(obj);
@@@ -4443,7 -4553,7 +4555,7 @@@
                 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
                         atomic_set(&obj->mm.pages_pin_count, 0);
                 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
-               GEM_BUG_ON(obj->mm.pages);
+               GEM_BUG_ON(i915_gem_object_has_pages(obj));
   
                 if (obj->base.import_attach)
                         drm_prime_gem_destroy(&obj->base, NULL);
@@@ -4454,16 -4564,29 +4566,29 @@@
   
                 kfree(obj->bit_17);
                 i915_gem_object_free(obj);
+ 
+               if (on)
+                       cond_resched();
         }
+       intel_runtime_pm_put(i915);
   }
   
   static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
   {
         struct llist_node *freed;
   
-       freed = llist_del_all(&i915->mm.free_list);
-       if (unlikely(freed))
+       /* Free the oldest, most stale object to keep the free_list short */
+       freed = NULL;
+       if (!llist_empty(&i915->mm.free_list)) { /* quick test for hotpath */
+               /* Only one consumer of llist_del_first() allowed */
+               spin_lock(&i915->mm.free_lock);
+               freed = llist_del_first(&i915->mm.free_list);
+               spin_unlock(&i915->mm.free_lock);
+       }
+       if (unlikely(freed)) {
+               freed->next = NULL;
                 __i915_gem_free_objects(i915, freed);
+       }
   }
   
   static void __i915_gem_free_work(struct work_struct *work)
@@@ -4480,11 -4603,17 +4605,17 @@@
          * unbound now.
          */
   
+       spin_lock(&i915->mm.free_lock);
         while ((freed = llist_del_all(&i915->mm.free_list))) {
+               spin_unlock(&i915->mm.free_lock);
+ 
                 __i915_gem_free_objects(i915, freed);
                 if (need_resched())
-                       break;
+                       return;
+ 
+               spin_lock(&i915->mm.free_lock);
         }
+       spin_unlock(&i915->mm.free_lock);
   }
   
   static void __i915_gem_free_object_rcu(struct rcu_head *head)
@@@ -4543,6 -4672,12 +4674,12 @@@ static void assert_kernel_context_is_cu
   
   void i915_gem_sanitize(struct drm_i915_private *i915)
   {
+       if (i915_terminally_wedged(&i915->gpu_error)) {
+               mutex_lock(&i915->drm.struct_mutex);
+               i915_gem_unset_wedged(i915);
+               mutex_unlock(&i915->drm.struct_mutex);
+       }
+ 
         /*
          * If we inherit context state from the BIOS or earlier occupants
          * of the GPU, the GPU may be in an inconsistent state when we
@@@ -4582,7 -4717,7 +4719,7 @@@ int i915_gem_suspend(struct drm_i915_pr
         ret = i915_gem_wait_for_idle(dev_priv,
                                      I915_WAIT_INTERRUPTIBLE |
                                      I915_WAIT_LOCKED);
-       if (ret)
+       if (ret && ret != -EIO)
                 goto err_unlock;
   
         assert_kernel_context_is_current(dev_priv);
@@@ -4597,14 -4732,14 +4734,14 @@@
         /* As the idle_work is rearming if it detects a race, play safe and
          * repeat the flush until it is definitely idle.
          */
-       while (flush_delayed_work(&dev_priv->gt.idle_work))
-               ;
+       drain_delayed_work(&dev_priv->gt.idle_work);
   
         /* Assert that we sucessfully flushed all the work and
          * reset the GPU back to its idle, low power state.
          */
         WARN_ON(dev_priv->gt.awake);
-       WARN_ON(!intel_engines_are_idle(dev_priv));
+       if (WARN_ON(!intel_engines_are_idle(dev_priv)))
+               i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
   
         /*
          * Neither the BIOS, ourselves or any other kernel
@@@ -4626,11 -4761,12 +4763,12 @@@
          * machine in an unusable condition.
          */
         i915_gem_sanitize(dev_priv);
-       goto out_rpm_put;
+ 
+       intel_runtime_pm_put(dev_priv);
+       return 0;
   
   err_unlock:
         mutex_unlock(&dev->struct_mutex);
- out_rpm_put:
         intel_runtime_pm_put(dev_priv);
         return ret;
   }
@@@ -4643,6 -4779,7 +4781,7 @@@ void i915_gem_resume(struct drm_i915_pr
   
         mutex_lock(&dev->struct_mutex);
         i915_gem_restore_gtt_mappings(dev_priv);
+       i915_gem_restore_fences(dev_priv);
   
         /* As we didn't flush the kernel context before suspend, we cannot
          * guarantee that the context image is complete. So let's just reset
@@@ -4756,6 -4893,10 +4895,10 @@@ int i915_gem_init_hw(struct drm_i915_pr
         init_unused_rings(dev_priv);
   
         BUG_ON(!dev_priv->kernel_context);
+       if (i915_terminally_wedged(&dev_priv->gpu_error)) {
+               ret = -EIO;
+               goto out;
+       }
   
         ret = i915_ppgtt_init_hw(dev_priv);
         if (ret) {
@@@ -4786,7 -4927,7 +4929,7 @@@ bool intel_sanitize_semaphores(struct d
                 return false;
   
         /* TODO: make semaphores and Execlists play nicely together */
-       if (i915.enable_execlists)
+       if (i915_modparams.enable_execlists)
                 return false;
   
         if (value >= 0)
@@@ -4805,9 -4946,18 +4948,18 @@@ int i915_gem_init(struct drm_i915_priva
   
         mutex_lock(&dev_priv->drm.struct_mutex);
   
+       /*
+        * We need to fallback to 4K pages since gvt gtt handling doesn't
+        * support huge page entries - we will need to check either hypervisor
+        * mm can support huge guest page or just do emulation in gvt.
+        */
+       if (intel_vgpu_active(dev_priv))
+               mkwrite_device_info(dev_priv)->page_sizes =
+                       I915_GTT_PAGE_SIZE_4K;
+ 
         dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
   
-       if (!i915.enable_execlists) {
+       if (!i915_modparams.enable_execlists) {
                 dev_priv->gt.resume = intel_legacy_submission_resume;
                 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
         } else {
@@@ -4845,8 -4995,10 +4997,10 @@@
                  * wedged. But we only want to do this where the GPU is angry,
                  * for all other failure, such as an allocation failure, bail.
                  */
-               DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
-               i915_gem_set_wedged(dev_priv);
+               if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
+                       DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
+                       i915_gem_set_wedged(dev_priv);
+               }
                 ret = 0;
         }
   
@@@ -4946,11 -5098,15 +5100,15 @@@ i915_gem_load_init(struct drm_i915_priv
                 goto err_priorities;
   
         INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
+ 
+       spin_lock_init(&dev_priv->mm.obj_lock);
+       spin_lock_init(&dev_priv->mm.free_lock);
         init_llist_head(&dev_priv->mm.free_list);
         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
         INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
+ 
         INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
                           i915_gem_retire_work_handler);
         INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
@@@ -4962,6 -5118,10 +5120,10 @@@
   
         spin_lock_init(&dev_priv->fb_tracking.lock);
   
+       err = i915_gemfs_init(dev_priv);
+       if (err)
+               DRM_NOTE("Unable to create a private tmpfs mount, hugepage support will be disabled(%d).\n", err);
+ 
         return 0;
   
   err_priorities:
@@@ -5000,6 -5160,8 +5162,8 @@@ void i915_gem_load_cleanup(struct drm_i
   
         /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
         rcu_barrier();
+ 
+       i915_gemfs_fini(dev_priv);
   }
   
   int i915_gem_freeze(struct drm_i915_private *dev_priv)
@@@ -5038,12 -5200,12 +5202,12 @@@ int i915_gem_freeze_late(struct drm_i91
         i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_UNBOUND);
         i915_gem_drain_freed_objects(dev_priv);
   
-       mutex_lock(&dev_priv->drm.struct_mutex);
+       spin_lock(&dev_priv->mm.obj_lock);
         for (p = phases; *p; p++) {
-               list_for_each_entry(obj, *p, global_link)
+               list_for_each_entry(obj, *p, mm.link)
                         __start_cpu_write(obj);
         }
-       mutex_unlock(&dev_priv->drm.struct_mutex);
+       spin_unlock(&dev_priv->mm.obj_lock);
   
         return 0;
   }
@@@ -5362,7 -5524,17 +5526,17 @@@ int i915_gem_object_attach_phys(struct 
                 goto err_unlock;
         }
   
-       pages = obj->mm.pages;
+       pages = fetch_and_zero(&obj->mm.pages);
+       if (pages) {
+               struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ 
+               __i915_gem_object_reset_page_iter(obj);
+ 
+               spin_lock(&i915->mm.obj_lock);
+               list_del(&obj->mm.link);
+               spin_unlock(&i915->mm.obj_lock);
+       }
+ 
         obj->ops = &i915_gem_phys_ops;
   
         err = ____i915_gem_object_get_pages(obj);
@@@ -5389,6 -5561,7 +5563,7 @@@ err_unlock
   #include "selftests/scatterlist.c"
   #include "selftests/mock_gem_device.c"
   #include "selftests/huge_gem_object.c"
+ #include "selftests/huge_pages.c"
   #include "selftests/i915_gem_object.c"
   #include "selftests/i915_gem_coherency.c"
   #endif
diff --combined drivers/gpu/drm/i915/i915_gem_context.c

index 8afd2ce59b8d5050161bdd13611fcec4602a5321,e304dcbc6042d9e846efda1139f145b338056ac8..f782cf2069c16fc70acec32f49aea8081e0bf694
--- 1/drivers/gpu/drm/i915/i915_gem_context.c
--- 2/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@@ -104,19 -104,12 +104,14 @@@ static void lut_close(struct i915_gem_c
                 kmem_cache_free(ctx->i915->luts, lut);
         }
   
+ +      rcu_read_lock();
         radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
                 struct i915_vma *vma = rcu_dereference_raw(*slot);
-               struct drm_i915_gem_object *obj = vma->obj;
   
                 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
- 
-               if (!i915_vma_is_ggtt(vma))
-                       i915_vma_close(vma);
- 
-               __i915_gem_object_release_unless_active(obj);
+               __i915_gem_object_release_unless_active(vma->obj);
         }
+ +      rcu_read_unlock();
   }
   
   static void i915_gem_context_free(struct i915_gem_context *ctx)
@@@ -200,6 -193,11 +195,11 @@@ static void context_close(struct i915_g
   {
         i915_gem_context_set_closed(ctx);
   
+       /*
+        * The LUT uses the VMA as a backpointer to unref the object,
+        * so we need to clear the LUT before we close all the VMA (inside
+        * the ppgtt).
+        */
         lut_close(ctx);
         if (ctx->ppgtt)
                 i915_ppgtt_close(&ctx->ppgtt->base);
@@@ -316,7 -314,7 +316,7 @@@ __create_hw_context(struct drm_i915_pri
          * present or not in use we still need a small bias as ring wraparound
          * at offset 0 sometimes hangs. No idea why.
          */
-       if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
+       if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
                 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
         else
                 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
@@@ -409,7 -407,7 +409,7 @@@ i915_gem_context_create_gvt(struct drm_
         i915_gem_context_set_closed(ctx); /* not user accessible */
         i915_gem_context_clear_bannable(ctx);
         i915_gem_context_set_force_single_submission(ctx);
-       if (!i915.enable_guc_submission)
+       if (!i915_modparams.enable_guc_submission)
                 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
   
         GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
@@@ -418,14 -416,43 +418,43 @@@ out
         return ctx;
   }
   
+ static struct i915_gem_context *
+ create_kernel_context(struct drm_i915_private *i915, int prio)
+ {
+       struct i915_gem_context *ctx;
+ 
+       ctx = i915_gem_create_context(i915, NULL);
+       if (IS_ERR(ctx))
+               return ctx;
+ 
+       i915_gem_context_clear_bannable(ctx);
+       ctx->priority = prio;
+       ctx->ring_size = PAGE_SIZE;
+ 
+       GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+ 
+       return ctx;
+ }
+ 
+ static void
+ destroy_kernel_context(struct i915_gem_context **ctxp)
+ {
+       struct i915_gem_context *ctx;
+ 
+       /* Keep the context ref so that we can free it immediately ourselves */
+       ctx = i915_gem_context_get(fetch_and_zero(ctxp));
+       GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+ 
+       context_close(ctx);
+       i915_gem_context_free(ctx);
+ }
+ 
   int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
   {
         struct i915_gem_context *ctx;
+       int err;
   
-       /* Init should only be called once per module load. Eventually the
-        * restriction on the context_disabled check can be loosened. */
-       if (WARN_ON(dev_priv->kernel_context))
-               return 0;
+       GEM_BUG_ON(dev_priv->kernel_context);
   
         INIT_LIST_HEAD(&dev_priv->contexts.list);
         INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
@@@ -433,7 -460,7 +462,7 @@@
   
         if (intel_vgpu_active(dev_priv) &&
             HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
-               if (!i915.enable_execlists) {
+               if (!i915_modparams.enable_execlists) {
                         DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
                         return -EINVAL;
                 }
@@@ -443,28 -470,38 +472,38 @@@
         BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
         ida_init(&dev_priv->contexts.hw_ida);
   
-       ctx = i915_gem_create_context(dev_priv, NULL);
+       /* lowest priority; idle task */
+       ctx = create_kernel_context(dev_priv, I915_PRIORITY_MIN);
         if (IS_ERR(ctx)) {
-               DRM_ERROR("Failed to create default global context (error %ld)\n",
-                         PTR_ERR(ctx));
-               return PTR_ERR(ctx);
+               DRM_ERROR("Failed to create default global context\n");
+               err = PTR_ERR(ctx);
+               goto err;
         }
- 
-       /* For easy recognisablity, we want the kernel context to be 0 and then
+       /*
+        * For easy recognisablity, we want the kernel context to be 0 and then
          * all user contexts will have non-zero hw_id.
          */
         GEM_BUG_ON(ctx->hw_id);
- 
-       i915_gem_context_clear_bannable(ctx);
-       ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
         dev_priv->kernel_context = ctx;
   
-       GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+       /* highest priority; preempting task */
+       ctx = create_kernel_context(dev_priv, INT_MAX);
+       if (IS_ERR(ctx)) {
+               DRM_ERROR("Failed to create default preempt context\n");
+               err = PTR_ERR(ctx);
+               goto err_kernel_context;
+       }
+       dev_priv->preempt_context = ctx;
   
         DRM_DEBUG_DRIVER("%s context support initialized\n",
                          dev_priv->engine[RCS]->context_size ? "logical" :
                          "fake");
         return 0;
+ 
+ err_kernel_context:
+       destroy_kernel_context(&dev_priv->kernel_context);
+ err:
+       return err;
   }
   
   void i915_gem_contexts_lost(struct drm_i915_private *dev_priv)
@@@ -485,7 -522,7 +524,7 @@@
         }
   
         /* Force the GPU state to be restored on enabling */
-       if (!i915.enable_execlists) {
+       if (!i915_modparams.enable_execlists) {
                 struct i915_gem_context *ctx;
   
                 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
@@@ -509,15 -546,10 +548,10 @@@
   
   void i915_gem_contexts_fini(struct drm_i915_private *i915)
   {
-       struct i915_gem_context *ctx;
- 
         lockdep_assert_held(&i915->drm.struct_mutex);
   
-       /* Keep the context so that we can free it immediately ourselves */
-       ctx = i915_gem_context_get(fetch_and_zero(&i915->kernel_context));
-       GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
-       context_close(ctx);
-       i915_gem_context_free(ctx);
+       destroy_kernel_context(&i915->preempt_context);
+       destroy_kernel_context(&i915->kernel_context);
   
         /* Must free all deferred contexts (via flush_workqueue) first */
         ida_destroy(&i915->contexts.hw_ida);
@@@ -570,7 -602,7 +604,7 @@@ mi_set_context(struct drm_i915_gem_requ
         enum intel_engine_id id;
         const int num_rings =
                 /* Use an extended w/a on gen7 if signalling from other rings */
-               (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
+               (i915_modparams.semaphores && INTEL_GEN(dev_priv) == 7) ?
                 INTEL_INFO(dev_priv)->num_rings - 1 :
                 0;
         int len;
@@@ -839,7 -871,7 +873,7 @@@ int i915_switch_context(struct drm_i915
         struct intel_engine_cs *engine = req->engine;
   
         lockdep_assert_held(&req->i915->drm.struct_mutex);
-       if (i915.enable_execlists)
+       if (i915_modparams.enable_execlists)
                 return 0;
   
         if (!req->ctx->engine[engine->id].state) {
@@@ -1038,6 -1070,9 +1072,9 @@@ int i915_gem_context_getparam_ioctl(str
         case I915_CONTEXT_PARAM_BANNABLE:
                 args->value = i915_gem_context_is_bannable(ctx);
                 break;
+       case I915_CONTEXT_PARAM_PRIORITY:
+               args->value = ctx->priority;
+               break;
         default:
                 ret = -EINVAL;
                 break;
@@@ -1093,6 -1128,26 +1130,26 @@@ int i915_gem_context_setparam_ioctl(str
                 else
                         i915_gem_context_clear_bannable(ctx);
                 break;
+ 
+       case I915_CONTEXT_PARAM_PRIORITY:
+               {
+                       int priority = args->value;
+ 
+                       if (args->size)
+                               ret = -EINVAL;
+                       else if (!to_i915(dev)->engine[RCS]->schedule)
+                               ret = -ENODEV;
+                       else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
+                                priority < I915_CONTEXT_MIN_USER_PRIORITY)
+                               ret = -EINVAL;
+                       else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
+                                !capable(CAP_SYS_NICE))
+                               ret = -EPERM;
+                       else
+                               ctx->priority = priority;
+               }
+               break;
+ 
         default:
                 ret = -EINVAL;
                 break;
diff --combined drivers/gpu/drm/i915/i915_gem_execbuffer.c

index 83876a1c8d98b86037d50f6f007af7fa722c2652,3d7190764f1012ed97265c34d79c14554d8c4252..435ed95df144c1bc54d438c892a4a63c8a1b3cba
--- 1/drivers/gpu/drm/i915/i915_gem_execbuffer.c
--- 2/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@@ -58,6 -58,7 +58,7 @@@ enum 
   
   #define __EXEC_HAS_RELOC      BIT(31)
   #define __EXEC_VALIDATED      BIT(30)
+ #define __EXEC_INTERNAL_FLAGS (~0u << 30)
   #define UPDATE                        PIN_OFFSET_FIXED
   
   #define BATCH_OFFSET_BIAS (256*1024)
@@@ -268,6 -269,11 +269,11 @@@ static inline u64 gen8_noncanonical_add
         return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
   }
   
+ static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
+ {
+       return eb->engine->needs_cmd_parser && eb->batch_len;
+ }
+ 
   static int eb_create(struct i915_execbuffer *eb)
   {
         if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
@@@ -337,10 -343,6 +343,10 @@@ eb_vma_misplaced(const struct drm_i915_
             (vma->node.start + vma->node.size - 1) >> 32)
                 return true;
   
+ +      if (flags & __EXEC_OBJECT_NEEDS_MAP &&
+ +          !i915_vma_is_map_and_fenceable(vma))
+ +              return true;
+ +
         return false;
   }
   
@@@ -365,12 -367,12 +371,12 @@@ eb_pin_vma(struct i915_execbuffer *eb
                 return false;
   
         if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
-               if (unlikely(i915_vma_get_fence(vma))) {
+               if (unlikely(i915_vma_pin_fence(vma))) {
                         i915_vma_unpin(vma);
                         return false;
                 }
   
-               if (i915_vma_pin_fence(vma))
+               if (vma->fence)
                         exec_flags |= __EXEC_OBJECT_HAS_FENCE;
         }
   
@@@ -383,7 -385,7 +389,7 @@@ static inline void __eb_unreserve_vma(s
         GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
   
         if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
-               i915_vma_unpin_fence(vma);
+               __i915_vma_unpin_fence(vma);
   
         __i915_vma_unpin(vma);
   }
@@@ -561,13 -563,13 +567,13 @@@ static int eb_reserve_vma(const struct 
         }
   
         if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
-               err = i915_vma_get_fence(vma);
+               err = i915_vma_pin_fence(vma);
                 if (unlikely(err)) {
                         i915_vma_unpin(vma);
                         return err;
                 }
   
-               if (i915_vma_pin_fence(vma))
+               if (vma->fence)
                         exec_flags |= __EXEC_OBJECT_HAS_FENCE;
         }
   
@@@ -678,7 -680,7 +684,7 @@@ static int eb_select_context(struct i91
   static int eb_lookup_vmas(struct i915_execbuffer *eb)
   {
         struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
-       struct drm_i915_gem_object *uninitialized_var(obj);
+       struct drm_i915_gem_object *obj;
         unsigned int i;
         int err;
   
@@@ -724,19 -726,17 +730,17 @@@
                         goto err_obj;
                 }
   
+               /* transfer ref to ctx */
                 vma->open_count++;
                 list_add(&lut->obj_link, &obj->lut_list);
                 list_add(&lut->ctx_link, &eb->ctx->handles_list);
                 lut->ctx = eb->ctx;
                 lut->handle = handle;
   
-               /* transfer ref to ctx */
-               obj = NULL;
- 
   add_vma:
                 err = eb_add_vma(eb, i, vma);
                 if (unlikely(err))
-                       goto err_obj;
+                       goto err_vma;
   
                 GEM_BUG_ON(vma != eb->vma[i]);
                 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
@@@ -765,8 -765,7 +769,7 @@@
         return eb_reserve(eb);
   
   err_obj:
-       if (obj)
-               i915_gem_object_put(obj);
+       i915_gem_object_put(obj);
   err_vma:
         eb->vma[i] = NULL;
         return err;
@@@ -975,7 -974,9 +978,9 @@@ static void *reloc_iomap(struct drm_i91
                         return ERR_PTR(err);
   
                 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
-                                              PIN_MAPPABLE | PIN_NONBLOCK);
+                                              PIN_MAPPABLE |
+                                              PIN_NONBLOCK |
+                                              PIN_NONFAULT);
                 if (IS_ERR(vma)) {
                         memset(&cache->node, 0, sizeof(cache->node));
                         err = drm_mm_insert_node_in_range
@@@ -1163,6 -1164,13 +1168,13 @@@ static u32 *reloc_gpu(struct i915_execb
         if (unlikely(!cache->rq)) {
                 int err;
   
+               /* If we need to copy for the cmdparser, we will stall anyway */
+               if (eb_use_cmdparser(eb))
+                       return ERR_PTR(-EWOULDBLOCK);
+ 
+               if (!intel_engine_can_store_dword(eb->engine))
+                       return ERR_PTR(-ENODEV);
+ 
                 err = __reloc_gpu_alloc(eb, vma, len);
                 if (unlikely(err))
                         return ERR_PTR(err);
@@@ -1187,9 -1195,7 +1199,7 @@@ relocate_entry(struct i915_vma *vma
   
         if (!eb->reloc_cache.vaddr &&
             (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
-            !reservation_object_test_signaled_rcu(vma->resv, true)) &&
-           __intel_engine_can_store_dword(eb->reloc_cache.gen,
-                                          eb->engine->class)) {
+            !reservation_object_test_signaled_rcu(vma->resv, true))) {
                 const unsigned int gen = eb->reloc_cache.gen;
                 unsigned int len;
                 u32 *batch;
@@@ -1581,7 -1587,7 +1591,7 @@@ static int eb_prefault_relocations(cons
         const unsigned int count = eb->buffer_count;
         unsigned int i;
   
-       if (unlikely(i915.prefault_disable))
+       if (unlikely(i915_modparams.prefault_disable))
                 return 0;
   
         for (i = 0; i < count; i++) {
@@@ -2094,11 -2100,6 +2104,11 @@@ get_fence_array(struct drm_i915_gem_exe
                         goto err;
                 }
   
+ +              if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ +                      err = -EINVAL;
+ +                      goto err;
+ +              }
+ +
                 syncobj = drm_syncobj_find(file, fence.handle);
                 if (!syncobj) {
                         DRM_DEBUG("Invalid syncobj handle provided\n");
@@@ -2106,9 -2107,6 +2116,9 @@@
                         goto err;
                 }
   
+ +              BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
+ +                           ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
+ +
                 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
         }
   
@@@ -2190,6 -2188,7 +2200,7 @@@ i915_gem_do_execbuffer(struct drm_devic
         int out_fence_fd = -1;
         int err;
   
+       BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
         BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
                      ~__EXEC_OBJECT_UNKNOWN_FLAGS);
   
@@@ -2303,7 -2302,7 +2314,7 @@@
                 goto err_vma;
         }
   
-       if (eb.engine->needs_cmd_parser && eb.batch_len) {
+       if (eb_use_cmdparser(&eb)) {
                 struct i915_vma *vma;
   
                 vma = eb_parse(&eb, drm_is_current_master(file));
diff --combined drivers/gpu/drm/i915/i915_gem_gtt.c

index 7982ad817c116e031c1f4cd78d715785a5b59e5e,5eaa6893daaa1a193eda7235e5acf8e9adbda87c..2af65ecf2df84e8a26fe694f8e115d9e8e7d3671
--- 1/drivers/gpu/drm/i915/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -135,11 -135,12 +135,12 @@@ static inline void i915_ggtt_invalidate
   int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
                                 int enable_ppgtt)
   {
-       bool has_aliasing_ppgtt;
         bool has_full_ppgtt;
         bool has_full_48bit_ppgtt;
   
-       has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt;
+       if (!dev_priv->info.has_aliasing_ppgtt)
+               return 0;
+ 
         has_full_ppgtt = dev_priv->info.has_full_ppgtt;
         has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
   
@@@ -149,9 -150,6 +150,6 @@@
                 has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
         }
   
-       if (!has_aliasing_ppgtt)
-               return 0;
- 
         /*
          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
          * execlists, the sole mechanism available to submit work.
@@@ -180,7 -178,7 +178,7 @@@
                 return 0;
         }
   
-       if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
+       if (INTEL_GEN(dev_priv) >= 8 && i915_modparams.enable_execlists) {
                 if (has_full_48bit_ppgtt)
                         return 3;
   
@@@ -188,7 -186,7 +186,7 @@@
                         return 2;
         }
   
-       return has_aliasing_ppgtt ? 1 : 0;
+       return 1;
   }
   
   static int ppgtt_bind_vma(struct i915_vma *vma,
@@@ -205,8 -203,6 +203,6 @@@
                         return ret;
         }
   
-       vma->pages = vma->obj->mm.pages;
- 
         /* Currently applicable only to VLV */
         pte_flags = 0;
         if (vma->obj->gt_ro)
@@@ -222,6 -218,30 +218,30 @@@ static void ppgtt_unbind_vma(struct i91
         vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
   }
   
+ static int ppgtt_set_pages(struct i915_vma *vma)
+ {
+       GEM_BUG_ON(vma->pages);
+ 
+       vma->pages = vma->obj->mm.pages;
+ 
+       vma->page_sizes = vma->obj->mm.page_sizes;
+ 
+       return 0;
+ }
+ 
+ static void clear_pages(struct i915_vma *vma)
+ {
+       GEM_BUG_ON(!vma->pages);
+ 
+       if (vma->pages != vma->obj->mm.pages) {
+               sg_free_table(vma->pages);
+               kfree(vma->pages);
+       }
+       vma->pages = NULL;
+ 
+       memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
+ }
+ 
   static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
                                   enum i915_cache_level level)
   {
@@@ -230,13 -250,13 +250,13 @@@
   
         switch (level) {
         case I915_CACHE_NONE:
-               pte |= PPAT_UNCACHED_INDEX;
+               pte |= PPAT_UNCACHED;
                 break;
         case I915_CACHE_WT:
-               pte |= PPAT_DISPLAY_ELLC_INDEX;
+               pte |= PPAT_DISPLAY_ELLC;
                 break;
         default:
-               pte |= PPAT_CACHED_INDEX;
+               pte |= PPAT_CACHED;
                 break;
         }
   
@@@ -249,9 -269,9 +269,9 @@@ static gen8_pde_t gen8_pde_encode(cons
         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
         pde |= addr;
         if (level != I915_CACHE_NONE)
-               pde |= PPAT_CACHED_PDE_INDEX;
+               pde |= PPAT_CACHED_PDE;
         else
-               pde |= PPAT_UNCACHED_INDEX;
+               pde |= PPAT_UNCACHED;
         return pde;
   }
   
@@@ -356,39 -376,86 +376,86 @@@ static gen6_pte_t iris_pte_encode(dma_a
   
   static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
   {
-       struct page *page;
+       struct pagevec *pvec = &vm->free_pages;
   
         if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
                 i915_gem_shrink_all(vm->i915);
   
-       if (vm->free_pages.nr)
-               return vm->free_pages.pages[--vm->free_pages.nr];
+       if (likely(pvec->nr))
+               return pvec->pages[--pvec->nr];
+ 
+       if (!vm->pt_kmap_wc)
+               return alloc_page(gfp);
   
-       page = alloc_page(gfp);
-       if (!page)
+       /* A placeholder for a specific mutex to guard the WC stash */
+       lockdep_assert_held(&vm->i915->drm.struct_mutex);
+ 
+       /* Look in our global stash of WC pages... */
+       pvec = &vm->i915->mm.wc_stash;
+       if (likely(pvec->nr))
+               return pvec->pages[--pvec->nr];
+ 
+       /* Otherwise batch allocate pages to amoritize cost of set_pages_wc. */
+       do {
+               struct page *page;
+ 
+               page = alloc_page(gfp);
+               if (unlikely(!page))
+                       break;
+ 
+               pvec->pages[pvec->nr++] = page;
+       } while (pagevec_space(pvec));
+ 
+       if (unlikely(!pvec->nr))
                 return NULL;
   
-       if (vm->pt_kmap_wc)
-               set_pages_array_wc(&page, 1);
+       set_pages_array_wc(pvec->pages, pvec->nr);
   
-       return page;
+       return pvec->pages[--pvec->nr];
   }
   
- static void vm_free_pages_release(struct i915_address_space *vm)
+ static void vm_free_pages_release(struct i915_address_space *vm,
+                                 bool immediate)
   {
-       GEM_BUG_ON(!pagevec_count(&vm->free_pages));
+       struct pagevec *pvec = &vm->free_pages;
+ 
+       GEM_BUG_ON(!pagevec_count(pvec));
   
-       if (vm->pt_kmap_wc)
-               set_pages_array_wb(vm->free_pages.pages,
-                                  pagevec_count(&vm->free_pages));
+       if (vm->pt_kmap_wc) {
+               struct pagevec *stash = &vm->i915->mm.wc_stash;
   
-       __pagevec_release(&vm->free_pages);
+               /* When we use WC, first fill up the global stash and then
+                * only if full immediately free the overflow.
+                */
+ 
+               lockdep_assert_held(&vm->i915->drm.struct_mutex);
+               if (pagevec_space(stash)) {
+                       do {
+                               stash->pages[stash->nr++] =
+                                       pvec->pages[--pvec->nr];
+                               if (!pvec->nr)
+                                       return;
+                       } while (pagevec_space(stash));
+ 
+                       /* As we have made some room in the VM's free_pages,
+                        * we can wait for it to fill again. Unless we are
+                        * inside i915_address_space_fini() and must
+                        * immediately release the pages!
+                        */
+                       if (!immediate)
+                               return;
+               }
+ 
+               set_pages_array_wb(pvec->pages, pvec->nr);
+       }
+ 
+       __pagevec_release(pvec);
   }
   
   static void vm_free_page(struct i915_address_space *vm, struct page *page)
   {
         if (!pagevec_add(&vm->free_pages, page))
-               vm_free_pages_release(vm);
+               vm_free_pages_release(vm, false);
   }
   
   static int __setup_page_dma(struct i915_address_space *vm,
@@@ -434,10 -501,8 +501,8 @@@ static void fill_page_dma(struct i915_a
                           const u64 val)
   {
         u64 * const vaddr = kmap_atomic(p->page);
-       int i;
   
-       for (i = 0; i < 512; i++)
-               vaddr[i] = val;
+       memset64(vaddr, val, PAGE_SIZE / sizeof(val));
   
         kunmap_atomic(vaddr);
   }
@@@ -452,12 -517,73 +517,73 @@@ static void fill_page_dma_32(struct i91
   static int
   setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
   {
-       return __setup_page_dma(vm, &vm->scratch_page, gfp | __GFP_ZERO);
+       struct page *page = NULL;
+       dma_addr_t addr;
+       int order;
+ 
+       /*
+        * In order to utilize 64K pages for an object with a size < 2M, we will
+        * need to support a 64K scratch page, given that every 16th entry for a
+        * page-table operating in 64K mode must point to a properly aligned 64K
+        * region, including any PTEs which happen to point to scratch.
+        *
+        * This is only relevant for the 48b PPGTT where we support
+        * huge-gtt-pages, see also i915_vma_insert().
+        *
+        * TODO: we should really consider write-protecting the scratch-page and
+        * sharing between ppgtt
+        */
+       if (i915_vm_is_48bit(vm) &&
+           HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
+               order = get_order(I915_GTT_PAGE_SIZE_64K);
+               page = alloc_pages(gfp | __GFP_ZERO | __GFP_NOWARN, order);
+               if (page) {
+                       addr = dma_map_page(vm->dma, page, 0,
+                                           I915_GTT_PAGE_SIZE_64K,
+                                           PCI_DMA_BIDIRECTIONAL);
+                       if (unlikely(dma_mapping_error(vm->dma, addr))) {
+                               __free_pages(page, order);
+                               page = NULL;
+                       }
+ 
+                       if (!IS_ALIGNED(addr, I915_GTT_PAGE_SIZE_64K)) {
+                               dma_unmap_page(vm->dma, addr,
+                                              I915_GTT_PAGE_SIZE_64K,
+                                              PCI_DMA_BIDIRECTIONAL);
+                               __free_pages(page, order);
+                               page = NULL;
+                       }
+               }
+       }
+ 
+       if (!page) {
+               order = 0;
+               page = alloc_page(gfp | __GFP_ZERO);
+               if (unlikely(!page))
+                       return -ENOMEM;
+ 
+               addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE,
+                                   PCI_DMA_BIDIRECTIONAL);
+               if (unlikely(dma_mapping_error(vm->dma, addr))) {
+                       __free_page(page);
+                       return -ENOMEM;
+               }
+       }
+ 
+       vm->scratch_page.page = page;
+       vm->scratch_page.daddr = addr;
+       vm->scratch_page.order = order;
+ 
+       return 0;
   }
   
   static void cleanup_scratch_page(struct i915_address_space *vm)
   {
-       cleanup_page_dma(vm, &vm->scratch_page);
+       struct i915_page_dma *p = &vm->scratch_page;
+ 
+       dma_unmap_page(vm->dma, p->daddr, BIT(p->order) << PAGE_SHIFT,
+                      PCI_DMA_BIDIRECTIONAL);
+       __free_pages(p->page, p->order);
   }
   
   static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
@@@ -832,14 -958,10 +958,14 @@@ static void gen8_ppgtt_clear_4lvl(struc
         }
   }
   
- -struct sgt_dma {
+ +static inline struct sgt_dma {
         struct scatterlist *sg;
         dma_addr_t dma, max;
- -};
+ +} sgt_dma(struct i915_vma *vma) {
+ +      struct scatterlist *sg = vma->pages->sgl;
+ +      dma_addr_t addr = sg_dma_address(sg);
+ +      return (struct sgt_dma) { sg, addr, addr + sg->length };
+ +}
   
   struct gen8_insert_pte {
         u16 pml4e;
@@@ -920,11 -1042,114 +1046,110 @@@ static void gen8_ppgtt_insert_3lvl(stru
                                    u32 unused)
   {
         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- -      struct sgt_dma iter = {
- -              .sg = vma->pages->sgl,
- -              .dma = sg_dma_address(iter.sg),
- -              .max = iter.dma + iter.sg->length,
- -      };
+ +      struct sgt_dma iter = sgt_dma(vma);
         struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
   
         gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
                                       cache_level);
+ 
+       vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+ }
+ 
+ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
+                                          struct i915_page_directory_pointer **pdps,
+                                          struct sgt_dma *iter,
+                                          enum i915_cache_level cache_level)
+ {
+       const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
+       u64 start = vma->node.start;
+       dma_addr_t rem = iter->sg->length;
+ 
+       do {
+               struct gen8_insert_pte idx = gen8_insert_pte(start);
+               struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
+               struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
+               unsigned int page_size;
+               bool maybe_64K = false;
+               gen8_pte_t encode = pte_encode;
+               gen8_pte_t *vaddr;
+               u16 index, max;
+ 
+               if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
+                   IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
+                   rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
+                       index = idx.pde;
+                       max = I915_PDES;
+                       page_size = I915_GTT_PAGE_SIZE_2M;
+ 
+                       encode |= GEN8_PDE_PS_2M;
+ 
+                       vaddr = kmap_atomic_px(pd);
+               } else {
+                       struct i915_page_table *pt = pd->page_table[idx.pde];
+ 
+                       index = idx.pte;
+                       max = GEN8_PTES;
+                       page_size = I915_GTT_PAGE_SIZE;
+ 
+                       if (!index &&
+                           vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
+                           IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
+                           (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
+                            rem >= (max - index) << PAGE_SHIFT))
+                               maybe_64K = true;
+ 
+                       vaddr = kmap_atomic_px(pt);
+               }
+ 
+               do {
+                       GEM_BUG_ON(iter->sg->length < page_size);
+                       vaddr[index++] = encode | iter->dma;
+ 
+                       start += page_size;
+                       iter->dma += page_size;
+                       rem -= page_size;
+                       if (iter->dma >= iter->max) {
+                               iter->sg = __sg_next(iter->sg);
+                               if (!iter->sg)
+                                       break;
+ 
+                               rem = iter->sg->length;
+                               iter->dma = sg_dma_address(iter->sg);
+                               iter->max = iter->dma + rem;
+ 
+                               if (maybe_64K && index < max &&
+                                   !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
+                                     (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
+                                      rem >= (max - index) << PAGE_SHIFT)))
+                                       maybe_64K = false;
+ 
+                               if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
+                                       break;
+                       }
+               } while (rem >= page_size && index < max);
+ 
+               kunmap_atomic(vaddr);
+ 
+               /*
+                * Is it safe to mark the 2M block as 64K? -- Either we have
+                * filled whole page-table with 64K entries, or filled part of
+                * it and have reached the end of the sg table and we have
+                * enough padding.
+                */
+               if (maybe_64K &&
+                   (index == max ||
+                    (i915_vm_has_scratch_64K(vma->vm) &&
+                     !iter->sg && IS_ALIGNED(vma->node.start +
+                                             vma->node.size,
+                                             I915_GTT_PAGE_SIZE_2M)))) {
+                       vaddr = kmap_atomic_px(pd);
+                       vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
+                       kunmap_atomic(vaddr);
+                       page_size = I915_GTT_PAGE_SIZE_64K;
+               }
+ 
+               vma->page_sizes.gtt |= page_size;
+       } while (iter->sg);
   }
   
   static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
@@@ -933,13 -1158,24 +1158,20 @@@
                                    u32 unused)
   {
         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- -      struct sgt_dma iter = {
- -              .sg = vma->pages->sgl,
- -              .dma = sg_dma_address(iter.sg),
- -              .max = iter.dma + iter.sg->length,
- -      };
+ +      struct sgt_dma iter = sgt_dma(vma);
         struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
-       struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
   
-       while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter,
-                                            &idx, cache_level))
-               GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+       if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
+               gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level);
+       } else {
+               struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
+ 
+               while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
+                                                    &iter, &idx, cache_level))
+                       GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+ 
+               vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+       }
   }
   
   static void gen8_free_page_tables(struct i915_address_space *vm,
@@@ -1098,19 -1334,22 +1330,22 @@@ static int gen8_ppgtt_alloc_pd(struct i
         unsigned int pde;
   
         gen8_for_each_pde(pt, pd, start, length, pde) {
+               int count = gen8_pte_count(start, length);
+ 
                 if (pt == vm->scratch_pt) {
                         pt = alloc_pt(vm);
                         if (IS_ERR(pt))
                                 goto unwind;
   
-                       gen8_initialize_pt(vm, pt);
+                       if (count < GEN8_PTES || intel_vgpu_active(vm->i915))
+                               gen8_initialize_pt(vm, pt);
   
                         gen8_ppgtt_set_pde(vm, pd, pt, pde);
                         pd->used_pdes++;
                         GEM_BUG_ON(pd->used_pdes > I915_PDES);
                 }
   
-               pt->used_ptes += gen8_pte_count(start, length);
+               pt->used_ptes += count;
         }
         return 0;
   
@@@ -1333,18 -1572,18 +1568,18 @@@ static int gen8_ppgtt_init(struct i915_
                 1ULL << 48 :
                 1ULL << 32;
   
-       ret = gen8_init_scratch(&ppgtt->base);
-       if (ret) {
-               ppgtt->base.total = 0;
-               return ret;
-       }
- 
         /* There are only few exceptions for gen >=6. chv and bxt.
          * And we are not sure about the latter so play safe for now.
          */
         if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
                 ppgtt->base.pt_kmap_wc = true;
   
+       ret = gen8_init_scratch(&ppgtt->base);
+       if (ret) {
+               ppgtt->base.total = 0;
+               return ret;
+       }
+ 
         if (use_4lvl(vm)) {
                 ret = setup_px(&ppgtt->base, &ppgtt->pml4);
                 if (ret)
@@@ -1381,6 -1620,8 +1616,8 @@@
         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
         ppgtt->base.bind_vma = ppgtt_bind_vma;
+       ppgtt->base.set_pages = ppgtt_set_pages;
+       ppgtt->base.clear_pages = clear_pages;
         ppgtt->debug_dump = gen8_dump_ppgtt;
   
         return 0;
@@@ -1628,10 -1869,13 +1865,10 @@@ static void gen6_ppgtt_insert_entries(s
         unsigned act_pt = first_entry / GEN6_PTES;
         unsigned act_pte = first_entry % GEN6_PTES;
         const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
- -      struct sgt_dma iter;
+ +      struct sgt_dma iter = sgt_dma(vma);
         gen6_pte_t *vaddr;
   
         vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
- -      iter.sg = vma->pages->sgl;
- -      iter.dma = sg_dma_address(iter.sg);
- -      iter.max = iter.dma + iter.sg->length;
         do {
                 vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
   
@@@ -1652,6 -1896,8 +1889,8 @@@
                 }
         } while (1);
         kunmap_atomic(vaddr);
+ 
+       vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
   }
   
   static int gen6_alloc_va_range(struct i915_address_space *vm,
@@@ -1820,6 -2066,8 +2059,8 @@@ static int gen6_ppgtt_init(struct i915_
         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
         ppgtt->base.bind_vma = ppgtt_bind_vma;
+       ppgtt->base.set_pages = ppgtt_set_pages;
+       ppgtt->base.clear_pages = clear_pages;
         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
         ppgtt->debug_dump = gen6_dump_ppgtt;
   
@@@ -1859,13 -2107,13 +2100,13 @@@ static void i915_address_space_init(str
         INIT_LIST_HEAD(&vm->unbound_list);
   
         list_add_tail(&vm->global_link, &dev_priv->vm_list);
- -      pagevec_init(&vm->free_pages, false);
+ +      pagevec_init(&vm->free_pages);
   }
   
   static void i915_address_space_fini(struct i915_address_space *vm)
   {
         if (pagevec_count(&vm->free_pages))
-               vm_free_pages_release(vm);
+               vm_free_pages_release(vm, true);
   
         i915_gem_timeline_fini(&vm->timeline);
         drm_mm_takedown(&vm->mm);
@@@ -1878,15 -2126,32 +2119,32 @@@ static void gtt_write_workarounds(struc
          * called on driver load and after a GPU reset, so you can place
          * workarounds here even if they get overwritten by GPU reset.
          */
-       /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
+       /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
         if (IS_BROADWELL(dev_priv))
                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
         else if (IS_CHERRYVIEW(dev_priv))
                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-       else if (IS_GEN9_BC(dev_priv))
+       else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
         else if (IS_GEN9_LP(dev_priv))
                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+ 
+       /*
+        * To support 64K PTEs we need to first enable the use of the
+        * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
+        * mmio, otherwise the page-walker will simply ignore the IPS bit. This
+        * shouldn't be needed after GEN10.
+        *
+        * 64K pages were first introduced from BDW+, although technically they
+        * only *work* from gen9+. For pre-BDW we instead have the option for
+        * 32K pages, but we don't currently have any support for it in our
+        * driver.
+        */
+       if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
+           INTEL_GEN(dev_priv) <= 10)
+               I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
+                          I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
+                          GAMW_ECO_ENABLE_64K_IPS_FIELD);
   }
   
   int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
@@@ -1896,7 -2161,7 +2154,7 @@@
         /* In the case of execlists, PPGTT is enabled by the context descriptor
          * and the PDPs are contained within the context itself.  We don't
          * need to do anything here. */
-       if (i915.enable_execlists)
+       if (i915_modparams.enable_execlists)
                 return 0;
   
         if (!USES_PPGTT(dev_priv))
@@@ -2331,12 -2596,6 +2589,6 @@@ static int ggtt_bind_vma(struct i915_vm
         struct drm_i915_gem_object *obj = vma->obj;
         u32 pte_flags;
   
-       if (unlikely(!vma->pages)) {
-               int ret = i915_get_ggtt_vma_pages(vma);
-               if (ret)
-                       return ret;
-       }
- 
         /* Currently applicable only to VLV */
         pte_flags = 0;
         if (obj->gt_ro)
@@@ -2346,6 -2605,8 +2598,8 @@@
         vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
         intel_runtime_pm_put(i915);
   
+       vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+ 
         /*
          * Without aliasing PPGTT there's no difference between
          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
@@@ -2373,12 -2634,6 +2627,6 @@@ static int aliasing_gtt_bind_vma(struc
         u32 pte_flags;
         int ret;
   
-       if (unlikely(!vma->pages)) {
-               ret = i915_get_ggtt_vma_pages(vma);
-               if (ret)
-                       return ret;
-       }
- 
         /* Currently applicable only to VLV */
         pte_flags = 0;
         if (vma->obj->gt_ro)
@@@ -2393,7 -2648,7 +2641,7 @@@
                                                              vma->node.start,
                                                              vma->size);
                         if (ret)
-                               goto err_pages;
+                               return ret;
                 }
   
                 appgtt->base.insert_entries(&appgtt->base, vma, cache_level,
@@@ -2407,17 -2662,6 +2655,6 @@@
         }
   
         return 0;
- 
- err_pages:
-       if (!(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND))) {
-               if (vma->pages != vma->obj->mm.pages) {
-                       GEM_BUG_ON(!vma->pages);
-                       sg_free_table(vma->pages);
-                       kfree(vma->pages);
-               }
-               vma->pages = NULL;
-       }
-       return ret;
   }
   
   static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
@@@ -2455,6 -2699,21 +2692,21 @@@ void i915_gem_gtt_finish_pages(struct d
         dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
   }
   
+ static int ggtt_set_pages(struct i915_vma *vma)
+ {
+       int ret;
+ 
+       GEM_BUG_ON(vma->pages);
+ 
+       ret = i915_get_ggtt_vma_pages(vma);
+       if (ret)
+               return ret;
+ 
+       vma->page_sizes = vma->obj->mm.page_sizes;
+ 
+       return 0;
+ }
+ 
   static void i915_gtt_color_adjust(const struct drm_mm_node *node,
                                   unsigned long color,
                                   u64 *start,
@@@ -2591,6 -2850,7 +2843,7 @@@ void i915_ggtt_cleanup_hw(struct drm_i9
   {
         struct i915_ggtt *ggtt = &dev_priv->ggtt;
         struct i915_vma *vma, *vn;
+       struct pagevec *pvec;
   
         ggtt->base.closed = true;
   
@@@ -2614,6 -2874,13 +2867,13 @@@
         }
   
         ggtt->base.cleanup(&ggtt->base);
+ 
+       pvec = &dev_priv->mm.wc_stash;
+       if (pvec->nr) {
+               set_pages_array_wb(pvec->pages, pvec->nr);
+               __pagevec_release(pvec);
+       }
+ 
         mutex_unlock(&dev_priv->drm.struct_mutex);
   
         arch_phys_wc_del(ggtt->mtrr);
@@@ -2709,13 -2976,13 +2969,13 @@@ static int ggtt_probe_common(struct i91
         phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
   
         /*
-        * On BXT writes larger than 64 bit to the GTT pagetable range will be
-        * dropped. For WC mappings in general we have 64 byte burst writes
-        * when the WC buffer is flushed, so we can't use it, but have to
+        * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
+        * will be dropped. For WC mappings in general we have 64 byte burst
+        * writes when the WC buffer is flushed, so we can't use it, but have to
          * resort to an uncached mapping. The WC issue is easily caught by the
          * readback check when writing GTT PTE entries.
          */
-       if (IS_GEN9_LP(dev_priv))
+       if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
                 ggtt->gsm = ioremap_nocache(phys_addr, size);
         else
                 ggtt->gsm = ioremap_wc(phys_addr, size);
@@@ -2735,41 -3002,209 +2995,209 @@@
         return 0;
   }
   
- static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+ static struct intel_ppat_entry *
+ __alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
+ {
+       struct intel_ppat_entry *entry = &ppat->entries[index];
+ 
+       GEM_BUG_ON(index >= ppat->max_entries);
+       GEM_BUG_ON(test_bit(index, ppat->used));
+ 
+       entry->ppat = ppat;
+       entry->value = value;
+       kref_init(&entry->ref);
+       set_bit(index, ppat->used);
+       set_bit(index, ppat->dirty);
+ 
+       return entry;
+ }
+ 
+ static void __free_ppat_entry(struct intel_ppat_entry *entry)
   {
+       struct intel_ppat *ppat = entry->ppat;
+       unsigned int index = entry - ppat->entries;
+ 
+       GEM_BUG_ON(index >= ppat->max_entries);
+       GEM_BUG_ON(!test_bit(index, ppat->used));
+ 
+       entry->value = ppat->clear_value;
+       clear_bit(index, ppat->used);
+       set_bit(index, ppat->dirty);
+ }
+ 
+ /**
+  * intel_ppat_get - get a usable PPAT entry
+  * @i915: i915 device instance
+  * @value: the PPAT value required by the caller
+  *
+  * The function tries to search if there is an existing PPAT entry which
+  * matches with the required value. If perfectly matched, the existing PPAT
+  * entry will be used. If only partially matched, it will try to check if
+  * there is any available PPAT index. If yes, it will allocate a new PPAT
+  * index for the required entry and update the HW. If not, the partially
+  * matched entry will be used.
+  */
+ const struct intel_ppat_entry *
+ intel_ppat_get(struct drm_i915_private *i915, u8 value)
+ {
+       struct intel_ppat *ppat = &i915->ppat;
+       struct intel_ppat_entry *entry;
+       unsigned int scanned, best_score;
+       int i;
+ 
+       GEM_BUG_ON(!ppat->max_entries);
+ 
+       scanned = best_score = 0;
+       for_each_set_bit(i, ppat->used, ppat->max_entries) {
+               unsigned int score;
+ 
+               score = ppat->match(ppat->entries[i].value, value);
+               if (score > best_score) {
+                       entry = &ppat->entries[i];
+                       if (score == INTEL_PPAT_PERFECT_MATCH) {
+                               kref_get(&entry->ref);
+                               return entry;
+                       }
+                       best_score = score;
+               }
+               scanned++;
+       }
+ 
+       if (scanned == ppat->max_entries) {
+               if (!best_score)
+                       return ERR_PTR(-ENOSPC);
+ 
+               kref_get(&entry->ref);
+               return entry;
+       }
+ 
+       i = find_first_zero_bit(ppat->used, ppat->max_entries);
+       entry = __alloc_ppat_entry(ppat, i, value);
+       ppat->update_hw(i915);
+       return entry;
+ }
+ 
+ static void release_ppat(struct kref *kref)
+ {
+       struct intel_ppat_entry *entry =
+               container_of(kref, struct intel_ppat_entry, ref);
+       struct drm_i915_private *i915 = entry->ppat->i915;
+ 
+       __free_ppat_entry(entry);
+       entry->ppat->update_hw(i915);
+ }
+ 
+ /**
+  * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
+  * @entry: an intel PPAT entry
+  *
+  * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
+  * entry is dynamically allocated, its reference count will be decreased. Once
+  * the reference count becomes into zero, the PPAT index becomes free again.
+  */
+ void intel_ppat_put(const struct intel_ppat_entry *entry)
+ {
+       struct intel_ppat *ppat = entry->ppat;
+       unsigned int index = entry - ppat->entries;
+ 
+       GEM_BUG_ON(!ppat->max_entries);
+ 
+       kref_put(&ppat->entries[index].ref, release_ppat);
+ }
+ 
+ static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
+ {
+       struct intel_ppat *ppat = &dev_priv->ppat;
+       int i;
+ 
+       for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
+               I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
+               clear_bit(i, ppat->dirty);
+       }
+ }
+ 
+ static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
+ {
+       struct intel_ppat *ppat = &dev_priv->ppat;
+       u64 pat = 0;
+       int i;
+ 
+       for (i = 0; i < ppat->max_entries; i++)
+               pat |= GEN8_PPAT(i, ppat->entries[i].value);
+ 
+       bitmap_clear(ppat->dirty, 0, ppat->max_entries);
+ 
+       I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
+       I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
+ }
+ 
+ static unsigned int bdw_private_pat_match(u8 src, u8 dst)
+ {
+       unsigned int score = 0;
+       enum {
+               AGE_MATCH = BIT(0),
+               TC_MATCH = BIT(1),
+               CA_MATCH = BIT(2),
+       };
+ 
+       /* Cache attribute has to be matched. */
+       if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
+               return 0;
+ 
+       score |= CA_MATCH;
+ 
+       if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
+               score |= TC_MATCH;
+ 
+       if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
+               score |= AGE_MATCH;
+ 
+       if (score == (AGE_MATCH | TC_MATCH | CA_MATCH))
+               return INTEL_PPAT_PERFECT_MATCH;
+ 
+       return score;
+ }
+ 
+ static unsigned int chv_private_pat_match(u8 src, u8 dst)
+ {
+       return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
+               INTEL_PPAT_PERFECT_MATCH : 0;
+ }
+ 
+ static void cnl_setup_private_ppat(struct intel_ppat *ppat)
+ {
+       ppat->max_entries = 8;
+       ppat->update_hw = cnl_private_pat_update_hw;
+       ppat->match = bdw_private_pat_match;
+       ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
+ 
         /* XXX: spec is unclear if this is still needed for CNL+ */
-       if (!USES_PPGTT(dev_priv)) {
-               I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
+       if (!USES_PPGTT(ppat->i915)) {
+               __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
                 return;
         }
   
-       I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
-       I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
-       I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
-       I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
-       I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-       I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-       I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-       I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+       __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
+       __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
+       __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+       __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
+       __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
+       __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
+       __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
+       __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
   }
   
   /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
    * bits. When using advanced contexts each context stores its own PAT, but
    * writing this data shouldn't be harmful even in those cases. */
- static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
+ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
   {
-       u64 pat;
+       ppat->max_entries = 8;
+       ppat->update_hw = bdw_private_pat_update_hw;
+       ppat->match = bdw_private_pat_match;
+       ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
   
-       pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
-             GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
-             GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
-             GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
-             GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
-             GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
-             GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
-             GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
- 
-       if (!USES_PPGTT(dev_priv))
+       if (!USES_PPGTT(ppat->i915)) {
                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
                  * so RTL will always use the value corresponding to
                  * pat_sel = 000".
@@@ -2783,17 -3218,26 +3211,26 @@@
                  * So we can still hold onto all our assumptions wrt cpu
                  * clflushing on LLC machines.
                  */
-               pat = GEN8_PPAT(0, GEN8_PPAT_UC);
+               __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+               return;
+       }
   
-       /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
-        * write would work. */
-       I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-       I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+       __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);      /* for normal objects, no eLLC */
+       __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for something pointing to ptes? */
+       __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for scanout with eLLC */
+       __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);                      /* Uncached objects, mostly for scanout */
+       __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
+       __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
+       __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
+       __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
   }
   
- static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
+ static void chv_setup_private_ppat(struct intel_ppat *ppat)
   {
-       u64 pat;
+       ppat->max_entries = 8;
+       ppat->update_hw = bdw_private_pat_update_hw;
+       ppat->match = chv_private_pat_match;
+       ppat->clear_value = CHV_PPAT_SNOOP;
   
         /*
          * Map WB on BDW to snooped on CHV.
@@@ -2813,17 -3257,15 +3250,15 @@@
          * Which means we must set the snoop bit in PAT entry 0
          * in order to keep the global status page working.
          */
-       pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
-             GEN8_PPAT(1, 0) |
-             GEN8_PPAT(2, 0) |
-             GEN8_PPAT(3, 0) |
-             GEN8_PPAT(4, CHV_PPAT_SNOOP) |
-             GEN8_PPAT(5, CHV_PPAT_SNOOP) |
-             GEN8_PPAT(6, CHV_PPAT_SNOOP) |
-             GEN8_PPAT(7, CHV_PPAT_SNOOP);
   
-       I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-       I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+       __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
+       __alloc_ppat_entry(ppat, 1, 0);
+       __alloc_ppat_entry(ppat, 2, 0);
+       __alloc_ppat_entry(ppat, 3, 0);
+       __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
+       __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
+       __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
+       __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
   }
   
   static void gen6_gmch_remove(struct i915_address_space *vm)
@@@ -2834,6 -3276,31 +3269,31 @@@
         cleanup_scratch_page(vm);
   }
   
+ static void setup_private_pat(struct drm_i915_private *dev_priv)
+ {
+       struct intel_ppat *ppat = &dev_priv->ppat;
+       int i;
+ 
+       ppat->i915 = dev_priv;
+ 
+       if (INTEL_GEN(dev_priv) >= 10)
+               cnl_setup_private_ppat(ppat);
+       else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+               chv_setup_private_ppat(ppat);
+       else
+               bdw_setup_private_ppat(ppat);
+ 
+       GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES);
+ 
+       for_each_clear_bit(i, ppat->used, ppat->max_entries) {
+               ppat->entries[i].value = ppat->clear_value;
+               ppat->entries[i].ppat = ppat;
+               set_bit(i, ppat->dirty);
+       }
+ 
+       ppat->update_hw(dev_priv);
+ }
+ 
   static int gen8_gmch_probe(struct i915_ggtt *ggtt)
   {
         struct drm_i915_private *dev_priv = ggtt->base.i915;
@@@ -2866,17 -3333,11 +3326,11 @@@
         }
   
         ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
- 
-       if (INTEL_GEN(dev_priv) >= 10)
-               cnl_setup_private_ppat(dev_priv);
-       else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-               chv_setup_private_ppat(dev_priv);
-       else
-               bdw_setup_private_ppat(dev_priv);
- 
         ggtt->base.cleanup = gen6_gmch_remove;
         ggtt->base.bind_vma = ggtt_bind_vma;
         ggtt->base.unbind_vma = ggtt_unbind_vma;
+       ggtt->base.set_pages = ggtt_set_pages;
+       ggtt->base.clear_pages = clear_pages;
         ggtt->base.insert_page = gen8_ggtt_insert_page;
         ggtt->base.clear_range = nop_clear_range;
         if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
@@@ -2894,6 -3355,8 +3348,8 @@@
   
         ggtt->invalidate = gen6_ggtt_invalidate;
   
+       setup_private_pat(dev_priv);
+ 
         return ggtt_probe_common(ggtt, size);
   }
   
@@@ -2933,6 -3396,8 +3389,8 @@@ static int gen6_gmch_probe(struct i915_
         ggtt->base.insert_entries = gen6_ggtt_insert_entries;
         ggtt->base.bind_vma = ggtt_bind_vma;
         ggtt->base.unbind_vma = ggtt_unbind_vma;
+       ggtt->base.set_pages = ggtt_set_pages;
+       ggtt->base.clear_pages = clear_pages;
         ggtt->base.cleanup = gen6_gmch_remove;
   
         ggtt->invalidate = gen6_ggtt_invalidate;
@@@ -2978,6 -3443,8 +3436,8 @@@ static int i915_gmch_probe(struct i915_
         ggtt->base.clear_range = i915_ggtt_clear_range;
         ggtt->base.bind_vma = ggtt_bind_vma;
         ggtt->base.unbind_vma = ggtt_unbind_vma;
+       ggtt->base.set_pages = ggtt_set_pages;
+       ggtt->base.clear_pages = clear_pages;
         ggtt->base.cleanup = i915_gmch_remove;
   
         ggtt->invalidate = gmch_ggtt_invalidate;
@@@ -3014,7 -3481,7 +3474,7 @@@ int i915_ggtt_probe_hw(struct drm_i915_
          * currently don't have any bits spare to pass in this upper
          * restriction!
          */
-       if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
+       if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
                 ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
                 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
         }
@@@ -3127,8 -3594,7 +3587,7 @@@ void i915_gem_restore_gtt_mappings(stru
         ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */
   
         /* clflush objects bound into the GGTT and rebind them. */
-       list_for_each_entry_safe(obj, on,
-                                &dev_priv->mm.bound_list, global_link) {
+       list_for_each_entry_safe(obj, on, &dev_priv->mm.bound_list, mm.link) {
                 bool ggtt_bound = false;
                 struct i915_vma *vma;
   
@@@ -3151,13 -3617,10 +3610,10 @@@
         ggtt->base.closed = false;
   
         if (INTEL_GEN(dev_priv) >= 8) {
-               if (INTEL_GEN(dev_priv) >= 10)
-                       cnl_setup_private_ppat(dev_priv);
-               else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-                       chv_setup_private_ppat(dev_priv);
-               else
-                       bdw_setup_private_ppat(dev_priv);
+               struct intel_ppat *ppat = &dev_priv->ppat;
   
+               bitmap_set(ppat->dirty, 0, ppat->max_entries);
+               dev_priv->ppat.update_hw(dev_priv);
                 return;
         }
   
diff --combined drivers/gpu/drm/i915/i915_gem_userptr.c

index aa22361bd5a15a47129b42a7bcd90fcf51bbdce9,e26b23171b56f5425f44e9094e7a55a28465b821..135fc750a8375f172e130c6b45b85747535693d9
--- 1/drivers/gpu/drm/i915/i915_gem_userptr.c
--- 2/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@@ -82,11 -82,11 +82,11 @@@ static void cancel_userptr(struct work_
         /* We are inside a kthread context and can't be interrupted */
         if (i915_gem_object_unbind(obj) == 0)
                 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
-       WARN_ONCE(obj->mm.pages,
-                 "Failed to release pages: bind_count=%d, pages_pin_count=%d, pin_display=%d\n",
+       WARN_ONCE(i915_gem_object_has_pages(obj),
+                 "Failed to release pages: bind_count=%d, pages_pin_count=%d, pin_global=%d\n",
                   obj->bind_count,
                   atomic_read(&obj->mm.pages_pin_count),
-                 obj->pin_display);
+                 obj->pin_global);
   
         mutex_unlock(&obj->base.dev->struct_mutex);
   
@@@ -164,7 -164,6 +164,6 @@@ static struct i915_mmu_notifier 
   i915_mmu_notifier_create(struct mm_struct *mm)
   {
         struct i915_mmu_notifier *mn;
-       int ret;
   
         mn = kmalloc(sizeof(*mn), GFP_KERNEL);
         if (mn == NULL)
@@@ -179,14 -178,6 +178,6 @@@
                 return ERR_PTR(-ENOMEM);
         }
   
-        /* Protected by mmap_sem (write-lock) */
-       ret = __mmu_notifier_register(&mn->mn, mm);
-       if (ret) {
-               destroy_workqueue(mn->wq);
-               kfree(mn);
-               return ERR_PTR(ret);
-       }
- 
         return mn;
   }
   
@@@ -210,23 -201,42 +201,42 @@@ i915_gem_userptr_release__mmu_notifier(
   static struct i915_mmu_notifier *
   i915_mmu_notifier_find(struct i915_mm_struct *mm)
   {
-       struct i915_mmu_notifier *mn = mm->mn;
+       struct i915_mmu_notifier *mn;
+       int err = 0;
   
         mn = mm->mn;
         if (mn)
                 return mn;
   
+       mn = i915_mmu_notifier_create(mm->mm);
+       if (IS_ERR(mn))
+               err = PTR_ERR(mn);
+ 
         down_write(&mm->mm->mmap_sem);
         mutex_lock(&mm->i915->mm_lock);
-       if ((mn = mm->mn) == NULL) {
-               mn = i915_mmu_notifier_create(mm->mm);
-               if (!IS_ERR(mn))
-                       mm->mn = mn;
+       if (mm->mn == NULL && !err) {
+               /* Protected by mmap_sem (write-lock) */
+               err = __mmu_notifier_register(&mn->mn, mm->mm);
+               if (!err) {
+                       /* Protected by mm_lock */
+                       mm->mn = fetch_and_zero(&mn);
+               }
+       } else if (mm->mn) {
+               /*
+                * Someone else raced and successfully installed the mmu
+                * notifier, we can cancel our own errors.
+                */
+               err = 0;
         }
         mutex_unlock(&mm->i915->mm_lock);
         up_write(&mm->mm->mmap_sem);
   
-       return mn;
+       if (mn && !IS_ERR(mn)) {
+               destroy_workqueue(mn->wq);
+               kfree(mn);
+       }
+ 
+       return err ? ERR_PTR(err) : mm->mn;
   }
   
   static int
@@@ -399,64 -409,47 +409,47 @@@ struct get_pages_work 
         struct task_struct *task;
   };
   
- #if IS_ENABLED(CONFIG_SWIOTLB)
- #define swiotlb_active() swiotlb_nr_tbl()
- #else
- #define swiotlb_active() 0
- #endif
- 
- static int
- st_set_pages(struct sg_table **st, struct page **pvec, int num_pages)
- {
-       struct scatterlist *sg;
-       int ret, n;
- 
-       *st = kmalloc(sizeof(**st), GFP_KERNEL);
-       if (*st == NULL)
-               return -ENOMEM;
- 
-       if (swiotlb_active()) {
-               ret = sg_alloc_table(*st, num_pages, GFP_KERNEL);
-               if (ret)
-                       goto err;
- 
-               for_each_sg((*st)->sgl, sg, num_pages, n)
-                       sg_set_page(sg, pvec[n], PAGE_SIZE, 0);
-       } else {
-               ret = sg_alloc_table_from_pages(*st, pvec, num_pages,
-                                               0, num_pages << PAGE_SHIFT,
-                                               GFP_KERNEL);
-               if (ret)
-                       goto err;
-       }
- 
-       return 0;
- 
- err:
-       kfree(*st);
-       *st = NULL;
-       return ret;
- }
- 
   static struct sg_table *
- __i915_gem_userptr_set_pages(struct drm_i915_gem_object *obj,
-                            struct page **pvec, int num_pages)
+ __i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj,
+                              struct page **pvec, int num_pages)
   {
-       struct sg_table *pages;
+       unsigned int max_segment = i915_sg_segment_size();
+       struct sg_table *st;
+       unsigned int sg_page_sizes;
         int ret;
   
-       ret = st_set_pages(&pages, pvec, num_pages);
-       if (ret)
+       st = kmalloc(sizeof(*st), GFP_KERNEL);
+       if (!st)
+               return ERR_PTR(-ENOMEM);
+ 
+ alloc_table:
+       ret = __sg_alloc_table_from_pages(st, pvec, num_pages,
+                                         0, num_pages << PAGE_SHIFT,
+                                         max_segment,
+                                         GFP_KERNEL);
+       if (ret) {
+               kfree(st);
                 return ERR_PTR(ret);
+       }
   
-       ret = i915_gem_gtt_prepare_pages(obj, pages);
+       ret = i915_gem_gtt_prepare_pages(obj, st);
         if (ret) {
-               sg_free_table(pages);
-               kfree(pages);
+               sg_free_table(st);
+ 
+               if (max_segment > PAGE_SIZE) {
+                       max_segment = PAGE_SIZE;
+                       goto alloc_table;
+               }
+ 
+               kfree(st);
                 return ERR_PTR(ret);
         }
   
-       return pages;
+       sg_page_sizes = i915_sg_page_sizes(st->sgl);
+ 
+       __i915_gem_object_set_pages(obj, st, sg_page_sizes);
+ 
+       return st;
   }
   
   static int
@@@ -540,9 -533,9 +533,9 @@@ __i915_gem_userptr_get_pages_worker(str
                 struct sg_table *pages = ERR_PTR(ret);
   
                 if (pinned == npages) {
-                       pages = __i915_gem_userptr_set_pages(obj, pvec, npages);
+                       pages = __i915_gem_userptr_alloc_pages(obj, pvec,
+                                                              npages);
                         if (!IS_ERR(pages)) {
-                               __i915_gem_object_set_pages(obj, pages);
                                 pinned = 0;
                                 pages = NULL;
                         }
@@@ -554,7 -547,7 +547,7 @@@
         }
         mutex_unlock(&obj->mm.lock);
   
- -      release_pages(pvec, pinned, 0);
+ +      release_pages(pvec, pinned);
         kvfree(pvec);
   
         i915_gem_object_put(obj);
@@@ -603,8 -596,7 +596,7 @@@ __i915_gem_userptr_get_pages_schedule(s
         return ERR_PTR(-EAGAIN);
   }
   
- static struct sg_table *
- i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
+ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
   {
         const int num_pages = obj->base.size >> PAGE_SHIFT;
         struct mm_struct *mm = obj->userptr.mm->mm;
@@@ -633,9 -625,9 +625,9 @@@
         if (obj->userptr.work) {
                 /* active flag should still be held for the pending work */
                 if (IS_ERR(obj->userptr.work))
-                       return ERR_CAST(obj->userptr.work);
+                       return PTR_ERR(obj->userptr.work);
                 else
-                       return ERR_PTR(-EAGAIN);
+                       return -EAGAIN;
         }
   
         pvec = NULL;
@@@ -661,17 -653,17 +653,17 @@@
                 pages = __i915_gem_userptr_get_pages_schedule(obj);
                 active = pages == ERR_PTR(-EAGAIN);
         } else {
-               pages = __i915_gem_userptr_set_pages(obj, pvec, num_pages);
+               pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages);
                 active = !IS_ERR(pages);
         }
         if (active)
                 __i915_gem_userptr_set_active(obj, true);
   
         if (IS_ERR(pages))
- -              release_pages(pvec, pinned, 0);
+ +              release_pages(pvec, pinned);
         kvfree(pvec);
   
-       return pages;
+       return PTR_ERR_OR_ZERO(pages);
   }
   
   static void
@@@ -834,7 -826,9 +826,9 @@@ int i915_gem_init_userptr(struct drm_i9
         hash_init(dev_priv->mm_structs);
   
         dev_priv->mm.userptr_wq =
-               alloc_workqueue("i915-userptr-acquire", WQ_HIGHPRI, 0);
+               alloc_workqueue("i915-userptr-acquire",
+                               WQ_HIGHPRI | WQ_MEM_RECLAIM,
+                               0);
         if (!dev_priv->mm.userptr_wq)
                 return -ENOMEM;
   
diff --combined drivers/gpu/drm/i915/i915_trace.h

index ef72da74b87f73f484d5b6f4322d457967e36f85,9cab91ddeb79f469b7cc410ce0cf2a64538688f9..4e76768ffa9570c0034575f77bbf3b2c682fa19b
--- 1/drivers/gpu/drm/i915/i915_trace.h
--- 2/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #if !defined(_I915_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
   #define _I915_TRACE_H_
   
@@@ -346,7 -345,7 +346,7 @@@ TRACE_EVENT(i915_gem_object_create
   
             TP_STRUCT__entry(
                              __field(struct drm_i915_gem_object *, obj)
-                            __field(u32, size)
+                            __field(u64, size)
                              ),
   
             TP_fast_assign(
@@@ -354,7 -353,7 +354,7 @@@
                            __entry->size = obj->base.size;
                            ),
   
-           TP_printk("obj=%p, size=%u", __entry->obj, __entry->size)
+           TP_printk("obj=%p, size=0x%llx", __entry->obj, __entry->size)
   );
   
   TRACE_EVENT(i915_gem_shrink,
@@@ -385,7 -384,7 +385,7 @@@ TRACE_EVENT(i915_vma_bind
                              __field(struct drm_i915_gem_object *, obj)
                              __field(struct i915_address_space *, vm)
                              __field(u64, offset)
-                            __field(u32, size)
+                            __field(u64, size)
                              __field(unsigned, flags)
                              ),
   
@@@ -397,7 -396,7 +397,7 @@@
                            __entry->flags = flags;
                            ),
   
-           TP_printk("obj=%p, offset=%016llx size=%x%s vm=%p",
+           TP_printk("obj=%p, offset=0x%016llx size=0x%llx%s vm=%p",
                       __entry->obj, __entry->offset, __entry->size,
                       __entry->flags & PIN_MAPPABLE ? ", mappable" : "",
                       __entry->vm)
@@@ -411,7 -410,7 +411,7 @@@ TRACE_EVENT(i915_vma_unbind
                              __field(struct drm_i915_gem_object *, obj)
                              __field(struct i915_address_space *, vm)
                              __field(u64, offset)
-                            __field(u32, size)
+                            __field(u64, size)
                              ),
   
             TP_fast_assign(
@@@ -421,18 -420,18 +421,18 @@@
                            __entry->size = vma->node.size;
                            ),
   
-           TP_printk("obj=%p, offset=%016llx size=%x vm=%p",
+           TP_printk("obj=%p, offset=0x%016llx size=0x%llx vm=%p",
                       __entry->obj, __entry->offset, __entry->size, __entry->vm)
   );
   
   TRACE_EVENT(i915_gem_object_pwrite,
-           TP_PROTO(struct drm_i915_gem_object *obj, u32 offset, u32 len),
+           TP_PROTO(struct drm_i915_gem_object *obj, u64 offset, u64 len),
             TP_ARGS(obj, offset, len),
   
             TP_STRUCT__entry(
                              __field(struct drm_i915_gem_object *, obj)
-                            __field(u32, offset)
-                            __field(u32, len)
+                            __field(u64, offset)
+                            __field(u64, len)
                              ),
   
             TP_fast_assign(
@@@ -441,18 -440,18 +441,18 @@@
                            __entry->len = len;
                            ),
   
-           TP_printk("obj=%p, offset=%u, len=%u",
+           TP_printk("obj=%p, offset=0x%llx, len=0x%llx",
                       __entry->obj, __entry->offset, __entry->len)
   );
   
   TRACE_EVENT(i915_gem_object_pread,
-           TP_PROTO(struct drm_i915_gem_object *obj, u32 offset, u32 len),
+           TP_PROTO(struct drm_i915_gem_object *obj, u64 offset, u64 len),
             TP_ARGS(obj, offset, len),
   
             TP_STRUCT__entry(
                              __field(struct drm_i915_gem_object *, obj)
-                            __field(u32, offset)
-                            __field(u32, len)
+                            __field(u64, offset)
+                            __field(u64, len)
                              ),
   
             TP_fast_assign(
@@@ -461,17 -460,17 +461,17 @@@
                            __entry->len = len;
                            ),
   
-           TP_printk("obj=%p, offset=%u, len=%u",
+           TP_printk("obj=%p, offset=0x%llx, len=0x%llx",
                       __entry->obj, __entry->offset, __entry->len)
   );
   
   TRACE_EVENT(i915_gem_object_fault,
-           TP_PROTO(struct drm_i915_gem_object *obj, u32 index, bool gtt, bool write),
+           TP_PROTO(struct drm_i915_gem_object *obj, u64 index, bool gtt, bool write),
             TP_ARGS(obj, index, gtt, write),
   
             TP_STRUCT__entry(
                              __field(struct drm_i915_gem_object *, obj)
-                            __field(u32, index)
+                            __field(u64, index)
                              __field(bool, gtt)
                              __field(bool, write)
                              ),
@@@ -483,7 -482,7 +483,7 @@@
                            __entry->write = write;
                            ),
   
-           TP_printk("obj=%p, %s index=%u %s",
+           TP_printk("obj=%p, %s index=%llu %s",
                       __entry->obj,
                       __entry->gtt ? "GTT" : "CPU",
                       __entry->index,
@@@ -516,14 -515,14 +516,14 @@@ DEFINE_EVENT(i915_gem_object, i915_gem_
   );
   
   TRACE_EVENT(i915_gem_evict,
-           TP_PROTO(struct i915_address_space *vm, u32 size, u32 align, unsigned int flags),
+           TP_PROTO(struct i915_address_space *vm, u64 size, u64 align, unsigned int flags),
             TP_ARGS(vm, size, align, flags),
   
             TP_STRUCT__entry(
                              __field(u32, dev)
                              __field(struct i915_address_space *, vm)
-                            __field(u32, size)
-                            __field(u32, align)
+                            __field(u64, size)
+                            __field(u64, align)
                              __field(unsigned int, flags)
                             ),
   
@@@ -535,43 -534,11 +535,11 @@@
                            __entry->flags = flags;
                           ),
   
-           TP_printk("dev=%d, vm=%p, size=%d, align=%d %s",
+           TP_printk("dev=%d, vm=%p, size=0x%llx, align=0x%llx %s",
                       __entry->dev, __entry->vm, __entry->size, __entry->align,
                       __entry->flags & PIN_MAPPABLE ? ", mappable" : "")
   );
   
- TRACE_EVENT(i915_gem_evict_everything,
-           TP_PROTO(struct drm_device *dev),
-           TP_ARGS(dev),
- 
-           TP_STRUCT__entry(
-                            __field(u32, dev)
-                           ),
- 
-           TP_fast_assign(
-                          __entry->dev = dev->primary->index;
-                         ),
- 
-           TP_printk("dev=%d", __entry->dev)
- );
- 
- TRACE_EVENT(i915_gem_evict_vm,
-           TP_PROTO(struct i915_address_space *vm),
-           TP_ARGS(vm),
- 
-           TP_STRUCT__entry(
-                            __field(u32, dev)
-                            __field(struct i915_address_space *, vm)
-                           ),
- 
-           TP_fast_assign(
-                          __entry->dev = vm->i915->drm.primary->index;
-                          __entry->vm = vm;
-                         ),
- 
-           TP_printk("dev=%d, vm=%p", __entry->dev, __entry->vm)
- );
- 
   TRACE_EVENT(i915_gem_evict_node,
             TP_PROTO(struct i915_address_space *vm, struct drm_mm_node *node, unsigned int flags),
             TP_ARGS(vm, node, flags),
@@@ -594,12 -561,29 +562,29 @@@
                            __entry->flags = flags;
                           ),
   
-           TP_printk("dev=%d, vm=%p, start=%llx size=%llx, color=%lx, flags=%x",
+           TP_printk("dev=%d, vm=%p, start=0x%llx size=0x%llx, color=0x%lx, flags=%x",
                       __entry->dev, __entry->vm,
                       __entry->start, __entry->size,
                       __entry->color, __entry->flags)
   );
   
+ TRACE_EVENT(i915_gem_evict_vm,
+           TP_PROTO(struct i915_address_space *vm),
+           TP_ARGS(vm),
+ 
+           TP_STRUCT__entry(
+                            __field(u32, dev)
+                            __field(struct i915_address_space *, vm)
+                           ),
+ 
+           TP_fast_assign(
+                          __entry->dev = vm->i915->drm.primary->index;
+                          __entry->vm = vm;
+                         ),
+ 
+           TP_printk("dev=%d, vm=%p", __entry->dev, __entry->vm)
+ );
+ 
   TRACE_EVENT(i915_gem_ring_sync_to,
             TP_PROTO(struct drm_i915_gem_request *to,
                      struct drm_i915_gem_request *from),
@@@ -650,29 -634,6 +635,6 @@@ TRACE_EVENT(i915_gem_request_queue
                       __entry->flags)
   );
   
- TRACE_EVENT(i915_gem_ring_flush,
-           TP_PROTO(struct drm_i915_gem_request *req, u32 invalidate, u32 flush),
-           TP_ARGS(req, invalidate, flush),
- 
-           TP_STRUCT__entry(
-                            __field(u32, dev)
-                            __field(u32, ring)
-                            __field(u32, invalidate)
-                            __field(u32, flush)
-                            ),
- 
-           TP_fast_assign(
-                          __entry->dev = req->i915->drm.primary->index;
-                          __entry->ring = req->engine->id;
-                          __entry->invalidate = invalidate;
-                          __entry->flush = flush;
-                          ),
- 
-           TP_printk("dev=%u, ring=%x, invalidate=%04x, flush=%04x",
-                     __entry->dev, __entry->ring,
-                     __entry->invalidate, __entry->flush)
- );
- 
   DECLARE_EVENT_CLASS(i915_gem_request,
             TP_PROTO(struct drm_i915_gem_request *req),
             TP_ARGS(req),
@@@ -1032,5 -993,5 +994,5 @@@ TRACE_EVENT(switch_mm
   
   /* This part must be outside protection */
   #undef TRACE_INCLUDE_PATH
- #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915
   #include <trace/define_trace.h>
diff --combined drivers/gpu/drm/i915/intel_display.c

index 5ebdb63330ddf13af590fee88fda5eb9139f80bb,f4a9a182868f50dc0cd3f04c69de73909e94216a..878acc432a4b0c7ad3ea4774696928309756b207
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -1539,7 -1539,7 +1539,7 @@@ static void chv_enable_pll(struct intel
                  * DPLLCMD is AWOL. Use chicken bits to propagate
                  * the value from DPLLBMD to either pipe B or C.
                  */
-               I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
+               I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
                 I915_WRITE(CBR4_VLV, 0);
                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
@@@ -1568,11 -1568,12 +1568,12 @@@ static int intel_num_dvo_pipes(struct d
         return count;
   }
   
- static void i9xx_enable_pll(struct intel_crtc *crtc)
+ static void i9xx_enable_pll(struct intel_crtc *crtc,
+                           const struct intel_crtc_state *crtc_state)
   {
         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
         i915_reg_t reg = DPLL(crtc->pipe);
-       u32 dpll = crtc->config->dpll_hw_state.dpll;
+       u32 dpll = crtc_state->dpll_hw_state.dpll;
         int i;
   
         assert_pipe_disabled(dev_priv, crtc->pipe);
@@@ -1609,7 -1610,7 +1610,7 @@@
   
         if (INTEL_GEN(dev_priv) >= 4) {
                 I915_WRITE(DPLL_MD(crtc->pipe),
-                          crtc->config->dpll_hw_state.dpll_md);
+                          crtc_state->dpll_hw_state.dpll_md);
         } else {
                 /* The pixel multiplier can only be updated once the
                  * DPLL is enabled and the clocks are stable.
@@@ -1627,15 -1628,6 +1628,6 @@@
         }
   }
   
- /**
-  * i9xx_disable_pll - disable a PLL
-  * @dev_priv: i915 private structure
-  * @pipe: pipe PLL to disable
-  *
-  * Disable the PLL for @pipe, making sure the pipe is off first.
-  *
-  * Note!  This is for pre-ILK only.
-  */
   static void i9xx_disable_pll(struct intel_crtc *crtc)
   {
         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@@ -2219,8 -2211,7 +2211,7 @@@ intel_pin_and_fence_fb_obj(struct drm_f
                  * something and try to run the system in a "less than optimal"
                  * mode that matches the user configuration.
                  */
-               if (i915_vma_get_fence(vma) == 0)
-                       i915_vma_pin_fence(vma);
+               i915_vma_pin_fence(vma);
         }
   
         i915_vma_get(vma);
@@@ -2856,7 -2847,7 +2847,7 @@@ intel_find_initial_plane_obj(struct int
   
                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
                         fb = c->primary->fb;
-                       drm_framebuffer_reference(fb);
+                       drm_framebuffer_get(fb);
                         goto valid_fb;
                 }
         }
@@@ -2887,7 -2878,7 +2878,7 @@@ valid_fb
                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
   
                 intel_state->vma = NULL;
-               drm_framebuffer_unreference(fb);
+               drm_framebuffer_put(fb);
                 return;
         }
   
@@@ -2908,7 -2899,7 +2899,7 @@@
         if (i915_gem_object_is_tiled(obj))
                 dev_priv->preserve_bios_swizzle = true;
   
-       drm_framebuffer_reference(fb);
+       drm_framebuffer_get(fb);
         primary->fb = primary->state->fb = fb;
         primary->crtc = primary->state->crtc = &intel_crtc->base;
   
@@@ -3298,7 -3289,6 +3289,6 @@@ static void i9xx_update_primary_plane(s
                                       const struct intel_plane_state *plane_state)
   {
         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
         const struct drm_framebuffer *fb = plane_state->base.fb;
         enum plane plane = primary->plane;
         u32 linear_offset;
@@@ -3307,16 -3297,14 +3297,14 @@@
         int x = plane_state->main.x;
         int y = plane_state->main.y;
         unsigned long irqflags;
+       u32 dspaddr_offset;
   
         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
   
         if (INTEL_GEN(dev_priv) >= 4)
-               crtc->dspaddr_offset = plane_state->main.offset;
+               dspaddr_offset = plane_state->main.offset;
         else
-               crtc->dspaddr_offset = linear_offset;
- 
-       crtc->adjusted_x = x;
-       crtc->adjusted_y = y;
+               dspaddr_offset = linear_offset;
   
         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
   
@@@ -3342,18 -3330,18 +3330,18 @@@
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
                 I915_WRITE_FW(DSPSURF(plane),
                               intel_plane_ggtt_offset(plane_state) +
-                             crtc->dspaddr_offset);
+                             dspaddr_offset);
                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
         } else if (INTEL_GEN(dev_priv) >= 4) {
                 I915_WRITE_FW(DSPSURF(plane),
                               intel_plane_ggtt_offset(plane_state) +
-                             crtc->dspaddr_offset);
+                             dspaddr_offset);
                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
         } else {
                 I915_WRITE_FW(DSPADDR(plane),
                               intel_plane_ggtt_offset(plane_state) +
-                             crtc->dspaddr_offset);
+                             dspaddr_offset);
         }
         POSTING_READ_FW(reg);
   
@@@ -3553,100 -3541,6 +3541,6 @@@ u32 skl_plane_ctl(const struct intel_cr
         return plane_ctl;
   }
   
- static void skylake_update_primary_plane(struct intel_plane *plane,
-                                        const struct intel_crtc_state *crtc_state,
-                                        const struct intel_plane_state *plane_state)
- {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-       const struct drm_framebuffer *fb = plane_state->base.fb;
-       enum plane_id plane_id = plane->id;
-       enum pipe pipe = plane->pipe;
-       u32 plane_ctl = plane_state->ctl;
-       unsigned int rotation = plane_state->base.rotation;
-       u32 stride = skl_plane_stride(fb, 0, rotation);
-       u32 aux_stride = skl_plane_stride(fb, 1, rotation);
-       u32 surf_addr = plane_state->main.offset;
-       int scaler_id = plane_state->scaler_id;
-       int src_x = plane_state->main.x;
-       int src_y = plane_state->main.y;
-       int src_w = drm_rect_width(&plane_state->base.src) >> 16;
-       int src_h = drm_rect_height(&plane_state->base.src) >> 16;
-       int dst_x = plane_state->base.dst.x1;
-       int dst_y = plane_state->base.dst.y1;
-       int dst_w = drm_rect_width(&plane_state->base.dst);
-       int dst_h = drm_rect_height(&plane_state->base.dst);
-       unsigned long irqflags;
- 
-       /* Sizes are 0 based */
-       src_w--;
-       src_h--;
-       dst_w--;
-       dst_h--;
- 
-       crtc->dspaddr_offset = surf_addr;
- 
-       crtc->adjusted_x = src_x;
-       crtc->adjusted_y = src_y;
- 
-       spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- 
-       if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-               I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-                             PLANE_COLOR_PIPE_GAMMA_ENABLE |
-                             PLANE_COLOR_PIPE_CSC_ENABLE |
-                             PLANE_COLOR_PLANE_GAMMA_DISABLE);
-       }
- 
-       I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
-       I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
-       I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
-       I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-       I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-                     (plane_state->aux.offset - surf_addr) | aux_stride);
-       I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
-                     (plane_state->aux.y << 16) | plane_state->aux.x);
- 
-       if (scaler_id >= 0) {
-               uint32_t ps_ctrl = 0;
- 
-               WARN_ON(!dst_w || !dst_h);
-               ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-                       crtc_state->scaler_state.scalers[scaler_id].mode;
-               I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
-               I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
-               I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
-               I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
-               I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
-       } else {
-               I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
-       }
- 
-       I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
-                     intel_plane_ggtt_offset(plane_state) + surf_addr);
- 
-       POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
- 
-       spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
- }
- 
- static void skylake_disable_primary_plane(struct intel_plane *primary,
-                                         struct intel_crtc *crtc)
- {
-       struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-       enum plane_id plane_id = primary->id;
-       enum pipe pipe = primary->pipe;
-       unsigned long irqflags;
- 
-       spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- 
-       I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
-       I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
-       POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
- 
-       spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
- }
- 
   static int
   __intel_display_resume(struct drm_device *dev,
                        struct drm_atomic_state *state,
@@@ -3701,7 -3595,7 +3595,7 @@@ void intel_prepare_reset(struct drm_i91
   
   
         /* reset doesn't touch the display */
-       if (!i915.force_reset_modeset_test &&
+       if (!i915_modparams.force_reset_modeset_test &&
             !gpu_reset_clobbers_display(dev_priv))
                 return;
   
@@@ -3757,7 -3651,7 +3651,7 @@@ void intel_finish_reset(struct drm_i915
         int ret;
   
         /* reset doesn't touch the display */
-       if (!i915.force_reset_modeset_test &&
+       if (!i915_modparams.force_reset_modeset_test &&
             !gpu_reset_clobbers_display(dev_priv))
                 return;
   
@@@ -3770,8 -3664,8 +3664,8 @@@
         if (!gpu_reset_clobbers_display(dev_priv)) {
                 /* for testing only restore the display */
                 ret = __intel_display_resume(dev, state, ctx);
-                       if (ret)
-                               DRM_ERROR("Restoring old state failed with %i\n", ret);
+               if (ret)
+                       DRM_ERROR("Restoring old state failed with %i\n", ret);
         } else {
                 /*
                  * The display has been reset as well,
@@@ -3782,6 -3676,7 +3676,7 @@@
   
                 intel_pps_unlock_regs_wa(dev_priv);
                 intel_modeset_init_hw(dev);
+               intel_init_clock_gating(dev_priv);
   
                 spin_lock_irq(&dev_priv->irq_lock);
                 if (dev_priv->display.hpd_irq_setup)
@@@ -3804,15 -3699,14 +3699,14 @@@ unlock
         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
   }
   
- static void intel_update_pipe_config(struct intel_crtc *crtc,
-                                    struct intel_crtc_state *old_crtc_state)
+ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
+                                    const struct intel_crtc_state *new_crtc_state)
   {
+       struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-       struct intel_crtc_state *pipe_config =
-               to_intel_crtc_state(crtc->base.state);
   
         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
-       crtc->base.mode = crtc->base.state->mode;
+       crtc->base.mode = new_crtc_state->base.mode;
   
         /*
          * Update pipe size and adjust fitter if needed: the reason for this is
@@@ -3824,17 -3718,17 +3718,17 @@@
          */
   
         I915_WRITE(PIPESRC(crtc->pipe),
-                  ((pipe_config->pipe_src_w - 1) << 16) |
-                  (pipe_config->pipe_src_h - 1));
+                  ((new_crtc_state->pipe_src_w - 1) << 16) |
+                  (new_crtc_state->pipe_src_h - 1));
   
         /* on skylake this is done by detaching scalers */
         if (INTEL_GEN(dev_priv) >= 9) {
                 skl_detach_scalers(crtc);
   
-               if (pipe_config->pch_pfit.enabled)
+               if (new_crtc_state->pch_pfit.enabled)
                         skylake_pfit_enable(crtc);
         } else if (HAS_PCH_SPLIT(dev_priv)) {
-               if (pipe_config->pch_pfit.enabled)
+               if (new_crtc_state->pch_pfit.enabled)
                         ironlake_pfit_enable(crtc);
                 else if (old_crtc_state->pch_pfit.enabled)
                         ironlake_pfit_disable(crtc, true);
@@@ -4956,9 -4850,10 +4850,10 @@@ void hsw_enable_ips(struct intel_crtc *
   
         assert_plane_enabled(dev_priv, crtc->plane);
         if (IS_BROADWELL(dev_priv)) {
-               mutex_lock(&dev_priv->rps.hw_lock);
-               WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
-               mutex_unlock(&dev_priv->rps.hw_lock);
+               mutex_lock(&dev_priv->pcu_lock);
+               WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
+                                               IPS_ENABLE | IPS_PCODE_CONTROL));
+               mutex_unlock(&dev_priv->pcu_lock);
                 /* Quoting Art Runyan: "its not safe to expect any particular
                  * value in IPS_CTL bit 31 after enabling IPS through the
                  * mailbox." Moreover, the mailbox may return a bogus state,
@@@ -4988,9 -4883,9 +4883,9 @@@ void hsw_disable_ips(struct intel_crtc 
   
         assert_plane_enabled(dev_priv, crtc->plane);
         if (IS_BROADWELL(dev_priv)) {
-               mutex_lock(&dev_priv->rps.hw_lock);
+               mutex_lock(&dev_priv->pcu_lock);
                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
-               mutex_unlock(&dev_priv->rps.hw_lock);
+               mutex_unlock(&dev_priv->pcu_lock);
                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
                 if (intel_wait_for_register(dev_priv,
                                             IPS_CTL, IPS_ENABLE, 0,
@@@ -5118,7 -5013,8 +5013,8 @@@ static void intel_post_plane_update(str
         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
         struct drm_atomic_state *old_state = old_crtc_state->base.state;
         struct intel_crtc_state *pipe_config =
-               to_intel_crtc_state(crtc->base.state);
+               intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
+                                               crtc);
         struct drm_plane *primary = crtc->base.primary;
         struct drm_plane_state *old_pri_state =
                 drm_atomic_get_existing_plane_state(old_state, primary);
@@@ -5130,7 -5026,8 +5026,8 @@@
   
         if (old_pri_state) {
                 struct intel_plane_state *primary_state =
-                       to_intel_plane_state(primary->state);
+                       intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
+                                                        to_intel_plane(primary));
                 struct intel_plane_state *old_primary_state =
                         to_intel_plane_state(old_pri_state);
   
@@@ -5159,7 -5056,8 +5056,8 @@@ static void intel_pre_plane_update(stru
   
         if (old_pri_state) {
                 struct intel_plane_state *primary_state =
-                       to_intel_plane_state(primary->state);
+                       intel_atomic_get_new_plane_state(old_intel_state,
+                                                        to_intel_plane(primary));
                 struct intel_plane_state *old_primary_state =
                         to_intel_plane_state(old_pri_state);
   
@@@ -5456,6 -5354,20 +5354,20 @@@ static bool hsw_crtc_supports_ips(struc
         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
   }
   
+ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
+                                           enum pipe pipe, bool apply)
+ {
+       u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
+       u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
+ 
+       if (apply)
+               val |= mask;
+       else
+               val &= ~mask;
+ 
+       I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
+ }
+ 
   static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
                                 struct drm_atomic_state *old_state)
   {
@@@ -5466,13 -5378,11 +5378,11 @@@
         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
         struct intel_atomic_state *old_intel_state =
                 to_intel_atomic_state(old_state);
+       bool psl_clkgate_wa;
   
         if (WARN_ON(intel_crtc->active))
                 return;
   
-       if (intel_crtc->config->has_pch_encoder)
-               intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
- 
         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
   
         if (intel_crtc->config->shared_dpll)
@@@ -5506,19 -5416,17 +5416,17 @@@
   
         intel_crtc->active = true;
   
-       if (intel_crtc->config->has_pch_encoder)
-               intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-       else
-               intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- 
         intel_encoders_pre_enable(crtc, pipe_config, old_state);
   
-       if (intel_crtc->config->has_pch_encoder)
-               dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
- 
         if (!transcoder_is_dsi(cpu_transcoder))
                 intel_ddi_enable_pipe_clock(pipe_config);
   
+       /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
+       psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
+                        intel_crtc->config->pch_pfit.enabled;
+       if (psl_clkgate_wa)
+               glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
+ 
         if (INTEL_GEN(dev_priv) >= 9)
                 skylake_pfit_enable(intel_crtc);
         else
@@@ -5552,11 -5460,9 +5460,9 @@@
   
         intel_encoders_enable(crtc, pipe_config, old_state);
   
-       if (intel_crtc->config->has_pch_encoder) {
-               intel_wait_for_vblank(dev_priv, pipe);
+       if (psl_clkgate_wa) {
                 intel_wait_for_vblank(dev_priv, pipe);
-               intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-               intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+               glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
         }
   
         /* If we change the relative order between pipe/planes enabling, we need
@@@ -5652,9 -5558,6 +5558,6 @@@ static void haswell_crtc_disable(struc
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
   
-       if (intel_crtc->config->has_pch_encoder)
-               intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
- 
         intel_encoders_disable(crtc, old_crtc_state, old_state);
   
         drm_crtc_vblank_off(crtc);
@@@ -5679,9 -5582,6 +5582,6 @@@
                 intel_ddi_disable_pipe_clock(intel_crtc->config);
   
         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
- 
-       if (old_crtc_state->has_pch_encoder)
-               intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
   }
   
   static void i9xx_pfit_enable(struct intel_crtc *crtc)
@@@ -5891,7 -5791,7 +5791,7 @@@ static void i9xx_crtc_enable(struct int
   
         intel_encoders_pre_enable(crtc, pipe_config, old_state);
   
-       i9xx_enable_pll(intel_crtc);
+       i9xx_enable_pll(intel_crtc, pipe_config);
   
         i9xx_pfit_enable(intel_crtc);
   
@@@ -6038,7 -5938,7 +5938,7 @@@ static void intel_crtc_disable_noatomic
         intel_crtc->enabled_power_domains = 0;
   
         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
-       dev_priv->min_pixclk[intel_crtc->pipe] = 0;
+       dev_priv->min_cdclk[intel_crtc->pipe] = 0;
   }
   
   /*
@@@ -6143,6 -6043,19 +6043,19 @@@ struct intel_connector *intel_connector
         return connector;
   }
   
+ /*
+  * Free the bits allocated by intel_connector_alloc.
+  * This should only be used after intel_connector_alloc has returned
+  * successfully, and before drm_connector_init returns successfully.
+  * Otherwise the destroy callbacks for the connector and the state should
+  * take care of proper cleanup/free
+  */
+ void intel_connector_free(struct intel_connector *connector)
+ {
+       kfree(to_intel_digital_connector_state(connector->base.state));
+       kfree(connector);
+ }
+ 
   /* Simple connector->get_hw_state implementation for encoders that support only
    * one connector and no cloning and hence the encoder state determines the state
    * of the connector. */
@@@ -6283,6 -6196,9 +6196,9 @@@ retry
   static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
                                      struct intel_crtc_state *pipe_config)
   {
+       if (pipe_config->ips_force_disable)
+               return false;
+ 
         if (pipe_config->pipe_bpp > 24)
                 return false;
   
@@@ -6307,7 -6223,7 +6223,7 @@@ static void hsw_compute_ips_config(stru
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
   
-       pipe_config->ips_enabled = i915.enable_ips &&
+       pipe_config->ips_enabled = i915_modparams.enable_ips &&
                 hsw_crtc_supports_ips(crtc) &&
                 pipe_config_supports_ips(dev_priv, pipe_config);
   }
@@@ -6488,8 -6404,8 +6404,8 @@@ intel_link_compute_m_n(int bits_per_pix
   
   static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
   {
-       if (i915.panel_use_ssc >= 0)
-               return i915.panel_use_ssc != 0;
+       if (i915_modparams.panel_use_ssc >= 0)
+               return i915_modparams.panel_use_ssc != 0;
         return dev_priv->vbt.lvds_use_ssc
                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
   }
@@@ -6523,11 -6439,9 +6439,9 @@@ static void i9xx_update_pll_dividers(st
   
         crtc_state->dpll_hw_state.fp0 = fp;
   
-       crtc->lowfreq_avail = false;
         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
             reduced_clock) {
                 crtc_state->dpll_hw_state.fp1 = fp2;
-               crtc->lowfreq_avail = true;
         } else {
                 crtc_state->dpll_hw_state.fp1 = fp;
         }
@@@ -7222,15 -7136,6 +7136,6 @@@ static void i9xx_set_pipeconf(struct in
                 }
         }
   
-       if (HAS_PIPE_CXSR(dev_priv)) {
-               if (intel_crtc->lowfreq_avail) {
-                       DRM_DEBUG_KMS("enabling CxSR downclocking\n");
-                       pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
-               } else {
-                       DRM_DEBUG_KMS("disabling CxSR downclocking\n");
-               }
-       }
- 
         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
                 if (INTEL_GEN(dev_priv) < 4 ||
                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
@@@ -8366,8 -8271,6 +8271,6 @@@ static int ironlake_crtc_compute_clock(
         memset(&crtc_state->dpll_hw_state, 0,
                sizeof(crtc_state->dpll_hw_state));
   
-       crtc->lowfreq_avail = false;
- 
         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
         if (!crtc_state->has_pch_encoder)
                 return 0;
@@@ -8840,11 -8743,11 +8743,11 @@@ static uint32_t hsw_read_dcomp(struct d
   static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
   {
         if (IS_HASWELL(dev_priv)) {
-               mutex_lock(&dev_priv->rps.hw_lock);
+               mutex_lock(&dev_priv->pcu_lock);
                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
                                             val))
                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
-               mutex_unlock(&dev_priv->rps.hw_lock);
+               mutex_unlock(&dev_priv->pcu_lock);
         } else {
                 I915_WRITE(D_COMP_BDW, val);
                 POSTING_READ(D_COMP_BDW);
@@@ -9026,8 -8929,6 +8929,6 @@@ static int haswell_crtc_compute_clock(s
                 }
         }
   
-       crtc->lowfreq_avail = false;
- 
         return 0;
   }
   
@@@ -9039,7 -8940,7 +8940,7 @@@ static void cannonlake_get_ddi_pll(stru
         u32 temp;
   
         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-       id = temp >> (port * 2);
+       id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
   
         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
                 return;
@@@ -9304,11 -9205,11 +9205,11 @@@ static bool haswell_get_pipe_config(str
         pipe_config->gamma_mode =
                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
   
-       if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
+       if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
   
-               if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
+               if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
                         bool blend_mode_420 = tmp &
                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
   
@@@ -9753,7 -9654,7 +9654,7 @@@ static void i9xx_disable_cursor(struct 
   
   
   /* VESA 640x480x72Hz mode to set on the pipe */
- static struct drm_display_mode load_detect_mode = {
+ static const struct drm_display_mode load_detect_mode = {
         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
   };
@@@ -9788,7 -9689,7 +9689,7 @@@ intel_framebuffer_pitch_for_width(int w
   }
   
   static u32
- intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
+ intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
   {
         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
         return PAGE_ALIGN(pitch * mode->vdisplay);
@@@ -9796,7 -9697,7 +9697,7 @@@
   
   static struct drm_framebuffer *
   intel_framebuffer_create_for_mode(struct drm_device *dev,
-                                 struct drm_display_mode *mode,
+                                 const struct drm_display_mode *mode,
                                   int depth, int bpp)
   {
         struct drm_framebuffer *fb;
@@@ -9823,7 -9724,7 +9724,7 @@@
   
   static struct drm_framebuffer *
   mode_fits_in_fbdev(struct drm_device *dev,
-                  struct drm_display_mode *mode)
+                  const struct drm_display_mode *mode)
   {
   #ifdef CONFIG_DRM_FBDEV_EMULATION
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -9847,7 -9748,7 +9748,7 @@@
         if (obj->base.size < mode->vdisplay * fb->pitches[0])
                 return NULL;
   
-       drm_framebuffer_reference(fb);
+       drm_framebuffer_get(fb);
         return fb;
   #else
         return NULL;
@@@ -9856,7 -9757,7 +9757,7 @@@
   
   static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
                                            struct drm_crtc *crtc,
-                                          struct drm_display_mode *mode,
+                                          const struct drm_display_mode *mode,
                                            struct drm_framebuffer *fb,
                                            int x, int y)
   {
@@@ -9890,7 -9791,7 +9791,7 @@@
   }
   
   int intel_get_load_detect_pipe(struct drm_connector *connector,
-                              struct drm_display_mode *mode,
+                              const struct drm_display_mode *mode,
                                struct intel_load_detect_pipe *old,
                                struct drm_modeset_acquire_ctx *ctx)
   {
@@@ -10028,7 -9929,7 +9929,7 @@@ found
         if (ret)
                 goto fail;
   
-       drm_framebuffer_unreference(fb);
+       drm_framebuffer_put(fb);
   
         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
         if (ret)
@@@ -10218,7 -10119,7 +10119,7 @@@ int intel_dotclock_calculate(int link_f
         if (!m_n->link_n)
                 return 0;
   
-       return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
+       return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
   }
   
   static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@@ -10239,62 -10140,44 +10140,44 @@@
                                          &pipe_config->fdi_m_n);
   }
   
- /** Returns the currently programmed mode of the given pipe. */
- struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
-                                            struct drm_crtc *crtc)
+ /* Returns the currently programmed mode of the given encoder. */
+ struct drm_display_mode *
+ intel_encoder_current_mode(struct intel_encoder *encoder)
   {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       enum transcoder cpu_transcoder;
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc_state *crtc_state;
         struct drm_display_mode *mode;
-       struct intel_crtc_state *pipe_config;
-       u32 htot, hsync, vtot, vsync;
-       enum pipe pipe = intel_crtc->pipe;
+       struct intel_crtc *crtc;
+       enum pipe pipe;
+ 
+       if (!encoder->get_hw_state(encoder, &pipe))
+               return NULL;
+ 
+       crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
   
         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
         if (!mode)
                 return NULL;
   
-       pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
-       if (!pipe_config) {
+       crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+       if (!crtc_state) {
                 kfree(mode);
                 return NULL;
         }
   
-       /*
-        * Construct a pipe_config sufficient for getting the clock info
-        * back out of crtc_clock_get.
-        *
-        * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
-        * to use a real value here instead.
-        */
-       pipe_config->cpu_transcoder = (enum transcoder) pipe;
-       pipe_config->pixel_multiplier = 1;
-       pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
-       pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
-       pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
-       i9xx_crtc_clock_get(intel_crtc, pipe_config);
- 
-       mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
- 
-       cpu_transcoder = pipe_config->cpu_transcoder;
-       htot = I915_READ(HTOTAL(cpu_transcoder));
-       hsync = I915_READ(HSYNC(cpu_transcoder));
-       vtot = I915_READ(VTOTAL(cpu_transcoder));
-       vsync = I915_READ(VSYNC(cpu_transcoder));
- 
-       mode->hdisplay = (htot & 0xffff) + 1;
-       mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
-       mode->hsync_start = (hsync & 0xffff) + 1;
-       mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
-       mode->vdisplay = (vtot & 0xffff) + 1;
-       mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
-       mode->vsync_start = (vsync & 0xffff) + 1;
-       mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
+       crtc_state->base.crtc = &crtc->base;
   
-       drm_mode_set_name(mode);
+       if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
+               kfree(crtc_state);
+               kfree(mode);
+               return NULL;
+       }
   
-       kfree(pipe_config);
+       encoder->get_config(encoder, crtc_state);
+ 
+       intel_mode_from_pipe_config(mode, crtc_state);
+ 
+       kfree(crtc_state);
   
         return mode;
   }
@@@ -10341,7 -10224,7 +10224,7 @@@ static bool intel_wm_need_update(struc
         return false;
   }
   
- static bool needs_scaling(struct intel_plane_state *state)
+ static bool needs_scaling(const struct intel_plane_state *state)
   {
         int src_w = drm_rect_width(&state->base.src) >> 16;
         int src_h = drm_rect_height(&state->base.src) >> 16;
@@@ -10351,7 -10234,9 +10234,9 @@@
         return (src_w != dst_w || src_h != dst_h);
   }
   
- int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
+ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
+                                   struct drm_crtc_state *crtc_state,
+                                   const struct intel_plane_state *old_plane_state,
                                     struct drm_plane_state *plane_state)
   {
         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
@@@ -10360,10 -10245,8 +10245,8 @@@
         struct intel_plane *plane = to_intel_plane(plane_state->plane);
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_plane_state *old_plane_state =
-               to_intel_plane_state(plane->base.state);
         bool mode_changed = needs_modeset(crtc_state);
-       bool was_crtc_enabled = crtc->state->active;
+       bool was_crtc_enabled = old_crtc_state->base.active;
         bool is_crtc_enabled = crtc_state->active;
         bool turn_off, turn_on, visible, was_visible;
         struct drm_framebuffer *fb = plane_state->fb;
@@@ -10681,6 -10564,52 +10564,52 @@@ intel_dump_m_n_config(struct intel_crtc
                       m_n->link_m, m_n->link_n, m_n->tu);
   }
   
+ #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
+ 
+ static const char * const output_type_str[] = {
+       OUTPUT_TYPE(UNUSED),
+       OUTPUT_TYPE(ANALOG),
+       OUTPUT_TYPE(DVO),
+       OUTPUT_TYPE(SDVO),
+       OUTPUT_TYPE(LVDS),
+       OUTPUT_TYPE(TVOUT),
+       OUTPUT_TYPE(HDMI),
+       OUTPUT_TYPE(DP),
+       OUTPUT_TYPE(EDP),
+       OUTPUT_TYPE(DSI),
+       OUTPUT_TYPE(UNKNOWN),
+       OUTPUT_TYPE(DP_MST),
+ };
+ 
+ #undef OUTPUT_TYPE
+ 
+ static void snprintf_output_types(char *buf, size_t len,
+                                 unsigned int output_types)
+ {
+       char *str = buf;
+       int i;
+ 
+       str[0] = '\0';
+ 
+       for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
+               int r;
+ 
+               if ((output_types & BIT(i)) == 0)
+                       continue;
+ 
+               r = snprintf(str, len, "%s%s",
+                            str != buf ? "," : "", output_type_str[i]);
+               if (r >= len)
+                       break;
+               str += r;
+               len -= r;
+ 
+               output_types &= ~BIT(i);
+       }
+ 
+       WARN_ON_ONCE(output_types != 0);
+ }
+ 
   static void intel_dump_pipe_config(struct intel_crtc *crtc,
                                    struct intel_crtc_state *pipe_config,
                                    const char *context)
@@@ -10691,10 -10620,15 +10620,15 @@@
         struct intel_plane *intel_plane;
         struct intel_plane_state *state;
         struct drm_framebuffer *fb;
+       char buf[64];
   
         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
                       crtc->base.base.id, crtc->base.name, context);
   
+       snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
+       DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
+                     buf, pipe_config->output_types);
+ 
         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
                       transcoder_name(pipe_config->cpu_transcoder),
                       pipe_config->pipe_bpp, pipe_config->dither);
@@@ -10854,7 -10788,7 +10788,7 @@@ clear_intel_crtc_state(struct intel_crt
         struct intel_dpll_hw_state dpll_hw_state;
         struct intel_shared_dpll *shared_dpll;
         struct intel_crtc_wm_state wm_state;
-       bool force_thru;
+       bool force_thru, ips_force_disable;
   
         /* FIXME: before the switch to atomic started, a new pipe_config was
          * kzalloc'd. Code that depends on any field being zero should be
@@@ -10865,6 -10799,7 +10799,7 @@@
         shared_dpll = crtc_state->shared_dpll;
         dpll_hw_state = crtc_state->dpll_hw_state;
         force_thru = crtc_state->pch_pfit.force_thru;
+       ips_force_disable = crtc_state->ips_force_disable;
         if (IS_G4X(dev_priv) ||
             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                 wm_state = crtc_state->wm;
@@@ -10878,6 -10813,7 +10813,7 @@@
         crtc_state->shared_dpll = shared_dpll;
         crtc_state->dpll_hw_state = dpll_hw_state;
         crtc_state->pch_pfit.force_thru = force_thru;
+       crtc_state->ips_force_disable = ips_force_disable;
         if (IS_G4X(dev_priv) ||
             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                 crtc_state->wm = wm_state;
@@@ -11332,6 -11268,18 +11268,18 @@@ intel_pipe_config_compare(struct drm_i9
         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+       PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
+       PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+       PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+       PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
   
         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
         PIPE_CONF_CHECK_X(dsi_pll.div);
@@@ -12080,7 -12028,7 +12028,7 @@@ static int intel_atomic_check(struct dr
                         return ret;
                 }
   
-               if (i915.fastboot &&
+               if (i915_modparams.fastboot &&
                     intel_pipe_config_compare(dev_priv,
                                         to_intel_crtc_state(old_crtc_state),
                                         pipe_config, true)) {
@@@ -12133,73 -12081,10 +12081,10 @@@ u32 intel_crtc_get_vblank_counter(struc
         return dev->driver->get_vblank_counter(dev, crtc->pipe);
   }
   
- static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
-                                         struct drm_i915_private *dev_priv,
-                                         unsigned crtc_mask)
- {
-       unsigned last_vblank_count[I915_MAX_PIPES];
-       enum pipe pipe;
-       int ret;
- 
-       if (!crtc_mask)
-               return;
- 
-       for_each_pipe(dev_priv, pipe) {
-               struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
-                                                                 pipe);
- 
-               if (!((1 << pipe) & crtc_mask))
-                       continue;
- 
-               ret = drm_crtc_vblank_get(&crtc->base);
-               if (WARN_ON(ret != 0)) {
-                       crtc_mask &= ~(1 << pipe);
-                       continue;
-               }
- 
-               last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
-       }
- 
-       for_each_pipe(dev_priv, pipe) {
-               struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
-                                                                 pipe);
-               long lret;
- 
-               if (!((1 << pipe) & crtc_mask))
-                       continue;
- 
-               lret = wait_event_timeout(dev->vblank[pipe].queue,
-                               last_vblank_count[pipe] !=
-                                       drm_crtc_vblank_count(&crtc->base),
-                               msecs_to_jiffies(50));
- 
-               WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
- 
-               drm_crtc_vblank_put(&crtc->base);
-       }
- }
- 
- static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
- {
-       /* fb updated, need to unpin old fb */
-       if (crtc_state->fb_changed)
-               return true;
- 
-       /* wm changes, need vblank before final wm's */
-       if (crtc_state->update_wm_post)
-               return true;
- 
-       if (crtc_state->wm.need_postvbl_update)
-               return true;
- 
-       return false;
- }
- 
   static void intel_update_crtc(struct drm_crtc *crtc,
                               struct drm_atomic_state *state,
                               struct drm_crtc_state *old_crtc_state,
-                             struct drm_crtc_state *new_crtc_state,
-                             unsigned int *crtc_vblank_mask)
+                             struct drm_crtc_state *new_crtc_state)
   {
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -12222,13 -12107,9 +12107,9 @@@
         }
   
         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
- 
-       if (needs_vblank_wait(pipe_config))
-               *crtc_vblank_mask |= drm_crtc_mask(crtc);
   }
   
- static void intel_update_crtcs(struct drm_atomic_state *state,
-                              unsigned int *crtc_vblank_mask)
+ static void intel_update_crtcs(struct drm_atomic_state *state)
   {
         struct drm_crtc *crtc;
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
@@@ -12239,12 -12120,11 +12120,11 @@@
                         continue;
   
                 intel_update_crtc(crtc, state, old_crtc_state,
-                                 new_crtc_state, crtc_vblank_mask);
+                                 new_crtc_state);
         }
   }
   
- static void skl_update_crtcs(struct drm_atomic_state *state,
-                            unsigned int *crtc_vblank_mask)
+ static void skl_update_crtcs(struct drm_atomic_state *state)
   {
         struct drm_i915_private *dev_priv = to_i915(state->dev);
         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
@@@ -12278,13 -12158,16 +12158,16 @@@
                         unsigned int cmask = drm_crtc_mask(crtc);
   
                         intel_crtc = to_intel_crtc(crtc);
-                       cstate = to_intel_crtc_state(crtc->state);
+                       cstate = to_intel_crtc_state(new_crtc_state);
                         pipe = intel_crtc->pipe;
   
                         if (updated & cmask || !cstate->base.active)
                                 continue;
   
-                       if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
+                       if (skl_ddb_allocation_overlaps(dev_priv,
+                                                       entries,
+                                                       &cstate->wm.skl.ddb,
+                                                       i))
                                 continue;
   
                         updated |= cmask;
@@@ -12303,7 -12186,7 +12186,7 @@@
                                 vbl_wait = true;
   
                         intel_update_crtc(crtc, state, old_crtc_state,
-                                         new_crtc_state, crtc_vblank_mask);
+                                         new_crtc_state);
   
                         if (vbl_wait)
                                 intel_wait_for_vblank(dev_priv, pipe);
@@@ -12364,7 -12247,6 +12247,6 @@@ static void intel_atomic_commit_tail(st
         struct drm_crtc *crtc;
         struct intel_crtc_state *intel_cstate;
         u64 put_domains[I915_MAX_PIPES] = {};
-       unsigned crtc_vblank_mask = 0;
         int i;
   
         intel_atomic_commit_fence_wait(intel_state);
@@@ -12405,7 -12287,7 +12287,7 @@@
                         intel_check_cpu_fifo_underruns(dev_priv);
                         intel_check_pch_fifo_underruns(dev_priv);
   
-                       if (!crtc->state->active) {
+                       if (!new_crtc_state->active) {
                                 /*
                                  * Make sure we don't call initial_watermarks
                                  * for ILK-style watermark updates.
@@@ -12414,7 -12296,7 +12296,7 @@@
                                  */
                                 if (INTEL_GEN(dev_priv) >= 9)
                                         dev_priv->display.initial_watermarks(intel_state,
-                                                                            to_intel_crtc_state(crtc->state));
+                                                                            to_intel_crtc_state(new_crtc_state));
                         }
                 }
         }
@@@ -12453,7 -12335,7 +12335,7 @@@
         }
   
         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
-       dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
+       dev_priv->display.update_crtcs(state);
   
         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
          * already, but still need the state for the delayed optimization. To
@@@ -12464,8 -12346,7 +12346,7 @@@
          * - switch over to the vblank wait helper in the core after that since
          *   we don't need out special handling any more.
          */
-       if (!state->legacy_cursor_update)
-               intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
+       drm_atomic_helper_wait_for_flip_done(dev, state);
   
         /*
          * Now that the vblank has passed, we can go ahead and program the
@@@ -12581,21 -12462,10 +12462,10 @@@ static int intel_atomic_commit(struct d
         struct drm_i915_private *dev_priv = to_i915(dev);
         int ret = 0;
   
-       ret = drm_atomic_helper_setup_commit(state, nonblock);
-       if (ret)
-               return ret;
- 
         drm_atomic_state_get(state);
         i915_sw_fence_init(&intel_state->commit_ready,
                            intel_atomic_commit_ready);
   
-       ret = intel_atomic_prepare_commit(dev, state);
-       if (ret) {
-               DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
-               i915_sw_fence_commit(&intel_state->commit_ready);
-               return ret;
-       }
- 
         /*
          * The intel_legacy_cursor_update() fast path takes care
          * of avoiding the vblank waits for simple cursor
@@@ -12604,19 -12474,37 +12474,37 @@@
          * updates happen during the correct frames. Gen9+ have
          * double buffered watermarks and so shouldn't need this.
          *
-        * Do this after drm_atomic_helper_setup_commit() and
-        * intel_atomic_prepare_commit() because we still want
-        * to skip the flip and fb cleanup waits. Although that
-        * does risk yanking the mapping from under the display
-        * engine.
+        * Unset state->legacy_cursor_update before the call to
+        * drm_atomic_helper_setup_commit() because otherwise
+        * drm_atomic_helper_wait_for_flip_done() is a noop and
+        * we get FIFO underruns because we didn't wait
+        * for vblank.
          *
          * FIXME doing watermarks and fb cleanup from a vblank worker
          * (assuming we had any) would solve these problems.
          */
-       if (INTEL_GEN(dev_priv) < 9)
-               state->legacy_cursor_update = false;
+       if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
+               struct intel_crtc_state *new_crtc_state;
+               struct intel_crtc *crtc;
+               int i;
+ 
+               for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
+                       if (new_crtc_state->wm.need_postvbl_update ||
+                           new_crtc_state->update_wm_post)
+                               state->legacy_cursor_update = false;
+       }
+ 
+       ret = intel_atomic_prepare_commit(dev, state);
+       if (ret) {
+               DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
+               i915_sw_fence_commit(&intel_state->commit_ready);
+               return ret;
+       }
+ 
+       ret = drm_atomic_helper_setup_commit(state, nonblock);
+       if (!ret)
+               ret = drm_atomic_helper_swap_state(state, true);
   
-       ret = drm_atomic_helper_swap_state(state, true);
         if (ret) {
                 i915_sw_fence_commit(&intel_state->commit_ready);
   
@@@ -12628,8 -12516,8 +12516,8 @@@
         intel_atomic_track_fbs(state);
   
         if (intel_state->modeset) {
-               memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
-                      sizeof(intel_state->min_pixclk));
+               memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
+                      sizeof(intel_state->min_cdclk));
                 dev_priv->active_crtcs = intel_state->active_crtcs;
                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
@@@ -12658,6 -12546,58 +12546,58 @@@ static const struct drm_crtc_funcs inte
         .set_crc_source = intel_crtc_set_crc_source,
   };
   
+ struct wait_rps_boost {
+       struct wait_queue_entry wait;
+ 
+       struct drm_crtc *crtc;
+       struct drm_i915_gem_request *request;
+ };
+ 
+ static int do_rps_boost(struct wait_queue_entry *_wait,
+                       unsigned mode, int sync, void *key)
+ {
+       struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
+       struct drm_i915_gem_request *rq = wait->request;
+ 
+       gen6_rps_boost(rq, NULL);
+       i915_gem_request_put(rq);
+ 
+       drm_crtc_vblank_put(wait->crtc);
+ 
+       list_del(&wait->wait.entry);
+       kfree(wait);
+       return 1;
+ }
+ 
+ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
+                                      struct dma_fence *fence)
+ {
+       struct wait_rps_boost *wait;
+ 
+       if (!dma_fence_is_i915(fence))
+               return;
+ 
+       if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+               return;
+ 
+       if (drm_crtc_vblank_get(crtc))
+               return;
+ 
+       wait = kmalloc(sizeof(*wait), GFP_KERNEL);
+       if (!wait) {
+               drm_crtc_vblank_put(crtc);
+               return;
+       }
+ 
+       wait->request = to_request(dma_fence_get(fence));
+       wait->crtc = crtc;
+ 
+       wait->wait.func = do_rps_boost;
+       wait->wait.flags = 0;
+ 
+       add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
+ }
+ 
   /**
    * intel_prepare_plane_fb - Prepare fb for usage on plane
    * @plane: drm plane to prepare for
@@@ -12755,12 -12695,22 +12695,22 @@@ intel_prepare_plane_fb(struct drm_plan
                 return ret;
   
         if (!new_state->fence) { /* implicit fencing */
+               struct dma_fence *fence;
+ 
                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
                                                       obj->resv, NULL,
                                                       false, I915_FENCE_TIMEOUT,
                                                       GFP_KERNEL);
                 if (ret < 0)
                         return ret;
+ 
+               fence = reservation_object_get_excl_rcu(obj->resv);
+               if (fence) {
+                       add_rps_boost_after_vblank(new_state->crtc, fence);
+                       dma_fence_put(fence);
+               }
+       } else {
+               add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
         }
   
         return 0;
@@@ -12877,29 -12827,29 +12827,29 @@@ static void intel_begin_crtc_commit(str
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       struct intel_crtc_state *intel_cstate =
-               to_intel_crtc_state(crtc->state);
         struct intel_crtc_state *old_intel_cstate =
                 to_intel_crtc_state(old_crtc_state);
         struct intel_atomic_state *old_intel_state =
                 to_intel_atomic_state(old_crtc_state->state);
-       bool modeset = needs_modeset(crtc->state);
+       struct intel_crtc_state *intel_cstate =
+               intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
+       bool modeset = needs_modeset(&intel_cstate->base);
   
         if (!modeset &&
             (intel_cstate->base.color_mgmt_changed ||
              intel_cstate->update_pipe)) {
-               intel_color_set_csc(crtc->state);
-               intel_color_load_luts(crtc->state);
+               intel_color_set_csc(&intel_cstate->base);
+               intel_color_load_luts(&intel_cstate->base);
         }
   
         /* Perform vblank evasion around commit operation */
-       intel_pipe_update_start(intel_crtc);
+       intel_pipe_update_start(intel_cstate);
   
         if (modeset)
                 goto out;
   
         if (intel_cstate->update_pipe)
-               intel_update_pipe_config(intel_crtc, old_intel_cstate);
+               intel_update_pipe_config(old_intel_cstate, intel_cstate);
         else if (INTEL_GEN(dev_priv) >= 9)
                 skl_detach_scalers(intel_crtc);
   
@@@ -12913,8 -12863,12 +12863,12 @@@ static void intel_finish_crtc_commit(st
                                      struct drm_crtc_state *old_crtc_state)
   {
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       struct intel_atomic_state *old_intel_state =
+               to_intel_atomic_state(old_crtc_state->state);
+       struct intel_crtc_state *new_crtc_state =
+               intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
   
-       intel_pipe_update_end(intel_crtc);
+       intel_pipe_update_end(new_crtc_state);
   }
   
   /**
@@@ -13063,6 -13017,14 +13017,14 @@@ intel_legacy_cursor_update(struct drm_p
                 goto slow;
   
         old_plane_state = plane->state;
+       /*
+        * Don't do an async update if there is an outstanding commit modifying
+        * the plane.  This prevents our async update's changes from getting
+        * overridden by a previous synchronous update's state.
+        */
+       if (old_plane_state->commit &&
+           !try_wait_for_completion(&old_plane_state->commit->hw_done))
+               goto slow;
   
         /*
          * If any parameters change that may affect watermarks,
@@@ -13093,6 -13055,8 +13055,8 @@@
         new_plane_state->crtc_h = crtc_h;
   
         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
+                                                 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
+                                                 to_intel_plane_state(plane->state),
                                                   to_intel_plane_state(new_plane_state));
         if (ret)
                 goto out_free;
@@@ -13122,17 -13086,12 +13086,12 @@@
         }
   
         old_fb = old_plane_state->fb;
-       old_vma = to_intel_plane_state(old_plane_state)->vma;
   
         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
                           intel_plane->frontbuffer_bit);
   
         /* Swap plane state */
-       new_plane_state->fence = old_plane_state->fence;
-       *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
-       new_plane_state->fence = NULL;
-       new_plane_state->fb = old_fb;
-       to_intel_plane_state(new_plane_state)->vma = NULL;
+       plane->state = new_plane_state;
   
         if (plane->state->visible) {
                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
@@@ -13144,13 -13103,17 +13103,17 @@@
                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
         }
   
+       old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
         if (old_vma)
                 intel_unpin_fb_vma(old_vma);
   
   out_unlock:
         mutex_unlock(&dev_priv->drm.struct_mutex);
   out_free:
-       intel_plane_destroy_state(plane, new_plane_state);
+       if (ret)
+               intel_plane_destroy_state(plane, new_plane_state);
+       else
+               intel_plane_destroy_state(plane, old_plane_state);
         return ret;
   
   slow:
@@@ -13219,8 -13182,8 +13182,8 @@@ intel_primary_plane_create(struct drm_i
                 num_formats = ARRAY_SIZE(skl_primary_formats);
                 modifiers = skl_format_modifiers_ccs;
   
-               primary->update_plane = skylake_update_primary_plane;
-               primary->disable_plane = skylake_disable_primary_plane;
+               primary->update_plane = skl_update_plane;
+               primary->disable_plane = skl_disable_plane;
         } else if (INTEL_GEN(dev_priv) >= 9) {
                 intel_primary_formats = skl_primary_formats;
                 num_formats = ARRAY_SIZE(skl_primary_formats);
@@@ -13229,8 -13192,8 +13192,8 @@@
                 else
                         modifiers = skl_format_modifiers_noccs;
   
-               primary->update_plane = skylake_update_primary_plane;
-               primary->disable_plane = skylake_disable_primary_plane;
+               primary->update_plane = skl_update_plane;
+               primary->disable_plane = skl_disable_plane;
         } else if (INTEL_GEN(dev_priv) >= 4) {
                 intel_primary_formats = i965_primary_formats;
                 num_formats = ARRAY_SIZE(i965_primary_formats);
@@@ -13501,7 -13464,7 +13464,7 @@@ int intel_get_pipe_from_crtc_id(struct 
         struct drm_crtc *drmmode_crtc;
         struct intel_crtc *crtc;
   
-       drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
+       drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
         if (!drmmode_crtc)
                 return -ENOENT;
   
@@@ -13665,7 -13628,7 +13628,7 @@@ static void intel_setup_outputs(struct 
   
         } else if (HAS_PCH_SPLIT(dev_priv)) {
                 int found;
-               dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
+               dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
   
                 if (has_edp_a(dev_priv))
                         intel_dp_init(dev_priv, DP_A, PORT_A);
@@@ -13708,14 -13671,14 +13671,14 @@@
                  * trust the port type the VBT declares as we've seen at least
                  * HDMI ports that the VBT claim are DP or eDP.
                  */
-               has_edp = intel_dp_is_edp(dev_priv, PORT_B);
+               has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
   
-               has_edp = intel_dp_is_edp(dev_priv, PORT_C);
+               has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
@@@ -14208,7 -14171,7 +14171,7 @@@ void intel_init_display_hooks(struct dr
                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
         }
   
-       if (dev_priv->info.gen >= 9)
+       if (INTEL_GEN(dev_priv) >= 9)
                 dev_priv->display.update_crtcs = skl_update_crtcs;
         else
                 dev_priv->display.update_crtcs = intel_update_crtcs;
@@@ -14388,8 -14351,6 +14351,6 @@@ void intel_modeset_init_hw(struct drm_d
   
         intel_update_cdclk(dev_priv);
         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
- 
-       intel_init_clock_gating(dev_priv);
   }
   
   /*
@@@ -14739,10 -14700,10 +14700,10 @@@ static struct intel_connector *intel_en
   }
   
   static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
-                             enum transcoder pch_transcoder)
+                             enum pipe pch_transcoder)
   {
         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-               (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
+               (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
   }
   
   static void intel_sanitize_crtc(struct intel_crtc *crtc,
@@@ -14825,7 -14786,7 +14786,7 @@@
                  * PCH transcoders B and C would prevent enabling the south
                  * error interrupt (see cpt_can_enable_serr_int()).
                  */
-               if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
+               if (has_pch_trancoder(dev_priv, crtc->pipe))
                         crtc->pch_fifo_underrun_disabled = true;
         }
   }
@@@ -15032,7 -14993,7 +14993,7 @@@ static void intel_modeset_readout_hw_st
         for_each_intel_crtc(dev, crtc) {
                 struct intel_crtc_state *crtc_state =
                         to_intel_crtc_state(crtc->base.state);
-               int pixclk = 0;
+               int min_cdclk = 0;
   
                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
                 if (crtc_state->base.active) {
@@@ -15053,22 -15014,18 +15014,18 @@@
   
                         intel_crtc_compute_pixel_rate(crtc_state);
   
-                       if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
-                           IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-                               pixclk = crtc_state->pixel_rate;
-                       else
-                               WARN_ON(dev_priv->display.modeset_calc_cdclk);
- 
-                       /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-                       if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
-                               pixclk = DIV_ROUND_UP(pixclk * 100, 95);
+                       if (dev_priv->display.modeset_calc_cdclk) {
+                               min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
+                               if (WARN_ON(min_cdclk < 0))
+                                       min_cdclk = 0;
+                       }
   
                         drm_calc_timestamping_constants(&crtc->base,
                                                         &crtc_state->base.adjusted_mode);
                         update_scanline_offset(crtc);
                 }
   
-               dev_priv->min_pixclk[crtc->pipe] = pixclk;
+               dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
   
                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
         }
@@@ -15105,6 -15062,15 +15062,15 @@@ intel_modeset_setup_hw_state(struct drm
         struct intel_encoder *encoder;
         int i;
   
+       if (IS_HASWELL(dev_priv)) {
+               /*
+                * WaRsPkgCStateDisplayPMReq:hsw
+                * System hang if this isn't done before disabling all planes!
+                */
+               I915_WRITE(CHICKEN_PAR1_1,
+                          I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+       }
+ 
         intel_modeset_readout_hw_state(dev);
   
         /* HW state is read out, now we need to sanitize this mess. */
@@@ -15186,6 -15152,7 +15152,7 @@@ void intel_display_resume(struct drm_de
         if (!ret)
                 ret = __intel_display_resume(dev, state, &ctx);
   
+       intel_enable_ipc(dev_priv);
         drm_modeset_drop_locks(&ctx);
         drm_modeset_acquire_fini(&ctx);
   
@@@ -15201,6 -15168,8 +15168,8 @@@ void intel_modeset_gem_init(struct drm_
   
         intel_init_gt_powersave(dev_priv);
   
+       intel_init_clock_gating(dev_priv);
+ 
         intel_setup_overlay(dev_priv);
   }
   
@@@ -15227,23 -15196,6 +15196,23 @@@ void intel_connector_unregister(struct 
         intel_panel_destroy_backlight(connector);
   }
   
+ +static void intel_hpd_poll_fini(struct drm_device *dev)
+ +{
+ +      struct intel_connector *connector;
+ +      struct drm_connector_list_iter conn_iter;
+ +
+ +      /* First disable polling... */
+ +      drm_kms_helper_poll_fini(dev);
+ +
+ +      /* Then kill the work that may have been queued by hpd. */
+ +      drm_connector_list_iter_begin(dev, &conn_iter);
+ +      for_each_intel_connector_iter(connector, &conn_iter) {
+ +              if (connector->modeset_retry_work.func)
+ +                      cancel_work_sync(&connector->modeset_retry_work);
+ +      }
+ +      drm_connector_list_iter_end(&conn_iter);
+ +}
+ +
   void intel_modeset_cleanup(struct drm_device *dev)
   {
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -15264,7 -15216,7 +15233,7 @@@
          * Due to the hpd irq storm handling the hotplug work can re-arm the
          * poll handlers. Hence disable polling after hpd handling is shut down.
          */
- -      drm_kms_helper_poll_fini(dev);
+ +      intel_hpd_poll_fini(dev);
   
         /* poll work can call into fbdev, hence clean that up afterwards */
         intel_fbdev_fini(dev_priv);
diff --combined drivers/gpu/drm/i915/intel_dp.c

index 09f274419eea1c7466b2ff6b846b4cc41aeae3d0,aa75f55eeb61b16c282bde6a47aeb68ddc7b898e..158438bb03891092514b047f9ca73f57d89dcb82
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -42,6 -42,7 +42,7 @@@
   #include "i915_drv.h"
   
   #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+ #define DP_DPRX_ESI_LEN 14
   
   /* Compliance test status bits  */
   #define INTEL_DP_RESOLUTION_SHIFT_MASK        0
@@@ -103,13 -104,13 +104,13 @@@ static const int cnl_rates[] = { 162000
   static const int default_rates[] = { 162000, 270000, 540000 };
   
   /**
-  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
+  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
    * @intel_dp: DP struct
    *
    * If a CPU or PCH DP output is attached to an eDP panel, this function
    * will return true, and false otherwise.
    */
- static bool is_edp(struct intel_dp *intel_dp)
+ bool intel_dp_is_edp(struct intel_dp *intel_dp)
   {
         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
   
@@@ -136,32 -137,20 +137,20 @@@ static void vlv_steal_power_sequencer(s
                                       enum pipe pipe);
   static void intel_dp_unset_edid(struct intel_dp *intel_dp);
   
- static int intel_dp_num_rates(u8 link_bw_code)
- {
-       switch (link_bw_code) {
-       default:
-               WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
-                    link_bw_code);
-       case DP_LINK_BW_1_62:
-               return 1;
-       case DP_LINK_BW_2_7:
-               return 2;
-       case DP_LINK_BW_5_4:
-               return 3;
-       }
- }
- 
   /* update sink rates from dpcd */
   static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
   {
-       int i, num_rates;
+       int i, max_rate;
   
-       num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+       max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
   
-       for (i = 0; i < num_rates; i++)
+       for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
+               if (default_rates[i] > max_rate)
+                       break;
                 intel_dp->sink_rates[i] = default_rates[i];
+       }
   
-       intel_dp->num_sink_rates = num_rates;
+       intel_dp->num_sink_rates = i;
   }
   
   /* Theoretical max between source and sink */
@@@ -253,15 -242,15 +242,15 @@@ intel_dp_set_source_rates(struct intel_
         } else if (IS_GEN9_BC(dev_priv)) {
                 source_rates = skl_rates;
                 size = ARRAY_SIZE(skl_rates);
-       } else {
+       } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
+                  IS_BROADWELL(dev_priv)) {
                 source_rates = default_rates;
                 size = ARRAY_SIZE(default_rates);
+       } else {
+               source_rates = default_rates;
+               size = ARRAY_SIZE(default_rates) - 1;
         }
   
-       /* This depends on the fact that 5.4 is last value in the array */
-       if (!intel_dp_source_supports_hbr2(intel_dp))
-               size--;
- 
         intel_dp->source_rates = source_rates;
         intel_dp->num_source_rates = size;
   }
@@@ -388,7 -377,7 +377,7 @@@ intel_dp_mode_valid(struct drm_connecto
   
         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
   
-       if (is_edp(intel_dp) && fixed_mode) {
+       if (intel_dp_is_edp(intel_dp) && fixed_mode) {
                 if (mode->hdisplay > fixed_mode->hdisplay)
                         return MODE_PANEL;
   
@@@ -597,7 -586,7 +586,7 @@@ vlv_power_sequencer_pipe(struct intel_d
         lockdep_assert_held(&dev_priv->pps_mutex);
   
         /* We should never land here with regular DP ports */
-       WARN_ON(!is_edp(intel_dp));
+       WARN_ON(!intel_dp_is_edp(intel_dp));
   
         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
                 intel_dp->active_pipe != intel_dp->pps_pipe);
@@@ -644,7 -633,7 +633,7 @@@ bxt_power_sequencer_idx(struct intel_d
         lockdep_assert_held(&dev_priv->pps_mutex);
   
         /* We should never land here with regular DP ports */
-       WARN_ON(!is_edp(intel_dp));
+       WARN_ON(!intel_dp_is_edp(intel_dp));
   
         /*
          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
@@@ -847,7 -836,7 +836,7 @@@ static int edp_notify_handler(struct no
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = to_i915(dev);
   
-       if (!is_edp(intel_dp) || code != SYS_RESTART)
+       if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
                 return 0;
   
         pps_lock(intel_dp);
@@@ -907,7 -896,7 +896,7 @@@ intel_dp_check_edp(struct intel_dp *int
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = to_i915(dev);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
@@@ -1018,7 -1007,7 +1007,7 @@@ static uint32_t g4x_get_aux_send_ctl(st
         else
                 precharge = 5;
   
-       if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
+       if (IS_BROADWELL(dev_priv))
                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
         else
                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@@ -1043,7 -1032,7 +1032,7 @@@ static uint32_t skl_get_aux_send_ctl(st
                DP_AUX_CH_CTL_DONE |
                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
                DP_AUX_CH_CTL_TIME_OUT_ERROR |
-              DP_AUX_CH_CTL_TIME_OUT_1600us |
+              DP_AUX_CH_CTL_TIME_OUT_MAX |
                DP_AUX_CH_CTL_RECEIVE_ERROR |
                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
@@@ -1481,14 -1470,9 +1470,9 @@@ intel_dp_aux_init(struct intel_dp *inte
   
   bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
   {
-       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-       struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+       int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
   
-       if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
-           IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
-               return true;
-       else
-               return false;
+       return max_rate >= 540000;
   }
   
   static void
@@@ -1681,7 -1665,7 +1665,7 @@@ intel_dp_compute_config(struct intel_en
         else
                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
   
-       if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
+       if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
                 struct drm_display_mode *panel_mode =
                         intel_connector->panel.alt_fixed_mode;
                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
@@@ -1736,7 -1720,7 +1720,7 @@@
         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
          * bpc in between. */
         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
-       if (is_edp(intel_dp)) {
+       if (intel_dp_is_edp(intel_dp)) {
   
                 /* Get bpp from vbt only for panels that dont have bpp in edid */
                 if (intel_connector->base.display_info.bpc == 0 &&
@@@ -1829,7 -1813,7 +1813,7 @@@ found
          * DPLL0 VCO may need to be adjusted to get the correct
          * clock for eDP. This will affect cdclk as well.
          */
-       if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
+       if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
                 int vco;
   
                 switch (pipe_config->port_clock / 2) {
@@@ -1848,6 -1832,8 +1832,8 @@@
         if (!HAS_DDI(dev_priv))
                 intel_dp_set_clock(encoder, pipe_config);
   
+       intel_psr_compute_config(intel_dp, pipe_config);
+ 
         return true;
   }
   
@@@ -1861,7 -1847,7 +1847,7 @@@ void intel_dp_set_link_params(struct in
   }
   
   static void intel_dp_prepare(struct intel_encoder *encoder,
-                            struct intel_crtc_state *pipe_config)
+                            const struct intel_crtc_state *pipe_config)
   {
         struct drm_device *dev = encoder->base.dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -2069,7 -2055,7 +2055,7 @@@ static bool edp_panel_vdd_on(struct int
   
         lockdep_assert_held(&dev_priv->pps_mutex);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return false;
   
         cancel_delayed_work(&intel_dp->panel_vdd_work);
@@@ -2119,7 -2105,7 +2105,7 @@@ void intel_edp_panel_vdd_on(struct inte
   {
         bool vdd;
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         pps_lock(intel_dp);
@@@ -2203,7 -2189,7 +2189,7 @@@ static void edp_panel_vdd_off(struct in
   
         lockdep_assert_held(&dev_priv->pps_mutex);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
@@@ -2226,7 -2212,7 +2212,7 @@@ static void edp_panel_on(struct intel_d
   
         lockdep_assert_held(&dev_priv->pps_mutex);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
@@@ -2267,7 -2253,7 +2253,7 @@@
   
   void intel_edp_panel_on(struct intel_dp *intel_dp)
   {
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         pps_lock(intel_dp);
@@@ -2285,7 -2271,7 +2271,7 @@@ static void edp_panel_off(struct intel_
   
         lockdep_assert_held(&dev_priv->pps_mutex);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
@@@ -2316,7 -2302,7 +2302,7 @@@
   
   void intel_edp_panel_off(struct intel_dp *intel_dp)
   {
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         pps_lock(intel_dp);
@@@ -2360,7 -2346,7 +2346,7 @@@ void intel_edp_backlight_on(const struc
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         DRM_DEBUG_KMS("\n");
@@@ -2377,7 -2363,7 +2363,7 @@@ static void _intel_edp_backlight_off(st
         u32 pp;
         i915_reg_t pp_ctrl_reg;
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         pps_lock(intel_dp);
@@@ -2401,7 -2387,7 +2387,7 @@@ void intel_edp_backlight_off(const stru
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         DRM_DEBUG_KMS("\n");
@@@ -2461,7 -2447,7 +2447,7 @@@ static void assert_edp_pll(struct drm_i
   #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
   
   static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
-                               struct intel_crtc_state *pipe_config)
+                               const struct intel_crtc_state *pipe_config)
   {
         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@@ -2666,7 -2652,7 +2652,7 @@@ static void intel_dp_get_config(struct 
                 intel_dotclock_calculate(pipe_config->port_clock,
                                          &pipe_config->dp_m_n);
   
-       if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
+       if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
                 /*
                  * This is a big fat ugly hack.
@@@ -2688,33 -2674,55 +2674,55 @@@
   }
   
   static void intel_disable_dp(struct intel_encoder *encoder,
-                            struct intel_crtc_state *old_crtc_state,
-                            struct drm_connector_state *old_conn_state)
+                            const struct intel_crtc_state *old_crtc_state,
+                            const struct drm_connector_state *old_conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   
         if (old_crtc_state->has_audio)
                 intel_audio_codec_disable(encoder);
   
-       if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
-               intel_psr_disable(intel_dp);
- 
         /* Make sure the panel is off before trying to change the mode. But also
          * ensure that we have vdd while we switch off the panel. */
         intel_edp_panel_vdd_on(intel_dp);
         intel_edp_backlight_off(old_conn_state);
         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
         intel_edp_panel_off(intel_dp);
+ }
+ 
+ static void g4x_disable_dp(struct intel_encoder *encoder,
+                          const struct intel_crtc_state *old_crtc_state,
+                          const struct drm_connector_state *old_conn_state)
+ {
+       struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ 
+       intel_disable_dp(encoder, old_crtc_state, old_conn_state);
   
         /* disable the port before the pipe on g4x */
-       if (INTEL_GEN(dev_priv) < 5)
-               intel_dp_link_down(intel_dp);
+       intel_dp_link_down(intel_dp);
+ }
+ 
+ static void ilk_disable_dp(struct intel_encoder *encoder,
+                          const struct intel_crtc_state *old_crtc_state,
+                          const struct drm_connector_state *old_conn_state)
+ {
+       intel_disable_dp(encoder, old_crtc_state, old_conn_state);
+ }
+ 
+ static void vlv_disable_dp(struct intel_encoder *encoder,
+                          const struct intel_crtc_state *old_crtc_state,
+                          const struct drm_connector_state *old_conn_state)
+ {
+       struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ 
+       intel_psr_disable(intel_dp, old_crtc_state);
+ 
+       intel_disable_dp(encoder, old_crtc_state, old_conn_state);
   }
   
   static void ilk_post_disable_dp(struct intel_encoder *encoder,
-                               struct intel_crtc_state *old_crtc_state,
-                               struct drm_connector_state *old_conn_state)
+                               const struct intel_crtc_state *old_crtc_state,
+                               const struct drm_connector_state *old_conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
         enum port port = dp_to_dig_port(intel_dp)->port;
@@@ -2727,8 -2735,8 +2735,8 @@@
   }
   
   static void vlv_post_disable_dp(struct intel_encoder *encoder,
-                               struct intel_crtc_state *old_crtc_state,
-                               struct drm_connector_state *old_conn_state)
+                               const struct intel_crtc_state *old_crtc_state,
+                               const struct drm_connector_state *old_conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
   
@@@ -2736,8 -2744,8 +2744,8 @@@
   }
   
   static void chv_post_disable_dp(struct intel_encoder *encoder,
-                               struct intel_crtc_state *old_crtc_state,
-                               struct drm_connector_state *old_conn_state)
+                               const struct intel_crtc_state *old_crtc_state,
+                               const struct drm_connector_state *old_conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
         struct drm_device *dev = encoder->base.dev;
@@@ -2842,7 -2850,7 +2850,7 @@@ _intel_dp_set_link_train(struct intel_d
   }
   
   static void intel_dp_enable_port(struct intel_dp *intel_dp,
-                                struct intel_crtc_state *old_crtc_state)
+                                const struct intel_crtc_state *old_crtc_state)
   {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -2866,8 -2874,8 +2874,8 @@@
   }
   
   static void intel_enable_dp(struct intel_encoder *encoder,
-                           struct intel_crtc_state *pipe_config,
-                           struct drm_connector_state *conn_state)
+                           const struct intel_crtc_state *pipe_config,
+                           const struct drm_connector_state *conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
         struct drm_device *dev = encoder->base.dev;
@@@ -2914,26 -2922,26 +2922,26 @@@
   }
   
   static void g4x_enable_dp(struct intel_encoder *encoder,
-                         struct intel_crtc_state *pipe_config,
-                         struct drm_connector_state *conn_state)
+                         const struct intel_crtc_state *pipe_config,
+                         const struct drm_connector_state *conn_state)
   {
         intel_enable_dp(encoder, pipe_config, conn_state);
         intel_edp_backlight_on(pipe_config, conn_state);
   }
   
   static void vlv_enable_dp(struct intel_encoder *encoder,
-                         struct intel_crtc_state *pipe_config,
-                         struct drm_connector_state *conn_state)
+                         const struct intel_crtc_state *pipe_config,
+                         const struct drm_connector_state *conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
   
         intel_edp_backlight_on(pipe_config, conn_state);
-       intel_psr_enable(intel_dp);
+       intel_psr_enable(intel_dp, pipe_config);
   }
   
   static void g4x_pre_enable_dp(struct intel_encoder *encoder,
-                             struct intel_crtc_state *pipe_config,
-                             struct drm_connector_state *conn_state)
+                             const struct intel_crtc_state *pipe_config,
+                             const struct drm_connector_state *conn_state)
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
         enum port port = dp_to_dig_port(intel_dp)->port;
@@@ -3040,7 -3048,7 +3048,7 @@@ static void vlv_init_panel_power_sequen
   
         intel_dp->active_pipe = crtc->pipe;
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         /* now it's all ours */
@@@ -3055,8 -3063,8 +3063,8 @@@
   }
   
   static void vlv_pre_enable_dp(struct intel_encoder *encoder,
-                             struct intel_crtc_state *pipe_config,
-                             struct drm_connector_state *conn_state)
+                             const struct intel_crtc_state *pipe_config,
+                             const struct drm_connector_state *conn_state)
   {
         vlv_phy_pre_encoder_enable(encoder);
   
@@@ -3064,8 -3072,8 +3072,8 @@@
   }
   
   static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
-                                 struct intel_crtc_state *pipe_config,
-                                 struct drm_connector_state *conn_state)
+                                 const struct intel_crtc_state *pipe_config,
+                                 const struct drm_connector_state *conn_state)
   {
         intel_dp_prepare(encoder, pipe_config);
   
@@@ -3073,8 -3081,8 +3081,8 @@@
   }
   
   static void chv_pre_enable_dp(struct intel_encoder *encoder,
-                             struct intel_crtc_state *pipe_config,
-                             struct drm_connector_state *conn_state)
+                             const struct intel_crtc_state *pipe_config,
+                             const struct drm_connector_state *conn_state)
   {
         chv_phy_pre_encoder_enable(encoder);
   
@@@ -3085,8 -3093,8 +3093,8 @@@
   }
   
   static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
-                                 struct intel_crtc_state *pipe_config,
-                                 struct drm_connector_state *conn_state)
+                                 const struct intel_crtc_state *pipe_config,
+                                 const struct drm_connector_state *conn_state)
   {
         intel_dp_prepare(encoder, pipe_config);
   
@@@ -3094,8 -3102,8 +3102,8 @@@
   }
   
   static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
-                                   struct intel_crtc_state *pipe_config,
-                                   struct drm_connector_state *conn_state)
+                                   const struct intel_crtc_state *pipe_config,
+                                   const struct drm_connector_state *conn_state)
   {
         chv_phy_post_pll_disable(encoder);
   }
@@@ -3147,9 -3155,7 +3155,7 @@@ intel_dp_voltage_max(struct intel_dp *i
         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
         enum port port = dp_to_dig_port(intel_dp)->port;
   
-       if (IS_GEN9_LP(dev_priv))
-               return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-       else if (INTEL_GEN(dev_priv) >= 9) {
+       if (INTEL_GEN(dev_priv) >= 9) {
                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
                 return intel_ddi_dp_voltage_max(encoder);
         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@@ -3506,13 -3512,11 +3512,11 @@@ intel_dp_set_signal_levels(struct intel
         uint32_t signal_levels, mask = 0;
         uint8_t train_set = intel_dp->train_set[0];
   
-       if (HAS_DDI(dev_priv)) {
+       if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+               signal_levels = bxt_signal_levels(intel_dp);
+       } else if (HAS_DDI(dev_priv)) {
                 signal_levels = ddi_signal_levels(intel_dp);
- 
-               if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
-                       signal_levels = 0;
-               else
-                       mask = DDI_BUF_EMP_MASK;
+               mask = DDI_BUF_EMP_MASK;
         } else if (IS_CHERRYVIEW(dev_priv)) {
                 signal_levels = chv_signal_levels(intel_dp);
         } else if (IS_VALLEYVIEW(dev_priv)) {
@@@ -3731,16 -3735,9 +3735,16 @@@ intel_edp_init_dpcd(struct intel_dp *in
   
         }
   
- -      /* Read the eDP Display control capabilities registers */
- -      if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
- -          drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
+ +      /*
+ +       * Read the eDP display control registers.
+ +       *
+ +       * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
+ +       * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
+ +       * set, but require eDP 1.4+ detection (e.g. for supported link rates
+ +       * method). The display control registers should read zero if they're
+ +       * not supported anyway.
+ +       */
+ +      if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
                              sizeof(intel_dp->edp_dpcd))
                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
@@@ -3791,7 -3788,7 +3795,7 @@@ intel_dp_get_dpcd(struct intel_dp *inte
                 return false;
   
         /* Don't clobber cached eDP rates. */
-       if (!is_edp(intel_dp)) {
+       if (!intel_dp_is_edp(intel_dp)) {
                 intel_dp_set_sink_rates(intel_dp);
                 intel_dp_set_common_rates(intel_dp);
         }
@@@ -3813,7 -3810,7 +3817,7 @@@
          * downstream port information. So, an early return here saves
          * time from performing other operations which are not required.
          */
-       if (!is_edp(intel_dp) && !intel_dp->sink_count)
+       if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
                 return false;
   
         if (!drm_dp_is_branch(intel_dp->dpcd))
@@@ -3835,7 -3832,7 +3839,7 @@@ intel_dp_can_mst(struct intel_dp *intel
   {
         u8 mstm_cap;
   
-       if (!i915.enable_dp_mst)
+       if (!i915_modparams.enable_dp_mst)
                 return false;
   
         if (!intel_dp->can_mst)
@@@ -3853,7 -3850,7 +3857,7 @@@
   static void
   intel_dp_configure_mst(struct intel_dp *intel_dp)
   {
-       if (!i915.enable_dp_mst)
+       if (!i915_modparams.enable_dp_mst)
                 return;
   
         if (!intel_dp->can_mst)
@@@ -4000,15 -3997,9 +4004,9 @@@ intel_dp_get_sink_irq(struct intel_dp *
   static bool
   intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
   {
-       int ret;
- 
-       ret = drm_dp_dpcd_read(&intel_dp->aux,
-                                            DP_SINK_COUNT_ESI,
-                                            sink_irq_vector, 14);
-       if (ret != 14)
-               return false;
- 
-       return true;
+       return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
+                               sink_irq_vector, DP_DPRX_ESI_LEN) ==
+               DP_DPRX_ESI_LEN;
   }
   
   static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
@@@ -4208,7 -4199,7 +4206,7 @@@ intel_dp_check_mst_status(struct intel_
         bool bret;
   
         if (intel_dp->is_mst) {
-               u8 esi[16] = { 0 };
+               u8 esi[DP_DPRX_ESI_LEN] = { 0 };
                 int ret = 0;
                 int retry;
                 bool handled;
@@@ -4403,7 -4394,7 +4401,7 @@@ intel_dp_detect_dpcd(struct intel_dp *i
         if (!intel_dp_get_dpcd(intel_dp))
                 return connector_status_disconnected;
   
-       if (is_edp(intel_dp))
+       if (intel_dp_is_edp(intel_dp))
                 return connector_status_connected;
   
         /* if there's no downstream port, we're done */
@@@ -4719,7 -4710,7 +4717,7 @@@ intel_dp_long_pulse(struct intel_connec
         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
   
         /* Can't disconnect eDP, but you can close the lid... */
-       if (is_edp(intel_dp))
+       if (intel_dp_is_edp(intel_dp))
                 status = edp_detect(intel_dp);
         else if (intel_digital_port_connected(to_i915(dev),
                                               dp_to_dig_port(intel_dp)))
@@@ -4745,10 -4736,6 +4743,6 @@@
         if (intel_encoder->type != INTEL_OUTPUT_EDP)
                 intel_encoder->type = INTEL_OUTPUT_DP;
   
-       DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
-                     yesno(intel_dp_source_supports_hbr2(intel_dp)),
-                     yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
- 
         if (intel_dp->reset_link_params) {
                 /* Initial max link lane count */
                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
@@@ -4799,7 -4786,7 +4793,7 @@@
         intel_dp->aux.i2c_defer_count = 0;
   
         intel_dp_set_edid(intel_dp);
-       if (is_edp(intel_dp) || intel_connector->detect_edid)
+       if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid)
                 status = connector_status_connected;
         intel_dp->detect_done = true;
   
@@@ -4883,7 -4870,7 +4877,7 @@@ static int intel_dp_get_modes(struct dr
         }
   
         /* if eDP has no EDID, fall back to fixed mode */
-       if (is_edp(intel_attached_dp(connector)) &&
+       if (intel_dp_is_edp(intel_attached_dp(connector)) &&
             intel_connector->panel.fixed_mode) {
                 struct drm_display_mode *mode;
   
@@@ -4934,8 -4921,10 +4928,10 @@@ intel_dp_connector_destroy(struct drm_c
         if (!IS_ERR_OR_NULL(intel_connector->edid))
                 kfree(intel_connector->edid);
   
-       /* Can't call is_edp() since the encoder may have been destroyed
-        * already. */
+       /*
+        * Can't call intel_dp_is_edp() since the encoder may have been
+        * destroyed already.
+        */
         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
                 intel_panel_fini(&intel_connector->panel);
   
@@@ -4949,7 -4938,7 +4945,7 @@@ void intel_dp_encoder_destroy(struct dr
         struct intel_dp *intel_dp = &intel_dig_port->dp;
   
         intel_dp_mst_encoder_cleanup(intel_dig_port);
-       if (is_edp(intel_dp)) {
+       if (intel_dp_is_edp(intel_dp)) {
                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
                 /*
                  * vdd might still be enabled do to the delayed vdd off.
@@@ -4975,7 -4964,7 +4971,7 @@@ void intel_dp_encoder_suspend(struct in
   {
         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return;
   
         /*
@@@ -5043,7 -5032,7 +5039,7 @@@ void intel_dp_encoder_reset(struct drm_
         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
   
-       if (is_edp(intel_dp)) {
+       if (intel_dp_is_edp(intel_dp)) {
                 /* Reinit the power sequencer, in case BIOS did something with it. */
                 intel_dp_pps_init(encoder->dev, intel_dp);
                 intel_edp_panel_vdd_sanitize(intel_dp);
@@@ -5144,7 -5133,7 +5140,7 @@@ put_power
   }
   
   /* check the VBT to see whether the eDP is on another port */
- bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
+ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
   {
         /*
          * eDP not supported on g4x. so bail out early just
@@@ -5167,7 -5156,7 +5163,7 @@@ intel_dp_add_properties(struct intel_d
         intel_attach_force_audio_property(connector);
         intel_attach_broadcast_rgb_property(connector);
   
-       if (is_edp(intel_dp)) {
+       if (intel_dp_is_edp(intel_dp)) {
                 u32 allowed_scalers;
   
                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
@@@ -5455,7 -5444,7 +5451,7 @@@ static void intel_dp_pps_init(struct dr
    * The caller of this function needs to take a lock on dev_priv->drrs.
    */
   static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
-                                   struct intel_crtc_state *crtc_state,
+                                   const struct intel_crtc_state *crtc_state,
                                     int refresh_rate)
   {
         struct intel_encoder *encoder;
@@@ -5474,11 -5463,6 +5470,6 @@@
                 return;
         }
   
-       /*
-        * FIXME: This needs proper synchronization with psr state for some
-        * platforms that cannot have PSR and DRRS enabled at the same time.
-        */
- 
         dig_port = dp_to_dig_port(intel_dp);
         encoder = &dig_port->base;
         intel_crtc = to_intel_crtc(encoder->base.crtc);
@@@ -5552,7 -5536,7 +5543,7 @@@
    * Initializes frontbuffer_bits and drrs.dp
    */
   void intel_edp_drrs_enable(struct intel_dp *intel_dp,
-                          struct intel_crtc_state *crtc_state)
+                          const struct intel_crtc_state *crtc_state)
   {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -5562,6 -5546,11 +5553,11 @@@
                 return;
         }
   
+       if (dev_priv->psr.enabled) {
+               DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
+               return;
+       }
+ 
         mutex_lock(&dev_priv->drrs.mutex);
         if (WARN_ON(dev_priv->drrs.dp)) {
                 DRM_ERROR("DRRS already enabled\n");
@@@ -5583,7 -5572,7 +5579,7 @@@ unlock
    *
    */
   void intel_edp_drrs_disable(struct intel_dp *intel_dp,
-                           struct intel_crtc_state *old_crtc_state)
+                           const struct intel_crtc_state *old_crtc_state)
   {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = to_i915(dev);
@@@ -5833,7 -5822,7 +5829,7 @@@ static bool intel_edp_init_connector(st
         struct edid *edid;
         enum pipe pipe = INVALID_PIPE;
   
-       if (!is_edp(intel_dp))
+       if (!intel_dp_is_edp(intel_dp))
                 return true;
   
         /*
@@@ -6049,7 -6038,7 +6045,7 @@@ intel_dp_init_connector(struct intel_di
         intel_dp->DP = I915_READ(intel_dp->output_reg);
         intel_dp->attached_connector = intel_connector;
   
-       if (intel_dp_is_edp(dev_priv, port))
+       if (intel_dp_is_port_edp(dev_priv, port))
                 type = DRM_MODE_CONNECTOR_eDP;
         else
                 type = DRM_MODE_CONNECTOR_DisplayPort;
@@@ -6067,7 -6056,8 +6063,8 @@@
   
         /* eDP only on port B and/or C on vlv/chv */
         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
-                   is_edp(intel_dp) && port != PORT_B && port != PORT_C))
+                   intel_dp_is_edp(intel_dp) &&
+                   port != PORT_B && port != PORT_C))
                 return false;
   
         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
@@@ -6095,7 -6085,7 +6092,7 @@@
                 intel_connector->get_hw_state = intel_connector_get_hw_state;
   
         /* init MST on ports that can support it */
-       if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
+       if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
             (port == PORT_B || port == PORT_C || port == PORT_D))
                 intel_dp_mst_encoder_init(intel_dig_port,
                                           intel_connector->base.base.id);
@@@ -6151,7 -6141,6 +6148,6 @@@ bool intel_dp_init(struct drm_i915_priv
                 goto err_encoder_init;
   
         intel_encoder->compute_config = intel_dp_compute_config;
-       intel_encoder->disable = intel_disable_dp;
         intel_encoder->get_hw_state = intel_dp_get_hw_state;
         intel_encoder->get_config = intel_dp_get_config;
         intel_encoder->suspend = intel_dp_encoder_suspend;
@@@ -6159,18 -6148,24 +6155,24 @@@
                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
                 intel_encoder->pre_enable = chv_pre_enable_dp;
                 intel_encoder->enable = vlv_enable_dp;
+               intel_encoder->disable = vlv_disable_dp;
                 intel_encoder->post_disable = chv_post_disable_dp;
                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
         } else if (IS_VALLEYVIEW(dev_priv)) {
                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
                 intel_encoder->pre_enable = vlv_pre_enable_dp;
                 intel_encoder->enable = vlv_enable_dp;
+               intel_encoder->disable = vlv_disable_dp;
                 intel_encoder->post_disable = vlv_post_disable_dp;
+       } else if (INTEL_GEN(dev_priv) >= 5) {
+               intel_encoder->pre_enable = g4x_pre_enable_dp;
+               intel_encoder->enable = g4x_enable_dp;
+               intel_encoder->disable = ilk_disable_dp;
+               intel_encoder->post_disable = ilk_post_disable_dp;
         } else {
                 intel_encoder->pre_enable = g4x_pre_enable_dp;
                 intel_encoder->enable = g4x_enable_dp;
-               if (INTEL_GEN(dev_priv) >= 5)
-                       intel_encoder->post_disable = ilk_post_disable_dp;
+               intel_encoder->disable = g4x_disable_dp;
         }
   
         intel_dig_port->port = port;
@@@ -6193,6 -6188,9 +6195,9 @@@
         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
         dev_priv->hotplug.irq_port[port] = intel_dig_port;
   
+       if (port != PORT_A)
+               intel_infoframe_init(intel_dig_port);
+ 
         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
                 goto err_init_connector;
   
diff --combined drivers/gpu/drm/i915/intel_drv.h

index 79fbaf78f6044b33dcc8b4429efc41972a65c67d,47d022d487181f721b419ed34c3e8b8037940b51..7bc60c848940f95d1352ac79b7040867fa6268a3
--- 1/drivers/gpu/drm/i915/intel_drv.h
--- 2/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@@ -220,23 -220,23 +220,23 @@@ struct intel_encoder 
                                struct intel_crtc_state *,
                                struct drm_connector_state *);
         void (*pre_pll_enable)(struct intel_encoder *,
-                              struct intel_crtc_state *,
-                              struct drm_connector_state *);
+                              const struct intel_crtc_state *,
+                              const struct drm_connector_state *);
         void (*pre_enable)(struct intel_encoder *,
-                          struct intel_crtc_state *,
-                          struct drm_connector_state *);
+                          const struct intel_crtc_state *,
+                          const struct drm_connector_state *);
         void (*enable)(struct intel_encoder *,
-                      struct intel_crtc_state *,
-                      struct drm_connector_state *);
+                      const struct intel_crtc_state *,
+                      const struct drm_connector_state *);
         void (*disable)(struct intel_encoder *,
-                       struct intel_crtc_state *,
-                       struct drm_connector_state *);
+                       const struct intel_crtc_state *,
+                       const struct drm_connector_state *);
         void (*post_disable)(struct intel_encoder *,
-                            struct intel_crtc_state *,
-                            struct drm_connector_state *);
+                            const struct intel_crtc_state *,
+                            const struct drm_connector_state *);
         void (*post_pll_disable)(struct intel_encoder *,
-                                struct intel_crtc_state *,
-                                struct drm_connector_state *);
+                                const struct intel_crtc_state *,
+                                const struct drm_connector_state *);
         /* Read out the current hw state of this connector, returning true if
          * the encoder is active. If the encoder is enabled it also set the pipe
          * it is connected to in the pipe parameter. */
@@@ -384,7 -384,8 +384,8 @@@ struct intel_atomic_state 
         unsigned int active_pipe_changes;
   
         unsigned int active_crtcs;
-       unsigned int min_pixclk[I915_MAX_PIPES];
+       /* minimum acceptable cdclk for each pipe */
+       int min_cdclk[I915_MAX_PIPES];
   
         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
   
@@@ -493,9 -494,12 +494,11 @@@ struct intel_crtc_scaler_state 
   
   /* drm_mode->private_flags */
   #define I915_MODE_FLAG_INHERITED 1
+ /* Flag to get scanline using frame time stamps */
+ #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
   
   struct intel_pipe_wm {
         struct intel_wm_level wm[5];
- -      struct intel_wm_level raw_wm[5];
         uint32_t linetime;
         bool fbc_wm_enabled;
         bool pipe_enabled;
@@@ -714,6 -718,9 +717,9 @@@ struct intel_crtc_state 
         struct intel_link_m_n dp_m2_n2;
         bool has_drrs;
   
+       bool has_psr;
+       bool has_psr2;
+ 
         /*
          * Frequence the dpll for the port should run at. Differs from the
          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
@@@ -752,6 -759,7 +758,7 @@@
         struct intel_link_m_n fdi_m_n;
   
         bool ips_enabled;
+       bool ips_force_disable;
   
         bool enable_fbc;
   
@@@ -795,18 -803,10 +802,10 @@@ struct intel_crtc 
          * some outputs connected to this crtc.
          */
         bool active;
-       bool lowfreq_avail;
         u8 plane_ids_mask;
         unsigned long long enabled_power_domains;
         struct intel_overlay *overlay;
   
-       /* Display surface base address adjustement for pageflips. Note that on
-        * gen4+ this only adjusts up to a tile, offsets within a tile are
-        * handled in the hw itself (with the TILEOFF register). */
-       u32 dspaddr_offset;
-       int adjusted_x;
-       int adjusted_y;
- 
         struct intel_crtc_state *config;
   
         /* global reset count when the last flip was submitted */
@@@ -908,16 -908,6 +907,6 @@@ struct intel_hdmi 
         bool has_audio;
         bool rgb_quant_range_selectable;
         struct intel_connector *attached_connector;
-       void (*write_infoframe)(struct drm_encoder *encoder,
-                               const struct intel_crtc_state *crtc_state,
-                               enum hdmi_infoframe_type type,
-                               const void *frame, ssize_t len);
-       void (*set_infoframes)(struct drm_encoder *encoder,
-                              bool enable,
-                              const struct intel_crtc_state *crtc_state,
-                              const struct drm_connector_state *conn_state);
-       bool (*infoframe_enabled)(struct drm_encoder *encoder,
-                                 const struct intel_crtc_state *pipe_config);
   };
   
   struct intel_dp_mst_encoder;
@@@ -1068,6 -1058,17 +1057,17 @@@ struct intel_digital_port 
         bool release_cl2_override;
         uint8_t max_lanes;
         enum intel_display_power_domain ddi_io_power_domain;
+ 
+       void (*write_infoframe)(struct drm_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state,
+                               unsigned int type,
+                               const void *frame, ssize_t len);
+       void (*set_infoframes)(struct drm_encoder *encoder,
+                              bool enable,
+                              const struct intel_crtc_state *crtc_state,
+                              const struct drm_connector_state *conn_state);
+       bool (*infoframe_enabled)(struct drm_encoder *encoder,
+                                 const struct intel_crtc_state *pipe_config);
   };
   
   struct intel_dp_mst_encoder {
@@@ -1188,6 -1189,30 +1188,30 @@@ hdmi_to_dig_port(struct intel_hdmi *int
         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
   }
   
+ static inline struct intel_plane_state *
+ intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
+                                struct intel_plane *plane)
+ {
+       return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
+                                                                  &plane->base));
+ }
+ 
+ static inline struct intel_crtc_state *
+ intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
+                               struct intel_crtc *crtc)
+ {
+       return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
+                                                                &crtc->base));
+ }
+ 
+ static inline struct intel_crtc_state *
+ intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
+                               struct intel_crtc *crtc)
+ {
+       return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
+                                                                &crtc->base));
+ }
+ 
   /* intel_fifo_underrun.c */
   bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
                                            enum pipe pipe, bool enable);
@@@ -1204,11 -1229,8 +1228,8 @@@ void intel_check_pch_fifo_underruns(str
   /* i915_irq.c */
   void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
   void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
- void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
   void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
   void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
- void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
- void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
   void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
   void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
   void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
@@@ -1216,7 -1238,7 +1237,7 @@@
   static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
                                             u32 mask)
   {
-       return mask & ~i915->rps.pm_intrmsk_mbz;
+       return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
   }
   
   void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
@@@ -1227,7 -1249,7 +1248,7 @@@ static inline bool intel_irqs_enabled(s
          * We only use drm_irq_uninstall() at unload and VT switch, so
          * this is the only thing we need to check.
          */
-       return dev_priv->pm.irqs_enabled;
+       return dev_priv->runtime_pm.irqs_enabled;
   }
   
   int intel_get_crtc_scanline(struct intel_crtc *crtc);
@@@ -1245,8 -1267,8 +1266,8 @@@ void intel_crt_reset(struct drm_encode
   
   /* intel_ddi.c */
   void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
-                               struct intel_crtc_state *old_crtc_state,
-                               struct drm_connector_state *old_conn_state);
+                               const struct intel_crtc_state *old_crtc_state,
+                               const struct drm_connector_state *old_conn_state);
   void hsw_fdi_link_train(struct intel_crtc *crtc,
                         const struct intel_crtc_state *crtc_state);
   void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
@@@ -1271,6 -1293,7 +1292,7 @@@ void intel_ddi_clock_get(struct intel_e
                          struct intel_crtc_state *pipe_config);
   void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
                                     bool state);
+ u32 bxt_signal_levels(struct intel_dp *intel_dp);
   uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
   u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
   
@@@ -1289,6 -1312,7 +1311,7 @@@ void intel_audio_init(struct drm_i915_p
   void intel_audio_deinit(struct drm_i915_private *dev_priv);
   
   /* intel_cdclk.c */
+ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
   void skl_init_cdclk(struct drm_i915_private *dev_priv);
   void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
   void cnl_init_cdclk(struct drm_i915_private *dev_priv);
@@@ -1331,11 -1355,13 +1354,13 @@@ void intel_pps_unlock_regs_wa(struct dr
   void intel_encoder_destroy(struct drm_encoder *encoder);
   int intel_connector_init(struct intel_connector *);
   struct intel_connector *intel_connector_alloc(void);
+ void intel_connector_free(struct intel_connector *connector);
   bool intel_connector_get_hw_state(struct intel_connector *connector);
   void intel_connector_attach_encoder(struct intel_connector *connector,
                                     struct intel_encoder *encoder);
- struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
-                                            struct drm_crtc *crtc);
+ struct drm_display_mode *
+ intel_encoder_current_mode(struct intel_encoder *encoder);
+ 
   enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
   int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
                                 struct drm_file *file_priv);
@@@ -1376,7 -1402,7 +1401,7 @@@ void vlv_wait_port_ready(struct drm_i91
                          struct intel_digital_port *dport,
                          unsigned int expected_mask);
   int intel_get_load_detect_pipe(struct drm_connector *connector,
-                              struct drm_display_mode *mode,
+                              const struct drm_display_mode *mode,
                                struct intel_load_detect_pipe *old,
                                struct drm_modeset_acquire_ctx *ctx);
   void intel_release_load_detect_pipe(struct drm_connector *connector,
@@@ -1400,7 -1426,9 +1425,9 @@@ int intel_plane_atomic_set_property(str
                                     struct drm_plane_state *state,
                                     struct drm_property *property,
                                     uint64_t val);
- int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
+ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
+                                   struct drm_crtc_state *crtc_state,
+                                   const struct intel_plane_state *old_plane_state,
                                     struct drm_plane_state *plane_state);
   
   void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
@@@ -1498,7 -1526,8 +1525,8 @@@ int intel_dp_sink_crc(struct intel_dp *
   bool intel_dp_compute_config(struct intel_encoder *encoder,
                              struct intel_crtc_state *pipe_config,
                              struct drm_connector_state *conn_state);
- bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
+ bool intel_dp_is_edp(struct intel_dp *intel_dp);
+ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
   enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
                                   bool long_hpd);
   void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
@@@ -1517,9 -1546,9 +1545,9 @@@ void intel_power_sequencer_reset(struc
   uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
   void intel_plane_destroy(struct drm_plane *plane);
   void intel_edp_drrs_enable(struct intel_dp *intel_dp,
-                          struct intel_crtc_state *crtc_state);
+                          const struct intel_crtc_state *crtc_state);
   void intel_edp_drrs_disable(struct intel_dp *intel_dp,
-                          struct intel_crtc_state *crtc_state);
+                           const struct intel_crtc_state *crtc_state);
   void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
                                unsigned int frontbuffer_bits);
   void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
@@@ -1647,6 -1676,7 +1675,7 @@@ void intel_hdmi_handle_sink_scrambling(
                                        bool high_tmds_clock_ratio,
                                        bool scrambling);
   void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
+ void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
   
   
   /* intel_lvds.c */
@@@ -1718,8 -1748,10 +1747,10 @@@ static inline void intel_backlight_devi
   
   
   /* intel_psr.c */
- void intel_psr_enable(struct intel_dp *intel_dp);
- void intel_psr_disable(struct intel_dp *intel_dp);
+ void intel_psr_enable(struct intel_dp *intel_dp,
+                     const struct intel_crtc_state *crtc_state);
+ void intel_psr_disable(struct intel_dp *intel_dp,
+                     const struct intel_crtc_state *old_crtc_state);
   void intel_psr_invalidate(struct drm_i915_private *dev_priv,
                           unsigned frontbuffer_bits);
   void intel_psr_flush(struct drm_i915_private *dev_priv,
@@@ -1728,6 -1760,8 +1759,8 @@@
   void intel_psr_init(struct drm_i915_private *dev_priv);
   void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
                                    unsigned frontbuffer_bits);
+ void intel_psr_compute_config(struct intel_dp *intel_dp,
+                             struct intel_crtc_state *crtc_state);
   
   /* intel_runtime_pm.c */
   int intel_power_domains_init(struct drm_i915_private *);
@@@ -1755,7 -1789,7 +1788,7 @@@ void intel_display_power_put(struct drm
   static inline void
   assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
   {
-       WARN_ONCE(dev_priv->pm.suspended,
+       WARN_ONCE(dev_priv->runtime_pm.suspended,
                   "Device suspended during HW access\n");
   }
   
@@@ -1763,7 -1797,7 +1796,7 @@@ static inline voi
   assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
   {
         assert_rpm_device_not_suspended(dev_priv);
-       WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
+       WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
                   "RPM wakelock ref not held during HW access");
   }
   
@@@ -1788,7 -1822,7 +1821,7 @@@
   static inline void
   disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
   {
-       atomic_inc(&dev_priv->pm.wakeref_count);
+       atomic_inc(&dev_priv->runtime_pm.wakeref_count);
   }
   
   /**
@@@ -1805,7 -1839,7 +1838,7 @@@
   static inline void
   enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
   {
-       atomic_dec(&dev_priv->pm.wakeref_count);
+       atomic_dec(&dev_priv->runtime_pm.wakeref_count);
   }
   
   void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
@@@ -1843,7 -1877,6 +1876,6 @@@ void gen6_rps_reset_ei(struct drm_i915_
   void gen6_rps_idle(struct drm_i915_private *dev_priv);
   void gen6_rps_boost(struct drm_i915_gem_request *rq,
                     struct intel_rps_client *rps);
- void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
   void g4x_wm_get_hw_state(struct drm_device *dev);
   void vlv_wm_get_hw_state(struct drm_device *dev);
   void ilk_wm_get_hw_state(struct drm_device *dev);
@@@ -1859,16 -1892,19 +1891,19 @@@ int intel_enable_sagv(struct drm_i915_p
   int intel_disable_sagv(struct drm_i915_private *dev_priv);
   bool skl_wm_level_equals(const struct skl_wm_level *l1,
                          const struct skl_wm_level *l2);
- bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
+ bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
+                                const struct skl_ddb_entry **entries,
                                  const struct skl_ddb_entry *ddb,
                                  int ignore);
   bool ilk_disable_lp_wm(struct drm_device *dev);
   int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
   int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
                                   struct intel_crtc_state *cstate);
- static inline int intel_enable_rc6(void)
+ void intel_init_ipc(struct drm_i915_private *dev_priv);
+ void intel_enable_ipc(struct drm_i915_private *dev_priv);
+ static inline int intel_rc6_enabled(void)
   {
-       return i915.enable_rc6;
+       return i915_modparams.enable_rc6;
   }
   
   /* intel_sdvo.c */
@@@ -1883,8 -1919,12 +1918,12 @@@ struct intel_plane *intel_sprite_plane_
                                               enum pipe pipe, int plane);
   int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
                               struct drm_file *file_priv);
- void intel_pipe_update_start(struct intel_crtc *crtc);
- void intel_pipe_update_end(struct intel_crtc *crtc);
+ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
+ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+ void skl_update_plane(struct intel_plane *plane,
+                     const struct intel_crtc_state *crtc_state,
+                     const struct intel_plane_state *plane_state);
+ void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
   
   /* intel_tv.c */
   void intel_tv_init(struct drm_i915_private *dev_priv);
@@@ -1956,7 -1996,9 +1995,9 @@@ struct drm_plane_state *intel_plane_dup
   void intel_plane_destroy_state(struct drm_plane *plane,
                                struct drm_plane_state *state);
   extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
- int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
+ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
+                                       struct intel_crtc_state *crtc_state,
+                                       const struct intel_plane_state *old_plane_state,
                                         struct intel_plane_state *intel_state);
   
   /* intel_color.c */
diff --combined drivers/gpu/drm/i915/intel_pm.c

index cb950752c34695063a2714be448834bec7ed354f,aa12a44e9a76b1cf8419dccd3494d1bda76f6e5b..f4a4e9496893232a6dd26ae953e45d356879328e
--- 1/drivers/gpu/drm/i915/intel_pm.c
--- 2/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -58,24 -58,23 +58,23 @@@
   
   static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
   {
+       if (HAS_LLC(dev_priv)) {
+               /*
+                * WaCompressedResourceDisplayNewHashMode:skl,kbl
+                * Display WA#0390: skl,kbl
+                *
+                * Must match Sampler, Pixel Back End, and Media. See
+                * WaCompressedResourceSamplerPbeMediaNewHashMode.
+                */
+               I915_WRITE(CHICKEN_PAR1_1,
+                          I915_READ(CHICKEN_PAR1_1) |
+                          SKL_DE_COMPRESSED_HASH_MODE);
+       }
+ 
         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
         I915_WRITE(CHICKEN_PAR1_1,
                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
   
-       /*
-        * Display WA#0390: skl,bxt,kbl,glk
-        *
-        * Must match Sampler, Pixel Back End, and Media
-        * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31).
-        *
-        * Including bits outside the page in the hash would
-        * require 2 (or 4?) MiB alignment of resources. Just
-        * assume the defaul hashing mode which only uses bits
-        * within the page.
-        */
-       I915_WRITE(CHICKEN_PAR1_1,
-                  I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE);
- 
         I915_WRITE(GEN8_CONFIG0,
                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
   
@@@ -125,6 -124,7 +124,7 @@@ static void bxt_init_clock_gating(struc
   
   static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
   {
+       u32 val;
         gen9_init_clock_gating(dev_priv);
   
         /*
@@@ -144,6 -144,11 +144,11 @@@
                 I915_WRITE(CHICKEN_MISC_2, val);
         }
   
+       /* Display WA #1133: WaFbcSkipSegments:glk */
+       val = I915_READ(ILK_DPFC_CHICKEN);
+       val &= ~GLK_SKIP_SEG_COUNT_MASK;
+       val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+       I915_WRITE(ILK_DPFC_CHICKEN, val);
   }
   
   static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@@ -317,7 -322,7 +322,7 @@@ static void chv_set_memory_dvfs(struct 
   {
         u32 val;
   
-       mutex_lock(&dev_priv->rps.hw_lock);
+       mutex_lock(&dev_priv->pcu_lock);
   
         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
         if (enable)
@@@ -332,14 -337,14 +337,14 @@@
                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
   
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   }
   
   static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
   {
         u32 val;
   
-       mutex_lock(&dev_priv->rps.hw_lock);
+       mutex_lock(&dev_priv->pcu_lock);
   
         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
         if (enable)
@@@ -348,7 -353,7 +353,7 @@@
                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
   
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   }
   
   #define FW_WM(value, plane) \
@@@ -1322,21 -1327,21 +1327,21 @@@ static int g4x_compute_pipe_wm(struct i
         int num_active_planes = hweight32(crtc_state->active_planes &
                                           ~BIT(PLANE_CURSOR));
         const struct g4x_pipe_wm *raw;
-       struct intel_plane_state *plane_state;
+       const struct intel_plane_state *old_plane_state;
+       const struct intel_plane_state *new_plane_state;
         struct intel_plane *plane;
         enum plane_id plane_id;
         int i, level;
         unsigned int dirty = 0;
   
-       for_each_intel_plane_in_state(state, plane, plane_state, i) {
-               const struct intel_plane_state *old_plane_state =
-                       to_intel_plane_state(plane->base.state);
- 
-               if (plane_state->base.crtc != &crtc->base &&
+       for_each_oldnew_intel_plane_in_state(state, plane,
+                                            old_plane_state,
+                                            new_plane_state, i) {
+               if (new_plane_state->base.crtc != &crtc->base &&
                     old_plane_state->base.crtc != &crtc->base)
                         continue;
   
-               if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
+               if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
                         dirty |= BIT(plane->id);
         }
   
@@@ -1831,21 -1836,21 +1836,21 @@@ static int vlv_compute_pipe_wm(struct i
         int num_active_planes = hweight32(crtc_state->active_planes &
                                           ~BIT(PLANE_CURSOR));
         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
-       struct intel_plane_state *plane_state;
+       const struct intel_plane_state *old_plane_state;
+       const struct intel_plane_state *new_plane_state;
         struct intel_plane *plane;
         enum plane_id plane_id;
         int level, ret, i;
         unsigned int dirty = 0;
   
-       for_each_intel_plane_in_state(state, plane, plane_state, i) {
-               const struct intel_plane_state *old_plane_state =
-                       to_intel_plane_state(plane->base.state);
- 
-               if (plane_state->base.crtc != &crtc->base &&
+       for_each_oldnew_intel_plane_in_state(state, plane,
+                                            old_plane_state,
+                                            new_plane_state, i) {
+               if (new_plane_state->base.crtc != &crtc->base &&
                     old_plane_state->base.crtc != &crtc->base)
                         continue;
   
-               if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
+               if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
                         dirty |= BIT(plane->id);
         }
   
@@@ -1864,7 -1869,7 +1869,7 @@@
         /* cursor changes don't warrant a FIFO recompute */
         if (dirty & ~BIT(PLANE_CURSOR)) {
                 const struct intel_crtc_state *old_crtc_state =
-                       to_intel_crtc_state(crtc->base.state);
+                       intel_atomic_get_old_crtc_state(state, crtc);
                 const struct vlv_fifo_state *old_fifo_state =
                         &old_crtc_state->wm.vlv.fifo_state;
   
@@@ -2716,9 -2721,9 +2721,9 @@@ static void ilk_compute_wm_level(const 
                                  const struct intel_crtc *intel_crtc,
                                  int level,
                                  struct intel_crtc_state *cstate,
- -                               struct intel_plane_state *pristate,
- -                               struct intel_plane_state *sprstate,
- -                               struct intel_plane_state *curstate,
+ +                               const struct intel_plane_state *pristate,
+ +                               const struct intel_plane_state *sprstate,
+ +                               const struct intel_plane_state *curstate,
                                  struct intel_wm_level *result)
   {
         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
@@@ -2785,11 -2790,11 +2790,11 @@@ static void intel_read_wm_latency(struc
   
                 /* read the first set of memory latencies[0:3] */
                 val = 0; /* data0 to be programmed to 0 for first set */
-               mutex_lock(&dev_priv->rps.hw_lock);
+               mutex_lock(&dev_priv->pcu_lock);
                 ret = sandybridge_pcode_read(dev_priv,
                                              GEN9_PCODE_READ_MEM_LATENCY,
                                              &val);
-               mutex_unlock(&dev_priv->rps.hw_lock);
+               mutex_unlock(&dev_priv->pcu_lock);
   
                 if (ret) {
                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
@@@ -2806,11 -2811,11 +2811,11 @@@
   
                 /* read the second set of memory latencies[4:7] */
                 val = 1; /* data0 to be programmed to 1 for second set */
-               mutex_lock(&dev_priv->rps.hw_lock);
+               mutex_lock(&dev_priv->pcu_lock);
                 ret = sandybridge_pcode_read(dev_priv,
                                              GEN9_PCODE_READ_MEM_LATENCY,
                                              &val);
-               mutex_unlock(&dev_priv->rps.hw_lock);
+               mutex_unlock(&dev_priv->pcu_lock);
                 if (ret) {
                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
                         return;
@@@ -3038,24 -3043,28 +3043,24 @@@ static int ilk_compute_pipe_wm(struct i
         struct intel_pipe_wm *pipe_wm;
         struct drm_device *dev = state->dev;
         const struct drm_i915_private *dev_priv = to_i915(dev);
- -      struct intel_plane *intel_plane;
- -      struct intel_plane_state *pristate = NULL;
- -      struct intel_plane_state *sprstate = NULL;
- -      struct intel_plane_state *curstate = NULL;
+ +      struct drm_plane *plane;
+ +      const struct drm_plane_state *plane_state;
+ +      const struct intel_plane_state *pristate = NULL;
+ +      const struct intel_plane_state *sprstate = NULL;
+ +      const struct intel_plane_state *curstate = NULL;
         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
         struct ilk_wm_maximums max;
   
         pipe_wm = &cstate->wm.ilk.optimal;
   
- -      for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- -              struct intel_plane_state *ps;
+ +      drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
+ +              const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
   
- -              ps = intel_atomic_get_existing_plane_state(state,
- -                                                         intel_plane);
- -              if (!ps)
- -                      continue;
- -
- -              if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
+ +              if (plane->type == DRM_PLANE_TYPE_PRIMARY)
                         pristate = ps;
- -              else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
+ +              else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
                         sprstate = ps;
- -              else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ +              else if (plane->type == DRM_PLANE_TYPE_CURSOR)
                         curstate = ps;
         }
   
@@@ -3077,9 -3086,11 +3082,9 @@@
         if (pipe_wm->sprites_scaled)
                 usable_level = 0;
   
- -      ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
- -                           pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
- -
         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
- -      pipe_wm->wm[0] = pipe_wm->raw_wm[0];
+ +      ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
+ +                           pristate, sprstate, curstate, &pipe_wm->wm[0]);
   
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
@@@ -3089,8 -3100,8 +3094,8 @@@
   
         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
   
- -      for (level = 1; level <= max_level; level++) {
- -              struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
+ +      for (level = 1; level <= usable_level; level++) {
+ +              struct intel_wm_level *wm = &pipe_wm->wm[level];
   
                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
                                      pristate, sprstate, curstate, wm);
@@@ -3100,10 -3111,13 +3105,10 @@@
                  * register maximums since such watermarks are
                  * always invalid.
                  */
- -              if (level > usable_level)
- -                      continue;
- -
- -              if (ilk_validate_wm_level(level, &max, wm))
- -                      pipe_wm->wm[level] = *wm;
- -              else
- -                      usable_level = level;
+ +              if (!ilk_validate_wm_level(level, &max, wm)) {
+ +                      memset(wm, 0, sizeof(*wm));
+ +                      break;
+ +              }
         }
   
         return 0;
@@@ -3119,7 -3133,11 +3124,11 @@@ static int ilk_compute_intermediate_wm(
                                        struct intel_crtc_state *newstate)
   {
         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
-       struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
+       struct intel_atomic_state *intel_state =
+               to_intel_atomic_state(newstate->base.state);
+       const struct intel_crtc_state *oldstate =
+               intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
+       const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
         int level, max_level = ilk_wm_max_level(to_i915(dev));
   
         /*
@@@ -3128,6 -3146,9 +3137,9 @@@
          * and after the vblank.
          */
         *a = newstate->wm.ilk.optimal;
+       if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base))
+               return 0;
+ 
         a->pipe_enabled |= b->pipe_enabled;
         a->sprites_enabled |= b->sprites_enabled;
         a->sprites_scaled |= b->sprites_scaled;
@@@ -3594,13 -3615,13 +3606,13 @@@ intel_enable_sagv(struct drm_i915_priva
                 return 0;
   
         DRM_DEBUG_KMS("Enabling the SAGV\n");
-       mutex_lock(&dev_priv->rps.hw_lock);
+       mutex_lock(&dev_priv->pcu_lock);
   
         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
                                       GEN9_SAGV_ENABLE);
   
         /* We don't need to wait for the SAGV when enabling */
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   
         /*
          * Some skl systems, pre-release machines in particular,
@@@ -3631,14 -3652,14 +3643,14 @@@ intel_disable_sagv(struct drm_i915_priv
                 return 0;
   
         DRM_DEBUG_KMS("Disabling the SAGV\n");
-       mutex_lock(&dev_priv->rps.hw_lock);
+       mutex_lock(&dev_priv->pcu_lock);
   
         /* bspec says to keep retrying for at least 1 ms */
         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
                                 GEN9_SAGV_DISABLE,
                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
                                 1);
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   
         /*
          * Some skl systems, pre-release machines in particular,
@@@ -4361,134 -4382,147 +4373,147 @@@ skl_adjusted_plane_pixel_rate(const str
                                             downscale_amount);
   }
   
- static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
-                               struct intel_crtc_state *cstate,
-                               const struct intel_plane_state *intel_pstate,
-                               uint16_t ddb_allocation,
-                               int level,
-                               uint16_t *out_blocks, /* out */
-                               uint8_t *out_lines, /* out */
-                               bool *enabled /* out */)
+ static int
+ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
+                           struct intel_crtc_state *cstate,
+                           const struct intel_plane_state *intel_pstate,
+                           struct skl_wm_params *wp)
   {
         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
         const struct drm_plane_state *pstate = &intel_pstate->base;
         const struct drm_framebuffer *fb = pstate->fb;
-       uint32_t latency = dev_priv->wm.skl_latency[level];
-       uint_fixed_16_16_t method1, method2;
-       uint_fixed_16_16_t plane_blocks_per_line;
-       uint_fixed_16_16_t selected_result;
         uint32_t interm_pbpl;
-       uint32_t plane_bytes_per_line;
-       uint32_t res_blocks, res_lines;
-       uint8_t cpp;
-       uint32_t width = 0;
-       uint32_t plane_pixel_rate;
-       uint_fixed_16_16_t y_tile_minimum;
-       uint32_t y_min_scanlines;
         struct intel_atomic_state *state =
                 to_intel_atomic_state(cstate->base.state);
         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
-       bool y_tiled, x_tiled;
   
-       if (latency == 0 ||
-           !intel_wm_plane_visible(cstate, intel_pstate)) {
-               *enabled = false;
+       if (!intel_wm_plane_visible(cstate, intel_pstate))
                 return 0;
-       }
- 
-       y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-                 fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
-                 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-                 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-       x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
- 
-       /* Display WA #1141: kbl,cfl */
-       if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
-           dev_priv->ipc_enabled)
-               latency += 4;
   
-       if (apply_memory_bw_wa && x_tiled)
-               latency += 15;
+       wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+                     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
+                     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+                     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+       wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
+       wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+                        fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
   
         if (plane->id == PLANE_CURSOR) {
-               width = intel_pstate->base.crtc_w;
+               wp->width = intel_pstate->base.crtc_w;
         } else {
                 /*
                  * Src coordinates are already rotated by 270 degrees for
                  * the 90/270 degree plane rotation cases (to match the
                  * GTT mapping), hence no need to account for rotation here.
                  */
-               width = drm_rect_width(&intel_pstate->base.src) >> 16;
+               wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
         }
   
-       cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
-                                                       fb->format->cpp[0];
-       plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
+       wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
+                                                           fb->format->cpp[0];
+       wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
+                                                            intel_pstate);
   
         if (drm_rotation_90_or_270(pstate->rotation)) {
   
-               switch (cpp) {
+               switch (wp->cpp) {
                 case 1:
-                       y_min_scanlines = 16;
+                       wp->y_min_scanlines = 16;
                         break;
                 case 2:
-                       y_min_scanlines = 8;
+                       wp->y_min_scanlines = 8;
                         break;
                 case 4:
-                       y_min_scanlines = 4;
+                       wp->y_min_scanlines = 4;
                         break;
                 default:
-                       MISSING_CASE(cpp);
+                       MISSING_CASE(wp->cpp);
                         return -EINVAL;
                 }
         } else {
-               y_min_scanlines = 4;
+               wp->y_min_scanlines = 4;
         }
   
         if (apply_memory_bw_wa)
-               y_min_scanlines *= 2;
+               wp->y_min_scanlines *= 2;
   
-       plane_bytes_per_line = width * cpp;
-       if (y_tiled) {
-               interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
-                                          y_min_scanlines, 512);
+       wp->plane_bytes_per_line = wp->width * wp->cpp;
+       if (wp->y_tiled) {
+               interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
+                                          wp->y_min_scanlines, 512);
   
                 if (INTEL_GEN(dev_priv) >= 10)
                         interm_pbpl++;
   
-               plane_blocks_per_line = div_fixed16(interm_pbpl,
-                                                       y_min_scanlines);
-       } else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
-               interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
-               plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
+               wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
+                                                       wp->y_min_scanlines);
+       } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
+               interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
+               wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
         } else {
-               interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
-               plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
+               interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
+               wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
+       }
+ 
+       wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
+                                            wp->plane_blocks_per_line);
+       wp->linetime_us = fixed16_to_u32_round_up(
+                                       intel_get_linetime_us(cstate));
+ 
+       return 0;
+ }
+ 
+ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
+                               struct intel_crtc_state *cstate,
+                               const struct intel_plane_state *intel_pstate,
+                               uint16_t ddb_allocation,
+                               int level,
+                               const struct skl_wm_params *wp,
+                               uint16_t *out_blocks, /* out */
+                               uint8_t *out_lines, /* out */
+                               bool *enabled /* out */)
+ {
+       const struct drm_plane_state *pstate = &intel_pstate->base;
+       uint32_t latency = dev_priv->wm.skl_latency[level];
+       uint_fixed_16_16_t method1, method2;
+       uint_fixed_16_16_t selected_result;
+       uint32_t res_blocks, res_lines;
+       struct intel_atomic_state *state =
+               to_intel_atomic_state(cstate->base.state);
+       bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+ 
+       if (latency == 0 ||
+           !intel_wm_plane_visible(cstate, intel_pstate)) {
+               *enabled = false;
+               return 0;
         }
   
-       method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
-       method2 = skl_wm_method2(plane_pixel_rate,
+       /* Display WA #1141: kbl,cfl */
+       if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
+           IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
+           dev_priv->ipc_enabled)
+               latency += 4;
+ 
+       if (apply_memory_bw_wa && wp->x_tiled)
+               latency += 15;
+ 
+       method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
+                                wp->cpp, latency);
+       method2 = skl_wm_method2(wp->plane_pixel_rate,
                                  cstate->base.adjusted_mode.crtc_htotal,
                                  latency,
-                                plane_blocks_per_line);
- 
-       y_tile_minimum = mul_u32_fixed16(y_min_scanlines,
-                                        plane_blocks_per_line);
+                                wp->plane_blocks_per_line);
   
-       if (y_tiled) {
-               selected_result = max_fixed16(method2, y_tile_minimum);
+       if (wp->y_tiled) {
+               selected_result = max_fixed16(method2, wp->y_tile_minimum);
         } else {
-               uint32_t linetime_us;
- 
-               linetime_us = fixed16_to_u32_round_up(
-                               intel_get_linetime_us(cstate));
-               if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
-                   (plane_bytes_per_line / 512 < 1))
+               if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
+                    512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
                         selected_result = method2;
                 else if (ddb_allocation >=
-                        fixed16_to_u32_round_up(plane_blocks_per_line))
+                        fixed16_to_u32_round_up(wp->plane_blocks_per_line))
                         selected_result = min_fixed16(method1, method2);
-               else if (latency >= linetime_us)
+               else if (latency >= wp->linetime_us)
                         selected_result = min_fixed16(method1, method2);
                 else
                         selected_result = method1;
@@@ -4496,19 -4530,18 +4521,18 @@@
   
         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
         res_lines = div_round_up_fixed16(selected_result,
-                                        plane_blocks_per_line);
+                                        wp->plane_blocks_per_line);
   
         /* Display WA #1125: skl,bxt,kbl,glk */
-       if (level == 0 &&
-           (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-            fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
-               res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
+       if (level == 0 && wp->rc_surface)
+               res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
   
         /* Display WA #1126: skl,bxt,kbl,glk */
         if (level >= 1 && level <= 7) {
-               if (y_tiled) {
-                       res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
-                       res_lines += y_min_scanlines;
+               if (wp->y_tiled) {
+                       res_blocks += fixed16_to_u32_round_up(
+                                                       wp->y_tile_minimum);
+                       res_lines += wp->y_min_scanlines;
                 } else {
                         res_blocks++;
                 }
@@@ -4546,6 -4579,7 +4570,7 @@@ skl_compute_wm_levels(const struct drm_
                       struct skl_ddb_allocation *ddb,
                       struct intel_crtc_state *cstate,
                       const struct intel_plane_state *intel_pstate,
+                     const struct skl_wm_params *wm_params,
                       struct skl_plane_wm *wm)
   {
         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
@@@ -4569,6 -4603,7 +4594,7 @@@
                                            intel_pstate,
                                            ddb_blocks,
                                            level,
+                                          wm_params,
                                            &result->plane_res_b,
                                            &result->plane_res_l,
                                            &result->plane_en);
@@@ -4594,20 -4629,65 +4620,65 @@@ skl_compute_linetime_wm(struct intel_cr
   
         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
   
-       /* Display WA #1135: bxt. */
-       if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
-               linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
+       /* Display WA #1135: bxt:ALL GLK:ALL */
+       if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) &&
+           dev_priv->ipc_enabled)
+               linetime_wm /= 2;
   
         return linetime_wm;
   }
   
   static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
+                                     struct skl_wm_params *wp,
+                                     struct skl_wm_level *wm_l0,
+                                     uint16_t ddb_allocation,
                                       struct skl_wm_level *trans_wm /* out */)
   {
+       struct drm_device *dev = cstate->base.crtc->dev;
+       const struct drm_i915_private *dev_priv = to_i915(dev);
+       uint16_t trans_min, trans_y_tile_min;
+       const uint16_t trans_amount = 10; /* This is configurable amount */
+       uint16_t trans_offset_b, res_blocks;
+ 
         if (!cstate->base.active)
+               goto exit;
+ 
+       /* Transition WM are not recommended by HW team for GEN9 */
+       if (INTEL_GEN(dev_priv) <= 9)
+               goto exit;
+ 
+       /* Transition WM don't make any sense if ipc is disabled */
+       if (!dev_priv->ipc_enabled)
+               goto exit;
+ 
+       if (INTEL_GEN(dev_priv) >= 10)
+               trans_min = 4;
+ 
+       trans_offset_b = trans_min + trans_amount;
+ 
+       if (wp->y_tiled) {
+               trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
+                                                       wp->y_tile_minimum);
+               res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
+                               trans_offset_b;
+       } else {
+               res_blocks = wm_l0->plane_res_b + trans_offset_b;
+ 
+               /* WA BUG:1938466 add one block for non y-tile planes */
+               if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+                       res_blocks += 1;
+ 
+       }
+ 
+       res_blocks += 1;
+ 
+       if (res_blocks < ddb_allocation) {
+               trans_wm->plane_res_b = res_blocks;
+               trans_wm->plane_en = true;
                 return;
+       }
   
-       /* Until we know more, just disable transition WMs */
+ exit:
         trans_wm->plane_en = false;
   }
   
@@@ -4633,14 -4713,25 +4704,25 @@@ static int skl_build_pipe_wm(struct int
                 const struct intel_plane_state *intel_pstate =
                                                 to_intel_plane_state(pstate);
                 enum plane_id plane_id = to_intel_plane(plane)->id;
+               struct skl_wm_params wm_params;
+               enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
+               uint16_t ddb_blocks;
   
                 wm = &pipe_wm->planes[plane_id];
+               ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+               memset(&wm_params, 0, sizeof(struct skl_wm_params));
+ 
+               ret = skl_compute_plane_wm_params(dev_priv, cstate,
+                                                 intel_pstate, &wm_params);
+               if (ret)
+                       return ret;
   
                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
-                                           intel_pstate, wm);
+                                           intel_pstate, &wm_params, wm);
                 if (ret)
                         return ret;
-               skl_compute_transition_wm(cstate, &wm->trans_wm);
+               skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
+                                         ddb_blocks, &wm->trans_wm);
         }
         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
   
@@@ -4736,16 -4827,18 +4818,18 @@@ static inline bool skl_ddb_entries_over
         return a->start < b->end && b->start < a->end;
   }
   
- bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
+ bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
+                                const struct skl_ddb_entry **entries,
                                  const struct skl_ddb_entry *ddb,
                                  int ignore)
   {
-       int i;
+       enum pipe pipe;
   
-       for (i = 0; i < I915_MAX_PIPES; i++)
-               if (i != ignore && entries[i] &&
-                   skl_ddb_entries_overlap(ddb, entries[i]))
+       for_each_pipe(dev_priv, pipe) {
+               if (pipe != ignore && entries[pipe] &&
+                   skl_ddb_entries_overlap(ddb, entries[pipe]))
                         return true;
+       }
   
         return false;
   }
@@@ -5535,7 -5628,7 +5619,7 @@@ void vlv_wm_get_hw_state(struct drm_dev
         wm->level = VLV_WM_LEVEL_PM2;
   
         if (IS_CHERRYVIEW(dev_priv)) {
-               mutex_lock(&dev_priv->rps.hw_lock);
+               mutex_lock(&dev_priv->pcu_lock);
   
                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
                 if (val & DSP_MAXFIFO_PM5_ENABLE)
@@@ -5565,7 -5658,7 +5649,7 @@@
                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
                 }
   
-               mutex_unlock(&dev_priv->rps.hw_lock);
+               mutex_unlock(&dev_priv->pcu_lock);
         }
   
         for_each_intel_crtc(dev, crtc) {
@@@ -5669,12 -5762,30 +5753,30 @@@ void vlv_wm_sanitize(struct drm_i915_pr
         mutex_unlock(&dev_priv->wm.wm_mutex);
   }
   
+ /*
+  * FIXME should probably kill this and improve
+  * the real watermark readout/sanitation instead
+  */
+ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
+ {
+       I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
+       I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
+       I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
+ 
+       /*
+        * Don't touch WM1S_LP_EN here.
+        * Doing so could cause underruns.
+        */
+ }
+ 
   void ilk_wm_get_hw_state(struct drm_device *dev)
   {
         struct drm_i915_private *dev_priv = to_i915(dev);
         struct ilk_wm_values *hw = &dev_priv->wm.hw;
         struct drm_crtc *crtc;
   
+       ilk_init_lp_watermarks(dev_priv);
+ 
         for_each_crtc(dev, crtc)
                 ilk_pipe_wm_get_hw_state(crtc);
   
@@@ -5739,6 -5850,36 +5841,36 @@@ void intel_update_watermarks(struct int
                 dev_priv->display.update_wm(crtc);
   }
   
+ void intel_enable_ipc(struct drm_i915_private *dev_priv)
+ {
+       u32 val;
+ 
+       /* Display WA #0477 WaDisableIPC: skl */
+       if (IS_SKYLAKE(dev_priv)) {
+               dev_priv->ipc_enabled = false;
+               return;
+       }
+ 
+       val = I915_READ(DISP_ARB_CTL2);
+ 
+       if (dev_priv->ipc_enabled)
+               val |= DISP_IPC_ENABLE;
+       else
+               val &= ~DISP_IPC_ENABLE;
+ 
+       I915_WRITE(DISP_ARB_CTL2, val);
+ }
+ 
+ void intel_init_ipc(struct drm_i915_private *dev_priv)
+ {
+       dev_priv->ipc_enabled = false;
+       if (!HAS_IPC(dev_priv))
+               return;
+ 
+       dev_priv->ipc_enabled = true;
+       intel_enable_ipc(dev_priv);
+ }
+ 
   /*
    * Lock protecting IPS related data structures
    */
@@@ -5872,6 -6013,7 +6004,7 @@@ static void ironlake_disable_drps(struc
    */
   static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         u32 limits;
   
         /* Only set the down limit when we've reached the lowest level to avoid
@@@ -5881,13 -6023,13 +6014,13 @@@
          * frequency, if the down threshold expires in that window we will not
          * receive a down interrupt. */
         if (INTEL_GEN(dev_priv) >= 9) {
-               limits = (dev_priv->rps.max_freq_softlimit) << 23;
-               if (val <= dev_priv->rps.min_freq_softlimit)
-                       limits |= (dev_priv->rps.min_freq_softlimit) << 14;
+               limits = (rps->max_freq_softlimit) << 23;
+               if (val <= rps->min_freq_softlimit)
+                       limits |= (rps->min_freq_softlimit) << 14;
         } else {
-               limits = dev_priv->rps.max_freq_softlimit << 24;
-               if (val <= dev_priv->rps.min_freq_softlimit)
-                       limits |= dev_priv->rps.min_freq_softlimit << 16;
+               limits = rps->max_freq_softlimit << 24;
+               if (val <= rps->min_freq_softlimit)
+                       limits |= rps->min_freq_softlimit << 16;
         }
   
         return limits;
@@@ -5895,39 -6037,40 +6028,40 @@@
   
   static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         int new_power;
         u32 threshold_up = 0, threshold_down = 0; /* in % */
         u32 ei_up = 0, ei_down = 0;
   
-       new_power = dev_priv->rps.power;
-       switch (dev_priv->rps.power) {
+       new_power = rps->power;
+       switch (rps->power) {
         case LOW_POWER:
-               if (val > dev_priv->rps.efficient_freq + 1 &&
-                   val > dev_priv->rps.cur_freq)
+               if (val > rps->efficient_freq + 1 &&
+                   val > rps->cur_freq)
                         new_power = BETWEEN;
                 break;
   
         case BETWEEN:
-               if (val <= dev_priv->rps.efficient_freq &&
-                   val < dev_priv->rps.cur_freq)
+               if (val <= rps->efficient_freq &&
+                   val < rps->cur_freq)
                         new_power = LOW_POWER;
-               else if (val >= dev_priv->rps.rp0_freq &&
-                        val > dev_priv->rps.cur_freq)
+               else if (val >= rps->rp0_freq &&
+                        val > rps->cur_freq)
                         new_power = HIGH_POWER;
                 break;
   
         case HIGH_POWER:
-               if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
-                   val < dev_priv->rps.cur_freq)
+               if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
+                   val < rps->cur_freq)
                         new_power = BETWEEN;
                 break;
         }
         /* Max/min bins are special */
-       if (val <= dev_priv->rps.min_freq_softlimit)
+       if (val <= rps->min_freq_softlimit)
                 new_power = LOW_POWER;
-       if (val >= dev_priv->rps.max_freq_softlimit)
+       if (val >= rps->max_freq_softlimit)
                 new_power = HIGH_POWER;
-       if (new_power == dev_priv->rps.power)
+       if (new_power == rps->power)
                 return;
   
         /* Note the units here are not exactly 1us, but 1280ns. */
@@@ -5990,20 -6133,21 +6124,21 @@@
                    GEN6_RP_DOWN_IDLE_AVG);
   
   skip_hw_write:
-       dev_priv->rps.power = new_power;
-       dev_priv->rps.up_threshold = threshold_up;
-       dev_priv->rps.down_threshold = threshold_down;
-       dev_priv->rps.last_adj = 0;
+       rps->power = new_power;
+       rps->up_threshold = threshold_up;
+       rps->down_threshold = threshold_down;
+       rps->last_adj = 0;
   }
   
   static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         u32 mask = 0;
   
         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
-       if (val > dev_priv->rps.min_freq_softlimit)
+       if (val > rps->min_freq_softlimit)
                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
-       if (val < dev_priv->rps.max_freq_softlimit)
+       if (val < rps->max_freq_softlimit)
                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
   
         mask &= dev_priv->pm_rps_events;
@@@ -6016,10 -6160,12 +6151,12 @@@
    * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
   static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /* min/max delay may still have been modified so be sure to
          * write the limits value.
          */
-       if (val != dev_priv->rps.cur_freq) {
+       if (val != rps->cur_freq) {
                 gen6_set_rps_thresholds(dev_priv, val);
   
                 if (INTEL_GEN(dev_priv) >= 9)
@@@ -6041,7 -6187,7 +6178,7 @@@
         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
   
-       dev_priv->rps.cur_freq = val;
+       rps->cur_freq = val;
         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
   
         return 0;
@@@ -6057,7 -6203,7 +6194,7 @@@ static int valleyview_set_rps(struct dr
   
         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
   
-       if (val != dev_priv->rps.cur_freq) {
+       if (val != dev_priv->gt_pm.rps.cur_freq) {
                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
                 if (err)
                         return err;
@@@ -6065,7 -6211,7 +6202,7 @@@
                 gen6_set_rps_thresholds(dev_priv, val);
         }
   
-       dev_priv->rps.cur_freq = val;
+       dev_priv->gt_pm.rps.cur_freq = val;
         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
   
         return 0;
@@@ -6080,10 -6226,11 +6217,11 @@@
   */
   static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
   {
-       u32 val = dev_priv->rps.idle_freq;
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+       u32 val = rps->idle_freq;
         int err;
   
-       if (dev_priv->rps.cur_freq <= val)
+       if (rps->cur_freq <= val)
                 return;
   
         /* The punit delays the write of the frequency and voltage until it
@@@ -6108,34 -6255,38 +6246,38 @@@
   
   void gen6_rps_busy(struct drm_i915_private *dev_priv)
   {
-       mutex_lock(&dev_priv->rps.hw_lock);
-       if (dev_priv->rps.enabled) {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
+       mutex_lock(&dev_priv->pcu_lock);
+       if (rps->enabled) {
                 u8 freq;
   
                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
                         gen6_rps_reset_ei(dev_priv);
                 I915_WRITE(GEN6_PMINTRMSK,
-                          gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
+                          gen6_rps_pm_mask(dev_priv, rps->cur_freq));
   
                 gen6_enable_rps_interrupts(dev_priv);
   
                 /* Use the user's desired frequency as a guide, but for better
                  * performance, jump directly to RPe as our starting frequency.
                  */
-               freq = max(dev_priv->rps.cur_freq,
-                          dev_priv->rps.efficient_freq);
+               freq = max(rps->cur_freq,
+                          rps->efficient_freq);
   
                 if (intel_set_rps(dev_priv,
                                   clamp(freq,
-                                       dev_priv->rps.min_freq_softlimit,
-                                       dev_priv->rps.max_freq_softlimit)))
+                                       rps->min_freq_softlimit,
+                                       rps->max_freq_softlimit)))
                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
         }
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   }
   
   void gen6_rps_idle(struct drm_i915_private *dev_priv)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /* Flush our bottom-half so that it does not race with us
          * setting the idle frequency and so that it is bounded by
          * our rpm wakeref. And then disable the interrupts to stop any
@@@ -6143,58 -6294,60 +6285,60 @@@
          */
         gen6_disable_rps_interrupts(dev_priv);
   
-       mutex_lock(&dev_priv->rps.hw_lock);
-       if (dev_priv->rps.enabled) {
+       mutex_lock(&dev_priv->pcu_lock);
+       if (rps->enabled) {
                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                         vlv_set_rps_idle(dev_priv);
                 else
-                       gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
-               dev_priv->rps.last_adj = 0;
+                       gen6_set_rps(dev_priv, rps->idle_freq);
+               rps->last_adj = 0;
                 I915_WRITE(GEN6_PMINTRMSK,
                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
         }
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   }
   
   void gen6_rps_boost(struct drm_i915_gem_request *rq,
-                   struct intel_rps_client *rps)
+                   struct intel_rps_client *rps_client)
   {
-       struct drm_i915_private *i915 = rq->i915;
+       struct intel_rps *rps = &rq->i915->gt_pm.rps;
+       unsigned long flags;
         bool boost;
   
         /* This is intentionally racy! We peek at the state here, then
          * validate inside the RPS worker.
          */
-       if (!i915->rps.enabled)
+       if (!rps->enabled)
                 return;
   
         boost = false;
-       spin_lock_irq(&rq->lock);
+       spin_lock_irqsave(&rq->lock, flags);
         if (!rq->waitboost && !i915_gem_request_completed(rq)) {
-               atomic_inc(&i915->rps.num_waiters);
+               atomic_inc(&rps->num_waiters);
                 rq->waitboost = true;
                 boost = true;
         }
-       spin_unlock_irq(&rq->lock);
+       spin_unlock_irqrestore(&rq->lock, flags);
         if (!boost)
                 return;
   
-       if (READ_ONCE(i915->rps.cur_freq) < i915->rps.boost_freq)
-               schedule_work(&i915->rps.work);
+       if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
+               schedule_work(&rps->work);
   
-       atomic_inc(rps ? &rps->boosts : &i915->rps.boosts);
+       atomic_inc(rps_client ? &rps_client->boosts : &rps->boosts);
   }
   
   int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         int err;
   
-       lockdep_assert_held(&dev_priv->rps.hw_lock);
-       GEM_BUG_ON(val > dev_priv->rps.max_freq);
-       GEM_BUG_ON(val < dev_priv->rps.min_freq);
+       lockdep_assert_held(&dev_priv->pcu_lock);
+       GEM_BUG_ON(val > rps->max_freq);
+       GEM_BUG_ON(val < rps->min_freq);
   
-       if (!dev_priv->rps.enabled) {
-               dev_priv->rps.cur_freq = val;
+       if (!rps->enabled) {
+               rps->cur_freq = val;
                 return 0;
         }
   
@@@ -6217,21 -6370,30 +6361,30 @@@ static void gen9_disable_rps(struct drm
         I915_WRITE(GEN6_RP_CONTROL, 0);
   }
   
- static void gen6_disable_rps(struct drm_i915_private *dev_priv)
+ static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
   {
         I915_WRITE(GEN6_RC_CONTROL, 0);
+ }
+ 
+ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
+ {
         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
         I915_WRITE(GEN6_RP_CONTROL, 0);
   }
   
- static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+ static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
   {
         I915_WRITE(GEN6_RC_CONTROL, 0);
   }
   
- static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
+ static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
   {
-       /* we're doing forcewake before Disabling RC6,
+       I915_WRITE(GEN6_RP_CONTROL, 0);
+ }
+ 
+ static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
+ {
+       /* We're doing forcewake before Disabling RC6,
          * This what the BIOS expects when going into suspend */
         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
   
@@@ -6240,6 -6402,11 +6393,11 @@@
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
   }
   
+ static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
+ {
+       I915_WRITE(GEN6_RP_CONTROL, 0);
+ }
+ 
   static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
   {
         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@@ -6362,24 -6529,26 +6520,26 @@@ int sanitize_rc6_option(struct drm_i915
   
   static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /* All of these values are in units of 50MHz */
   
         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
         if (IS_GEN9_LP(dev_priv)) {
                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
-               dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
-               dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
-               dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
+               rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
+               rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
+               rps->min_freq = (rp_state_cap >>  0) & 0xff;
         } else {
                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-               dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
-               dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
-               dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
+               rps->rp0_freq = (rp_state_cap >>  0) & 0xff;
+               rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
+               rps->min_freq = (rp_state_cap >> 16) & 0xff;
         }
         /* hw_max = RP0 until we check for overclocking */
-       dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
+       rps->max_freq = rps->rp0_freq;
   
-       dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
+       rps->efficient_freq = rps->rp1_freq;
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
             IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
                 u32 ddcc_status = 0;
@@@ -6387,33 -6556,34 +6547,34 @@@
                 if (sandybridge_pcode_read(dev_priv,
                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
                                            &ddcc_status) == 0)
-                       dev_priv->rps.efficient_freq =
+                       rps->efficient_freq =
                                 clamp_t(u8,
                                         ((ddcc_status >> 8) & 0xff),
-                                       dev_priv->rps.min_freq,
-                                       dev_priv->rps.max_freq);
+                                       rps->min_freq,
+                                       rps->max_freq);
         }
   
         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
                 /* Store the frequency values in 16.66 MHZ units, which is
                  * the natural hardware unit for SKL
                  */
-               dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
-               dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
-               dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
-               dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
-               dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
+               rps->rp0_freq *= GEN9_FREQ_SCALER;
+               rps->rp1_freq *= GEN9_FREQ_SCALER;
+               rps->min_freq *= GEN9_FREQ_SCALER;
+               rps->max_freq *= GEN9_FREQ_SCALER;
+               rps->efficient_freq *= GEN9_FREQ_SCALER;
         }
   }
   
   static void reset_rps(struct drm_i915_private *dev_priv,
                       int (*set)(struct drm_i915_private *, u8))
   {
-       u8 freq = dev_priv->rps.cur_freq;
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+       u8 freq = rps->cur_freq;
   
         /* force a reset */
-       dev_priv->rps.power = -1;
-       dev_priv->rps.cur_freq = -1;
+       rps->power = -1;
+       rps->cur_freq = -1;
   
         if (set(dev_priv, freq))
                 DRM_ERROR("Failed to reset RPS to initial values\n");
@@@ -6426,7 -6596,7 +6587,7 @@@ static void gen9_enable_rps(struct drm_
   
         /* Program defaults and thresholds for RPS*/
         I915_WRITE(GEN6_RC_VIDEO_FREQ,
-               GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
+               GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
   
         /* 1 second timeout*/
         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
@@@ -6446,7 -6616,7 +6607,7 @@@ static void gen9_enable_rc6(struct drm_
   {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
-       uint32_t rc6_mask = 0;
+       u32 rc6_mode, rc6_mask = 0;
   
         /* 1a: Software RC state - RC0 */
         I915_WRITE(GEN6_RC_STATE, 0);
@@@ -6480,12 -6650,19 +6641,19 @@@
         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
   
         /* 3a: Enable RC6 */
-       if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+       if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+ 
+       /* WaRsUseTimeoutMode:cnl (pre-prod) */
+       if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
+               rc6_mode = GEN7_RC_CTL_TO_MODE;
+       else
+               rc6_mode = GEN6_RC_CTL_EI_MODE(1);
+ 
         I915_WRITE(GEN6_RC_CONTROL,
-                  GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
+                  GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask);
   
         /*
          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
@@@ -6500,7 -6677,7 +6668,7 @@@
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
   }
   
- static void gen8_enable_rps(struct drm_i915_private *dev_priv)
+ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
   {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
@@@ -6509,7 -6686,7 +6677,7 @@@
         /* 1a: Software RC state - RC0 */
         I915_WRITE(GEN6_RC_STATE, 0);
   
-       /* 1c & 1d: Get forcewake during program sequence. Although the driver
+       /* 1b: Get forcewake during program sequence. Although the driver
          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
   
@@@ -6523,36 -6700,38 +6691,38 @@@
         for_each_engine(engine, dev_priv, id)
                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
         I915_WRITE(GEN6_RC_SLEEP, 0);
-       if (IS_BROADWELL(dev_priv))
-               I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
-       else
-               I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+       I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
   
         /* 3: Enable RC6 */
-       if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+       if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
         intel_print_rc6_info(dev_priv, rc6_mask);
-       if (IS_BROADWELL(dev_priv))
-               I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-                               GEN7_RC_CTL_TO_MODE |
-                               rc6_mask);
-       else
-               I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-                               GEN6_RC_CTL_EI_MODE(1) |
-                               rc6_mask);
   
-       /* 4 Program defaults and thresholds for RPS*/
+       I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                       GEN7_RC_CTL_TO_MODE |
+                       rc6_mask);
+ 
+       intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ }
+ 
+ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
+ {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
+       intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ 
+       /* 1 Program defaults and thresholds for RPS*/
         I915_WRITE(GEN6_RPNSWREQ,
-                  HSW_FREQUENCY(dev_priv->rps.rp1_freq));
+                  HSW_FREQUENCY(rps->rp1_freq));
         I915_WRITE(GEN6_RC_VIDEO_FREQ,
-                  HSW_FREQUENCY(dev_priv->rps.rp1_freq));
+                  HSW_FREQUENCY(rps->rp1_freq));
         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
   
         /* Docs recommend 900MHz, and 300 MHz respectively */
         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
-                  dev_priv->rps.max_freq_softlimit << 24 |
-                  dev_priv->rps.min_freq_softlimit << 16);
+                  rps->max_freq_softlimit << 24 |
+                  rps->min_freq_softlimit << 16);
   
         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
@@@ -6561,7 -6740,7 +6731,7 @@@
   
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
   
-       /* 5: Enable RPS */
+       /* 2: Enable RPS */
         I915_WRITE(GEN6_RP_CONTROL,
                    GEN6_RP_MEDIA_TURBO |
                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
@@@ -6570,14 -6749,12 +6740,12 @@@
                    GEN6_RP_UP_BUSY_AVG |
                    GEN6_RP_DOWN_IDLE_AVG);
   
-       /* 6: Ring frequency + overclocking (our driver does this later */
- 
         reset_rps(dev_priv, gen6_set_rps);
   
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
   }
   
- static void gen6_enable_rps(struct drm_i915_private *dev_priv)
+ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
   {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
@@@ -6586,14 -6763,6 +6754,6 @@@
         int rc6_mode;
         int ret;
   
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
- 
-       /* Here begins a magic sequence of register writes to enable
-        * auto-downclocking.
-        *
-        * Perhaps there might be some value in exposing these to
-        * userspace...
-        */
         I915_WRITE(GEN6_RC_STATE, 0);
   
         /* Clear the DBG now so we don't confuse earlier errors */
@@@ -6627,7 -6796,7 +6787,7 @@@
         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
   
         /* Check if we are enabling RC6 */
-       rc6_mode = intel_enable_rc6();
+       rc6_mode = intel_rc6_enabled();
         if (rc6_mode & INTEL_RC6_ENABLE)
                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
   
@@@ -6647,12 -6816,6 +6807,6 @@@
                    GEN6_RC_CTL_EI_MODE(1) |
                    GEN6_RC_CTL_HW_ENABLE);
   
-       /* Power down if completely idle for over 50ms */
-       I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
-       I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
- 
-       reset_rps(dev_priv, gen6_set_rps);
- 
         rc6vids = 0;
         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
         if (IS_GEN6(dev_priv) && ret) {
@@@ -6670,8 -6833,28 +6824,28 @@@
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
   }
   
+ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
+ {
+       /* Here begins a magic sequence of register writes to enable
+        * auto-downclocking.
+        *
+        * Perhaps there might be some value in exposing these to
+        * userspace...
+        */
+       intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ 
+       /* Power down if completely idle for over 50ms */
+       I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
+       I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+ 
+       reset_rps(dev_priv, gen6_set_rps);
+ 
+       intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ }
+ 
   static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         int min_freq = 15;
         unsigned int gpu_freq;
         unsigned int max_ia_freq, min_ring_freq;
@@@ -6679,7 -6862,7 +6853,7 @@@
         int scaling_factor = 180;
         struct cpufreq_policy *policy;
   
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+       WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
   
         policy = cpufreq_cpu_get(0);
         if (policy) {
@@@ -6702,11 -6885,11 +6876,11 @@@
   
         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
                 /* Convert GT frequency to 50 HZ units */
-               min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
-               max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
+               min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
+               max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
         } else {
-               min_gpu_freq = dev_priv->rps.min_freq;
-               max_gpu_freq = dev_priv->rps.max_freq;
+               min_gpu_freq = rps->min_freq;
+               max_gpu_freq = rps->max_freq;
         }
   
         /*
@@@ -6957,17 -7140,18 +7131,18 @@@ static void valleyview_cleanup_pctx(str
   
   static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
   {
-       dev_priv->rps.gpll_ref_freq =
+       dev_priv->gt_pm.rps.gpll_ref_freq =
                 vlv_get_cck_clock(dev_priv, "GPLL ref",
                                   CCK_GPLL_CLOCK_CONTROL,
                                   dev_priv->czclk_freq);
   
         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
-                        dev_priv->rps.gpll_ref_freq);
+                        dev_priv->gt_pm.rps.gpll_ref_freq);
   }
   
   static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         u32 val;
   
         valleyview_setup_pctx(dev_priv);
@@@ -6989,30 -7173,31 +7164,31 @@@
         }
         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
   
-       dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
-       dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+       rps->max_freq = valleyview_rps_max_freq(dev_priv);
+       rps->rp0_freq = rps->max_freq;
         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
-                        dev_priv->rps.max_freq);
+                        intel_gpu_freq(dev_priv, rps->max_freq),
+                        rps->max_freq);
   
-       dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
+       rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
-                        dev_priv->rps.efficient_freq);
+                        intel_gpu_freq(dev_priv, rps->efficient_freq),
+                        rps->efficient_freq);
   
-       dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
+       rps->rp1_freq = valleyview_rps_guar_freq(dev_priv);
         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
-                        dev_priv->rps.rp1_freq);
+                        intel_gpu_freq(dev_priv, rps->rp1_freq),
+                        rps->rp1_freq);
   
-       dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
+       rps->min_freq = valleyview_rps_min_freq(dev_priv);
         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
-                        dev_priv->rps.min_freq);
+                        intel_gpu_freq(dev_priv, rps->min_freq),
+                        rps->min_freq);
   }
   
   static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
         u32 val;
   
         cherryview_setup_pctx(dev_priv);
@@@ -7033,31 -7218,29 +7209,29 @@@
         }
         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
   
-       dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
-       dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+       rps->max_freq = cherryview_rps_max_freq(dev_priv);
+       rps->rp0_freq = rps->max_freq;
         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
-                        dev_priv->rps.max_freq);
+                        intel_gpu_freq(dev_priv, rps->max_freq),
+                        rps->max_freq);
   
-       dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+       rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
-                        dev_priv->rps.efficient_freq);
+                        intel_gpu_freq(dev_priv, rps->efficient_freq),
+                        rps->efficient_freq);
   
-       dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
+       rps->rp1_freq = cherryview_rps_guar_freq(dev_priv);
         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
-                        dev_priv->rps.rp1_freq);
+                        intel_gpu_freq(dev_priv, rps->rp1_freq),
+                        rps->rp1_freq);
   
-       dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+       rps->min_freq = cherryview_rps_min_freq(dev_priv);
         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
-                        intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
-                        dev_priv->rps.min_freq);
+                        intel_gpu_freq(dev_priv, rps->min_freq),
+                        rps->min_freq);
   
-       WARN_ONCE((dev_priv->rps.max_freq |
-                  dev_priv->rps.efficient_freq |
-                  dev_priv->rps.rp1_freq |
-                  dev_priv->rps.min_freq) & 1,
+       WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
+                  rps->min_freq) & 1,
                   "Odd GPU freq values\n");
   }
   
@@@ -7066,13 -7249,11 +7240,11 @@@ static void valleyview_cleanup_gt_power
         valleyview_cleanup_pctx(dev_priv);
   }
   
- static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
   {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
-       u32 gtfifodbg, val, rc6_mode = 0, pcbr;
- 
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+       u32 gtfifodbg, rc6_mode = 0, pcbr;
   
         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
                                              GT_FIFO_FREE_ENTRIES_CHV);
@@@ -7103,7 -7284,7 +7275,7 @@@
         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
   
-       /* allows RC6 residency counter to work */
+       /* Allows RC6 residency counter to work */
         I915_WRITE(VLV_COUNTER_CONTROL,
                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
                                       VLV_MEDIA_RC6_COUNT_EN |
@@@ -7113,13 -7294,22 +7285,22 @@@
         pcbr = I915_READ(VLV_PCBR);
   
         /* 3: Enable RC6 */
-       if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
+       if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) &&
             (pcbr >> VLV_PCBR_ADDR_SHIFT))
                 rc6_mode = GEN7_RC_CTL_TO_MODE;
   
         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
   
-       /* 4 Program defaults and thresholds for RPS*/
+       intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ }
+ 
+ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+ {
+       u32 val;
+ 
+       intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ 
+       /* 1: Program defaults and thresholds for RPS*/
         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@@ -7128,7 -7318,7 +7309,7 @@@
   
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
   
-       /* 5: Enable RPS */
+       /* 2: Enable RPS */
         I915_WRITE(GEN6_RP_CONTROL,
                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
                    GEN6_RP_MEDIA_IS_GFX |
@@@ -7155,13 -7345,11 +7336,11 @@@
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
   }
   
- static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
+ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
   {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
-       u32 gtfifodbg, val, rc6_mode = 0;
- 
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+       u32 gtfifodbg, rc6_mode = 0;
   
         valleyview_check_pctx(dev_priv);
   
@@@ -7172,28 -7360,11 +7351,11 @@@
                 I915_WRITE(GTFIFODBG, gtfifodbg);
         }
   
-       /* If VLV, Forcewake all wells, else re-direct to regular path */
         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
   
         /*  Disable RC states. */
         I915_WRITE(GEN6_RC_CONTROL, 0);
   
-       I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
-       I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-       I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
-       I915_WRITE(GEN6_RP_UP_EI, 66000);
-       I915_WRITE(GEN6_RP_DOWN_EI, 350000);
- 
-       I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
- 
-       I915_WRITE(GEN6_RP_CONTROL,
-                  GEN6_RP_MEDIA_TURBO |
-                  GEN6_RP_MEDIA_HW_NORMAL_MODE |
-                  GEN6_RP_MEDIA_IS_GFX |
-                  GEN6_RP_ENABLE |
-                  GEN6_RP_UP_BUSY_AVG |
-                  GEN6_RP_DOWN_IDLE_CONT);
- 
         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
@@@ -7203,7 -7374,7 +7365,7 @@@
   
         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
   
-       /* allows RC6 residency counter to work */
+       /* Allows RC6 residency counter to work */
         I915_WRITE(VLV_COUNTER_CONTROL,
                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
                                       VLV_MEDIA_RC0_COUNT_EN |
@@@ -7211,13 -7382,38 +7373,38 @@@
                                       VLV_MEDIA_RC6_COUNT_EN |
                                       VLV_RENDER_RC6_COUNT_EN));
   
-       if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+       if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
   
         intel_print_rc6_info(dev_priv, rc6_mode);
   
         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
   
+       intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ }
+ 
+ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
+ {
+       u32 val;
+ 
+       intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ 
+       I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
+       I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+       I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+       I915_WRITE(GEN6_RP_UP_EI, 66000);
+       I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+ 
+       I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+ 
+       I915_WRITE(GEN6_RP_CONTROL,
+                  GEN6_RP_MEDIA_TURBO |
+                  GEN6_RP_MEDIA_HW_NORMAL_MODE |
+                  GEN6_RP_MEDIA_IS_GFX |
+                  GEN6_RP_ENABLE |
+                  GEN6_RP_UP_BUSY_AVG |
+                  GEN6_RP_DOWN_IDLE_CONT);
+ 
         /* Setting Fixed Bias */
         val = VLV_OVERRIDE_EN |
                   VLV_SOC_TDP_EN |
@@@ -7425,7 -7621,7 +7612,7 @@@ static unsigned long __i915_gfx_val(str
   
         lockdep_assert_held(&mchdev_lock);
   
-       pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
+       pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
         pxvid = (pxvid >> 24) & 0x7f;
         ext_v = pvid_to_extvid(dev_priv, pxvid);
   
@@@ -7712,17 -7908,19 +7899,19 @@@ static void intel_init_emon(struct drm_
   
   void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /*
          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
          * requirement.
          */
-       if (!i915.enable_rc6) {
+       if (!i915_modparams.enable_rc6) {
                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
                 intel_runtime_pm_get(dev_priv);
         }
   
         mutex_lock(&dev_priv->drm.struct_mutex);
-       mutex_lock(&dev_priv->rps.hw_lock);
+       mutex_lock(&dev_priv->pcu_lock);
   
         /* Initialize RPS limits (for userspace) */
         if (IS_CHERRYVIEW(dev_priv))
@@@ -7733,16 -7931,16 +7922,16 @@@
                 gen6_init_rps_frequencies(dev_priv);
   
         /* Derive initial user preferences/limits from the hardware limits */
-       dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
-       dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
+       rps->idle_freq = rps->min_freq;
+       rps->cur_freq = rps->idle_freq;
   
-       dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
-       dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+       rps->max_freq_softlimit = rps->max_freq;
+       rps->min_freq_softlimit = rps->min_freq;
   
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-               dev_priv->rps.min_freq_softlimit =
+               rps->min_freq_softlimit =
                         max_t(int,
-                             dev_priv->rps.efficient_freq,
+                             rps->efficient_freq,
                               intel_freq_opcode(dev_priv, 450));
   
         /* After setting max-softlimit, find the overclock max freq */
@@@ -7753,16 -7951,16 +7942,16 @@@
                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
                 if (params & BIT(31)) { /* OC supported */
                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
-                                        (dev_priv->rps.max_freq & 0xff) * 50,
+                                        (rps->max_freq & 0xff) * 50,
                                          (params & 0xff) * 50);
-                       dev_priv->rps.max_freq = params & 0xff;
+                       rps->max_freq = params & 0xff;
                 }
         }
   
         /* Finally allow us to boost to max by default */
-       dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
+       rps->boost_freq = rps->max_freq;
   
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
         mutex_unlock(&dev_priv->drm.struct_mutex);
   
         intel_autoenable_gt_powersave(dev_priv);
@@@ -7773,7 -7971,7 +7962,7 @@@ void intel_cleanup_gt_powersave(struct 
         if (IS_VALLEYVIEW(dev_priv))
                 valleyview_cleanup_gt_powersave(dev_priv);
   
-       if (!i915.enable_rc6)
+       if (!i915_modparams.enable_rc6)
                 intel_runtime_pm_put(dev_priv);
   }
   
@@@ -7790,7 -7988,7 +7979,7 @@@ void intel_suspend_gt_powersave(struct 
         if (INTEL_GEN(dev_priv) < 6)
                 return;
   
-       if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
+       if (cancel_delayed_work_sync(&dev_priv->gt_pm.autoenable_work))
                 intel_runtime_pm_put(dev_priv);
   
         /* gen6_rps_idle() will be called later to disable interrupts */
@@@ -7798,90 -7996,168 +7987,168 @@@
   
   void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
   {
-       dev_priv->rps.enabled = true; /* force disabling */
+       dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
+       dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
         intel_disable_gt_powersave(dev_priv);
   
         gen6_reset_rps_interrupts(dev_priv);
   }
   
- void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+ static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
   {
-       if (!READ_ONCE(dev_priv->rps.enabled))
+       lockdep_assert_held(&i915->pcu_lock);
+ 
+       if (!i915->gt_pm.llc_pstate.enabled)
                 return;
   
-       mutex_lock(&dev_priv->rps.hw_lock);
+       /* Currently there is no HW configuration to be done to disable. */
   
-       if (INTEL_GEN(dev_priv) >= 9) {
+       i915->gt_pm.llc_pstate.enabled = false;
+ }
+ 
+ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
+ {
+       lockdep_assert_held(&dev_priv->pcu_lock);
+ 
+       if (!dev_priv->gt_pm.rc6.enabled)
+               return;
+ 
+       if (INTEL_GEN(dev_priv) >= 9)
                 gen9_disable_rc6(dev_priv);
+       else if (IS_CHERRYVIEW(dev_priv))
+               cherryview_disable_rc6(dev_priv);
+       else if (IS_VALLEYVIEW(dev_priv))
+               valleyview_disable_rc6(dev_priv);
+       else if (INTEL_GEN(dev_priv) >= 6)
+               gen6_disable_rc6(dev_priv);
+ 
+       dev_priv->gt_pm.rc6.enabled = false;
+ }
+ 
+ static void intel_disable_rps(struct drm_i915_private *dev_priv)
+ {
+       lockdep_assert_held(&dev_priv->pcu_lock);
+ 
+       if (!dev_priv->gt_pm.rps.enabled)
+               return;
+ 
+       if (INTEL_GEN(dev_priv) >= 9)
                 gen9_disable_rps(dev_priv);
-       } else if (IS_CHERRYVIEW(dev_priv)) {
+       else if (IS_CHERRYVIEW(dev_priv))
                 cherryview_disable_rps(dev_priv);
-       } else if (IS_VALLEYVIEW(dev_priv)) {
+       else if (IS_VALLEYVIEW(dev_priv))
                 valleyview_disable_rps(dev_priv);
-       } else if (INTEL_GEN(dev_priv) >= 6) {
+       else if (INTEL_GEN(dev_priv) >= 6)
                 gen6_disable_rps(dev_priv);
-       }  else if (IS_IRONLAKE_M(dev_priv)) {
+       else if (IS_IRONLAKE_M(dev_priv))
                 ironlake_disable_drps(dev_priv);
-       }
   
-       dev_priv->rps.enabled = false;
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       dev_priv->gt_pm.rps.enabled = false;
   }
   
- void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
   {
-       /* We shouldn't be disabling as we submit, so this should be less
-        * racy than it appears!
-        */
-       if (READ_ONCE(dev_priv->rps.enabled))
+       mutex_lock(&dev_priv->pcu_lock);
+ 
+       intel_disable_rc6(dev_priv);
+       intel_disable_rps(dev_priv);
+       if (HAS_LLC(dev_priv))
+               intel_disable_llc_pstate(dev_priv);
+ 
+       mutex_unlock(&dev_priv->pcu_lock);
+ }
+ 
+ static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
+ {
+       lockdep_assert_held(&i915->pcu_lock);
+ 
+       if (i915->gt_pm.llc_pstate.enabled)
                 return;
   
-       /* Powersaving is controlled by the host when inside a VM */
-       if (intel_vgpu_active(dev_priv))
+       gen6_update_ring_freq(i915);
+ 
+       i915->gt_pm.llc_pstate.enabled = true;
+ }
+ 
+ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
+ {
+       lockdep_assert_held(&dev_priv->pcu_lock);
+ 
+       if (dev_priv->gt_pm.rc6.enabled)
                 return;
   
-       mutex_lock(&dev_priv->rps.hw_lock);
+       if (IS_CHERRYVIEW(dev_priv))
+               cherryview_enable_rc6(dev_priv);
+       else if (IS_VALLEYVIEW(dev_priv))
+               valleyview_enable_rc6(dev_priv);
+       else if (INTEL_GEN(dev_priv) >= 9)
+               gen9_enable_rc6(dev_priv);
+       else if (IS_BROADWELL(dev_priv))
+               gen8_enable_rc6(dev_priv);
+       else if (INTEL_GEN(dev_priv) >= 6)
+               gen6_enable_rc6(dev_priv);
+ 
+       dev_priv->gt_pm.rc6.enabled = true;
+ }
+ 
+ static void intel_enable_rps(struct drm_i915_private *dev_priv)
+ {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
+       lockdep_assert_held(&dev_priv->pcu_lock);
+ 
+       if (rps->enabled)
+               return;
   
         if (IS_CHERRYVIEW(dev_priv)) {
                 cherryview_enable_rps(dev_priv);
         } else if (IS_VALLEYVIEW(dev_priv)) {
                 valleyview_enable_rps(dev_priv);
         } else if (INTEL_GEN(dev_priv) >= 9) {
-               gen9_enable_rc6(dev_priv);
                 gen9_enable_rps(dev_priv);
-               if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
-                       gen6_update_ring_freq(dev_priv);
         } else if (IS_BROADWELL(dev_priv)) {
                 gen8_enable_rps(dev_priv);
-               gen6_update_ring_freq(dev_priv);
         } else if (INTEL_GEN(dev_priv) >= 6) {
                 gen6_enable_rps(dev_priv);
-               gen6_update_ring_freq(dev_priv);
         } else if (IS_IRONLAKE_M(dev_priv)) {
                 ironlake_enable_drps(dev_priv);
                 intel_init_emon(dev_priv);
         }
   
-       WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
-       WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
+       WARN_ON(rps->max_freq < rps->min_freq);
+       WARN_ON(rps->idle_freq > rps->max_freq);
+ 
+       WARN_ON(rps->efficient_freq < rps->min_freq);
+       WARN_ON(rps->efficient_freq > rps->max_freq);
+ 
+       rps->enabled = true;
+ }
+ 
+ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+ {
+       /* Powersaving is controlled by the host when inside a VM */
+       if (intel_vgpu_active(dev_priv))
+               return;
+ 
+       mutex_lock(&dev_priv->pcu_lock);
   
-       WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
-       WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
+       intel_enable_rc6(dev_priv);
+       intel_enable_rps(dev_priv);
+       if (HAS_LLC(dev_priv))
+               intel_enable_llc_pstate(dev_priv);
   
-       dev_priv->rps.enabled = true;
-       mutex_unlock(&dev_priv->rps.hw_lock);
+       mutex_unlock(&dev_priv->pcu_lock);
   }
   
   static void __intel_autoenable_gt_powersave(struct work_struct *work)
   {
         struct drm_i915_private *dev_priv =
-               container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
+               container_of(work,
+                            typeof(*dev_priv),
+                            gt_pm.autoenable_work.work);
         struct intel_engine_cs *rcs;
         struct drm_i915_gem_request *req;
   
-       if (READ_ONCE(dev_priv->rps.enabled))
-               goto out;
- 
         rcs = dev_priv->engine[RCS];
         if (rcs->last_retired_context)
                 goto out;
@@@ -7895,7 -8171,7 +8162,7 @@@
         if (IS_ERR(req))
                 goto unlock;
   
-       if (!i915.enable_execlists && i915_switch_context(req) == 0)
+       if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
                 rcs->init_context(req);
   
         /* Mark the device busy, calling intel_enable_gt_powersave() */
@@@ -7909,9 -8185,6 +8176,6 @@@ out
   
   void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
   {
-       if (READ_ONCE(dev_priv->rps.enabled))
-               return;
- 
         if (IS_IRONLAKE_M(dev_priv)) {
                 ironlake_enable_drps(dev_priv);
                 intel_init_emon(dev_priv);
@@@ -7929,7 -8202,7 +8193,7 @@@
                  * runtime resume it's necessary).
                  */
                 if (queue_delayed_work(dev_priv->wq,
-                                      &dev_priv->rps.autoenable_work,
+                                      &dev_priv->gt_pm.autoenable_work,
                                        round_jiffies_up_relative(HZ)))
                         intel_runtime_pm_get_noresume(dev_priv);
         }
@@@ -7959,19 -8232,7 +8223,7 @@@ static void g4x_disable_trickle_feed(st
         }
   }
   
- static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
- {
-       I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
-       I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
-       I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
- 
-       /*
-        * Don't touch WM1S_LP_EN here.
-        * Doing so could cause underruns.
-        */
- }
- 
- static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
   
@@@ -8004,8 -8265,6 +8256,6 @@@
                    (I915_READ(DISP_ARB_CTL) |
                     DISP_FBC_WM_DIS));
   
-       ilk_init_lp_watermarks(dev_priv);
- 
         /*
          * Based on the document from hardware guys the following bits
          * should be set unconditionally in order to enable FBC.
@@@ -8118,8 -8377,6 +8368,6 @@@ static void gen6_init_clock_gating(stru
         I915_WRITE(GEN6_GT_MODE,
                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
   
-       ilk_init_lp_watermarks(dev_priv);
- 
         I915_WRITE(CACHE_MODE_0,
                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
   
@@@ -8257,7 -8514,57 +8505,57 @@@ static void gen8_set_l3sqc_credits(stru
         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
   }
   
- static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
+ {
+       if (!HAS_PCH_CNP(dev_priv))
+               return;
+ 
+       /* Wa #1181 */
+       I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
+                  CNP_PWM_CGE_GATING_DISABLE);
+ }
+ 
+ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
+ {
+       u32 val;
+       cnp_init_clock_gating(dev_priv);
+ 
+       /* This is not an Wa. Enable for better image quality */
+       I915_WRITE(_3D_CHICKEN3,
+                  _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+ 
+       /* WaEnableChickenDCPR:cnl */
+       I915_WRITE(GEN8_CHICKEN_DCPR_1,
+                  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+ 
+       /* WaFbcWakeMemOn:cnl */
+       I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+                  DISP_FBC_MEMORY_WAKE);
+ 
+       /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
+       if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
+               I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+                          I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+                          SARBUNIT_CLKGATE_DIS);
+ 
+       /* Display WA #1133: WaFbcSkipSegments:cnl */
+       val = I915_READ(ILK_DPFC_CHICKEN);
+       val &= ~GLK_SKIP_SEG_COUNT_MASK;
+       val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+       I915_WRITE(ILK_DPFC_CHICKEN, val);
+ }
+ 
+ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
+ {
+       cnp_init_clock_gating(dev_priv);
+       gen9_init_clock_gating(dev_priv);
+ 
+       /* WaFbcNukeOnHostModify:cfl */
+       I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+                  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+ }
+ 
+ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         gen9_init_clock_gating(dev_priv);
   
@@@ -8271,12 -8578,12 +8569,12 @@@
                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
   
-       /* WaFbcNukeOnHostModify:kbl,cfl */
+       /* WaFbcNukeOnHostModify:kbl */
         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
   }
   
- static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         gen9_init_clock_gating(dev_priv);
   
@@@ -8289,12 -8596,13 +8587,13 @@@
                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
   }
   
- static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
   {
+       /* The GTT cache must be disabled if the system is using 2M pages. */
+       bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
+                                                I915_GTT_PAGE_SIZE_2M);
         enum pipe pipe;
   
-       ilk_init_lp_watermarks(dev_priv);
- 
         /* WaSwitchSolVfFArbitrationPriority:bdw */
         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
   
@@@ -8325,12 -8633,8 +8624,8 @@@
         /* WaProgramL3SqcReg1Default:bdw */
         gen8_set_l3sqc_credits(dev_priv, 30, 2);
   
-       /*
-        * WaGttCachingOffByDefault:bdw
-        * GTT cache may not work with big pages, so if those
-        * are ever enabled GTT cache may need to be disabled.
-        */
-       I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+       /* WaGttCachingOffByDefault:bdw */
+       I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
   
         /* WaKVMNotificationOnConfigChange:bdw */
         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
@@@ -8347,10 -8651,8 +8642,8 @@@
                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
   }
   
- static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
   {
-       ilk_init_lp_watermarks(dev_priv);
- 
         /* L3 caching of data atomics doesn't work -- disable it. */
         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
         I915_WRITE(HSW_ROW_CHICKEN3,
@@@ -8394,19 -8696,13 +8687,13 @@@
         /* WaSwitchSolVfFArbitrationPriority:hsw */
         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
   
-       /* WaRsPkgCStateDisplayPMReq:hsw */
-       I915_WRITE(CHICKEN_PAR1_1,
-                  I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
- 
         lpt_init_clock_gating(dev_priv);
   }
   
- static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         uint32_t snpcr;
   
-       ilk_init_lp_watermarks(dev_priv);
- 
         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
   
         /* WaDisableEarlyCull:ivb */
@@@ -8498,7 -8794,7 +8785,7 @@@
         gen6_check_mch_setup(dev_priv);
   }
   
- static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         /* WaDisableEarlyCull:vlv */
         I915_WRITE(_3D_CHICKEN3,
@@@ -8578,7 -8874,7 +8865,7 @@@
         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
   }
   
- static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         /* WaVSRefCountFullforceMissDisable:chv */
         /* WaDSRefCountFullforceMissDisable:chv */
@@@ -8638,7 -8934,7 +8925,7 @@@ static void g4x_init_clock_gating(struc
         g4x_disable_trickle_feed(dev_priv);
   }
   
- static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
         I915_WRITE(RENCLK_GATE_D2, 0);
@@@ -8652,7 -8948,7 +8939,7 @@@
         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
   }
   
- static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
+ static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
   {
         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
                    I965_RCC_CLOCK_GATE_DISABLE |
@@@ -8737,34 -9033,38 +9024,38 @@@ static void nop_init_clock_gating(struc
    */
   void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
   {
-       if (IS_SKYLAKE(dev_priv))
-               dev_priv->display.init_clock_gating = skylake_init_clock_gating;
-       else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
-               dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
+       if (IS_CANNONLAKE(dev_priv))
+               dev_priv->display.init_clock_gating = cnl_init_clock_gating;
+       else if (IS_COFFEELAKE(dev_priv))
+               dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+       else if (IS_SKYLAKE(dev_priv))
+               dev_priv->display.init_clock_gating = skl_init_clock_gating;
+       else if (IS_KABYLAKE(dev_priv))
+               dev_priv->display.init_clock_gating = kbl_init_clock_gating;
         else if (IS_BROXTON(dev_priv))
                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
         else if (IS_GEMINILAKE(dev_priv))
                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
         else if (IS_BROADWELL(dev_priv))
-               dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
+               dev_priv->display.init_clock_gating = bdw_init_clock_gating;
         else if (IS_CHERRYVIEW(dev_priv))
-               dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
+               dev_priv->display.init_clock_gating = chv_init_clock_gating;
         else if (IS_HASWELL(dev_priv))
-               dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+               dev_priv->display.init_clock_gating = hsw_init_clock_gating;
         else if (IS_IVYBRIDGE(dev_priv))
-               dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+               dev_priv->display.init_clock_gating = ivb_init_clock_gating;
         else if (IS_VALLEYVIEW(dev_priv))
-               dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
+               dev_priv->display.init_clock_gating = vlv_init_clock_gating;
         else if (IS_GEN6(dev_priv))
                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
         else if (IS_GEN5(dev_priv))
-               dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
+               dev_priv->display.init_clock_gating = ilk_init_clock_gating;
         else if (IS_G4X(dev_priv))
                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
         else if (IS_I965GM(dev_priv))
-               dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+               dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
         else if (IS_I965G(dev_priv))
-               dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+               dev_priv->display.init_clock_gating = i965g_init_clock_gating;
         else if (IS_GEN3(dev_priv))
                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
@@@ -8907,7 -9207,7 +9198,7 @@@ int sandybridge_pcode_read(struct drm_i
   {
         int status;
   
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+       WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
   
         /* GEN6_PCODE_* are outside of the forcewake domain, we can
          * use te fw I915_READ variants to reduce the amount of work
@@@ -8954,7 -9254,7 +9245,7 @@@ int sandybridge_pcode_write(struct drm_
   {
         int status;
   
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+       WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
   
         /* GEN6_PCODE_* are outside of the forcewake domain, we can
          * use te fw I915_READ variants to reduce the amount of work
@@@ -9031,7 -9331,7 +9322,7 @@@ int skl_pcode_request(struct drm_i915_p
         u32 status;
         int ret;
   
-       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+       WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
   
   #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
                                    &status)
@@@ -9073,31 -9373,39 +9364,39 @@@ out
   
   static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /*
          * N = val - 0xb7
          * Slow = Fast = GPLL ref * N
          */
-       return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
+       return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
   }
   
   static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
   {
-       return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
+       return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
   }
   
   static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /*
          * N = val / 2
          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
          */
-       return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
+       return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
   }
   
   static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
   {
+       struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ 
         /* CHV needs even values */
-       return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
+       return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
   }
   
   int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
@@@ -9126,53 -9434,16 +9425,16 @@@ int intel_freq_opcode(struct drm_i915_p
                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
   }
   
- struct request_boost {
-       struct work_struct work;
-       struct drm_i915_gem_request *req;
- };
- 
- static void __intel_rps_boost_work(struct work_struct *work)
- {
-       struct request_boost *boost = container_of(work, struct request_boost, work);
-       struct drm_i915_gem_request *req = boost->req;
- 
-       if (!i915_gem_request_completed(req))
-               gen6_rps_boost(req, NULL);
- 
-       i915_gem_request_put(req);
-       kfree(boost);
- }
- 
- void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
- {
-       struct request_boost *boost;
- 
-       if (req == NULL || INTEL_GEN(req->i915) < 6)
-               return;
- 
-       if (i915_gem_request_completed(req))
-               return;
- 
-       boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
-       if (boost == NULL)
-               return;
- 
-       boost->req = i915_gem_request_get(req);
- 
-       INIT_WORK(&boost->work, __intel_rps_boost_work);
-       queue_work(req->i915->wq, &boost->work);
- }
- 
   void intel_pm_setup(struct drm_i915_private *dev_priv)
   {
-       mutex_init(&dev_priv->rps.hw_lock);
+       mutex_init(&dev_priv->pcu_lock);
   
-       INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
+       INIT_DELAYED_WORK(&dev_priv->gt_pm.autoenable_work,
                           __intel_autoenable_gt_powersave);
-       atomic_set(&dev_priv->rps.num_waiters, 0);
+       atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
   
-       dev_priv->pm.suspended = false;
-       atomic_set(&dev_priv->pm.wakeref_count, 0);
+       dev_priv->runtime_pm.suspended = false;
+       atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
   }
   
   static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
@@@ -9225,7 -9496,7 +9487,7 @@@ u64 intel_rc6_residency_us(struct drm_i
   {
         u64 time_hw, units, div;
   
-       if (!intel_enable_rc6())
+       if (!intel_rc6_enabled())
                 return 0;
   
         intel_runtime_pm_get(dev_priv);
diff --combined drivers/gpu/drm/i915/intel_ringbuffer.h

index 6b2067f1082402bf0f5598dda62fa1c28531fa0d,6a42ed618a28ce1f47b2aeca7263cb9f561a1a86..2863d5a65187a970eaa5c8872e66d53bc28eed9f
--- 1/drivers/gpu/drm/i915/intel_ringbuffer.h
--- 2/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef _INTEL_RINGBUFFER_H_
   #define _INTEL_RINGBUFFER_H_
   
@@@ -8,6 -7,8 +8,8 @@@
   #include "i915_gem_timeline.h"
   #include "i915_selftest.h"
   
+ struct drm_printer;
+ 
   #define I915_CMD_HASH_ORDER 9
   
   /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
@@@ -185,6 -186,104 +187,104 @@@ struct i915_priolist 
         int priority;
   };
   
+ /**
+  * struct intel_engine_execlists - execlist submission queue and port state
+  *
+  * The struct intel_engine_execlists represents the combined logical state of
+  * driver and the hardware state for execlist mode of submission.
+  */
+ struct intel_engine_execlists {
+       /**
+        * @irq_tasklet: softirq tasklet for bottom handler
+        */
+       struct tasklet_struct irq_tasklet;
+ 
+       /**
+        * @default_priolist: priority list for I915_PRIORITY_NORMAL
+        */
+       struct i915_priolist default_priolist;
+ 
+       /**
+        * @no_priolist: priority lists disabled
+        */
+       bool no_priolist;
+ 
+       /**
+        * @port: execlist port states
+        *
+        * For each hardware ELSP (ExecList Submission Port) we keep
+        * track of the last request and the number of times we submitted
+        * that port to hw. We then count the number of times the hw reports
+        * a context completion or preemption. As only one context can
+        * be active on hw, we limit resubmission of context to port[0]. This
+        * is called Lite Restore, of the context.
+        */
+       struct execlist_port {
+               /**
+                * @request_count: combined request and submission count
+                */
+               struct drm_i915_gem_request *request_count;
+ #define EXECLIST_COUNT_BITS 2
+ #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
+ #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
+ #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
+ #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
+ #define port_set(p, packed) ((p)->request_count = (packed))
+ #define port_isset(p) ((p)->request_count)
+ #define port_index(p, execlists) ((p) - (execlists)->port)
+ 
+               /**
+                * @context_id: context ID for port
+                */
+               GEM_DEBUG_DECL(u32 context_id);
+ 
+ #define EXECLIST_MAX_PORTS 2
+       } port[EXECLIST_MAX_PORTS];
+ 
+       /**
+        * @active: is the HW active? We consider the HW as active after
+        * submitting any context for execution and until we have seen the
+        * last context completion event. After that, we do not expect any
+        * more events until we submit, and so can park the HW.
+        *
+        * As we have a small number of different sources from which we feed
+        * the HW, we track the state of each inside a single bitfield.
+        */
+       unsigned int active;
+ #define EXECLISTS_ACTIVE_USER 0
+ #define EXECLISTS_ACTIVE_PREEMPT 1
+ 
+       /**
+        * @port_mask: number of execlist ports - 1
+        */
+       unsigned int port_mask;
+ 
+       /**
+        * @queue: queue of requests, in priority lists
+        */
+       struct rb_root queue;
+ 
+       /**
+        * @first: leftmost level in priority @queue
+        */
+       struct rb_node *first;
+ 
+       /**
+        * @fw_domains: forcewake domains for irq tasklet
+        */
+       unsigned int fw_domains;
+ 
+       /**
+        * @csb_head: context status buffer head
+        */
+       unsigned int csb_head;
+ 
+       /**
+        * @csb_use_mmio: access csb through mmio, instead of hwsp
+        */
+       bool csb_use_mmio;
+ };
+ 
   #define INTEL_ENGINE_CS_MAX_NAME 8
   
   struct intel_engine_cs {
@@@ -307,6 -406,14 +407,14 @@@
         void            (*schedule)(struct drm_i915_gem_request *request,
                                     int priority);
   
+       /*
+        * Cancel all requests on the hardware, or queued for execution.
+        * This should only cancel the ready requests that have been
+        * submitted to the engine (via the engine->submit_request callback).
+        * This is called when marking the device as wedged.
+        */
+       void            (*cancel_requests)(struct intel_engine_cs *engine);
+ 
         /* Some chipsets are not quite as coherent as advertised and need
          * an expensive kick to force a true read of the up-to-date seqno.
          * However, the up-to-date seqno is not always required and the last
@@@ -373,25 -480,7 +481,7 @@@
                 u32     *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
         } semaphore;
   
-       /* Execlists */
-       struct tasklet_struct irq_tasklet;
-       struct i915_priolist default_priolist;
-       bool no_priolist;
-       struct execlist_port {
-               struct drm_i915_gem_request *request_count;
- #define EXECLIST_COUNT_BITS 2
- #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
- #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
- #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
- #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
- #define port_set(p, packed) ((p)->request_count = (packed))
- #define port_isset(p) ((p)->request_count)
- #define port_index(p, e) ((p) - (e)->execlist_port)
-               GEM_DEBUG_DECL(u32 context_id);
-       } execlist_port[2];
-       struct rb_root execlist_queue;
-       struct rb_node *execlist_first;
-       unsigned int fw_domains;
+       struct intel_engine_execlists execlists;
   
         /* Contexts are pinned whilst they are active on the GPU. The last
          * context executed remains active whilst the GPU is idle - the
@@@ -444,6 -533,46 +534,46 @@@
         u32 (*get_cmd_length_mask)(u32 cmd_header);
   };
   
+ static inline void
+ execlists_set_active(struct intel_engine_execlists *execlists,
+                    unsigned int bit)
+ {
+       __set_bit(bit, (unsigned long *)&execlists->active);
+ }
+ 
+ static inline void
+ execlists_clear_active(struct intel_engine_execlists *execlists,
+                      unsigned int bit)
+ {
+       __clear_bit(bit, (unsigned long *)&execlists->active);
+ }
+ 
+ static inline bool
+ execlists_is_active(const struct intel_engine_execlists *execlists,
+                   unsigned int bit)
+ {
+       return test_bit(bit, (unsigned long *)&execlists->active);
+ }
+ 
+ static inline unsigned int
+ execlists_num_ports(const struct intel_engine_execlists * const execlists)
+ {
+       return execlists->port_mask + 1;
+ }
+ 
+ static inline void
+ execlists_port_complete(struct intel_engine_execlists * const execlists,
+                       struct execlist_port * const port)
+ {
+       const unsigned int m = execlists->port_mask;
+ 
+       GEM_BUG_ON(port_index(port, execlists) != 0);
+       GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
+ 
+       memmove(port, port + 1, m * sizeof(struct execlist_port));
+       memset(port + m, 0, sizeof(struct execlist_port));
+ }
+ 
   static inline unsigned int
   intel_engine_flag(const struct intel_engine_cs *engine)
   {
@@@ -497,6 -626,10 +627,10 @@@ intel_write_status_page(struct intel_en
   #define I915_GEM_HWS_SCRATCH_INDEX    0x40
   #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
   
+ #define I915_HWS_CSB_BUF0_INDEX               0x10
+ #define I915_HWS_CSB_WRITE_INDEX      0x1f
+ #define CNL_HWS_CSB_WRITE_INDEX               0x2f
+ 
   struct intel_ring *
   intel_engine_create_ring(struct intel_engine_cs *engine, int size);
   int intel_ring_pin(struct intel_ring *ring,
@@@ -736,16 -869,8 +870,8 @@@ bool intel_engines_are_idle(struct drm_
   void intel_engines_mark_idle(struct drm_i915_private *i915);
   void intel_engines_reset_default_submission(struct drm_i915_private *i915);
   
- static inline bool
- __intel_engine_can_store_dword(unsigned int gen, unsigned int class)
- {
-       if (gen <= 2)
-               return false; /* uses physical not virtual addresses */
+ bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
   
-       if (gen == 6 && class == VIDEO_DECODE_CLASS)
-               return false; /* b0rked */
- 
-       return true;
- }
+ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p);
   
   #endif /* _INTEL_RINGBUFFER_H_ */
diff --combined drivers/gpu/drm/i915/selftests/i915_live_selftests.h

index 1519f1b7841b124fbc85534adb0d1376ad887bd2,54a73534b37e812970f12c7f36fd2d273ef0c804..d7dd98a6acad590531b0b10f13dd6aec86aacc38
--- 1/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
--- 2/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   /* List each unit test as selftest(name, function)
    *
    * The name is used as both an enum and expanded as subtest__name to create
@@@ -16,5 -15,7 +16,7 @@@ selftest(objects, i915_gem_object_live_
   selftest(dmabuf, i915_gem_dmabuf_live_selftests)
   selftest(coherency, i915_gem_coherency_live_selftests)
   selftest(gtt, i915_gem_gtt_live_selftests)
+ selftest(evict, i915_gem_evict_live_selftests)
+ selftest(hugepages, i915_gem_huge_page_live_selftests)
   selftest(contexts, i915_gem_context_live_selftests)
   selftest(hangcheck, intel_hangcheck_live_selftests)
diff --combined drivers/gpu/drm/i915/selftests/i915_mock_selftests.h

index e5a9e5dcf2f38e6bb2e9fdb644cc6f2d48c05b4c,9961b44f76ed4e3166761137bda500fa076f79cf..19c6fce837dfbc994162beb39ff028d85aa8906a
--- 1/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
--- 2/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   /* List each unit test as selftest(name, function)
    *
    * The name is used as both an enum and expanded as subtest__name to create
@@@ -22,3 -21,4 +22,4 @@@ selftest(dmabuf, i915_gem_dmabuf_mock_s
   selftest(vma, i915_vma_mock_selftests)
   selftest(evict, i915_gem_evict_mock_selftests)
   selftest(gtt, i915_gem_gtt_mock_selftests)
+ selftest(hugepages, i915_gem_huge_page_mock_selftests)
diff --combined drivers/gpu/drm/msm/Makefile

index ced70783b44e8e2d602fcee6ead1bf65d8390333,d0b26dd80076f2922423c914df8d11258fcd3366..92b3844202d2bd9cb08837730e13fa15df422d3d
--- 1/drivers/gpu/drm/msm/Makefile
--- 2/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   ccflags-y := -Idrivers/gpu/drm/msm
   ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
   
@@@ -9,6 -8,7 +9,7 @@@ msm-y := 
         adreno/a4xx_gpu.o \
         adreno/a5xx_gpu.o \
         adreno/a5xx_power.o \
+       adreno/a5xx_preempt.o \
         hdmi/hdmi.o \
         hdmi/hdmi_audio.o \
         hdmi/hdmi_bridge.o \
@@@ -58,7 -58,8 +59,8 @@@
         msm_iommu.o \
         msm_perf.o \
         msm_rd.o \
-       msm_ringbuffer.o
+       msm_ringbuffer.o \
+       msm_submitqueue.o
   
   msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
   msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
diff --combined drivers/gpu/drm/nouveau/include/nvif/cl506e.h

index b4cd580933007a698d85cf14949c2fca4e99ca03,f5086601100298ee3757943df6522e36f4e4e727..989690fe3cd88ec8330d1ed798efb71b4141a3ca
--- 1/drivers/gpu/drm/nouveau/include/nvif/cl506e.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/cl506e.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CL506E_H__
   #define __NVIF_CL506E_H__
   
@@@ -6,7 -5,7 +6,7 @@@ struct nv50_channel_dma_v0 
         __u8  version;
         __u8  chid;
         __u8  pad02[6];
-       __u64 vm;
+       __u64 vmm;
         __u64 pushbuf;
         __u64 offset;
   };
diff --combined drivers/gpu/drm/nouveau/include/nvif/cl506f.h

index 14d20c813cdb9be972336a9362ee9ac5a3003892,0e5bbb55315839b44916e70954654d63b0139a04..5137b6879abdc9de6f8cbce6c7716983570c79d3
--- 1/drivers/gpu/drm/nouveau/include/nvif/cl506f.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/cl506f.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CL506F_H__
   #define __NVIF_CL506F_H__
   
@@@ -9,6 -8,6 +9,6 @@@ struct nv50_channel_gpfifo_v0 
         __u32 ilength;
         __u64 ioffset;
         __u64 pushbuf;
-       __u64 vm;
+       __u64 vmm;
   };
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvif/cl826e.h

index 36944ff09e3c6a24cb950384add06538e9a0086d,7f6a8ce5a418d0eed0722104b962592c4c9d7919..1a875090b251ddc4183b273cdcfc30382791ba58
--- 1/drivers/gpu/drm/nouveau/include/nvif/cl826e.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/cl826e.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CL826E_H__
   #define __NVIF_CL826E_H__
   
@@@ -6,7 -5,7 +6,7 @@@ struct g82_channel_dma_v0 
         __u8  version;
         __u8  chid;
         __u8  pad02[6];
-       __u64 vm;
+       __u64 vmm;
         __u64 pushbuf;
         __u64 offset;
   };
diff --combined drivers/gpu/drm/nouveau/include/nvif/cl826f.h

index df09a50817eb0a9ca0e306bebb47b04f42d520ed,c4d35522331a4795437de2644465830900d85307..e4e50cfe88f16cf9b6929039967181ab27f0d9fa
--- 1/drivers/gpu/drm/nouveau/include/nvif/cl826f.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/cl826f.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CL826F_H__
   #define __NVIF_CL826F_H__
   
@@@ -9,7 -8,7 +9,7 @@@ struct g82_channel_gpfifo_v0 
         __u32 ilength;
         __u64 ioffset;
         __u64 pushbuf;
-       __u64 vm;
+       __u64 vmm;
   };
   
   #define NV826F_V0_NTFY_NON_STALL_INTERRUPT                                 0x00
diff --combined drivers/gpu/drm/nouveau/include/nvif/cl906f.h

index 6d16a3a2ec02820dcabe7ec519de3d6219486f3f,169161c1587f7e29e282d40ebaac9ebec32430c8..ab0fa8adb756cbd77d7fe607e91019f50c1dab58
--- 1/drivers/gpu/drm/nouveau/include/nvif/cl906f.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/cl906f.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CL906F_H__
   #define __NVIF_CL906F_H__
   
@@@ -8,7 -7,7 +8,7 @@@ struct fermi_channel_gpfifo_v0 
         __u8  pad02[2];
         __u32 ilength;
         __u64 ioffset;
-       __u64 vm;
+       __u64 vmm;
   };
   
   #define NV906F_V0_NTFY_NON_STALL_INTERRUPT                                 0x00
diff --combined drivers/gpu/drm/nouveau/include/nvif/cla06f.h

index 597ebb52d5f92e8e3da863a056904ae642faf48d,3e57089526e3a05c8738a910fd9cc70c38cf51bd..56f5bd81e480bdeb3a6aad875d979d517ca37307
--- 1/drivers/gpu/drm/nouveau/include/nvif/cla06f.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/cla06f.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CLA06F_H__
   #define __NVIF_CLA06F_H__
   
@@@ -23,7 -22,7 +23,7 @@@ struct kepler_channel_gpfifo_a_v0 
         __u32 engines;
         __u32 ilength;
         __u64 ioffset;
-       __u64 vm;
+       __u64 vmm;
   };
   
   #define NVA06F_V0_NTFY_NON_STALL_INTERRUPT                                 0x00
diff --combined drivers/gpu/drm/nouveau/include/nvif/class.h

index e3a2ea8bde7051e739e3f633d9db88056d55f9e5,56aade45067d3721b687875c2f59b81e46019de9..a7c5bf5727883f5027de9ca24db3303992094977
--- 1/drivers/gpu/drm/nouveau/include/nvif/class.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_CLASS_H__
   #define __NVIF_CLASS_H__
   
@@@ -15,6 -14,23 +15,23 @@@
   #define NVIF_CLASS_SW_NV50                           /* if0005.h */ -0x00000006
   #define NVIF_CLASS_SW_GF100                          /* if0005.h */ -0x00000007
   
+ #define NVIF_CLASS_MMU                               /* if0008.h */  0x80000008
+ #define NVIF_CLASS_MMU_NV04                          /* if0008.h */  0x80000009
+ #define NVIF_CLASS_MMU_NV50                          /* if0008.h */  0x80005009
+ #define NVIF_CLASS_MMU_GF100                         /* if0008.h */  0x80009009
+ 
+ #define NVIF_CLASS_MEM                               /* if000a.h */  0x8000000a
+ #define NVIF_CLASS_MEM_NV04                          /* if000b.h */  0x8000000b
+ #define NVIF_CLASS_MEM_NV50                          /* if500b.h */  0x8000500b
+ #define NVIF_CLASS_MEM_GF100                         /* if900b.h */  0x8000900b
+ 
+ #define NVIF_CLASS_VMM                               /* if000c.h */  0x8000000c
+ #define NVIF_CLASS_VMM_NV04                          /* if000d.h */  0x8000000d
+ #define NVIF_CLASS_VMM_NV50                          /* if500d.h */  0x8000500d
+ #define NVIF_CLASS_VMM_GF100                         /* if900d.h */  0x8000900d
+ #define NVIF_CLASS_VMM_GM200                         /* ifb00d.h */  0x8000b00d
+ #define NVIF_CLASS_VMM_GP100                         /* ifc00d.h */  0x8000c00d
+ 
   /* the below match nvidia-assigned (either in hw, or sw) class numbers */
   #define NV_NULL_CLASS                                                0x00000030
   
diff --combined drivers/gpu/drm/nouveau/include/nvif/device.h

index 09439b037870888a0fa4e3cc782f191475b81f7f,b579633b80c0de588317219b69206007dc0a25d0..6edb6266857e45b18cb255c5e29591f59f2a92d0
--- 1/drivers/gpu/drm/nouveau/include/nvif/device.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_DEVICE_H__
   #define __NVIF_DEVICE_H__
   
@@@ -39,7 -38,6 +39,6 @@@ u64  nvif_device_time(struct nvif_devic
   /*XXX*/
   #include <subdev/bios.h>
   #include <subdev/fb.h>
- #include <subdev/mmu.h>
   #include <subdev/bar.h>
   #include <subdev/gpio.h>
   #include <subdev/clk.h>
@@@ -58,8 -56,6 +57,6 @@@
   })
   #define nvxx_bios(a) nvxx_device(a)->bios
   #define nvxx_fb(a) nvxx_device(a)->fb
- #define nvxx_mmu(a) nvxx_device(a)->mmu
- #define nvxx_bar(a) nvxx_device(a)->bar
   #define nvxx_gpio(a) nvxx_device(a)->gpio
   #define nvxx_clk(a) nvxx_device(a)->clk
   #define nvxx_i2c(a) nvxx_device(a)->i2c
@@@ -67,10 -63,8 +64,8 @@@
   #define nvxx_therm(a) nvxx_device(a)->therm
   #define nvxx_volt(a) nvxx_device(a)->volt
   
- #include <core/device.h>
   #include <engine/fifo.h>
   #include <engine/gr.h>
- #include <engine/sw.h>
   
   #define nvxx_fifo(a) nvxx_device(a)->fifo
   #define nvxx_gr(a) nvxx_device(a)->gr
diff --combined drivers/gpu/drm/nouveau/include/nvif/ioctl.h

index 688c4bcd9c64d5cd14a476b0a0db05fdcfed8221,1886366457f18cdd83db32c70d5154995b957ca6..b93d586a2304e02c810c5cd24cf2ecf052f6673f
--- 1/drivers/gpu/drm/nouveau/include/nvif/ioctl.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/ioctl.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h
@@@ -1,8 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_IOCTL_H__
   #define __NVIF_IOCTL_H__
   
- #define NVIF_VERSION_LATEST                               0x0000000000000000ULL
+ #define NVIF_VERSION_LATEST                               0x0000000000000100ULL
   
   struct nvif_ioctl_v0 {
         __u8  version;
@@@ -84,9 -83,13 +84,13 @@@ struct nvif_ioctl_wr_v0 
   struct nvif_ioctl_map_v0 {
         /* nvif_ioctl ... */
         __u8  version;
-       __u8  pad01[3];
-       __u32 length;
+ #define NVIF_IOCTL_MAP_V0_IO                                               0x00
+ #define NVIF_IOCTL_MAP_V0_VA                                               0x01
+       __u8  type;
+       __u8  pad02[6];
         __u64 handle;
+       __u64 length;
+       __u8  data[];
   };
   
   struct nvif_ioctl_unmap {
diff --combined drivers/gpu/drm/nouveau/include/nvif/object.h

index 6912b8cffc98152879a7b4959755d87a01cf271d,0b54261bdefe5609949c793f9bfe4eb7944061c2..a2d5244ff2b77ae6b270a5edf4f1e72007ca6226
--- 1/drivers/gpu/drm/nouveau/include/nvif/object.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/object.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/object.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVIF_OBJECT_H__
   #define __NVIF_OBJECT_H__
   
@@@ -17,7 -16,7 +17,7 @@@ struct nvif_object 
         void *priv; /*XXX: hack */
         struct {
                 void __iomem *ptr;
-               u32 size;
+               u64 size;
         } map;
   };
   
@@@ -30,7 -29,10 +30,10 @@@ void nvif_object_sclass_put(struct nvif
   u32  nvif_object_rd(struct nvif_object *, int, u64);
   void nvif_object_wr(struct nvif_object *, int, u64, u32);
   int  nvif_object_mthd(struct nvif_object *, u32, void *, u32);
- int  nvif_object_map(struct nvif_object *);
+ int  nvif_object_map_handle(struct nvif_object *, void *, u32,
+                           u64 *handle, u64 *length);
+ void nvif_object_unmap_handle(struct nvif_object *);
+ int  nvif_object_map(struct nvif_object *, void *, u32);
   void nvif_object_unmap(struct nvif_object *);
   
   #define nvif_handle(a) (unsigned long)(void *)(a)
diff --combined drivers/gpu/drm/nouveau/include/nvif/os.h

index 6b16ab6b26d534258f23db99875dc9c21b658390,5efdf80d5abcbca75039de4a8deae3cc1142d064..fd09b28429723cd7aa91be61975b199cd1730074
--- 1/drivers/gpu/drm/nouveau/include/nvif/os.h
--- 2/drivers/gpu/drm/nouveau/include/nvif/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/os.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_OS_H__
   #define __NOUVEAU_OS_H__
   
@@@ -34,18 -33,4 +34,4 @@@
   
   #include <soc/tegra/fuse.h>
   #include <soc/tegra/pmc.h>
- 
- #ifndef ioread32_native
- #ifdef __BIG_ENDIAN
- #define ioread16_native ioread16be
- #define iowrite16_native iowrite16be
- #define ioread32_native  ioread32be
- #define iowrite32_native iowrite32be
- #else /* def __BIG_ENDIAN */
- #define ioread16_native ioread16
- #define iowrite16_native iowrite16
- #define ioread32_native  ioread32
- #define iowrite32_native iowrite32
- #endif /* def __BIG_ENDIAN else */
- #endif /* !ioread32_native */
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/client.h

index ca23230d574377bfde2926c20ef3d6381e4b3101,79624f6d0a2b30b5de2bec5380ad6baf5b8f8c6d..757fac823a10fa9f0de9c4962829bab818044615
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_CLIENT_H__
   #define __NVKM_CLIENT_H__
   #define nvkm_client(p) container_of((p), struct nvkm_client, object)
@@@ -17,7 -16,8 +17,8 @@@ struct nvkm_client 
         void *data;
         int (*ntfy)(const void *, u32, const void *, u32);
   
-       struct nvkm_vm *vm;
+       struct list_head umem;
+       spinlock_t lock;
   };
   
   int  nvkm_client_new(const char *name, u64 device, const char *cfg,
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/device.h

index d7ecb65ba19f62c85f4fc8c1c9aa29f64fa1cdea,5046e1db99acdc9d4c1f8d4c7c9f15a7b7d539d2..560265b15ec23705decabcfec7491c4f47f09f4b
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@@ -1,8 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_DEVICE_H__
   #define __NVKM_DEVICE_H__
+ #include <core/oclass.h>
   #include <core/event.h>
- #include <core/object.h>
   
   enum nvkm_devidx {
         NVKM_SUBDEV_PCI,
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/engine.h

index c6bcd8a64caebb171afc97e507547f32f5605083,7730499bfd958aed0e993f0a0e0c9fcdab639566..ebf8473a39fe87e2dc7b748aa97d77979ec8ace4
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_ENGINE_H__
   #define __NVKM_ENGINE_H__
   #define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev)
@@@ -16,6 -15,7 +16,7 @@@ struct nvkm_engine 
   
   struct nvkm_engine_func {
         void *(*dtor)(struct nvkm_engine *);
+       void (*preinit)(struct nvkm_engine *);
         int (*oneinit)(struct nvkm_engine *);
         int (*init)(struct nvkm_engine *);
         int (*fini)(struct nvkm_engine *, bool suspend);
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h

index 473ba0b9a3682d0de7c3d34d0671c486be4feb3c,51691667b81300afcde1c48abf7d45f75b4999b8..10eeaeebc242d54e735fe53e901741672cc89694
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
@@@ -1,18 -1,16 +1,17 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_GPUOBJ_H__
   #define __NVKM_GPUOBJ_H__
- #include <core/object.h>
   #include <core/memory.h>
   #include <core/mm.h>
- struct nvkm_vma;
- struct nvkm_vm;
   
   #define NVOBJ_FLAG_ZERO_ALLOC 0x00000001
   #define NVOBJ_FLAG_HEAP       0x00000004
   
   struct nvkm_gpuobj {
-       struct nvkm_object object;
-       const struct nvkm_gpuobj_func *func;
+       union {
+               const struct nvkm_gpuobj_func *func;
+               const struct nvkm_gpuobj_func *ptrs;
+       };
         struct nvkm_gpuobj *parent;
         struct nvkm_memory *memory;
         struct nvkm_mm_node *node;
@@@ -29,15 -27,14 +28,14 @@@ struct nvkm_gpuobj_func 
         void (*release)(struct nvkm_gpuobj *);
         u32 (*rd32)(struct nvkm_gpuobj *, u32 offset);
         void (*wr32)(struct nvkm_gpuobj *, u32 offset, u32 data);
+       int (*map)(struct nvkm_gpuobj *, u64 offset, struct nvkm_vmm *,
+                  struct nvkm_vma *, void *argv, u32 argc);
   };
   
   int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero,
                     struct nvkm_gpuobj *parent, struct nvkm_gpuobj **);
   void nvkm_gpuobj_del(struct nvkm_gpuobj **);
   int nvkm_gpuobj_wrap(struct nvkm_memory *, struct nvkm_gpuobj **);
- int nvkm_gpuobj_map(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
-                   struct nvkm_vma *);
- void nvkm_gpuobj_unmap(struct nvkm_vma *);
   void nvkm_gpuobj_memcpy_to(struct nvkm_gpuobj *dst, u32 dstoffset, void *src,
                            u32 length);
   void nvkm_gpuobj_memcpy_from(void *dst, struct nvkm_gpuobj *src, u32 srcoffset,
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/memory.h

index affba21fcbade03b3ccfbe1a6ee767e9dbb7bf0e,13ebf4da2b963324f4a24e9d26d923777e048e54..05f505de0075f5256b39814292789ae56b8d044f
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
@@@ -1,10 -1,14 +1,15 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_MEMORY_H__
   #define __NVKM_MEMORY_H__
   #include <core/os.h>
   struct nvkm_device;
   struct nvkm_vma;
- struct nvkm_vm;
+ struct nvkm_vmm;
+ 
+ struct nvkm_tags {
+       struct nvkm_mm_node *mn;
+       refcount_t refcount;
+ };
   
   enum nvkm_memory_target {
         NVKM_MEM_TARGET_INST, /* instance memory */
@@@ -15,41 -19,84 +20,84 @@@
   
   struct nvkm_memory {
         const struct nvkm_memory_func *func;
+       const struct nvkm_memory_ptrs *ptrs;
+       struct kref kref;
+       struct nvkm_tags *tags;
   };
   
   struct nvkm_memory_func {
         void *(*dtor)(struct nvkm_memory *);
         enum nvkm_memory_target (*target)(struct nvkm_memory *);
+       u8 (*page)(struct nvkm_memory *);
         u64 (*addr)(struct nvkm_memory *);
         u64 (*size)(struct nvkm_memory *);
-       void (*boot)(struct nvkm_memory *, struct nvkm_vm *);
+       void (*boot)(struct nvkm_memory *, struct nvkm_vmm *);
         void __iomem *(*acquire)(struct nvkm_memory *);
         void (*release)(struct nvkm_memory *);
+       int (*map)(struct nvkm_memory *, u64 offset, struct nvkm_vmm *,
+                  struct nvkm_vma *, void *argv, u32 argc);
+ };
+ 
+ struct nvkm_memory_ptrs {
         u32 (*rd32)(struct nvkm_memory *, u64 offset);
         void (*wr32)(struct nvkm_memory *, u64 offset, u32 data);
-       void (*map)(struct nvkm_memory *, struct nvkm_vma *, u64 offset);
   };
   
   void nvkm_memory_ctor(const struct nvkm_memory_func *, struct nvkm_memory *);
   int nvkm_memory_new(struct nvkm_device *, enum nvkm_memory_target,
                     u64 size, u32 align, bool zero, struct nvkm_memory **);
- void nvkm_memory_del(struct nvkm_memory **);
+ struct nvkm_memory *nvkm_memory_ref(struct nvkm_memory *);
+ void nvkm_memory_unref(struct nvkm_memory **);
+ int nvkm_memory_tags_get(struct nvkm_memory *, struct nvkm_device *, u32 tags,
+                        void (*clear)(struct nvkm_device *, u32, u32),
+                        struct nvkm_tags **);
+ void nvkm_memory_tags_put(struct nvkm_memory *, struct nvkm_device *,
+                         struct nvkm_tags **);
+ 
   #define nvkm_memory_target(p) (p)->func->target(p)
+ #define nvkm_memory_page(p) (p)->func->page(p)
   #define nvkm_memory_addr(p) (p)->func->addr(p)
   #define nvkm_memory_size(p) (p)->func->size(p)
   #define nvkm_memory_boot(p,v) (p)->func->boot((p),(v))
- #define nvkm_memory_map(p,v,o) (p)->func->map((p),(v),(o))
+ #define nvkm_memory_map(p,o,vm,va,av,ac)                                       \
+       (p)->func->map((p),(o),(vm),(va),(av),(ac))
   
   /* accessor macros - kmap()/done() must bracket use of the other accessor
    * macros to guarantee correct behaviour across all chipsets
    */
   #define nvkm_kmap(o)     (o)->func->acquire(o)
- #define nvkm_ro32(o,a)   (o)->func->rd32((o), (a))
- #define nvkm_wo32(o,a,d) (o)->func->wr32((o), (a), (d))
+ #define nvkm_done(o)     (o)->func->release(o)
+ 
+ #define nvkm_ro32(o,a)   (o)->ptrs->rd32((o), (a))
+ #define nvkm_wo32(o,a,d) (o)->ptrs->wr32((o), (a), (d))
   #define nvkm_mo32(o,a,m,d) ({                                                  \
         u32 _addr = (a), _data = nvkm_ro32((o), _addr);                        \
         nvkm_wo32((o), _addr, (_data & ~(m)) | (d));                           \
         _data;                                                                 \
   })
- #define nvkm_done(o)     (o)->func->release(o)
+ 
+ #define nvkm_wo64(o,a,d) do {                                                  \
+       u64 __a = (a), __d = (d);                                              \
+       nvkm_wo32((o), __a + 0, lower_32_bits(__d));                           \
+       nvkm_wo32((o), __a + 4, upper_32_bits(__d));                           \
+ } while(0)
+ 
+ #define nvkm_fill(t,s,o,a,d,c) do {                                            \
+       u64 _a = (a), _c = (c), _d = (d), _o = _a >> s, _s = _c << s;          \
+       u##t __iomem *_m = nvkm_kmap(o);                                       \
+       if (likely(_m)) {                                                      \
+               if (_d) {                                                      \
+                       while (_c--)                                           \
+                               iowrite##t##_native(_d, &_m[_o++]);            \
+               } else {                                                       \
+                       memset_io(&_m[_o], _d, _s);                            \
+               }                                                              \
+       } else {                                                               \
+               for (; _c; _c--, _a += BIT(s))                                 \
+                       nvkm_wo##t((o), _a, _d);                               \
+       }                                                                      \
+       nvkm_done(o);                                                          \
+ } while(0)
+ #define nvkm_fo32(o,a,d,c) nvkm_fill(32, 2, (o), (a), (d), (c))
+ #define nvkm_fo64(o,a,d,c) nvkm_fill(64, 3, (o), (a), (d), (c))
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/mm.h

index 2002a4da999905dfafcf5066ed281abf5caa82cd,5c1261351138be2a829cda73807a52dc8440c324..b0726c39429ea8441629ecf59375598f6aae2f6c
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_MM_H__
   #define __NVKM_MM_H__
   #include <core/os.h>
@@@ -31,7 -30,7 +31,7 @@@ nvkm_mm_initialised(struct nvkm_mm *mm
         return mm->heap_nodes;
   }
   
- int  nvkm_mm_init(struct nvkm_mm *, u32 offset, u32 length, u32 block);
+ int  nvkm_mm_init(struct nvkm_mm *, u8 heap, u32 offset, u32 length, u32 block);
   int  nvkm_mm_fini(struct nvkm_mm *);
   int  nvkm_mm_head(struct nvkm_mm *, u8 heap, u8 type, u32 size_max,
                   u32 size_min, u32 align, struct nvkm_mm_node **);
@@@ -40,9 -39,39 +40,39 @@@ int  nvkm_mm_tail(struct nvkm_mm *, u8 
   void nvkm_mm_free(struct nvkm_mm *, struct nvkm_mm_node **);
   void nvkm_mm_dump(struct nvkm_mm *, const char *);
   
+ static inline u32
+ nvkm_mm_heap_size(struct nvkm_mm *mm, u8 heap)
+ {
+       struct nvkm_mm_node *node;
+       u32 size = 0;
+       list_for_each_entry(node, &mm->nodes, nl_entry) {
+               if (node->heap == heap)
+                       size += node->length;
+       }
+       return size;
+ }
+ 
   static inline bool
   nvkm_mm_contiguous(struct nvkm_mm_node *node)
   {
         return !node->next;
   }
+ 
+ static inline u32
+ nvkm_mm_addr(struct nvkm_mm_node *node)
+ {
+       if (WARN_ON(!nvkm_mm_contiguous(node)))
+               return 0;
+       return node->offset;
+ }
+ 
+ static inline u32
+ nvkm_mm_size(struct nvkm_mm_node *node)
+ {
+       u32 size = 0;
+       do {
+               size += node->length;
+       } while ((node = node->next));
+       return size;
+ }
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/object.h

index 3f13ff1d4ee4a3332aeb97799234d25f2ed7d044,916a4b76d430bc31f8594df3e6047596c9b8b330..270f893cc15456e0776785064faa0e3c8723834c
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
@@@ -1,11 -1,8 +1,9 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_OBJECT_H__
   #define __NVKM_OBJECT_H__
- #include <core/os.h>
- #include <core/debug.h>
+ #include <core/oclass.h>
   struct nvkm_event;
   struct nvkm_gpuobj;
- struct nvkm_oclass;
   
   struct nvkm_object {
         const struct nvkm_object_func *func;
@@@ -22,13 -19,20 +20,20 @@@
         struct rb_node node;
   };
   
+ enum nvkm_object_map {
+       NVKM_OBJECT_MAP_IO,
+       NVKM_OBJECT_MAP_VA
+ };
+ 
   struct nvkm_object_func {
         void *(*dtor)(struct nvkm_object *);
         int (*init)(struct nvkm_object *);
         int (*fini)(struct nvkm_object *, bool suspend);
         int (*mthd)(struct nvkm_object *, u32 mthd, void *data, u32 size);
         int (*ntfy)(struct nvkm_object *, u32 mthd, struct nvkm_event **);
-       int (*map)(struct nvkm_object *, u64 *addr, u32 *size);
+       int (*map)(struct nvkm_object *, void *argv, u32 argc,
+                  enum nvkm_object_map *, u64 *addr, u64 *size);
+       int (*unmap)(struct nvkm_object *);
         int (*rd08)(struct nvkm_object *, u64 addr, u8 *data);
         int (*rd16)(struct nvkm_object *, u64 addr, u16 *data);
         int (*rd32)(struct nvkm_object *, u64 addr, u32 *data);
@@@ -53,7 -57,9 +58,9 @@@ int nvkm_object_init(struct nvkm_objec
   int nvkm_object_fini(struct nvkm_object *, bool suspend);
   int nvkm_object_mthd(struct nvkm_object *, u32 mthd, void *data, u32 size);
   int nvkm_object_ntfy(struct nvkm_object *, u32 mthd, struct nvkm_event **);
- int nvkm_object_map(struct nvkm_object *, u64 *addr, u32 *size);
+ int nvkm_object_map(struct nvkm_object *, void *argv, u32 argc,
+                   enum nvkm_object_map *, u64 *addr, u64 *size);
+ int nvkm_object_unmap(struct nvkm_object *);
   int nvkm_object_rd08(struct nvkm_object *, u64 addr, u8  *data);
   int nvkm_object_rd16(struct nvkm_object *, u64 addr, u16 *data);
   int nvkm_object_rd32(struct nvkm_object *, u64 addr, u32 *data);
@@@ -67,28 -73,4 +74,4 @@@ bool nvkm_object_insert(struct nvkm_obj
   void nvkm_object_remove(struct nvkm_object *);
   struct nvkm_object *nvkm_object_search(struct nvkm_client *, u64 object,
                                        const struct nvkm_object_func *);
- 
- struct nvkm_sclass {
-       int minver;
-       int maxver;
-       s32 oclass;
-       const struct nvkm_object_func *func;
-       int (*ctor)(const struct nvkm_oclass *, void *data, u32 size,
-                   struct nvkm_object **);
- };
- 
- struct nvkm_oclass {
-       int (*ctor)(const struct nvkm_oclass *, void *data, u32 size,
-                   struct nvkm_object **);
-       struct nvkm_sclass base;
-       const void *priv;
-       const void *engn;
-       u32 handle;
-       u8  route;
-       u64 token;
-       u64 object;
-       struct nvkm_client *client;
-       struct nvkm_object *parent;
-       struct nvkm_engine *engine;
- };
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/os.h

index fc9e8cd360877dda261c280d5d37e5c253f8dd6c,1f0108fdd24af4068f98efc1156e535e007205b8..445602d1e8d3a987396807c587860c73a8eeb408
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@@ -1,5 -1,23 +1,24 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_OS_H__
   #define __NVKM_OS_H__
   #include <nvif/os.h>
+ 
+ #ifdef __BIG_ENDIAN
+ #define ioread16_native ioread16be
+ #define iowrite16_native iowrite16be
+ #define ioread32_native  ioread32be
+ #define iowrite32_native iowrite32be
+ #else
+ #define ioread16_native ioread16
+ #define iowrite16_native iowrite16
+ #define ioread32_native  ioread32
+ #define iowrite32_native iowrite32
+ #endif
+ 
+ #define iowrite64_native(v,p) do {                                             \
+       u32 __iomem *_p = (u32 __iomem *)(p);                                  \
+       u64 _v = (v);                                                          \
+       iowrite32_native(lower_32_bits(_v), &_p[0]);                           \
+       iowrite32_native(upper_32_bits(_v), &_p[1]);                           \
+ } while(0)
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h

index 674a3840824038450e85c93543c6c0dfdb33ec84,8a48ca67f60dbed5bd5799e7c56715b53354af19..d5d789663aca392d9eee88a3073beacbb374922b
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
@@@ -1,7 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_RAMHT_H__
   #define __NVKM_RAMHT_H__
   #include <core/gpuobj.h>
+ struct nvkm_object;
   
   struct nvkm_ramht_data {
         struct nvkm_gpuobj *inst;
diff --combined drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h

index 38f51ff7ab40fdcd9e873ad56a0f71d2b3f4d364,a6c21be7537f7f5935f4482e4dd35593ff20680f..63df2290177f3b038a50da1566c617fc26ebe232
--- 1/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_SUBDEV_H__
   #define __NVKM_SUBDEV_H__
   #include <core/device.h>
@@@ -34,7 -33,7 +34,7 @@@ void nvkm_subdev_intr(struct nvkm_subde
   /* subdev logging */
   #define nvkm_printk_(s,l,p,f,a...) do {                                        \
         const struct nvkm_subdev *_subdev = (s);                               \
-       if (_subdev->debug >= (l)) {                                           \
+       if (CONFIG_NOUVEAU_DEBUG >= (l) && _subdev->debug >= (l)) {            \
                 dev_##p(_subdev->device->dev, "%s: "f,                         \
                         nvkm_subdev_name[_subdev->index], ##a);                \
         }                                                                      \
diff --combined drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h

index 5f5cae7c474e88ab7633adad9a2ca0182658ef6d,b672a3b07f5542243e42bdb7076250407ccb0a93..0f9c1c702ed6141f8091f3ca95ea229b1d6726ef
--- 1/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
@@@ -1,7 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_DMA_H__
   #define __NVKM_DMA_H__
   #include <core/engine.h>
+ #include <core/object.h>
   struct nvkm_client;
   
   struct nvkm_dmaobj {
diff --combined drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

index 5a51842bc241c9d4320c72822d59a80d5d077f87,f0024fb5a5aff8294b76a65be4c65aa7b215dc58..6427747b6f77ffc4f599881808524dc357d276c5
--- 1/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
@@@ -1,9 -1,9 +1,10 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_FALCON_H__
   #define __NVKM_FALCON_H__
   #define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine)
   #include <core/engine.h>
   struct nvkm_fifo_chan;
+ struct nvkm_gpuobj;
   
   enum nvkm_falcon_dmaidx {
         FALCON_DMAIDX_UCODE             = 0,
@@@ -78,7 -78,7 +79,7 @@@ struct nvkm_falcon_func 
         void (*load_imem)(struct nvkm_falcon *, void *, u32, u32, u16, u8, bool);
         void (*load_dmem)(struct nvkm_falcon *, void *, u32, u32, u8);
         void (*read_dmem)(struct nvkm_falcon *, u32, u32, u8, void *);
-       void (*bind_context)(struct nvkm_falcon *, struct nvkm_gpuobj *);
+       void (*bind_context)(struct nvkm_falcon *, struct nvkm_memory *);
         int (*wait_for_halt)(struct nvkm_falcon *, u32);
         int (*clear_interrupt)(struct nvkm_falcon *, u32);
         void (*set_start_addr)(struct nvkm_falcon *, u32 start_addr);
@@@ -113,7 -113,7 +114,7 @@@ void nvkm_falcon_load_imem(struct nvkm_
                            bool);
   void nvkm_falcon_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8);
   void nvkm_falcon_read_dmem(struct nvkm_falcon *, u32, u32, u8, void *);
- void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_gpuobj *);
+ void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_memory *);
   void nvkm_falcon_set_start_addr(struct nvkm_falcon *, u32);
   void nvkm_falcon_start(struct nvkm_falcon *);
   int nvkm_falcon_wait_for_halt(struct nvkm_falcon *, u32);
diff --combined drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h

index 025f400c9f5d9f4b14a8b576cfdfc1f395c41460,e42d686fbd8b424ff2dd5d58c7957c9e26ae1d0c..c17b3a9bf8fbc0411c6655459e91a0078303d913
--- 1/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
@@@ -1,7 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_FIFO_H__
   #define __NVKM_FIFO_H__
   #include <core/engine.h>
+ #include <core/object.h>
   #include <core/event.h>
   
   #define NVKM_FIFO_CHID_NR 4096
@@@ -22,7 -22,7 +23,7 @@@ struct nvkm_fifo_chan 
         u16 chid;
         struct nvkm_gpuobj *inst;
         struct nvkm_gpuobj *push;
-       struct nvkm_vm *vm;
+       struct nvkm_vmm *vmm;
         void __iomem *user;
         u64 addr;
         u32 size;
diff --combined drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h

index 91f1e0efe061c82b3576b3706c22e5a26f48ec4f,ffa963939e15bf566245ffb41a31841d26c6305f..f6bd94c7e0f75fa71586a41270a1865c6c702a11
--- 1/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_BAR_H__
   #define __NVKM_BAR_H__
   #include <core/subdev.h>
@@@ -9,17 -8,22 +9,22 @@@ struct nvkm_bar 
         struct nvkm_subdev subdev;
   
         spinlock_t lock;
+       bool bar2;
   
         /* whether the BAR supports to be ioremapped WC or should be uncached */
         bool iomap_uncached;
   };
   
+ struct nvkm_vmm *nvkm_bar_bar1_vmm(struct nvkm_device *);
+ void nvkm_bar_bar2_init(struct nvkm_device *);
+ void nvkm_bar_bar2_fini(struct nvkm_device *);
+ struct nvkm_vmm *nvkm_bar_bar2_vmm(struct nvkm_device *);
   void nvkm_bar_flush(struct nvkm_bar *);
- struct nvkm_vm *nvkm_bar_kmap(struct nvkm_bar *);
- int nvkm_bar_umap(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
   
   int nv50_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
   int g84_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
   int gf100_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
   int gk20a_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
+ int gm107_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
+ int gm20b_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h

index 4da68dd5261948a52df0b32809ee358545647950,a00fd2e59215c462bd27432d9812e185a1e09ee4..adb78f7d083ad8fb57330ef4870305f3dd97d30b
--- 1/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
@@@ -1,9 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_FB_H__
   #define __NVKM_FB_H__
   #include <core/subdev.h>
- 
- #include <subdev/mmu.h>
+ #include <core/mm.h>
   
   /* memory type/access flags, do not match hardware values */
   #define NV_MEM_ACCESS_RO  1
@@@ -22,22 -20,6 +21,6 @@@
   #define NVKM_RAM_TYPE_VM 0x7f
   #define NV_MEM_COMP_VM 0x03
   
- struct nvkm_mem {
-       struct drm_device *dev;
- 
-       struct nvkm_vma bar_vma;
-       struct nvkm_vma vma[2];
-       u8  page_shift;
- 
-       struct nvkm_mm_node *tag;
-       struct nvkm_mm_node *mem;
-       dma_addr_t *pages;
-       u32 memtype;
-       u64 offset;
-       u64 size;
-       struct sg_table *sg;
- };
- 
   struct nvkm_fb_tile {
         struct nvkm_mm_node *tag;
         u32 addr;
@@@ -51,6 -33,7 +34,7 @@@ struct nvkm_fb 
         struct nvkm_subdev subdev;
   
         struct nvkm_ram *ram;
+       struct nvkm_mm tags;
   
         struct {
                 struct nvkm_fb_tile region[16];
@@@ -63,7 -46,6 +47,6 @@@
         struct nvkm_memory *mmu_wr;
   };
   
- bool nvkm_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
   void nvkm_fb_tile_init(struct nvkm_fb *, int region, u32 addr, u32 size,
                        u32 pitch, u32 flags, struct nvkm_fb_tile *);
   void nvkm_fb_tile_fini(struct nvkm_fb *, int region, struct nvkm_fb_tile *);
@@@ -130,8 -112,11 +113,11 @@@ struct nvkm_ram 
         u64 size;
   
   #define NVKM_RAM_MM_SHIFT 12
+ #define NVKM_RAM_MM_ANY    (NVKM_MM_HEAP_ANY + 0)
+ #define NVKM_RAM_MM_NORMAL (NVKM_MM_HEAP_ANY + 1)
+ #define NVKM_RAM_MM_NOMAP  (NVKM_MM_HEAP_ANY + 2)
+ #define NVKM_RAM_MM_MIXED  (NVKM_MM_HEAP_ANY + 3)
         struct nvkm_mm vram;
-       struct nvkm_mm tags;
         u64 stolen;
   
         int ranks;
@@@ -148,6 -133,10 +134,10 @@@
         struct nvkm_ram_data target;
   };
   
+ int
+ nvkm_ram_get(struct nvkm_device *, u8 heap, u8 type, u8 page, u64 size,
+            bool contig, bool back, struct nvkm_memory **);
+ 
   struct nvkm_ram_func {
         u64 upper;
         u32 (*probe_fbp)(const struct nvkm_ram_func *, struct nvkm_device *,
@@@ -158,14 -147,8 +148,8 @@@
         void *(*dtor)(struct nvkm_ram *);
         int (*init)(struct nvkm_ram *);
   
-       int (*get)(struct nvkm_ram *, u64 size, u32 align, u32 size_nc,
-                  u32 type, struct nvkm_mem **);
-       void (*put)(struct nvkm_ram *, struct nvkm_mem **);
- 
         int (*calc)(struct nvkm_ram *, u32 freq);
         int (*prog)(struct nvkm_ram *);
         void (*tidy)(struct nvkm_ram *);
   };
- 
- extern const u8 gf100_pte_storage_type_map[256];
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h

index 91126fd292223f8f70f8284ebb0f0e32efcb5448,8111c0c3c5ecd9c2bc2f1593228a6be89641eafe..36ed520ed2d0178a737e162ba573d60ae6a2d972
--- 1/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_INSTMEM_H__
   #define __NVKM_INSTMEM_H__
   #include <core/subdev.h>
@@@ -10,6 -9,7 +10,7 @@@ struct nvkm_instmem 
   
         spinlock_t lock;
         struct list_head list;
+       struct list_head boot;
         u32 reserved;
   
         struct nvkm_memory *vbios;
diff --combined drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h

index 63b7ad1f9ce23cd322b77a2cdc0c5188f93d7660,4a224fd22e48b1b8018122062cb2ca55fbc9b78b..95b611554d535d3b4093ba11a30057f8c98b9e1c
--- 1/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_LTC_H__
   #define __NVKM_LTC_H__
   #include <core/subdev.h>
@@@ -15,8 -14,7 +15,7 @@@ struct nvkm_ltc 
   
         u32 num_tags;
         u32 tag_base;
-       struct nvkm_mm tags;
-       struct nvkm_mm_node *tag_ram;
+       struct nvkm_memory *tag_ram;
   
         int zbc_min;
         int zbc_max;
@@@ -24,9 -22,7 +23,7 @@@
         u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
   };
   
- int nvkm_ltc_tags_alloc(struct nvkm_ltc *, u32 count, struct nvkm_mm_node **);
- void nvkm_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
- void nvkm_ltc_tags_clear(struct nvkm_ltc *, u32 first, u32 count);
+ void nvkm_ltc_tags_clear(struct nvkm_device *, u32 first, u32 count);
   
   int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]);
   int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32);
diff --combined drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h

index 0fdfc610ceb3e0d2d669011b1741b5db54461f83,975c42f620a08bd2e413d9eb56c7bc2a0895d274..0760b93e9d1fd84a7833c3247a2bc4e9cec069e7
--- 1/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
@@@ -1,69 -1,130 +1,131 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_MMU_H__
   #define __NVKM_MMU_H__
   #include <core/subdev.h>
- #include <core/mm.h>
- struct nvkm_device;
- struct nvkm_mem;
- 
- struct nvkm_vm_pgt {
-       struct nvkm_memory *mem[2];
-       u32 refcount[2];
- };
- 
- struct nvkm_vm_pgd {
-       struct list_head head;
-       struct nvkm_gpuobj *obj;
- };
   
   struct nvkm_vma {
         struct list_head head;
-       int refcount;
-       struct nvkm_vm *vm;
-       struct nvkm_mm_node *node;
-       u64 offset;
-       u32 access;
+       struct rb_node tree;
+       u64 addr;
+       u64 size:50;
+       bool mapref:1; /* PTs (de)referenced on (un)map (vs pre-allocated). */
+       bool sparse:1; /* Unmapped PDEs/PTEs will not trigger MMU faults. */
+ #define NVKM_VMA_PAGE_NONE 7
+       u8   page:3; /* Requested page type (index, or NONE for automatic). */
+       u8   refd:3; /* Current page type (index, or NONE for unreferenced). */
+       bool used:1; /* Region allocated. */
+       bool part:1; /* Region was split from an allocated region by map(). */
+       bool user:1; /* Region user-allocated. */
+       bool busy:1; /* Region busy (for temporarily preventing user access). */
+       struct nvkm_memory *memory; /* Memory currently mapped into VMA. */
+       struct nvkm_tags *tags; /* Compression tag reference. */
   };
   
- struct nvkm_vm {
+ struct nvkm_vmm {
+       const struct nvkm_vmm_func *func;
         struct nvkm_mmu *mmu;
- 
+       const char *name;
+       u32 debug;
+       struct kref kref;
         struct mutex mutex;
-       struct nvkm_mm mm;
-       struct kref refcount;
   
-       struct list_head pgd_list;
+       u64 start;
+       u64 limit;
+ 
+       struct nvkm_vmm_pt *pd;
+       struct list_head join;
+ 
+       struct list_head list;
+       struct rb_root free;
+       struct rb_root root;
+ 
+       bool bootstrapped;
         atomic_t engref[NVKM_SUBDEV_NR];
   
-       struct nvkm_vm_pgt *pgt;
-       u32 fpde;
-       u32 lpde;
+       dma_addr_t null;
+       void *nullp;
   };
   
- int  nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
-                struct lock_class_key *, struct nvkm_vm **);
- int  nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
- int  nvkm_vm_boot(struct nvkm_vm *, u64 size);
- int  nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
-                struct nvkm_vma *);
- void nvkm_vm_put(struct nvkm_vma *);
- void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
- void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
- void nvkm_vm_unmap(struct nvkm_vma *);
- void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
+ int nvkm_vmm_new(struct nvkm_device *, u64 addr, u64 size, void *argv, u32 argc,
+                struct lock_class_key *, const char *name, struct nvkm_vmm **);
+ struct nvkm_vmm *nvkm_vmm_ref(struct nvkm_vmm *);
+ void nvkm_vmm_unref(struct nvkm_vmm **);
+ int nvkm_vmm_boot(struct nvkm_vmm *);
+ int nvkm_vmm_join(struct nvkm_vmm *, struct nvkm_memory *inst);
+ void nvkm_vmm_part(struct nvkm_vmm *, struct nvkm_memory *inst);
+ int nvkm_vmm_get(struct nvkm_vmm *, u8 page, u64 size, struct nvkm_vma **);
+ void nvkm_vmm_put(struct nvkm_vmm *, struct nvkm_vma **);
+ 
+ struct nvkm_vmm_map {
+       struct nvkm_memory *memory;
+       u64 offset;
+ 
+       struct nvkm_mm_node *mem;
+       struct scatterlist *sgl;
+       dma_addr_t *dma;
+       u64 off;
+ 
+       const struct nvkm_vmm_page *page;
+ 
+       struct nvkm_tags *tags;
+       u64 next;
+       u64 type;
+       u64 ctag;
+ };
+ 
+ int nvkm_vmm_map(struct nvkm_vmm *, struct nvkm_vma *, void *argv, u32 argc,
+                struct nvkm_vmm_map *);
+ void nvkm_vmm_unmap(struct nvkm_vmm *, struct nvkm_vma *);
+ 
+ struct nvkm_memory *nvkm_umem_search(struct nvkm_client *, u64);
+ struct nvkm_vmm *nvkm_uvmm_search(struct nvkm_client *, u64 handle);
   
   struct nvkm_mmu {
         const struct nvkm_mmu_func *func;
         struct nvkm_subdev subdev;
   
-       u64 limit;
         u8  dma_bits;
-       u8  lpg_shift;
+ 
+       int heap_nr;
+       struct {
+ #define NVKM_MEM_VRAM                                                      0x01
+ #define NVKM_MEM_HOST                                                      0x02
+ #define NVKM_MEM_COMP                                                      0x04
+ #define NVKM_MEM_DISP                                                      0x08
+               u8  type;
+               u64 size;
+       } heap[4];
+ 
+       int type_nr;
+       struct {
+ #define NVKM_MEM_KIND                                                      0x10
+ #define NVKM_MEM_MAPPABLE                                                  0x20
+ #define NVKM_MEM_COHERENT                                                  0x40
+ #define NVKM_MEM_UNCACHED                                                  0x80
+               u8 type;
+               u8 heap;
+       } type[16];
+ 
+       struct nvkm_vmm *vmm;
+ 
+       struct {
+               struct mutex mutex;
+               struct list_head list;
+       } ptc, ptp;
+ 
+       struct nvkm_device_oclass user;
   };
   
   int nv04_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
   int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
   int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
   int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int g84_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
   int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int gk104_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int gk20a_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int gm200_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int gm20b_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int gp100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
+ int gp10b_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
   #endif
diff --combined drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h

index 98fe1d0fd592021608ee329dde698d69b5481e89,9841f076da2e5c871f96a6dc076ee491d55dd5f9..b1ac47eb786e7a541aa8770f49da50a5ed753706
--- 1/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
--- 2/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_THERM_H__
   #define __NVKM_THERM_H__
   #include <core/subdev.h>
@@@ -98,4 -97,5 +98,5 @@@ int gt215_therm_new(struct nvkm_device 
   int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
   int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
   int gm200_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
+ int gp100_therm_new(struct nvkm_device *, int, struct nvkm_therm **);
   #endif
diff --combined drivers/gpu/drm/nouveau/nouveau_abi16.h

index 441100aa2320b70bd7b88aa0e79b6f9f66af8622,32774768032483c435b9f0fd59732b33b22a6f6e..36fde1ff3ad5d886c3f3cf92c59b6cdd5384779e
--- 1/drivers/gpu/drm/nouveau/nouveau_abi16.h
--- 2/drivers/gpu/drm/nouveau/nouveau_abi16.h
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_ABI16_H__
   #define __NOUVEAU_ABI16_H__
   
@@@ -24,7 -23,7 +24,7 @@@ struct nouveau_abi16_chan 
         struct nouveau_channel *chan;
         struct list_head notifiers;
         struct nouveau_bo *ntfy;
-       struct nvkm_vma ntfy_vma;
+       struct nouveau_vma *ntfy_vma;
         struct nvkm_mm  heap;
   };
   
diff --combined drivers/gpu/drm/nouveau/nouveau_bo.h

index 4caade5dee501845cc6dfc586c955cb2db738f2b,23002bdd94a894d14e17d0f2f9cb1002791ae5e2..7b5cc5c73d208987e533d15c22c2ca43acc62ef3
--- 1/drivers/gpu/drm/nouveau/nouveau_bo.h
--- 2/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_BO_H__
   #define __NOUVEAU_BO_H__
   
@@@ -25,12 -24,16 +25,16 @@@ struct nouveau_bo 
         bool validate_mapped;
   
         struct list_head vma_list;
-       unsigned page_shift;
   
         struct nouveau_cli *cli;
   
-       u32 tile_mode;
-       u32 tile_flags;
+       unsigned contig:1;
+       unsigned page:5;
+       unsigned kind:8;
+       unsigned comp:3;
+       unsigned zeta:3;
+       unsigned mode;
+ 
         struct nouveau_drm_tile *tile;
   
         /* Only valid if allocated via nouveau_gem_new() and iff you hold a
@@@ -90,13 -93,6 +94,6 @@@ int  nouveau_bo_validate(struct nouveau
   void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo);
   void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo);
   
- struct nvkm_vma *
- nouveau_bo_vma_find(struct nouveau_bo *, struct nvkm_vm *);
- 
- int  nouveau_bo_vma_add(struct nouveau_bo *, struct nvkm_vm *,
-                       struct nvkm_vma *);
- void nouveau_bo_vma_del(struct nouveau_bo *, struct nvkm_vma *);
- 
   /* TODO: submit equivalent to TTM generic API upstream? */
   static inline void __iomem *
   nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
diff --combined drivers/gpu/drm/nouveau/nouveau_chan.h

index 9463a78613cb64780a42f461a9e8cd5a03b1620c,f29d3a72c48c5530519651496e878f5488911640..14607c16a2bd6a1755c4fb27268efd8eb50c608e
--- 1/drivers/gpu/drm/nouveau/nouveau_chan.h
--- 2/drivers/gpu/drm/nouveau/nouveau_chan.h
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_CHAN_H__
   #define __NOUVEAU_CHAN_H__
   #include <nvif/object.h>
@@@ -17,8 -16,9 +17,9 @@@ struct nouveau_channel 
   
         struct {
                 struct nouveau_bo *buffer;
-               struct nvkm_vma vma;
+               struct nouveau_vma *vma;
                 struct nvif_object ctxdma;
+               u64 addr;
         } push;
   
         /* TODO: this will be reworked in the near future */
diff --combined drivers/gpu/drm/nouveau/nouveau_display.h

index 34cd144681b9ba71a0e5fcc94a48ba8cdf4be517,1411bf05b89d5de1971cacd91856257a668aed7b..270ba56f27560e91205e922cd6f0551d1f7e475e
--- 1/drivers/gpu/drm/nouveau/nouveau_display.h
--- 2/drivers/gpu/drm/nouveau/nouveau_display.h
+++ b/drivers/gpu/drm/nouveau/nouveau_display.h
@@@ -1,15 -1,11 +1,12 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_DISPLAY_H__
   #define __NOUVEAU_DISPLAY_H__
- 
- #include <subdev/mmu.h>
- 
   #include "nouveau_drv.h"
   
   struct nouveau_framebuffer {
         struct drm_framebuffer base;
         struct nouveau_bo *nvbo;
-       struct nvkm_vma vma;
+       struct nouveau_vma *vma;
         u32 r_handle;
         u32 r_format;
         u32 r_pitch;
diff --combined drivers/gpu/drm/nouveau/nouveau_drv.h

index 77dea95c1bf12fcf92e1749a83b7f0d5585bc7e9,e86b8220a4bb66d95d0f073cdcc83c9f7c46381f..3331e82ae9e7130b18f4a6f307cc284519f873d3
--- 1/drivers/gpu/drm/nouveau/nouveau_drv.h
--- 2/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_DRV_H__
   #define __NOUVEAU_DRV_H__
   
@@@ -6,7 -5,7 +6,7 @@@
   #define DRIVER_EMAIL          "nouveau@lists.freedesktop.org"
   
   #define DRIVER_NAME           "nouveau"
- #define DRIVER_DESC           "nVidia Riva/TNT/GeForce/Quadro/Tesla"
+ #define DRIVER_DESC           "nVidia Riva/TNT/GeForce/Quadro/Tesla/Tegra K1+"
   #define DRIVER_DATE           "20120801"
   
   #define DRIVER_MAJOR          1
@@@ -43,6 -42,8 +43,8 @@@
   #include <nvif/client.h>
   #include <nvif/device.h>
   #include <nvif/ioctl.h>
+ #include <nvif/mmu.h>
+ #include <nvif/vmm.h>
   
   #include <drm/drmP.h>
   
@@@ -62,6 -63,7 +64,7 @@@ struct platform_device
   
   #include "nouveau_fence.h"
   #include "nouveau_bios.h"
+ #include "nouveau_vmm.h"
   
   struct nouveau_drm_tile {
         struct nouveau_fence *fence;
@@@ -87,19 -89,37 +90,37 @@@ enum nouveau_drm_handle 
   
   struct nouveau_cli {
         struct nvif_client base;
-       struct drm_device *dev;
+       struct nouveau_drm *drm;
         struct mutex mutex;
   
         struct nvif_device device;
+       struct nvif_mmu mmu;
+       struct nouveau_vmm vmm;
+       const struct nvif_mclass *mem;
   
-       struct nvkm_vm *vm; /*XXX*/
         struct list_head head;
         void *abi16;
         struct list_head objects;
         struct list_head notifys;
         char name[32];
+ 
+       struct work_struct work;
+       struct list_head worker;
+       struct mutex lock;
   };
   
+ struct nouveau_cli_work {
+       void (*func)(struct nouveau_cli_work *);
+       struct nouveau_cli *cli;
+       struct list_head head;
+ 
+       struct dma_fence *fence;
+       struct dma_fence_cb cb;
+ };
+ 
+ void nouveau_cli_work_queue(struct nouveau_cli *, struct dma_fence *,
+                           struct nouveau_cli_work *);
+ 
   static inline struct nouveau_cli *
   nouveau_cli(struct drm_file *fpriv)
   {
@@@ -110,6 -130,7 +131,7 @@@
   #include <nvif/device.h>
   
   struct nouveau_drm {
+       struct nouveau_cli master;
         struct nouveau_cli client;
         struct drm_device *dev;
   
@@@ -134,6 -155,9 +156,9 @@@
                 struct nouveau_channel *chan;
                 struct nvif_object copy;
                 int mtrr;
+               int type_vram;
+               int type_host;
+               int type_ncoh;
         } ttm;
   
         /* GEM interface support */
@@@ -205,7 -229,7 +230,7 @@@ void nouveau_drm_device_remove(struct d
   
   #define NV_PRINTK(l,c,f,a...) do {                                             \
         struct nouveau_cli *_cli = (c);                                        \
-       dev_##l(_cli->dev->dev, "%s: "f, _cli->name, ##a);                     \
+       dev_##l(_cli->drm->dev->dev, "%s: "f, _cli->name, ##a);                \
   } while(0)
   #define NV_FATAL(drm,f,a...) NV_PRINTK(crit, &(drm)->client, f, ##a)
   #define NV_ERROR(drm,f,a...) NV_PRINTK(err, &(drm)->client, f, ##a)
diff --combined drivers/gpu/drm/nouveau/nouveau_fence.h

index c9b399ad89e6f732bd878bf2400c5ed7cbfb5b69,c36031aa013e7c3bd00d66876d13dea1a6e08e6a..5bd8d30d165702269de4beeccf2199a377b9cecf
--- 1/drivers/gpu/drm/nouveau/nouveau_fence.h
--- 2/drivers/gpu/drm/nouveau/nouveau_fence.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_FENCE_H__
   #define __NOUVEAU_FENCE_H__
   
@@@ -13,8 -12,6 +13,6 @@@ struct nouveau_fence 
   
         struct list_head head;
   
-       bool sysmem;
- 
         struct nouveau_channel __rcu *channel;
         unsigned long timeout;
   };
@@@ -25,7 -22,6 +23,6 @@@ void nouveau_fence_unref(struct nouveau
   
   int  nouveau_fence_emit(struct nouveau_fence *, struct nouveau_channel *);
   bool nouveau_fence_done(struct nouveau_fence *);
- void nouveau_fence_work(struct dma_fence *, void (*)(void *), void *);
   int  nouveau_fence_wait(struct nouveau_fence *, bool lazy, bool intr);
   int  nouveau_fence_sync(struct nouveau_bo *, struct nouveau_channel *, bool exclusive, bool intr);
   
@@@ -91,14 -87,12 +88,12 @@@ int nouveau_flip_complete(struct nvif_n
   
   struct nv84_fence_chan {
         struct nouveau_fence_chan base;
-       struct nvkm_vma vma;
-       struct nvkm_vma vma_gart;
+       struct nouveau_vma *vma;
   };
   
   struct nv84_fence_priv {
         struct nouveau_fence_priv base;
         struct nouveau_bo *bo;
-       struct nouveau_bo *bo_gart;
         u32 *suspend;
         struct mutex mutex;
   };
diff --combined drivers/gpu/drm/nouveau/nouveau_gem.h

index 0456c94a5d4df29d5b7cb64e867d7f3efaf36df7,d39f845dda8755ce28b0d7cfadc96e891ccc0344..fe39998f65cc054de3a3767e1fd43937fbf13c6e
--- 1/drivers/gpu/drm/nouveau/nouveau_gem.h
--- 2/drivers/gpu/drm/nouveau/nouveau_gem.h
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NOUVEAU_GEM_H__
   #define __NOUVEAU_GEM_H__
   
@@@ -7,9 -6,6 +7,6 @@@
   #include "nouveau_drv.h"
   #include "nouveau_bo.h"
   
- #define nouveau_bo_tile_layout(nvbo)                          \
-       ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
- 
   static inline struct nouveau_bo *
   nouveau_gem_object(struct drm_gem_object *gem)
   {
diff --combined drivers/gpu/drm/nouveau/nouveau_sgdma.c

index fde11ce466e45cca46ee81c611e9e345332ab525,941bf33bd24970c667b10b2315503649730ad683..11f6ca89769b4d003c3ffe35ced95a01045e5e0a
--- 1/drivers/gpu/drm/nouveau/nouveau_sgdma.c
--- 2/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@@ -1,8 -1,8 +1,9 @@@
+ +// SPDX-License-Identifier: GPL-2.0
   #include <linux/pagemap.h>
   #include <linux/slab.h>
   
   #include "nouveau_drv.h"
+ #include "nouveau_mem.h"
   #include "nouveau_ttm.h"
   
   struct nouveau_sgdma_be {
@@@ -10,7 -10,7 +11,7 @@@
          * nouve_bo.c works properly, otherwise have to move them here
          */
         struct ttm_dma_tt ttm;
-       struct nvkm_mem *node;
+       struct nouveau_mem *mem;
   };
   
   static void
@@@ -28,19 -28,20 +29,20 @@@ static in
   nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *reg)
   {
         struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
-       struct nvkm_mem *node = reg->mm_node;
- 
-       if (ttm->sg) {
-               node->sg    = ttm->sg;
-               node->pages = NULL;
-       } else {
-               node->sg    = NULL;
-               node->pages = nvbe->ttm.dma_address;
+       struct nouveau_mem *mem = nouveau_mem(reg);
+       int ret;
+ 
+       ret = nouveau_mem_host(reg, &nvbe->ttm);
+       if (ret)
+               return ret;
+ 
+       ret = nouveau_mem_map(mem, &mem->cli->vmm.vmm, &mem->vma[0]);
+       if (ret) {
+               nouveau_mem_fini(mem);
+               return ret;
         }
-       node->size = (reg->num_pages << PAGE_SHIFT) >> 12;
   
-       nvkm_vm_map(&node->vma[0], node);
-       nvbe->node = node;
+       nvbe->mem = mem;
         return 0;
   }
   
@@@ -48,7 -49,7 +50,7 @@@ static in
   nv04_sgdma_unbind(struct ttm_tt *ttm)
   {
         struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
-       nvkm_vm_unmap(&nvbe->node->vma[0]);
+       nouveau_mem_fini(nvbe->mem);
         return 0;
   }
   
@@@ -62,30 -63,20 +64,20 @@@ static in
   nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *reg)
   {
         struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
-       struct nvkm_mem *node = reg->mm_node;
- 
-       /* noop: bound in move_notify() */
-       if (ttm->sg) {
-               node->sg    = ttm->sg;
-               node->pages = NULL;
-       } else {
-               node->sg    = NULL;
-               node->pages = nvbe->ttm.dma_address;
-       }
-       node->size = (reg->num_pages << PAGE_SHIFT) >> 12;
-       return 0;
- }
+       struct nouveau_mem *mem = nouveau_mem(reg);
+       int ret;
   
- static int
- nv50_sgdma_unbind(struct ttm_tt *ttm)
- {
-       /* noop: unbound in move_notify() */
+       ret = nouveau_mem_host(reg, &nvbe->ttm);
+       if (ret)
+               return ret;
+ 
+       nvbe->mem = mem;
         return 0;
   }
   
   static struct ttm_backend_func nv50_sgdma_backend = {
         .bind                   = nv50_sgdma_bind,
-       .unbind                 = nv50_sgdma_unbind,
+       .unbind                 = nv04_sgdma_unbind,
         .destroy                = nouveau_sgdma_destroy
   };
   
diff --combined drivers/gpu/drm/nouveau/nv50_display.c

index fb47d46050ec4f688664065f94ade1d9ab3bb2c0,92d46222c79dfa51bdb58413d788821322f3c26f..584466ef688f5f965acf14de06f06a217bc1afab
--- 1/drivers/gpu/drm/nouveau/nv50_display.c
--- 2/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@@ -318,7 -318,7 +318,7 @@@ nv50_chan_create(struct nvif_device *de
                                 ret = nvif_object_init(disp, 0, oclass[0],
                                                        data, size, &chan->user);
                                 if (ret == 0)
-                                       nvif_object_map(&chan->user);
+                                       nvif_object_map(&chan->user, NULL, 0);
                                 nvif_object_sclass_put(&sclass);
                                 return ret;
                         }
@@@ -424,7 -424,7 +424,7 @@@ nv50_dmac_ctxdma_new(struct nv50_dmac *
   {
         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
         struct nv50_dmac_ctxdma *ctxdma;
-       const u8    kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
+       const u8    kind = fb->nvbo->kind;
         const u32 handle = 0xfb000000 | kind;
         struct {
                 struct nv_dma_v0 base;
@@@ -510,6 -510,7 +510,7 @@@ nv50_dmac_create(struct nvif_device *de
         int ret;
   
         mutex_init(&dmac->lock);
+       INIT_LIST_HEAD(&dmac->ctxdma);
   
         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
                                        &dmac->handle, GFP_KERNEL);
@@@ -556,7 -557,6 +557,6 @@@
         if (ret)
                 return ret;
   
-       INIT_LIST_HEAD(&dmac->ctxdma);
         return ret;
   }
   
@@@ -847,7 -847,7 +847,7 @@@ nv50_wndw_atomic_check_acquire(struct n
   
         asyw->image.w = fb->base.width;
         asyw->image.h = fb->base.height;
-       asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
+       asyw->image.kind = fb->nvbo->kind;
   
         if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
                 asyw->interval = 0;
@@@ -857,9 -857,9 +857,9 @@@
         if (asyw->image.kind) {
                 asyw->image.layout = 0;
                 if (drm->client.device.info.chipset >= 0xc0)
-                       asyw->image.block = fb->nvbo->tile_mode >> 4;
+                       asyw->image.block = fb->nvbo->mode >> 4;
                 else
-                       asyw->image.block = fb->nvbo->tile_mode;
+                       asyw->image.block = fb->nvbo->mode;
                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
         } else {
                 asyw->image.layout = 1;
@@@ -4099,7 -4099,7 +4099,7 @@@ nv50_disp_atomic_commit(struct drm_devi
   {
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nv50_disp *disp = nv50_disp(dev);
- -      struct drm_plane_state *old_plane_state;
+ +      struct drm_plane_state *new_plane_state;
         struct drm_plane *plane;
         struct drm_crtc *crtc;
         bool active = false;
@@@ -4129,8 -4129,8 +4129,8 @@@
         if (ret)
                 goto err_cleanup;
   
- -      for_each_old_plane_in_state(state, plane, old_plane_state, i) {
- -              struct nv50_wndw_atom *asyw = nv50_wndw_atom(old_plane_state);
+ +      for_each_new_plane_in_state(state, plane, new_plane_state, i) {
+ +              struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
                 struct nv50_wndw *wndw = nv50_wndw(plane);
   
                 if (asyw->set.image) {
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h

index f279162f48c6b239443f0de2997a3e5b88ed167c,2c3c3ee3c494a879e479d8b9b6bdd66c9518e25c..ebcc5c52fbd1ede346bb95f58b88acc39d6a10d6
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h
@@@ -1,8 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_DEVICE_CTRL_H__
   #define __NVKM_DEVICE_CTRL_H__
   #define nvkm_control(p) container_of((p), struct nvkm_control, object)
- #include <core/device.h>
+ #include <core/object.h>
   
   struct nvkm_control {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h

index 5701b3221a54e093f3ba383ba1e9b7ddf5570817,9bb4ad5b0e57ff17fb0863390a5b4c7b79a82822..40681db91a022a9cd90d20f01b8e19b03c8324a2
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
@@@ -1,7 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV50_DISP_CHAN_H__
   #define __NV50_DISP_CHAN_H__
   #define nv50_disp_chan(p) container_of((p), struct nv50_disp_chan, object)
+ #include <core/object.h>
   #include "nv50.h"
   
   struct nv50_disp_chan {
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

index cd6dd8742dc62e64bd81d7d51e890a43a55bcb96,c9e0a8f7b5d5cbcb5ae936fcf649d00f4c213710..4548c031b9375f24951cbec7a15bd54561208e75
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_DISP_IOR_H__
   #define __NVKM_DISP_IOR_H__
   #include "priv.h"
@@@ -148,7 -147,7 +148,7 @@@ void gf119_hda_eld(struct nvkm_ior *, u
   
   #define IOR_MSG(i,l,f,a...) do {                                               \
         struct nvkm_ior *_ior = (i);                                           \
-       nvkm_##l(&_ior->disp->engine.subdev, "%s: "f, _ior->name, ##a);        \
+       nvkm_##l(&_ior->disp->engine.subdev, "%s: "f"\n", _ior->name, ##a);    \
   } while(0)
   #define IOR_WARN(i,f,a...) IOR_MSG((i), warn, f, ##a)
   #define IOR_DBG(i,f,a...) IOR_MSG((i), debug, f, ##a)
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h

index 27002caba42066123b4ecf45c37c28c05b426fa7,fc1142af02cfb1512aaf1d8a9720cfb5654e886c..b653664e081bbd702514b9b11609e796342ed113
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __GF100_FIFO_CHAN_H__
   #define __GF100_FIFO_CHAN_H__
   #define gf100_fifo_chan(p) container_of((p), struct gf100_fifo_chan, base)
@@@ -12,12 -11,9 +12,9 @@@ struct gf100_fifo_chan 
         struct list_head head;
         bool killed;
   
-       struct nvkm_gpuobj *pgd;
-       struct nvkm_vm *vm;
- 
         struct {
                 struct nvkm_gpuobj *inst;
-               struct nvkm_vma vma;
+               struct nvkm_vma *vma;
         } engn[NVKM_SUBDEV_NR];
   };
   
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h

index ec10be2984a95d01de7a18bd758ba1825e4064b3,5beb5c628473e6355ce53b491ce6ecf75f066f7b..1208e3d9dbe283da18ad25435272815bf0084b6f
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __GK104_FIFO_CHAN_H__
   #define __GK104_FIFO_CHAN_H__
   #define gk104_fifo_chan(p) container_of((p), struct gk104_fifo_chan, base)
@@@ -13,12 -12,9 +13,9 @@@ struct gk104_fifo_chan 
         struct list_head head;
         bool killed;
   
-       struct nvkm_gpuobj *pgd;
-       struct nvkm_vm *vm;
- 
         struct {
                 struct nvkm_gpuobj *inst;
-               struct nvkm_vma vma;
+               struct nvkm_vma *vma;
         } engn[NVKM_SUBDEV_NR];
   };
   
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h

index ad9aa157e07831c8211ad1fb3f5efde0b2712cef,d853056e040bfca8a158a4af9f5d1ba800f6e640..2e3c4005b874ed98afe0798468ce57064044e2d8
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV50_FIFO_CHAN_H__
   #define __NV50_FIFO_CHAN_H__
   #define nv50_fifo_chan(p) container_of((p), struct nv50_fifo_chan, base)
@@@ -14,19 -13,18 +14,18 @@@ struct nv50_fifo_chan 
         struct nvkm_gpuobj *eng;
         struct nvkm_gpuobj *pgd;
         struct nvkm_ramht *ramht;
-       struct nvkm_vm *vm;
   
         struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR];
   };
   
- int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push,
+ int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,
                         const struct nvkm_oclass *, struct nv50_fifo_chan *);
   void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *);
   void nv50_fifo_chan_fini(struct nvkm_fifo_chan *);
   void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *);
   void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int);
   
- int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push,
+ int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,
                        const struct nvkm_oclass *, struct nv50_fifo_chan *);
   
   extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h

index 571a6edb3f97671a0ee05a9b7890c7bd0c747c24,b81a2ad48aa4a2a22f65ad0a513aab4bee0c8898..68f97ba03df696164a8eed26d9b63c773a8a398b
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __GF100_FIFO_H__
   #define __GF100_FIFO_H__
   #define gf100_fifo(p) container_of((p), struct gf100_fifo, base)
@@@ -27,7 -26,7 +27,7 @@@ struct gf100_fifo 
   
         struct {
                 struct nvkm_memory *mem;
-               struct nvkm_vma bar;
+               struct nvkm_vma *bar;
         } user;
   };
   
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h

index 0506c52909361ca4150e93795dc9df60bbcdf75a,466f1051f91afa0280649c91a066dec516b91b43..1579785cf941ef34eb48fb2494023b606ab30766
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __GK104_FIFO_H__
   #define __GK104_FIFO_H__
   #define gk104_fifo(p) container_of((p), struct gk104_fifo, base)
@@@ -38,7 -37,7 +38,7 @@@ struct gk104_fifo 
   
         struct {
                 struct nvkm_memory *mem;
-               struct nvkm_vma bar;
+               struct nvkm_vma *bar;
         } user;
   };
   
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h

index 2812ca511c9c3304608ac1fd0c5a67ca0725dfa1,4731e56fbb1159579058734492d6890f5f119ff2..5199e5aa0cb726d0e19a0e46fa9c8a5e976550d0
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_GRCTX_NVC0_H__
   #define __NVKM_GRCTX_NVC0_H__
   #include "gf100.h"
@@@ -12,7 -11,7 +12,7 @@@ struct gf100_grctx 
         u64 addr;
   };
   
- int  gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, u32 access);
+ int  gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, bool priv);
   void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int);
   
   #define mmio_vram(a,b,c,d) gf100_grctx_mmio_data((a), (b), (c), (d))
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

index df2cd864147c9efc07ad561e4d10a72bbefcb107,d6840dc81a295a0872d6e02d46ca7d3f8abbab30..111c8bb4497bb857cd75ff8ecf87f5cbd890b367
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
@@@ -1,4 -1,3 +1,4 @@@
+ +// SPDX-License-Identifier: GPL-2.0
   #include "nv20.h"
   #include "regs.h"
   
@@@ -60,7 -59,7 +60,7 @@@ void 
   nv20_gr_chan_dtor(struct nvkm_object *object)
   {
         struct nv20_gr_chan *chan = nv20_gr_chan(object);
-       nvkm_memory_del(&chan->inst);
+       nvkm_memory_unref(&chan->inst);
         return chan;
   }
   
@@@ -324,7 -323,7 +324,7 @@@ void 
   nv20_gr_dtor(struct nvkm_gr *base)
   {
         struct nv20_gr *gr = nv20_gr(base);
-       nvkm_memory_del(&gr->ctxtab);
+       nvkm_memory_unref(&gr->ctxtab);
         return gr;
   }
   
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h

index ad7e53bb7c235dec94b4168a4367f4e495cf0077,d0cb2b8846ec6822967c525a39368592a0356864..979dc5f7b32ecadeff6e6199d44b9f8e801e067e
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV20_GR_H__
   #define __NV20_GR_H__
   #define nv20_gr(p) container_of((p), struct nv20_gr, base)
@@@ -20,6 -19,7 +20,7 @@@ void nv20_gr_tile(struct nvkm_gr *, int
   int nv30_gr_init(struct nvkm_gr *);
   
   #define nv20_gr_chan(p) container_of((p), struct nv20_gr_chan, object)
+ #include <core/object.h>
   
   struct nv20_gr_chan {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h

index 89b773233ac5f76ef363dc5a4568e6833c17658b,bee8ef2d5697412c587b0b59044ac7b66eb8f7e6..731400937edd237dc87a886bcd8f3eea04e21ee6
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV40_GR_H__
   #define __NV40_GR_H__
   #define nv40_gr(p) container_of((p), struct nv40_gr, base)
@@@ -17,6 -16,7 +17,7 @@@ void nv40_gr_intr(struct nvkm_gr *)
   u64 nv40_gr_units(struct nvkm_gr *);
   
   #define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object)
+ #include <core/object.h>
   
   struct nv40_gr_chan {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h

index 567fa4f3e5182aebd1a3746cd834c0c021ebcb9b,1ab6ea436b703188ebebccad6cf96c2c8da8dd29..5b9d99bee20780c243839831e05eddf7599a6aaf
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV50_GR_H__
   #define __NV50_GR_H__
   #define nv50_gr(p) container_of((p), struct nv50_gr, base)
@@@ -20,6 -19,7 +20,7 @@@ u64 nv50_gr_units(struct nvkm_gr *)
   int g84_gr_tlb_flush(struct nvkm_gr *);
   
   #define nv50_gr_chan(p) container_of((p), struct nv50_gr_chan, object)
+ #include <core/object.h>
   
   struct nv50_gr_chan {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h

index 1ac2b4558bec4bc5bcb197c35feeb8d9bd9719f3,f0d35beb58df2e0b0df972cc387396d4cea0711f..b31fad8bdaadafcf764c5d7fa723a4874d8d6218
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV31_MPEG_H__
   #define __NV31_MPEG_H__
   #define nv31_mpeg(p) container_of((p), struct nv31_mpeg, engine)
@@@ -19,6 -18,7 +19,7 @@@ struct nv31_mpeg_func 
   };
   
   #define nv31_mpeg_chan(p) container_of((p), struct nv31_mpeg_chan, object)
+ #include <core/object.h>
   
   struct nv31_mpeg_chan {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h

index 17240d54b1ebd13c8ad2e0cd9d308a82f08f3d30,4ff0475e776c6fa76ae08aa163744be0f72b887c..9fad3611a843bb4d865209e3f237d4b0647e9b21
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_PM_PRIV_H__
   #define __NVKM_PM_PRIV_H__
   #define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
@@@ -68,6 -67,7 +68,7 @@@ struct nvkm_specdom 
   };
   
   #define nvkm_perfdom(p) container_of((p), struct nvkm_perfdom, object)
+ #include <core/object.h>
   
   struct nvkm_perfdom {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h

index b1fa69314e4a9472059fa197ec3aefa7d2ba22ac,b5be49f0ac5625199f60fd6c0b235f082c114eaa..d42862fc43fda5519b4d30fb7073b349493d2603
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h
@@@ -1,10 -1,11 +1,12 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_SW_CHAN_H__
   #define __NVKM_SW_CHAN_H__
   #define nvkm_sw_chan(p) container_of((p), struct nvkm_sw_chan, object)
- #include "priv.h"
+ #include <core/object.h>
   #include <core/event.h>
   
+ #include "priv.h"
+ 
   struct nvkm_sw_chan {
         const struct nvkm_sw_chan_func *func;
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h

index 7050a9e49db120a1ed666cc0270f28702c43f1a5,bcfff62131fe377aced0d48cdf2ab4e8ec26ae0d..d7034950ba87ed1bd2b1aa4e1d93a4c803e2d19f
--- 1/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h
--- 2/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h
@@@ -1,8 -1,7 +1,8 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_NVSW_H__
   #define __NVKM_NVSW_H__
   #define nvkm_nvsw(p) container_of((p), struct nvkm_nvsw, object)
- #include "priv.h"
+ #include <core/object.h>
   
   struct nvkm_nvsw {
         struct nvkm_object object;
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h

index 9accd7923788f6a61d194ecf73fcf9cb2d4777a6,e4da39139e959a182b27480adc8f8de1ead29581..4f2b66e8d7950d94c27f6b928b3a3aa43f5869b6
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
@@@ -1,25 -1,26 +1,27 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __GF100_BAR_H__
   #define __GF100_BAR_H__
   #define gf100_bar(p) container_of((p), struct gf100_bar, base)
   #include "priv.h"
   
- struct gf100_bar_vm {
-       struct nvkm_memory *mem;
-       struct nvkm_gpuobj *pgd;
-       struct nvkm_vm *vm;
+ struct gf100_barN {
+       struct nvkm_memory *inst;
+       struct nvkm_vmm *vmm;
   };
   
   struct gf100_bar {
         struct nvkm_bar base;
         bool bar2_halve;
-       struct gf100_bar_vm bar[2];
+       struct gf100_barN bar[2];
   };
   
   int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *,
                    int, struct nvkm_bar **);
   void *gf100_bar_dtor(struct nvkm_bar *);
   int gf100_bar_oneinit(struct nvkm_bar *);
- int gf100_bar_init(struct nvkm_bar *);
- int gf100_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
+ void gf100_bar_bar1_init(struct nvkm_bar *);
+ void gf100_bar_bar1_wait(struct nvkm_bar *);
+ struct nvkm_vmm *gf100_bar_bar1_vmm(struct nvkm_bar *);
+ void gf100_bar_bar2_init(struct nvkm_bar *);
+ struct nvkm_vmm *gf100_bar_bar2_vmm(struct nvkm_bar *);
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h

index ce9ab9110b08b3124fd9fa18da0a14122f18392a,140b76f588b6ad0cabfe043e9cf28dcaa1bd8f26..2fe833f6d9f79d5f5be931b52cc13847b8b936b9
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV50_BAR_H__
   #define __NV50_BAR_H__
   #define nv50_bar(p) container_of((p), struct nv50_bar, base)
@@@ -10,18 -9,20 +10,20 @@@ struct nv50_bar 
         struct nvkm_gpuobj *mem;
         struct nvkm_gpuobj *pad;
         struct nvkm_gpuobj *pgd;
-       struct nvkm_vm *bar1_vm;
+       struct nvkm_vmm *bar1_vmm;
         struct nvkm_gpuobj *bar1;
-       struct nvkm_vm *bar3_vm;
-       struct nvkm_gpuobj *bar3;
+       struct nvkm_vmm *bar2_vmm;
+       struct nvkm_gpuobj *bar2;
   };
   
   int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *,
                   int, u32 pgd_addr, struct nvkm_bar **);
   void *nv50_bar_dtor(struct nvkm_bar *);
   int nv50_bar_oneinit(struct nvkm_bar *);
- int nv50_bar_init(struct nvkm_bar *);
- struct nvkm_vm *nv50_bar_kmap(struct nvkm_bar *);
- int nv50_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
- void nv50_bar_unmap(struct nvkm_bar *, struct nvkm_vma *);
+ void nv50_bar_init(struct nvkm_bar *);
+ void nv50_bar_bar1_init(struct nvkm_bar *);
+ void nv50_bar_bar1_wait(struct nvkm_bar *);
+ struct nvkm_vmm *nv50_bar_bar1_vmm(struct nvkm_bar *);
+ void nv50_bar_bar2_init(struct nvkm_bar *);
+ struct nvkm_vmm *nv50_bar_bar2_vmm(struct nvkm_bar *);
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h

index 63d111c8afd4697ffd05e527c622f1cb493c0c16,14398e2dbdf991a4aed458681ab366d4b67717e1..01ba5b26666e839f8fb411b601419602cb8c45cc
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_BAR_PRIV_H__
   #define __NVKM_BAR_PRIV_H__
   #define nvkm_bar(p) container_of((p), struct nvkm_bar, subdev)
@@@ -10,11 -9,25 +10,25 @@@ void nvkm_bar_ctor(const struct nvkm_ba
   struct nvkm_bar_func {
         void *(*dtor)(struct nvkm_bar *);
         int (*oneinit)(struct nvkm_bar *);
-       int (*init)(struct nvkm_bar *);
-       struct nvkm_vm *(*kmap)(struct nvkm_bar *);
-       int  (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
+       void (*init)(struct nvkm_bar *);
+ 
+       struct {
+               void (*init)(struct nvkm_bar *);
+               void (*fini)(struct nvkm_bar *);
+               void (*wait)(struct nvkm_bar *);
+               struct nvkm_vmm *(*vmm)(struct nvkm_bar *);
+       } bar1, bar2;
+ 
         void (*flush)(struct nvkm_bar *);
   };
   
+ void nv50_bar_bar1_fini(struct nvkm_bar *);
+ void nv50_bar_bar2_fini(struct nvkm_bar *);
+ 
   void g84_bar_flush(struct nvkm_bar *);
+ 
+ void gf100_bar_bar1_fini(struct nvkm_bar *);
+ void gf100_bar_bar2_fini(struct nvkm_bar *);
+ 
+ void gm107_bar_bar1_wait(struct nvkm_bar *);
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h

index 1756f7b02858a1dd59762d2a177e241061679d91,e3cf0515bb70a09493cc2a298e92506f324497ce..ab261310753a6f0d8d9eea057e77ff99afa96c32
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_RAM_NVC0_H__
   #define __NVKM_RAM_NVC0_H__
   #define gf100_fb(p) container_of((p), struct gf100_fb, base)
@@@ -18,7 -17,5 +18,5 @@@ void gf100_fb_intr(struct nvkm_fb *)
   
   void gp100_fb_init(struct nvkm_fb *);
   
- void gm200_fb_init_page(struct nvkm_fb *fb);
   void gm200_fb_init(struct nvkm_fb *base);
- 
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h

index a37758c76268f2e8232cabafaa53abc74d88a42b,13231d4b00d932234f4ee8067c36e556230fc2b1..dacc696387b62b44e7e208c2bdedba93bf16c4c6
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_FB_NV50_H__
   #define __NVKM_FB_NV50_H__
   #define nv50_fb(p) container_of((p), struct nv50_fb, base)
@@@ -13,10 -12,10 +13,10 @@@ struct nv50_fb 
   
   struct nv50_fb_func {
         int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **);
+       u32 (*tags)(struct nvkm_fb *);
         u32 trap;
   };
   
   int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, int index,
                  struct nvkm_fb **pfb);
- extern int nv50_fb_memtype[0x80];
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h

index 8e87b887d4f5e4fd95b7e4355857bbfccd4e054b,e05d95240e853c903e49e411f0e29ef14b62b62f..9351188d5d764b6238af6f62825703fa51d4300e
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_FB_PRIV_H__
   #define __NVKM_FB_PRIV_H__
   #define nvkm_fb(p) container_of((p), struct nvkm_fb, subdev)
@@@ -7,9 -6,10 +7,10 @@@ struct nvkm_bios
   
   struct nvkm_fb_func {
         void *(*dtor)(struct nvkm_fb *);
+       u32 (*tags)(struct nvkm_fb *);
         int (*oneinit)(struct nvkm_fb *);
         void (*init)(struct nvkm_fb *);
-       void (*init_page)(struct nvkm_fb *);
+       int (*init_page)(struct nvkm_fb *);
         void (*init_unkn)(struct nvkm_fb *);
         void (*intr)(struct nvkm_fb *);
   
@@@ -25,7 -25,7 +26,7 @@@
   
         int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **);
   
-       bool (*memtype_valid)(struct nvkm_fb *, u32 memtype);
+       u8 default_bigpage;
   };
   
   void nvkm_fb_ctor(const struct nvkm_fb_func *, struct nvkm_device *device,
@@@ -34,13 -34,12 +35,12 @@@ int nvkm_fb_new_(const struct nvkm_fb_f
                  int index, struct nvkm_fb **);
   int nvkm_fb_bios_memtype(struct nvkm_bios *);
   
- bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
- 
   void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
                        u32 pitch, u32 flags, struct nvkm_fb_tile *);
   void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
   void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
   
+ u32 nv20_fb_tags(struct nvkm_fb *);
   void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
                        u32 pitch, u32 flags, struct nvkm_fb_tile *);
   void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
@@@ -63,8 -62,7 +63,7 @@@ void nv46_fb_tile_init(struct nvkm_fb *
                        u32 pitch, u32 flags, struct nvkm_fb_tile *);
   
   int gf100_fb_oneinit(struct nvkm_fb *);
- void gf100_fb_init_page(struct nvkm_fb *);
- bool gf100_fb_memtype_valid(struct nvkm_fb *, u32);
+ int gf100_fb_init_page(struct nvkm_fb *);
   
- void gm200_fb_init_page(struct nvkm_fb *);
+ int gm200_fb_init_page(struct nvkm_fb *);
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h

index b2122d261f8dc50195841e17d99d58beabe35df5,70fd59dcd06d6715fc565d94a330aceec308c501..330132e95b6f6505b10da5ab5182eef66f929acb
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
@@@ -1,14 -1,11 +1,12 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_FB_RAM_PRIV_H__
   #define __NVKM_FB_RAM_PRIV_H__
   #include "priv.h"
   
   int  nvkm_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *,
-                  enum nvkm_ram_type, u64 size, u32 tags,
-                  struct nvkm_ram *);
+                  enum nvkm_ram_type, u64 size, struct nvkm_ram *);
   int  nvkm_ram_new_(const struct nvkm_ram_func *, struct nvkm_fb *,
-                  enum nvkm_ram_type, u64 size, u32 tags,
-                  struct nvkm_ram **);
+                  enum nvkm_ram_type, u64 size, struct nvkm_ram **);
   void nvkm_ram_del(struct nvkm_ram **);
   int  nvkm_ram_init(struct nvkm_ram *);
   
@@@ -16,9 -13,6 +14,6 @@@ extern const struct nvkm_ram_func nv04_
   
   int  nv50_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *,
                    struct nvkm_ram *);
- int  nv50_ram_get(struct nvkm_ram *, u64, u32, u32, u32, struct nvkm_mem **);
- void nv50_ram_put(struct nvkm_ram *, struct nvkm_mem **);
- void __nv50_ram_put(struct nvkm_ram *, struct nvkm_mem *);
   
   int gf100_ram_new_(const struct nvkm_ram_func *, struct nvkm_fb *,
                    struct nvkm_ram **);
@@@ -29,8 -23,6 +24,6 @@@ u32  gf100_ram_probe_fbp(const struct n
   u32  gf100_ram_probe_fbp_amount(const struct nvkm_ram_func *, u32,
                                 struct nvkm_device *, int, int *);
   u32  gf100_ram_probe_fbpa_amount(struct nvkm_device *, int);
- int  gf100_ram_get(struct nvkm_ram *, u64, u32, u32, u32, struct nvkm_mem **);
- void gf100_ram_put(struct nvkm_ram *, struct nvkm_mem **);
   int gf100_ram_init(struct nvkm_ram *);
   int gf100_ram_calc(struct nvkm_ram *, u32);
   int gf100_ram_prog(struct nvkm_ram *);
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h

index 8549fdf2437cc61f8cd277f63b6e55c4908f6b81,ec5dcbfcaea8f0b57cf83b0d33943269054f1c7e..11f6bb2936b99813c2860c74483f7d3f832e3e34
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NV40_FB_RAM_H__
   #define __NV40_FB_RAM_H__
   #define nv40_ram(p) container_of((p), struct nv40_ram, base)
@@@ -10,6 -9,6 +10,6 @@@ struct nv40_ram 
         u32 coef;
   };
   
- int nv40_ram_new_(struct nvkm_fb *fb, enum nvkm_ram_type, u64, u32,
+ int nv40_ram_new_(struct nvkm_fb *fb, enum nvkm_ram_type, u64,
                   struct nvkm_ram **);
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h

index 021e7a1f39a105c5e88be7dd32febaea9f4072bb,44651ca42d5297761557c99a813589ada6580814..b9e4751b9921018940187fcf410bf5a13fd0ccfe
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_INSTMEM_PRIV_H__
   #define __NVKM_INSTMEM_PRIV_H__
   #define nvkm_instmem(p) container_of((p), struct nvkm_instmem, subdev)
@@@ -12,10 -11,22 +12,22 @@@ struct nvkm_instmem_func 
         void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data);
         int (*memory_new)(struct nvkm_instmem *, u32 size, u32 align,
                           bool zero, struct nvkm_memory **);
-       bool persistent;
         bool zero;
   };
   
   void nvkm_instmem_ctor(const struct nvkm_instmem_func *, struct nvkm_device *,
                        int index, struct nvkm_instmem *);
+ void nvkm_instmem_boot(struct nvkm_instmem *);
+ 
+ #include <core/memory.h>
+ 
+ struct nvkm_instobj {
+       struct nvkm_memory memory;
+       struct list_head head;
+       u32 *suspend;
+ };
+ 
+ void nvkm_instobj_ctor(const struct nvkm_memory_func *func,
+                      struct nvkm_instmem *, struct nvkm_instobj *);
+ void nvkm_instobj_dtor(struct nvkm_instmem *, struct nvkm_instobj *);
   #endif
diff --combined drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h

index bf37f313b5bb8795c6680b13b81d4ef9854deb58,d024d8055fcb175af5e55451e289f6c556f545d7..948a48c21be47089185883af387c6a150b621106
--- 1/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h
--- 2/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __NVKM_MMU_PRIV_H__
   #define __NVKM_MMU_PRIV_H__
   #define nvkm_mmu(p) container_of((p), struct nvkm_mmu, subdev)
@@@ -10,31 -9,57 +10,57 @@@ int nvkm_mmu_new_(const struct nvkm_mmu
                   int index, struct nvkm_mmu **);
   
   struct nvkm_mmu_func {
-       void *(*dtor)(struct nvkm_mmu *);
-       int (*oneinit)(struct nvkm_mmu *);
         void (*init)(struct nvkm_mmu *);
   
-       u64 limit;
         u8  dma_bits;
-       u32 pgt_bits;
-       u8  spg_shift;
-       u8  lpg_shift;
- 
-       int  (*create)(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
-                      struct lock_class_key *, struct nvkm_vm **);
- 
-       void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
-                       struct nvkm_memory *pgt[2]);
-       void (*map)(struct nvkm_vma *, struct nvkm_memory *,
-                   struct nvkm_mem *, u32 pte, u32 cnt,
-                   u64 phys, u64 delta);
-       void (*map_sg)(struct nvkm_vma *, struct nvkm_memory *,
-                      struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
-       void (*unmap)(struct nvkm_vma *, struct nvkm_memory *pgt,
-                     u32 pte, u32 cnt);
-       void (*flush)(struct nvkm_vm *);
+ 
+       struct {
+               struct nvkm_sclass user;
+       } mmu;
+ 
+       struct {
+               struct nvkm_sclass user;
+               int (*vram)(struct nvkm_mmu *, int type, u8 page, u64 size,
+                           void *argv, u32 argc, struct nvkm_memory **);
+               int (*umap)(struct nvkm_mmu *, struct nvkm_memory *, void *argv,
+                           u32 argc, u64 *addr, u64 *size, struct nvkm_vma **);
+       } mem;
+ 
+       struct {
+               struct nvkm_sclass user;
+               int (*ctor)(struct nvkm_mmu *, u64 addr, u64 size,
+                           void *argv, u32 argc, struct lock_class_key *,
+                           const char *name, struct nvkm_vmm **);
+               bool global;
+               u32 pd_offset;
+       } vmm;
+ 
+       const u8 *(*kind)(struct nvkm_mmu *, int *count);
+       bool kind_sys;
+ };
+ 
+ extern const struct nvkm_mmu_func nv04_mmu;
+ 
+ const u8 *nv50_mmu_kind(struct nvkm_mmu *, int *count);
+ 
+ const u8 *gf100_mmu_kind(struct nvkm_mmu *, int *count);
+ 
+ const u8 *gm200_mmu_kind(struct nvkm_mmu *, int *);
+ 
+ struct nvkm_mmu_pt {
+       union {
+               struct nvkm_mmu_ptc *ptc;
+               struct nvkm_mmu_ptp *ptp;
+       };
+       struct nvkm_memory *memory;
+       bool sub;
+       u16 base;
+       u64 addr;
+       struct list_head head;
   };
   
- int nvkm_vm_create(struct nvkm_mmu *, u64, u64, u64, u32,
-                  struct lock_class_key *, struct nvkm_vm **);
+ void nvkm_mmu_ptc_dump(struct nvkm_mmu *);
+ struct nvkm_mmu_pt *
+ nvkm_mmu_ptc_get(struct nvkm_mmu *, u32 size, u32 align, bool zero);
+ void nvkm_mmu_ptc_put(struct nvkm_mmu *, bool force, struct nvkm_mmu_pt **);
   #endif
diff --combined drivers/gpu/drm/omapdrm/dss/Makefile

index 62d5b4f45420b5e9490b40109ef0aca5ae7bf237,3c5644c3fc3877e3c7d4d38ab78f566d11e660b7..904101c5e79d42f2d367cf1dcd1c58692def73e6
--- 1/drivers/gpu/drm/omapdrm/dss/Makefile
--- 2/drivers/gpu/drm/omapdrm/dss/Makefile
+++ b/drivers/gpu/drm/omapdrm/dss/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   obj-$(CONFIG_OMAP2_DSS_INIT) += omapdss-boot-init.o
   
   obj-$(CONFIG_OMAP_DSS_BASE) += omapdss-base.o
@@@ -15,5 -14,6 +15,6 @@@ omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.
   omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \
         hdmi_phy.o
   omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o
+ omapdss-$(CONFIG_OMAP4_DSS_HDMI_CEC) += hdmi4_cec.o
   omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o
   ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
diff --combined drivers/gpu/drm/panel/Makefile

index d73d3e661cec5e6943296292166d93663bf53c75,77ede3467324301b6fddf29a41cda7addca96626..2c4e1a93e05fbd7045cdbb700dfe65e990400c4e
--- 1/drivers/gpu/drm/panel/Makefile
--- 2/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@@ -1,13 -1,16 +1,17 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
   obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
   obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
   obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
   obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
+ obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o
   obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o
+ obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o
   obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
   obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
+ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
   obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o
+ obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
   obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
   obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
   obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
diff --combined drivers/gpu/drm/pl111/Makefile

index f2874bbdaa140bdfbd70f8f87508e5ee615024e0,fce1453a93e19e42fb146c343179d50a17f1813d..9c5e8dba8ac68669c1b39a12876f9995df25a797
--- 1/drivers/gpu/drm/pl111/Makefile
--- 2/drivers/gpu/drm/pl111/Makefile
+++ b/drivers/gpu/drm/pl111/Makefile
@@@ -1,6 -1,5 +1,6 @@@
- pl111_drm-y +=        pl111_connector.o \
-               pl111_display.o \
+ +# SPDX-License-Identifier: GPL-2.0
+ pl111_drm-y +=        pl111_display.o \
+               pl111_versatile.o \
                 pl111_drv.o
   
   pl111_drm-$(CONFIG_DEBUG_FS) += pl111_debugfs.o
diff --combined drivers/gpu/drm/radeon/Makefile

index 0ad8244b5ccf4a38d30f629eea4aed8672f833a0,cf3e5985e3e7bb57e537ec354ea6e29910332f44..92ccd7aed0d44e3423657405a4ab07ce36617cf4
--- 1/drivers/gpu/drm/radeon/Makefile
--- 2/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   #
   # Makefile for the drm device driver.  This driver provides support for the
   # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
@@@ -103,12 -102,9 +103,9 @@@ radeon-y += 
   radeon-y += \
         radeon_vce.o \
         vce_v1_0.o \
-       vce_v2_0.o \
-       radeon_kfd.o
+       vce_v2_0.o
   
   radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
   radeon-$(CONFIG_ACPI) += radeon_acpi.o
   
   obj-$(CONFIG_DRM_RADEON)+= radeon.o
- 
- CFLAGS_radeon_trace_points.o := -I$(src)
diff --combined drivers/gpu/drm/radeon/radeon_trace.h

index db8f079e441eb54e4a54826526da9dcc7c2551da,815eaa8c394bb084df55a8f8888fba1e994694a9..bc26efd1793e21066ce14360fee4a467011b8a6c
--- 1/drivers/gpu/drm/radeon/radeon_trace.h
--- 2/drivers/gpu/drm/radeon/radeon_trace.h
+++ b/drivers/gpu/drm/radeon/radeon_trace.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #if !defined(_RADEON_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
   #define _RADEON_TRACE_H_
   
@@@ -205,5 -204,5 +205,5 @@@ DEFINE_EVENT(radeon_semaphore_request, 
   
   /* This part must be outside protection */
   #undef TRACE_INCLUDE_PATH
- #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/radeon
   #include <trace/define_trace.h>
diff --combined drivers/gpu/drm/radeon/radeon_ttm.c

index 1fdfc7a46072aa221419b7c61084e39ee017ff61,8032da57e40905b522ebd89acaa2054706ead5a5..6ada64db00e9c5b8208f6f83e1e35d80e429b253
--- 1/drivers/gpu/drm/radeon/radeon_ttm.c
--- 2/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@@ -597,7 -597,7 +597,7 @@@ release_sg
         kfree(ttm->sg);
   
   release_pages:
- -      release_pages(ttm->pages, pinned, 0);
+ +      release_pages(ttm->pages, pinned);
         return r;
   }
   
@@@ -725,8 -725,6 +725,6 @@@ static int radeon_ttm_tt_populate(struc
   {
         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
         struct radeon_device *rdev;
-       unsigned i;
-       int r;
         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
   
         if (ttm->state != tt_unpopulated)
@@@ -762,33 -760,13 +760,13 @@@
         }
   #endif
   
-       r = ttm_pool_populate(ttm);
-       if (r) {
-               return r;
-       }
- 
-       for (i = 0; i < ttm->num_pages; i++) {
-               gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
-                                                      0, PAGE_SIZE,
-                                                      PCI_DMA_BIDIRECTIONAL);
-               if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
-                       while (i--) {
-                               pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
-                                              PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-                               gtt->ttm.dma_address[i] = 0;
-                       }
-                       ttm_pool_unpopulate(ttm);
-                       return -EFAULT;
-               }
-       }
-       return 0;
+       return ttm_populate_and_map_pages(rdev->dev, &gtt->ttm);
   }
   
   static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
   {
         struct radeon_device *rdev;
         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
-       unsigned i;
         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
   
         if (gtt && gtt->userptr) {
@@@ -815,14 -793,7 +793,7 @@@
         }
   #endif
   
-       for (i = 0; i < ttm->num_pages; i++) {
-               if (gtt->ttm.dma_address[i]) {
-                       pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
-                                      PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-               }
-       }
- 
-       ttm_pool_unpopulate(ttm);
+       ttm_unmap_and_unpopulate_pages(rdev->dev, &gtt->ttm);
   }
   
   int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
diff --combined drivers/gpu/drm/rockchip/Makefile

index 305409818ffbf07b28792f3edc3336bbbcf500e8,a881d2cc4f25046b0c680bfad889af6d2562c779..a314e2109e76ce532b901886579e6f63a9c55b63
--- 1/drivers/gpu/drm/rockchip/Makefile
--- 2/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   #
   # Makefile for the drm device driver.  This driver provides support for the
   # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
@@@ -13,5 -12,6 +13,6 @@@ rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) +
   rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
   rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
   rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
   
   obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o
diff --combined drivers/gpu/drm/sun4i/Makefile

index 55b32368f8fb4c7a5424d53711aafe14851b4cf1,301b5b1452db2274638ede942e21a86f55872fbd..0c2f8c7facae707883beccdf8237db0176d9c66f
--- 1/drivers/gpu/drm/sun4i/Makefile
--- 2/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@@ -1,25 -1,25 +1,26 @@@
- sun4i-drm-y += sun4i_drv.o
- sun4i-drm-y += sun4i_framebuffer.o
+ +# SPDX-License-Identifier: GPL-2.0
+ sun4i-backend-y                       += sun4i_backend.o sun4i_layer.o
   
- sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
- sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o
- sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
- sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
+ sun4i-drm-y                   += sun4i_drv.o
+ sun4i-drm-y                   += sun4i_framebuffer.o
   
- sun4i-tcon-y += sun4i_tcon.o
- sun4i-tcon-y += sun4i_rgb.o
- sun4i-tcon-y += sun4i_dotclock.o
- sun4i-tcon-y += sun4i_crtc.o
+ sun4i-drm-hdmi-y              += sun4i_hdmi_ddc_clk.o
+ sun4i-drm-hdmi-y              += sun4i_hdmi_enc.o
+ sun4i-drm-hdmi-y              += sun4i_hdmi_i2c.o
+ sun4i-drm-hdmi-y              += sun4i_hdmi_tmds_clk.o
   
- sun4i-backend-y += sun4i_backend.o sun4i_layer.o
+ sun8i-mixer-y                 += sun8i_mixer.o sun8i_layer.o
   
- sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
+ sun4i-tcon-y                  += sun4i_crtc.o
+ sun4i-tcon-y                  += sun4i_dotclock.o
+ sun4i-tcon-y                  += sun4i_tcon.o
+ sun4i-tcon-y                  += sun4i_rgb.o
   
- obj-$(CONFIG_DRM_SUN4I)               += sun4i-drm.o sun4i-tcon.o
- obj-$(CONFIG_DRM_SUN4I)               += sun6i_drc.o
+ obj-$(CONFIG_DRM_SUN4I)               += sun4i-drm.o
+ obj-$(CONFIG_DRM_SUN4I)               += sun4i-tcon.o
   obj-$(CONFIG_DRM_SUN4I)               += sun4i_tv.o
+ obj-$(CONFIG_DRM_SUN4I)               += sun6i_drc.o
   
- obj-$(CONFIG_DRM_SUN4I_BACKEND)               += sun4i-backend.o
+ obj-$(CONFIG_DRM_SUN4I_BACKEND)       += sun4i-backend.o
   obj-$(CONFIG_DRM_SUN4I_HDMI)  += sun4i-drm-hdmi.o
- obj-$(CONFIG_DRM_SUN8I_MIXER)         += sun8i-mixer.o
+ obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o
diff --combined drivers/gpu/drm/tegra/drm.c

index b822e484b7e55a0b3207cb4829d928cc30b78978,943bdf88c4a267214db5f01bda0216be2fb4d5c7..52552b9b89ef713b345fa31abac4d735c26f1d06
--- 1/drivers/gpu/drm/tegra/drm.c
--- 2/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@@ -155,7 -155,8 +155,7 @@@ static int tegra_drm_load(struct drm_de
   
                 order = __ffs(tegra->domain->pgsize_bitmap);
                 init_iova_domain(&tegra->carveout.domain, 1UL << order,
- -                               carveout_start >> order,
- -                               carveout_end >> order);
+ +                               carveout_start >> order);
   
                 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
                 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
@@@ -385,12 -386,10 +385,10 @@@ int tegra_drm_submit(struct tegra_drm_c
         unsigned int num_cmdbufs = args->num_cmdbufs;
         unsigned int num_relocs = args->num_relocs;
         unsigned int num_waitchks = args->num_waitchks;
-       struct drm_tegra_cmdbuf __user *cmdbufs =
-               (void __user *)(uintptr_t)args->cmdbufs;
-       struct drm_tegra_reloc __user *relocs =
-               (void __user *)(uintptr_t)args->relocs;
-       struct drm_tegra_waitchk __user *waitchks =
-               (void __user *)(uintptr_t)args->waitchks;
+       struct drm_tegra_cmdbuf __user *user_cmdbufs;
+       struct drm_tegra_reloc __user *user_relocs;
+       struct drm_tegra_waitchk __user *user_waitchks;
+       struct drm_tegra_syncpt __user *user_syncpt;
         struct drm_tegra_syncpt syncpt;
         struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
         struct drm_gem_object **refs;
@@@ -399,6 -398,11 +397,11 @@@
         unsigned int num_refs;
         int err;
   
+       user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
+       user_relocs = u64_to_user_ptr(args->relocs);
+       user_waitchks = u64_to_user_ptr(args->waitchks);
+       user_syncpt = u64_to_user_ptr(args->syncpts);
+ 
         /* We don't yet support other than one syncpt_incr struct per submit */
         if (args->num_syncpts != 1)
                 return -EINVAL;
@@@ -439,7 -443,7 +442,7 @@@
                 struct tegra_bo *obj;
                 u64 offset;
   
-               if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
+               if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
                         err = -EFAULT;
                         goto fail;
                 }
@@@ -475,7 -479,7 +478,7 @@@
   
                 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
                 num_cmdbufs--;
-               cmdbufs++;
+               user_cmdbufs++;
         }
   
         /* copy and resolve relocations from submit */
@@@ -484,7 -488,7 +487,7 @@@
                 struct tegra_bo *obj;
   
                 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
-                                                 &relocs[num_relocs], drm,
+                                                 &user_relocs[num_relocs], drm,
                                                   file);
                 if (err < 0)
                         goto fail;
@@@ -518,9 -522,8 +521,8 @@@
                 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
                 struct tegra_bo *obj;
   
-               err = host1x_waitchk_copy_from_user(wait,
-                                                   &waitchks[num_waitchks],
-                                                   file);
+               err = host1x_waitchk_copy_from_user(
+                       wait, &user_waitchks[num_waitchks], file);
                 if (err < 0)
                         goto fail;
   
@@@ -538,8 -541,7 +540,7 @@@
                 }
         }
   
-       if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
-                          sizeof(syncpt))) {
+       if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
                 err = -EFAULT;
                 goto fail;
         }
@@@ -1316,6 -1318,7 +1317,7 @@@ static const struct of_device_id host1x
         { .compatible = "nvidia,tegra210-sor", },
         { .compatible = "nvidia,tegra210-sor1", },
         { .compatible = "nvidia,tegra210-vic", },
+       { .compatible = "nvidia,tegra186-vic", },
         { /* sentinel */ }
   };
   
diff --combined drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c

index 54025af534d4ffb7c821006b5facbc302a29c28b,482299a6f3b04df664990b29cba6bcb47cce5ba9..d2b9e5f047242d12bc8c191efe0088d937ad203f
--- 1/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
--- 2/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
@@@ -145,6 -145,7 +145,6 @@@ static struct device_node * __init tilc
                 __dtb_tilcdc_slave_compat_begin;
         static void *overlay_data;
         struct device_node *overlay;
- -      int ret;
   
         if (!size) {
                 pr_warn("%s: No overlay data\n", __func__);
@@@ -162,8 -163,12 +162,6 @@@
                 return NULL;
         }
   
-       of_node_set_flag(overlay, OF_DETACHED);
- -      ret = of_resolve_phandles(overlay);
- -      if (ret) {
- -              pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret);
- -              return NULL;
- -      }
--
         return overlay;
   }
   
@@@ -198,7 -203,7 +196,7 @@@ static void __init tilcdc_convert_slave
         /* For all memory needed for the overlay tree. This memory can
            be freed after the overlay has been applied. */
         struct kfree_table kft;
- -      int ret;
+ +      int ovcs_id, ret;
   
         if (kfree_table_init(&kft))
                 return;
@@@ -241,11 -246,9 +239,11 @@@
   
         tilcdc_node_disable(slave);
   
- -      ret = of_overlay_create(overlay);
+ +      ovcs_id = 0;
+ +      ret = of_overlay_apply(overlay, &ovcs_id);
         if (ret)
- -              pr_err("%s: Creating overlay failed: %d\n", __func__, ret);
+ +              pr_err("%s: Applying overlay changeset failed: %d\n",
+ +                      __func__, ret);
         else
                 pr_info("%s: ti,tilcdc,slave node successfully converted\n",
                         __func__);
diff --combined drivers/gpu/drm/vc4/Makefile

index 837c82757339259bd168a01e22c2cbec7543ce83,719a771f3d5c615398012b3b188387693cb9f031..f5500df51686f0fed9e8f9f7ff5cfa888cfdad7c
--- 1/drivers/gpu/drm/vc4/Makefile
--- 2/drivers/gpu/drm/vc4/Makefile
+++ b/drivers/gpu/drm/vc4/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   # Please keep these build lists sorted!
   
   # core driver code
@@@ -25,5 -24,3 +25,3 @@@ vc4-y := 
   vc4-$(CONFIG_DEBUG_FS) += vc4_debugfs.o
   
   obj-$(CONFIG_DRM_VC4)  += vc4.o
- 
- CFLAGS_vc4_trace_points.o := -I$(src)
diff --combined drivers/gpu/host1x/Makefile

index c0b80244158d72a9465bc83cd8477e98f6c2099c,4fb61bd57aeeea34b662e04fcbc1d0b7a4226959..b92016ce09b77c442d8e19f7bedba305456fe187
--- 1/drivers/gpu/host1x/Makefile
--- 2/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@@ -1,4 -1,3 +1,4 @@@
+ +# SPDX-License-Identifier: GPL-2.0
   host1x-y = \
         bus.o \
         syncpt.o \
@@@ -12,6 -11,7 +12,7 @@@
         hw/host1x01.o \
         hw/host1x02.o \
         hw/host1x04.o \
-       hw/host1x05.o
+       hw/host1x05.o \
+       hw/host1x06.o
   
   obj-$(CONFIG_TEGRA_HOST1X) += host1x.o
diff --combined drivers/gpu/host1x/bus.c

index ed03b3243195bbacea19c283fba166018acae049,66ea5acee820fa637883e635cef698804c800dc9..2e57c9cea696e317ae67a5ee9a7eb2b512fb2cf7
--- 1/drivers/gpu/host1x/bus.c
--- 2/drivers/gpu/host1x/bus.c
+++ b/drivers/gpu/host1x/bus.c
@@@ -320,7 -320,6 +320,7 @@@ struct bus_type host1x_bus_type = 
         .name = "host1x",
         .match = host1x_device_match,
         .pm = &host1x_device_pm_ops,
+ +      .force_dma = true,
   };
   
   static void __host1x_device_del(struct host1x_device *device)
@@@ -404,12 -403,13 +404,13 @@@ static int host1x_device_add(struct hos
         device->dev.coherent_dma_mask = host1x->dev->coherent_dma_mask;
         device->dev.dma_mask = &device->dev.coherent_dma_mask;
         dev_set_name(&device->dev, "%s", driver->driver.name);
-       of_dma_configure(&device->dev, host1x->dev->of_node);
         device->dev.release = host1x_device_release;
         device->dev.of_node = host1x->dev->of_node;
         device->dev.bus = &host1x_bus_type;
         device->dev.parent = host1x->dev;
   
+       of_dma_configure(&device->dev, host1x->dev->of_node);
+ 
         err = host1x_device_parse_dt(device, driver);
         if (err < 0) {
                 kfree(device);
diff --combined drivers/gpu/host1x/dev.c

index 5267c62e88962bd31addc6b0493c535facce9558,773d6337aa300eb2b4dffbf8eaf646623f30c958..bf67c3aeb6342e0554d5e568365f2272bf35ef73
--- 1/drivers/gpu/host1x/dev.c
--- 2/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@@ -39,6 -39,17 +39,17 @@@
   #include "hw/host1x02.h"
   #include "hw/host1x04.h"
   #include "hw/host1x05.h"
+ #include "hw/host1x06.h"
+ 
+ void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
+ {
+       writel(v, host1x->hv_regs + r);
+ }
+ 
+ u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
+ {
+       return readl(host1x->hv_regs + r);
+ }
   
   void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
   {
@@@ -104,7 -115,19 +115,19 @@@ static const struct host1x_info host1x0
         .dma_mask = DMA_BIT_MASK(34),
   };
   
+ static const struct host1x_info host1x06_info = {
+       .nb_channels = 63,
+       .nb_pts = 576,
+       .nb_mlocks = 24,
+       .nb_bases = 16,
+       .init = host1x06_init,
+       .sync_offset = 0x0,
+       .dma_mask = DMA_BIT_MASK(34),
+       .has_hypervisor = true,
+ };
+ 
   static const struct of_device_id host1x_of_match[] = {
+       { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
         { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
         { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
         { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
@@@ -116,20 -139,37 +139,37 @@@ MODULE_DEVICE_TABLE(of, host1x_of_match
   
   static int host1x_probe(struct platform_device *pdev)
   {
-       const struct of_device_id *id;
         struct host1x *host;
-       struct resource *regs;
+       struct resource *regs, *hv_regs = NULL;
         int syncpt_irq;
         int err;
   
-       id = of_match_device(host1x_of_match, &pdev->dev);
-       if (!id)
-               return -EINVAL;
+       host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
+       if (!host)
+               return -ENOMEM;
   
-       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       if (!regs) {
-               dev_err(&pdev->dev, "failed to get registers\n");
-               return -ENXIO;
+       host->info = of_device_get_match_data(&pdev->dev);
+ 
+       if (host->info->has_hypervisor) {
+               regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
+               if (!regs) {
+                       dev_err(&pdev->dev, "failed to get vm registers\n");
+                       return -ENXIO;
+               }
+ 
+               hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                                      "hypervisor");
+               if (!hv_regs) {
+                       dev_err(&pdev->dev,
+                               "failed to get hypervisor registers\n");
+                       return -ENXIO;
+               }
+       } else {
+               regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+               if (!regs) {
+                       dev_err(&pdev->dev, "failed to get registers\n");
+                       return -ENXIO;
+               }
         }
   
         syncpt_irq = platform_get_irq(pdev, 0);
@@@ -138,15 -178,10 +178,10 @@@
                 return syncpt_irq;
         }
   
-       host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
-       if (!host)
-               return -ENOMEM;
- 
         mutex_init(&host->devices_lock);
         INIT_LIST_HEAD(&host->devices);
         INIT_LIST_HEAD(&host->list);
         host->dev = &pdev->dev;
-       host->info = id->data;
   
         /* set common host1x device data */
         platform_set_drvdata(pdev, host);
@@@ -155,6 -190,12 +190,12 @@@
         if (IS_ERR(host->regs))
                 return PTR_ERR(host->regs);
   
+       if (host->info->has_hypervisor) {
+               host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
+               if (IS_ERR(host->hv_regs))
+                       return PTR_ERR(host->hv_regs);
+       }
+ 
         dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
   
         if (host->info->init) {
@@@ -198,7 -239,8 +239,7 @@@
   
                 order = __ffs(host->domain->pgsize_bitmap);
                 init_iova_domain(&host->iova, 1UL << order,
- -                               geometry->aperture_start >> order,
- -                               geometry->aperture_end >> order);
+ +                               geometry->aperture_start >> order);
                 host->iova_end = geometry->aperture_end;
         }
   
diff --combined drivers/staging/vboxvideo/vbox_mode.c

index 6f08dc966719365942e0168879f0b07cf2476c6e,c745a0402c6896e2d75b135bfdacfb45e0eaccbd..b265fe9245565666f20219a62720eeaa29a74743
--- 1/drivers/staging/vboxvideo/vbox_mode.c
--- 2/drivers/staging/vboxvideo/vbox_mode.c
+++ b/drivers/staging/vboxvideo/vbox_mode.c
@@@ -377,7 -377,7 +377,7 @@@ static struct drm_encoder *vbox_best_si
   
         /* pick the encoder ids */
         if (enc_id)
-               return drm_encoder_find(connector->dev, enc_id);
+               return drm_encoder_find(connector->dev, NULL, enc_id);
   
         return NULL;
   }
@@@ -553,22 -553,12 +553,22 @@@ static int vbox_get_modes(struct drm_co
                 ++num_modes;
         }
         vbox_set_edid(connector, preferred_width, preferred_height);
- -      drm_object_property_set_value(
- -              &connector->base, vbox->dev->mode_config.suggested_x_property,
- -              vbox_connector->vbox_crtc->x_hint);
- -      drm_object_property_set_value(
- -              &connector->base, vbox->dev->mode_config.suggested_y_property,
- -              vbox_connector->vbox_crtc->y_hint);
+ +
+ +      if (vbox_connector->vbox_crtc->x_hint != -1)
+ +              drm_object_property_set_value(&connector->base,
+ +                      vbox->dev->mode_config.suggested_x_property,
+ +                      vbox_connector->vbox_crtc->x_hint);
+ +      else
+ +              drm_object_property_set_value(&connector->base,
+ +                      vbox->dev->mode_config.suggested_x_property, 0);
+ +
+ +      if (vbox_connector->vbox_crtc->y_hint != -1)
+ +              drm_object_property_set_value(&connector->base,
+ +                      vbox->dev->mode_config.suggested_y_property,
+ +                      vbox_connector->vbox_crtc->y_hint);
+ +      else
+ +              drm_object_property_set_value(&connector->base,
+ +                      vbox->dev->mode_config.suggested_y_property, 0);
   
         return num_modes;
   }
@@@ -650,9 -640,9 +650,9 @@@ static int vbox_connector_init(struct d
   
         drm_mode_create_suggested_offset_properties(dev);
         drm_object_attach_property(&connector->base,
- -                                 dev->mode_config.suggested_x_property, -1);
+ +                                 dev->mode_config.suggested_x_property, 0);
         drm_object_attach_property(&connector->base,
- -                                 dev->mode_config.suggested_y_property, -1);
+ +                                 dev->mode_config.suggested_y_property, 0);
         drm_connector_register(connector);
   
         drm_mode_connector_attach_encoder(connector, encoder);
diff --combined include/drm/drm_fb_cma_helper.h

index 1df291d117101901f94239343d5a303d448e8447,023f052a58731c0bde79eedd5243bad1da57b2cb..faf56c53df284def80f3b96be854851bb10d11d8
--- 1/include/drm/drm_fb_cma_helper.h
--- 2/include/drm/drm_fb_cma_helper.h
+++ b/include/drm/drm_fb_cma_helper.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __DRM_FB_CMA_HELPER_H__
   #define __DRM_FB_CMA_HELPER_H__
   
@@@ -29,16 -28,6 +29,6 @@@ void drm_fbdev_cma_set_suspend(struct d
   void drm_fbdev_cma_set_suspend_unlocked(struct drm_fbdev_cma *fbdev_cma,
                                         bool state);
   
- void drm_fb_cma_destroy(struct drm_framebuffer *fb);
- int drm_fb_cma_create_handle(struct drm_framebuffer *fb,
-       struct drm_file *file_priv, unsigned int *handle);
- 
- struct drm_framebuffer *drm_fb_cma_create_with_funcs(struct drm_device *dev,
-       struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
-       const struct drm_framebuffer_funcs *funcs);
- struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
-       struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd);
- 
   struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
         unsigned int plane);
   
@@@ -46,9 -35,6 +36,6 @@@ dma_addr_t drm_fb_cma_get_gem_addr(stru
                                    struct drm_plane_state *state,
                                    unsigned int plane);
   
- int drm_fb_cma_prepare_fb(struct drm_plane *plane,
-                         struct drm_plane_state *state);
- 
   #ifdef CONFIG_DEBUG_FS
   struct seq_file;
   
diff --combined include/drm/drm_of.h

index 4f835490d77a761d11fd859afbf976595c7679ff,d20ec4e0431dd31544390e1a1441fc4b6f28a773..b93c239afb608e04f2d06149833488cd66db4d88
--- 1/include/drm/drm_of.h
--- 2/include/drm/drm_of.h
+++ b/include/drm/drm_of.h
@@@ -1,8 -1,10 +1,11 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __DRM_OF_H__
   #define __DRM_OF_H__
   
   #include <linux/of_graph.h>
+ #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_PANEL_BRIDGE)
+ #include <drm/drm_bridge.h>
+ #endif
   
   struct component_master_ops;
   struct component_match;
@@@ -68,6 -70,34 +71,34 @@@ static inline int drm_of_find_panel_or_
   }
   #endif
   
+ /*
+  * drm_of_panel_bridge_remove - remove panel bridge
+  * @np: device tree node containing panel bridge output ports
+  *
+  * Remove the panel bridge of a given DT node's port and endpoint number
+  *
+  * Returns zero if successful, or one of the standard error codes if it fails.
+  */
+ static inline int drm_of_panel_bridge_remove(const struct device_node *np,
+                                            int port, int endpoint)
+ {
+ #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_PANEL_BRIDGE)
+       struct drm_bridge *bridge;
+       struct device_node *remote;
+ 
+       remote = of_graph_get_remote_node(np, port, endpoint);
+       if (!remote)
+               return -ENODEV;
+ 
+       bridge = of_drm_find_bridge(remote);
+       drm_panel_bridge_remove(bridge);
+ 
+       return 0;
+ #else
+       return -EINVAL;
+ #endif
+ }
+ 
   static inline int drm_of_encoder_active_endpoint_id(struct device_node *node,
                                                     struct drm_encoder *encoder)
   {
diff --combined include/linux/scatterlist.h

index d87dfa41142d4d7770b6774b5f19681293862656,874b50c232de2acfc3646e76ee40258136faa698..b7c83254c566855d26f476ec9cd8a4d4fcb9c190
--- 1/include/linux/scatterlist.h
--- 2/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef _LINUX_SCATTERLIST_H
   #define _LINUX_SCATTERLIST_H
   
@@@ -21,6 -20,12 +21,12 @@@ struct scatterlist 
   #endif
   };
   
+ /*
+  * Since the above length field is an unsigned int, below we define the maximum
+  * length in bytes that can be stored in one scatterlist entry.
+  */
+ #define SCATTERLIST_MAX_SEGMENT (UINT_MAX & PAGE_MASK)
+ 
   /*
    * These macros should be used after a dma_map_sg call has been done
    * to get bus addresses of each of the SG entries and their lengths.
@@@ -262,10 -267,13 +268,13 @@@ void sg_free_table(struct sg_table *)
   int __sg_alloc_table(struct sg_table *, unsigned int, unsigned int,
                      struct scatterlist *, gfp_t, sg_alloc_fn *);
   int sg_alloc_table(struct sg_table *, unsigned int, gfp_t);
- int sg_alloc_table_from_pages(struct sg_table *sgt,
-       struct page **pages, unsigned int n_pages,
-       unsigned long offset, unsigned long size,
-       gfp_t gfp_mask);
+ int __sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
+                               unsigned int n_pages, unsigned int offset,
+                               unsigned long size, unsigned int max_segment,
+                               gfp_t gfp_mask);
+ int sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
+                             unsigned int n_pages, unsigned int offset,
+                             unsigned long size, gfp_t gfp_mask);
   
   size_t sg_copy_buffer(struct scatterlist *sgl, unsigned int nents, void *buf,
                       size_t buflen, off_t skip, bool to_buffer);
diff --combined include/linux/shmem_fs.h

index ed91ce57c428da1632c7696e8b75fb0bf88941c3,0937d9a7d8fbc96cc1573a369e91ad7ce54ebb41..06b295bec00dd8bd3310290d147c97a3166bc706
--- 1/include/linux/shmem_fs.h
--- 2/include/linux/shmem_fs.h
+++ b/include/linux/shmem_fs.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 */
   #ifndef __SHMEM_FS_H
   #define __SHMEM_FS_H
   
@@@ -54,6 -53,8 +54,8 @@@ extern struct file *shmem_file_setup(co
                                         loff_t size, unsigned long flags);
   extern struct file *shmem_kernel_file_setup(const char *name, loff_t size,
                                             unsigned long flags);
+ extern struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt,
+               const char *name, loff_t size, unsigned long flags);
   extern int shmem_zero_setup(struct vm_area_struct *);
   extern unsigned long shmem_get_unmapped_area(struct file *, unsigned long addr,
                 unsigned long len, unsigned long pgoff, unsigned long flags);
diff --combined include/uapi/drm/etnaviv_drm.h

index d4463f3fa42743b75fcd74bc3b9c4f8aafb29ae0,110cc73bf549b488fffc9411b2ea338552808513..e9b997a0ef272afcb8085e35460d7c92c41a0ffd
--- 1/include/uapi/drm/etnaviv_drm.h
--- 2/include/uapi/drm/etnaviv_drm.h
+++ b/include/uapi/drm/etnaviv_drm.h
@@@ -1,4 -1,3 +1,4 @@@
+ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   /*
    * Copyright (C) 2015 Etnaviv Project
    *
@@@ -151,6 -150,19 +151,19 @@@ struct drm_etnaviv_gem_submit_bo 
         __u64 presumed;       /* in/out, presumed buffer address */
   };
   
+ /* performance monitor request (pmr) */
+ #define ETNA_PM_PROCESS_PRE             0x0001
+ #define ETNA_PM_PROCESS_POST            0x0002
+ struct drm_etnaviv_gem_submit_pmr {
+       __u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
+       __u8  domain;         /* in, pm domain */
+       __u8  pad;
+       __u16 signal;         /* in, pm signal */
+       __u32 sequence;       /* in, sequence number */
+       __u32 read_offset;    /* in, offset from read_bo */
+       __u32 read_idx;       /* in, index of read_bo buffer */
+ };
+ 
   /* Each cmdstream submit consists of a table of buffers involved, and
    * one or more cmdstream buffers.  This allows for conditional execution
    * (context-restore), and IB buffers needed for per tile/bin draw cmds.
@@@ -176,6 -188,9 +189,9 @@@ struct drm_etnaviv_gem_submit 
         __u64 stream;         /* in, ptr to cmdstream */
         __u32 flags;          /* in, mask of ETNA_SUBMIT_x */
         __s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
+       __u64 pmrs;           /* in, ptr to array of submit_pmr's */
+       __u32 nr_pmrs;        /* in, number of submit_pmr's */
+       __u32 pad;
   };
   
   /* The normal way to synchronize with the GPU is just to CPU_PREP on
@@@ -211,6 -226,27 +227,27 @@@ struct drm_etnaviv_gem_wait 
         struct drm_etnaviv_timespec timeout;    /* in */
   };
   
+ /*
+  * Performance Monitor (PM):
+  */
+ 
+ struct drm_etnaviv_pm_domain {
+       __u32 pipe;       /* in */
+       __u8  iter;       /* in/out, select pm domain at index iter */
+       __u8  id;         /* out, id of domain */
+       __u16 nr_signals; /* out, how many signals does this domain provide */
+       char  name[64];   /* out, name of domain */
+ };
+ 
+ struct drm_etnaviv_pm_signal {
+       __u32 pipe;       /* in */
+       __u8  domain;     /* in, pm domain index */
+       __u8  pad;
+       __u16 iter;       /* in/out, select pm source at index iter */
+       __u16 id;         /* out, id of signal */
+       char  name[64];   /* out, name of domain */
+ };
+ 
   #define DRM_ETNAVIV_GET_PARAM          0x00
   /* placeholder:
   #define DRM_ETNAVIV_SET_PARAM          0x01
@@@ -223,7 -259,9 +260,9 @@@
   #define DRM_ETNAVIV_WAIT_FENCE         0x07
   #define DRM_ETNAVIV_GEM_USERPTR        0x08
   #define DRM_ETNAVIV_GEM_WAIT           0x09
- #define DRM_ETNAVIV_NUM_IOCTLS         0x0a
+ #define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
+ #define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
+ #define DRM_ETNAVIV_NUM_IOCTLS         0x0c
   
   #define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
   #define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
@@@ -234,6 -272,8 +273,8 @@@
   #define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
   #define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
   #define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
+ #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
+ #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
   
   #if defined(__cplusplus)
   }
diff --combined include/uapi/drm/i915_drm.h

index 9816590d3ad24b0d7037eb65f9b84c3c571c9b53,125bde7d95045e80473a0e709ac7943a8cb9d5cd..ac3c6503ca27f156ddbc3dd304bbf91671a9ac2a
--- 1/include/uapi/drm/i915_drm.h
--- 2/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@@ -397,10 -397,20 +397,20 @@@ typedef struct drm_i915_irq_wait 
   #define I915_PARAM_MIN_EU_IN_POOL      39
   #define I915_PARAM_MMAP_GTT_VERSION    40
   
- /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+ /*
+  * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
    * priorities and the driver will attempt to execute batches in priority order.
+  * The param returns a capability bitmask, nonzero implies that the scheduler
+  * is enabled, with different features present according to the mask.
+  *
+  * The initial priority for each batch is supplied by the context and is
+  * controlled via I915_CONTEXT_PARAM_PRIORITY.
    */
   #define I915_PARAM_HAS_SCHEDULER       41
+ #define   I915_SCHEDULER_CAP_ENABLED  (1ul << 0)
+ #define   I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
+ #define   I915_SCHEDULER_CAP_PREEMPTION       (1ul << 2)
+ 
   #define I915_PARAM_HUC_STATUS          42
   
   /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
@@@ -829,7 -839,6 +839,7 @@@ struct drm_i915_gem_exec_fence 
   
   #define I915_EXEC_FENCE_WAIT            (1<<0)
   #define I915_EXEC_FENCE_SIGNAL          (1<<1)
+ +#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
         __u32 flags;
   };
   
@@@ -1309,14 -1318,16 +1319,16 @@@ struct drm_i915_reg_read 
          * be specified
          */
         __u64 offset;
+ #define I915_REG_READ_8B_WA (1ul << 0)
+ 
         __u64 val; /* Return value */
   };
   /* Known registers:
    *
    * Render engine timestamp - 0x2358 + 64bit - gen7+
    * - Note this register returns an invalid value if using the default
-  *   single instruction 8byte read, in order to workaround that use
-  *   offset (0x2538 | 1) instead.
+  *   single instruction 8byte read, in order to workaround that pass
+  *   flag I915_REG_READ_8B_WA in offset field.
    *
    */
   
@@@ -1359,6 -1370,10 +1371,10 @@@ struct drm_i915_gem_context_param 
   #define I915_CONTEXT_PARAM_GTT_SIZE   0x3
   #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE   0x4
   #define I915_CONTEXT_PARAM_BANNABLE   0x5
+ #define I915_CONTEXT_PARAM_PRIORITY   0x6
+ #define   I915_CONTEXT_MAX_USER_PRIORITY      1023 /* inclusive */
+ #define   I915_CONTEXT_DEFAULT_PRIORITY               0
+ #define   I915_CONTEXT_MIN_USER_PRIORITY      -1023 /* inclusive */
         __u64 value;
   };
   
@@@ -1510,9 -1525,14 +1526,14 @@@ struct drm_i915_perf_oa_config 
         __u32 n_boolean_regs;
         __u32 n_flex_regs;
   
-       __u64 __user mux_regs_ptr;
-       __u64 __user boolean_regs_ptr;
-       __u64 __user flex_regs_ptr;
+       /*
+        * These fields are pointers to tuples of u32 values (register
+        * address, value). For example the expected length of the buffer
+        * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+        */
+       __u64 mux_regs_ptr;
+       __u64 boolean_regs_ptr;
+       __u64 flex_regs_ptr;
   };
   
   #if defined(__cplusplus)
diff --combined mm/shmem.c

index ab22eaa2412eac0ef6c0bc434ed56b81cfe19432,3229d27503ec79ba68f7dec597bb94df0426460d..1f97d77551c3e539f303758693497705c424a4ab
--- 1/mm/shmem.c
--- 2/mm/shmem.c
+++ b/mm/shmem.c
@@@ -338,7 -338,7 +338,7 @@@ static int shmem_radix_tree_replace(str
         if (item != expected)
                 return -ENOENT;
         __radix_tree_replace(&mapping->page_tree, node, pslot,
- -                           replacement, NULL, NULL);
+ +                           replacement, NULL);
         return 0;
   }
   
@@@ -747,7 -747,7 +747,7 @@@ void shmem_unlock_mapping(struct addres
         pgoff_t indices[PAGEVEC_SIZE];
         pgoff_t index = 0;
   
- -      pagevec_init(&pvec, 0);
+ +      pagevec_init(&pvec);
         /*
          * Minor point, but we might as well stop if someone else SHM_LOCKs it.
          */
@@@ -790,7 -790,7 +790,7 @@@ static void shmem_undo_range(struct ino
         if (lend == -1)
                 end = -1;       /* unsigned, so actually very big */
   
- -      pagevec_init(&pvec, 0);
+ +      pagevec_init(&pvec);
         index = start;
         while (index < end) {
                 pvec.nr = find_get_entries(mapping, index,
@@@ -2528,7 -2528,7 +2528,7 @@@ static pgoff_t shmem_seek_hole_data(str
         bool done = false;
         int i;
   
- -      pagevec_init(&pvec, 0);
+ +      pagevec_init(&pvec);
         pvec.nr = 1;            /* start small: we may be there already */
         while (!done) {
                 pvec.nr = find_get_entries(mapping, index,
@@@ -3862,11 -3862,12 +3862,11 @@@ static void shmem_init_inode(void *foo
         inode_init_once(&info->vfs_inode);
   }
   
- -static int shmem_init_inodecache(void)
+ +static void shmem_init_inodecache(void)
   {
         shmem_inode_cachep = kmem_cache_create("shmem_inode_cache",
                                 sizeof(struct shmem_inode_info),
                                 0, SLAB_PANIC|SLAB_ACCOUNT, shmem_init_inode);
- -      return 0;
   }
   
   static void shmem_destroy_inodecache(void)
@@@ -3990,7 -3991,9 +3990,7 @@@ int __init shmem_init(void
         if (shmem_inode_cachep)
                 return 0;
   
- -      error = shmem_init_inodecache();
- -      if (error)
- -              goto out3;
+ +      shmem_init_inodecache();
   
         error = register_filesystem(&shmem_fs_type);
         if (error) {
@@@ -4017,6 -4020,7 +4017,6 @@@ out1
         unregister_filesystem(&shmem_fs_type);
   out2:
         shmem_destroy_inodecache();
- -out3:
         shm_mnt = ERR_PTR(error);
         return error;
   }
@@@ -4098,7 -4102,6 +4098,7 @@@ bool shmem_huge_enabled(struct vm_area_
                         if (i_size >= HPAGE_PMD_SIZE &&
                                         i_size >> PAGE_SHIFT >= off)
                                 return true;
+ +                      /* fall through */
                 case SHMEM_HUGE_ADVISE:
                         /* TODO: implement fadvise() hints */
                         return (vma->vm_flags & VM_HUGEPAGE);
@@@ -4180,7 -4183,7 +4180,7 @@@ static const struct dentry_operations a
         .d_dname = simple_dname
   };
   
- static struct file *__shmem_file_setup(const char *name, loff_t size,
+ static struct file *__shmem_file_setup(struct vfsmount *mnt, const char *name, loff_t size,
                                        unsigned long flags, unsigned int i_flags)
   {
         struct file *res;
@@@ -4189,8 -4192,8 +4189,8 @@@
         struct super_block *sb;
         struct qstr this;
   
-       if (IS_ERR(shm_mnt))
-               return ERR_CAST(shm_mnt);
+       if (IS_ERR(mnt))
+               return ERR_CAST(mnt);
   
         if (size < 0 || size > MAX_LFS_FILESIZE)
                 return ERR_PTR(-EINVAL);
@@@ -4202,8 -4205,8 +4202,8 @@@
         this.name = name;
         this.len = strlen(name);
         this.hash = 0; /* will go */
-       sb = shm_mnt->mnt_sb;
-       path.mnt = mntget(shm_mnt);
+       sb = mnt->mnt_sb;
+       path.mnt = mntget(mnt);
         path.dentry = d_alloc_pseudo(sb, &this);
         if (!path.dentry)
                 goto put_memory;
@@@ -4248,7 -4251,7 +4248,7 @@@ put_path
    */
   struct file *shmem_kernel_file_setup(const char *name, loff_t size, unsigned long flags)
   {
-       return __shmem_file_setup(name, size, flags, S_PRIVATE);
+       return __shmem_file_setup(shm_mnt, name, size, flags, S_PRIVATE);
   }
   
   /**
@@@ -4259,10 -4262,24 +4259,24 @@@
    */
   struct file *shmem_file_setup(const char *name, loff_t size, unsigned long flags)
   {
-       return __shmem_file_setup(name, size, flags, 0);
+       return __shmem_file_setup(shm_mnt, name, size, flags, 0);
   }
   EXPORT_SYMBOL_GPL(shmem_file_setup);
   
+ /**
+  * shmem_file_setup_with_mnt - get an unlinked file living in tmpfs
+  * @mnt: the tmpfs mount where the file will be created
+  * @name: name for dentry (to be seen in /proc/<pid>/maps
+  * @size: size to be set for the file
+  * @flags: VM_NORESERVE suppresses pre-accounting of the entire object size
+  */
+ struct file *shmem_file_setup_with_mnt(struct vfsmount *mnt, const char *name,
+                                      loff_t size, unsigned long flags)
+ {
+       return __shmem_file_setup(mnt, name, size, flags, 0);
+ }
+ EXPORT_SYMBOL_GPL(shmem_file_setup_with_mnt);
+ 
   /**
    * shmem_zero_setup - setup a shared anonymous mapping
    * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
@@@ -4278,7 -4295,7 +4292,7 @@@ int shmem_zero_setup(struct vm_area_str
          * accessible to the user through its mapping, use S_PRIVATE flag to
          * bypass file security, in the same way as shmem_kernel_file_setup().
          */
-       file = __shmem_file_setup("dev/zero", size, vma->vm_flags, S_PRIVATE);
+       file = shmem_kernel_file_setup("dev/zero", size, vma->vm_flags);
         if (IS_ERR(file))
                 return PTR_ERR(file);
   
diff --combined scripts/coccinelle/api/drm-get-put.cocci

index bf1313274f0b647183c726f0039f65dbe1824688,dc10dee356c283d06587a4eecfeb4e2272ef8a16..91fceb8f1fa28a65f5acea5b2a347cf6db4a8225
--- 1/scripts/coccinelle/api/drm-get-put.cocci
--- 2/scripts/coccinelle/api/drm-get-put.cocci
+++ b/scripts/coccinelle/api/drm-get-put.cocci
@@@ -1,4 -1,3 +1,4 @@@
+ +// SPDX-License-Identifier: GPL-2.0
   ///
   /// Use drm_*_get() and drm_*_put() helpers instead of drm_*_reference() and
   /// drm_*_unreference() helpers.
@@@ -51,6 -50,9 +51,9 @@@ expression object
   |
   - drm_property_unreference_blob(object)
   + drm_property_blob_put(object)
+ |
+ - drm_dev_unref(object)
+ + drm_dev_put(object)
   )
   
   @r depends on report@
@@@ -82,6 -84,8 +85,8 @@@ drm_gem_object_unreference_unlocked(obj
   drm_property_unreference_blob@p(object)
   |
   drm_property_reference_blob@p(object)
+ |
+ drm_dev_unref@p(object)
   )
   
   @script:python depends on report@
author	Linus Torvalds <torvalds@linux-foundation.org>
	Thu, 16 Nov 2017 04:42:10 +0000 (20:42 -0800)
committer	Linus Torvalds <torvalds@linux-foundation.org>
	Thu, 16 Nov 2017 04:42:10 +0000 (20:42 -0800)
		1	2
Documentation/admin-guide/kernel-parameters.txt	patch \|	diff1 \|	diff2 \|	blob \| history
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt	patch \|	diff1 \|	diff2 \|	blob \| history
Documentation/devicetree/bindings/vendor-prefixes.txt	patch \|	diff1 \|	diff2 \|	blob \| history
MAINTAINERS	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/powerplay/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/powerplay/smumgr/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/armada/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/armada/armada_trace.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/bridge/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/drm_trace.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/etnaviv/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/etnaviv/etnaviv_gem.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/etnaviv/etnaviv_gpu.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_drv.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_gem.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_gem_context.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_gem_execbuffer.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_gem_gtt.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_gem_userptr.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/i915_trace.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/intel_display.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/intel_dp.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/intel_drv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/intel_pm.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/intel_ringbuffer.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/selftests/i915_live_selftests.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/i915/selftests/i915_mock_selftests.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/msm/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/cl506e.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/cl506f.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/cl826e.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/cl826f.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/cl906f.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/cla06f.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/class.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/device.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/ioctl.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/object.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvif/os.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/client.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/device.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/memory.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/mm.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/object.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/os.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_abi16.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_bo.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_chan.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_display.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_drv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_fence.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_gem.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nouveau_sgdma.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nv50_display.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/omapdrm/dss/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/panel/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/pl111/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/radeon/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/radeon/radeon_trace.h	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/radeon/radeon_ttm.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/rockchip/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/sun4i/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/tegra/drm.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/drm/vc4/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/host1x/Makefile	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/host1x/bus.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/gpu/host1x/dev.c	patch \|	diff1 \|	diff2 \|	blob \| history
drivers/staging/vboxvideo/vbox_mode.c	patch \|	diff1 \|	diff2 \|	blob \| history
include/drm/drm_fb_cma_helper.h	patch \|	diff1 \|	diff2 \|	blob \| history
include/drm/drm_of.h	patch \|	diff1 \|	diff2 \|	blob \| history
include/linux/scatterlist.h	patch \|	diff1 \|	diff2 \|	blob \| history
include/linux/shmem_fs.h	patch \|	diff1 \|	diff2 \|	blob \| history
include/uapi/drm/etnaviv_drm.h	patch \|	diff1 \|	diff2 \|	blob \| history
include/uapi/drm/i915_drm.h	patch \|	diff1 \|	diff2 \|	blob \| history
mm/shmem.c	patch \|	diff1 \|	diff2 \|	blob \| history
scripts/coccinelle/api/drm-get-put.cocci	patch \|	diff1 \|	diff2 \|	blob \| history