drm/i915/skl+: support verification of DDB HW state for NV12

For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Config register. Both register values
should be verified during verify_wm_state.

v2: Addressed review comments by Maarten.

v3: Addressed review comments by Shashank Sharma.

v4: Adding reviewed by tag from Shashank Sharma

v5: Added reviewed by from Juha-Pekka Heikkila

v6: Rebased the series

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-5-git-send-email-vidya.srinivas@intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fa78f2590eea764b4771fa3cf526b97889aa8c30..057f3cf95e862a26134c6f76c61396b6af2f1442 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2657,7 +2657,7 @@ static int i9xx_format_to_fourcc(int format)
        }
 }
 
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
        switch (format) {
        case PLANE_CTL_FORMAT_RGB_565:

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 626a46c11f50b6c2c75a860b540ed0552b33a880..4eeaca3504111496d83b42e77364bfe8ab26061d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1613,6 +1613,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
                            struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fda22b1ae7535822f7d3c886d62de0f9d3d4d26e..d22d9b2cbc62f5a62ffe1d9cf20ac5e2fbb4f4f3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3825,6 +3825,44 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
                entry->end += 1;
 }
 
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+                          const enum pipe pipe,
+                          const enum plane_id plane_id,
+                          struct skl_ddb_allocation *ddb /* out */)
+{
+       u32 val, val2 = 0;
+       int fourcc, pixel_format;
+
+       /* Cursor doesn't support NV12/planar, so no extra calculation needed */
+       if (plane_id == PLANE_CURSOR) {
+               val = I915_READ(CUR_BUF_CFG(pipe));
+               skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+               return;
+       }
+
+       val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+       /* No DDB allocated for disabled planes */
+       if (!(val & PLANE_CTL_ENABLE))
+               return;
+
+       pixel_format = val & PLANE_CTL_FORMAT_MASK;
+       fourcc = skl_format_to_fourcc(pixel_format,
+                                     val & PLANE_CTL_ORDER_RGBX,
+                                     val & PLANE_CTL_ALPHA_MASK);
+
+       val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+       val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+       if (fourcc == DRM_FORMAT_NV12) {
+               skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+               skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+       } else {
+               skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+       }
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
                          struct skl_ddb_allocation *ddb /* out */)
 {
@@ -3841,16 +3879,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
                if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
                        continue;
 
-               for_each_plane_id_on_crtc(crtc, plane_id) {
-                       u32 val;
-
-                       if (plane_id != PLANE_CURSOR)
-                               val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-                       else
-                               val = I915_READ(CUR_BUF_CFG(pipe));
-
-                       skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
-               }
+               for_each_plane_id_on_crtc(crtc, plane_id)
+                       skl_ddb_get_hw_plane_state(dev_priv, pipe,
+                                                  plane_id, ddb);
 
                intel_display_power_put(dev_priv, power_domain);
        }