Merge remote-tracking branches 'asoc/topic/mtk', 'asoc/topic/nau8540', 'asoc/topic...
authorMark Brown <broonie@kernel.org>
Fri, 12 Jan 2018 12:29:18 +0000 (12:29 +0000)
committerMark Brown <broonie@kernel.org>
Fri, 12 Jan 2018 12:29:18 +0000 (12:29 +0000)
16 files changed:
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
Documentation/devicetree/bindings/sound/nau8825.txt
sound/soc/codecs/nau8540.c
sound/soc/codecs/nau8540.h
sound/soc/codecs/nau8824.c
sound/soc/codecs/nau8825.c
sound/soc/codecs/nau8825.h
sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
sound/soc/mediatek/mt2701/mt2701-afe-common.h
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
sound/soc/mediatek/mt2701/mt2701-reg.h
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
sound/soc/mediatek/mt8173/mt8173-rt5650.c
sound/soc/nuc900/nuc900-ac97.c

index 77a57f84bed486204f0a7caa3780d6e18416544a..6df87b97f7cb27c0293e823f78ac41e5721ab877 100644 (file)
@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701
 
 Required properties:
 - compatible = "mediatek,mt2701-audio";
-- reg: register location and size
 - interrupts: should contain AFE and ASYS interrupts
 - interrupt-names: should be "afe" and "asys"
 - power-domains: should define the power domain
+- clocks: Must contain an entry for each entry in clock-names
+  See ../clocks/clock-bindings.txt for details
 - clock-names: should have these clock names:
                "infra_sys_audio_clk",
                "top_audio_mux1_sel",
                "top_audio_mux2_sel",
-               "top_audio_mux1_div",
-               "top_audio_mux2_div",
-               "top_audio_48k_timing",
-               "top_audio_44k_timing",
-               "top_audpll_mux_sel",
-               "top_apll_sel",
-               "top_aud1_pll_98M",
-               "top_aud2_pll_90M",
-               "top_hadds2_pll_98M",
-               "top_hadds2_pll_294M",
-               "top_audpll",
-               "top_audpll_d4",
-               "top_audpll_d8",
-               "top_audpll_d16",
-               "top_audpll_d24",
-               "top_audintbus_sel",
-               "clk_26m",
-               "top_syspll1_d4",
-               "top_aud_k1_src_sel",
-               "top_aud_k2_src_sel",
-               "top_aud_k3_src_sel",
-               "top_aud_k4_src_sel",
-               "top_aud_k5_src_sel",
-               "top_aud_k6_src_sel",
-               "top_aud_k1_src_div",
-               "top_aud_k2_src_div",
-               "top_aud_k3_src_div",
-               "top_aud_k4_src_div",
-               "top_aud_k5_src_div",
-               "top_aud_k6_src_div",
-               "top_aud_i2s1_mclk",
-               "top_aud_i2s2_mclk",
-               "top_aud_i2s3_mclk",
-               "top_aud_i2s4_mclk",
-               "top_aud_i2s5_mclk",
-               "top_aud_i2s6_mclk",
-               "top_asm_m_sel",
-               "top_asm_h_sel",
-               "top_univpll2_d4",
-               "top_univpll2_d2",
-               "top_syspll_d5";
+               "top_audio_a1sys_hp",
+               "top_audio_a2sys_hp",
+               "i2s0_src_sel",
+               "i2s1_src_sel",
+               "i2s2_src_sel",
+               "i2s3_src_sel",
+               "i2s0_src_div",
+               "i2s1_src_div",
+               "i2s2_src_div",
+               "i2s3_src_div",
+               "i2s0_mclk_en",
+               "i2s1_mclk_en",
+               "i2s2_mclk_en",
+               "i2s3_mclk_en",
+               "i2so0_hop_ck",
+               "i2so1_hop_ck",
+               "i2so2_hop_ck",
+               "i2so3_hop_ck",
+               "i2si0_hop_ck",
+               "i2si1_hop_ck",
+               "i2si2_hop_ck",
+               "i2si3_hop_ck",
+               "asrc0_out_ck",
+               "asrc1_out_ck",
+               "asrc2_out_ck",
+               "asrc3_out_ck",
+               "audio_afe_pd",
+               "audio_afe_conn_pd",
+               "audio_a1sys_pd",
+               "audio_a2sys_pd",
+               "audio_mrgif_pd";
+- assigned-clocks: list of input clocks and dividers for the audio system.
+                  See ../clocks/clock-bindings.txt for details.
+- assigned-clocks-parents: parent of input clocks of assigned clocks.
+- assigned-clock-rates: list of clock frequencies of assigned clocks.
+
+Must be a subnode of MediaTek audsys device tree node.
+See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
 
 Example:
 
-       afe: mt2701-afe-pcm@11220000 {
-               compatible = "mediatek,mt2701-audio";
-               reg = <0 0x11220000 0 0x2000>,
-                     <0 0x112A0000 0 0x20000>;
-               interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
-               interrupt-names = "afe", "asys";
-               power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-               clocks = <&infracfg CLK_INFRA_AUDIO>,
-                        <&topckgen CLK_TOP_AUD_MUX1_SEL>,
-                        <&topckgen CLK_TOP_AUD_MUX2_SEL>,
-                        <&topckgen CLK_TOP_AUD_MUX1_DIV>,
-                        <&topckgen CLK_TOP_AUD_MUX2_DIV>,
-                        <&topckgen CLK_TOP_AUD_48K_TIMING>,
-                        <&topckgen CLK_TOP_AUD_44K_TIMING>,
-                        <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
-                        <&topckgen CLK_TOP_APLL_SEL>,
-                        <&topckgen CLK_TOP_AUD1PLL_98M>,
-                        <&topckgen CLK_TOP_AUD2PLL_90M>,
-                        <&topckgen CLK_TOP_HADDS2PLL_98M>,
-                        <&topckgen CLK_TOP_HADDS2PLL_294M>,
-                        <&topckgen CLK_TOP_AUDPLL>,
-                        <&topckgen CLK_TOP_AUDPLL_D4>,
-                        <&topckgen CLK_TOP_AUDPLL_D8>,
-                        <&topckgen CLK_TOP_AUDPLL_D16>,
-                        <&topckgen CLK_TOP_AUDPLL_D24>,
-                        <&topckgen CLK_TOP_AUDINTBUS_SEL>,
-                        <&clk26m>,
-                        <&topckgen CLK_TOP_SYSPLL1_D4>,
-                        <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
-                        <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
-                        <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
-                        <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
-                        <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
-                        <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
-                        <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
-                        <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
-                        <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
-                        <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
-                        <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
-                        <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
-                        <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
-                        <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
-                        <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
-                        <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
-                        <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
-                        <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
-                        <&topckgen CLK_TOP_ASM_M_SEL>,
-                        <&topckgen CLK_TOP_ASM_H_SEL>,
-                        <&topckgen CLK_TOP_UNIVPLL2_D4>,
-                        <&topckgen CLK_TOP_UNIVPLL2_D2>,
-                        <&topckgen CLK_TOP_SYSPLL_D5>;
+       audsys: audio-subsystem@11220000 {
+               compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+               ...
+
+               afe: audio-controller {
+                       compatible = "mediatek,mt2701-audio";
+                       interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+                                     <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+                       interrupt-names = "afe", "asys";
+                       power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+                       clocks = <&infracfg CLK_INFRA_AUDIO>,
+                                <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+                                <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+                                <&topckgen CLK_TOP_AUD_48K_TIMING>,
+                                <&topckgen CLK_TOP_AUD_44K_TIMING>,
+                                <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+                                <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+                                <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+                                <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+                                <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+                                <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+                                <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+                                <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+                                <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+                                <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+                                <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+                                <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+                                <&audsys CLK_AUD_I2SO1>,
+                                <&audsys CLK_AUD_I2SO2>,
+                                <&audsys CLK_AUD_I2SO3>,
+                                <&audsys CLK_AUD_I2SO4>,
+                                <&audsys CLK_AUD_I2SIN1>,
+                                <&audsys CLK_AUD_I2SIN2>,
+                                <&audsys CLK_AUD_I2SIN3>,
+                                <&audsys CLK_AUD_I2SIN4>,
+                                <&audsys CLK_AUD_ASRCO1>,
+                                <&audsys CLK_AUD_ASRCO2>,
+                                <&audsys CLK_AUD_ASRCO3>,
+                                <&audsys CLK_AUD_ASRCO4>,
+                                <&audsys CLK_AUD_AFE>,
+                                <&audsys CLK_AUD_AFE_CONN>,
+                                <&audsys CLK_AUD_A1SYS>,
+                                <&audsys CLK_AUD_A2SYS>,
+                                <&audsys CLK_AUD_AFE_MRGIF>;
+
+                       clock-names = "infra_sys_audio_clk",
+                                     "top_audio_mux1_sel",
+                                     "top_audio_mux2_sel",
+                                     "top_audio_a1sys_hp",
+                                     "top_audio_a2sys_hp",
+                                     "i2s0_src_sel",
+                                     "i2s1_src_sel",
+                                     "i2s2_src_sel",
+                                     "i2s3_src_sel",
+                                     "i2s0_src_div",
+                                     "i2s1_src_div",
+                                     "i2s2_src_div",
+                                     "i2s3_src_div",
+                                     "i2s0_mclk_en",
+                                     "i2s1_mclk_en",
+                                     "i2s2_mclk_en",
+                                     "i2s3_mclk_en",
+                                     "i2so0_hop_ck",
+                                     "i2so1_hop_ck",
+                                     "i2so2_hop_ck",
+                                     "i2so3_hop_ck",
+                                     "i2si0_hop_ck",
+                                     "i2si1_hop_ck",
+                                     "i2si2_hop_ck",
+                                     "i2si3_hop_ck",
+                                     "asrc0_out_ck",
+                                     "asrc1_out_ck",
+                                     "asrc2_out_ck",
+                                     "asrc3_out_ck",
+                                     "audio_afe_pd",
+                                     "audio_afe_conn_pd",
+                                     "audio_a1sys_pd",
+                                     "audio_a2sys_pd",
+                                     "audio_mrgif_pd";
 
-               clock-names = "infra_sys_audio_clk",
-                             "top_audio_mux1_sel",
-                             "top_audio_mux2_sel",
-                             "top_audio_mux1_div",
-                             "top_audio_mux2_div",
-                             "top_audio_48k_timing",
-                             "top_audio_44k_timing",
-                             "top_audpll_mux_sel",
-                             "top_apll_sel",
-                             "top_aud1_pll_98M",
-                             "top_aud2_pll_90M",
-                             "top_hadds2_pll_98M",
-                             "top_hadds2_pll_294M",
-                             "top_audpll",
-                             "top_audpll_d4",
-                             "top_audpll_d8",
-                             "top_audpll_d16",
-                             "top_audpll_d24",
-                             "top_audintbus_sel",
-                             "clk_26m",
-                             "top_syspll1_d4",
-                             "top_aud_k1_src_sel",
-                             "top_aud_k2_src_sel",
-                             "top_aud_k3_src_sel",
-                             "top_aud_k4_src_sel",
-                             "top_aud_k5_src_sel",
-                             "top_aud_k6_src_sel",
-                             "top_aud_k1_src_div",
-                             "top_aud_k2_src_div",
-                             "top_aud_k3_src_div",
-                             "top_aud_k4_src_div",
-                             "top_aud_k5_src_div",
-                             "top_aud_k6_src_div",
-                             "top_aud_i2s1_mclk",
-                             "top_aud_i2s2_mclk",
-                             "top_aud_i2s3_mclk",
-                             "top_aud_i2s4_mclk",
-                             "top_aud_i2s5_mclk",
-                             "top_aud_i2s6_mclk",
-                             "top_asm_m_sel",
-                             "top_asm_h_sel",
-                             "top_univpll2_d4",
-                             "top_univpll2_d2",
-                             "top_syspll_d5";
+                       assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+                                         <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+                                         <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+                                         <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+                                                <&topckgen CLK_TOP_AUD2PLL_90M>;
+                       assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+               };
        };
index 2f5e973285a648a3a7ea1bedb5d5cc9c79311589..d16d96839bcbf1a9aeb9c11fc5ffb79c25115c43 100644 (file)
@@ -69,7 +69,7 @@ Optional properties:
   - nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
   - nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
 
-  - nuvoton,crosstalk-bypass: make crosstalk function bypass if set.
+  - nuvoton,crosstalk-enable: make crosstalk function enable if set.
 
   - clocks: list of phandle and clock specifier pairs according to common clock bindings for the
       clocks described in clock-names
@@ -98,7 +98,7 @@ Example:
       nuvoton,short-key-debounce = <2>;
       nuvoton,jack-insert-debounce = <7>;
       nuvoton,jack-eject-debounce = <7>;
-      nuvoton,crosstalk-bypass;
+      nuvoton,crosstalk-enable;
 
       clock-names = "mclk";
       clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
index f9c9933acffb60ee50c9c7ec062e3cc278bedf60..b08fb7e243c3ce3ca75d08a78f79a4e7ce6b8e4f 100644 (file)
@@ -233,6 +233,41 @@ static SOC_ENUM_SINGLE_DECL(
 static const struct snd_kcontrol_new digital_ch1_mux =
        SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
 
+static int adc_power_control(struct snd_soc_dapm_widget *w,
+               struct snd_kcontrol *k, int  event)
+{
+       struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+       struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
+
+       if (SND_SOC_DAPM_EVENT_ON(event)) {
+               msleep(300);
+               /* DO12 and DO34 pad output enable */
+               regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
+                       NAU8540_I2S_DO12_TRI, 0);
+               regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
+                       NAU8540_I2S_DO34_TRI, 0);
+       } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
+               regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
+                       NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
+               regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
+                       NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
+       }
+       return 0;
+}
+
+static int aiftx_power_control(struct snd_soc_dapm_widget *w,
+               struct snd_kcontrol *k, int  event)
+{
+       struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+       struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
+
+       if (SND_SOC_DAPM_EVENT_OFF(event)) {
+               regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
+               regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
+       }
+       return 0;
+}
+
 static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
        SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
        SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
@@ -247,14 +282,18 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
        SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
        SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
 
-       SND_SOC_DAPM_ADC("ADC1", NULL,
-               NAU8540_REG_POWER_MANAGEMENT, 0, 0),
-       SND_SOC_DAPM_ADC("ADC2", NULL,
-               NAU8540_REG_POWER_MANAGEMENT, 1, 0),
-       SND_SOC_DAPM_ADC("ADC3", NULL,
-               NAU8540_REG_POWER_MANAGEMENT, 2, 0),
-       SND_SOC_DAPM_ADC("ADC4", NULL,
-               NAU8540_REG_POWER_MANAGEMENT, 3, 0),
+       SND_SOC_DAPM_ADC_E("ADC1", NULL,
+               NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+       SND_SOC_DAPM_ADC_E("ADC2", NULL,
+               NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+       SND_SOC_DAPM_ADC_E("ADC3", NULL,
+               NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+       SND_SOC_DAPM_ADC_E("ADC4", NULL,
+               NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
        SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
        SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
@@ -270,7 +309,8 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
        SND_SOC_DAPM_MUX("Digital CH1 Mux",
                SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
 
-       SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
+               aiftx_power_control, SND_SOC_DAPM_POST_PMD),
 };
 
 static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
@@ -575,7 +615,8 @@ static void nau8540_fll_apply(struct regmap *regmap,
                NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
                NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
        regmap_update_bits(regmap, NAU8540_REG_FLL1,
-               NAU8540_FLL_RATIO_MASK, fll_param->ratio);
+               NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
+               fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
        /* FLL 16-bit fractional input */
        regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
        /* FLL 10-bit integer input */
@@ -596,13 +637,14 @@ static void nau8540_fll_apply(struct regmap *regmap,
                        NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
                        NAU8540_FLL_FTR_SW_FILTER);
                regmap_update_bits(regmap, NAU8540_REG_FLL6,
-                       NAU8540_SDM_EN, NAU8540_SDM_EN);
+                       NAU8540_SDM_EN | NAU8540_CUTOFF500,
+                       NAU8540_SDM_EN | NAU8540_CUTOFF500);
        } else {
                regmap_update_bits(regmap, NAU8540_REG_FLL5,
                        NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
                        NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
-               regmap_update_bits(regmap,
-                       NAU8540_REG_FLL6, NAU8540_SDM_EN, 0);
+               regmap_update_bits(regmap, NAU8540_REG_FLL6,
+                       NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
        }
 }
 
@@ -617,17 +659,22 @@ static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
        switch (pll_id) {
        case NAU8540_CLK_FLL_MCLK:
                regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
-                       NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK);
+                       NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
+                       NAU8540_FLL_CLK_SRC_MCLK | 0);
                break;
 
        case NAU8540_CLK_FLL_BLK:
                regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
-                       NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK);
+                       NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
+                       NAU8540_FLL_CLK_SRC_BLK |
+                       (0xf << NAU8540_GAIN_ERR_SFT));
                break;
 
        case NAU8540_CLK_FLL_FS:
                regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
-                       NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS);
+                       NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
+                       NAU8540_FLL_CLK_SRC_FS |
+                       (0xf << NAU8540_GAIN_ERR_SFT));
                break;
 
        default:
@@ -710,9 +757,24 @@ static void nau8540_init_regs(struct nau8540 *nau8540)
        regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
                NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
                NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
-       /* ADC OSR selection, CLK_ADC = Fs * OSR */
+       /* ADC OSR selection, CLK_ADC = Fs * OSR;
+        * Channel time alignment enable.
+        */
        regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
-               NAU8540_ADC_OSR_MASK, NAU8540_ADC_OSR_64);
+               NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
+               NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
+       /* PGA input mode selection */
+       regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
+               NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
+               NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
+       regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
+               NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
+               NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
+       /* DO12 and DO34 pad output disable */
+       regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
+               NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
+       regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
+               NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
 }
 
 static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec)
index 5db5b224944dd12ceff7df4d8244bc7bfd8d48e1..732b490edf81488da4567fbb062cfa5938702f45 100644 (file)
 #define NAU8540_CLK_MCLK_SRC_MASK      0xf
 
 /* FLL1 (0x04) */
+#define NAU8540_ICTRL_LATCH_SFT        10
+#define NAU8540_ICTRL_LATCH_MASK       (0x7 << NAU8540_ICTRL_LATCH_SFT)
 #define NAU8540_FLL_RATIO_MASK 0x7f
 
 /* FLL3 (0x06) */
+#define NAU8540_GAIN_ERR_SFT           12
+#define NAU8540_GAIN_ERR_MASK          (0xf << NAU8540_GAIN_ERR_SFT)
 #define NAU8540_FLL_CLK_SRC_SFT        10
 #define NAU8540_FLL_CLK_SRC_MASK       (0x3 << NAU8540_FLL_CLK_SRC_SFT)
 #define NAU8540_FLL_CLK_SRC_MCLK       (0 << NAU8540_FLL_CLK_SRC_SFT)
 /* FLL6 (0x9) */
 #define NAU8540_DCO_EN                 (0x1 << 15)
 #define NAU8540_SDM_EN                 (0x1 << 14)
+#define NAU8540_CUTOFF500              (0x1 << 13)
 
 /* PCM_CTRL0 (0x10) */
 #define NAU8540_I2S_BP_SFT             7
 #define NAU8540_I2S_DF_PCM_AB          0x3
 
 /* PCM_CTRL1 (0x11) */
+#define NAU8540_I2S_DO12_TRI           (0x1 << 15)
 #define NAU8540_I2S_LRC_DIV_SFT        12
 #define NAU8540_I2S_LRC_DIV_MASK       (0x3 << NAU8540_I2S_LRC_DIV_SFT)
 #define NAU8540_I2S_DO12_OE            (0x1 << 4)
 #define NAU8540_I2S_BLK_DIV_MASK       0x7
 
 /* PCM_CTRL1 (0x12) */
+#define NAU8540_I2S_DO34_TRI           (0x1 << 15)
 #define NAU8540_I2S_DO34_OE            (0x1 << 11)
 #define NAU8540_I2S_TSLOT_L_MASK       0x3ff
 
 #define NAU8540_TDM_TX_MASK            0xf
 
 /* ADC_SAMPLE_RATE (0x3A) */
+#define NAU8540_CH_SYNC                (0x1 << 14)
 #define NAU8540_ADC_OSR_MASK           0x3
 #define NAU8540_ADC_OSR_256            0x3
 #define NAU8540_ADC_OSR_128            0x2
 #define NAU8540_PRECHARGE_DIS          (0x1 << 13)
 #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
 
+/* FEPGA1 (0x69) */
+#define NAU8540_FEPGA1_MODCH2_SHT_SFT  7
+#define NAU8540_FEPGA1_MODCH2_SHT      (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
+#define NAU8540_FEPGA1_MODCH1_SHT_SFT  3
+#define NAU8540_FEPGA1_MODCH1_SHT      (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
+
+/* FEPGA2 (0x6A) */
+#define NAU8540_FEPGA2_MODCH4_SHT_SFT  7
+#define NAU8540_FEPGA2_MODCH4_SHT      (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
+#define NAU8540_FEPGA2_MODCH3_SHT_SFT  3
+#define NAU8540_FEPGA2_MODCH3_SHT      (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
+
 
 /* System Clock Source */
 enum {
index 0240759f951c7ea22b06004aa0e26320bba224fa..088e0cef4cb8d469f17c24f22941e045fbc5f1a8 100644 (file)
@@ -43,7 +43,7 @@ static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
 
 /* the parameter threshold of FLL */
 #define NAU_FREF_MAX 13500000
-#define NAU_FVCO_MAX 124000000
+#define NAU_FVCO_MAX 100000000
 #define NAU_FVCO_MIN 90000000
 
 /* scaling for mclk from sysclk_src output */
@@ -811,7 +811,8 @@ static void nau8824_eject_jack(struct nau8824 *nau8824)
                NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
 
        /* Close clock for jack type detection at manual mode */
-       nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
+       if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
+               nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
 }
 
 static void nau8824_jdet_work(struct work_struct *work)
@@ -843,6 +844,11 @@ static void nau8824_jdet_work(struct work_struct *work)
        event_mask |= SND_JACK_HEADSET;
        snd_soc_jack_report(nau8824->jack, event, event_mask);
 
+       /* Enable short key press and release interruption. */
+       regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
+               NAU8824_IRQ_KEY_RELEASE_DIS |
+               NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
+
        nau8824_sema_release(nau8824);
 }
 
@@ -850,15 +856,15 @@ static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
 {
        struct regmap *regmap = nau8824->regmap;
 
-       /* Enable jack ejection, short key press and release interruption. */
+       /* Enable jack ejection interruption. */
        regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
                NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
                NAU8824_IRQ_EJECT_EN);
        regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
-               NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_KEY_RELEASE_DIS |
-               NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
+               NAU8824_IRQ_EJECT_DIS, 0);
        /* Enable internal VCO needed for interruptions */
-       nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
+       if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
+               nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
        regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
                NAU8824_JD_SLEEP_MODE, 0);
 }
index e853a6dfd33b0ee7b8bf700dffea8b1e477f2d09..a1b697b6fb6483a357f68efa5818725a2a6e62e8 100644 (file)
@@ -194,10 +194,10 @@ static const struct reg_default nau8825_reg_defaults[] = {
 
 /* register backup table when cross talk detection */
 static struct reg_default nau8825_xtalk_baktab[] = {
-       { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
+       { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
        { NAU8825_REG_HSVOL_CTRL, 0 },
-       { NAU8825_REG_DACL_CTRL, 0 },
-       { NAU8825_REG_DACR_CTRL, 0 },
+       { NAU8825_REG_DACL_CTRL, 0x00cf },
+       { NAU8825_REG_DACR_CTRL, 0x02cf },
 };
 
 static const unsigned short logtable[256] = {
@@ -245,13 +245,14 @@ static const unsigned short logtable[256] = {
  * tasks are allowed to acquire the semaphore, calling this function will
  * put the task to sleep. If the semaphore is not released within the
  * specified number of jiffies, this function returns.
- * Acquires the semaphore without jiffies. If no more tasks are allowed
- * to acquire the semaphore, calling this function will put the task to
- * sleep until the semaphore is released.
  * If the semaphore is not released within the specified number of jiffies,
- * this function returns -ETIME.
- * If the sleep is interrupted by a signal, this function will return -EINTR.
- * It returns 0 if the semaphore was acquired successfully.
+ * this function returns -ETIME. If the sleep is interrupted by a signal,
+ * this function will return -EINTR. It returns 0 if the semaphore was
+ * acquired successfully.
+ *
+ * Acquires the semaphore without jiffies. Try to acquire the semaphore
+ * atomically. Returns 0 if the semaphore has been acquired successfully
+ * or 1 if it it cannot be acquired.
  */
 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
 {
@@ -262,8 +263,8 @@ static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
                if (ret < 0)
                        dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
        } else {
-               ret = down_interruptible(&nau8825->xtalk_sem);
-               if (ret < 0)
+               ret = down_trylock(&nau8825->xtalk_sem);
+               if (ret)
                        dev_warn(nau8825->dev, "Acquire semaphore fail\n");
        }
 
@@ -454,22 +455,32 @@ static void nau8825_xtalk_backup(struct nau8825 *nau8825)
 {
        int i;
 
+       if (nau8825->xtalk_baktab_initialized)
+               return;
+
        /* Backup some register values to backup table */
        for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
                regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
                                &nau8825_xtalk_baktab[i].def);
+
+       nau8825->xtalk_baktab_initialized = true;
 }
 
-static void nau8825_xtalk_restore(struct nau8825 *nau8825)
+static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel)
 {
        int i, volume;
 
+       if (!nau8825->xtalk_baktab_initialized)
+               return;
+
        /* Restore register values from backup table; When the driver restores
-        * the headphone volumem, it needs recover to original level gradually
-        * with 3dB per step for less pop noise.
+        * the headphone volume in XTALK_DONE state, it needs recover to
+        * original level gradually with 3dB per step for less pop noise.
+        * Otherwise, the restore should do ASAP.
         */
        for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
-               if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
+               if (!cause_cancel && nau8825_xtalk_baktab[i].reg ==
+                       NAU8825_REG_HSVOL_CTRL) {
                        /* Ramping up the volume change to reduce pop noise */
                        volume = nau8825_xtalk_baktab[i].def &
                                NAU8825_HPR_VOL_MASK;
@@ -479,6 +490,8 @@ static void nau8825_xtalk_restore(struct nau8825 *nau8825)
                regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
                                nau8825_xtalk_baktab[i].def);
        }
+
+       nau8825->xtalk_baktab_initialized = false;
 }
 
 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
@@ -644,7 +657,7 @@ static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
                NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
 }
 
-static void nau8825_xtalk_clean(struct nau8825 *nau8825)
+static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel)
 {
        /* Enable internal VCO needed for interruptions */
        nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
@@ -660,7 +673,7 @@ static void nau8825_xtalk_clean(struct nau8825 *nau8825)
                NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
                NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
        /* Restore value of specific register for cross talk */
-       nau8825_xtalk_restore(nau8825);
+       nau8825_xtalk_restore(nau8825, cause_cancel);
 }
 
 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
@@ -779,7 +792,7 @@ static void nau8825_xtalk_measure(struct nau8825 *nau8825)
                dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
                regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
                                        (sidetone << 8) | sidetone);
-               nau8825_xtalk_clean(nau8825);
+               nau8825_xtalk_clean(nau8825, false);
                nau8825->xtalk_state = NAU8825_XTALK_DONE;
                break;
        default:
@@ -815,13 +828,14 @@ static void nau8825_xtalk_work(struct work_struct *work)
 
 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
 {
-       /* If the xtalk_protect is true, that means the process is still
-        * on going. The driver forces to cancel the cross talk task and
+       /* If the crosstalk is eanbled and the process is on going,
+        * the driver forces to cancel the crosstalk task and
         * restores the configuration to original status.
         */
-       if (nau8825->xtalk_protect) {
+       if (nau8825->xtalk_enable && nau8825->xtalk_state !=
+               NAU8825_XTALK_DONE) {
                cancel_work_sync(&nau8825->xtalk_work);
-               nau8825_xtalk_clean(nau8825);
+               nau8825_xtalk_clean(nau8825, true);
        }
        /* Reset parameters for cross talk suppression function */
        nau8825_sema_reset(nau8825);
@@ -1246,8 +1260,10 @@ static int nau8825_hw_params(struct snd_pcm_substream *substream,
                regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
                osr &= NAU8825_DAC_OVERSAMPLE_MASK;
                if (nau8825_clock_check(nau8825, substream->stream,
-                       params_rate(params), osr))
+                       params_rate(params), osr)) {
+                       nau8825_sema_release(nau8825);
                        return -EINVAL;
+               }
                regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
                        NAU8825_CLK_DAC_SRC_MASK,
                        osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
@@ -1255,8 +1271,10 @@ static int nau8825_hw_params(struct snd_pcm_substream *substream,
                regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
                osr &= NAU8825_ADC_SYNC_DOWN_MASK;
                if (nau8825_clock_check(nau8825, substream->stream,
-                       params_rate(params), osr))
+                       params_rate(params), osr)) {
+                       nau8825_sema_release(nau8825);
                        return -EINVAL;
+               }
                regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
                        NAU8825_CLK_ADC_SRC_MASK,
                        osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
@@ -1273,8 +1291,10 @@ static int nau8825_hw_params(struct snd_pcm_substream *substream,
                        bclk_div = 1;
                else if (bclk_fs <= 128)
                        bclk_div = 0;
-               else
+               else {
+                       nau8825_sema_release(nau8825);
                        return -EINVAL;
+               }
                regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
                        NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
                        ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
@@ -1294,6 +1314,7 @@ static int nau8825_hw_params(struct snd_pcm_substream *substream,
                val_len |= NAU8825_I2S_DL_32;
                break;
        default:
+               nau8825_sema_release(nau8825);
                return -EINVAL;
        }
 
@@ -1312,8 +1333,6 @@ static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
        struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
        unsigned int ctrl1_val = 0, ctrl2_val = 0;
 
-       nau8825_sema_acquire(nau8825, 3 * HZ);
-
        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
        case SND_SOC_DAIFMT_CBM_CFM:
                ctrl2_val |= NAU8825_I2S_MS_MASTER;
@@ -1355,6 +1374,8 @@ static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
                return -EINVAL;
        }
 
+       nau8825_sema_acquire(nau8825, 3 * HZ);
+
        regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
                NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
                NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
@@ -1687,7 +1708,7 @@ static irqreturn_t nau8825_interrupt(int irq, void *data)
        } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
                if (nau8825_is_jack_inserted(regmap)) {
                        event |= nau8825_jack_insert(nau8825);
-                       if (!nau8825->xtalk_bypass && !nau8825->high_imped) {
+                       if (nau8825->xtalk_enable && !nau8825->high_imped) {
                                /* Apply the cross talk suppression in the
                                 * headset without high impedance.
                                 */
@@ -1701,12 +1722,15 @@ static irqreturn_t nau8825_interrupt(int irq, void *data)
                                        int ret;
                                        nau8825->xtalk_protect = true;
                                        ret = nau8825_sema_acquire(nau8825, 0);
-                                       if (ret < 0)
+                                       if (ret)
                                                nau8825->xtalk_protect = false;
                                }
                                /* Startup cross talk detection process */
-                               nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
-                               schedule_work(&nau8825->xtalk_work);
+                               if (nau8825->xtalk_protect) {
+                                       nau8825->xtalk_state =
+                                               NAU8825_XTALK_PREPARE;
+                                       schedule_work(&nau8825->xtalk_work);
+                               }
                        } else {
                                /* The cross talk suppression shouldn't apply
                                 * in the headset with high impedance. Thus,
@@ -1733,7 +1757,9 @@ static irqreturn_t nau8825_interrupt(int irq, void *data)
                        nau8825->xtalk_event_mask = event_mask;
                }
        } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
-               schedule_work(&nau8825->xtalk_work);
+               /* crosstalk detection enable and process on going */
+               if (nau8825->xtalk_enable && nau8825->xtalk_protect)
+                       schedule_work(&nau8825->xtalk_work);
                clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
        } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
                NAU8825_JACK_INSERTION_DETECTED) {
@@ -2382,7 +2408,7 @@ static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
        regcache_sync(nau8825->regmap);
        nau8825->xtalk_protect = true;
        ret = nau8825_sema_acquire(nau8825, 0);
-       if (ret < 0)
+       if (ret)
                nau8825->xtalk_protect = false;
        enable_irq(nau8825->irq);
 
@@ -2441,8 +2467,8 @@ static void nau8825_print_device_properties(struct nau8825 *nau8825)
                        nau8825->jack_insert_debounce);
        dev_dbg(dev, "jack-eject-debounce:  %d\n",
                        nau8825->jack_eject_debounce);
-       dev_dbg(dev, "crosstalk-bypass:     %d\n",
-                       nau8825->xtalk_bypass);
+       dev_dbg(dev, "crosstalk-enable:     %d\n",
+                       nau8825->xtalk_enable);
 }
 
 static int nau8825_read_device_properties(struct device *dev,
@@ -2507,8 +2533,8 @@ static int nau8825_read_device_properties(struct device *dev,
                &nau8825->jack_eject_debounce);
        if (ret)
                nau8825->jack_eject_debounce = 0;
-       nau8825->xtalk_bypass = device_property_read_bool(dev,
-               "nuvoton,crosstalk-bypass");
+       nau8825->xtalk_enable = device_property_read_bool(dev,
+               "nuvoton,crosstalk-enable");
 
        nau8825->mclk = devm_clk_get(dev, "mclk");
        if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
@@ -2569,6 +2595,7 @@ static int nau8825_i2c_probe(struct i2c_client *i2c,
         */
        nau8825->xtalk_state = NAU8825_XTALK_DONE;
        nau8825->xtalk_protect = false;
+       nau8825->xtalk_baktab_initialized = false;
        sema_init(&nau8825->xtalk_sem, 1);
        INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
 
index 8aee5c8647aee153f151ac09175dc3f6a9fd25da..f7e7321258825759d2adad0db15e84ced34f698e 100644 (file)
@@ -476,7 +476,8 @@ struct nau8825 {
        int xtalk_event_mask;
        bool xtalk_protect;
        int imp_rms[NAU8825_XTALK_IMM];
-       int xtalk_bypass;
+       int xtalk_enable;
+       bool xtalk_baktab_initialized; /* True if initialized. */
 };
 
 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
index affa7fb25dd9080b853672d9669d0820205443cf..949fc3a1d02578d4e718cb80c87af4263de72d9f 100644 (file)
  * GNU General Public License for more details.
  */
 
-#include <sound/soc.h>
-#include <linux/regmap.h>
-#include <linux/pm_runtime.h>
-
 #include "mt2701-afe-common.h"
 #include "mt2701-afe-clock-ctrl.h"
 
-static const char *aud_clks[MT2701_CLOCK_NUM] = {
-       [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
-       [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
-       [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
-       [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
-       [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
-       [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
-       [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
-       [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
-       [MT2701_AUD_APLL_SEL] = "top_apll_sel",
-       [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
-       [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
-       [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
-       [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
-       [MT2701_AUD_AUDPLL] = "top_audpll",
-       [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
-       [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
-       [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
-       [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
-       [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
-       [MT2701_AUD_CLK_26M] = "clk_26m",
-       [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
-       [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
-       [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
-       [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
-       [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
-       [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
-       [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
-       [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
-       [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
-       [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
-       [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
-       [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
-       [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
-       [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
-       [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
-       [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
-       [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
-       [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
-       [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
-       [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
-       [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
-       [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
-       [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
-       [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
+static const char *const base_clks[] = {
+       [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
+       [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
+       [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
+       [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
+       [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
+       [MT2701_AUDSYS_AFE] = "audio_afe_pd",
+       [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
+       [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
+       [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
 };
 
 int mt2701_init_clock(struct mtk_base_afe *afe)
 {
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
-       int i = 0;
-
-       for (i = 0; i < MT2701_CLOCK_NUM; i++) {
-               afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
-               if (IS_ERR(afe_priv->clocks[i])) {
-                       dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
-                                __func__, aud_clks[i]);
-                       return PTR_ERR(aud_clks[i]);
+       int i;
+
+       for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
+               afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
+               if (IS_ERR(afe_priv->base_ck[i])) {
+                       dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
+                       return PTR_ERR(afe_priv->base_ck[i]);
+               }
+       }
+
+       /* Get I2S related clocks */
+       for (i = 0; i < MT2701_I2S_NUM; i++) {
+               struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
+               char name[13];
+
+               snprintf(name, sizeof(name), "i2s%d_src_sel", i);
+               i2s_path->sel_ck = devm_clk_get(afe->dev, name);
+               if (IS_ERR(i2s_path->sel_ck)) {
+                       dev_err(afe->dev, "failed to get %s\n", name);
+                       return PTR_ERR(i2s_path->sel_ck);
+               }
+
+               snprintf(name, sizeof(name), "i2s%d_src_div", i);
+               i2s_path->div_ck = devm_clk_get(afe->dev, name);
+               if (IS_ERR(i2s_path->div_ck)) {
+                       dev_err(afe->dev, "failed to get %s\n", name);
+                       return PTR_ERR(i2s_path->div_ck);
+               }
+
+               snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
+               i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
+               if (IS_ERR(i2s_path->mclk_ck)) {
+                       dev_err(afe->dev, "failed to get %s\n", name);
+                       return PTR_ERR(i2s_path->mclk_ck);
+               }
+
+               snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
+               i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name);
+               if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) {
+                       dev_err(afe->dev, "failed to get %s\n", name);
+                       return PTR_ERR(i2s_path->hop_ck[I2S_OUT]);
+               }
+
+               snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
+               i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name);
+               if (IS_ERR(i2s_path->hop_ck[I2S_IN])) {
+                       dev_err(afe->dev, "failed to get %s\n", name);
+                       return PTR_ERR(i2s_path->hop_ck[I2S_IN]);
+               }
+
+               snprintf(name, sizeof(name), "asrc%d_out_ck", i);
+               i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
+               if (IS_ERR(i2s_path->asrco_ck)) {
+                       dev_err(afe->dev, "failed to get %s\n", name);
+                       return PTR_ERR(i2s_path->asrco_ck);
                }
        }
 
+       /* Some platforms may support BT path */
+       afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
+       if (IS_ERR(afe_priv->mrgif_ck)) {
+               if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
+                       return -EPROBE_DEFER;
+
+               afe_priv->mrgif_ck = NULL;
+       }
+
        return 0;
 }
 
-int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
+int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir)
 {
-       int ret = 0;
+       struct mt2701_afe_private *afe_priv = afe->platform_priv;
+       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
+       int ret;
 
-       ret = mt2701_turn_on_a1sys_clock(afe);
+       ret = clk_prepare_enable(i2s_path->asrco_ck);
        if (ret) {
-               dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
-                       __func__, ret);
+               dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
                return ret;
        }
 
-       ret = mt2701_turn_on_a2sys_clock(afe);
+       ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
        if (ret) {
-               dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n",
-                       __func__, ret);
-               mt2701_turn_off_a1sys_clock(afe);
-               return ret;
+               dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
+               goto err_hop_ck;
        }
 
-       ret = mt2701_turn_on_afe_clock(afe);
-       if (ret) {
-               dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
-                       __func__, ret);
-               mt2701_turn_off_a1sys_clock(afe);
-               mt2701_turn_off_a2sys_clock(afe);
-               return ret;
-       }
+       return 0;
 
-       regmap_update_bits(afe->regmap, ASYS_TOP_CON,
-                          AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
-                          AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
-       regmap_update_bits(afe->regmap, AFE_DAC_CON0,
-                          AFE_DAC_CON0_AFE_ON,
-                          AFE_DAC_CON0_AFE_ON);
-       regmap_write(afe->regmap, PWR2_TOP_CON,
-                    PWR2_TOP_CON_INIT_VAL);
-       regmap_write(afe->regmap, PWR1_ASM_CON1,
-                    PWR1_ASM_CON1_INIT_VAL);
-       regmap_write(afe->regmap, PWR2_ASM_CON1,
-                    PWR2_ASM_CON1_INIT_VAL);
+err_hop_ck:
+       clk_disable_unprepare(i2s_path->asrco_ck);
 
-       return 0;
+       return ret;
 }
 
-void mt2701_afe_disable_clock(struct mtk_base_afe *afe)
+void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir)
 {
-       mt2701_turn_off_afe_clock(afe);
-       mt2701_turn_off_a1sys_clock(afe);
-       mt2701_turn_off_a2sys_clock(afe);
-       regmap_update_bits(afe->regmap, ASYS_TOP_CON,
-                          AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
-       regmap_update_bits(afe->regmap, AFE_DAC_CON0,
-                          AFE_DAC_CON0_AFE_ON, 0);
+       struct mt2701_afe_private *afe_priv = afe->platform_priv;
+       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
+
+       clk_disable_unprepare(i2s_path->hop_ck[dir]);
+       clk_disable_unprepare(i2s_path->asrco_ck);
 }
 
-int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe)
+int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
 {
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
-       int ret = 0;
-
-       /* Set Mux */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
-               goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
-       }
-
-       ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
-                            afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_AUD_MUX1_SEL],
-                       aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
-               goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
-       }
-
-       /* Set Divider */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__,
-                       aud_clks[MT2701_AUD_AUD_MUX1_DIV],
-                       ret);
-               goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
-       }
-
-       ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
-                          MT2701_AUD_AUD_MUX1_DIV_RATE);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_AUD_MUX1_DIV],
-                       MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
-               goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
-       }
+       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
 
-       /* Enable clock gate */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
-               goto A1SYS_CLK_AUD_48K_ERR;
-       }
+       return clk_prepare_enable(i2s_path->mclk_ck);
+}
 
-       /* Enable infra audio */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
-               goto A1SYS_CLK_INFRA_ERR;
-       }
+void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
+{
+       struct mt2701_afe_private *afe_priv = afe->platform_priv;
+       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
 
-       return 0;
+       clk_disable_unprepare(i2s_path->mclk_ck);
+}
 
-A1SYS_CLK_INFRA_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-A1SYS_CLK_AUD_48K_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
-A1SYS_CLK_AUD_MUX1_DIV_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
-A1SYS_CLK_AUD_MUX1_SEL_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
+int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
+{
+       struct mt2701_afe_private *afe_priv = afe->platform_priv;
 
-       return ret;
+       return clk_prepare_enable(afe_priv->mrgif_ck);
 }
 
-void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe)
+void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
 {
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
 
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
+       clk_disable_unprepare(afe_priv->mrgif_ck);
 }
 
-int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe)
+static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
 {
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
-       int ret = 0;
+       int ret;
 
-       /* Set Mux */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
-               goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
-       }
+       /* Enable infra clock gate */
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
+       if (ret)
+               return ret;
 
-       ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL],
-                            afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_AUD_MUX2_SEL],
-                       aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
-               goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
-       }
+       /* Enable top a1sys clock gate */
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
+       if (ret)
+               goto err_a1sys;
 
-       /* Set Divider */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
-               goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
-       }
+       /* Enable top a2sys clock gate */
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
+       if (ret)
+               goto err_a2sys;
 
-       ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV],
-                          MT2701_AUD_AUD_MUX2_DIV_RATE);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_AUD_MUX2_DIV],
-                       MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
-               goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
-       }
+       /* Internal clock gates */
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
+       if (ret)
+               goto err_afe;
 
-       /* Enable clock gate */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
-               goto A2SYS_CLK_AUD_44K_ERR;
-       }
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
+       if (ret)
+               goto err_audio_a1sys;
 
-       /* Enable infra audio */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
-               goto A2SYS_CLK_INFRA_ERR;
-       }
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
+       if (ret)
+               goto err_audio_a2sys;
+
+       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
+       if (ret)
+               goto err_afe_conn;
 
        return 0;
 
-A2SYS_CLK_INFRA_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-A2SYS_CLK_AUD_44K_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
-A2SYS_CLK_AUD_MUX2_DIV_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
-A2SYS_CLK_AUD_MUX2_SEL_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
+err_afe_conn:
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
+err_audio_a2sys:
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
+err_audio_a1sys:
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
+err_afe:
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
+err_a2sys:
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
+err_a1sys:
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
 
        return ret;
 }
 
-void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe)
+static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
 {
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
 
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
+       clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
 }
 
-int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe)
+int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
 {
-       struct mt2701_afe_private *afe_priv = afe->platform_priv;
        int ret;
 
-       /* enable INFRA_SYS */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
-               goto AFE_AUD_INFRA_ERR;
-       }
-
-       /* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
-               goto AFE_AUD_AUDINTBUS_ERR;
-       }
-
-       ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
-                            afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_AUDINTBUS],
-                       aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
-               goto AFE_AUD_AUDINTBUS_ERR;
-       }
-
-       /* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
+       /* Enable audio system */
+       ret = mt2701_afe_enable_audsys(afe);
        if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret);
-               goto AFE_AUD_ASM_H_ERR;
-       }
-
-       ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
-                            afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_ASM_H_SEL],
-                       aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
-               goto AFE_AUD_ASM_H_ERR;
-       }
-
-       /* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
-       ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
-               goto AFE_AUD_ASM_M_ERR;
+               dev_err(afe->dev, "failed to enable audio system %d\n", ret);
+               return ret;
        }
 
-       ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL],
-                            afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]);
-       if (ret) {
-               dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
-                       aud_clks[MT2701_AUD_ASM_M_SEL],
-                       aud_clks[MT2701_AUD_UNIVPLL2_D4], ret);
-               goto AFE_AUD_ASM_M_ERR;
-       }
+       regmap_update_bits(afe->regmap, ASYS_TOP_CON,
+                          ASYS_TOP_CON_ASYS_TIMING_ON,
+                          ASYS_TOP_CON_ASYS_TIMING_ON);
+       regmap_update_bits(afe->regmap, AFE_DAC_CON0,
+                          AFE_DAC_CON0_AFE_ON,
+                          AFE_DAC_CON0_AFE_ON);
 
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
-                          AUDIO_TOP_CON0_PDN_AFE, 0);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
-                          AUDIO_TOP_CON0_PDN_APLL_CK, 0);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_A1SYS, 0);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_A2SYS, 0);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
+       /* Configure ASRC */
+       regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
+       regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
 
        return 0;
-
-AFE_AUD_ASM_M_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
-AFE_AUD_ASM_H_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
-AFE_AUD_AUDINTBUS_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
-AFE_AUD_INFRA_ERR:
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-
-       return ret;
 }
 
-void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe)
+int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
 {
-       struct mt2701_afe_private *afe_priv = afe->platform_priv;
+       regmap_update_bits(afe->regmap, ASYS_TOP_CON,
+                          ASYS_TOP_CON_ASYS_TIMING_ON, 0);
+       regmap_update_bits(afe->regmap, AFE_DAC_CON0,
+                          AFE_DAC_CON0_AFE_ON, 0);
+
+       mt2701_afe_disable_audsys(afe);
 
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
-       clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
-
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
-                          AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
-                          AUDIO_TOP_CON0_PDN_APLL_CK,
-                          AUDIO_TOP_CON0_PDN_APLL_CK);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_A1SYS,
-                          AUDIO_TOP_CON4_PDN_A1SYS);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_A2SYS,
-                          AUDIO_TOP_CON4_PDN_A2SYS);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_AFE_CONN,
-                          AUDIO_TOP_CON4_PDN_AFE_CONN);
+       return 0;
 }
 
 void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
                               int mclk)
 {
-       struct mt2701_afe_private *afe_priv = afe->platform_priv;
+       struct mt2701_afe_private *priv = afe->platform_priv;
+       struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
        int ret;
-       int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
-       int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
 
-       /* Set MCLK Kx_SRC_SEL(domain) */
-       ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]);
-       if (ret)
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[aud_src_clk_id], ret);
-
-       if (domain == 0) {
-               ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
-                                    afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
-               if (ret)
-                       dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
-                               __func__, aud_clks[aud_src_clk_id],
-                               aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
-       } else {
-               ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
-                                    afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
-               if (ret)
-                       dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
-                               __func__, aud_clks[aud_src_clk_id],
-                               aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
-       }
-       clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
+       /* Set mclk source */
+       if (domain == 0)
+               ret = clk_set_parent(i2s_path->sel_ck,
+                                    priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
+       else
+               ret = clk_set_parent(i2s_path->sel_ck,
+                                    priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
 
-       /* Set MCLK Kx_SRC_DIV(divider) */
-       ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
        if (ret)
-               dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
-                       __func__, aud_clks[aud_src_div_id], ret);
+               dev_err(afe->dev, "failed to set domain%d mclk source %d\n",
+                       domain, ret);
 
-       ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk);
+       /* Set mclk divider */
+       ret = clk_set_rate(i2s_path->div_ck, mclk);
        if (ret)
-               dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__,
-                       aud_clks[aud_src_div_id], mclk, ret);
-       clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
+               dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
 }
-
-MODULE_DESCRIPTION("MT2701 afe clock control");
-MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
-MODULE_LICENSE("GPL v2");
index 6497d570cf097df78ef529157f3009e447b70213..15417d9d6597879d9b567f11c3fa0179267747f1 100644 (file)
@@ -21,16 +21,15 @@ struct mtk_base_afe;
 
 int mt2701_init_clock(struct mtk_base_afe *afe);
 int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
-void mt2701_afe_disable_clock(struct mtk_base_afe *afe);
+int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
 
-int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe);
-void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe);
+int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
+void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
+int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
+void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
 
-int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe);
-void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe);
-
-int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
-void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
+int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
+void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
 
 void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
                               int mclk);
index c19430e98adf172bd71476294030fef3e4a75f76..ae8ddeacfbfe25584c2e9c6a2e6133a959f754bf 100644 (file)
@@ -16,6 +16,7 @@
 
 #ifndef _MT_2701_AFE_COMMON_H_
 #define _MT_2701_AFE_COMMON_H_
+
 #include <sound/soc.h>
 #include <linux/clk.h>
 #include <linux/regmap.h>
 #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
 #define MT2701_PLL_DOMAIN_0_RATE       98304000
 #define MT2701_PLL_DOMAIN_1_RATE       90316800
-#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2)
-#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
-
-enum {
-       MT2701_I2S_1,
-       MT2701_I2S_2,
-       MT2701_I2S_3,
-       MT2701_I2S_4,
-       MT2701_I2S_NUM,
-};
+#define MT2701_I2S_NUM 4
 
 enum {
        MT2701_MEMIF_DL1,
@@ -62,60 +54,23 @@ enum {
 };
 
 enum {
-       MT2701_IRQ_ASYS_START,
-       MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
+       MT2701_IRQ_ASYS_IRQ1,
        MT2701_IRQ_ASYS_IRQ2,
        MT2701_IRQ_ASYS_IRQ3,
        MT2701_IRQ_ASYS_END,
 };
 
-/* 2701 clock def */
-enum audio_system_clock_type {
-       MT2701_AUD_INFRA_SYS_AUDIO,
-       MT2701_AUD_AUD_MUX1_SEL,
-       MT2701_AUD_AUD_MUX2_SEL,
-       MT2701_AUD_AUD_MUX1_DIV,
-       MT2701_AUD_AUD_MUX2_DIV,
-       MT2701_AUD_AUD_48K_TIMING,
-       MT2701_AUD_AUD_44K_TIMING,
-       MT2701_AUD_AUDPLL_MUX_SEL,
-       MT2701_AUD_APLL_SEL,
-       MT2701_AUD_AUD1PLL_98M,
-       MT2701_AUD_AUD2PLL_90M,
-       MT2701_AUD_HADDS2PLL_98M,
-       MT2701_AUD_HADDS2PLL_294M,
-       MT2701_AUD_AUDPLL,
-       MT2701_AUD_AUDPLL_D4,
-       MT2701_AUD_AUDPLL_D8,
-       MT2701_AUD_AUDPLL_D16,
-       MT2701_AUD_AUDPLL_D24,
-       MT2701_AUD_AUDINTBUS,
-       MT2701_AUD_CLK_26M,
-       MT2701_AUD_SYSPLL1_D4,
-       MT2701_AUD_AUD_K1_SRC_SEL,
-       MT2701_AUD_AUD_K2_SRC_SEL,
-       MT2701_AUD_AUD_K3_SRC_SEL,
-       MT2701_AUD_AUD_K4_SRC_SEL,
-       MT2701_AUD_AUD_K5_SRC_SEL,
-       MT2701_AUD_AUD_K6_SRC_SEL,
-       MT2701_AUD_AUD_K1_SRC_DIV,
-       MT2701_AUD_AUD_K2_SRC_DIV,
-       MT2701_AUD_AUD_K3_SRC_DIV,
-       MT2701_AUD_AUD_K4_SRC_DIV,
-       MT2701_AUD_AUD_K5_SRC_DIV,
-       MT2701_AUD_AUD_K6_SRC_DIV,
-       MT2701_AUD_AUD_I2S1_MCLK,
-       MT2701_AUD_AUD_I2S2_MCLK,
-       MT2701_AUD_AUD_I2S3_MCLK,
-       MT2701_AUD_AUD_I2S4_MCLK,
-       MT2701_AUD_AUD_I2S5_MCLK,
-       MT2701_AUD_AUD_I2S6_MCLK,
-       MT2701_AUD_ASM_M_SEL,
-       MT2701_AUD_ASM_H_SEL,
-       MT2701_AUD_UNIVPLL2_D4,
-       MT2701_AUD_UNIVPLL2_D2,
-       MT2701_AUD_SYSPLL_D5,
-       MT2701_CLOCK_NUM
+enum audio_base_clock {
+       MT2701_INFRA_SYS_AUDIO,
+       MT2701_TOP_AUD_MCLK_SRC0,
+       MT2701_TOP_AUD_MCLK_SRC1,
+       MT2701_TOP_AUD_A1SYS,
+       MT2701_TOP_AUD_A2SYS,
+       MT2701_AUDSYS_AFE,
+       MT2701_AUDSYS_AFE_CONN,
+       MT2701_AUDSYS_A1SYS,
+       MT2701_AUDSYS_A2SYS,
+       MT2701_BASE_CLK_NUM,
 };
 
 static const unsigned int mt2701_afe_backup_list[] = {
@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = {
        AFE_MEMIF_PBUF_SIZE,
 };
 
-struct snd_pcm_substream;
-struct mtk_base_irq_data;
-
 struct mt2701_i2s_data {
        int i2s_ctrl_reg;
-       int i2s_pwn_shift;
        int i2s_asrc_fs_shift;
        int i2s_asrc_fs_mask;
 };
@@ -160,12 +111,18 @@ struct mt2701_i2s_path {
        int mclk_rate;
        int on[I2S_DIR_NUM];
        int occupied[I2S_DIR_NUM];
-       const struct mt2701_i2s_data *i2s_data[2];
+       const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
+       struct clk *hop_ck[I2S_DIR_NUM];
+       struct clk *sel_ck;
+       struct clk *div_ck;
+       struct clk *mclk_ck;
+       struct clk *asrco_ck;
 };
 
 struct mt2701_afe_private {
-       struct clk *clocks[MT2701_CLOCK_NUM];
        struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
+       struct clk *base_ck[MT2701_BASE_CLK_NUM];
+       struct clk *mrgif_ck;
        bool mrg_enable[MT2701_STREAM_DIR_NUM];
 };
 
index a7362d1cda1b6a26cd391a7b0790c07d03fcde15..5bc4e00a4a297728e3afcc54a9a4018d6e04eec6 100644 (file)
 
 #include <linux/delay.h>
 #include <linux/module.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/pm_runtime.h>
-#include <sound/soc.h>
 
 #include "mt2701-afe-common.h"
-
 #include "mt2701-afe-clock-ctrl.h"
 #include "../common/mtk-afe-platform-driver.h"
 #include "../common/mtk-afe-fe-dai.h"
 
-#define AFE_IRQ_STATUS_BITS    0xff
-
 static const struct snd_pcm_hardware mt2701_afe_hardware = {
        .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
                | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
@@ -97,40 +94,26 @@ static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
-       struct mt2701_afe_private *afe_priv = afe->platform_priv;
        int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
-       int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
-       int ret = 0;
 
        if (i2s_num < 0)
                return i2s_num;
 
-       /* enable mclk */
-       ret = clk_prepare_enable(afe_priv->clocks[clk_num]);
-       if (ret)
-               dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n",
-                       i2s_num);
-
-       return ret;
+       return mt2701_afe_enable_mclk(afe, i2s_num);
 }
 
 static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
                                        struct snd_soc_dai *dai,
+                                       int i2s_num,
                                        int dir_invert)
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
-       int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
-       struct mt2701_i2s_path *i2s_path;
+       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
        const struct mt2701_i2s_data *i2s_data;
        int stream_dir = substream->stream;
 
-       if (i2s_num < 0)
-               return i2s_num;
-
-       i2s_path = &afe_priv->i2s_path[i2s_num];
-
        if (dir_invert) {
                if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
                        stream_dir = SNDRV_PCM_STREAM_CAPTURE;
@@ -151,9 +134,9 @@ static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
        /* disable i2s */
        regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
                           ASYS_I2S_CON_I2S_EN, 0);
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          1 << i2s_data->i2s_pwn_shift,
-                          1 << i2s_data->i2s_pwn_shift);
+
+       mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
+
        return 0;
 }
 
@@ -165,7 +148,6 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
        int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
        struct mt2701_i2s_path *i2s_path;
-       int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
 
        if (i2s_num < 0)
                return;
@@ -177,37 +159,32 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
        else
                goto I2S_UNSTART;
 
-       mt2701_afe_i2s_path_shutdown(substream, dai, 0);
+       mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
 
        /* need to disable i2s-out path when disable i2s-in */
        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-               mt2701_afe_i2s_path_shutdown(substream, dai, 1);
+               mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
 
 I2S_UNSTART:
        /* disable mclk */
-       clk_disable_unprepare(afe_priv->clocks[clk_num]);
+       mt2701_afe_disable_mclk(afe, i2s_num);
 }
 
 static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
                                          struct snd_soc_dai *dai,
+                                         int i2s_num,
                                          int dir_invert)
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
-       int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
-       struct mt2701_i2s_path *i2s_path;
+       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
        const struct mt2701_i2s_data *i2s_data;
        struct snd_pcm_runtime * const runtime = substream->runtime;
        int reg, fs, w_len = 1; /* now we support bck 64bits only */
        int stream_dir = substream->stream;
        unsigned int mask = 0, val = 0;
 
-       if (i2s_num < 0)
-               return i2s_num;
-
-       i2s_path = &afe_priv->i2s_path[i2s_num];
-
        if (dir_invert) {
                if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
                        stream_dir = SNDRV_PCM_STREAM_CAPTURE;
@@ -251,9 +228,7 @@ static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
                           fs << i2s_data->i2s_asrc_fs_shift);
 
        /* enable i2s */
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          1 << i2s_data->i2s_pwn_shift,
-                          0 << i2s_data->i2s_pwn_shift);
+       mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
 
        /* reset i2s hw status before enable */
        regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
@@ -300,13 +275,13 @@ static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
        mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
 
        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-               mt2701_i2s_path_prepare_enable(substream, dai, 0);
+               mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
        } else {
                /* need to enable i2s-out path when enable i2s-in */
                /* prepare for another direction "out" */
-               mt2701_i2s_path_prepare_enable(substream, dai, 1);
+               mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
                /* prepare for "in" */
-               mt2701_i2s_path_prepare_enable(substream, dai, 0);
+               mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
        }
 
        return 0;
@@ -339,9 +314,11 @@ static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
        struct mt2701_afe_private *afe_priv = afe->platform_priv;
+       int ret;
 
-       regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                          AUDIO_TOP_CON4_PDN_MRGIF, 0);
+       ret = mt2701_enable_btmrg_clk(afe);
+       if (ret)
+               return ret;
 
        afe_priv->mrg_enable[substream->stream] = 1;
        return 0;
@@ -406,9 +383,7 @@ static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
                                   AFE_MRGIF_CON_MRG_EN, 0);
                regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
                                   AFE_MRGIF_CON_MRG_I2S_EN, 0);
-               regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
-                                  AUDIO_TOP_CON4_PDN_MRGIF,
-                                  AUDIO_TOP_CON4_PDN_MRGIF);
+               mt2701_disable_btmrg_clk(afe);
        }
        afe_priv->mrg_enable[substream->stream] = 0;
 }
@@ -574,7 +549,6 @@ static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
        .hw_free        = mtk_afe_fe_hw_free,
        .prepare        = mtk_afe_fe_prepare,
        .trigger        = mtk_afe_fe_trigger,
-
 };
 
 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
@@ -915,31 +889,6 @@ static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
                                    PWR2_TOP_CON, 19, 1, 0),
 };
 
-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = {
-       SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1,
-                                   1),
-};
-
-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = {
-       SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1,
-                                   1),
-};
-
-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = {
-       SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1,
-                                   1),
-};
-
-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = {
-       SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1,
-                                   1),
-};
-
-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = {
-       SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1,
-                                   1),
-};
-
 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
        /* inter-connections */
        SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -999,19 +948,6 @@ static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
        SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
                           mt2701_afe_multi_ch_out_i2s3,
                           ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
-
-       SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0,
-                          mt2701_afe_multi_ch_out_asrc0,
-                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)),
-       SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0,
-                          mt2701_afe_multi_ch_out_asrc1,
-                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)),
-       SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0,
-                          mt2701_afe_multi_ch_out_asrc2,
-                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)),
-       SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0,
-                          mt2701_afe_multi_ch_out_asrc3,
-                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)),
 };
 
 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
@@ -1021,7 +957,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
 
        {"I2S0 Playback", NULL, "O15"},
        {"I2S0 Playback", NULL, "O16"},
-
        {"I2S1 Playback", NULL, "O17"},
        {"I2S1 Playback", NULL, "O18"},
        {"I2S2 Playback", NULL, "O19"},
@@ -1038,7 +973,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
 
        {"I00", NULL, "I2S0 Capture"},
        {"I01", NULL, "I2S0 Capture"},
-
        {"I02", NULL, "I2S1 Capture"},
        {"I03", NULL, "I2S1 Capture"},
        /* I02,03 link to UL2, also need to open I2S0 */
@@ -1046,15 +980,10 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
 
        {"I26", NULL, "BT Capture"},
 
-       {"ASRC_O0", "Asrc0 out Switch", "DLM"},
-       {"ASRC_O1", "Asrc1 out Switch", "DLM"},
-       {"ASRC_O2", "Asrc2 out Switch", "DLM"},
-       {"ASRC_O3", "Asrc3 out Switch", "DLM"},
-
-       {"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"},
-       {"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"},
-       {"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"},
-       {"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"},
+       {"I12I13", "Multich I2S0 Out Switch", "DLM"},
+       {"I14I15", "Multich I2S1 Out Switch", "DLM"},
+       {"I16I17", "Multich I2S2 Out Switch", "DLM"},
+       {"I18I19", "Multich I2S3 Out Switch", "DLM"},
 
        { "I12", NULL, "I12I13" },
        { "I13", NULL, "I12I13" },
@@ -1079,7 +1008,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
        { "O21", "I18 Switch", "I18" },
        { "O22", "I19 Switch", "I19" },
        { "O31", "I35 Switch", "I35" },
-
 };
 
 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
@@ -1386,14 +1314,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
        {
                {
                        .i2s_ctrl_reg = ASYS_I2SO1_CON,
-                       .i2s_pwn_shift = 6,
                        .i2s_asrc_fs_shift = 0,
                        .i2s_asrc_fs_mask = 0x1f,
 
                },
                {
                        .i2s_ctrl_reg = ASYS_I2SIN1_CON,
-                       .i2s_pwn_shift = 0,
                        .i2s_asrc_fs_shift = 0,
                        .i2s_asrc_fs_mask = 0x1f,
 
@@ -1402,14 +1328,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
        {
                {
                        .i2s_ctrl_reg = ASYS_I2SO2_CON,
-                       .i2s_pwn_shift = 7,
                        .i2s_asrc_fs_shift = 5,
                        .i2s_asrc_fs_mask = 0x1f,
 
                },
                {
                        .i2s_ctrl_reg = ASYS_I2SIN2_CON,
-                       .i2s_pwn_shift = 1,
                        .i2s_asrc_fs_shift = 5,
                        .i2s_asrc_fs_mask = 0x1f,
 
@@ -1418,14 +1342,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
        {
                {
                        .i2s_ctrl_reg = ASYS_I2SO3_CON,
-                       .i2s_pwn_shift = 8,
                        .i2s_asrc_fs_shift = 10,
                        .i2s_asrc_fs_mask = 0x1f,
 
                },
                {
                        .i2s_ctrl_reg = ASYS_I2SIN3_CON,
-                       .i2s_pwn_shift = 2,
                        .i2s_asrc_fs_shift = 10,
                        .i2s_asrc_fs_mask = 0x1f,
 
@@ -1434,14 +1356,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
        {
                {
                        .i2s_ctrl_reg = ASYS_I2SO4_CON,
-                       .i2s_pwn_shift = 9,
                        .i2s_asrc_fs_shift = 15,
                        .i2s_asrc_fs_mask = 0x1f,
 
                },
                {
                        .i2s_ctrl_reg = ASYS_I2SIN4_CON,
-                       .i2s_pwn_shift = 3,
                        .i2s_asrc_fs_shift = 15,
                        .i2s_asrc_fs_mask = 0x1f,
 
@@ -1449,14 +1369,6 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
        },
 };
 
-static const struct regmap_config mt2701_afe_regmap_config = {
-       .reg_bits = 32,
-       .reg_stride = 4,
-       .val_bits = 32,
-       .max_register = AFE_END_ADDR,
-       .cache_type = REGCACHE_NONE,
-};
-
 static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
 {
        int id;
@@ -1483,8 +1395,7 @@ static int mt2701_afe_runtime_suspend(struct device *dev)
 {
        struct mtk_base_afe *afe = dev_get_drvdata(dev);
 
-       mt2701_afe_disable_clock(afe);
-       return 0;
+       return mt2701_afe_disable_clock(afe);
 }
 
 static int mt2701_afe_runtime_resume(struct device *dev)
@@ -1496,21 +1407,22 @@ static int mt2701_afe_runtime_resume(struct device *dev)
 
 static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
 {
+       struct snd_soc_component *component;
        struct mtk_base_afe *afe;
        struct mt2701_afe_private *afe_priv;
-       struct resource *res;
        struct device *dev;
        int i, irq_id, ret;
 
        afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
        if (!afe)
                return -ENOMEM;
+
        afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
                                          GFP_KERNEL);
        if (!afe->platform_priv)
                return -ENOMEM;
-       afe_priv = afe->platform_priv;
 
+       afe_priv = afe->platform_priv;
        afe->dev = &pdev->dev;
        dev = afe->dev;
 
@@ -1527,17 +1439,11 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
                return ret;
        }
 
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-       afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
-
-       if (IS_ERR(afe->base_addr))
-               return PTR_ERR(afe->base_addr);
-
-       afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
-               &mt2701_afe_regmap_config);
-       if (IS_ERR(afe->regmap))
+       afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
+       if (IS_ERR(afe->regmap)) {
+               dev_err(dev, "could not get regmap from parent\n");
                return PTR_ERR(afe->regmap);
+       }
 
        mutex_init(&afe->irq_alloc_lock);
 
@@ -1545,7 +1451,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
        afe->memif_size = MT2701_MEMIF_NUM;
        afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
                                  GFP_KERNEL);
-
        if (!afe->memif)
                return -ENOMEM;
 
@@ -1558,7 +1463,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
        afe->irqs_size = MT2701_IRQ_ASYS_END;
        afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
                                 GFP_KERNEL);
-
        if (!afe->irqs)
                return -ENOMEM;
 
@@ -1573,10 +1477,15 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
                        = &mt2701_i2s_data[i][I2S_IN];
        }
 
+       component = kzalloc(sizeof(*component), GFP_KERNEL);
+       if (!component)
+               return -ENOMEM;
+
+       component->regmap = afe->regmap;
+
        afe->mtk_afe_hardware = &mt2701_afe_hardware;
        afe->memif_fs = mt2701_memif_fs;
        afe->irq_fs = mt2701_irq_fs;
-
        afe->reg_back_up_list = mt2701_afe_backup_list;
        afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
        afe->runtime_resume = mt2701_afe_runtime_resume;
@@ -1586,7 +1495,7 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
        ret = mt2701_init_clock(afe);
        if (ret) {
                dev_err(dev, "init clock error\n");
-               return ret;
+               goto err_init_clock;
        }
 
        platform_set_drvdata(pdev, afe);
@@ -1605,10 +1514,10 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
                goto err_platform;
        }
 
-       ret = snd_soc_register_component(&pdev->dev,
-                                        &mt2701_afe_pcm_dai_component,
-                                        mt2701_afe_pcm_dais,
-                                        ARRAY_SIZE(mt2701_afe_pcm_dais));
+       ret = snd_soc_add_component(dev, component,
+                                   &mt2701_afe_pcm_dai_component,
+                                   mt2701_afe_pcm_dais,
+                                   ARRAY_SIZE(mt2701_afe_pcm_dais));
        if (ret) {
                dev_warn(dev, "err_dai_component\n");
                goto err_dai_component;
@@ -1622,6 +1531,8 @@ err_platform:
        pm_runtime_put_sync(dev);
 err_pm_disable:
        pm_runtime_disable(dev);
+err_init_clock:
+       kfree(component);
 
        return ret;
 }
@@ -1667,4 +1578,3 @@ module_platform_driver(mt2701_afe_pcm_driver);
 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
 MODULE_LICENSE("GPL v2");
-
index bb62b1c55957201e5952b4ea72a7932cd11bd927..18e676974f22cff17d41edb9ce456d605ef9450e 100644 (file)
 #ifndef _MT2701_REG_H_
 #define _MT2701_REG_H_
 
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/pm_runtime.h>
-#include <sound/soc.h>
-#include "mt2701-afe-common.h"
-
-/*****************************************************************************
- *                  R E G I S T E R       D E F I N I T I O N
- *****************************************************************************/
 #define AUDIO_TOP_CON0 0x0000
 #define AUDIO_TOP_CON4 0x0010
 #define AUDIO_TOP_CON5 0x0014
 #define AFE_DAI_BASE 0x1370
 #define AFE_DAI_CUR 0x137c
 
-/* AUDIO_TOP_CON0 (0x0000) */
-#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON  (0x3 << 0)
-#define AUDIO_TOP_CON0_PDN_AFE         (0x1 << 2)
-#define AUDIO_TOP_CON0_PDN_APLL_CK     (0x1 << 23)
-
-/* AUDIO_TOP_CON4 (0x0010) */
-#define AUDIO_TOP_CON4_I2SO1_PWN       (0x1 << 6)
-#define AUDIO_TOP_CON4_PDN_A1SYS       (0x1 << 21)
-#define AUDIO_TOP_CON4_PDN_A2SYS       (0x1 << 22)
-#define AUDIO_TOP_CON4_PDN_AFE_CONN    (0x1 << 23)
-#define AUDIO_TOP_CON4_PDN_MRGIF       (0x1 << 25)
-
 /* AFE_DAIBT_CON0 (0x001c) */
 #define AFE_DAIBT_CON0_DAIBT_EN                (0x1 << 0)
 #define AFE_DAIBT_CON0_BT_FUNC_EN      (0x1 << 1)
 #define AFE_MRGIF_CON_I2S_MODE_MASK    (0xf << 20)
 #define AFE_MRGIF_CON_I2S_MODE_32K     (0x4 << 20)
 
-/* ASYS_I2SO1_CON (0x061c) */
-#define ASYS_I2SO1_CON_FS              (0x1f << 8)
-#define ASYS_I2SO1_CON_FS_SET(x)       ((x) << 8)
-#define ASYS_I2SO1_CON_MULTI_CH                (0x1 << 16)
-#define ASYS_I2SO1_CON_SIDEGEN         (0x1 << 30)
-#define ASYS_I2SO1_CON_I2S_EN          (0x1 << 0)
-/* 0:EIAJ 1:I2S */
-#define ASYS_I2SO1_CON_I2S_MODE                (0x1 << 3)
-#define ASYS_I2SO1_CON_WIDE_MODE       (0x1 << 1)
-#define ASYS_I2SO1_CON_WIDE_MODE_SET(x)        ((x) << 1)
-
-/* PWR2_TOP_CON (0x0634) */
-#define PWR2_TOP_CON_INIT_VAL          (0xffe1ffff)
-
-/* ASYS_IRQ_CLR (0x07c0) */
-#define ASYS_IRQ_CLR_ALL               (0xffffffff)
+/* ASYS_TOP_CON (0x0600) */
+#define ASYS_TOP_CON_ASYS_TIMING_ON            (0x3 << 0)
 
 /* PWR2_ASM_CON1 (0x1070) */
 #define PWR2_ASM_CON1_INIT_VAL         (0x492492)
 #define ASYS_I2S_CON_WIDE_MODE_SET(x)  ((x) << 1)
 #define ASYS_I2S_IN_PHASE_FIX          (0x1 << 31)
 
-#define AFE_END_ADDR 0x15e0
 #endif
index 99c15219dbc819404a14c4ea322f1a4eaf3ade45..5a9a5482976ec88b152843b8af9d9625470dc191 100644 (file)
@@ -37,8 +37,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = {
        {"Sub DMIC1R", NULL, "Int Mic"},
        {"Headphone", NULL, "HPOL"},
        {"Headphone", NULL, "HPOR"},
-       {"Headset Mic", NULL, "micbias1"},
-       {"Headset Mic", NULL, "micbias2"},
        {"IN1P", NULL, "Headset Mic"},
        {"IN1N", NULL, "Headset Mic"},
 };
index 42de84ca8c8443450d049f4d22d2f249f5d3fa3b..b7248085ca042387a86fc215eee7d0df8b6a8945 100644 (file)
@@ -40,8 +40,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = {
        {"Headphone", NULL, "HPOL"},
        {"Headphone", NULL, "HPOR"},
        {"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650  */
-       {"Headset Mic", NULL, "micbias1"},
-       {"Headset Mic", NULL, "micbias2"},
        {"IN1P", NULL, "Headset Mic"},
        {"IN1N", NULL, "Headset Mic"},
        {"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650  */
index e69c141d8ed4c9a72d18187d1701c903cec41331..40ebefd625c1e4370e1f6527e3003b03fac4d34d 100644 (file)
@@ -51,8 +51,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = {
        {"DMIC R1", NULL, "Int Mic"},
        {"Headphone", NULL, "HPOL"},
        {"Headphone", NULL, "HPOR"},
-       {"Headset Mic", NULL, "micbias1"},
-       {"Headset Mic", NULL, "micbias2"},
        {"IN1P", NULL, "Headset Mic"},
        {"IN1N", NULL, "Headset Mic"},
 };
index b6615affe5718b379df657f401cf34eeddc08dd1..81b09d740ed96ee39eeed88705305d46051c45da 100644 (file)
@@ -67,7 +67,7 @@ static unsigned short nuc900_ac97_read(struct snd_ac97 *ac97,
 
        /* polling the AC_R_FINISH */
        while (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_R_FINISH)
-                                                               && timeout--)
+                                                               && --timeout)
                mdelay(1);
 
        if (!timeout) {
@@ -121,7 +121,7 @@ static void nuc900_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
 
        /* polling the AC_W_FINISH */
        while ((AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_W_FINISH)
-                                                               && timeout--)
+                                                               && --timeout)
                mdelay(1);
 
        if (!timeout)
@@ -345,11 +345,10 @@ static int nuc900_ac97_drvprobe(struct platform_device *pdev)
                goto out;
        }
 
-       nuc900_audio->irq_num = platform_get_irq(pdev, 0);
-       if (!nuc900_audio->irq_num) {
-               ret = -EBUSY;
+       ret = platform_get_irq(pdev, 0);
+       if (ret < 0)
                goto out;
-       }
+       nuc900_audio->irq_num = ret;
 
        nuc900_ac97_data = nuc900_audio;