Merge branch 'clk-fixes' into clk-next
authorMichael Turquette <mturquette@linaro.org>
Tue, 25 Nov 2014 01:45:33 +0000 (17:45 -0800)
committerMichael Turquette <mturquette@linaro.org>
Tue, 25 Nov 2014 01:45:33 +0000 (17:45 -0800)
58 files changed:
Documentation/devicetree/bindings/clock/exynos4415-clock.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/exynos7-clock.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/marvell,mmp2.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/marvell,pxa168.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/marvell,pxa910.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
MAINTAINERS
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/mmp2-brownstone.dts
arch/arm/boot/dts/mmp2.dtsi
arch/arm/boot/dts/pxa168-aspenite.dts
arch/arm/boot/dts/pxa168.dtsi
arch/arm/boot/dts/pxa910-dkb.dts
arch/arm/boot/dts/pxa910.dtsi
arch/arm/mach-mmp/Kconfig
arch/arm/mach-mmp/mmp-dt.c
arch/arm/mach-mmp/mmp2-dt.c
drivers/clk/clk-mux.c
drivers/clk/clk.c
drivers/clk/hisilicon/clk-hi3620.c
drivers/clk/mmp/Makefile
drivers/clk/mmp/clk-frac.c
drivers/clk/mmp/clk-gate.c [new file with mode: 0644]
drivers/clk/mmp/clk-mix.c [new file with mode: 0644]
drivers/clk/mmp/clk-mmp2.c
drivers/clk/mmp/clk-of-mmp2.c [new file with mode: 0644]
drivers/clk/mmp/clk-of-pxa168.c [new file with mode: 0644]
drivers/clk/mmp/clk-of-pxa910.c [new file with mode: 0644]
drivers/clk/mmp/clk-pxa168.c
drivers/clk/mmp/clk-pxa910.c
drivers/clk/mmp/clk.c [new file with mode: 0644]
drivers/clk/mmp/clk.h
drivers/clk/mmp/reset.c [new file with mode: 0644]
drivers/clk/mmp/reset.h [new file with mode: 0644]
drivers/clk/pxa/Makefile
drivers/clk/pxa/clk-pxa.c
drivers/clk/pxa/clk-pxa.h
drivers/clk/pxa/clk-pxa25x.c [new file with mode: 0644]
drivers/clk/pxa/clk-pxa27x.c
drivers/clk/rockchip/clk-rk3188.c
drivers/clk/rockchip/clk-rk3288.c
drivers/clk/rockchip/clk.c
drivers/clk/rockchip/clk.h
drivers/clk/samsung/Makefile
drivers/clk/samsung/clk-exynos4415.c [new file with mode: 0644]
drivers/clk/samsung/clk-exynos5260.c
drivers/clk/samsung/clk-exynos7.c [new file with mode: 0644]
drivers/clk/samsung/clk-pll.c
drivers/clk/samsung/clk-pll.h
drivers/clk/samsung/clk.c
drivers/clk/samsung/clk.h
drivers/clk/shmobile/clk-div6.c
include/dt-bindings/clock/exynos4415.h [new file with mode: 0644]
include/dt-bindings/clock/exynos7-clk.h [new file with mode: 0644]
include/dt-bindings/clock/marvell,mmp2.h [new file with mode: 0644]
include/dt-bindings/clock/marvell,pxa168.h [new file with mode: 0644]
include/dt-bindings/clock/marvell,pxa910.h [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
new file mode 100644 (file)
index 0000000..847d98b
--- /dev/null
@@ -0,0 +1,38 @@
+* Samsung Exynos4415 Clock Controller
+
+The Exynos4415 clock controller generates and supplies clock to various
+consumer devices within the Exynos4415 SoC.
+
+Required properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4415-cmu" - for the main system clocks controller
+    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
+  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
+    Controller (DMC) domain clock controller.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4415.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+       cmu: clock-controller@10030000 {
+               compatible = "samsung,exynos4415-cmu";
+               reg = <0x10030000 0x18000>;
+               #clock-cells = <1>;
+       };
+
+       cmu-dmc: clock-controller@105C0000 {
+               compatible = "samsung,exynos4415-cmu-dmc";
+               reg = <0x105C0000 0x3000>;
+               #clock-cells = <1>;
+       };
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644 (file)
index 0000000..6d3d5f8
--- /dev/null
@@ -0,0 +1,93 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+       compatible strings to indicate the clock controller
+       functionality.
+
+       - "samsung,exynos7-clock-topc"
+       - "samsung,exynos7-clock-top0"
+       - "samsung,exynos7-clock-top1"
+       - "samsung,exynos7-clock-ccore"
+       - "samsung,exynos7-clock-peric0"
+       - "samsung,exynos7-clock-peric1"
+       - "samsung,exynos7-clock-peris"
+       - "samsung,exynos7-clock-fsys0"
+       - "samsung,exynos7-clock-fsys1"
+
+ - reg: physical base address of the controller and the length of
+       memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+       the given clock controller. Please refer the next section to
+       find the input clocks for a given controller.
+
+- clock-names: list of names of clocks which are fed as the input
+       to the given clock controller.
+
+Input clocks for top0 clock controller:
+       - fin_pll
+       - dout_sclk_bus0_pll
+       - dout_sclk_bus1_pll
+       - dout_sclk_cc_pll
+       - dout_sclk_mfc_pll
+
+Input clocks for top1 clock controller:
+       - fin_pll
+       - dout_sclk_bus0_pll
+       - dout_sclk_bus1_pll
+       - dout_sclk_cc_pll
+       - dout_sclk_mfc_pll
+
+Input clocks for ccore clock controller:
+       - fin_pll
+       - dout_aclk_ccore_133
+
+Input clocks for peric0 clock controller:
+       - fin_pll
+       - dout_aclk_peric0_66
+       - sclk_uart0
+
+Input clocks for peric1 clock controller:
+       - fin_pll
+       - dout_aclk_peric1_66
+       - sclk_uart1
+       - sclk_uart2
+       - sclk_uart3
+
+Input clocks for peris clock controller:
+       - fin_pll
+       - dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+       - fin_pll
+       - dout_aclk_fsys0_200
+       - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+       - fin_pll
+       - dout_aclk_fsys1_200
+       - dout_sclk_mmc0
+       - dout_sclk_mmc1
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
new file mode 100644 (file)
index 0000000..af376a0
--- /dev/null
@@ -0,0 +1,21 @@
+* Marvell MMP2 Clock Controller
+
+The MMP2 clock subsystem generates and supplies clock to various
+controllers within the MMP2 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt
new file mode 100644 (file)
index 0000000..c62eb1d
--- /dev/null
@@ -0,0 +1,21 @@
+* Marvell PXA168 Clock Controller
+
+The PXA168 clock subsystem generates and supplies clock to various
+controllers within the PXA168 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt
new file mode 100644 (file)
index 0000000..d9f41f3
--- /dev/null
@@ -0,0 +1,21 @@
+* Marvell PXA910 Clock Controller
+
+The PXA910 clock subsystem generates and supplies clock to various
+controllers within the PXA910 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 4 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
index 952e373178d27b10d4fca3bdffc8519d5f4531ae..054f65f9319cd71c74936dcab565901559a9d280 100644 (file)
@@ -7,11 +7,16 @@ to 64.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
+    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
     - "renesas,cpg-div6-clock" for generic DIV6 clocks
   - reg: Base address and length of the memory resource used by the DIV6 clock
-  - clocks: Reference to the parent clock
+  - clocks: Reference to the parent clock(s); either one, four, or eight
+    clocks must be specified.  For clocks with multiple parents, invalid
+    settings must be specified as "<0>".
   - #clock-cells: Must be 0
   - clock-output-names: The name of the clock as a free-form string
 
@@ -19,10 +24,11 @@ Required Properties:
 Example
 -------
 
-       sd2_clk: sd2_clk@e6150078 {
-               compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
-               reg = <0 0xe6150078 0 4>;
-               clocks = <&pll1_div2_clk>;
+       sdhi2_clk: sdhi2_clk@e615007c {
+               compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+               reg = <0 0xe615007c 0 4>;
+               clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                        <0>, <&extal2_clk>;
                #clock-cells = <0>;
-               clock-output-names = "sd2";
+               clock-output-names = "sdhi2ck";
        };
index a5f52238c80d5f9b9560914f59e653e772b42bea..2e18676bd4b56503ce42ec4b4d368c32041fe1d0 100644 (file)
@@ -26,11 +26,11 @@ Required Properties:
     must appear in the same order as the output clocks.
   - #clock-cells: Must be 1
   - clock-output-names: The name of the clocks as free-form strings
-  - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
+  - clock-indices: Indices of the gate clocks into the group (0 to 31)
 
-The clocks, clock-output-names and renesas,clock-indices properties contain one
-entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
-gate clocks must not be declared.
+The clocks, clock-output-names and clock-indices properties contain one entry
+per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
+clocks must not be declared.
 
 
 Example
index ea4d0058fd1b68b7d5e11f5228a4867aa0b96eea..924499202dac89afab39ebd93005daa53fcb6ab5 100644 (file)
@@ -2491,8 +2491,9 @@ F:        include/uapi/linux/coda*.h
 
 COMMON CLK FRAMEWORK
 M:     Mike Turquette <mturquette@linaro.org>
+M:     Stephen Boyd <sboyd@codeaurora.org>
 L:     linux-kernel@vger.kernel.org
-T:     git git://git.linaro.org/people/mturquette/linux.git
+T:     git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
 S:     Maintained
 F:     drivers/clk/
 X:     drivers/clk/clkdev.c
index 38c89cafa1ab8ea3ee682b8ccb0c02af8739f785..5b31c3f6d8e57803c4858323636364c67f37188c 100644 (file)
@@ -164,6 +164,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
+dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
+       pxa910-dkb.dtb \
+       mmp2-brownstone.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
        imx1-ads.dtb \
index 7f70a39459f649d7051b5423c754e356686762db..350208c5e1ed2f6d27d192d1c256ab58db5ecb27 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "mmp2.dtsi"
+#include "mmp2.dtsi"
 
 / {
        model = "Marvell MMP2 Brownstone Development Board";
index 4e8b08c628c7ee405efd864f743cbadc8a617321..766bbb8495b60d796ccd857c4965ab4f8d09721c 100644 (file)
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,mmp2.h>
 
 / {
        aliases {
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4030000 0x1000>;
                                interrupts = <27>;
+                               clocks = <&soc_clocks MMP2_CLK_UART0>;
+                               resets = <&soc_clocks MMP2_CLK_UART0>;
                                status = "disabled";
                        };
 
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <28>;
+                               clocks = <&soc_clocks MMP2_CLK_UART1>;
+                               resets = <&soc_clocks MMP2_CLK_UART1>;
                                status = "disabled";
                        };
 
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <24>;
+                               clocks = <&soc_clocks MMP2_CLK_UART2>;
+                               resets = <&soc_clocks MMP2_CLK_UART2>;
                                status = "disabled";
                        };
 
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4016000 0x1000>;
                                interrupts = <46>;
+                               clocks = <&soc_clocks MMP2_CLK_UART3>;
+                               resets = <&soc_clocks MMP2_CLK_UART3>;
                                status = "disabled";
                        };
 
                                #gpio-cells = <2>;
                                interrupts = <49>;
                                interrupt-names = "gpio_mux";
+                               clocks = <&soc_clocks MMP2_CLK_GPIO>;
+                               resets = <&soc_clocks MMP2_CLK_GPIO>;
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                ranges;
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                               clocks = <&soc_clocks MMP2_CLK_TWSI0>;
+                               resets = <&soc_clocks MMP2_CLK_TWSI0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                mrvl,i2c-fast-mode;
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4025000 0x1000>;
                                interrupts = <58>;
+                               clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+                               resets = <&soc_clocks MMP2_CLK_TWSI1>;
                                status = "disabled";
                        };
 
                                interrupts = <1 0>;
                                interrupt-names = "rtc 1Hz", "rtc alarm";
                                interrupt-parent = <&intcmux5>;
+                               clocks = <&soc_clocks MMP2_CLK_RTC>;
+                               resets = <&soc_clocks MMP2_CLK_RTC>;
                                status = "disabled";
                        };
                };
+
+               soc_clocks: clocks{
+                       compatible = "marvell,mmp2-clock";
+                       reg = <0xd4050000 0x1000>,
+                             <0xd4282800 0x400>,
+                             <0xd4015000 0x1000>;
+                       reg-names = "mpmu", "apmu", "apbc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
        };
 };
index e762facb3fa434473e2a1b53ca0a3c68f323c20a..0a988b3fb248ee46658bf1d65780f3f01b4582be 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "pxa168.dtsi"
+#include "pxa168.dtsi"
 
 / {
        model = "Marvell PXA168 Aspenite Development Board";
index 975dad21ac3890d4b81bb23a0d1bf2962a831e09..b899e25cbb1be973c60dc8a8d8c220c02cf3c039 100644 (file)
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa168.h>
 
 / {
        aliases {
@@ -59,6 +60,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <27>;
+                               clocks = <&soc_clocks PXA168_CLK_UART0>;
+                               resets = <&soc_clocks PXA168_CLK_UART0>;
                                status = "disabled";
                        };
 
@@ -66,6 +69,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <28>;
+                               clocks = <&soc_clocks PXA168_CLK_UART1>;
+                               resets = <&soc_clocks PXA168_CLK_UART1>;
                                status = "disabled";
                        };
 
@@ -73,6 +78,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4026000 0x1000>;
                                interrupts = <29>;
+                               clocks = <&soc_clocks PXA168_CLK_UART2>;
+                               resets = <&soc_clocks PXA168_CLK_UART2>;
                                status = "disabled";
                        };
 
@@ -84,6 +91,8 @@
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupts = <49>;
+                               clocks = <&soc_clocks PXA168_CLK_GPIO>;
+                               resets = <&soc_clocks PXA168_CLK_GPIO>;
                                interrupt-names = "gpio_mux";
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                               clocks = <&soc_clocks PXA168_CLK_TWSI0>;
+                               resets = <&soc_clocks PXA168_CLK_TWSI0>;
                                mrvl,i2c-fast-mode;
                                status = "disabled";
                        };
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4025000 0x1000>;
                                interrupts = <58>;
+                               clocks = <&soc_clocks PXA168_CLK_TWSI1>;
+                               resets = <&soc_clocks PXA168_CLK_TWSI1>;
                                status = "disabled";
                        };
 
                                reg = <0xd4010000 0x1000>;
                                interrupts = <5 6>;
                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                               clocks = <&soc_clocks PXA168_CLK_RTC>;
+                               resets = <&soc_clocks PXA168_CLK_RTC>;
                                status = "disabled";
                        };
                };
+
+               soc_clocks: clocks{
+                       compatible = "marvell,pxa168-clock";
+                       reg = <0xd4050000 0x1000>,
+                             <0xd4282800 0x400>,
+                             <0xd4015000 0x1000>;
+                       reg-names = "mpmu", "apmu", "apbc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
        };
 };
index 595492aa505372047aab605aff58b043f16896f6..c82f2810ec73c2274b9c9f4a996cf5a31e530379 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "pxa910.dtsi"
+#include "pxa910.dtsi"
 
 / {
        model = "Marvell PXA910 DKB Development Board";
index 0247c622f580728f77f31dbb36d555d310f524d0..0868f6729be1eaf60fc6df14887f449e92f750c6 100644 (file)
@@ -7,7 +7,8 @@
  *  publishhed by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa910.h>
 
 / {
        aliases {
@@ -71,6 +72,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <27>;
+                               clocks = <&soc_clocks PXA910_CLK_UART0>;
+                               resets = <&soc_clocks PXA910_CLK_UART0>;
                                status = "disabled";
                        };
 
@@ -78,6 +81,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <28>;
+                               clocks = <&soc_clocks PXA910_CLK_UART1>;
+                               resets = <&soc_clocks PXA910_CLK_UART1>;
                                status = "disabled";
                        };
 
@@ -85,6 +90,8 @@
                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4036000 0x1000>;
                                interrupts = <59>;
+                               clocks = <&soc_clocks PXA910_CLK_UART2>;
+                               resets = <&soc_clocks PXA910_CLK_UART2>;
                                status = "disabled";
                        };
 
                                #gpio-cells = <2>;
                                interrupts = <49>;
                                interrupt-names = "gpio_mux";
+                               clocks = <&soc_clocks PXA910_CLK_GPIO>;
+                               resets = <&soc_clocks PXA910_CLK_GPIO>;
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                ranges;
                                #size-cells = <0>;
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                               clocks = <&soc_clocks PXA910_CLK_TWSI0>;
+                               resets = <&soc_clocks PXA910_CLK_TWSI0>;
                                mrvl,i2c-fast-mode;
                                status = "disabled";
                        };
                                #size-cells = <0>;
                                reg = <0xd4037000 0x1000>;
                                interrupts = <54>;
+                               clocks = <&soc_clocks PXA910_CLK_TWSI1>;
+                               resets = <&soc_clocks PXA910_CLK_TWSI1>;
                                status = "disabled";
                        };
 
                                reg = <0xd4010000 0x1000>;
                                interrupts = <5 6>;
                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                               clocks = <&soc_clocks PXA910_CLK_RTC>;
+                               resets = <&soc_clocks PXA910_CLK_RTC>;
                                status = "disabled";
                        };
                };
+
+               soc_clocks: clocks{
+                       compatible = "marvell,pxa910-clock";
+                       reg = <0xd4050000 0x1000>,
+                             <0xd4282800 0x400>,
+                             <0xd4015000 0x1000>,
+                             <0xd403b000 0x1000>;
+                       reg-names = "mpmu", "apmu", "apbc", "apbcp";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
        };
 };
index ebdba87b96711a4a2a3970bcd824253ea9273327..fdbfadf00c84b492bb032f3ca47cf94f78f9c0d7 100644 (file)
@@ -86,11 +86,12 @@ config MACH_GPLUGD
 
 config MACH_MMP_DT
        bool "Support MMP (ARMv5) platforms from device tree"
-       select CPU_PXA168
-       select CPU_PXA910
        select USE_OF
        select PINCTRL
        select PINCTRL_SINGLE
+       select COMMON_CLK
+       select ARCH_HAS_RESET_CONTROLLER
+       select CPU_MOHAWK
        help
          Include support for Marvell MMP2 based platforms using
          the device tree. Needn't select any other machine while
@@ -99,10 +100,12 @@ config MACH_MMP_DT
 config MACH_MMP2_DT
        bool "Support MMP2 (ARMv7) platforms from device tree"
        depends on !CPU_MOHAWK
-       select CPU_MMP2
        select USE_OF
        select PINCTRL
        select PINCTRL_SINGLE
+       select COMMON_CLK
+       select ARCH_HAS_RESET_CONTROLLER
+       select CPU_PJ4
        help
          Include support for Marvell MMP2 based platforms using
          the device tree.
@@ -111,21 +114,18 @@ endmenu
 
 config CPU_PXA168
        bool
-       select COMMON_CLK
        select CPU_MOHAWK
        help
          Select code specific to PXA168
 
 config CPU_PXA910
        bool
-       select COMMON_CLK
        select CPU_MOHAWK
        help
          Select code specific to PXA910
 
 config CPU_MMP2
        bool
-       select COMMON_CLK
        select CPU_PJ4
        help
          Select code specific to MMP2. MMP2 is ARMv7 compatible.
index cca529ceecb758101f0120faa547c2790b004e80..b2296c9309b87659566992548a2a177888f1cf03 100644 (file)
 
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/clk-provider.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
 extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-       OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-       {}
+static const char *pxa168_dt_board_compat[] __initdata = {
+       "mrvl,pxa168-aspenite",
+       NULL,
 };
 
-static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
-       OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-       {}
+static const char *pxa910_dt_board_compat[] __initdata = {
+       "mrvl,pxa910-dkb",
+       NULL,
 };
 
-static void __init pxa168_dt_init(void)
-{
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            pxa168_auxdata_lookup, NULL);
-}
-
-static void __init pxa910_dt_init(void)
+static void __init mmp_init_time(void)
 {
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            pxa910_auxdata_lookup, NULL);
+#ifdef CONFIG_CACHE_TAUROS2
+       tauros2_init(0);
+#endif
+       mmp_dt_init_timer();
+       of_clk_init(NULL);
 }
 
-static const char *mmp_dt_board_compat[] __initdata = {
-       "mrvl,pxa168-aspenite",
-       "mrvl,pxa910-dkb",
-       NULL,
-};
-
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
        .map_io         = mmp_map_io,
-       .init_time      = mmp_dt_init_timer,
-       .init_machine   = pxa168_dt_init,
-       .dt_compat      = mmp_dt_board_compat,
+       .init_time      = mmp_init_time,
+       .dt_compat      = pxa168_dt_board_compat,
 MACHINE_END
 
 DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
        .map_io         = mmp_map_io,
-       .init_time      = mmp_dt_init_timer,
-       .init_machine   = pxa910_dt_init,
-       .dt_compat      = mmp_dt_board_compat,
+       .init_time      = mmp_init_time,
+       .dt_compat      = pxa910_dt_board_compat,
 MACHINE_END
index 023cb453f157ff621110d6c17b6f0cc185b8d8ba..998c0f533abc842659b7f4bcb0d05e2a873a9b58 100644 (file)
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/clk-provider.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-tauros2.h>
 
 #include "common.h"
 
 extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-       OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
-       OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-       {}
-};
-
-static void __init mmp2_dt_init(void)
+static void __init mmp_init_time(void)
 {
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            mmp2_auxdata_lookup, NULL);
+#ifdef CONFIG_CACHE_TAUROS2
+       tauros2_init(0);
+#endif
+       mmp_dt_init_timer();
+       of_clk_init(NULL);
 }
 
 static const char *mmp2_dt_board_compat[] __initdata = {
@@ -44,7 +37,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
        .map_io         = mmp_map_io,
-       .init_time      = mmp_dt_init_timer,
-       .init_machine   = mmp2_dt_init,
+       .init_time      = mmp_init_time,
        .dt_compat      = mmp2_dt_board_compat,
 MACHINE_END
index 4f96ff3ba728321563cbdc6b728f9a25c65d74c6..6e1ecf94bf58daa279cb47e42065da9a9db3c581 100644 (file)
@@ -77,7 +77,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 
        else {
                if (mux->flags & CLK_MUX_INDEX_BIT)
-                       index = (1 << ffs(index));
+                       index = 1 << index;
 
                if (mux->flags & CLK_MUX_INDEX_ONE)
                        index++;
index 4896ae9e23da0c23ed52872cf1992f95609e1b59..5307225684eb351c49463b1332fdf9eb6e4f9755 100644 (file)
@@ -1614,7 +1614,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
 
        if (clk->num_parents == 1) {
                if (IS_ERR_OR_NULL(clk->parent))
-                       ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+                       clk->parent = __clk_lookup(clk->parent_names[0]);
                ret = clk->parent;
                goto out;
        }
index 339945d2503b33798ca4e98b51e140f2b8f658ae..640ea3327c3e481f242d818d74c8782d0dc2a420 100644 (file)
 #include "clk.h"
 
 /* clock parent list */
-static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
-static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
-static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
-static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
-static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
-static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
-static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
-static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
-static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
-static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
-static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
-static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
-static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
-static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
+static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
+static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
+static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
+static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
+static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
+static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
+static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
+static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
+static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
+static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
+static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", };
+static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
 /* share axi parent */
-static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
-static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
-static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
-static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
-static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
+static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
+static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
+static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
+static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
+static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
                                             "armpll3", "armpll5", };
-static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
+static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
                                             "armpll3", "armpll5", };
-static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
-static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
-static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
+static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
+static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
 
 
 /* fixed rate clocks */
index 392d78044ce3748903ad1614ffc4589a7cdb168c..3caaf7cc169c684559973f105317dea76bbd1d54 100644 (file)
@@ -2,7 +2,12 @@
 # Makefile for mmp specific clk
 #
 
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
+
+obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+
+obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
+obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
index 23a56f561812decc149624fe72b803a7bbb726ab..eeba52c2def6df56d25bf8d641d7fa38e261db6d 100644 (file)
  * numerator/denominator = Fin / (Fout * factor)
  */
 
-#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
-struct clk_factor {
-       struct clk_hw           hw;
-       void __iomem            *base;
-       struct clk_factor_masks *masks;
-       struct clk_factor_tbl   *ftbl;
-       unsigned int            ftbl_cnt;
-};
+#define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw)
 
 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
                unsigned long *prate)
 {
-       struct clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
        unsigned long rate = 0, prev_rate;
        int i;
 
@@ -58,8 +51,8 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
 static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
                unsigned long parent_rate)
 {
-       struct clk_factor *factor = to_clk_factor(hw);
-       struct clk_factor_masks *masks = factor->masks;
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor_masks *masks = factor->masks;
        unsigned int val, num, den;
 
        val = readl_relaxed(factor->base);
@@ -81,11 +74,12 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
 static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
                                unsigned long prate)
 {
-       struct clk_factor *factor = to_clk_factor(hw);
-       struct clk_factor_masks *masks = factor->masks;
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor_masks *masks = factor->masks;
        int i;
        unsigned long val;
        unsigned long prev_rate, rate = 0;
+       unsigned long flags = 0;
 
        for (i = 0; i < factor->ftbl_cnt; i++) {
                prev_rate = rate;
@@ -97,6 +91,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
        if (i > 0)
                i--;
 
+       if (factor->lock)
+               spin_lock_irqsave(factor->lock, flags);
+
        val = readl_relaxed(factor->base);
 
        val &= ~(masks->num_mask << masks->num_shift);
@@ -107,21 +104,65 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
 
        writel_relaxed(val, factor->base);
 
+       if (factor->lock)
+               spin_unlock_irqrestore(factor->lock, flags);
+
        return 0;
 }
 
+void clk_factor_init(struct clk_hw *hw)
+{
+       struct mmp_clk_factor *factor = to_clk_factor(hw);
+       struct mmp_clk_factor_masks *masks = factor->masks;
+       u32 val, num, den;
+       int i;
+       unsigned long flags = 0;
+
+       if (factor->lock)
+               spin_lock_irqsave(factor->lock, flags);
+
+       val = readl(factor->base);
+
+       /* calculate numerator */
+       num = (val >> masks->num_shift) & masks->num_mask;
+
+       /* calculate denominator */
+       den = (val >> masks->den_shift) & masks->den_mask;
+
+       for (i = 0; i < factor->ftbl_cnt; i++)
+               if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
+                       break;
+
+       if (i >= factor->ftbl_cnt) {
+               val &= ~(masks->num_mask << masks->num_shift);
+               val |= (factor->ftbl[0].num & masks->num_mask) <<
+                       masks->num_shift;
+
+               val &= ~(masks->den_mask << masks->den_shift);
+               val |= (factor->ftbl[0].den & masks->den_mask) <<
+                       masks->den_shift;
+
+               writel(val, factor->base);
+       }
+
+       if (factor->lock)
+               spin_unlock_irqrestore(factor->lock, flags);
+}
+
 static struct clk_ops clk_factor_ops = {
        .recalc_rate = clk_factor_recalc_rate,
        .round_rate = clk_factor_round_rate,
        .set_rate = clk_factor_set_rate,
+       .init = clk_factor_init,
 };
 
 struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
                unsigned long flags, void __iomem *base,
-               struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
-               unsigned int ftbl_cnt)
+               struct mmp_clk_factor_masks *masks,
+               struct mmp_clk_factor_tbl *ftbl,
+               unsigned int ftbl_cnt, spinlock_t *lock)
 {
-       struct clk_factor *factor;
+       struct mmp_clk_factor *factor;
        struct clk_init_data init;
        struct clk *clk;
 
@@ -142,6 +183,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
        factor->ftbl = ftbl;
        factor->ftbl_cnt = ftbl_cnt;
        factor->hw.init = &init;
+       factor->lock = lock;
 
        init.name = name;
        init.ops = &clk_factor_ops;
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644 (file)
index 0000000..adbd9d6
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie <chao.xie@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include "clk.h"
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)    container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+       struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+       struct clk *clk = hw->clk;
+       unsigned long flags = 0;
+       unsigned long rate;
+       u32 tmp;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       tmp = readl(gate->reg);
+       tmp &= ~gate->mask;
+       tmp |= gate->val_enable;
+       writel(tmp, gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+
+       if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
+               rate = __clk_get_rate(clk);
+               /* Need delay 2 cycles. */
+               udelay(2000000/rate);
+       }
+
+       return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+       struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+       unsigned long flags = 0;
+       u32 tmp;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       tmp = readl(gate->reg);
+       tmp &= ~gate->mask;
+       tmp |= gate->val_disable;
+       writel(tmp, gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+       struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+       unsigned long flags = 0;
+       u32 tmp;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       tmp = readl(gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+
+       return (tmp & gate->mask) == gate->val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+       .enable = mmp_clk_gate_enable,
+       .disable = mmp_clk_gate_disable,
+       .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+               const char *parent_name, unsigned long flags,
+               void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+               unsigned int gate_flags, spinlock_t *lock)
+{
+       struct mmp_clk_gate *gate;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       /* allocate the gate */
+       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+       if (!gate) {
+               pr_err("%s:%s could not allocate gate clk\n", __func__, name);
+               return ERR_PTR(-ENOMEM);
+       }
+
+       init.name = name;
+       init.ops = &mmp_clk_gate_ops;
+       init.flags = flags | CLK_IS_BASIC;
+       init.parent_names = (parent_name ? &parent_name : NULL);
+       init.num_parents = (parent_name ? 1 : 0);
+
+       /* struct clk_gate assignments */
+       gate->reg = reg;
+       gate->mask = mask;
+       gate->val_enable = val_enable;
+       gate->val_disable = val_disable;
+       gate->flags = gate_flags;
+       gate->lock = lock;
+       gate->hw.init = &init;
+
+       clk = clk_register(dev, &gate->hw);
+
+       if (IS_ERR(clk))
+               kfree(gate);
+
+       return clk;
+}
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
new file mode 100644 (file)
index 0000000..b79742c
--- /dev/null
@@ -0,0 +1,513 @@
+/*
+ * mmp mix(div and mux) clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie <chao.xie@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+
+/*
+ * The mix clock is a clock combined mux and div type clock.
+ * Because the div field and mux field need to be set at same
+ * time, we can not divide it into 2 types of clock
+ */
+
+#define to_clk_mix(hw) container_of(hw, struct mmp_clk_mix, hw)
+
+static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
+{
+       unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
+       unsigned int maxdiv = 0;
+       struct clk_div_table *clkt;
+
+       if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+               return div_mask;
+       if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+               return 1 << div_mask;
+       if (mix->div_table) {
+               for (clkt = mix->div_table; clkt->div; clkt++)
+                       if (clkt->div > maxdiv)
+                               maxdiv = clkt->div;
+               return maxdiv;
+       }
+       return div_mask + 1;
+}
+
+static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
+{
+       struct clk_div_table *clkt;
+
+       if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+               return val;
+       if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+               return 1 << val;
+       if (mix->div_table) {
+               for (clkt = mix->div_table; clkt->div; clkt++)
+                       if (clkt->val == val)
+                               return clkt->div;
+               if (clkt->div == 0)
+                       return 0;
+       }
+       return val + 1;
+}
+
+static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val)
+{
+       int num_parents = __clk_get_num_parents(mix->hw.clk);
+       int i;
+
+       if (mix->mux_flags & CLK_MUX_INDEX_BIT)
+               return ffs(val) - 1;
+       if (mix->mux_flags & CLK_MUX_INDEX_ONE)
+               return val - 1;
+       if (mix->mux_table) {
+               for (i = 0; i < num_parents; i++)
+                       if (mix->mux_table[i] == val)
+                               return i;
+               if (i == num_parents)
+                       return 0;
+       }
+
+       return val;
+}
+static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div)
+{
+       struct clk_div_table *clkt;
+
+       if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
+               return div;
+       if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+               return __ffs(div);
+       if (mix->div_table) {
+               for (clkt = mix->div_table; clkt->div; clkt++)
+                       if (clkt->div == div)
+                               return clkt->val;
+               if (clkt->div == 0)
+                       return 0;
+       }
+
+       return div - 1;
+}
+
+static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux)
+{
+       if (mix->mux_table)
+               return mix->mux_table[mux];
+
+       return mux;
+}
+
+static void _filter_clk_table(struct mmp_clk_mix *mix,
+                               struct mmp_clk_mix_clk_table *table,
+                               unsigned int table_size)
+{
+       int i;
+       struct mmp_clk_mix_clk_table *item;
+       struct clk *parent, *clk;
+       unsigned long parent_rate;
+
+       clk = mix->hw.clk;
+
+       for (i = 0; i < table_size; i++) {
+               item = &table[i];
+               parent = clk_get_parent_by_index(clk, item->parent_index);
+               parent_rate = __clk_get_rate(parent);
+               if (parent_rate % item->rate) {
+                       item->valid = 0;
+               } else {
+                       item->divisor = parent_rate / item->rate;
+                       item->valid = 1;
+               }
+       }
+}
+
+static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,
+                       unsigned int change_mux, unsigned int change_div)
+{
+       struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+       u8 width, shift;
+       u32 mux_div, fc_req;
+       int ret, timeout = 50;
+       unsigned long flags = 0;
+
+       if (!change_mux && !change_div)
+               return -EINVAL;
+
+       if (mix->lock)
+               spin_lock_irqsave(mix->lock, flags);
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1
+               || mix->type == MMP_CLK_MIX_TYPE_V2)
+               mux_div = readl(ri->reg_clk_ctrl);
+       else
+               mux_div = readl(ri->reg_clk_sel);
+
+       if (change_div) {
+               width = ri->width_div;
+               shift = ri->shift_div;
+               mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
+               mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift);
+       }
+
+       if (change_mux) {
+               width = ri->width_mux;
+               shift = ri->shift_mux;
+               mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
+               mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift);
+       }
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1) {
+               writel(mux_div, ri->reg_clk_ctrl);
+       } else if (mix->type == MMP_CLK_MIX_TYPE_V2) {
+               mux_div |= (1 << ri->bit_fc);
+               writel(mux_div, ri->reg_clk_ctrl);
+
+               do {
+                       fc_req = readl(ri->reg_clk_ctrl);
+                       timeout--;
+                       if (!(fc_req & (1 << ri->bit_fc)))
+                               break;
+               } while (timeout);
+
+               if (timeout == 0) {
+                       pr_err("%s:%s cannot do frequency change\n",
+                               __func__, __clk_get_name(mix->hw.clk));
+                       ret = -EBUSY;
+                       goto error;
+               }
+       } else {
+               fc_req = readl(ri->reg_clk_ctrl);
+               fc_req |= 1 << ri->bit_fc;
+               writel(fc_req, ri->reg_clk_ctrl);
+               writel(mux_div, ri->reg_clk_sel);
+               fc_req &= ~(1 << ri->bit_fc);
+       }
+
+       ret = 0;
+error:
+       if (mix->lock)
+               spin_unlock_irqrestore(mix->lock, flags);
+
+       return ret;
+}
+
+static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
+                                       unsigned long *best_parent_rate,
+                                       struct clk **best_parent_clk)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_clk_table *item;
+       struct clk *parent, *parent_best, *mix_clk;
+       unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;
+       unsigned long gap, gap_best;
+       u32 div_val_max;
+       unsigned int div;
+       int i, j;
+
+       mix_clk = hw->clk;
+
+       parent = NULL;
+       mix_rate_best = 0;
+       parent_rate_best = 0;
+       gap_best = rate;
+       parent_best = NULL;
+
+       if (mix->table) {
+               for (i = 0; i < mix->table_size; i++) {
+                       item = &mix->table[i];
+                       if (item->valid == 0)
+                               continue;
+                       parent = clk_get_parent_by_index(mix_clk,
+                                                       item->parent_index);
+                       parent_rate = __clk_get_rate(parent);
+                       mix_rate = parent_rate / item->divisor;
+                       gap = abs(mix_rate - rate);
+                       if (parent_best == NULL || gap < gap_best) {
+                               parent_best = parent;
+                               parent_rate_best = parent_rate;
+                               mix_rate_best = mix_rate;
+                               gap_best = gap;
+                               if (gap_best == 0)
+                                       goto found;
+                       }
+               }
+       } else {
+               for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
+                       parent = clk_get_parent_by_index(mix_clk, i);
+                       parent_rate = __clk_get_rate(parent);
+                       div_val_max = _get_maxdiv(mix);
+                       for (j = 0; j < div_val_max; j++) {
+                               div = _get_div(mix, j);
+                               mix_rate = parent_rate / div;
+                               gap = abs(mix_rate - rate);
+                               if (parent_best == NULL || gap < gap_best) {
+                                       parent_best = parent;
+                                       parent_rate_best = parent_rate;
+                                       mix_rate_best = mix_rate;
+                                       gap_best = gap;
+                                       if (gap_best == 0)
+                                               goto found;
+                               }
+                       }
+               }
+       }
+
+found:
+       *best_parent_rate = parent_rate_best;
+       *best_parent_clk = parent_best;
+
+       return mix_rate_best;
+}
+
+static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw,
+                                               unsigned long rate,
+                                               unsigned long parent_rate,
+                                               u8 index)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       unsigned int div;
+       u32 div_val, mux_val;
+
+       div = parent_rate / rate;
+       div_val = _get_div_val(mix, div);
+       mux_val = _get_mux_val(mix, index);
+
+       return _set_rate(mix, mux_val, div_val, 1, 1);
+}
+
+static u8 mmp_clk_mix_get_parent(struct clk_hw *hw)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+       unsigned long flags = 0;
+       u32 mux_div = 0;
+       u8 width, shift;
+       u32 mux_val;
+
+       if (mix->lock)
+               spin_lock_irqsave(mix->lock, flags);
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1
+               || mix->type == MMP_CLK_MIX_TYPE_V2)
+               mux_div = readl(ri->reg_clk_ctrl);
+       else
+               mux_div = readl(ri->reg_clk_sel);
+
+       if (mix->lock)
+               spin_unlock_irqrestore(mix->lock, flags);
+
+       width = mix->reg_info.width_mux;
+       shift = mix->reg_info.shift_mux;
+
+       mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift);
+
+       return _get_mux(mix, mux_val);
+}
+
+static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw,
+                                       unsigned long parent_rate)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
+       unsigned long flags = 0;
+       u32 mux_div = 0;
+       u8 width, shift;
+       unsigned int div;
+
+       if (mix->lock)
+               spin_lock_irqsave(mix->lock, flags);
+
+       if (mix->type == MMP_CLK_MIX_TYPE_V1
+               || mix->type == MMP_CLK_MIX_TYPE_V2)
+               mux_div = readl(ri->reg_clk_ctrl);
+       else
+               mux_div = readl(ri->reg_clk_sel);
+
+       if (mix->lock)
+               spin_unlock_irqrestore(mix->lock, flags);
+
+       width = mix->reg_info.width_div;
+       shift = mix->reg_info.shift_div;
+
+       div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift));
+
+       return parent_rate / div;
+}
+
+static int mmp_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_clk_table *item;
+       int i;
+       u32 div_val, mux_val;
+
+       if (mix->table) {
+               for (i = 0; i < mix->table_size; i++) {
+                       item = &mix->table[i];
+                       if (item->valid == 0)
+                               continue;
+                       if (item->parent_index == index)
+                               break;
+               }
+               if (i < mix->table_size) {
+                       div_val = _get_div_val(mix, item->divisor);
+                       mux_val = _get_mux_val(mix, item->parent_index);
+               } else
+                       return -EINVAL;
+       } else {
+               mux_val = _get_mux_val(mix, index);
+               div_val = 0;
+       }
+
+       return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0);
+}
+
+static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long best_parent_rate)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+       struct mmp_clk_mix_clk_table *item;
+       unsigned long parent_rate;
+       unsigned int best_divisor;
+       struct clk *mix_clk, *parent;
+       int i;
+
+       best_divisor = best_parent_rate / rate;
+
+       mix_clk = hw->clk;
+       if (mix->table) {
+               for (i = 0; i < mix->table_size; i++) {
+                       item = &mix->table[i];
+                       if (item->valid == 0)
+                               continue;
+                       parent = clk_get_parent_by_index(mix_clk,
+                                                       item->parent_index);
+                       parent_rate = __clk_get_rate(parent);
+                       if (parent_rate == best_parent_rate
+                               && item->divisor == best_divisor)
+                               break;
+               }
+               if (i < mix->table_size)
+                       return _set_rate(mix,
+                                       _get_mux_val(mix, item->parent_index),
+                                       _get_div_val(mix, item->divisor),
+                                       1, 1);
+               else
+                       return -EINVAL;
+       } else {
+               for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
+                       parent = clk_get_parent_by_index(mix_clk, i);
+                       parent_rate = __clk_get_rate(parent);
+                       if (parent_rate == best_parent_rate)
+                               break;
+               }
+               if (i < __clk_get_num_parents(mix_clk))
+                       return _set_rate(mix, _get_mux_val(mix, i),
+                                       _get_div_val(mix, best_divisor), 1, 1);
+               else
+                       return -EINVAL;
+       }
+}
+
+static void mmp_clk_mix_init(struct clk_hw *hw)
+{
+       struct mmp_clk_mix *mix = to_clk_mix(hw);
+
+       if (mix->table)
+               _filter_clk_table(mix, mix->table, mix->table_size);
+}
+
+const struct clk_ops mmp_clk_mix_ops = {
+       .determine_rate = mmp_clk_mix_determine_rate,
+       .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
+       .set_rate = mmp_clk_set_rate,
+       .set_parent = mmp_clk_set_parent,
+       .get_parent = mmp_clk_mix_get_parent,
+       .recalc_rate = mmp_clk_mix_recalc_rate,
+       .init = mmp_clk_mix_init,
+};
+
+struct clk *mmp_clk_register_mix(struct device *dev,
+                                       const char *name,
+                                       const char **parent_names,
+                                       u8 num_parents,
+                                       unsigned long flags,
+                                       struct mmp_clk_mix_config *config,
+                                       spinlock_t *lock)
+{
+       struct mmp_clk_mix *mix;
+       struct clk *clk;
+       struct clk_init_data init;
+       size_t table_bytes;
+
+       mix = kzalloc(sizeof(*mix), GFP_KERNEL);
+       if (!mix) {
+               pr_err("%s:%s: could not allocate mmp mix clk\n",
+                       __func__, name);
+               return ERR_PTR(-ENOMEM);
+       }
+
+       init.name = name;
+       init.flags = flags | CLK_GET_RATE_NOCACHE;
+       init.parent_names = parent_names;
+       init.num_parents = num_parents;
+       init.ops = &mmp_clk_mix_ops;
+
+       memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
+       if (config->table) {
+               table_bytes = sizeof(*config->table) * config->table_size;
+               mix->table = kzalloc(table_bytes, GFP_KERNEL);
+               if (!mix->table) {
+                       pr_err("%s:%s: could not allocate mmp mix table\n",
+                               __func__, name);
+                       kfree(mix);
+                       return ERR_PTR(-ENOMEM);
+               }
+               memcpy(mix->table, config->table, table_bytes);
+               mix->table_size = config->table_size;
+       }
+
+       if (config->mux_table) {
+               table_bytes = sizeof(u32) * num_parents;
+               mix->mux_table = kzalloc(table_bytes, GFP_KERNEL);
+               if (!mix->mux_table) {
+                       pr_err("%s:%s: could not allocate mmp mix mux-table\n",
+                               __func__, name);
+                       kfree(mix->table);
+                       kfree(mix);
+                       return ERR_PTR(-ENOMEM);
+               }
+               memcpy(mix->mux_table, config->mux_table, table_bytes);
+       }
+
+       mix->div_flags = config->div_flags;
+       mix->mux_flags = config->mux_flags;
+       mix->lock = lock;
+       mix->hw.init = &init;
+
+       if (config->reg_info.bit_fc >= 32)
+               mix->type = MMP_CLK_MIX_TYPE_V1;
+       else if (config->reg_info.reg_clk_sel)
+               mix->type = MMP_CLK_MIX_TYPE_V3;
+       else
+               mix->type = MMP_CLK_MIX_TYPE_V2;
+       clk = clk_register(dev, &mix->hw);
+
+       if (IS_ERR(clk)) {
+               kfree(mix->mux_table);
+               kfree(mix->table);
+               kfree(mix);
+       }
+
+       return clk;
+}
index b2721cae257adcca4a106cee4e9a9e443bf5d808..5c90a4230fa3d3f2718c7ed6452c32c51df70b24 100644 (file)
@@ -54,7 +54,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
        .factor = 2,
        .num_mask = 0x1fff,
        .den_mask = 0x1fff,
@@ -62,7 +62,7 @@ static struct clk_factor_masks uart_factor_masks = {
        .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
        {.num = 14634, .den = 2165},    /*14.745MHZ */
        {.num = 3521, .den = 689},      /*19.23MHZ */
        {.num = 9679, .den = 5728},     /*58.9824MHZ */
@@ -191,7 +191,7 @@ void __init mmp2_clk_init(void)
        clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(clk, 14745600);
        clk_register_clkdev(clk, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
new file mode 100644 (file)
index 0000000..2cbc2b4
--- /dev/null
@@ -0,0 +1,334 @@
+/*
+ * mmp2 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,mmp2.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC       0x0
+#define APBC_TWSI0     0x4
+#define APBC_TWSI1     0x8
+#define APBC_TWSI2     0xc
+#define APBC_TWSI3     0x10
+#define APBC_TWSI4     0x7c
+#define APBC_TWSI5     0x80
+#define APBC_KPC       0x18
+#define APBC_UART0     0x2c
+#define APBC_UART1     0x30
+#define APBC_UART2     0x34
+#define APBC_UART3     0x88
+#define APBC_GPIO      0x38
+#define APBC_PWM0      0x3c
+#define APBC_PWM1      0x40
+#define APBC_PWM2      0x44
+#define APBC_PWM3      0x48
+#define APBC_SSP0      0x50
+#define APBC_SSP1      0x54
+#define APBC_SSP2      0x58
+#define APBC_SSP3      0x5c
+#define APMU_SDH0      0x54
+#define APMU_SDH1      0x58
+#define APMU_SDH2      0xe8
+#define APMU_SDH3      0xec
+#define APMU_USB       0x5c
+#define APMU_DISP0     0x4c
+#define APMU_DISP1     0x110
+#define APMU_CCIC0     0x50
+#define APMU_CCIC1     0xf4
+#define MPMU_UART_PLL  0x14
+
+struct mmp2_clk_unit {
+       struct mmp_clk_unit unit;
+       void __iomem *mpmu_base;
+       void __iomem *apmu_base;
+       void __iomem *apbc_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+       {MMP2_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+       {MMP2_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+       {MMP2_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 800000000},
+       {MMP2_CLK_PLL2, "pll2", NULL, CLK_IS_ROOT, 960000000},
+       {MMP2_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+       {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+       {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+       {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+       {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+       {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
+       {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
+       {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
+       {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+       {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
+       {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
+       {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
+       {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
+       {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
+       {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
+       {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
+       {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
+       {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+       .factor = 2,
+       .num_mask = 0x1fff,
+       .den_mask = 0x1fff,
+       .num_shift = 16,
+       .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+       {.num = 14634, .den = 2165},    /*14.745MHZ */
+       {.num = 3521, .den = 689},      /*19.23MHZ */
+       {.num = 9679, .den = 5728},     /*58.9824MHZ */
+       {.num = 15850, .den = 9451},    /*59.429MHZ */
+};
+
+static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                       ARRAY_SIZE(fixed_rate_clks));
+
+       mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                       ARRAY_SIZE(fixed_factor_clks));
+
+       clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                               CLK_SET_RATE_PARENT,
+                               pxa_unit->mpmu_base + MPMU_UART_PLL,
+                               &uart_factor_masks, uart_factor_tbl,
+                               ARRAY_SIZE(uart_factor_tbl), NULL);
+       mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static DEFINE_SPINLOCK(ssp2_lock);
+static DEFINE_SPINLOCK(ssp3_lock);
+static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+       {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+       {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+       {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
+       {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
+       {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+       {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+       {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
+       {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+       {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
+       {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
+       {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
+       {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
+       {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
+       {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
+       {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
+       {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
+       {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
+       {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
+       {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
+};
+
+static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_mux_clks));
+
+       mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh_lock);
+static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static struct mmp_clk_mix_config sdh_mix_config = {
+       .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
+};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static DEFINE_SPINLOCK(disp1_lock);
+static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static DEFINE_SPINLOCK(ccic1_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
+static struct mmp_clk_mix_config ccic0_mix_config = {
+       .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
+};
+static struct mmp_clk_mix_config ccic1_mix_config = {
+       .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
+};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+       {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
+       {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+       {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
+       {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
+       {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
+       {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+       {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+       {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+       /* The gate clocks has mux parent. */
+       {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
+       {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+       {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
+       {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
+       {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+       {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
+       {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
+       {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
+};
+
+static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
+       clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
+                                       ARRAY_SIZE(sdh_parent_names),
+                                       CLK_SET_RATE_PARENT,
+                                       &sdh_mix_config, &sdh_lock);
+
+       ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
+       clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
+                                       ARRAY_SIZE(ccic_parent_names),
+                                       CLK_SET_RATE_PARENT,
+                                       &ccic0_mix_config, &ccic0_lock);
+       mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
+
+       ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
+       clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
+                                       ARRAY_SIZE(ccic_parent_names),
+                                       CLK_SET_RATE_PARENT,
+                                       &ccic1_mix_config, &ccic1_lock);
+       mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
+
+       mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_mux_clks));
+
+       mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_div_clks));
+
+       mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void mmp2_clk_reset_init(struct device_node *np,
+                               struct mmp2_clk_unit *pxa_unit)
+{
+       struct mmp_clk_reset_cell *cells;
+       int i, nr_resets;
+
+       nr_resets = ARRAY_SIZE(apbc_gate_clks);
+       cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+       if (!cells)
+               return;
+
+       for (i = 0; i < nr_resets; i++) {
+               cells[i].clk_id = apbc_gate_clks[i].id;
+               cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[i].flags = 0;
+               cells[i].lock = apbc_gate_clks[i].lock;
+               cells[i].bits = 0x4;
+       }
+
+       mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init mmp2_clk_init(struct device_node *np)
+{
+       struct mmp2_clk_unit *pxa_unit;
+
+       pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+       if (!pxa_unit)
+               return;
+
+       pxa_unit->mpmu_base = of_iomap(np, 0);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map mpmu registers\n");
+               return;
+       }
+
+       pxa_unit->apmu_base = of_iomap(np, 1);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apmu registers\n");
+               return;
+       }
+
+       pxa_unit->apbc_base = of_iomap(np, 2);
+       if (!pxa_unit->apbc_base) {
+               pr_err("failed to map apbc registers\n");
+               return;
+       }
+
+       mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
+
+       mmp2_pll_init(pxa_unit);
+
+       mmp2_apb_periph_clk_init(pxa_unit);
+
+       mmp2_axi_periph_clk_init(pxa_unit);
+
+       mmp2_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
new file mode 100644 (file)
index 0000000..5b1810d
--- /dev/null
@@ -0,0 +1,279 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa168.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC       0x28
+#define APBC_TWSI0     0x2c
+#define APBC_KPC       0x30
+#define APBC_UART0     0x0
+#define APBC_UART1     0x4
+#define APBC_GPIO      0x8
+#define APBC_PWM0      0xc
+#define APBC_PWM1      0x10
+#define APBC_PWM2      0x14
+#define APBC_PWM3      0x18
+#define APBC_SSP0      0x81c
+#define APBC_SSP1      0x820
+#define APBC_SSP2      0x84c
+#define APBC_SSP3      0x858
+#define APBC_SSP4      0x85c
+#define APBC_TWSI1     0x6c
+#define APBC_UART2     0x70
+#define APMU_SDH0      0x54
+#define APMU_SDH1      0x58
+#define APMU_USB       0x5c
+#define APMU_DISP0     0x4c
+#define APMU_CCIC0     0x50
+#define APMU_DFC       0x60
+#define MPMU_UART_PLL  0x14
+
+struct pxa168_clk_unit {
+       struct mmp_clk_unit unit;
+       void __iomem *mpmu_base;
+       void __iomem *apmu_base;
+       void __iomem *apbc_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+       {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+       {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+       {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+       {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+       {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+       {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+       {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+       {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
+       {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+       {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
+       {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
+       {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
+       {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
+       {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
+       {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
+       {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+       .factor = 2,
+       .num_mask = 0x1fff,
+       .den_mask = 0x1fff,
+       .num_shift = 16,
+       .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+       {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                       ARRAY_SIZE(fixed_rate_clks));
+
+       mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                       ARRAY_SIZE(fixed_factor_clks));
+
+       clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                               CLK_SET_RATE_PARENT,
+                               pxa_unit->mpmu_base + MPMU_UART_PLL,
+                               &uart_factor_masks, uart_factor_tbl,
+                               ARRAY_SIZE(uart_factor_tbl), NULL);
+       mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static DEFINE_SPINLOCK(ssp2_lock);
+static DEFINE_SPINLOCK(ssp3_lock);
+static DEFINE_SPINLOCK(ssp4_lock);
+static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+       {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+       {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+       {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
+       {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+       {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+       {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
+       {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
+       {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+       {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
+       {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
+       {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
+       {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
+       {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
+       {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
+       {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
+       {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
+};
+
+static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_mux_clks));
+
+       mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_gate_clks));
+
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+       {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
+       {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
+       {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
+       {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
+       {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+       {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+       {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
+       {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+       {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
+       /* The gate clocks has mux parent. */
+       {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
+       {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
+       {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+       {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+       {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+       {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+};
+
+static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_mux_clks));
+
+       mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_div_clks));
+
+       mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void pxa168_clk_reset_init(struct device_node *np,
+                               struct pxa168_clk_unit *pxa_unit)
+{
+       struct mmp_clk_reset_cell *cells;
+       int i, nr_resets;
+
+       nr_resets = ARRAY_SIZE(apbc_gate_clks);
+       cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+       if (!cells)
+               return;
+
+       for (i = 0; i < nr_resets; i++) {
+               cells[i].clk_id = apbc_gate_clks[i].id;
+               cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[i].flags = 0;
+               cells[i].lock = apbc_gate_clks[i].lock;
+               cells[i].bits = 0x4;
+       }
+
+       mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init pxa168_clk_init(struct device_node *np)
+{
+       struct pxa168_clk_unit *pxa_unit;
+
+       pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+       if (!pxa_unit)
+               return;
+
+       pxa_unit->mpmu_base = of_iomap(np, 0);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map mpmu registers\n");
+               return;
+       }
+
+       pxa_unit->apmu_base = of_iomap(np, 1);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apmu registers\n");
+               return;
+       }
+
+       pxa_unit->apbc_base = of_iomap(np, 2);
+       if (!pxa_unit->apbc_base) {
+               pr_err("failed to map apbc registers\n");
+               return;
+       }
+
+       mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
+
+       pxa168_pll_init(pxa_unit);
+
+       pxa168_apb_periph_clk_init(pxa_unit);
+
+       pxa168_axi_periph_clk_init(pxa_unit);
+
+       pxa168_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
new file mode 100644 (file)
index 0000000..5e3c80d
--- /dev/null
@@ -0,0 +1,301 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa910.h>
+
+#include "clk.h"
+#include "reset.h"
+
+#define APBC_RTC       0x28
+#define APBC_TWSI0     0x2c
+#define APBC_KPC       0x18
+#define APBC_UART0     0x0
+#define APBC_UART1     0x4
+#define APBC_GPIO      0x8
+#define APBC_PWM0      0xc
+#define APBC_PWM1      0x10
+#define APBC_PWM2      0x14
+#define APBC_PWM3      0x18
+#define APBC_SSP0      0x1c
+#define APBC_SSP1      0x20
+#define APBC_SSP2      0x4c
+#define APBCP_TWSI1    0x28
+#define APBCP_UART2    0x1c
+#define APMU_SDH0      0x54
+#define APMU_SDH1      0x58
+#define APMU_USB       0x5c
+#define APMU_DISP0     0x4c
+#define APMU_CCIC0     0x50
+#define APMU_DFC       0x60
+#define MPMU_UART_PLL  0x14
+
+struct pxa910_clk_unit {
+       struct mmp_clk_unit unit;
+       void __iomem *mpmu_base;
+       void __iomem *apmu_base;
+       void __iomem *apbc_base;
+       void __iomem *apbcp_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+       {PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
+       {PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
+       {PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+       {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
+       {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
+       {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
+       {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
+       {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
+       {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
+       {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
+       {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
+       {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
+       {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
+       {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
+       {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
+       {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+       .factor = 2,
+       .num_mask = 0x1fff,
+       .den_mask = 0x1fff,
+       .num_shift = 16,
+       .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+       {.num = 8125, .den = 1536},     /*14.745MHZ */
+};
+
+static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
+{
+       struct clk *clk;
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+                                       ARRAY_SIZE(fixed_rate_clks));
+
+       mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+                                       ARRAY_SIZE(fixed_factor_clks));
+
+       clk = mmp_clk_register_factor("uart_pll", "pll1_4",
+                               CLK_SET_RATE_PARENT,
+                               pxa_unit->mpmu_base + MPMU_UART_PLL,
+                               &uart_factor_masks, uart_factor_tbl,
+                               ARRAY_SIZE(uart_factor_tbl), NULL);
+       mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
+}
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
+
+static DEFINE_SPINLOCK(ssp0_lock);
+static DEFINE_SPINLOCK(ssp1_lock);
+static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+
+static DEFINE_SPINLOCK(reset_lock);
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+       {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
+       {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
+       {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
+       {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
+};
+
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
+       {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
+};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+       {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
+       {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
+       {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
+       {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
+       {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
+       {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
+};
+
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
+       {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
+       /* The gate clocks has mux parent. */
+       {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
+};
+
+static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_mux_clks));
+
+       mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
+                               ARRAY_SIZE(apbcp_mux_clks));
+
+       mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+                               ARRAY_SIZE(apbc_gate_clks));
+
+       mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
+                               ARRAY_SIZE(apbcp_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
+
+static DEFINE_SPINLOCK(usb_lock);
+
+static DEFINE_SPINLOCK(disp0_lock);
+static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
+
+static DEFINE_SPINLOCK(ccic0_lock);
+static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
+
+static struct mmp_param_mux_clk apmu_mux_clks[] = {
+       {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
+       {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
+       {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
+       {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
+       {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
+};
+
+static struct mmp_param_div_clk apmu_div_clks[] = {
+       {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+       {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
+       {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
+       {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
+       /* The gate clocks has mux parent. */
+       {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
+       {PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
+       {PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+       {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
+       {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
+       {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
+};
+
+static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
+{
+       struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+       mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_mux_clks));
+
+       mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_div_clks));
+
+       mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+                               ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void pxa910_clk_reset_init(struct device_node *np,
+                               struct pxa910_clk_unit *pxa_unit)
+{
+       struct mmp_clk_reset_cell *cells;
+       int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
+
+       nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
+       nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
+       nr_resets = nr_resets_apbc + nr_resets_apbcp;
+       cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
+       if (!cells)
+               return;
+
+       base = 0;
+       for (i = 0; i < nr_resets_apbc; i++) {
+               cells[base + i].clk_id = apbc_gate_clks[i].id;
+               cells[base + i].reg =
+                       pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[base + i].flags = 0;
+               cells[base + i].lock = apbc_gate_clks[i].lock;
+               cells[base + i].bits = 0x4;
+       }
+
+       base = nr_resets_apbc;
+       for (i = 0; i < nr_resets_apbcp; i++) {
+               cells[base + i].clk_id = apbcp_gate_clks[i].id;
+               cells[base + i].reg =
+                       pxa_unit->apbc_base + apbc_gate_clks[i].offset;
+               cells[base + i].flags = 0;
+               cells[base + i].lock = apbc_gate_clks[i].lock;
+               cells[base + i].bits = 0x4;
+       }
+
+       mmp_clk_reset_register(np, cells, nr_resets);
+}
+
+static void __init pxa910_clk_init(struct device_node *np)
+{
+       struct pxa910_clk_unit *pxa_unit;
+
+       pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+       if (!pxa_unit)
+               return;
+
+       pxa_unit->mpmu_base = of_iomap(np, 0);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map mpmu registers\n");
+               return;
+       }
+
+       pxa_unit->apmu_base = of_iomap(np, 1);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apmu registers\n");
+               return;
+       }
+
+       pxa_unit->apbc_base = of_iomap(np, 2);
+       if (!pxa_unit->apbc_base) {
+               pr_err("failed to map apbc registers\n");
+               return;
+       }
+
+       pxa_unit->apbcp_base = of_iomap(np, 3);
+       if (!pxa_unit->mpmu_base) {
+               pr_err("failed to map apbcp registers\n");
+               return;
+       }
+
+       mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
+
+       pxa910_pll_init(pxa_unit);
+
+       pxa910_apb_periph_clk_init(pxa_unit);
+
+       pxa910_axi_periph_clk_init(pxa_unit);
+
+       pxa910_clk_reset_init(np, pxa_unit);
+}
+
+CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);
index 014396b028a2c8c137723ccf2063f2dba6404f02..93e967c0f972f954ef1f7af9bb2f90e0c3241cae 100644 (file)
@@ -47,7 +47,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
        .factor = 2,
        .num_mask = 0x1fff,
        .den_mask = 0x1fff,
@@ -55,7 +55,7 @@ static struct clk_factor_masks uart_factor_masks = {
        .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
        {.num = 8125, .den = 1536},     /*14.745MHZ */
 };
 
@@ -158,7 +158,7 @@ void __init pxa168_clk_init(void)
        uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(uart_pll, 14745600);
        clk_register_clkdev(uart_pll, "uart_pll", NULL);
 
index 9efc6a47535d3bf07747e3373078daef8162794a..993abcdb32cce825fdb1d2ea835cb69f3ecf94fc 100644 (file)
@@ -45,7 +45,7 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static struct clk_factor_masks uart_factor_masks = {
+static struct mmp_clk_factor_masks uart_factor_masks = {
        .factor = 2,
        .num_mask = 0x1fff,
        .den_mask = 0x1fff,
@@ -53,7 +53,7 @@ static struct clk_factor_masks uart_factor_masks = {
        .den_shift = 0,
 };
 
-static struct clk_factor_tbl uart_factor_tbl[] = {
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
        {.num = 8125, .den = 1536},     /*14.745MHZ */
 };
 
@@ -163,7 +163,7 @@ void __init pxa910_clk_init(void)
        uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(uart_pll, 14745600);
        clk_register_clkdev(uart_pll, "uart_pll", NULL);
 
diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c
new file mode 100644 (file)
index 0000000..cf038ef
--- /dev/null
@@ -0,0 +1,192 @@
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
+               int nr_clks)
+{
+       static struct clk **clk_table;
+
+       clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
+       if (!clk_table)
+               return;
+
+       unit->clk_table = clk_table;
+       unit->nr_clks = nr_clks;
+       unit->clk_data.clks = clk_table;
+       unit->clk_data.clk_num = nr_clks;
+       of_clk_add_provider(np, of_clk_src_onecell_get, &unit->clk_data);
+}
+
+void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_rate_clk *clks,
+                               int size)
+{
+       int i;
+       struct clk *clk;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_fixed_rate(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       clks[i].fixed_rate);
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_factor_clk *clks,
+                               int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_fixed_factor(NULL, clks[i].name,
+                                               clks[i].parent_name,
+                                               clks[i].flags, clks[i].mult,
+                                               clks[i].div);
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_general_gate_clk *clks,
+                               void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_gate(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].bit_idx,
+                                       clks[i].gate_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_gate_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_gate_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = mmp_clk_register_gate(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].mask,
+                                       clks[i].val_enable,
+                                       clks[i].val_disable,
+                                       clks[i].gate_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_mux_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_mux_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_mux(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].num_parents,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].shift,
+                                       clks[i].width,
+                                       clks[i].mux_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_register_div_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_div_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               clk = clk_register_divider(NULL, clks[i].name,
+                                       clks[i].parent_name,
+                                       clks[i].flags,
+                                       base + clks[i].offset,
+                                       clks[i].shift,
+                                       clks[i].width,
+                                       clks[i].div_flags,
+                                       clks[i].lock);
+
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
+
+void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
+                       struct clk *clk)
+{
+       if (IS_ERR_OR_NULL(clk)) {
+               pr_err("CLK %d has invalid pointer %p\n", id, clk);
+               return;
+       }
+       if (id > unit->nr_clks) {
+               pr_err("CLK %d is invalid\n", id);
+               return;
+       }
+
+       unit->clk_table[id] = clk;
+}
index ab86dd4a416a5fa6b75aa74d7588894e7b8c4c2e..adf9b711b03702e61c989b315124b66aafa6c07a 100644 (file)
 #define APBC_NO_BUS_CTRL       BIT(0)
 #define APBC_POWER_CTRL                BIT(1)
 
-struct clk_factor_masks {
-       unsigned int    factor;
-       unsigned int    num_mask;
-       unsigned int    den_mask;
-       unsigned int    num_shift;
-       unsigned int    den_shift;
+
+/* Clock type "factor" */
+struct mmp_clk_factor_masks {
+       unsigned int factor;
+       unsigned int num_mask;
+       unsigned int den_mask;
+       unsigned int num_shift;
+       unsigned int den_shift;
 };
 
-struct clk_factor_tbl {
+struct mmp_clk_factor_tbl {
        unsigned int num;
        unsigned int den;
 };
 
+struct mmp_clk_factor {
+       struct clk_hw hw;
+       void __iomem *base;
+       struct mmp_clk_factor_masks *masks;
+       struct mmp_clk_factor_tbl *ftbl;
+       unsigned int ftbl_cnt;
+       spinlock_t *lock;
+};
+
+extern struct clk *mmp_clk_register_factor(const char *name,
+               const char *parent_name, unsigned long flags,
+               void __iomem *base, struct mmp_clk_factor_masks *masks,
+               struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+               spinlock_t *lock);
+
+/* Clock type "mix" */
+#define MMP_CLK_BITS_MASK(width, shift)                        \
+               (((1 << (width)) - 1) << (shift))
+#define MMP_CLK_BITS_GET_VAL(data, width, shift)       \
+               ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
+#define MMP_CLK_BITS_SET_VAL(val, width, shift)                \
+               (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
+
+enum {
+       MMP_CLK_MIX_TYPE_V1,
+       MMP_CLK_MIX_TYPE_V2,
+       MMP_CLK_MIX_TYPE_V3,
+};
+
+/* The register layout */
+struct mmp_clk_mix_reg_info {
+       void __iomem *reg_clk_ctrl;
+       void __iomem *reg_clk_sel;
+       u8 width_div;
+       u8 shift_div;
+       u8 width_mux;
+       u8 shift_mux;
+       u8 bit_fc;
+};
+
+/* The suggested clock table from user. */
+struct mmp_clk_mix_clk_table {
+       unsigned long rate;
+       u8 parent_index;
+       unsigned int divisor;
+       unsigned int valid;
+};
+
+struct mmp_clk_mix_config {
+       struct mmp_clk_mix_reg_info reg_info;
+       struct mmp_clk_mix_clk_table *table;
+       unsigned int table_size;
+       u32 *mux_table;
+       struct clk_div_table *div_table;
+       u8 div_flags;
+       u8 mux_flags;
+};
+
+struct mmp_clk_mix {
+       struct clk_hw hw;
+       struct mmp_clk_mix_reg_info reg_info;
+       struct mmp_clk_mix_clk_table *table;
+       u32 *mux_table;
+       struct clk_div_table *div_table;
+       unsigned int table_size;
+       u8 div_flags;
+       u8 mux_flags;
+       unsigned int type;
+       spinlock_t *lock;
+};
+
+extern const struct clk_ops mmp_clk_mix_ops;
+extern struct clk *mmp_clk_register_mix(struct device *dev,
+                                       const char *name,
+                                       const char **parent_names,
+                                       u8 num_parents,
+                                       unsigned long flags,
+                                       struct mmp_clk_mix_config *config,
+                                       spinlock_t *lock);
+
+
+/* Clock type "gate". MMP private gate */
+#define MMP_CLK_GATE_NEED_DELAY                BIT(0)
+
+struct mmp_clk_gate {
+       struct clk_hw hw;
+       void __iomem *reg;
+       u32 mask;
+       u32 val_enable;
+       u32 val_disable;
+       unsigned int flags;
+       spinlock_t *lock;
+};
+
+extern const struct clk_ops mmp_clk_gate_ops;
+extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+                       const char *parent_name, unsigned long flags,
+                       void __iomem *reg, u32 mask, u32 val_enable,
+                       u32 val_disable, unsigned int gate_flags,
+                       spinlock_t *lock);
+
+
 extern struct clk *mmp_clk_register_pll2(const char *name,
                const char *parent_name, unsigned long flags);
 extern struct clk *mmp_clk_register_apbc(const char *name,
@@ -28,8 +132,108 @@ extern struct clk *mmp_clk_register_apbc(const char *name,
 extern struct clk *mmp_clk_register_apmu(const char *name,
                const char *parent_name, void __iomem *base, u32 enable_mask,
                spinlock_t *lock);
-extern struct clk *mmp_clk_register_factor(const char *name,
-               const char *parent_name, unsigned long flags,
-               void __iomem *base, struct clk_factor_masks *masks,
-               struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+
+struct mmp_clk_unit {
+       unsigned int nr_clks;
+       struct clk **clk_table;
+       struct clk_onecell_data clk_data;
+};
+
+struct mmp_param_fixed_rate_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long fixed_rate;
+};
+void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_rate_clk *clks,
+                               int size);
+
+struct mmp_param_fixed_factor_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long mult;
+       unsigned long div;
+       unsigned long flags;
+};
+void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_fixed_factor_clk *clks,
+                               int size);
+
+struct mmp_param_general_gate_clk {
+       unsigned int id;
+       const char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long offset;
+       u8 bit_idx;
+       u8 gate_flags;
+       spinlock_t *lock;
+};
+void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
+                               struct mmp_param_general_gate_clk *clks,
+                               void __iomem *base, int size);
+
+struct mmp_param_gate_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long offset;
+       u32 mask;
+       u32 val_enable;
+       u32 val_disable;
+       unsigned int gate_flags;
+       spinlock_t *lock;
+};
+void mmp_register_gate_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_gate_clk *clks,
+                       void __iomem *base, int size);
+
+struct mmp_param_mux_clk {
+       unsigned int id;
+       char *name;
+       const char **parent_name;
+       u8 num_parents;
+       unsigned long flags;
+       unsigned long offset;
+       u8 shift;
+       u8 width;
+       u8 mux_flags;
+       spinlock_t *lock;
+};
+void mmp_register_mux_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_mux_clk *clks,
+                       void __iomem *base, int size);
+
+struct mmp_param_div_clk {
+       unsigned int id;
+       char *name;
+       const char *parent_name;
+       unsigned long flags;
+       unsigned long offset;
+       u8 shift;
+       u8 width;
+       u8 div_flags;
+       spinlock_t *lock;
+};
+void mmp_register_div_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_div_clk *clks,
+                       void __iomem *base, int size);
+
+#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc)    \
+{                                                      \
+       .width_div = (w_d),                             \
+       .shift_div = (s_d),                             \
+       .width_mux = (w_m),                             \
+       .shift_mux = (s_m),                             \
+       .bit_fc = (fc),                                 \
+}
+
+void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
+               int nr_clks);
+void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
+               struct clk *clk);
 #endif
diff --git a/drivers/clk/mmp/reset.c b/drivers/clk/mmp/reset.c
new file mode 100644 (file)
index 0000000..b54da1f
--- /dev/null
@@ -0,0 +1,99 @@
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+
+#include "reset.h"
+
+#define rcdev_to_unit(rcdev) container_of(rcdev, struct mmp_clk_reset_unit, rcdev)
+
+static int mmp_of_reset_xlate(struct reset_controller_dev *rcdev,
+                         const struct of_phandle_args *reset_spec)
+{
+       struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+       struct mmp_clk_reset_cell *cell;
+       int i;
+
+       if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+               return -EINVAL;
+
+       for (i = 0; i < rcdev->nr_resets; i++) {
+               cell = &unit->cells[i];
+               if (cell->clk_id == reset_spec->args[0])
+                       break;
+       }
+
+       if (i == rcdev->nr_resets)
+               return -EINVAL;
+
+       return i;
+}
+
+static int mmp_clk_reset_assert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+       struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+       struct mmp_clk_reset_cell *cell;
+       unsigned long flags = 0;
+       u32 val;
+
+       cell = &unit->cells[id];
+       if (cell->lock)
+               spin_lock_irqsave(cell->lock, flags);
+
+       val = readl(cell->reg);
+       val |= cell->bits;
+       writel(val, cell->reg);
+
+       if (cell->lock)
+               spin_unlock_irqrestore(cell->lock, flags);
+
+       return 0;
+}
+
+static int mmp_clk_reset_deassert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+       struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
+       struct mmp_clk_reset_cell *cell;
+       unsigned long flags = 0;
+       u32 val;
+
+       cell = &unit->cells[id];
+       if (cell->lock)
+               spin_lock_irqsave(cell->lock, flags);
+
+       val = readl(cell->reg);
+       val &= ~cell->bits;
+       writel(val, cell->reg);
+
+       if (cell->lock)
+               spin_unlock_irqrestore(cell->lock, flags);
+
+       return 0;
+}
+
+static struct reset_control_ops mmp_clk_reset_ops = {
+       .assert         = mmp_clk_reset_assert,
+       .deassert       = mmp_clk_reset_deassert,
+};
+
+void mmp_clk_reset_register(struct device_node *np,
+                       struct mmp_clk_reset_cell *cells, int nr_resets)
+{
+       struct mmp_clk_reset_unit *unit;
+
+       unit = kzalloc(sizeof(*unit), GFP_KERNEL);
+       if (!unit)
+               return;
+
+       unit->cells = cells;
+       unit->rcdev.of_reset_n_cells = 1;
+       unit->rcdev.nr_resets = nr_resets;
+       unit->rcdev.ops = &mmp_clk_reset_ops;
+       unit->rcdev.of_node = np;
+       unit->rcdev.of_xlate = mmp_of_reset_xlate;
+
+       reset_controller_register(&unit->rcdev);
+}
diff --git a/drivers/clk/mmp/reset.h b/drivers/clk/mmp/reset.h
new file mode 100644 (file)
index 0000000..be8b1a7
--- /dev/null
@@ -0,0 +1,31 @@
+#ifndef __MACH_MMP_CLK_RESET_H
+#define __MACH_MMP_CLK_RESET_H
+
+#include <linux/reset-controller.h>
+
+#define MMP_RESET_INVERT       1
+
+struct mmp_clk_reset_cell {
+       unsigned int clk_id;
+       void __iomem *reg;
+       u32 bits;
+       unsigned int flags;
+       spinlock_t *lock;
+};
+
+struct mmp_clk_reset_unit {
+       struct reset_controller_dev rcdev;
+       struct mmp_clk_reset_cell *cells;
+};
+
+#ifdef CONFIG_RESET_CONTROLLER
+void mmp_clk_reset_register(struct device_node *np,
+                       struct mmp_clk_reset_cell *cells, int nr_resets);
+#else
+static inline void mmp_clk_reset_register(struct device_node *np,
+                       struct mmp_clk_reset_cell *cells, int nr_resets)
+{
+}
+#endif
+
+#endif
index 4ff2abcd500b8e2109241b56152eeef6dd46f0e0..38e9153446059a1fb0c0728c841517cf99747f40 100644 (file)
@@ -1,2 +1,3 @@
 obj-y                          += clk-pxa.o
+obj-$(CONFIG_PXA25x)           += clk-pxa25x.o
 obj-$(CONFIG_PXA27x)           += clk-pxa27x.o
index ef3c05389c0aeb4704a6f2c2e23720eda6311a83..4e834753ab094500677811702c37ad005503929b 100644 (file)
@@ -26,12 +26,20 @@ static struct clk_onecell_data onecell_data = {
        .clk_num = CLK_MAX,
 };
 
-#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
+struct pxa_clk {
+       struct clk_hw hw;
+       struct clk_fixed_factor lp;
+       struct clk_fixed_factor hp;
+       struct clk_gate gate;
+       bool (*is_in_low_power)(void);
+};
+
+#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
 
 static unsigned long cken_recalc_rate(struct clk_hw *hw,
                                      unsigned long parent_rate)
 {
-       struct pxa_clk_cken *pclk = to_pxa_clk(hw);
+       struct pxa_clk *pclk = to_pxa_clk(hw);
        struct clk_fixed_factor *fix;
 
        if (!pclk->is_in_low_power || pclk->is_in_low_power())
@@ -48,7 +56,7 @@ static struct clk_ops cken_rate_ops = {
 
 static u8 cken_get_parent(struct clk_hw *hw)
 {
-       struct pxa_clk_cken *pclk = to_pxa_clk(hw);
+       struct pxa_clk *pclk = to_pxa_clk(hw);
 
        if (!pclk->is_in_low_power)
                return 0;
@@ -69,29 +77,32 @@ void __init clkdev_pxa_register(int ckid, const char *con_id,
                clk_register_clkdev(clk, con_id, dev_id);
 }
 
-int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
+int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks)
 {
        int i;
-       struct pxa_clk_cken *pclk;
+       struct pxa_clk *pxa_clk;
        struct clk *clk;
 
        for (i = 0; i < nb_clks; i++) {
-               pclk = clks + i;
-               pclk->gate.lock = &lock;
-               clk = clk_register_composite(NULL, pclk->name,
-                                            pclk->parent_names, 2,
-                                            &pclk->hw, &cken_mux_ops,
-                                            &pclk->hw, &cken_rate_ops,
-                                            &pclk->gate.hw, &clk_gate_ops,
-                                            pclk->flags);
-               clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
-                                   clk);
+               pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
+               pxa_clk->is_in_low_power = clks[i].is_in_low_power;
+               pxa_clk->lp = clks[i].lp;
+               pxa_clk->hp = clks[i].hp;
+               pxa_clk->gate = clks[i].gate;
+               pxa_clk->gate.lock = &lock;
+               clk = clk_register_composite(NULL, clks[i].name,
+                                            clks[i].parent_names, 2,
+                                            &pxa_clk->hw, &cken_mux_ops,
+                                            &pxa_clk->hw, &cken_rate_ops,
+                                            &pxa_clk->gate.hw, &clk_gate_ops,
+                                            clks[i].flags);
+               clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
+                                   clks[i].dev_id, clk);
        }
        return 0;
 }
 
-static void __init pxa_dt_clocks_init(struct device_node *np)
+void __init clk_pxa_dt_common_init(struct device_node *np)
 {
        of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
 }
-CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
index 5fe219d06b490c49a7203dd547fe65b537089c73..323965430111943b33dad32b3e8d5a889c7dead2 100644 (file)
@@ -25,7 +25,7 @@
        static struct clk_ops name ## _rate_ops = {             \
                .recalc_rate = name ## _get_rate,               \
        };                                                      \
-       static struct clk *clk_register_ ## name(void)          \
+       static struct clk * __init clk_register_ ## name(void)  \
        {                                                       \
                return clk_register_composite(NULL, clk_name,   \
                        name ## _parents,                       \
@@ -40,7 +40,7 @@
        static struct clk_ops name ## _rate_ops = {             \
                .recalc_rate = name ## _get_rate,               \
        };                                                      \
-       static struct clk *clk_register_ ## name(void)          \
+       static struct clk * __init clk_register_ ## name(void)  \
        {                                                       \
                return clk_register_composite(NULL, clk_name,   \
                        name ## _parents,                       \
@@ -66,7 +66,7 @@
  *  |    Clock   | --- | / div_hp  |
  *  +------------+     +-----------+
  */
-struct pxa_clk_cken {
+struct desc_clk_cken {
        struct clk_hw hw;
        int ckid;
        const char *name;
@@ -102,6 +102,7 @@ static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
 
 extern void clkdev_pxa_register(int ckid, const char *con_id,
                                const char *dev_id, struct clk *clk);
-extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
+extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
+void clk_pxa_dt_common_init(struct device_node *np);
 
 #endif
diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c
new file mode 100644 (file)
index 0000000..6cd88d9
--- /dev/null
@@ -0,0 +1,273 @@
+/*
+ * Marvell PXA25x family clocks
+ *
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
+ * should go away.
+ */
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <mach/pxa25x.h>
+#include <mach/pxa2xx-regs.h>
+
+#include <dt-bindings/clock/pxa-clock.h>
+#include "clk-pxa.h"
+
+#define KHz 1000
+#define MHz (1000 * 1000)
+
+enum {
+       PXA_CORE_RUN = 0,
+       PXA_CORE_TURBO,
+};
+
+/*
+ * Various clock factors driven by the CCCR register.
+ */
+
+/* Crystal Frequency to Memory Frequency Multiplier (L) */
+static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
+
+/* Memory Frequency to Run Mode Frequency Multiplier (M) */
+static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
+
+/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
+/* Note: we store the value N * 2 here. */
+static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
+
+static const char * const get_freq_khz[] = {
+       "core", "run", "cpll", "memory"
+};
+
+/*
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa25x_get_clk_frequency_khz(int info)
+{
+       struct clk *clk;
+       unsigned long clks[5];
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
+               clk = clk_get(NULL, get_freq_khz[i]);
+               if (IS_ERR(clk)) {
+                       clks[i] = 0;
+               } else {
+                       clks[i] = clk_get_rate(clk);
+                       clk_put(clk);
+               }
+       }
+
+       if (info) {
+               pr_info("Run Mode clock: %ld.%02ldMHz\n",
+                       clks[1] / 1000000, (clks[1] % 1000000) / 10000);
+               pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
+                       clks[2] / 1000000, (clks[2] % 1000000) / 10000);
+               pr_info("Memory clock: %ld.%02ldMHz\n",
+                       clks[3] / 1000000, (clks[3] % 1000000) / 10000);
+       }
+
+       return (unsigned int)clks[0];
+}
+
+static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
+                                               unsigned long parent_rate)
+{
+       unsigned long cccr = CCCR;
+       unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
+
+       return parent_rate / m;
+}
+PARENTS(clk_pxa25x_memory) = { "run" };
+RATE_RO_OPS(clk_pxa25x_memory, "memory");
+
+PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
+PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
+PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
+
+#define PXA25X_CKEN(dev_id, con_id, parents, mult, div,                        \
+                   bit, is_lp, flags)                                  \
+       PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,    \
+                is_lp,  &CKEN, CKEN_ ## bit, flags)
+#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)        \
+       PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp,     \
+                   div_hp, bit, NULL, 0)
+#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
+       PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp,    \
+                   div_hp, bit, NULL, 0)
+#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)  \
+       PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp,       \
+                   div_hp, bit, NULL, 0)
+
+#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)         \
+       PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
+                      &CKEN, CKEN_ ## bit, 0)
+#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)      \
+       PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
+                      &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
+
+static struct desc_clk_cken pxa25x_clocks[] __initdata = {
+       PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
+       PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
+       PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
+       PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
+       PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
+       PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
+       PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
+       PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
+
+       PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
+       PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
+                            clk_pxa25x_memory_parents, 0),
+};
+
+static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
+{
+       unsigned long clkcfg;
+       unsigned int t;
+
+       asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
+       t  = clkcfg & (1 << 0);
+       if (t)
+               return PXA_CORE_TURBO;
+       return PXA_CORE_RUN;
+}
+
+static unsigned long clk_pxa25x_core_get_rate(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       return parent_rate;
+}
+PARENTS(clk_pxa25x_core) = { "run", "cpll" };
+MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core");
+
+static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
+                                            unsigned long parent_rate)
+{
+       unsigned long cccr = CCCR;
+       unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+       return (parent_rate / n2) * 2;
+}
+PARENTS(clk_pxa25x_run) = { "cpll" };
+RATE_RO_OPS(clk_pxa25x_run, "run");
+
+static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
+       unsigned long parent_rate)
+{
+       unsigned long clkcfg, cccr = CCCR;
+       unsigned int l, m, n2, t;
+
+       asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
+       t = clkcfg & (1 << 0);
+       l  =  L_clk_mult[(cccr >> 0) & 0x1f];
+       m = M_clk_mult[(cccr >> 5) & 0x03];
+       n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+       if (t)
+               return m * l * n2 * parent_rate / 2;
+       return m * l * parent_rate;
+}
+PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
+RATE_RO_OPS(clk_pxa25x_cpll, "cpll");
+
+static void __init pxa25x_register_core(void)
+{
+       clk_register_clk_pxa25x_cpll();
+       clk_register_clk_pxa25x_run();
+       clkdev_pxa_register(CLK_CORE, "core", NULL,
+                           clk_register_clk_pxa25x_core());
+}
+
+static void __init pxa25x_register_plls(void)
+{
+       clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
+                               CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
+                               3686400);
+       clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+                               CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
+                               32768);
+       clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
+       clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
+                                 0, 26, 1);
+       clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
+                                 0, 40, 1);
+}
+
+static void __init pxa25x_base_clocks_init(void)
+{
+       pxa25x_register_plls();
+       pxa25x_register_core();
+       clk_register_clk_pxa25x_memory();
+}
+
+#define DUMMY_CLK(_con_id, _dev_id, _parent) \
+       { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
+struct dummy_clk {
+       const char *con_id;
+       const char *dev_id;
+       const char *parent;
+};
+static struct dummy_clk dummy_clks[] __initdata = {
+       DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
+       DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
+       DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
+       DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
+       DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
+       DUMMY_CLK("OSTIMER0", NULL, "osc_32_768khz"),
+       DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
+};
+
+static void __init pxa25x_dummy_clocks_init(void)
+{
+       struct clk *clk;
+       struct dummy_clk *d;
+       const char *name;
+       int i;
+
+       /*
+        * All pinctrl logic has been wiped out of the clock driver, especially
+        * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
+        * control (ie. pxa2xx_mfp_config() invocation).
+        */
+       for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
+               d = &dummy_clks[i];
+               name = d->dev_id ? d->dev_id : d->con_id;
+               clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
+               clk_register_clkdev(clk, d->con_id, d->dev_id);
+       }
+}
+
+int __init pxa25x_clocks_init(void)
+{
+       pxa25x_base_clocks_init();
+       pxa25x_dummy_clocks_init();
+       return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
+}
+
+static void __init pxa25x_dt_clocks_init(struct device_node *np)
+{
+       pxa25x_clocks_init();
+       clk_pxa_dt_common_init(np);
+}
+CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
+              pxa25x_dt_clocks_init);
index 88b9fe13fa444b2a81a3bd8a2588b035357d0048..5f9b54b024b9e1607b724c8ceb5dcfba7b58c992 100644 (file)
@@ -111,7 +111,7 @@ PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
        PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
                       &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
 
-static struct pxa_clk_cken pxa27x_clocks[] = {
+static struct desc_clk_cken pxa27x_clocks[] __initdata = {
        PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
        PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
        PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
@@ -368,3 +368,10 @@ static int __init pxa27x_clocks_init(void)
        return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
 }
 postcore_initcall(pxa27x_clocks_init);
+
+static void __init pxa27x_dt_clocks_init(struct device_node *np)
+{
+       pxa27x_clocks_init();
+       clk_pxa_dt_common_init(np);
+}
+CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
index beed49c79126bb1412cf7b217586aa8c0b6e532d..f88eb7dacd9730028f881f03825897b3ad807318 100644 (file)
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
                        RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-       GATE(0, "gpll_ddr", "gpll", 0,
+       GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 7, GFLAGS),
-       COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
+       COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
                        RK2928_CLKGATE_CON(0), 6, GFLAGS),
        GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
                        RK2928_CLKGATE_CON(0), 5, GFLAGS),
-       GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
+       GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-       COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
                        RK2928_CLKGATE_CON(3), 0, GFLAGS),
        COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         * the 480m are generated inside the usb block from these clocks,
         * but they are also a source for the hsicphy clock.
         */
-       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 5, GFLAGS),
-       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
        COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -320,9 +320,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
                        RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
                        RK2928_CLKGATE_CON(2), 6, GFLAGS),
-       COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
+       COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,
                        RK2928_CLKSEL_CON(23), 0,
-                       RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
+                       RK2928_CLKGATE_CON(2), 7, GFLAGS),
        MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
                        RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
 
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 
        /* aclk_cpu gates */
        GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
-       GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
-       GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
+       GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
+       GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
        /* hclk_cpu gates */
        GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
 
        /* hclk_peri gates */
-       GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
-       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
+       GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
+       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
        GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
        GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
        GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
@@ -457,18 +457,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
        GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
        GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
-       GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
-       GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
+       GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
+       GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
 
        /* aclk_peri */
        GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
        GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
-       GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
-       GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
-       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
+       GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
+       GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
+       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
 
        /* pclk_peri gates */
-       GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
+       GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
        GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
        GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
        GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
@@ -511,7 +511,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
                                                            | CLK_DIVIDER_READ_ONLY,
                        RK2928_CLKGATE_CON(4), 9, GFLAGS),
 
-       GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
+       GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(9), 4, GFLAGS),
 
        COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
@@ -618,7 +618,7 @@ PNAME(mux_hsicphy_p)                = { "sclk_otgphy0", "sclk_otgphy1",
                                    "gpll", "cpll" };
 
 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
-       COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
+       COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
 
@@ -633,7 +633,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK2928_CLKGATE_CON(4), 9, GFLAGS),
 
-       GATE(CORE_L2C, "core_l2c", "armclk", 0,
+       GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(9), 4, GFLAGS),
 
        COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
index 23278291da448de806a9a8929fe300c6952aafec..174589c95e33fcb5de8eb78689bbd2bb4895cea6 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/syscore_ops.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "clk.h"
 
@@ -83,11 +84,13 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
        RK3066_PLL_RATE( 742500000, 8, 495, 2),
        RK3066_PLL_RATE( 696000000, 1, 58, 2),
        RK3066_PLL_RATE( 600000000, 1, 50, 2),
-       RK3066_PLL_RATE( 594000000, 2, 198, 4),
+       RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
        RK3066_PLL_RATE( 552000000, 1, 46, 2),
        RK3066_PLL_RATE( 504000000, 1, 84, 4),
+       RK3066_PLL_RATE( 500000000, 3, 125, 2),
        RK3066_PLL_RATE( 456000000, 1, 76, 4),
        RK3066_PLL_RATE( 408000000, 1, 68, 4),
+       RK3066_PLL_RATE( 400000000, 3, 100, 2),
        RK3066_PLL_RATE( 384000000, 2, 128, 4),
        RK3066_PLL_RATE( 360000000, 1, 60, 4),
        RK3066_PLL_RATE( 312000000, 1, 52, 4),
@@ -173,14 +176,14 @@ PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 PNAME(mux_pll_src_cpll_gpll_p)         = { "cpll", "gpll" };
 PNAME(mux_pll_src_npll_cpll_gpll_p)    = { "npll", "cpll", "gpll" };
 PNAME(mux_pll_src_cpll_gpll_npll_p)    = { "cpll", "gpll", "npll" };
-PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
+PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
+PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
 
 PNAME(mux_mmc_src_p)   = { "cpll", "gpll", "xin24m", "xin24m" };
 PNAME(mux_i2s_pre_p)   = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_clkout_p)        = { "i2s_pre", "xin12m" };
 PNAME(mux_spdif_p)     = { "spdif_pre", "spdif_frac", "xin12m" };
 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
-PNAME(mux_uart0_pll_p) = { "cpll", "gpll", "usbphy_480m_src", "npll" };
 PNAME(mux_uart0_p)     = { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)     = { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)     = { "uart2_src", "uart2_frac", "xin24m" };
@@ -192,8 +195,8 @@ PNAME(mux_hsadcout_p)       = { "hsadc_src", "ext_hsadc" };
 PNAME(mux_edp_24m_p)   = { "ext_edp_24m", "xin24m" };
 PNAME(mux_tspout_p)    = { "cpll", "gpll", "npll", "xin27m" };
 
-PNAME(mux_usbphy480m_p)                = { "sclk_otgphy0", "sclk_otgphy1",
-                                   "sclk_otgphy2" };
+PNAME(mux_usbphy480m_p)                = { "sclk_otgphy1", "sclk_otgphy2",
+                                   "sclk_otgphy0" };
 PNAME(mux_hsicphy480m_p)       = { "cpll", "gpll", "usbphy480m_src" };
 PNAME(mux_hsicphy12m_p)                = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 
@@ -226,67 +229,67 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         * Clock-Architecture Diagram 1
         */
 
-       GATE(0, "apll_core", "apll", 0,
+       GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 1, GFLAGS),
-       GATE(0, "gpll_core", "gpll", 0,
+       GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 2, GFLAGS),
 
-       COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 0, GFLAGS),
-       COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 1, GFLAGS),
-       COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 2, GFLAGS),
-       COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
+       COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 3, GFLAGS),
-       COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
+       COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 4, GFLAGS),
-       COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
+       COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 5, GFLAGS),
-       COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
+       COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 6, GFLAGS),
        COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
                        RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 7, GFLAGS),
-       COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
+       COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                        RK3288_CLKGATE_CON(12), 8, GFLAGS),
        GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
                        RK3288_CLKGATE_CON(12), 9, GFLAGS),
-       GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
+       GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(12), 10, GFLAGS),
        GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
                        RK3288_CLKGATE_CON(12), 11, GFLAGS),
 
-       GATE(0, "dpll_ddr", "dpll", 0,
+       GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3288_CLKGATE_CON(0), 9, GFLAGS),
-       COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
+       COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
                                        DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 
-       GATE(0, "gpll_aclk_cpu", "gpll", 0,
+       GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 10, GFLAGS),
-       GATE(0, "cpll_aclk_cpu", "cpll", 0,
+       GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 11, GFLAGS),
-       COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
+       COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
-       DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
+       DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
                        RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
-       GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
+       GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 3, GFLAGS),
-       COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
+       COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
                        RK3288_CLKGATE_CON(0), 5, GFLAGS),
-       COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
+       COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
                        RK3288_CLKGATE_CON(0), 4, GFLAGS),
        GATE(0, "c2c_host", "aclk_cpu_src", 0,
@@ -294,7 +297,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
                        RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
                        RK3288_CLKGATE_CON(5), 4, GFLAGS),
-       GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
+       GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 7, GFLAGS),
 
        COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
@@ -305,7 +308,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKGATE_CON(4), 2, GFLAGS),
        MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
                        RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
-       COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
+       COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
                        RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
                        RK3288_CLKGATE_CON(4), 0, GFLAGS),
        GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
@@ -325,7 +328,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
                        RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
                        RK3288_CLKGATE_CON(4), 7, GFLAGS),
-       COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
+       COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
                        RK3288_CLKSEL_CON(41), 0,
                        RK3288_CLKGATE_CON(4), 8, GFLAGS),
        COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
@@ -373,12 +376,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
                RK3288_CLKGATE_CON(9), 1, GFLAGS),
 
-       COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
+       COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 0, GFLAGS),
        DIV(0, "hclk_vio", "aclk_vio0", 0,
                        RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
-       COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
+       COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 2, GFLAGS),
 
@@ -436,24 +439,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
        DIV(0, "pclk_pd_alive", "gpll", 0,
                        RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
-       COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
+       COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(5), 8, GFLAGS),
 
-       COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
+       COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
                        RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(5), 7, GFLAGS),
 
-       COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(2), 0, GFLAGS),
        COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
                        RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK3288_CLKGATE_CON(2), 3, GFLAGS),
-       COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
+       COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                        RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
                        RK3288_CLKGATE_CON(2), 2, GFLAGS),
-       GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
+       GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(2), 1, GFLAGS),
 
        /*
@@ -490,13 +493,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3288_CLKGATE_CON(4), 10, GFLAGS),
 
-       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+       GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 4, GFLAGS),
-       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+       GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 5, GFLAGS),
-       GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
+       GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 6, GFLAGS),
-       GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
+       GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(13), 7, GFLAGS),
 
        COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
@@ -517,7 +520,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(5), 6, GFLAGS),
 
-       COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
+       COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
                        RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
                        RK3288_CLKGATE_CON(1), 8, GFLAGS),
        COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
@@ -585,7 +588,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
        COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
                        RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
-                       RK3288_CLKGATE_CON(5), 15, GFLAGS),
+                       RK3288_CLKGATE_CON(5), 14, GFLAGS),
        COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
                        RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
                        RK3288_CLKGATE_CON(3), 6, GFLAGS),
@@ -601,19 +604,19 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         */
 
        /* aclk_cpu gates */
-       GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
-       GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
-       GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
+       GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
+       GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
+       GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
        GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
-       GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
-       GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
+       GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
+       GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
        GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
        GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 
        /* hclk_cpu gates */
        GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
        GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
-       GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
+       GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
        GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
        GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 
@@ -630,34 +633,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
        GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
        GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
-       GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
+       GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 
        /* ddrctrl [DDR Controller PHY clock] gates */
-       GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
-       GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
+       GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
+       GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 
        /* ddrphy gates */
-       GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
-       GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
+       GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
+       GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 
        /* aclk_peri gates */
-       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
+       GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
        GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
-       GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
-       GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
+       GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
+       GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
        GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
        GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 
        /* hclk_peri gates */
-       GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
-       GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
+       GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
+       GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
        GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
-       GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
+       GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
        GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
-       GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
-       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
-       GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
-       GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
+       GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
+       GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
+       GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
+       GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
        GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
        GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
        GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
@@ -669,7 +672,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 
        /* pclk_peri gates */
-       GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
+       GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
        GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
        GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
        GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
@@ -705,48 +708,48 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
        GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
        GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
-       GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
-       GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
+       GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
+       GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 
        /* pclk_pd_pmu gates */
-       GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
-       GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
-       GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
-       GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
+       GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
+       GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
+       GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
+       GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
        GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 
        /* hclk_vio gates */
        GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
        GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
        GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
-       GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
-       GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
+       GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
+       GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
        GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
        GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
        GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
-       GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
+       GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
        GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
        GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
        GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
        GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
-       GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
+       GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
        GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
-       GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
+       GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 
        /* aclk_vio0 gates */
        GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
        GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
-       GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
+       GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
        GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 
        /* aclk_vio1 gates */
        GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
        GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
-       GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
+       GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 
        /* aclk_rga_pre gates */
        GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
-       GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
+       GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 
        /*
         * Other ungrouped clocks.
@@ -762,6 +765,64 @@ static const char *rk3288_critical_clocks[] __initconst = {
        "hclk_peri",
 };
 
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+
+/* Some CRU registers will be reset in maskrom when the system
+ * wakes up from fastboot.
+ * So save them before suspend, restore them after resume.
+ */
+static const int rk3288_saved_cru_reg_ids[] = {
+       RK3288_MODE_CON,
+       RK3288_CLKSEL_CON(0),
+       RK3288_CLKSEL_CON(1),
+       RK3288_CLKSEL_CON(10),
+       RK3288_CLKSEL_CON(33),
+       RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+static int rk3288_clk_suspend(void)
+{
+       int i, reg_id;
+
+       for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+               reg_id = rk3288_saved_cru_reg_ids[i];
+
+               rk3288_saved_cru_regs[i] =
+                               readl_relaxed(rk3288_cru_base + reg_id);
+       }
+       return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+       int i, reg_id;
+
+       for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+               reg_id = rk3288_saved_cru_reg_ids[i];
+
+               writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
+                              rk3288_cru_base + reg_id);
+       }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+       .suspend = rk3288_clk_suspend,
+       .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+       rk3288_cru_base = reg_base;
+       register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
 static void __init rk3288_clk_init(struct device_node *np)
 {
        void __iomem *reg_base;
@@ -810,5 +871,6 @@ static void __init rk3288_clk_init(struct device_node *np)
                                  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
        rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+       rk3288_clk_sleep_init(reg_base);
 }
 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
index 880a266f01431b3b9e7040565d3a3e81f0716a8b..70559fab36b68df3eaf67593a1bb6722ab6a0175 100644 (file)
@@ -244,9 +244,6 @@ void __init rockchip_clk_register_branches(
                                        list->div_flags, &clk_lock);
                        break;
                case branch_fraction_divider:
-                       /* keep all gates untouched for now */
-                       flags |= CLK_IGNORE_UNUSED;
-
                        clk = rockchip_clk_register_frac_branch(list->name,
                                list->parent_names, list->num_parents,
                                reg_base, list->muxdiv_offset, list->div_flags,
@@ -256,18 +253,12 @@ void __init rockchip_clk_register_branches(
                case branch_gate:
                        flags |= CLK_SET_RATE_PARENT;
 
-                       /* keep all gates untouched for now */
-                       flags |= CLK_IGNORE_UNUSED;
-
                        clk = clk_register_gate(NULL, list->name,
                                list->parent_names[0], flags,
                                reg_base + list->gate_offset,
                                list->gate_shift, list->gate_flags, &clk_lock);
                        break;
                case branch_composite:
-                       /* keep all gates untouched for now */
-                       flags |= CLK_IGNORE_UNUSED;
-
                        clk = rockchip_clk_register_branch(list->name,
                                list->parent_names, list->num_parents,
                                reg_base, list->muxdiv_offset, list->mux_shift,
index ca009ab0a33a28ad507d83cf9cf0de183b33a09e..6baf6655b5c383598c4eae85f48de7c079f5c6c2 100644 (file)
@@ -62,6 +62,15 @@ enum rockchip_pll_type {
        .bwadj = (_nf >> 1),                    \
 }
 
+#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw)       \
+{                                                              \
+       .rate   = _rate##U,                                     \
+       .nr = _nr,                                              \
+       .nf = _nf,                                              \
+       .no = _no,                                              \
+       .bwadj = _bw,                                           \
+}
+
 struct rockchip_pll_rate_table {
        unsigned long rate;
        unsigned int nr;
index 6fb4bc602e8ac467d4489e51f30b642e5771dda7..006c6f294310d51e804bfda91b76e3eeb211b7e7 100644 (file)
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)       += clk.o clk-pll.o
 obj-$(CONFIG_SOC_EXYNOS3250)   += clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS4415)   += clk-exynos4415.o
 obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)   += clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)   += clk-exynos5410.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420)  += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
 obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-clkout.o
+obj-$(CONFIG_ARCH_EXYNOS7)     += clk-exynos7.o
 obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
 obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
new file mode 100644 (file)
index 0000000..c7208c7
--- /dev/null
@@ -0,0 +1,1142 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos4415 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/exynos4415.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_LEFTBUS            0x4200
+#define DIV_LEFTBUS            0x4500
+#define GATE_IP_LEFTBUS                0x4800
+#define GATE_IP_IMAGE          0x4930
+#define SRC_RIGHTBUS           0x8200
+#define DIV_RIGHTBUS           0x8500
+#define GATE_IP_RIGHTBUS       0x8800
+#define GATE_IP_PERIR          0x8960
+#define EPLL_LOCK              0xc010
+#define G3D_PLL_LOCK           0xc020
+#define DISP_PLL_LOCK          0xc030
+#define ISP_PLL_LOCK           0xc040
+#define EPLL_CON0              0xc110
+#define EPLL_CON1              0xc114
+#define EPLL_CON2              0xc118
+#define G3D_PLL_CON0           0xc120
+#define G3D_PLL_CON1           0xc124
+#define G3D_PLL_CON2           0xc128
+#define ISP_PLL_CON0           0xc130
+#define ISP_PLL_CON1           0xc134
+#define ISP_PLL_CON2           0xc138
+#define DISP_PLL_CON0          0xc140
+#define DISP_PLL_CON1          0xc144
+#define DISP_PLL_CON2          0xc148
+#define SRC_TOP0               0xc210
+#define SRC_TOP1               0xc214
+#define SRC_CAM                        0xc220
+#define SRC_TV                 0xc224
+#define SRC_MFC                        0xc228
+#define SRC_G3D                        0xc22c
+#define SRC_LCD                        0xc234
+#define SRC_ISP                        0xc238
+#define SRC_MAUDIO             0xc23c
+#define SRC_FSYS               0xc240
+#define SRC_PERIL0             0xc250
+#define SRC_PERIL1             0xc254
+#define SRC_CAM1               0xc258
+#define SRC_TOP_ISP0           0xc25c
+#define SRC_TOP_ISP1           0xc260
+#define SRC_MASK_TOP           0xc310
+#define SRC_MASK_CAM           0xc320
+#define SRC_MASK_TV            0xc324
+#define SRC_MASK_LCD           0xc334
+#define SRC_MASK_ISP           0xc338
+#define SRC_MASK_MAUDIO                0xc33c
+#define SRC_MASK_FSYS          0xc340
+#define SRC_MASK_PERIL0                0xc350
+#define SRC_MASK_PERIL1                0xc354
+#define DIV_TOP                        0xc510
+#define DIV_CAM                        0xc520
+#define DIV_TV                 0xc524
+#define DIV_MFC                        0xc528
+#define DIV_G3D                        0xc52c
+#define DIV_LCD                        0xc534
+#define DIV_ISP                        0xc538
+#define DIV_MAUDIO             0xc53c
+#define DIV_FSYS0              0xc540
+#define DIV_FSYS1              0xc544
+#define DIV_FSYS2              0xc548
+#define DIV_PERIL0             0xc550
+#define DIV_PERIL1             0xc554
+#define DIV_PERIL2             0xc558
+#define DIV_PERIL3             0xc55c
+#define DIV_PERIL4             0xc560
+#define DIV_PERIL5             0xc564
+#define DIV_CAM1               0xc568
+#define DIV_TOP_ISP1           0xc56c
+#define DIV_TOP_ISP0           0xc570
+#define CLKDIV2_RATIO          0xc580
+#define GATE_SCLK_CAM          0xc820
+#define GATE_SCLK_TV           0xc824
+#define GATE_SCLK_MFC          0xc828
+#define GATE_SCLK_G3D          0xc82c
+#define GATE_SCLK_LCD          0xc834
+#define GATE_SCLK_MAUDIO       0xc83c
+#define GATE_SCLK_FSYS         0xc840
+#define GATE_SCLK_PERIL                0xc850
+#define GATE_IP_CAM            0xc920
+#define GATE_IP_TV             0xc924
+#define GATE_IP_MFC            0xc928
+#define GATE_IP_G3D            0xc92c
+#define GATE_IP_LCD            0xc934
+#define GATE_IP_FSYS           0xc940
+#define GATE_IP_PERIL          0xc950
+#define GATE_BLOCK             0xc970
+#define APLL_LOCK              0x14000
+#define APLL_CON0              0x14100
+#define SRC_CPU                        0x14200
+#define DIV_CPU0               0x14500
+#define DIV_CPU1               0x14504
+
+enum exynos4415_plls {
+       apll, epll, g3d_pll, isp_pll, disp_pll,
+       nr_plls,
+};
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4415_clk_regs;
+static struct samsung_clk_provider *exynos4415_ctx;
+
+static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
+       SRC_LEFTBUS,
+       DIV_LEFTBUS,
+       GATE_IP_LEFTBUS,
+       GATE_IP_IMAGE,
+       SRC_RIGHTBUS,
+       DIV_RIGHTBUS,
+       GATE_IP_RIGHTBUS,
+       GATE_IP_PERIR,
+       EPLL_LOCK,
+       G3D_PLL_LOCK,
+       DISP_PLL_LOCK,
+       ISP_PLL_LOCK,
+       EPLL_CON0,
+       EPLL_CON1,
+       EPLL_CON2,
+       G3D_PLL_CON0,
+       G3D_PLL_CON1,
+       G3D_PLL_CON2,
+       ISP_PLL_CON0,
+       ISP_PLL_CON1,
+       ISP_PLL_CON2,
+       DISP_PLL_CON0,
+       DISP_PLL_CON1,
+       DISP_PLL_CON2,
+       SRC_TOP0,
+       SRC_TOP1,
+       SRC_CAM,
+       SRC_TV,
+       SRC_MFC,
+       SRC_G3D,
+       SRC_LCD,
+       SRC_ISP,
+       SRC_MAUDIO,
+       SRC_FSYS,
+       SRC_PERIL0,
+       SRC_PERIL1,
+       SRC_CAM1,
+       SRC_TOP_ISP0,
+       SRC_TOP_ISP1,
+       SRC_MASK_TOP,
+       SRC_MASK_CAM,
+       SRC_MASK_TV,
+       SRC_MASK_LCD,
+       SRC_MASK_ISP,
+       SRC_MASK_MAUDIO,
+       SRC_MASK_FSYS,
+       SRC_MASK_PERIL0,
+       SRC_MASK_PERIL1,
+       DIV_TOP,
+       DIV_CAM,
+       DIV_TV,
+       DIV_MFC,
+       DIV_G3D,
+       DIV_LCD,
+       DIV_ISP,
+       DIV_MAUDIO,
+       DIV_FSYS0,
+       DIV_FSYS1,
+       DIV_FSYS2,
+       DIV_PERIL0,
+       DIV_PERIL1,
+       DIV_PERIL2,
+       DIV_PERIL3,
+       DIV_PERIL4,
+       DIV_PERIL5,
+       DIV_CAM1,
+       DIV_TOP_ISP1,
+       DIV_TOP_ISP0,
+       CLKDIV2_RATIO,
+       GATE_SCLK_CAM,
+       GATE_SCLK_TV,
+       GATE_SCLK_MFC,
+       GATE_SCLK_G3D,
+       GATE_SCLK_LCD,
+       GATE_SCLK_MAUDIO,
+       GATE_SCLK_FSYS,
+       GATE_SCLK_PERIL,
+       GATE_IP_CAM,
+       GATE_IP_TV,
+       GATE_IP_MFC,
+       GATE_IP_G3D,
+       GATE_IP_LCD,
+       GATE_IP_FSYS,
+       GATE_IP_PERIL,
+       GATE_BLOCK,
+       APLL_LOCK,
+       APLL_CON0,
+       SRC_CPU,
+       DIV_CPU0,
+       DIV_CPU1,
+};
+
+static int exynos4415_clk_suspend(void)
+{
+       samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_clk_regs));
+
+       return 0;
+}
+
+static void exynos4415_clk_resume(void)
+{
+       samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_clk_regs));
+}
+
+static struct syscore_ops exynos4415_clk_syscore_ops = {
+       .suspend = exynos4415_clk_suspend,
+       .resume = exynos4415_clk_resume,
+};
+
+static void exynos4415_clk_sleep_init(void)
+{
+       exynos4415_clk_regs =
+               samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
+                                       ARRAY_SIZE(exynos4415_cmu_clk_regs));
+       if (!exynos4415_clk_regs) {
+               pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+               return;
+       }
+
+       register_syscore_ops(&exynos4415_clk_syscore_ops);
+}
+#else
+static inline void exynos4415_clk_sleep_init(void) { }
+#endif
+
+/* list of all parent clock list */
+PNAME(mout_g3d_pllsrc_p)       = { "fin_pll", };
+
+PNAME(mout_apll_p)             = { "fin_pll", "fout_apll", };
+PNAME(mout_g3d_pll_p)          = { "fin_pll", "fout_g3d_pll", };
+PNAME(mout_isp_pll_p)          = { "fin_pll", "fout_isp_pll", };
+PNAME(mout_disp_pll_p)         = { "fin_pll", "fout_disp_pll", };
+
+PNAME(mout_mpll_user_p)                = { "fin_pll", "div_mpll_pre", };
+PNAME(mout_epll_p)             = { "fin_pll", "fout_epll", };
+PNAME(mout_core_p)             = { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_hpm_p)              = { "mout_apll", "mout_mpll_user_c", };
+
+PNAME(mout_ebi_p)              = { "div_aclk_200", "div_aclk_160", };
+PNAME(mout_ebi_1_p)            = { "mout_ebi", "mout_g3d_pll", };
+
+PNAME(mout_gdl_p)              = { "mout_mpll_user_l", };
+PNAME(mout_gdr_p)              = { "mout_mpll_user_r", };
+
+PNAME(mout_aclk_266_p)         = { "mout_mpll_user_t", "mout_g3d_pll", };
+
+PNAME(group_epll_g3dpll_p)     = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_sclk_p)            = { "xxti", "xusbxti",
+                                   "none", "mout_isp_pll",
+                                   "none", "none", "div_mpll_pre",
+                                   "mout_epll", "mout_g3d_pll", };
+PNAME(group_spdif_p)           = { "mout_audio0", "mout_audio1",
+                                   "mout_audio2", "spdif_extclk", };
+PNAME(group_sclk_audio2_p)     = { "audiocdclk2", "none",
+                                   "none", "mout_isp_pll",
+                                   "mout_disp_pll", "xusbxti",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_sclk_audio1_p)     = { "audiocdclk1", "none",
+                                   "none", "mout_isp_pll",
+                                   "mout_disp_pll", "xusbxti",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_sclk_audio0_p)     = { "audiocdclk0", "none",
+                                   "none", "mout_isp_pll",
+                                   "mout_disp_pll", "xusbxti",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_fimc_lclk_p)       = { "xxti", "xusbxti",
+                                   "none", "mout_isp_pll",
+                                   "none", "mout_disp_pll",
+                                   "mout_mpll_user_t", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(group_sclk_fimd0_p)      = { "xxti", "xusbxti",
+                                   "m_bitclkhsdiv4_4l", "mout_isp_pll",
+                                   "mout_disp_pll", "sclk_hdmiphy",
+                                   "div_mpll_pre", "mout_epll",
+                                   "mout_g3d_pll", };
+PNAME(mout_hdmi_p)             = { "sclk_pixel", "sclk_hdmiphy" };
+PNAME(mout_mfc_p)              = { "mout_mfc_0", "mout_mfc_1" };
+PNAME(mout_g3d_p)              = { "mout_g3d_0", "mout_g3d_1" };
+PNAME(mout_jpeg_p)             = { "mout_jpeg_0", "mout_jpeg_1" };
+PNAME(mout_jpeg1_p)            = { "mout_epll", "mout_g3d_pll" };
+PNAME(group_aclk_isp0_300_p)   = { "mout_isp_pll", "div_mpll_pre" };
+PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
+PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
+PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
+PNAME(group_mout_mpll_user_t_p)        = { "mout_mpll_user_t" };
+
+static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
+       /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
+       FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
+};
+
+static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
+       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+};
+
+static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
+       /*
+        * NOTE: Following table is sorted by register address in ascending
+        * order and then bitfield shift in descending order, as it is done
+        * in the User's Manual. When adding new entries, please make sure
+        * that the order is preserved, to avoid merge conflicts and make
+        * further work with defined data easier.
+        */
+
+       /* SRC_LEFTBUS */
+       MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
+               SRC_LEFTBUS, 4, 1),
+       MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
+
+       /* SRC_RIGHTBUS */
+       MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
+               SRC_RIGHTBUS, 4, 1),
+       MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
+
+       /* SRC_TOP0 */
+       MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
+       MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
+               SRC_TOP0, 24, 1),
+       MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
+               SRC_TOP0, 20, 1),
+       MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
+               SRC_TOP0, 16, 1),
+       MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
+               SRC_TOP0, 12, 1),
+       MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
+               SRC_TOP0, 8, 1),
+       MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
+       MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
+
+       /* SRC_TOP1 */
+       MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
+               SRC_TOP1, 28, 1),
+       MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+               SRC_TOP1, 16, 1),
+       MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
+               SRC_TOP1, 12, 1),
+       MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
+               group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
+       MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
+               SRC_TOP1, 0, 1),
+
+       /* SRC_CAM */
+       MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
+       MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
+       MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
+       MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
+               12, 4),
+       MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
+               8, 4),
+       MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
+               4, 4),
+       MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
+               0, 4),
+
+       /* SRC_TV */
+       MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+
+       /* SRC_MFC */
+       MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+       MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
+       MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
+               1),
+
+       /* SRC_G3D */
+       MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+       MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
+       MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
+               1),
+
+       /* SRC_LCD */
+       MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
+       MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
+
+       /* SRC_ISP */
+       MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
+               16, 4),
+       MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
+               12, 4),
+       MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
+               8, 4),
+       MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
+               4, 4),
+       MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
+               0, 4),
+
+       /* SRC_MAUDIO */
+       MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
+               0, 4),
+
+       /* SRC_FSYS */
+       MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+       MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
+       MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+       MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
+
+       /* SRC_PERIL0 */
+       MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
+       MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
+       MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
+       MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
+
+       /* SRC_PERIL1 */
+       MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
+       MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
+       MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
+       MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
+       MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
+               4, 4),
+       MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
+               0, 4),
+
+       /* SRC_CPU */
+       MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
+               SRC_CPU, 24, 1),
+       MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
+       MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
+               CLK_MUX_READ_ONLY),
+       MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+               CLK_SET_RATE_PARENT, 0),
+
+       /* SRC_CAM1 */
+       MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
+               group_fimc_lclk_p, SRC_CAM1, 20, 1),
+       MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
+               group_fimc_lclk_p, SRC_CAM1, 16, 1),
+       MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
+       MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
+       MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
+               0, 1),
+
+       /* SRC_TOP_ISP0 */
+       MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
+               group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
+       MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
+               group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
+       MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
+               group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
+
+       /* SRC_TOP_ISP1 */
+       MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
+               group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
+       MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
+               group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
+};
+
+static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
+       /*
+        * NOTE: Following table is sorted by register address in ascending
+        * order and then bitfield shift in descending order, as it is done
+        * in the User's Manual. When adding new entries, please make sure
+        * that the order is preserved, to avoid merge conflicts and make
+        * further work with defined data easier.
+        */
+
+       /* DIV_LEFTBUS */
+       DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+       DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
+
+       /* DIV_RIGHTBUS */
+       DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+       DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
+
+       /* DIV_TOP */
+       DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
+               "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
+       DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
+       DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
+       DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
+       DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
+       DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
+
+       /* DIV_CAM */
+       DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+       DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+       DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+       DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
+               12, 4),
+       DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
+               8, 4),
+       DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
+               4, 4),
+       DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
+               0, 4),
+
+       /* DIV_TV */
+       DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
+
+       /* DIV_MFC */
+       DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+
+       /* DIV_G3D */
+       DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+
+       /* DIV_LCD */
+       DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
+       DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
+
+       /* DIV_ISP */
+       DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
+       DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
+               DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
+       DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
+               DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
+       DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
+
+       /* DIV_MAUDIO */
+       DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
+       DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+
+       /* DIV_FSYS0 */
+       DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
+
+       /* DIV_FSYS1 */
+       DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+       DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+
+       /* DIV_FSYS2 */
+       DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
+               CLK_SET_RATE_PARENT, 0),
+
+       /* DIV_PERIL0 */
+       DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+       DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+       DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+       DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+
+       /* DIV_PERIL1 */
+       DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+       DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+
+       /* DIV_PERIL2 */
+       DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
+               CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+
+       /* DIV_PERIL4 */
+       DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
+       DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+       DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
+       DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+
+       /* DIV_PERIL5 */
+       DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
+
+       /* DIV_CAM1 */
+       DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
+               "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
+       DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
+               "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
+       DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
+
+       /* DIV_CPU0 */
+       DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
+       DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+       DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
+       DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
+       DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
+       DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
+       DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
+       DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
+               CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+
+       /* DIV_CPU1 */
+       DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+       DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+};
+
+static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
+       /*
+        * NOTE: Following table is sorted by register address in ascending
+        * order and then bitfield shift in descending order, as it is done
+        * in the User's Manual. When adding new entries, please make sure
+        * that the order is preserved, to avoid merge conflicts and make
+        * further work with defined data easier.
+        */
+
+       /* GATE_IP_LEFTBUS */
+       GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
+               CLK_IGNORE_UNUSED, 0),
+
+       /* GATE_IP_IMAGE */
+       GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
+               9, 0, 0),
+       GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
+               8, 0, 0),
+       GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
+               7, 0, 0),
+       GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
+               5, 0, 0),
+       GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
+               4, 0, 0),
+       GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
+       GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
+
+       /* GATE_IP_RIGHTBUS */
+       GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
+               GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
+
+       /* GATE_IP_PERIR */
+       GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
+               GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
+               GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
+               GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
+               GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
+               GATE_IP_PERIR, 17, 0, 0),
+       GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
+       GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
+       GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
+       GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
+       GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
+               CLK_IGNORE_UNUSED, 0),
+
+       /* GATE_SCLK_CAM - non-completed */
+       GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
+               "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
+               CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
+               "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
+               10, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
+               GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
+               GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
+               GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+               GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
+               GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
+               GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
+               GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
+               GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_TV */
+       GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
+               GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
+               GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
+               GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_MFC */
+       GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
+               GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_G3D */
+       GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
+               GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_LCD */
+       GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
+               GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
+               GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
+               GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
+               GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_MAUDIO */
+       GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
+               GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
+               GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_FSYS */
+       GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
+               GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
+               GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+               GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
+               GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
+               GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_SCLK_PERIL */
+       GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
+               GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
+               GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
+               GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
+               GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
+               GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
+               GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
+               GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
+               GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
+               GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+               GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+               GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+               GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+               GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
+
+       /* GATE_IP_CAM */
+       GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
+               22, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
+               20, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
+               18, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
+               17, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
+               16, CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
+       GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
+       GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
+       GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
+       GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
+       GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
+       GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
+       GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
+       GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
+       GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
+       GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
+       GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
+
+       /* GATE_IP_TV */
+       GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
+       GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
+       GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
+       GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
+       GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
+
+       /* GATE_IP_MFC */
+       GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
+       GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
+       GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
+
+       /* GATE_IP_G3D */
+       GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
+
+       /* GATE_IP_LCD */
+       GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
+       GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
+       GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
+       GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
+       GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
+
+       /* GATE_IP_FSYS */
+       GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
+       GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
+               CLK_IGNORE_UNUSED, 0),
+       GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
+       GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
+               0, 0),
+       GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
+       GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+       GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
+       GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
+       GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
+       GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
+       GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
+
+       /* GATE_IP_PERIL */
+       GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
+       GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
+       GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
+       GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
+       GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
+       GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
+       GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
+       GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
+       GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
+       GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
+       GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
+       GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
+       GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
+       GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
+       GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
+       GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
+       GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+       GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
+       GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
+       GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
+       GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
+};
+
+/*
+ * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
+ */
+static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
+       PLL_35XX_RATE(1600000000, 400, 3,  1),
+       PLL_35XX_RATE(1500000000, 250, 2,  1),
+       PLL_35XX_RATE(1400000000, 175, 3,  0),
+       PLL_35XX_RATE(1300000000, 325, 3,  1),
+       PLL_35XX_RATE(1200000000, 400, 4,  1),
+       PLL_35XX_RATE(1100000000, 275, 3,  1),
+       PLL_35XX_RATE(1066000000, 533, 6,  1),
+       PLL_35XX_RATE(1000000000, 250, 3,  1),
+       PLL_35XX_RATE(960000000,  320, 4,  1),
+       PLL_35XX_RATE(900000000,  300, 4,  1),
+       PLL_35XX_RATE(850000000,  425, 6,  1),
+       PLL_35XX_RATE(800000000,  200, 3,  1),
+       PLL_35XX_RATE(700000000,  175, 3,  1),
+       PLL_35XX_RATE(667000000,  667, 12, 1),
+       PLL_35XX_RATE(600000000,  400, 4,  2),
+       PLL_35XX_RATE(550000000,  275, 3,  2),
+       PLL_35XX_RATE(533000000,  533, 6,  2),
+       PLL_35XX_RATE(520000000,  260, 3,  2),
+       PLL_35XX_RATE(500000000,  250, 3,  2),
+       PLL_35XX_RATE(440000000,  220, 3,  2),
+       PLL_35XX_RATE(400000000,  200, 3,  2),
+       PLL_35XX_RATE(350000000,  175, 3,  2),
+       PLL_35XX_RATE(300000000,  300, 3,  3),
+       PLL_35XX_RATE(266000000,  266, 3,  3),
+       PLL_35XX_RATE(200000000,  200, 3,  3),
+       PLL_35XX_RATE(160000000,  160, 3,  3),
+       PLL_35XX_RATE(100000000,  200, 3,  4),
+       { /* sentinel */ }
+};
+
+/* EPLL */
+static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
+       PLL_36XX_RATE(800000000, 200, 3, 1,     0),
+       PLL_36XX_RATE(288000000,  96, 2, 2,     0),
+       PLL_36XX_RATE(192000000, 128, 2, 3,     0),
+       PLL_36XX_RATE(144000000,  96, 2, 3,     0),
+       PLL_36XX_RATE(96000000,  128, 2, 4,     0),
+       PLL_36XX_RATE(84000000,  112, 2, 4,     0),
+       PLL_36XX_RATE(80750011,  107, 2, 4, 43691),
+       PLL_36XX_RATE(73728004,   98, 2, 4, 19923),
+       PLL_36XX_RATE(67987602,  271, 3, 5, 62285),
+       PLL_36XX_RATE(65911004,  175, 2, 5, 49982),
+       PLL_36XX_RATE(50000000,  200, 3, 5,     0),
+       PLL_36XX_RATE(49152003,  131, 2, 5,  4719),
+       PLL_36XX_RATE(48000000,  128, 2, 5,     0),
+       PLL_36XX_RATE(45250000,  181, 3, 5,     0),
+       { /* sentinel */ }
+};
+
+static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
+       [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+                       APLL_LOCK, APLL_CON0, NULL),
+       [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+                       EPLL_LOCK, EPLL_CON0, NULL),
+       [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
+                       "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
+       [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
+                       ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
+       [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
+                       "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
+};
+
+static void __init exynos4415_cmu_init(struct device_node *np)
+{
+       void __iomem *reg_base;
+
+       reg_base = of_iomap(np, 0);
+       if (!reg_base)
+               panic("%s: failed to map registers\n", __func__);
+
+       exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+       if (!exynos4415_ctx)
+               panic("%s: unable to allocate context.\n", __func__);
+
+       exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
+       exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
+       exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
+       exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
+       exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
+
+       samsung_clk_register_fixed_factor(exynos4415_ctx,
+                               exynos4415_fixed_factor_clks,
+                               ARRAY_SIZE(exynos4415_fixed_factor_clks));
+       samsung_clk_register_fixed_rate(exynos4415_ctx,
+                               exynos4415_fixed_rate_clks,
+                               ARRAY_SIZE(exynos4415_fixed_rate_clks));
+
+       samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
+                               ARRAY_SIZE(exynos4415_plls), reg_base);
+       samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
+                               ARRAY_SIZE(exynos4415_mux_clks));
+       samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
+                               ARRAY_SIZE(exynos4415_div_clks));
+       samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
+                               ARRAY_SIZE(exynos4415_gate_clks));
+
+       exynos4415_clk_sleep_init();
+
+       samsung_clk_of_add_provider(np, exynos4415_ctx);
+}
+CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define MPLL_LOCK              0x008
+#define MPLL_CON0              0x108
+#define MPLL_CON1              0x10c
+#define MPLL_CON2              0x110
+#define BPLL_LOCK              0x118
+#define BPLL_CON0              0x218
+#define BPLL_CON1              0x21c
+#define BPLL_CON2              0x220
+#define SRC_DMC                        0x300
+#define DIV_DMC1               0x504
+
+enum exynos4415_dmc_plls {
+       mpll, bpll,
+       nr_dmc_plls,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
+static struct samsung_clk_provider *exynos4415_dmc_ctx;
+
+static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
+       MPLL_LOCK,
+       MPLL_CON0,
+       MPLL_CON1,
+       MPLL_CON2,
+       BPLL_LOCK,
+       BPLL_CON0,
+       BPLL_CON1,
+       BPLL_CON2,
+       SRC_DMC,
+       DIV_DMC1,
+};
+
+static int exynos4415_dmc_clk_suspend(void)
+{
+       samsung_clk_save(exynos4415_dmc_ctx->reg_base,
+                               exynos4415_dmc_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+       return 0;
+}
+
+static void exynos4415_dmc_clk_resume(void)
+{
+       samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
+                               exynos4415_dmc_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+}
+
+static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
+       .suspend = exynos4415_dmc_clk_suspend,
+       .resume = exynos4415_dmc_clk_resume,
+};
+
+static void exynos4415_dmc_clk_sleep_init(void)
+{
+       exynos4415_dmc_clk_regs =
+               samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
+                               ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
+       if (!exynos4415_dmc_clk_regs) {
+               pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+               return;
+       }
+
+       register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
+}
+#else
+static inline void exynos4415_dmc_clk_sleep_init(void) { }
+#endif /* CONFIG_PM_SLEEP */
+
+PNAME(mout_mpll_p)             = { "fin_pll", "fout_mpll", };
+PNAME(mout_bpll_p)             = { "fin_pll", "fout_bpll", };
+PNAME(mbpll_p)                 = { "mout_mpll", "mout_bpll", };
+
+static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
+       MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
+       MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
+       MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
+       MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
+};
+
+static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
+       DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
+       DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
+       DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
+               DIV_DMC1, 19, 2),
+       DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
+       DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
+       DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
+};
+
+static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
+       [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
+               MPLL_LOCK, MPLL_CON0, NULL),
+       [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
+               BPLL_LOCK, BPLL_CON0, NULL),
+};
+
+static void __init exynos4415_cmu_dmc_init(struct device_node *np)
+{
+       void __iomem *reg_base;
+
+       reg_base = of_iomap(np, 0);
+       if (!reg_base)
+               panic("%s: failed to map registers\n", __func__);
+
+       exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
+       if (!exynos4415_dmc_ctx)
+               panic("%s: unable to allocate context.\n", __func__);
+
+       exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
+       exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
+
+       samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
+                               ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
+       samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
+                               ARRAY_SIZE(exynos4415_dmc_mux_clks));
+       samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
+                               ARRAY_SIZE(exynos4415_dmc_div_clks));
+
+       exynos4415_dmc_clk_sleep_init();
+
+       samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
+}
+CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
+               exynos4415_cmu_dmc_init);
index 2527e39aadcfbfafab2a0b5c97d4aab2e4809458..e2e5193d10490b0295805023c448c1c0b685d02d 100644 (file)
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/syscore_ops.h>
 
 #include "clk-exynos5260.h"
 #include "clk.h"
 
 #include <dt-bindings/clock/exynos5260-clk.h>
 
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
-       struct list_head node;
-       void __iomem *reg_base;
-       struct samsung_clk_reg_dump *rdump;
-       unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
-       /* list of pll clocks and respective count */
-       struct samsung_pll_clock *pll_clks;
-       unsigned int nr_pll_clks;
-       /* list of mux clocks and respective count */
-       struct samsung_mux_clock *mux_clks;
-       unsigned int nr_mux_clks;
-       /* list of div clocks and respective count */
-       struct samsung_div_clock *div_clks;
-       unsigned int nr_div_clks;
-       /* list of gate clocks and respective count */
-       struct samsung_gate_clock *gate_clks;
-       unsigned int nr_gate_clks;
-       /* list of fixed clocks and respective count */
-       struct samsung_fixed_rate_clock *fixed_clks;
-       unsigned int nr_fixed_clks;
-       /* total number of clocks with IDs assigned*/
-       unsigned int nr_clk_ids;
-
-       /* list and number of clocks registers */
-       unsigned long *clk_regs;
-       unsigned int nr_clk_regs;
-};
-
 /*
  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
        PLL_36XX_RATE(66000000, 176, 2, 5, 0),
 };
 
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
-       struct exynos5260_clock_reg_cache *cache;
-
-       list_for_each_entry(cache, &clock_reg_cache_list, node)
-               samsung_clk_save(cache->reg_base, cache->rdump,
-                               cache->rd_num);
-
-       return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
-       struct exynos5260_clock_reg_cache *cache;
-
-       list_for_each_entry(cache, &clock_reg_cache_list, node)
-               samsung_clk_restore(cache->reg_base, cache->rdump,
-                               cache->rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
-       .suspend = exynos5260_clk_suspend,
-       .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-                       unsigned long *rdump,
-                       unsigned long nr_rdump)
-{
-       struct exynos5260_clock_reg_cache *reg_cache;
-
-       reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
-                       GFP_KERNEL);
-       if (!reg_cache)
-               panic("could not allocate register cache.\n");
-
-       reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
-       if (!reg_cache->rdump)
-               panic("could not allocate register dump storage.\n");
-
-       if (list_empty(&clock_reg_cache_list))
-               register_syscore_ops(&exynos5260_clk_syscore_ops);
-
-       reg_cache->rd_num = nr_rdump;
-       reg_cache->reg_base = reg_base;
-       list_add_tail(&reg_cache->node, &clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
-                       unsigned long *rdump,
-                       unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
-                       struct exynos5260_cmu_info *cmu)
-{
-       void __iomem *reg_base;
-       struct samsung_clk_provider *ctx;
-
-       reg_base = of_iomap(np, 0);
-       if (!reg_base)
-               panic("%s: failed to map registers\n", __func__);
-
-       ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
-       if (!ctx)
-               panic("%s: unable to alllocate ctx\n", __func__);
-
-       if (cmu->pll_clks)
-               samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
-                       reg_base);
-       if (cmu->mux_clks)
-               samsung_clk_register_mux(ctx,  cmu->mux_clks,
-                       cmu->nr_mux_clks);
-       if (cmu->div_clks)
-               samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
-       if (cmu->gate_clks)
-               samsung_clk_register_gate(ctx, cmu->gate_clks,
-                       cmu->nr_gate_clks);
-       if (cmu->fixed_clks)
-               samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
-                       cmu->nr_fixed_clks);
-       if (cmu->clk_regs)
-               exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
-                       cmu->nr_clk_regs);
-
-       samsung_clk_of_add_provider(np, ctx);
-}
-
-
 /* CMU_AUD */
 
 static unsigned long aud_clk_regs[] __initdata = {
@@ -268,7 +135,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_aud_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = aud_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
@@ -280,7 +147,7 @@ static void __init exynos5260_clk_aud_init(struct device_node *np)
        cmu.clk_regs = aud_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
@@ -458,7 +325,7 @@ struct samsung_gate_clock disp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_disp_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = disp_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
@@ -470,7 +337,7 @@ static void __init exynos5260_clk_disp_init(struct device_node *np)
        cmu.clk_regs = disp_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
@@ -522,7 +389,7 @@ static struct samsung_pll_clock egl_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_egl_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = egl_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(egl_pll_clks);
@@ -534,7 +401,7 @@ static void __init exynos5260_clk_egl_init(struct device_node *np)
        cmu.clk_regs = egl_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
@@ -624,7 +491,7 @@ struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_fsys_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = fsys_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
@@ -634,7 +501,7 @@ static void __init exynos5260_clk_fsys_init(struct device_node *np)
        cmu.clk_regs = fsys_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
@@ -713,7 +580,7 @@ struct samsung_gate_clock g2d_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_g2d_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = g2d_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
@@ -725,7 +592,7 @@ static void __init exynos5260_clk_g2d_init(struct device_node *np)
        cmu.clk_regs = g2d_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
@@ -774,7 +641,7 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_g3d_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = g3d_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(g3d_pll_clks);
@@ -788,7 +655,7 @@ static void __init exynos5260_clk_g3d_init(struct device_node *np)
        cmu.clk_regs = g3d_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
@@ -909,7 +776,7 @@ struct samsung_gate_clock gscl_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_gscl_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = gscl_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
@@ -921,7 +788,7 @@ static void __init exynos5260_clk_gscl_init(struct device_node *np)
        cmu.clk_regs = gscl_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
@@ -1028,7 +895,7 @@ struct samsung_gate_clock isp_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_isp_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = isp_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
@@ -1040,7 +907,7 @@ static void __init exynos5260_clk_isp_init(struct device_node *np)
        cmu.clk_regs = isp_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
@@ -1092,7 +959,7 @@ static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_kfc_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = kfc_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(kfc_pll_clks);
@@ -1104,7 +971,7 @@ static void __init exynos5260_clk_kfc_init(struct device_node *np)
        cmu.clk_regs = kfc_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
@@ -1148,7 +1015,7 @@ struct samsung_gate_clock mfc_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_mfc_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = mfc_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
@@ -1160,7 +1027,7 @@ static void __init exynos5260_clk_mfc_init(struct device_node *np)
        cmu.clk_regs = mfc_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
@@ -1295,7 +1162,7 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_mif_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = mif_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(mif_pll_clks);
@@ -1309,7 +1176,7 @@ static void __init exynos5260_clk_mif_init(struct device_node *np)
        cmu.clk_regs = mif_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
@@ -1503,7 +1370,7 @@ struct samsung_gate_clock peri_gate_clks[] __initdata = {
 
 static void __init exynos5260_clk_peri_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.mux_clks = peri_mux_clks;
        cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
@@ -1515,7 +1382,7 @@ static void __init exynos5260_clk_peri_init(struct device_node *np)
        cmu.clk_regs = peri_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
@@ -1959,7 +1826,7 @@ static struct samsung_pll_clock top_pll_clks[] __initdata = {
 
 static void __init exynos5260_clk_top_init(struct device_node *np)
 {
-       struct exynos5260_cmu_info cmu = {0};
+       struct samsung_cmu_info cmu = {0};
 
        cmu.pll_clks = top_pll_clks;
        cmu.nr_pll_clks =  ARRAY_SIZE(top_pll_clks);
@@ -1975,7 +1842,7 @@ static void __init exynos5260_clk_top_init(struct device_node *np)
        cmu.clk_regs = top_clk_regs;
        cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
 
-       exynos5260_cmu_register_one(np, &cmu);
+       samsung_cmu_register_one(np, &cmu);
 }
 
 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644 (file)
index 0000000..ea4483b
--- /dev/null
@@ -0,0 +1,743 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include "clk.h"
+#include <dt-bindings/clock/exynos7-clk.h>
+
+/* Register Offset definitions for CMU_TOPC (0x10570000) */
+#define CC_PLL_LOCK            0x0000
+#define BUS0_PLL_LOCK          0x0004
+#define BUS1_DPLL_LOCK         0x0008
+#define MFC_PLL_LOCK           0x000C
+#define AUD_PLL_LOCK           0x0010
+#define CC_PLL_CON0            0x0100
+#define BUS0_PLL_CON0          0x0110
+#define BUS1_DPLL_CON0         0x0120
+#define MFC_PLL_CON0           0x0130
+#define AUD_PLL_CON0           0x0140
+#define MUX_SEL_TOPC0          0x0200
+#define MUX_SEL_TOPC1          0x0204
+#define MUX_SEL_TOPC2          0x0208
+#define MUX_SEL_TOPC3          0x020C
+#define DIV_TOPC0              0x0600
+#define DIV_TOPC1              0x0604
+#define DIV_TOPC3              0x060C
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
+       FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_bus0_pll_div4",
+               "ffac_topc_bus0_pll_div2", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
+       FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_bus0_pll_ctrl_p)    = { "fin_pll", "fout_bus0_pll" };
+PNAME(mout_bus1_pll_ctrl_p)    = { "fin_pll", "fout_bus1_pll" };
+PNAME(mout_cc_pll_ctrl_p)      = { "fin_pll", "fout_cc_pll" };
+PNAME(mout_mfc_pll_ctrl_p)     = { "fin_pll", "fout_mfc_pll" };
+
+PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
+       "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
+       "mout_sclk_mfc_pll_cmuc" };
+
+PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
+       "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
+PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
+       "ffac_topc_bus1_pll_div2"};
+PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
+       "ffac_topc_cc_pll_div2"};
+PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
+       "ffac_topc_mfc_pll_div2"};
+
+
+PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
+       "ffac_topc_bus0_pll_div2"};
+
+static unsigned long topc_clk_regs[] __initdata = {
+       CC_PLL_LOCK,
+       BUS0_PLL_LOCK,
+       BUS1_DPLL_LOCK,
+       MFC_PLL_LOCK,
+       AUD_PLL_LOCK,
+       CC_PLL_CON0,
+       BUS0_PLL_CON0,
+       BUS1_DPLL_CON0,
+       MFC_PLL_CON0,
+       AUD_PLL_CON0,
+       MUX_SEL_TOPC0,
+       MUX_SEL_TOPC1,
+       MUX_SEL_TOPC2,
+       MUX_SEL_TOPC3,
+       DIV_TOPC0,
+       DIV_TOPC1,
+       DIV_TOPC3,
+};
+
+static struct samsung_mux_clock topc_mux_clks[] __initdata = {
+       MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
+       MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
+       MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
+       MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
+
+       MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
+               MUX_SEL_TOPC0, 16, 2),
+       MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
+               MUX_SEL_TOPC0, 20, 1),
+       MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
+               MUX_SEL_TOPC0, 24, 1),
+       MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
+               MUX_SEL_TOPC0, 28, 1),
+
+       MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
+               MUX_SEL_TOPC1, 16, 1),
+
+       MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
+
+       MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
+};
+
+static struct samsung_div_clock topc_div_clks[] __initdata = {
+       DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
+               DIV_TOPC0, 4, 4),
+
+       DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
+               DIV_TOPC1, 24, 4),
+
+       DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
+               DIV_TOPC3, 0, 3),
+       DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
+               DIV_TOPC3, 8, 3),
+       DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
+               DIV_TOPC3, 12, 3),
+       DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
+               DIV_TOPC3, 16, 3),
+};
+
+static struct samsung_pll_clock topc_pll_clks[] __initdata = {
+       PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
+               BUS0_PLL_CON0, NULL),
+       PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
+               CC_PLL_CON0, NULL),
+       PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
+               BUS1_DPLL_CON0, NULL),
+       PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
+               MFC_PLL_CON0, NULL),
+       PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
+               AUD_PLL_CON0, NULL),
+};
+
+static struct samsung_cmu_info topc_cmu_info __initdata = {
+       .pll_clks               = topc_pll_clks,
+       .nr_pll_clks            = ARRAY_SIZE(topc_pll_clks),
+       .mux_clks               = topc_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(topc_mux_clks),
+       .div_clks               = topc_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(topc_div_clks),
+       .fixed_factor_clks      = topc_fixed_factor_clks,
+       .nr_fixed_factor_clks   = ARRAY_SIZE(topc_fixed_factor_clks),
+       .nr_clk_ids             = TOPC_NR_CLK,
+       .clk_regs               = topc_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(topc_clk_regs),
+};
+
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &topc_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
+       exynos7_clk_topc_init);
+
+/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
+#define MUX_SEL_TOP00                  0x0200
+#define MUX_SEL_TOP01                  0x0204
+#define MUX_SEL_TOP03                  0x020C
+#define MUX_SEL_TOP0_PERIC3            0x023C
+#define DIV_TOP03                      0x060C
+#define DIV_TOP0_PERIC3                        0x063C
+#define ENABLE_SCLK_TOP0_PERIC3                0x0A3C
+
+/* List of parent clocks for Muxes in CMU_TOP0 */
+PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
+PNAME(mout_cc_pll_p)   = { "fin_pll", "dout_sclk_cc_pll" };
+PNAME(mout_mfc_pll_p)  = { "fin_pll", "dout_sclk_mfc_pll" };
+
+PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
+       "ffac_top0_bus0_pll_div2"};
+PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
+       "ffac_top0_bus1_pll_div2"};
+PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
+       "ffac_top0_cc_pll_div2"};
+PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
+       "ffac_top0_mfc_pll_div2"};
+
+PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
+       "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
+       "mout_top0_half_mfc_pll"};
+
+static unsigned long top0_clk_regs[] __initdata = {
+       MUX_SEL_TOP00,
+       MUX_SEL_TOP01,
+       MUX_SEL_TOP03,
+       MUX_SEL_TOP0_PERIC3,
+       DIV_TOP03,
+       DIV_TOP0_PERIC3,
+       ENABLE_SCLK_TOP0_PERIC3,
+};
+
+static struct samsung_mux_clock top0_mux_clks[] __initdata = {
+       MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
+       MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
+       MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
+       MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
+
+       MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
+               MUX_SEL_TOP01, 4, 1),
+       MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
+               MUX_SEL_TOP01, 8, 1),
+       MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
+               MUX_SEL_TOP01, 12, 1),
+       MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
+               MUX_SEL_TOP01, 16, 1),
+
+       MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
+       MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+
+       MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
+       MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
+       MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
+       MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+};
+
+static struct samsung_div_clock top0_div_clks[] __initdata = {
+       DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
+               DIV_TOP03, 12, 6),
+       DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
+               DIV_TOP03, 20, 6),
+
+       DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
+       DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
+       DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
+       DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+};
+
+static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+       GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
+               ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
+       GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
+               ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
+       GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
+               ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
+       GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
+               ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+};
+
+static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
+       FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top0_cmu_info __initdata = {
+       .mux_clks               = top0_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(top0_mux_clks),
+       .div_clks               = top0_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(top0_div_clks),
+       .gate_clks              = top0_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(top0_gate_clks),
+       .fixed_factor_clks      = top0_fixed_factor_clks,
+       .nr_fixed_factor_clks   = ARRAY_SIZE(top0_fixed_factor_clks),
+       .nr_clk_ids             = TOP0_NR_CLK,
+       .clk_regs               = top0_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(top0_clk_regs),
+};
+
+static void __init exynos7_clk_top0_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &top0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
+       exynos7_clk_top0_init);
+
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define MUX_SEL_TOP10                  0x0200
+#define MUX_SEL_TOP11                  0x0204
+#define MUX_SEL_TOP13                  0x020C
+#define MUX_SEL_TOP1_FSYS0             0x0224
+#define MUX_SEL_TOP1_FSYS1             0x0228
+#define DIV_TOP13                      0x060C
+#define DIV_TOP1_FSYS0                 0x0624
+#define DIV_TOP1_FSYS1                 0x0628
+#define ENABLE_ACLK_TOP13              0x080C
+#define ENABLE_SCLK_TOP1_FSYS0         0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1         0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)    = { "fin_pll", "dout_sclk_bus0_pll" };
+PNAME(mout_top1_bus1_pll_p)    = { "fin_pll", "dout_sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p)      = { "fin_pll", "dout_sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p)     = { "fin_pll", "dout_sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+       "ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+       "ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+       "ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+       "ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+       "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+       "mout_top1_half_mfc_pll"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+       MUX_SEL_TOP10,
+       MUX_SEL_TOP11,
+       MUX_SEL_TOP13,
+       MUX_SEL_TOP1_FSYS0,
+       MUX_SEL_TOP1_FSYS1,
+       DIV_TOP13,
+       DIV_TOP1_FSYS0,
+       DIV_TOP1_FSYS1,
+       ENABLE_ACLK_TOP13,
+       ENABLE_SCLK_TOP1_FSYS0,
+       ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+       MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+       MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+       MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+               MUX_SEL_TOP10, 12, 1),
+       MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+               MUX_SEL_TOP10, 16, 1),
+
+       MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+               MUX_SEL_TOP11, 4, 1),
+       MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+               MUX_SEL_TOP11, 8, 1),
+       MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+               MUX_SEL_TOP11, 12, 1),
+       MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+               MUX_SEL_TOP11, 16, 1),
+
+       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+       MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+       MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+       MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+       DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
+               DIV_TOP13, 24, 4),
+       DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
+               DIV_TOP13, 28, 4),
+
+       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
+               DIV_TOP1_FSYS0, 24, 4),
+
+       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
+               DIV_TOP1_FSYS1, 24, 4),
+       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
+               DIV_TOP1_FSYS1, 28, 4),
+};
+
+static struct samsung_gate_clock top1_gate_clks[] __initdata = {
+       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+               ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+
+       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+               ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+               ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
+       FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
+       FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+};
+
+static struct samsung_cmu_info top1_cmu_info __initdata = {
+       .mux_clks               = top1_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(top1_mux_clks),
+       .div_clks               = top1_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(top1_div_clks),
+       .gate_clks              = top1_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(top1_gate_clks),
+       .fixed_factor_clks      = top1_fixed_factor_clks,
+       .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
+       .nr_clk_ids             = TOP1_NR_CLK,
+       .clk_regs               = top1_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(top1_clk_regs),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &top1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+       exynos7_clk_top1_init);
+
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define MUX_SEL_CCORE                  0x0200
+#define DIV_CCORE                      0x0600
+#define ENABLE_ACLK_CCORE0             0x0800
+#define ENABLE_ACLK_CCORE1             0x0804
+#define ENABLE_PCLK_CCORE              0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_133_p)   = { "fin_pll", "dout_aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+       MUX_SEL_CCORE,
+       ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+               MUX_SEL_CCORE, 1, 1),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+       GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+               ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static struct samsung_cmu_info ccore_cmu_info __initdata = {
+       .mux_clks               = ccore_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(ccore_mux_clks),
+       .gate_clks              = ccore_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(ccore_gate_clks),
+       .nr_clk_ids             = CCORE_NR_CLK,
+       .clk_regs               = ccore_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(ccore_clk_regs),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &ccore_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+       exynos7_clk_ccore_init);
+
+/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
+#define MUX_SEL_PERIC0                 0x0200
+#define ENABLE_PCLK_PERIC0             0x0900
+#define ENABLE_SCLK_PERIC0             0x0A00
+
+/* List of parent clocks for Muxes in CMU_PERIC0 */
+PNAME(mout_aclk_peric0_66_p)   = { "fin_pll", "dout_aclk_peric0_66" };
+PNAME(mout_sclk_uart0_p)       = { "fin_pll", "sclk_uart0" };
+
+static unsigned long peric0_clk_regs[] __initdata = {
+       MUX_SEL_PERIC0,
+       ENABLE_PCLK_PERIC0,
+       ENABLE_SCLK_PERIC0,
+};
+
+static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
+               MUX_SEL_PERIC0, 0, 1),
+       MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
+               MUX_SEL_PERIC0, 16, 1),
+};
+
+static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+       GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 8, 0, 0),
+       GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 9, 0, 0),
+       GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 10, 0, 0),
+       GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 11, 0, 0),
+       GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 12, 0, 0),
+       GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 13, 0, 0),
+       GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 14, 0, 0),
+       GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 16, 0, 0),
+       GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 20, 0, 0),
+       GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+               ENABLE_PCLK_PERIC0, 21, 0, 0),
+
+       GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
+               ENABLE_SCLK_PERIC0, 16, 0, 0),
+       GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
+};
+
+static struct samsung_cmu_info peric0_cmu_info __initdata = {
+       .mux_clks               = peric0_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(peric0_mux_clks),
+       .gate_clks              = peric0_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(peric0_gate_clks),
+       .nr_clk_ids             = PERIC0_NR_CLK,
+       .clk_regs               = peric0_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(peric0_clk_regs),
+};
+
+static void __init exynos7_clk_peric0_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &peric0_cmu_info);
+}
+
+/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
+#define MUX_SEL_PERIC10                        0x0200
+#define MUX_SEL_PERIC11                        0x0204
+#define ENABLE_PCLK_PERIC1             0x0900
+#define ENABLE_SCLK_PERIC10            0x0A00
+
+CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
+       exynos7_clk_peric0_init);
+
+/* List of parent clocks for Muxes in CMU_PERIC1 */
+PNAME(mout_aclk_peric1_66_p)   = { "fin_pll", "dout_aclk_peric1_66" };
+PNAME(mout_sclk_uart1_p)       = { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_p)       = { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_p)       = { "fin_pll", "sclk_uart3" };
+
+static unsigned long peric1_clk_regs[] __initdata = {
+       MUX_SEL_PERIC10,
+       MUX_SEL_PERIC11,
+       ENABLE_PCLK_PERIC1,
+       ENABLE_SCLK_PERIC10,
+};
+
+static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
+               MUX_SEL_PERIC10, 0, 1),
+
+       MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+               MUX_SEL_PERIC11, 20, 1),
+       MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+               MUX_SEL_PERIC11, 24, 1),
+       MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+               MUX_SEL_PERIC11, 28, 1),
+};
+
+static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+       GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 4, 0, 0),
+       GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 5, 0, 0),
+       GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 6, 0, 0),
+       GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 7, 0, 0),
+       GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 8, 0, 0),
+       GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 9, 0, 0),
+       GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 10, 0, 0),
+       GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
+               ENABLE_PCLK_PERIC1, 11, 0, 0),
+
+       GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
+               ENABLE_SCLK_PERIC10, 9, 0, 0),
+       GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
+               ENABLE_SCLK_PERIC10, 10, 0, 0),
+       GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
+               ENABLE_SCLK_PERIC10, 11, 0, 0),
+};
+
+static struct samsung_cmu_info peric1_cmu_info __initdata = {
+       .mux_clks               = peric1_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(peric1_mux_clks),
+       .gate_clks              = peric1_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(peric1_gate_clks),
+       .nr_clk_ids             = PERIC1_NR_CLK,
+       .clk_regs               = peric1_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(peric1_clk_regs),
+};
+
+static void __init exynos7_clk_peric1_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &peric1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
+       exynos7_clk_peric1_init);
+
+/* Register Offset definitions for CMU_PERIS (0x10040000) */
+#define MUX_SEL_PERIS                  0x0200
+#define ENABLE_PCLK_PERIS              0x0900
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID        0x0910
+#define ENABLE_SCLK_PERIS              0x0A00
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID        0x0A10
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
+
+static unsigned long peris_clk_regs[] __initdata = {
+       MUX_SEL_PERIS,
+       ENABLE_PCLK_PERIS,
+       ENABLE_PCLK_PERIS_SECURE_CHIPID,
+       ENABLE_SCLK_PERIS,
+       ENABLE_SCLK_PERIS_SECURE_CHIPID,
+};
+
+static struct samsung_mux_clock peris_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_peris_66_user",
+               mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
+};
+
+static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+       GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
+               ENABLE_PCLK_PERIS, 6, 0, 0),
+       GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+               ENABLE_PCLK_PERIS, 10, 0, 0),
+
+       GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
+               ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+       GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
+               ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+       GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
+};
+
+static struct samsung_cmu_info peris_cmu_info __initdata = {
+       .mux_clks               = peris_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(peris_mux_clks),
+       .gate_clks              = peris_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
+       .nr_clk_ids             = PERIS_NR_CLK,
+       .clk_regs               = peris_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
+};
+
+static void __init exynos7_clk_peris_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &peris_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
+       exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define MUX_SEL_FSYS00                 0x0200
+#define MUX_SEL_FSYS01                 0x0204
+#define ENABLE_ACLK_FSYS01             0x0804
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_aclk_fsys0_200_p)   = { "fin_pll", "dout_aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_p)                = { "fin_pll", "sclk_mmc2" };
+
+static unsigned long fsys0_clk_regs[] __initdata = {
+       MUX_SEL_FSYS00,
+       MUX_SEL_FSYS01,
+       ENABLE_ACLK_FSYS01,
+};
+
+static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+               MUX_SEL_FSYS00, 24, 1),
+
+       MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+};
+
+static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+       GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+               ENABLE_ACLK_FSYS01, 31, 0, 0),
+};
+
+static struct samsung_cmu_info fsys0_cmu_info __initdata = {
+       .mux_clks               = fsys0_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
+       .gate_clks              = fsys0_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
+       .nr_clk_ids             = TOP1_NR_CLK,
+       .clk_regs               = fsys0_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &fsys0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+       exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define MUX_SEL_FSYS10                 0x0200
+#define MUX_SEL_FSYS11                 0x0204
+#define ENABLE_ACLK_FSYS1              0x0800
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_p)   = { "fin_pll",  "dout_aclk_fsys1_200" };
+PNAME(mout_sclk_mmc0_p)                = { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_p)                = { "fin_pll", "sclk_mmc1" };
+
+static unsigned long fsys1_clk_regs[] __initdata = {
+       MUX_SEL_FSYS10,
+       MUX_SEL_FSYS11,
+       ENABLE_ACLK_FSYS1,
+};
+
+static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+       MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+               MUX_SEL_FSYS10, 28, 1),
+
+       MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
+       MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
+};
+
+static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+       GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
+               ENABLE_ACLK_FSYS1, 29, 0, 0),
+       GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
+               ENABLE_ACLK_FSYS1, 30, 0, 0),
+};
+
+static struct samsung_cmu_info fsys1_cmu_info __initdata = {
+       .mux_clks               = fsys1_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
+       .gate_clks              = fsys1_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
+       .nr_clk_ids             = TOP1_NR_CLK,
+       .clk_regs               = fsys1_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+       samsung_cmu_register_one(np, &fsys1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+       exynos7_clk_fsys1_init);
index b07fad2a916703731731f40b5db3aa678e835b17..9d70e5c03804cee247ee54ff4faed549bbf7ea12 100644 (file)
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
 
 #define PLL46XX_VSEL_MASK      (1)
 #define PLL46XX_MDIV_MASK      (0x1FF)
+#define PLL1460X_MDIV_MASK     (0x3FF)
+
 #define PLL46XX_PDIV_MASK      (0x3F)
 #define PLL46XX_SDIV_MASK      (0x7)
 #define PLL46XX_VSEL_SHIFT     (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 
        pll_con0 = __raw_readl(pll->con_reg);
        pll_con1 = __raw_readl(pll->con_reg + 4);
-       mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+       mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+                               PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
        kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
                                        pll_con1 & PLL46XX_KDIV_MASK;
 
-       shift = pll->type == pll_4600 ? 16 : 10;
+       shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+
        fvco *= (mdiv << shift) + kdiv;
        do_div(fvco, (pdiv << sdiv));
        fvco >>= shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
                lock = 0xffff;
 
        /* Set PLL PMS and VSEL values. */
-       con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+       if (pll->type == pll_1460x) {
+               con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+                       (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+                       (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
+       } else {
+               con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
                        (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
                        (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
                        (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+               con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
+       }
+
        con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
                        (rate->pdiv << PLL46XX_PDIV_SHIFT) |
-                       (rate->sdiv << PLL46XX_SDIV_SHIFT) |
-                       (rate->vsel << PLL46XX_VSEL_SHIFT);
+                       (rate->sdiv << PLL46XX_SDIV_SHIFT);
 
        /* Set PLL K, MFR and MRR values. */
        con1 = __raw_readl(pll->con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
        /* clk_ops for 35xx and 2550 are similar */
        case pll_35xx:
        case pll_2550:
+       case pll_1450x:
+       case pll_1451x:
+       case pll_1452x:
                if (!pll->rate_table)
                        init.ops = &samsung_pll35xx_clk_min_ops;
                else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
        case pll_4600:
        case pll_4650:
        case pll_4650c:
+       case pll_1460x:
                if (!pll->rate_table)
                        init.ops = &samsung_pll46xx_clk_min_ops;
                else
index c0ed4d41fd90d96adb8f3c465b71e016c7bf787e..213de9af8b4f2ea34e9258ce9df3373f9571f712 100644 (file)
@@ -33,6 +33,10 @@ enum samsung_pll_type {
        pll_s3c2440_mpll,
        pll_2550xx,
        pll_2650xx,
+       pll_1450x,
+       pll_1451x,
+       pll_1452x,
+       pll_1460x,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)                       \
index deab84d9f37deec161070fc372f6756a90369a43..dd1f7c977b6b8d06bed125c45d08e53f097f0400 100644 (file)
@@ -14,6 +14,8 @@
 #include <linux/syscore_ops.h>
 #include "clk.h"
 
+static LIST_HEAD(clock_reg_cache_list);
+
 void samsung_clk_save(void __iomem *base,
                                    struct samsung_clk_reg_dump *rd,
                                    unsigned int num_regs)
@@ -313,3 +315,99 @@ unsigned long _get_rate(const char *clk_name)
 
        return clk_get_rate(clk);
 }
+
+#ifdef CONFIG_PM_SLEEP
+static int samsung_clk_suspend(void)
+{
+       struct samsung_clock_reg_cache *reg_cache;
+
+       list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+               samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
+                               reg_cache->rd_num);
+       return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+       struct samsung_clock_reg_cache *reg_cache;
+
+       list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
+               samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
+                               reg_cache->rd_num);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+       .suspend = samsung_clk_suspend,
+       .resume = samsung_clk_resume,
+};
+
+static void samsung_clk_sleep_init(void __iomem *reg_base,
+               const unsigned long *rdump,
+               unsigned long nr_rdump)
+{
+       struct samsung_clock_reg_cache *reg_cache;
+
+       reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
+                       GFP_KERNEL);
+       if (!reg_cache)
+               panic("could not allocate register reg_cache.\n");
+       reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
+
+       if (!reg_cache->rdump)
+               panic("could not allocate register dump storage.\n");
+
+       if (list_empty(&clock_reg_cache_list))
+               register_syscore_ops(&samsung_clk_syscore_ops);
+
+       reg_cache->reg_base = reg_base;
+       reg_cache->rd_num = nr_rdump;
+       list_add_tail(&reg_cache->node, &clock_reg_cache_list);
+}
+
+#else
+static void samsung_clk_sleep_init(void __iomem *reg_base,
+               const unsigned long *rdump,
+               unsigned long nr_rdump) {}
+#endif
+
+/*
+ * Common function which registers plls, muxes, dividers and gates
+ * for each CMU. It also add CMU register list to register cache.
+ */
+void __init samsung_cmu_register_one(struct device_node *np,
+                       struct samsung_cmu_info *cmu)
+{
+       void __iomem *reg_base;
+       struct samsung_clk_provider *ctx;
+
+       reg_base = of_iomap(np, 0);
+       if (!reg_base)
+               panic("%s: failed to map registers\n", __func__);
+
+       ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
+       if (!ctx)
+               panic("%s: unable to alllocate ctx\n", __func__);
+
+       if (cmu->pll_clks)
+               samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
+                       reg_base);
+       if (cmu->mux_clks)
+               samsung_clk_register_mux(ctx, cmu->mux_clks,
+                       cmu->nr_mux_clks);
+       if (cmu->div_clks)
+               samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
+       if (cmu->gate_clks)
+               samsung_clk_register_gate(ctx, cmu->gate_clks,
+                       cmu->nr_gate_clks);
+       if (cmu->fixed_clks)
+               samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
+                       cmu->nr_fixed_clks);
+       if (cmu->fixed_factor_clks)
+               samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
+                       cmu->nr_fixed_factor_clks);
+       if (cmu->clk_regs)
+               samsung_clk_sleep_init(reg_base, cmu->clk_regs,
+                       cmu->nr_clk_regs);
+
+       samsung_clk_of_add_provider(np, ctx);
+}
index 66ab36b5cef1018de647434cc0848f549b546ab2..3f471e958cb0ad692b55a7018e88c599a2507876 100644 (file)
@@ -324,6 +324,40 @@ struct samsung_pll_clock {
        __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE,     \
                _lock, _con, _rtable, _alias)
 
+struct samsung_clock_reg_cache {
+       struct list_head node;
+       void __iomem *reg_base;
+       struct samsung_clk_reg_dump *rdump;
+       unsigned int rd_num;
+};
+
+struct samsung_cmu_info {
+       /* list of pll clocks and respective count */
+       struct samsung_pll_clock *pll_clks;
+       unsigned int nr_pll_clks;
+       /* list of mux clocks and respective count */
+       struct samsung_mux_clock *mux_clks;
+       unsigned int nr_mux_clks;
+       /* list of div clocks and respective count */
+       struct samsung_div_clock *div_clks;
+       unsigned int nr_div_clks;
+       /* list of gate clocks and respective count */
+       struct samsung_gate_clock *gate_clks;
+       unsigned int nr_gate_clks;
+       /* list of fixed clocks and respective count */
+       struct samsung_fixed_rate_clock *fixed_clks;
+       unsigned int nr_fixed_clks;
+       /* list of fixed factor clocks and respective count */
+       struct samsung_fixed_factor_clock *fixed_factor_clks;
+       unsigned int nr_fixed_factor_clks;
+       /* total number of clocks with IDs assigned*/
+       unsigned int nr_clk_ids;
+
+       /* list and number of clocks registers */
+       unsigned long *clk_regs;
+       unsigned int nr_clk_regs;
+};
+
 extern struct samsung_clk_provider *__init samsung_clk_init(
                        struct device_node *np, void __iomem *base,
                        unsigned long nr_clks);
@@ -362,6 +396,9 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 &n