drm/amdgpu: PRT support for gfx9 (v3)
authorZhang, Jerry <Jerry.Zhang@amd.com>
Wed, 19 Apr 2017 01:53:29 +0000 (09:53 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 28 Apr 2017 21:32:47 +0000 (17:32 -0400)
Fix PRT handling on gfx9

v2: unify PRT bit for all ASICs
v3: move PRT flag checking in amdgpu_vm_bo_split_mapping()

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: David Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

index f34d822f92acae1edc3ca6863a543dbf4d1ac91e..c42a9979d056d77146061b099a9edca27cf70165 100644 (file)
@@ -1338,6 +1338,12 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
        flags &= ~AMDGPU_PTE_MTYPE_MASK;
        flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
 
+       if ((mapping->flags & AMDGPU_PTE_PRT) &&
+           (adev->asic_type >= CHIP_VEGA10)) {
+               flags |= AMDGPU_PTE_PRT;
+               flags &= ~AMDGPU_PTE_VALID;
+       }
+
        trace_amdgpu_vm_bo_update(mapping);
 
        pfn = mapping->offset >> PAGE_SHIFT;
index 661a8f6826ef5435ee5bebc933d5d10a731f42f7..d97e28b4bdc41cbb52e70647685b58db4886514a 100644 (file)
@@ -65,7 +65,8 @@ struct amdgpu_bo_list_entry;
 
 #define AMDGPU_PTE_FRAG(x)     ((x & 0x1fULL) << 7)
 
-#define AMDGPU_PTE_PRT         (1ULL << 63)
+/* TILED for VEGA10, reserved for older ASICs  */
+#define AMDGPU_PTE_PRT         (1ULL << 51)
 
 /* VEGA10 only */
 #define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)