Merge tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Mar 2019 18:12:50 +0000 (11:12 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Mar 2019 18:12:50 +0000 (11:12 -0700)
Pull pin control updates from Linus Walleij:
 "This is a calm cycle, not much happened this time around: not even
  much incremental development. Some three new drivers, that is all.

  No core changes.

  New drivers:

   - NXP (ex Freescale) i.MX 8QM driver.

   - NXP (ex Freescale) i.MX 8MM driver.

   - AT91 SAM9X60 subdriver.

  Improvements:

   - Support for external interrups (EINT) on Mediatek virtual GPIOs.

   - Make BCM2835 pin config fully generic.

   - Lots of Renesas SH-PFC incremental improvements"

* tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits)
  pinctrl: imx: fix scu link errors
  dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding
  pinctrl: qcom: spmi-gpio: Reorder debug print
  pinctrl: nomadik: fix possible object reference leak
  pinctrl: stm32: return error upon hwspinlock failure
  pinctrl: stm32: fix memory leak issue
  pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
  pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
  pinctrl: sh-pfc: Validate fixed-size field widths at build time
  pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups
  pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
  pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
  pinctrl: sh-pfc: emev2: Add missing pinmux functions
  pinctrl: sunxi: Support I/O bias voltage setting on A80
  pinctrl: ingenic: Add LCD pins for the JZ4725B SoC
  pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask
  pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl
  pinctrl: bcm2835: declare pin config as generic
  pinctrl: qcom: qcs404: Drop unused UFS_RESET macro
  dt-bindings: add documentation for slew rate
  ...

55 files changed:
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
Documentation/driver-api/pinctl.rst
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h [new file with mode: 0644]
drivers/pinctrl/bcm/pinctrl-bcm2835.c
drivers/pinctrl/berlin/pinctrl-as370.c
drivers/pinctrl/cirrus/pinctrl-madera-core.c
drivers/pinctrl/freescale/Kconfig
drivers/pinctrl/freescale/Makefile
drivers/pinctrl/freescale/pinctrl-imx8mm.c [new file with mode: 0644]
drivers/pinctrl/freescale/pinctrl-imx8qm.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
drivers/pinctrl/meson/pinctrl-meson.c
drivers/pinctrl/meson/pinctrl-meson.h
drivers/pinctrl/meson/pinctrl-meson8b.c
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
drivers/pinctrl/nomadik/pinctrl-nomadik.c
drivers/pinctrl/pinconf.c
drivers/pinctrl/pinctrl-amd.c
drivers/pinctrl/pinctrl-at91.c
drivers/pinctrl/pinctrl-at91.h
drivers/pinctrl/pinctrl-ingenic.c
drivers/pinctrl/pinctrl-mcp23s08.c
drivers/pinctrl/qcom/pinctrl-qcs404.c
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
drivers/pinctrl/samsung/pinctrl-exynos.c
drivers/pinctrl/sh-pfc/pfc-emev2.c
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
drivers/pinctrl/sh-pfc/pinctrl.c
drivers/pinctrl/sh-pfc/sh_pfc.h
drivers/pinctrl/sirf/pinctrl-atlas7.c
drivers/pinctrl/sirf/pinctrl-sirf.c
drivers/pinctrl/stm32/pinctrl-stm32.c
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
drivers/pinctrl/sunxi/pinctrl-sunxi.c
drivers/pinctrl/sunxi/pinctrl-sunxi.h
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
include/dt-bindings/pinctrl/at91.h
include/linux/pinctrl/pinconf.h

index 3e23fece99dabda20f18e649b708702524e02454..eb39f5051159f3aa29c0ace536288b7e592dae05 100644 (file)
@@ -19,7 +19,7 @@ such as pull-up, multi drive, etc.
 
 Required properties for iomux controller:
 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
-               or "atmel,sama5d3-pinctrl"
+               or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
   configured in this periph mode. All the periph and bank need to be describe.
 
@@ -100,6 +100,7 @@ DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
                                11 - High
 OUTPUT         (1 << 7): indicate this pin need to be configured as an output.
 OUTPUT_VAL     (1 << 8): output val (1 = high, 0 = low)
+SLEWRATE       (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
 DEBOUNCE       (1 << 16): indicate this pin needs debounce.
 DEBOUNCE_VAL   (0x3fff << 17): debounce value.
 
@@ -116,6 +117,19 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
    configurations by referring to the phandle of that pin configuration node.
 4. The gpio controller must be describe in the pinctrl simple-bus.
 
+For each bank the required properties are:
+- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
+  "microchip,sam9x60-gpio"
+- reg: physical base address and length of the controller's registers
+- interrupts: interrupt outputs from the controller
+- interrupt-controller: marks the device node as an interrupt controller
+- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
+  for more details.
+- gpio-controller
+- #gpio-cells: should be 2; the first cell is the GPIO number and the second
+  cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
+- clocks: bank clock
+
 Examples:
 
 pinctrl@fffff400 {
@@ -125,6 +139,17 @@ pinctrl@fffff400 {
        compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
        reg = <0xfffff400 0x600>;
 
+       pioA: gpio@fffff400 {
+               compatible = "atmel,at91sam9x5-gpio";
+               reg = <0xfffff400 0x200>;
+               interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+       };
+
        atmel,mux-mask = <
              /*    A         B     */
               0xffffffff 0xffc00c3b  /* pioA */
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt
new file mode 100644 (file)
index 0000000..6da01d6
--- /dev/null
@@ -0,0 +1,32 @@
+* Freescale IMX50 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx50-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx50 datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_HVE                    (1 << 13)
+PAD_CTL_HYS                    (1 << 8)
+PAD_CTL_PKE                    (1 << 7)
+PAD_CTL_PUE                    (1 << 6)
+PAD_CTL_PUS_100K_DOWN          (0 << 4)
+PAD_CTL_PUS_47K_UP             (1 << 4)
+PAD_CTL_PUS_100K_UP            (2 << 4)
+PAD_CTL_PUS_22K_UP             (3 << 4)
+PAD_CTL_ODE                    (1 << 3)
+PAD_CTL_DSE_LOW                        (0 << 1)
+PAD_CTL_DSE_MED                        (1 << 1)
+PAD_CTL_DSE_HIGH               (2 << 1)
+PAD_CTL_DSE_MAX                        (3 << 1)
+PAD_CTL_SRE_FAST               (1 << 0)
+PAD_CTL_SRE_SLOW               (0 << 0)
+
+Refer to imx50-pinfunc.h in device tree source folder for all available
+imx50 PIN_FUNC_ID.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
new file mode 100644 (file)
index 0000000..524a16f
--- /dev/null
@@ -0,0 +1,36 @@
+* Freescale IMX8MM IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+for common binding part and usage.
+
+Required properties:
+- compatible: "fsl,imx8mm-iomuxc"
+- reg: should contain the base physical address and size of the iomuxc
+  registers.
+
+Required properties in sub-nodes:
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
+  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+  <dt-bindings/pinctrl/imx8mm-pinfunc.h>. The last integer CONFIG is
+  the pad setting value like pull-up on this pin.  Please refer to i.MX8M Mini
+  Reference Manual for detailed CONFIG settings.
+
+Examples:
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+};
+
+iomuxc: pinctrl@30330000 {
+        compatible = "fsl,imx8mm-iomuxc";
+        reg = <0x0 0x30330000 0x0 0x10000>;
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX             0x140
+                        MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX             0x140
+                >;
+        };
+};
index c7c088d2dd503df005904b46a486d75e437e37e9..38dc56a5776041e4dcf325bc7b8bf66c4e290c77 100644 (file)
@@ -58,11 +58,11 @@ group pwm3
  - functions pwm, gpio
 
 group pmic1
- - pin 17
+ - pin 7
  - functions pmic, gpio
 
 group pmic0
- - pin 16
+ - pin 6
  - functions pmic, gpio
 
 group i2c2
@@ -112,19 +112,31 @@ group usb2_drvvbus1
  - functions drvbus, gpio
 
 group sdio_sb
- - pins 60-64
+ - pins 60-65
  - functions sdio, gpio
 
 group rgmii
- - pins 42-55
+ - pins 42-53
  - functions mii, gpio
 
 group pcie1
- - pins 39-40
+ - pins 39
+ - functions pcie, gpio
+
+group pcie1_clkreq
+ - pins 40
  - functions pcie, gpio
 
+group pcie1_wakeup
+ - pins 41
+ - functions pcie, gpio
+
+group smi
+ - pins 54-55
+ - functions smi, gpio
+
 group ptp
- - pins 56-58
+ - pins 56
  - functions ptp, gpio
 
 group ptp_clk
index 82ead40311f62ee1c6cb5009cefe9328e5869595..a47dd990a8d3ac5630ac47efbdb99c17ba1d4d13 100644 (file)
@@ -23,11 +23,11 @@ The GPIO bank for the controller is represented as a sub-node and it acts as a
 GPIO controller.
 
 Required properties for sub-nodes are:
- - reg: should contain address and size for mux, pull-enable, pull and
-   gpio register sets
- - reg-names: an array of strings describing the "reg" entries. Must
-   contain "mux", "pull" and "gpio". "pull-enable" is optional and
-   when it is missing the "pull" registers are used instead
+ - reg: should contain a list of address and size, one tuple for each entry
+   in reg-names.
+ - reg-names: an array of strings describing the "reg" entries.
+   Must contain "mux" and "gpio".
+   May contain "pull", "pull-enable" and "ds" when appropriate.
  - gpio-controller: identifies the node as a gpio controller
  - #gpio-cells: must be 2
 
index 6cb68d67fa75a7cef5eab57125fccac3a86a0139..2bb1bc4842782f89d0e3bd45313fb0064e466b5e 100644 (file)
@@ -274,15 +274,6 @@ configuration in the pin controller ops like this::
                .confops = &foo_pconf_ops,
        };
 
-Since some controllers have special logic for handling entire groups of pins
-they can exploit the special whole-group pin control function. The
-pin_config_group_set() callback is allowed to return the error code -EAGAIN,
-for groups it does not want to handle, or if it just wants to do some
-group-level handling and then fall through to iterate over all pins, in which
-case each individual pin will be treated by separate pin_config_set() calls as
-well.
-
-
 Interaction with the GPIO subsystem
 ===================================
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
new file mode 100644 (file)
index 0000000..e25f7fc
--- /dev/null
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DTS_IMX8MM_PINFUNC_H
+#define __DTS_IMX8MM_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0                                   0x028 0x290 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT          0x028 0x290 0x4C0 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K                          0x028 0x290 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1                       0x028 0x290 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL                                    0x028 0x290 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1                                   0x02C 0x294 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT                                    0x02C 0x294 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M                          0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2                       0x02C 0x294 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE                                  0x02C 0x294 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2                                   0x030 0x298 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B                                0x030 0x298 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY                              0x030 0x298 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B                                    0x030 0x298 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3                                   0x034 0x29C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT                              0x034 0x29C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0                            0x034 0x29C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK                              0x034 0x29C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE                                    0x034 0x29C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4                                   0x038 0x2A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT                              0x038 0x2A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1                            0x038 0x2A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV                           0x038 0x2A0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG                            0x038 0x2A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5                                   0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI                                      0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY                     0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT                       0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG                            0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6                                   0x040 0x2A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC                                   0x040 0x2A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B                                 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3                       0x040 0x2A8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG                            0x040 0x2A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7                                   0x044 0x2AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO                                  0x044 0x2AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP                                   0x044 0x2AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4                       0x044 0x2AC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG                            0x044 0x2AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8                                   0x048 0x2B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN                        0x048 0x2B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B                              0x048 0x2B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT                           0x048 0x2B0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG                              0x048 0x2B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9                                   0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT                       0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0                            0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP                           0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG                           0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10                                  0x050 0x2B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID                                 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED             0x050 0x2B8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11                                  0x054 0x2BC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID                                 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY                     0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0                           0x054 0x2BC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS                    0x054 0x2BC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12                                  0x058 0x2C0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR                                0x058 0x2C0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1                            0x058 0x2C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1                           0x058 0x2C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0                          0x058 0x2C0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13                                  0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC                                 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT                                    0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2                           0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1                          0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14                                  0x060 0x2C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR                                0x060 0x2C8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT                                    0x060 0x2C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1                          0x060 0x2C8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2                          0x060 0x2C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15                                  0x064 0x2CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC                                 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT                                    0x064 0x2CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2                          0x064 0x2CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB                             0x064 0x2CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                                     0x068 0x2D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16                                    0x068 0x2D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO                                   0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17                                   0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3                               0x070 0x2D8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18                                    0x070 0x2D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2                               0x074 0x2DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK                                  0x074 0x2DC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19                                    0x074 0x2DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1                               0x078 0x2E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20                                    0x078 0x2E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0                               0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21                                    0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL                         0x080 0x2E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22                                 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC                               0x084 0x2EC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER                                   0x084 0x2EC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                                    0x084 0x2EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL                         0x088 0x2F0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24                                 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC                               0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER                                   0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25                                    0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0                               0x090 0x2F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26                                    0x090 0x2F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1                               0x094 0x2FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27                                    0x094 0x2FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2                               0x098 0x300 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28                                    0x098 0x300 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3                               0x09C 0x304 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29                                    0x09C 0x304 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                                     0x0A0 0x308 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0                                      0x0A0 0x308 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4                                    0x0B0 0x318 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3                                 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5                                    0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4                                 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6                                    0x0B8 0x320 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5                                 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7                                    0x0BC 0x324 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6                                 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8                                    0x0C0 0x328 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7                                 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                                    0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B                             0x0C8 0x330 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10                                 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE                               0x0CC 0x334 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11                                  0x0CC 0x334 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B                                   0x0D0 0x338 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                                    0x0D0 0x338 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                                     0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13                                     0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0                          0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0                               0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                                     0x0D8 0x340 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14                                     0x0D8 0x340 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1                          0x0D8 0x340 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1                               0x0D8 0x340 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0                                 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15                                   0x0DC 0x344 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2                        0x0DC 0x344 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2                             0x0DC 0x344 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1                                 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16                                   0x0E0 0x348 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT                            0x0E0 0x348 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3                             0x0E0 0x348 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2                                 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17                                   0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP                            0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4                             0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3                                 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18                                   0x0E8 0x350 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET                     0x0E8 0x350 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B                             0x0EC 0x354 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19                                 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET                  0x0EC 0x354 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP                                       0x0F0 0x358 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20                                      0x0F0 0x358 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK                                 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE                                   0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK                                   0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0                                     0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0                                  0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B                               0x0F8 0x360 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B                                0x0F8 0x360 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1                                   0x0F8 0x360 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1                                0x0F8 0x360 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B                               0x0FC 0x364 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B                                0x0FC 0x364 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE                               0x0FC 0x364 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2                                   0x0FC 0x364 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2                                0x0FC 0x364 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B                               0x100 0x368 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B                                0x100 0x368 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5                                0x100 0x368 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3                                   0x100 0x368 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3                                0x100 0x368 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B                               0x104 0x36C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B                                0x104 0x36C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6                                0x104 0x36C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4                                   0x104 0x36C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0                                0x104 0x36C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE                                   0x108 0x370 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK                                   0x108 0x370 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7                                  0x108 0x370 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5                                     0x108 0x370 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1                                  0x108 0x370 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00                             0x10C 0x374 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0                               0x10C 0x374 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6                                  0x10C 0x374 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2                               0x10C 0x374 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01                             0x110 0x378 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1                               0x110 0x378 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7                                  0x110 0x378 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3                               0x110 0x378 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02                             0x114 0x37C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2                               0x114 0x37C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8                                  0x114 0x37C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4                               0x114 0x37C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03                             0x118 0x380 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3                               0x118 0x380 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9                                  0x118 0x380 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5                               0x118 0x380 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04                             0x11C 0x384 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0                               0x11C 0x384 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0                               0x11C 0x384 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10                                 0x11C 0x384 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6                               0x11C 0x384 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05                             0x120 0x388 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1                               0x120 0x388 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1                               0x120 0x388 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11                                 0x120 0x388 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7                               0x120 0x388 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06                             0x124 0x38C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2                               0x124 0x38C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2                              0x124 0x38C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12                                 0x124 0x38C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8                               0x124 0x38C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07                             0x128 0x390 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3                               0x128 0x390 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3                               0x128 0x390 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13                                 0x128 0x390 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9                               0x128 0x390 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS                                   0x12C 0x394 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS                                    0x12C 0x394 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14                                    0x12C 0x394 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10                                 0x12C 0x394 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B                                 0x130 0x398 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS                                   0x130 0x398 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4                                 0x130 0x398 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15                                   0x130 0x398 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11                                0x130 0x398 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B                           0x134 0x39C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16                                0x134 0x39C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12                             0x134 0x39C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B                                 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK                                   0x138 0x3A0 0x000 0x12 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17                                   0x138 0x3A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13                                0x138 0x3A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B                                 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD                                   0x13C 0x3A4 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18                                   0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14                                0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC                                 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0                                0x140 0x3A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19                                   0x140 0x3A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK                                  0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1                                 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK                                       0x144 0x3AC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20                                    0x144 0x3AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0                                0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2                                0x148 0x3B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0                                    0x148 0x3B0 0x534 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21                                   0x148 0x3B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1                                0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3                                0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC                                 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC                                 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1                                    0x14C 0x3B4 0x538 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22                                   0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2                                0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4                                0x150 0x3B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC                                 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK                                 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2                                    0x150 0x3B8 0x53c 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23                                   0x150 0x3B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3                                0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5                                0x154 0x3BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC                                 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0                                0x154 0x3BC 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3                                    0x154 0x3BC 0x540 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24                                   0x154 0x3BC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK                                    0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK                                 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK                                    0x158 0x3C0 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25                                   0x158 0x3C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK                      0x158 0x3C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC                                 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC                                 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK                          0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0                                    0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15                                0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK                                  0x160 0x3C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK                                  0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL                           0x160 0x3C8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1                                     0x160 0x3C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16                                 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0                                    0x164 0x3CC 0x534 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                             0x164 0x3CC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                       0x164 0x3CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1                                0x168 0x3D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1                                0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1                                    0x168 0x3D0 0x538 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1                             0x168 0x3D0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3                                    0x168 0x3D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1                       0x168 0x3D0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18                                0x168 0x3D0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2                                0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2                                0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2                                    0x16C 0x3D4 0x53C 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2                             0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4                                    0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2                       0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19                                0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3                                0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3                                0x170 0x3D8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3                                    0x170 0x3D8 0x540 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3                             0x170 0x3D8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5                                    0x170 0x3D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3                       0x170 0x3D8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20                                0x170 0x3D8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4                                0x174 0x3DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK                                 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK                                 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4                             0x174 0x3DC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6                                    0x174 0x3DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4                       0x174 0x3DC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21                                0x174 0x3DC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5                                0x178 0x3E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0                                0x178 0x3E0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0                                0x178 0x3E0 0x514 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC                                 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5                             0x178 0x3E0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7                                    0x178 0x3E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5                       0x178 0x3E0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22                                0x178 0x3E0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6                                0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC                                 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC                                 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6                             0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8                                    0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6                       0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23                                0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7                                0x180 0x3E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK                                    0x180 0x3E8 0x530 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC                                 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4                                0x180 0x3E8 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7                             0x180 0x3E8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9                                    0x180 0x3E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7                       0x180 0x3E8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24                                0x180 0x3E8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC                                 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC                                 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO                             0x184 0x3EC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10                                   0x184 0x3EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25                                0x184 0x3EC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK                                  0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK                                  0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI                              0x188 0x3F0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                                    0x188 0x3F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26                                 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0                                0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0                                0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8                             0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12                                   0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8                       0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27                                0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1                                0x190 0x3F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1                                0x190 0x3F8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9                             0x190 0x3F8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13                                   0x190 0x3F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9                       0x190 0x3F8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28                                0x190 0x3F8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2                                0x194 0x3FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2                                0x194 0x3FC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10                            0x194 0x3FC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14                                   0x194 0x3FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10                      0x194 0x3FC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29                                0x194 0x3FC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3                                0x198 0x400 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3                                0x198 0x400 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11                            0x198 0x400 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15                                   0x198 0x400 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11                      0x198 0x400 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30                                0x198 0x400 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4                                0x19C 0x404 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK                                 0x19C 0x404 0x510 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK                                 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12                            0x19C 0x404 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16                                   0x19C 0x404 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12                      0x19C 0x404 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31                                0x19C 0x404 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5                                0x1A0 0x408 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0                                0x1A0 0x408 0x514 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0                                0x1A0 0x408 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13                            0x1A0 0x408 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17                                   0x1A0 0x408 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13                      0x1A0 0x408 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0                                0x1A0 0x408 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6                                0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC                                 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC                                 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14                            0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18                                   0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14                      0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1                                0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7                                0x1A8 0x410 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK                                    0x1A8 0x410 0x530 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK                                      0x1A8 0x410 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15                            0x1A8 0x410 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19                                   0x1A8 0x410 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15                      0x1A8 0x410 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2                                0x1A8 0x410 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK                                    0x1AC 0x414 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK                                    0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK                                 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK                                      0x1AC 0x414 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20                                   0x1AC 0x414 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2                                 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                                    0x1C0 0x428 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT                               0x1C0 0x428 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0                                0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3                                0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26                                   0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK                                    0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK                                    0x1C8 0x430 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK                                    0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27                                   0x1C8 0x430 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR                              0x1C8 0x430 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC                                 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1                                0x1CC 0x434 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC                                 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28                                   0x1CC 0x434 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0                                0x1CC 0x434 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3                                 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3                                 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1                                     0x1E0 0x448 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3                                  0x1E0 0x448 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK                                    0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT                                     0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK                                    0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2                                    0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4                                 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT                                    0x1E8 0x450 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT                                      0x1E8 0x450 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3                                     0x1E8 0x450 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5                                  0x1E8 0x450 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN                                     0x1EC 0x454 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT                                      0x1EC 0x454 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4                                     0x1EC 0x454 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6                                  0x1EC 0x454 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                           0x1F0 0x458 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT                                 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5                                0x1F0 0x458 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7                             0x1F0 0x458 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK                                0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX                               0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX                               0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6                                  0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8                               0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI                                0x1F8 0x460 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX                               0x1F8 0x460 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX                               0x1F8 0x460 0x504 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7                                  0x1F8 0x460 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9                               0x1F8 0x460 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO                                0x1FC 0x464 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B                            0x1FC 0x464 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B                            0x1FC 0x464 0x500 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8                                  0x1FC 0x464 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10                              0x1FC 0x464 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0                                  0x200 0x468 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B                             0x200 0x468 0x500 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B                             0x200 0x468 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9                                   0x200 0x468 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11                               0x200 0x468 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK                                0x204 0x46C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX                               0x204 0x46C 0x50C 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX                               0x204 0x46C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10                                 0x204 0x46C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12                              0x204 0x46C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI                                0x208 0x470 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX                               0x208 0x470 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX                               0x208 0x470 0x50C 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11                                 0x208 0x470 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13                              0x208 0x470 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO                                0x20C 0x474 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B                            0x20C 0x474 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B                            0x20C 0x474 0x508 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12                                 0x20C 0x474 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14                              0x20C 0x474 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0                                  0x210 0x478 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B                             0x210 0x478 0x508 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B                             0x210 0x478 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13                                  0x210 0x478 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15                               0x210 0x478 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                                      0x214 0x47C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC                                     0x214 0x47C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14                                    0x214 0x47C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16                                 0x214 0x47C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                                      0x218 0x480 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO                                    0x218 0x480 0x4C0 0x1 0x2
+#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15                                    0x218 0x480 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17                                 0x218 0x480 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                                      0x21C 0x484 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN                          0x21C 0x484 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16                                    0x21C 0x484 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18                                 0x21C 0x484 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                                      0x220 0x488 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT                         0x220 0x488 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17                                    0x220 0x488 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19                                 0x220 0x488 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                                      0x224 0x48C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT                                      0x224 0x48C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK                                      0x224 0x48C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18                                    0x224 0x48C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20                                 0x224 0x48C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                                      0x228 0x490 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT                                      0x228 0x490 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK                                      0x228 0x490 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19                                    0x228 0x490 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21                                 0x228 0x490 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                                      0x22C 0x494 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT                                      0x22C 0x494 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x12 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20                                    0x22C 0x494 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22                                 0x22C 0x494 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                                      0x230 0x498 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT                                      0x230 0x498 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x2 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21                                    0x230 0x498 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23                                 0x230 0x498 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX                                 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX                                 0x234 0x49C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK                                  0x234 0x49C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22                                   0x234 0x49C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24                                0x234 0x49C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX                                 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI                                  0x238 0x4A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23                                   0x238 0x4A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25                                0x238 0x4A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX                                 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX                                 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO                                  0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24                                   0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26                                0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX                                 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX                                 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0                                   0x240 0x4A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25                                   0x240 0x4A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27                                0x240 0x4A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX                                 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX                                 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B                              0x244 0x4AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B                              0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26                                   0x244 0x4AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28                                0x244 0x4AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX                                 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX                                 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B                              0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B                              0x248 0x4B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27                                   0x248 0x4B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29                                0x248 0x4B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX                                 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX                                 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B                              0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B                              0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B                               0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28                                   0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30                                0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX                                 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX                                 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B                              0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B                              0x250 0x4B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B                               0x250 0x4B8 0x528 0x2 0x1
+#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29                                   0x250 0x4B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31                                0x250 0x4B8 0x000 0x7 0x0
+
+#endif /* __DTS_IMX8MM_PINFUNC_H */
index f180aa44a422ffb8207a1de7f5ddd9c8bc708e66..183d1ffe6a75de6f6f205c17b88bc15db4fd23a8 100644 (file)
@@ -341,6 +341,7 @@ static const struct gpio_chip bcm2835_gpio_chip = {
        .get_direction = bcm2835_gpio_get_direction,
        .get = bcm2835_gpio_get,
        .set = bcm2835_gpio_set,
+       .set_config = gpiochip_generic_config,
        .base = -1,
        .ngpio = BCM2835_NUM_GPIOS,
        .can_sleep = false,
@@ -960,7 +961,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
                        break;
 
                default:
-                       return -EINVAL;
+                       return -ENOTSUPP;
 
                } /* switch param type */
        } /* for each config */
@@ -969,6 +970,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
 }
 
 static const struct pinconf_ops bcm2835_pinconf_ops = {
+       .is_generic = true,
        .pin_config_get = bcm2835_pinconf_get,
        .pin_config_set = bcm2835_pinconf_set,
 };
index d2bb811fc5fa476731a5f9a59d2e315bdac932f8..44f8ccdbeeff0a6677de61b729bacec41a606e89 100644 (file)
@@ -36,13 +36,13 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("I2S1_DO2", 0x0, 0x3, 0x0c,
                        BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* CORE RSTB */
                        BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO2 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm4"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM4 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO4 */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG4 */
        BERLIN_PINCTRL_GROUP("I2S1_DO3", 0x0, 0x3, 0x0f,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO5 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO3 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm5"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM5 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "spififib"), /* SPDIFIB */
                        BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG5 */
@@ -61,24 +61,24 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x0, 0x3, 0x1b,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO9 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM2 */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG9 */
        BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x00,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO10 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM3 */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG10 */
        BERLIN_PINCTRL_GROUP("I2S2_DI2", 0x4, 0x3, 0x03,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO11 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI2 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm6"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM6 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "spdific"), /* SPDIFIC */
                        BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG11 */
        BERLIN_PINCTRL_GROUP("I2S2_DI3", 0x4, 0x3, 0x06,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO12 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI3 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm7"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM7 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "spdifia"), /* SPDIFIA */
                        BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG12 */
@@ -98,14 +98,14 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("PDM_DI2", 0x4, 0x3, 0x12,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI2 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm4"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM4 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "spdifid"), /* SPDIFID */
                        BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG16 */
        BERLIN_PINCTRL_GROUP("PDM_DI3", 0x4, 0x3, 0x15,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI3 */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm5"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM5 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "spdifi"), /* SPDIFI */
                        BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG17 */
@@ -139,11 +139,11 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
                        BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA7 */
        BERLIN_PINCTRL_GROUP("NAND_ALE", 0x8, 0x3, 0x12,
                        BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm6"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM6 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO18 */
        BERLIN_PINCTRL_GROUP("NAND_CLE", 0x8, 0x3, 0x15,
                        BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm7"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM7 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO19 */
        BERLIN_PINCTRL_GROUP("NAND_WEn", 0x8, 0x3, 0x18,
                        BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */
@@ -169,12 +169,12 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x0c,
                        BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
                        BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), /* GPIO26 */
-                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm2")),
+                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM2 */
        BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0xc, 0x3, 0x0f,
                        BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */
                        BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
                        BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), /* GPIO27 */
-                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm3")),
+                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM3 */
        BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0xc, 0x3, 0x12,
                        BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */
                        BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
@@ -182,11 +182,11 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0xc, 0x3, 0x15,
                        BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */
                        BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO29 */
-                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm4")),
+                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM4 */
        BERLIN_PINCTRL_GROUP("SPI1_SDO", 0xc, 0x3, 0x18,
                        BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */
                        BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO30 */
-                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm5")),
+                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM5 */
        BERLIN_PINCTRL_GROUP("SPI1_SDI", 0xc, 0x3, 0x1b,
                        BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */
                        BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO31 */
@@ -209,51 +209,51 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("TMS", 0x10, 0x3, 0x0f,
                        BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */
                        BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */
-                       BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")),
+                       BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), /* PWM0 */
        BERLIN_PINCTRL_GROUP("TDI", 0x10, 0x3, 0x12,
                        BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */
                        BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */
-                       BERLIN_PINCTRL_FUNCTION(0x4, "pwm1")),
+                       BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), /* PWM1 */
        BERLIN_PINCTRL_GROUP("TDO", 0x10, 0x3, 0x15,
                        BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */
                        BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */
-                       BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")),
+                       BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), /* PWM0 */
        BERLIN_PINCTRL_GROUP("PWM6", 0x10, 0x3, 0x18,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO40 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm6")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM6 */
        BERLIN_PINCTRL_GROUP("PWM7", 0x10, 0x3, 0x1b,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO41 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm7")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM7 */
        BERLIN_PINCTRL_GROUP("PWM0", 0x14, 0x3, 0x00,
                        BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* VDDCPUSOC RSTB */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm0"),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* PWM0 */
                        BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO42 */
        BERLIN_PINCTRL_GROUP("PWM1", 0x14, 0x3, 0x03,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO43 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm1")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM1 */
        BERLIN_PINCTRL_GROUP("PWM2", 0x14, 0x3, 0x06,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm2")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM2 */
        BERLIN_PINCTRL_GROUP("PWM3", 0x14, 0x3, 0x09,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm3")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM3 */
        BERLIN_PINCTRL_GROUP("PWM4", 0x14, 0x3, 0x0c,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm4")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM4 */
        BERLIN_PINCTRL_GROUP("PWM5", 0x14, 0x3, 0x0f,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO47 */
-                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm5")),
+                       BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM5 */
        BERLIN_PINCTRL_GROUP("URT1_RTSn", 0x14, 0x3, 0x12,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO48 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RTSn */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm6"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM6 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "tw1a"), /* SCL */
                        BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG0 */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG18 */
        BERLIN_PINCTRL_GROUP("URT1_CTSn", 0x14, 0x3, 0x15,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO49 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* CTSn */
-                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm7"),
+                       BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM7 */
                        BERLIN_PINCTRL_FUNCTION(0x3, "tw1a"), /* SDA */
                        BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG1 */
                        BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG19 */
@@ -308,11 +308,11 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
        BERLIN_PINCTRL_GROUP("SD0_CDn", 0x1c, 0x3, 0x00,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO62 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */
-                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm2")),
+                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM2 */
        BERLIN_PINCTRL_GROUP("SD0_WP", 0x1c, 0x3, 0x03,
                        BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO63 */
                        BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */
-                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm3")),
+                       BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM3 */
 };
 
 static const struct berlin_pinctrl_desc as370_soc_pinctrl_data = {
index a5dda832024a01236eea8a570ef92b60abed942d..7c9694593f790966c566e58c9b5d01a3e0d2bdb4 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
index 72b869d888e2d7ca804aaa9eb3be367085c5d307..0d8387851b87a768b9fd95b41e15077d794ce2f4 100644 (file)
@@ -122,6 +122,13 @@ config PINCTRL_IMX7ULP
        help
          Say Y here to enable the imx7ulp pinctrl driver
 
+config PINCTRL_IMX8MM
+       bool "IMX8MM pinctrl driver"
+       depends on ARCH_MXC && ARM64
+       select PINCTRL_IMX
+       help
+         Say Y here to enable the imx8mm pinctrl driver
+
 config PINCTRL_IMX8MQ
        bool "IMX8MQ pinctrl driver"
        depends on ARCH_MXC && ARM64
@@ -129,9 +136,16 @@ config PINCTRL_IMX8MQ
        help
          Say Y here to enable the imx8mq pinctrl driver
 
+config PINCTRL_IMX8QM
+       bool "IMX8QM pinctrl driver"
+       depends on IMX_SCU && ARCH_MXC && ARM64
+       select PINCTRL_IMX_SCU
+       help
+         Say Y here to enable the imx8qm pinctrl driver
+
 config PINCTRL_IMX8QXP
        bool "IMX8QXP pinctrl driver"
-       depends on ARCH_MXC && ARM64
+       depends on IMX_SCU && ARCH_MXC && ARM64
        select PINCTRL_IMX_SCU
        help
          Say Y here to enable the imx8qxp pinctrl driver
index 6ee398a3e4065ff79641918a590dbc2a965c41c7..02020a76bd9ca36cfe28c06abf55a9feeb7157f3 100644 (file)
@@ -18,7 +18,9 @@ obj-$(CONFIG_PINCTRL_IMX6SX)  += pinctrl-imx6sx.o
 obj-$(CONFIG_PINCTRL_IMX6UL)   += pinctrl-imx6ul.o
 obj-$(CONFIG_PINCTRL_IMX7D)    += pinctrl-imx7d.o
 obj-$(CONFIG_PINCTRL_IMX7ULP)  += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX8MM)   += pinctrl-imx8mm.o
 obj-$(CONFIG_PINCTRL_IMX8MQ)   += pinctrl-imx8mq.o
+obj-$(CONFIG_PINCTRL_IMX8QM)   += pinctrl-imx8qm.o
 obj-$(CONFIG_PINCTRL_IMX8QXP)  += pinctrl-imx8qxp.o
 obj-$(CONFIG_PINCTRL_VF610)    += pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_MXS)      += pinctrl-mxs.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c b/drivers/pinctrl/freescale/pinctrl-imx8mm.c
new file mode 100644 (file)
index 0000000..6d1038a
--- /dev/null
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-imx.h"
+
+enum imx8mm_pads {
+       MX8MM_PAD_RESERVE0 = 0,
+       MX8MM_PAD_RESERVE1 = 1,
+       MX8MM_PAD_RESERVE2 = 2,
+       MX8MM_PAD_RESERVE3 = 3,
+       MX8MM_PAD_RESERVE4 = 4,
+       MX8MM_PAD_RESERVE5 = 5,
+       MX8MM_PAD_RESERVE6 = 6,
+       MX8MM_PAD_RESERVE7 = 7,
+       MX8MM_PAD_RESERVE8 = 8,
+       MX8MM_PAD_RESERVE9 = 9,
+       MX8MM_IOMUXC_GPIO1_IO00 = 10,
+       MX8MM_IOMUXC_GPIO1_IO01 = 11,
+       MX8MM_IOMUXC_GPIO1_IO02 = 12,
+       MX8MM_IOMUXC_GPIO1_IO03 = 13,
+       MX8MM_IOMUXC_GPIO1_IO04 = 14,
+       MX8MM_IOMUXC_GPIO1_IO05 = 15,
+       MX8MM_IOMUXC_GPIO1_IO06 = 16,
+       MX8MM_IOMUXC_GPIO1_IO07 = 17,
+       MX8MM_IOMUXC_GPIO1_IO08 = 18,
+       MX8MM_IOMUXC_GPIO1_IO09 = 19,
+       MX8MM_IOMUXC_GPIO1_IO10 = 20,
+       MX8MM_IOMUXC_GPIO1_IO11 = 21,
+       MX8MM_IOMUXC_GPIO1_IO12 = 22,
+       MX8MM_IOMUXC_GPIO1_IO13 = 23,
+       MX8MM_IOMUXC_GPIO1_IO14 = 24,
+       MX8MM_IOMUXC_GPIO1_IO15 = 25,
+       MX8MM_IOMUXC_ENET_MDC = 26,
+       MX8MM_IOMUXC_ENET_MDIO = 27,
+       MX8MM_IOMUXC_ENET_TD3 = 28,
+       MX8MM_IOMUXC_ENET_TD2 = 29,
+       MX8MM_IOMUXC_ENET_TD1 = 30,
+       MX8MM_IOMUXC_ENET_TD0 = 31,
+       MX8MM_IOMUXC_ENET_TX_CTL = 32,
+       MX8MM_IOMUXC_ENET_TXC = 33,
+       MX8MM_IOMUXC_ENET_RX_CTL = 34,
+       MX8MM_IOMUXC_ENET_RXC = 35,
+       MX8MM_IOMUXC_ENET_RD0 = 36,
+       MX8MM_IOMUXC_ENET_RD1 = 37,
+       MX8MM_IOMUXC_ENET_RD2 = 38,
+       MX8MM_IOMUXC_ENET_RD3 = 39,
+       MX8MM_IOMUXC_SD1_CLK = 40,
+       MX8MM_IOMUXC_SD1_CMD = 41,
+       MX8MM_IOMUXC_SD1_DATA0 = 42,
+       MX8MM_IOMUXC_SD1_DATA1 = 43,
+       MX8MM_IOMUXC_SD1_DATA2 = 44,
+       MX8MM_IOMUXC_SD1_DATA3 = 45,
+       MX8MM_IOMUXC_SD1_DATA4 = 46,
+       MX8MM_IOMUXC_SD1_DATA5 = 47,
+       MX8MM_IOMUXC_SD1_DATA6 = 48,
+       MX8MM_IOMUXC_SD1_DATA7 = 49,
+       MX8MM_IOMUXC_SD1_RESET_B = 50,
+       MX8MM_IOMUXC_SD1_STROBE = 51,
+       MX8MM_IOMUXC_SD2_CD_B = 52,
+       MX8MM_IOMUXC_SD2_CLK = 53,
+       MX8MM_IOMUXC_SD2_CMD = 54,
+       MX8MM_IOMUXC_SD2_DATA0 = 55,
+       MX8MM_IOMUXC_SD2_DATA1 = 56,
+       MX8MM_IOMUXC_SD2_DATA2 = 57,
+       MX8MM_IOMUXC_SD2_DATA3 = 58,
+       MX8MM_IOMUXC_SD2_RESET_B = 59,
+       MX8MM_IOMUXC_SD2_WP = 60,
+       MX8MM_IOMUXC_NAND_ALE = 61,
+       MX8MM_IOMUXC_NAND_CE0 = 62,
+       MX8MM_IOMUXC_NAND_CE1 = 63,
+       MX8MM_IOMUXC_NAND_CE2 = 64,
+       MX8MM_IOMUXC_NAND_CE3 = 65,
+       MX8MM_IOMUXC_NAND_CLE = 66,
+       MX8MM_IOMUXC_NAND_DATA00 = 67,
+       MX8MM_IOMUXC_NAND_DATA01 = 68,
+       MX8MM_IOMUXC_NAND_DATA02 = 69,
+       MX8MM_IOMUXC_NAND_DATA03 = 70,
+       MX8MM_IOMUXC_NAND_DATA04 = 71,
+       MX8MM_IOMUXC_NAND_DATA05 = 72,
+       MX8MM_IOMUXC_NAND_DATA06 = 73,
+       MX8MM_IOMUXC_NAND_DATA07 = 74,
+       MX8MM_IOMUXC_NAND_DQS = 75,
+       MX8MM_IOMUXC_NAND_RE_B = 76,
+       MX8MM_IOMUXC_NAND_READY_B = 77,
+       MX8MM_IOMUXC_NAND_WE_B = 78,
+       MX8MM_IOMUXC_NAND_WP_B = 79,
+       MX8MM_IOMUXC_SAI5_RXFS = 80,
+       MX8MM_IOMUXC_SAI5_RXC = 81,
+       MX8MM_IOMUXC_SAI5_RXD0 = 82,
+       MX8MM_IOMUXC_SAI5_RXD1 = 83,
+       MX8MM_IOMUXC_SAI5_RXD2 = 84,
+       MX8MM_IOMUXC_SAI5_RXD3 = 85,
+       MX8MM_IOMUXC_SAI5_MCLK = 86,
+       MX8MM_IOMUXC_SAI1_RXFS = 87,
+       MX8MM_IOMUXC_SAI1_RXC = 88,
+       MX8MM_IOMUXC_SAI1_RXD0 = 89,
+       MX8MM_IOMUXC_SAI1_RXD1 = 90,
+       MX8MM_IOMUXC_SAI1_RXD2 = 91,
+       MX8MM_IOMUXC_SAI1_RXD3 = 92,
+       MX8MM_IOMUXC_SAI1_RXD4 = 93,
+       MX8MM_IOMUXC_SAI1_RXD5 = 94,
+       MX8MM_IOMUXC_SAI1_RXD6 = 95,
+       MX8MM_IOMUXC_SAI1_RXD7 = 96,
+       MX8MM_IOMUXC_SAI1_TXFS = 97,
+       MX8MM_IOMUXC_SAI1_TXC = 98,
+       MX8MM_IOMUXC_SAI1_TXD0 = 99,
+       MX8MM_IOMUXC_SAI1_TXD1 = 100,
+       MX8MM_IOMUXC_SAI1_TXD2 = 101,
+       MX8MM_IOMUXC_SAI1_TXD3 = 102,
+       MX8MM_IOMUXC_SAI1_TXD4 = 103,
+       MX8MM_IOMUXC_SAI1_TXD5 = 104,
+       MX8MM_IOMUXC_SAI1_TXD6 = 105,
+       MX8MM_IOMUXC_SAI1_TXD7 = 106,
+       MX8MM_IOMUXC_SAI1_MCLK = 107,
+       MX8MM_IOMUXC_SAI2_RXFS = 108,
+       MX8MM_IOMUXC_SAI2_RXC = 109,
+       MX8MM_IOMUXC_SAI2_RXD0 = 110,
+       MX8MM_IOMUXC_SAI2_TXFS = 111,
+       MX8MM_IOMUXC_SAI2_TXC = 112,
+       MX8MM_IOMUXC_SAI2_TXD0 = 113,
+       MX8MM_IOMUXC_SAI2_MCLK = 114,
+       MX8MM_IOMUXC_SAI3_RXFS = 115,
+       MX8MM_IOMUXC_SAI3_RXC = 116,
+       MX8MM_IOMUXC_SAI3_RXD = 117,
+       MX8MM_IOMUXC_SAI3_TXFS = 118,
+       MX8MM_IOMUXC_SAI3_TXC = 119,
+       MX8MM_IOMUXC_SAI3_TXD = 120,
+       MX8MM_IOMUXC_SAI3_MCLK = 121,
+       MX8MM_IOMUXC_SPDIF_TX = 122,
+       MX8MM_IOMUXC_SPDIF_RX = 123,
+       MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
+       MX8MM_IOMUXC_ECSPI1_SCLK = 125,
+       MX8MM_IOMUXC_ECSPI1_MOSI = 126,
+       MX8MM_IOMUXC_ECSPI1_MISO = 127,
+       MX8MM_IOMUXC_ECSPI1_SS0 = 128,
+       MX8MM_IOMUXC_ECSPI2_SCLK = 129,
+       MX8MM_IOMUXC_ECSPI2_MOSI = 130,
+       MX8MM_IOMUXC_ECSPI2_MISO = 131,
+       MX8MM_IOMUXC_ECSPI2_SS0 = 132,
+       MX8MM_IOMUXC_I2C1_SCL = 133,
+       MX8MM_IOMUXC_I2C1_SDA = 134,
+       MX8MM_IOMUXC_I2C2_SCL = 135,
+       MX8MM_IOMUXC_I2C2_SDA = 136,
+       MX8MM_IOMUXC_I2C3_SCL = 137,
+       MX8MM_IOMUXC_I2C3_SDA = 138,
+       MX8MM_IOMUXC_I2C4_SCL = 139,
+       MX8MM_IOMUXC_I2C4_SDA = 140,
+       MX8MM_IOMUXC_UART1_RXD = 141,
+       MX8MM_IOMUXC_UART1_TXD = 142,
+       MX8MM_IOMUXC_UART2_RXD = 143,
+       MX8MM_IOMUXC_UART2_TXD = 144,
+       MX8MM_IOMUXC_UART3_RXD = 145,
+       MX8MM_IOMUXC_UART3_TXD = 146,
+       MX8MM_IOMUXC_UART4_RXD = 147,
+       MX8MM_IOMUXC_UART4_TXD = 148,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
+       IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
+       IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
+};
+
+static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
+       .pins = imx8mm_pinctrl_pads,
+       .npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
+       .gpr_compatible = "fsl,imx8mm-iomuxc-gpr",
+};
+
+static const struct of_device_id imx8mm_pinctrl_of_match[] = {
+       { .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
+       { /* sentinel */ }
+};
+
+static int imx8mm_pinctrl_probe(struct platform_device *pdev)
+{
+       return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info);
+}
+
+static struct platform_driver imx8mm_pinctrl_driver = {
+       .driver = {
+               .name = "imx8mm-pinctrl",
+               .of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
+               .suppress_bind_attrs = true,
+       },
+       .probe = imx8mm_pinctrl_probe,
+};
+
+static int __init imx8mm_pinctrl_init(void)
+{
+       return platform_driver_register(&imx8mm_pinctrl_driver);
+}
+arch_initcall(imx8mm_pinctrl_init);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qm.c b/drivers/pinctrl/freescale/pinctrl-imx8qm.c
new file mode 100644 (file)
index 0000000..0b6029b
--- /dev/null
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *     Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-imx.h"
+
+static const struct pinctrl_pin_desc imx8qm_pinctrl_pads[] = {
+       IMX_PINCTRL_PIN(IMX8QM_SIM0_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_SIM0_RST),
+       IMX_PINCTRL_PIN(IMX8QM_SIM0_IO),
+       IMX_PINCTRL_PIN(IMX8QM_SIM0_PD),
+       IMX_PINCTRL_PIN(IMX8QM_SIM0_POWER_EN),
+       IMX_PINCTRL_PIN(IMX8QM_SIM0_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM),
+       IMX_PINCTRL_PIN(IMX8QM_M40_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_M40_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_M40_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_M40_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_M41_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_M41_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_M41_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_M41_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_GPT0_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_GPT0_CAPTURE),
+       IMX_PINCTRL_PIN(IMX8QM_GPT0_COMPARE),
+       IMX_PINCTRL_PIN(IMX8QM_GPT1_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_GPT1_CAPTURE),
+       IMX_PINCTRL_PIN(IMX8QM_GPT1_COMPARE),
+       IMX_PINCTRL_PIN(IMX8QM_UART0_RX),
+       IMX_PINCTRL_PIN(IMX8QM_UART0_TX),
+       IMX_PINCTRL_PIN(IMX8QM_UART0_RTS_B),
+       IMX_PINCTRL_PIN(IMX8QM_UART0_CTS_B),
+       IMX_PINCTRL_PIN(IMX8QM_UART1_TX),
+       IMX_PINCTRL_PIN(IMX8QM_UART1_RX),
+       IMX_PINCTRL_PIN(IMX8QM_UART1_RTS_B),
+       IMX_PINCTRL_PIN(IMX8QM_UART1_CTS_B),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_PMIC_MEMC_ON),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_WDOG_OUT),
+       IMX_PINCTRL_PIN(IMX8QM_PMIC_I2C_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_PMIC_I2C_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_PMIC_EARLY_WARNING),
+       IMX_PINCTRL_PIN(IMX8QM_PMIC_INT_B),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_02),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_03),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_04),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_05),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_06),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_07),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE0),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE1),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE2),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE3),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE4),
+       IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE5),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS0_GPIO00),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS0_GPIO01),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C1_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C1_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS1_GPIO00),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS1_GPIO01),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C1_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C1_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_MCLK_OUT),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_MCLK_OUT),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_GPIO0_00),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_GPIO0_01),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_I2C0_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_I2C0_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_HDMI_TX0_TS_SCL),
+       IMX_PINCTRL_PIN(IMX8QM_HDMI_TX0_TS_SDA),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_FSR),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_FST),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_SCKR),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_SCKT),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX0),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX1),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX2_RX3),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX3_RX2),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX4_RX1),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX5_RX0),
+       IMX_PINCTRL_PIN(IMX8QM_SPDIF0_RX),
+       IMX_PINCTRL_PIN(IMX8QM_SPDIF0_TX),
+       IMX_PINCTRL_PIN(IMX8QM_SPDIF0_EXT_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_SPI3_SCK),
+       IMX_PINCTRL_PIN(IMX8QM_SPI3_SDO),
+       IMX_PINCTRL_PIN(IMX8QM_SPI3_SDI),
+       IMX_PINCTRL_PIN(IMX8QM_SPI3_CS0),
+       IMX_PINCTRL_PIN(IMX8QM_SPI3_CS1),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_FSR),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_FST),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_SCKR),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_SCKT),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX0),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX1),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX2_RX3),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX3_RX2),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX4_RX1),
+       IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX5_RX0),
+       IMX_PINCTRL_PIN(IMX8QM_MCLK_IN0),
+       IMX_PINCTRL_PIN(IMX8QM_MCLK_OUT0),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC),
+       IMX_PINCTRL_PIN(IMX8QM_SPI0_SCK),
+       IMX_PINCTRL_PIN(IMX8QM_SPI0_SDO),
+       IMX_PINCTRL_PIN(IMX8QM_SPI0_SDI),
+       IMX_PINCTRL_PIN(IMX8QM_SPI0_CS0),
+       IMX_PINCTRL_PIN(IMX8QM_SPI0_CS1),
+       IMX_PINCTRL_PIN(IMX8QM_SPI2_SCK),
+       IMX_PINCTRL_PIN(IMX8QM_SPI2_SDO),
+       IMX_PINCTRL_PIN(IMX8QM_SPI2_SDI),
+       IMX_PINCTRL_PIN(IMX8QM_SPI2_CS0),
+       IMX_PINCTRL_PIN(IMX8QM_SPI2_CS1),
+       IMX_PINCTRL_PIN(IMX8QM_SAI1_RXC),
+       IMX_PINCTRL_PIN(IMX8QM_SAI1_RXD),
+       IMX_PINCTRL_PIN(IMX8QM_SAI1_RXFS),
+       IMX_PINCTRL_PIN(IMX8QM_SAI1_TXC),
+       IMX_PINCTRL_PIN(IMX8QM_SAI1_TXD),
+       IMX_PINCTRL_PIN(IMX8QM_SAI1_TXFS),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN7),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN6),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN5),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN4),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN3),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN2),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN1),
+       IMX_PINCTRL_PIN(IMX8QM_ADC_IN0),
+       IMX_PINCTRL_PIN(IMX8QM_MLB_SIG),
+       IMX_PINCTRL_PIN(IMX8QM_MLB_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_MLB_DATA),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT),
+       IMX_PINCTRL_PIN(IMX8QM_FLEXCAN0_RX),
+       IMX_PINCTRL_PIN(IMX8QM_FLEXCAN0_TX),
+       IMX_PINCTRL_PIN(IMX8QM_FLEXCAN1_RX),
+       IMX_PINCTRL_PIN(IMX8QM_FLEXCAN1_TX),
+       IMX_PINCTRL_PIN(IMX8QM_FLEXCAN2_RX),
+       IMX_PINCTRL_PIN(IMX8QM_FLEXCAN2_TX),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR),
+       IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC0),
+       IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC1),
+       IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC2),
+       IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC3),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_3V3_USB3IO),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_RESET_B),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_VSELECT),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_RESET_B),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_VSELECT),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_WP),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_CD_B),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_MDIO),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_MDC),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_REFCLK_125M_25M),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_REFCLK_125M_25M),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_MDIO),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_MDC),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SS0_B),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SS1_B),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SCLK),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DQS),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA3),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA2),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA1),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA0),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA0),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA1),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA2),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA3),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DQS),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SS0_B),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SS1_B),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SCLK),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SCLK),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA0),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA1),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA2),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA3),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DQS),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SS0_B),
+       IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SS1_B),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0),
+       IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_CLKREQ_B),
+       IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_WAKE_B),
+       IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_PERST_B),
+       IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_CLKREQ_B),
+       IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_WAKE_B),
+       IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_PERST_B),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
+       IMX_PINCTRL_PIN(IMX8QM_USB_HSIC0_DATA),
+       IMX_PINCTRL_PIN(IMX8QM_USB_HSIC0_STROBE),
+       IMX_PINCTRL_PIN(IMX8QM_CALIBRATION_0_HSIC),
+       IMX_PINCTRL_PIN(IMX8QM_CALIBRATION_1_HSIC),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_CMD),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA0),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA1),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA2),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA3),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA4),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA5),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA6),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA7),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_STROBE),
+       IMX_PINCTRL_PIN(IMX8QM_EMMC0_RESET_B),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_CMD),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA0),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA1),
+       IMX_PINCTRL_PIN(IMX8QM_CTL_NAND_RE_P_N),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA2),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA3),
+       IMX_PINCTRL_PIN(IMX8QM_CTL_NAND_DQS_P_N),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA4),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA5),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA6),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA7),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC1_STROBE),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_CLK),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_CMD),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA0),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA1),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA2),
+       IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA3),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXC),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TX_CTL),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD0),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD1),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD2),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD3),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXC),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RX_CTL),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD0),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD1),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD2),
+       IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD3),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXC),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TX_CTL),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD0),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD1),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD2),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD3),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXC),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RX_CTL),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD0),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD1),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD2),
+       IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD3),
+       IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA),
+};
+
+static const struct imx_pinctrl_soc_info imx8qm_pinctrl_info = {
+       .pins = imx8qm_pinctrl_pads,
+       .npins = ARRAY_SIZE(imx8qm_pinctrl_pads),
+       .flags = IMX_USE_SCU,
+};
+
+static const struct of_device_id imx8qm_pinctrl_of_match[] = {
+       { .compatible = "fsl,imx8qm-iomuxc", },
+       { /* sentinel */ }
+};
+
+static int imx8qm_pinctrl_probe(struct platform_device *pdev)
+{
+       int ret;
+
+       ret = imx_pinctrl_sc_ipc_init(pdev);
+       if (ret)
+               return ret;
+
+       return imx_pinctrl_probe(pdev, &imx8qm_pinctrl_info);
+}
+
+static struct platform_driver imx8qm_pinctrl_driver = {
+       .driver = {
+               .name = "imx8qm-pinctrl",
+               .of_match_table = of_match_ptr(imx8qm_pinctrl_of_match),
+               .suppress_bind_attrs = true,
+       },
+       .probe = imx8qm_pinctrl_probe,
+};
+
+static int __init imx8qm_pinctrl_init(void)
+{
+       return platform_driver_register(&imx8qm_pinctrl_driver);
+}
+arch_initcall(imx8qm_pinctrl_init);
index 4a9e0d4c2bbcbd3bf6e560a80be37fc7508afa2c..b1c368455d30ec4d9fbccd331ce7b2ac2cf7f039 100644 (file)
@@ -290,7 +290,13 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
                return err;
 
        err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
-       if (err)
+       /* SMT is supposed to be supported by every real GPIO and doesn't
+        * support virtual GPIOs, so the extra condition err != -ENOTSUPP
+        * is just for adding EINT support to these virtual GPIOs. It should
+        * add an extra flag in the pin descriptor when more pins with
+        * distinctive characteristic come out.
+        */
+       if (err && err != -ENOTSUPP)
                return err;
 
        return 0;
index ea87d739f534bdf9ede84639486cf3e41195ae7b..96a4a72708e49a47910026b78befe36402b3c50a 100644 (file)
@@ -31,6 +31,9 @@
  * In some cases the register ranges for pull enable and pull
  * direction are the same and thus there are only 3 register ranges.
  *
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
  * For the pull and GPIO configuration every bank uses a contiguous
  * set of bits in the register sets described above; the same register
  * can be shared by more banks with different offsets.
@@ -488,21 +491,26 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
                return PTR_ERR(pc->reg_mux);
        }
 
-       pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
-       if (IS_ERR(pc->reg_pull)) {
-               dev_err(pc->dev, "pull registers not found\n");
-               return PTR_ERR(pc->reg_pull);
+       pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+       if (IS_ERR(pc->reg_gpio)) {
+               dev_err(pc->dev, "gpio registers not found\n");
+               return PTR_ERR(pc->reg_gpio);
        }
 
+       pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+       /* Use gpio region if pull one is not present */
+       if (IS_ERR(pc->reg_pull))
+               pc->reg_pull = pc->reg_gpio;
+
        pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
        /* Use pull region if pull-enable one is not present */
        if (IS_ERR(pc->reg_pullen))
                pc->reg_pullen = pc->reg_pull;
 
-       pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
-       if (IS_ERR(pc->reg_gpio)) {
-               dev_err(pc->dev, "gpio registers not found\n");
-               return PTR_ERR(pc->reg_gpio);
+       pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
+       if (IS_ERR(pc->reg_ds)) {
+               dev_dbg(pc->dev, "ds registers not found - skipping\n");
+               pc->reg_ds = NULL;
        }
 
        return 0;
index eff61ea1c67e08235866938b1edc0e967d42c41e..5eaab925f427fcefe7c0f556ccbfe22d9845fc63 100644 (file)
@@ -120,6 +120,7 @@ struct meson_pinctrl {
        struct regmap *reg_pullen;
        struct regmap *reg_pull;
        struct regmap *reg_gpio;
+       struct regmap *reg_ds;
        struct gpio_chip chip;
        struct device_node *of_node;
 };
index 0f140a8021375a5d829f94d35c7145f75126a696..7f76000cc12ed52a99db4736920ed6fa4f8adadd 100644 (file)
@@ -346,6 +346,8 @@ static const unsigned int eth_rx_dv_pins[]  = { DIF_1_P };
 static const unsigned int eth_rx_clk_pins[]    = { DIF_1_N };
 static const unsigned int eth_txd0_1_pins[]    = { DIF_2_P };
 static const unsigned int eth_txd1_1_pins[]    = { DIF_2_N };
+static const unsigned int eth_rxd3_pins[]      = { DIF_2_P };
+static const unsigned int eth_rxd2_pins[]      = { DIF_2_N };
 static const unsigned int eth_tx_en_pins[]     = { DIF_3_P };
 static const unsigned int eth_ref_clk_pins[]   = { DIF_3_N };
 static const unsigned int eth_mdc_pins[]       = { DIF_4_P };
@@ -599,6 +601,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {
        GROUP(eth_ref_clk,      6,      8),
        GROUP(eth_mdc,          6,      9),
        GROUP(eth_mdio_en,      6,      10),
+       GROUP(eth_rxd3,         7,      22),
+       GROUP(eth_rxd2,         7,      23),
 };
 
 static struct meson_pmx_group meson8b_aobus_groups[] = {
@@ -748,7 +752,7 @@ static const char * const ethernet_groups[] = {
        "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
        "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
        "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
-       "eth_txd2", "eth_txd3"
+       "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2"
 };
 
 static const char * const i2c_a_groups[] = {
index aa48b3f23c7fd199138a6896328679569d2b8a75..6462d3ca7ceb9b44b406015397102eadec5c2f99 100644 (file)
@@ -170,8 +170,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
        PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
        PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
        PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
-       PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
-       PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
+       PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
+       PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
        PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
        PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
        PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
@@ -195,8 +195,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
        PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
        PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
        PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
-       PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
-       PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
+       PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
+       PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
+       PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
+       PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
+       PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
        PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
        PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
        PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
@@ -1104,8 +1107,8 @@ static int armada_3700_pinctrl_resume(struct device *dev)
  * to other IO drivers.
  */
 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
-       .suspend_late = armada_3700_pinctrl_suspend,
-       .resume_early = armada_3700_pinctrl_resume,
+       .suspend_noirq = armada_3700_pinctrl_suspend,
+       .resume_noirq = armada_3700_pinctrl_resume,
 };
 
 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
index 4cc2c47f87783f89ac1719d81e47fa1016136f80..ec02739bd21b43a4787542fefcc253816fadb630 100644 (file)
@@ -1056,17 +1056,22 @@ static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
        }
        if (of_property_read_u32(np, "gpio-bank", &id)) {
                dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
+               platform_device_put(gpio_pdev);
                return ERR_PTR(-EINVAL);
        }
 
        /* Already populated? */
        nmk_chip = nmk_gpio_chips[id];
-       if (nmk_chip)
+       if (nmk_chip) {
+               platform_device_put(gpio_pdev);
                return nmk_chip;
+       }
 
        nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
-       if (!nmk_chip)
+       if (!nmk_chip) {
+               platform_device_put(gpio_pdev);
                return ERR_PTR(-ENOMEM);
+       }
 
        nmk_chip->bank = id;
        chip = &nmk_chip->chip;
@@ -1077,13 +1082,17 @@ static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
 
        res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
        base = devm_ioremap_resource(&pdev->dev, res);
-       if (IS_ERR(base))
+       if (IS_ERR(base)) {
+               platform_device_put(gpio_pdev);
                return ERR_CAST(base);
+       }
        nmk_chip->addr = base;
 
        clk = clk_get(&gpio_pdev->dev, NULL);
-       if (IS_ERR(clk))
+       if (IS_ERR(clk)) {
+               platform_device_put(gpio_pdev);
                return (void *) clk;
+       }
        clk_prepare(clk);
        nmk_chip->clk = clk;
 
index 2c7229380f081a998ceb838c95bc14b70056462f..2678603df14b46bb7beaa2da93284b47bc1ed19b 100644 (file)
@@ -17,7 +17,6 @@
 #include <linux/slab.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
-#include <linux/uaccess.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinconf.h>
@@ -369,225 +368,6 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
 DEFINE_SHOW_ATTRIBUTE(pinconf_pins);
 DEFINE_SHOW_ATTRIBUTE(pinconf_groups);
 
-#define MAX_NAME_LEN 15
-
-struct dbg_cfg {
-       enum pinctrl_map_type map_type;
-       char dev_name[MAX_NAME_LEN + 1];
-       char state_name[MAX_NAME_LEN + 1];
-       char pin_name[MAX_NAME_LEN + 1];
-};
-
-/*
- * Goal is to keep this structure as global in order to simply read the
- * pinconf-config file after a write to check config is as expected
- */
-static struct dbg_cfg pinconf_dbg_conf;
-
-/**
- * pinconf_dbg_config_print() - display the pinctrl config from the pinctrl
- * map, of the dev/pin/state that was last written to pinconf-config file.
- * @s: string filled in  with config description
- * @d: not used
- */
-static int pinconf_dbg_config_print(struct seq_file *s, void *d)
-{
-       struct pinctrl_maps *maps_node;
-       const struct pinctrl_map *map;
-       const struct pinctrl_map *found = NULL;
-       struct pinctrl_dev *pctldev;
-       struct dbg_cfg *dbg = &pinconf_dbg_conf;
-       int i;
-
-       mutex_lock(&pinctrl_maps_mutex);
-
-       /* Parse the pinctrl map and look for the elected pin/state */
-       for_each_maps(maps_node, i, map) {
-               if (map->type != dbg->map_type)
-                       continue;
-               if (strcmp(map->dev_name, dbg->dev_name))
-                       continue;
-               if (strcmp(map->name, dbg->state_name))
-                       continue;
-
-               if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) {
-                       /* We found the right pin */
-                       found = map;
-                       break;
-               }
-       }
-
-       if (!found) {
-               seq_printf(s, "No config found for dev/state/pin, expected:\n");
-               seq_printf(s, "Searched dev:%s\n", dbg->dev_name);
-               seq_printf(s, "Searched state:%s\n", dbg->state_name);
-               seq_printf(s, "Searched pin:%s\n", dbg->pin_name);
-               seq_printf(s, "Use: modify config_pin <devname> "\
-                               "<state> <pinname> <value>\n");
-               goto exit;
-       }
-
-       pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name);
-       seq_printf(s, "Dev %s has config of %s in state %s:\n",
-                  dbg->dev_name, dbg->pin_name, dbg->state_name);
-       pinconf_show_config(s, pctldev, found->data.configs.configs,
-                           found->data.configs.num_configs);
-
-exit:
-       mutex_unlock(&pinctrl_maps_mutex);
-
-       return 0;
-}
-
-/**
- * pinconf_dbg_config_write() - modify the pinctrl config in the pinctrl
- * map, of a dev/pin/state entry based on user entries to pinconf-config
- * @user_buf: contains the modification request with expected format:
- *     modify <config> <devicename> <state> <name> <newvalue>
- * modify is literal string, alternatives like add/delete not supported yet
- * <config> is the configuration to be changed. Supported configs are
- *     "config_pin" or "config_group", alternatives like config_mux are not
- *     supported yet.
- * <devicename> <state> <name> are values that should match the pinctrl-maps
- * <newvalue> reflects the new config and is driver dependent
- */
-static ssize_t pinconf_dbg_config_write(struct file *file,
-       const char __user *user_buf, size_t count, loff_t *ppos)
-{
-       struct pinctrl_maps *maps_node;
-       const struct pinctrl_map *map;
-       const struct pinctrl_map *found = NULL;
-       struct pinctrl_dev *pctldev;
-       const struct pinconf_ops *confops = NULL;
-       struct dbg_cfg *dbg = &pinconf_dbg_conf;
-       const struct pinctrl_map_configs *configs;
-       char config[MAX_NAME_LEN + 1];
-       char buf[128];
-       char *b = &buf[0];
-       int buf_size;
-       char *token;
-       int i;
-
-       /* Get userspace string and assure termination */
-       buf_size = min(count, sizeof(buf) - 1);
-       if (copy_from_user(buf, user_buf, buf_size))
-               return -EFAULT;
-       buf[buf_size] = 0;
-
-       /*
-        * need to parse entry and extract parameters:
-        * modify configs_pin devicename state pinname newvalue
-        */
-
-       /* Get arg: 'modify' */
-       token = strsep(&b, " ");
-       if (!token)
-               return -EINVAL;
-       if (strcmp(token, "modify"))
-               return -EINVAL;
-
-       /*
-        * Get arg type: "config_pin" and "config_group"
-        *                types are supported so far
-        */
-       token = strsep(&b, " ");
-       if (!token)
-               return -EINVAL;
-       if (!strcmp(token, "config_pin"))
-               dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN;
-       else if (!strcmp(token, "config_group"))
-               dbg->map_type = PIN_MAP_TYPE_CONFIGS_GROUP;
-       else
-               return -EINVAL;
-
-       /* get arg 'device_name' */
-       token = strsep(&b, " ");
-       if (!token)
-               return -EINVAL;
-       if (strlen(token) >= MAX_NAME_LEN)
-               return -EINVAL;
-       strncpy(dbg->dev_name, token, MAX_NAME_LEN);
-
-       /* get arg 'state_name' */
-       token = strsep(&b, " ");
-       if (!token)
-               return -EINVAL;
-       if (strlen(token) >= MAX_NAME_LEN)
-               return -EINVAL;
-       strncpy(dbg->state_name, token, MAX_NAME_LEN);
-
-       /* get arg 'pin_name' */
-       token = strsep(&b, " ");
-       if (!token)
-               return -EINVAL;
-       if (strlen(token) >= MAX_NAME_LEN)
-               return -EINVAL;
-       strncpy(dbg->pin_name, token, MAX_NAME_LEN);
-
-       /* get new_value of config' */
-       token = strsep(&b, " ");
-       if (!token)
-               return -EINVAL;
-       if (strlen(token) >= MAX_NAME_LEN)
-               return -EINVAL;
-       strncpy(config, token, MAX_NAME_LEN);
-
-       mutex_lock(&pinctrl_maps_mutex);
-
-       /* Parse the pinctrl map and look for the selected dev/state/pin */
-       for_each_maps(maps_node, i, map) {
-               if (strcmp(map->dev_name, dbg->dev_name))
-                       continue;
-               if (map->type != dbg->map_type)
-                       continue;
-               if (strcmp(map->name, dbg->state_name))
-                       continue;
-
-               /*  we found the right pin / state, so overwrite config */
-               if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) {
-                       found = map;
-                       break;
-               }
-       }
-
-       if (!found) {
-               count = -EINVAL;
-               goto exit;
-       }
-
-       pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name);
-       if (pctldev)
-               confops = pctldev->desc->confops;
-
-       if (confops && confops->pin_config_dbg_parse_modify) {
-               configs = &found->data.configs;
-               for (i = 0; i < configs->num_configs; i++) {
-                       confops->pin_config_dbg_parse_modify(pctldev,
-                                                    config,
-                                                    &configs->configs[i]);
-               }
-       }
-
-exit:
-       mutex_unlock(&pinctrl_maps_mutex);
-
-       return count;
-}
-
-static int pinconf_dbg_config_open(struct inode *inode, struct file *file)
-{
-       return single_open(file, pinconf_dbg_config_print, inode->i_private);
-}
-
-static const struct file_operations pinconf_dbg_pinconfig_fops = {
-       .open = pinconf_dbg_config_open,
-       .write = pinconf_dbg_config_write,
-       .read = seq_read,
-       .llseek = seq_lseek,
-       .release = single_release,
-       .owner = THIS_MODULE,
-};
-
 void pinconf_init_device_debugfs(struct dentry *devroot,
                         struct pinctrl_dev *pctldev)
 {
@@ -595,8 +375,6 @@ void pinconf_init_device_debugfs(struct dentry *devroot,
                            devroot, pctldev, &pinconf_pins_fops);
        debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO,
                            devroot, pctldev, &pinconf_groups_fops);
-       debugfs_create_file("pinconf-config",  (S_IRUGO | S_IWUSR | S_IWGRP),
-                           devroot, pctldev, &pinconf_dbg_pinconfig_fops);
 }
 
 #endif
index 2a7d638978d804837793c7bcb54927eefe10b696..6689995fa3aa614cc47e8bd2971ba473a947efc3 100644 (file)
@@ -489,7 +489,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        /*
         * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
         * debounce registers of any GPIO will block wake/interrupt status
-        * generation for *all* GPIOs for a lenght of time that depends on
+        * generation for *all* GPIOs for a length of time that depends on
         * WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the
         * INTERRUPT_ENABLE bit will read as 0.
         *
index 3d49bbbcdbc7dcad74e0d51c9784d94e322df7cb..cb7c432769a5ece3775c31c70d3f13a387313d7b 100644 (file)
@@ -59,6 +59,9 @@ static int gpio_banks;
 #define OUTPUT         (1 << 7)
 #define OUTPUT_VAL_SHIFT       8
 #define OUTPUT_VAL     (0x1 << OUTPUT_VAL_SHIFT)
+#define SLEWRATE_SHIFT 9
+#define SLEWRATE_MASK  0x1
+#define SLEWRATE       (SLEWRATE_MASK << SLEWRATE_SHIFT)
 #define DEBOUNCE       (1 << 16)
 #define DEBOUNCE_VAL_SHIFT     17
 #define DEBOUNCE_VAL   (0x3fff << DEBOUNCE_VAL_SHIFT)
@@ -72,10 +75,22 @@ static int gpio_banks;
  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
  * strength when there is no dt config for it.
  */
-#define DRIVE_STRENGTH_DEFAULT         (0 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_LOW          (1 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_MED          (2 << DRIVE_STRENGTH_SHIFT)
-#define DRIVE_STRENGTH_HI           (3 << DRIVE_STRENGTH_SHIFT)
+enum drive_strength_bit {
+       DRIVE_STRENGTH_BIT_DEF,
+       DRIVE_STRENGTH_BIT_LOW,
+       DRIVE_STRENGTH_BIT_MED,
+       DRIVE_STRENGTH_BIT_HI,
+};
+
+#define DRIVE_STRENGTH_BIT_MSK(name)   (DRIVE_STRENGTH_BIT_##name << \
+                                        DRIVE_STRENGTH_SHIFT)
+
+enum slewrate_bit {
+       SLEWRATE_BIT_DIS,
+       SLEWRATE_BIT_ENA,
+};
+
+#define SLEWRATE_BIT_MSK(name)         (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
 
 /**
  * struct at91_pmx_func - describes AT91 pinmux functions
@@ -166,6 +181,8 @@ struct at91_pinctrl_mux_ops {
        unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
        void (*set_drivestrength)(void __iomem *pio, unsigned pin,
                                        u32 strength);
+       unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
+       void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
        /* irq */
        int (*irq_type)(struct irq_data *d, unsigned type);
 };
@@ -551,7 +568,7 @@ static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
        /* SAMA5 strength is 1:1 with our defines,
         * except 0 is equivalent to low per datasheet */
        if (!tmp)
-               tmp = DRIVE_STRENGTH_LOW;
+               tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
 
        return tmp;
 }
@@ -564,11 +581,32 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
 
        /* strength is inverse in SAM9x5s hardware with the pinctrl defines
         * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
-       tmp = DRIVE_STRENGTH_HI - tmp;
+       tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
 
        return tmp;
 }
 
+static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
+                                                  unsigned pin)
+{
+       unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+       if (tmp & BIT(pin))
+               return DRIVE_STRENGTH_BIT_HI;
+
+       return DRIVE_STRENGTH_BIT_LOW;
+}
+
+static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
+{
+       unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+       if ((tmp & BIT(pin)))
+               return SLEWRATE_BIT_ENA;
+
+       return SLEWRATE_BIT_DIS;
+}
+
 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
 {
        unsigned tmp = readl_relaxed(reg);
@@ -600,12 +638,51 @@ static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
 
        /* strength is inverse on SAM9x5s with our defines
         * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
-       setting = DRIVE_STRENGTH_HI - setting;
+       setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
 
        set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
                                setting);
 }
 
+static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
+                                              u32 setting)
+{
+       unsigned int tmp;
+
+       if (setting <= DRIVE_STRENGTH_BIT_DEF ||
+           setting == DRIVE_STRENGTH_BIT_MED ||
+           setting > DRIVE_STRENGTH_BIT_HI)
+               return;
+
+       tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
+
+       /* Strength is 0: low, 1: hi */
+       if (setting == DRIVE_STRENGTH_BIT_LOW)
+               tmp &= ~BIT(pin);
+       else
+               tmp |= BIT(pin);
+
+       writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
+}
+
+static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
+                                         u32 setting)
+{
+       unsigned int tmp;
+
+       if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+               return;
+
+       tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
+
+       if (setting == SLEWRATE_BIT_DIS)
+               tmp &= ~BIT(pin);
+       else
+               tmp |= BIT(pin);
+
+       writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
+}
+
 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
        .get_periph     = at91_mux_get_periph,
        .mux_A_periph   = at91_mux_set_A_periph,
@@ -634,6 +711,28 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
        .irq_type       = alt_gpio_irq_type,
 };
 
+static const struct at91_pinctrl_mux_ops sam9x60_ops = {
+       .get_periph     = at91_mux_pio3_get_periph,
+       .mux_A_periph   = at91_mux_pio3_set_A_periph,
+       .mux_B_periph   = at91_mux_pio3_set_B_periph,
+       .mux_C_periph   = at91_mux_pio3_set_C_periph,
+       .mux_D_periph   = at91_mux_pio3_set_D_periph,
+       .get_deglitch   = at91_mux_pio3_get_deglitch,
+       .set_deglitch   = at91_mux_pio3_set_deglitch,
+       .get_debounce   = at91_mux_pio3_get_debounce,
+       .set_debounce   = at91_mux_pio3_set_debounce,
+       .get_pulldown   = at91_mux_pio3_get_pulldown,
+       .set_pulldown   = at91_mux_pio3_set_pulldown,
+       .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
+       .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+       .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
+       .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
+       .get_slewrate   = at91_mux_sam9x60_get_slewrate,
+       .set_slewrate   = at91_mux_sam9x60_set_slewrate,
+       .irq_type       = alt_gpio_irq_type,
+
+};
+
 static struct at91_pinctrl_mux_ops sama5d3_ops = {
        .get_periph     = at91_mux_pio3_get_periph,
        .mux_A_periph   = at91_mux_pio3_set_A_periph,
@@ -893,6 +992,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
        if (info->ops->get_drivestrength)
                *config |= (info->ops->get_drivestrength(pio, pin)
                                << DRIVE_STRENGTH_SHIFT);
+       if (info->ops->get_slewrate)
+               *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
        if (at91_mux_get_output(pio, pin, &out))
                *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
 
@@ -944,6 +1045,9 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
                        info->ops->set_drivestrength(pio, pin,
                                (config & DRIVE_STRENGTH)
                                        >> DRIVE_STRENGTH_SHIFT);
+               if (info->ops->set_slewrate)
+                       info->ops->set_slewrate(pio, pin,
+                               (config & SLEWRATE) >> SLEWRATE_SHIFT);
 
        } /* for each config */
 
@@ -959,11 +1063,11 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
        }                                       \
 } while (0)
 
-#define DBG_SHOW_FLAG_MASKED(mask,flag) do {   \
+#define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
        if ((config & mask) == flag) {          \
                if (num_conf)                   \
                        seq_puts(s, "|");       \
-               seq_puts(s, #flag);             \
+               seq_puts(s, #name);             \
                num_conf++;                     \
        }                                       \
 } while (0)
@@ -981,9 +1085,13 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
        DBG_SHOW_FLAG(PULL_DOWN);
        DBG_SHOW_FLAG(DIS_SCHMIT);
        DBG_SHOW_FLAG(DEGLITCH);
-       DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
-       DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
-       DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
+       DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
+                            DRIVE_STRENGTH_LOW);
+       DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
+                            DRIVE_STRENGTH_MED);
+       DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
+                            DRIVE_STRENGTH_HI);
+       DBG_SHOW_FLAG(SLEWRATE);
        DBG_SHOW_FLAG(DEBOUNCE);
        if (config & DEBOUNCE) {
                val = config >> DEBOUNCE_VAL_SHIFT;
@@ -1155,6 +1263,7 @@ static const struct of_device_id at91_pinctrl_of_match[] = {
        { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
        { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
        { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
+       { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
        { /* sentinel */ }
 };
 
@@ -1697,6 +1806,7 @@ static const struct gpio_chip at91_gpio_template = {
 static const struct of_device_id at91_gpio_of_match[] = {
        { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
        { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
+       { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
        { /* sentinel */ }
 };
 
index 79b957f1dfa2900cdf50b1ba2ea6c6703b44d0f6..223620f14b05ee31cee7f187e38c213b7c30a41d 100644 (file)
@@ -69,4 +69,7 @@
 #define AT91SAM9X5_PIO_DRIVER1 0x114  /*PIO Driver 1 register offset*/
 #define AT91SAM9X5_PIO_DRIVER2 0x118  /*PIO Driver 2 register offset*/
 
+#define SAM9X60_PIO_SLEWR      0x110   /* PIO Slew Rate Control Register */
+#define SAM9X60_PIO_DRIVER1    0x118   /* PIO Driver 1 register offset */
+
 #endif
index db6b48ea5f473047401957aa252052be8bdc4b6c..bc21ceb15d68137a36caef78b234f63133dbb7d5 100644 (file)
@@ -233,6 +233,19 @@ static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
+static int jz4725b_lcd_8bit_pins[] = {
+       0x72, 0x73, 0x74,
+       0x60, 0x61, 0x62, 0x63,
+       0x64, 0x65, 0x66, 0x67,
+};
+static int jz4725b_lcd_16bit_pins[] = {
+       0x68, 0x69, 0x6a, 0x6b,
+       0x6c, 0x6d, 0x6e, 0x6f,
+};
+static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
+static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
+static int jz4725b_lcd_generic_pins[] = { 0x75, };
 
 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
@@ -251,6 +264,12 @@ static int jz4725b_pwm_pwm2_funcs[] = { 0, };
 static int jz4725b_pwm_pwm3_funcs[] = { 0, };
 static int jz4725b_pwm_pwm4_funcs[] = { 0, };
 static int jz4725b_pwm_pwm5_funcs[] = { 0, };
+static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
+static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
+static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
+static int jz4725b_lcd_generic_funcs[] = { 0, };
 
 static const struct group_desc jz4725b_groups[] = {
        INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
@@ -270,6 +289,12 @@ static const struct group_desc jz4725b_groups[] = {
        INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
        INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
        INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
+       INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
+       INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
+       INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
+       INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
+       INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
+       INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
 };
 
 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
@@ -285,6 +310,10 @@ static const char *jz4725b_pwm2_groups[] = { "pwm2", };
 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
+static const char *jz4725b_lcd_groups[] = {
+       "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
+       "lcd-special", "lcd-generic",
+};
 
 static const struct function_desc jz4725b_functions[] = {
        { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
@@ -297,6 +326,7 @@ static const struct function_desc jz4725b_functions[] = {
        { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
        { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
        { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
+       { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
 };
 
 static const struct ingenic_chip_info jz4725b_chip_info = {
@@ -321,47 +351,57 @@ static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
-static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
-static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
+static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
-static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
-static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
-static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
-static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
-static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_nemc_data_pins[] = {
+static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_nemc_8bit_data_pins[] = {
        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
+static int jz4770_nemc_16bit_data_pins[] = {
+       0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4770_nemc_wait_pins[] = { 0x1b, };
 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 static int jz4770_nemc_cs3_pins[] = { 0x17, };
 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
-static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
-static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
+static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
-static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
-static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
-static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
-static int jz4770_cim_pins[] = {
-       0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+static int jz4770_cim_8bit_pins[] = {
+       0x26, 0x27, 0x28, 0x29,
+       0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4770_cim_12bit_pins[] = {
+       0x32, 0x33, 0xb0, 0xb1,
 };
-static int jz4770_lcd_32bit_pins[] = {
+static int jz4770_lcd_24bit_pins[] = {
        0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
        0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
        0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-       0x58, 0x59, 0x51,
+       0x58, 0x59, 0x5a, 0x5b,
 };
 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
@@ -371,30 +411,41 @@ static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
+static int jz4770_mac_rmii_pins[] = {
+       0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
+};
+static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
 
 static int jz4770_uart0_data_funcs[] = { 0, 0, };
 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
 static int jz4770_uart1_data_funcs[] = { 0, 0, };
 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart2_data_funcs[] = { 1, 1, };
-static int jz4770_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4770_uart2_data_funcs[] = { 0, 0, };
+static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
 static int jz4770_uart3_data_funcs[] = { 0, 1, };
 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart4_data_funcs[] = { 2, 2, };
-static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
-static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
-static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
-static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
+static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
+static int jz4770_nemc_wait_funcs[] = { 0, };
 static int jz4770_nemc_cs1_funcs[] = { 0, };
 static int jz4770_nemc_cs2_funcs[] = { 0, };
 static int jz4770_nemc_cs3_funcs[] = { 0, };
@@ -404,14 +455,13 @@ static int jz4770_nemc_cs6_funcs[] = { 0, };
 static int jz4770_i2c0_funcs[] = { 0, 0, };
 static int jz4770_i2c1_funcs[] = { 0, 0, };
 static int jz4770_i2c2_funcs[] = { 2, 2, };
-static int jz4770_i2c3_funcs[] = { 1, 1, };
-static int jz4770_i2c4_e_funcs[] = { 1, 1, };
-static int jz4770_i2c4_f_funcs[] = { 1, 1, };
-static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_lcd_32bit_funcs[] = {
+static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
+static int jz4770_lcd_24bit_funcs[] = {
+       0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0,
-       0, 0, 0,
+       0, 0, 0, 0,
 };
 static int jz4770_pwm_pwm0_funcs[] = { 0, };
 static int jz4770_pwm_pwm1_funcs[] = { 0, };
@@ -421,6 +471,8 @@ static int jz4770_pwm_pwm4_funcs[] = { 0, };
 static int jz4770_pwm_pwm5_funcs[] = { 0, };
 static int jz4770_pwm_pwm6_funcs[] = { 0, };
 static int jz4770_pwm_pwm7_funcs[] = { 0, };
+static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mac_mii_funcs[] = { 0, 0, };
 
 static const struct group_desc jz4770_groups[] = {
        INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
@@ -431,21 +483,28 @@ static const struct group_desc jz4770_groups[] = {
        INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
        INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
        INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
-       INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data),
-       INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a),
-       INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
        INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
-       INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+       INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
        INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
-       INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+       INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+       INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
        INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
-       INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+       INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
        INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
-       INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data),
+       INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+       INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
+       INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+       INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+       INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+       INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
+       INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
+       INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
+       INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
        INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
        INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
        INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
        INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+       INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
        INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
        INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
        INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
@@ -455,11 +514,9 @@ static const struct group_desc jz4770_groups[] = {
        INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
        INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
        INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
-       INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3),
-       INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e),
-       INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f),
-       INGENIC_PIN_GROUP("cim-data", jz4770_cim),
-       INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit),
+       INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
+       INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
+       INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
        { "lcd-no-pins", },
        INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
        INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
@@ -469,32 +526,41 @@ static const struct group_desc jz4770_groups[] = {
        INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
        INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
        INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+       INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
+       INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
 };
 
 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
-static const char *jz4770_uart4_groups[] = { "uart4-data", };
 static const char *jz4770_mmc0_groups[] = {
-       "mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a",
-       "mmc0-1bit-e", "mmc0-4bit-e",
+       "mmc0-1bit-a", "mmc0-4bit-a",
+       "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 };
 static const char *jz4770_mmc1_groups[] = {
-       "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+       "mmc1-1bit-d", "mmc1-4bit-d",
+       "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
+};
+static const char *jz4770_mmc2_groups[] = {
+       "mmc2-1bit-b", "mmc2-4bit-b",
+       "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
 };
 static const char *jz4770_nemc_groups[] = {
-       "nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
+       "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
+       "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
+static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
+static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
+static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
+static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
-static const char *jz4770_i2c3_groups[] = { "i2c3-data", };
-static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
-static const char *jz4770_cim_groups[] = { "cim-data", };
-static const char *jz4770_lcd_groups[] = { "lcd-32bit", "lcd-no-pins", };
+static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
+static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
 static const char *jz4770_pwm0_groups[] = { "pwm0", };
 static const char *jz4770_pwm1_groups[] = { "pwm1", };
 static const char *jz4770_pwm2_groups[] = { "pwm2", };
@@ -503,23 +569,26 @@ static const char *jz4770_pwm4_groups[] = { "pwm4", };
 static const char *jz4770_pwm5_groups[] = { "pwm5", };
 static const char *jz4770_pwm6_groups[] = { "pwm6", };
 static const char *jz4770_pwm7_groups[] = { "pwm7", };
+static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
 
 static const struct function_desc jz4770_functions[] = {
        { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
        { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
        { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
        { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
-       { "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), },
        { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
        { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
+       { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
        { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
        { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+       { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
+       { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
+       { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
+       { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
        { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
        { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
        { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
        { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
-       { "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), },
-       { "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), },
        { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
        { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
        { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
@@ -530,6 +599,7 @@ static const struct function_desc jz4770_functions[] = {
        { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
        { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
        { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+       { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
 };
 
 static const struct ingenic_chip_info jz4770_chip_info = {
@@ -542,7 +612,140 @@ static const struct ingenic_chip_info jz4770_chip_info = {
        .pull_downs = jz4770_pull_downs,
 };
 
-static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
+static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
+static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
+static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
+static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
+static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
+static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
+
+static int jz4780_uart2_data_funcs[] = { 1, 1, };
+static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4780_uart4_data_funcs[] = { 2, 2, };
+static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
+static int jz4780_i2c3_funcs[] = { 1, 1, };
+static int jz4780_i2c4_e_funcs[] = { 1, 1, };
+static int jz4780_i2c4_f_funcs[] = { 1, 1, };
+
+static const struct group_desc jz4780_groups[] = {
+       INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
+       INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
+       INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
+       INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
+       INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
+       INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
+       INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
+       INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
+       INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
+       INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
+       INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
+       INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
+       INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
+       INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+       INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
+       INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+       INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
+       INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+       INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+       INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+       INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+       INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
+       INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
+       INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
+       INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
+       INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
+       INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+       INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
+       INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
+       INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
+       INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
+       INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
+       INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
+       INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
+       INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
+       INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
+       INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
+       INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
+       INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
+       INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
+       INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
+       INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
+       { "lcd-no-pins", },
+       INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
+       INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
+       INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
+       INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
+       INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
+       INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
+       INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
+       INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+};
+
+static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
+static const char *jz4780_uart4_groups[] = { "uart4-data", };
+static const char *jz4780_mmc0_groups[] = {
+       "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
+       "mmc0-1bit-e", "mmc0-4bit-e",
+};
+static const char *jz4780_mmc1_groups[] = {
+       "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+};
+static const char *jz4780_mmc2_groups[] = {
+       "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
+};
+static const char *jz4780_nemc_groups[] = {
+       "nemc-data", "nemc-cle-ale", "nemc-addr",
+       "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
+};
+static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
+static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
+static const char *jz4780_cim_groups[] = { "cim-data", };
+
+static const struct function_desc jz4780_functions[] = {
+       { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
+       { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
+       { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
+       { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
+       { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
+       { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
+       { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
+       { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
+       { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
+       { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+       { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
+       { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
+       { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
+       { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
+       { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
+       { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
+       { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
+       { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
+       { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
+       { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
+       { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
+       { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
+       { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
+       { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
+       { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
+       { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
+       { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
+       { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
+       { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
+       { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+};
+
+static const struct ingenic_chip_info jz4780_chip_info = {
+       .num_chips = 6,
+       .groups = jz4780_groups,
+       .num_groups = ARRAY_SIZE(jz4780_groups),
+       .functions = jz4780_functions,
+       .num_functions = ARRAY_SIZE(jz4780_functions),
+       .pull_ups = jz4770_pull_ups,
+       .pull_downs = jz4770_pull_downs,
+};
+
+static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 {
        unsigned int val;
 
@@ -551,7 +754,7 @@ static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
        return (u32) val;
 }
 
-static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
+static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
                u8 reg, u8 offset, bool set)
 {
        if (set)
@@ -565,7 +768,7 @@ static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
                                          u8 offset)
 {
-       unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
+       unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
 
        return !!(val & BIT(offset));
 }
@@ -574,9 +777,9 @@ static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
                                   u8 offset, int value)
 {
        if (jzgc->jzpc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
+               ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
        else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
+               ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
 }
 
 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
@@ -594,21 +797,21 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
 
        switch (type) {
        case IRQ_TYPE_EDGE_RISING:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+               ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+               ingenic_gpio_set_bit(jzgc, reg1, offset, true);
                break;
        case IRQ_TYPE_EDGE_FALLING:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+               ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+               ingenic_gpio_set_bit(jzgc, reg1, offset, true);
                break;
        case IRQ_TYPE_LEVEL_HIGH:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+               ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+               ingenic_gpio_set_bit(jzgc, reg1, offset, false);
                break;
        case IRQ_TYPE_LEVEL_LOW:
        default:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+               ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+               ingenic_gpio_set_bit(jzgc, reg1, offset, false);
                break;
        }
 }
@@ -618,7 +821,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd)
        struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
        struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-       gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
+       ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
 }
 
 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
@@ -626,7 +829,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
        struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
        struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-       gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
+       ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
 }
 
 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
@@ -636,9 +839,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
        int irq = irqd->hwirq;
 
        if (jzgc->jzpc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
+               ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
        else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
+               ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
 
        ingenic_gpio_irq_unmask(irqd);
 }
@@ -652,9 +855,9 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
        ingenic_gpio_irq_mask(irqd);
 
        if (jzgc->jzpc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
+               ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
        else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
+               ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
 }
 
 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
@@ -677,9 +880,9 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
        }
 
        if (jzgc->jzpc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
+               ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
        else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
+               ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
 }
 
 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -734,9 +937,9 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
        chained_irq_enter(irq_chip, desc);
 
        if (jzgc->jzpc->version >= ID_JZ4770)
-               flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
+               flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
        else
-               flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
+               flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
 
        for_each_set_bit(i, &flag, 32)
                generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
@@ -1185,7 +1388,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
        else
                jzpc->version = (enum jz_version)id->driver_data;
 
-       if (jzpc->version >= ID_JZ4770)
+       if (jzpc->version >= ID_JZ4780)
+               chip_info = &jz4780_chip_info;
+       else if (jzpc->version >= ID_JZ4770)
                chip_info = &jz4770_chip_info;
        else if (jzpc->version >= ID_JZ4725B)
                chip_info = &jz4725b_chip_info;
index 98905d4a79ca93b52935dc438b4797bb4fc86f78..5d7a8514def91927466bf5b6ff63ccbe2a16692d 100644 (file)
@@ -68,6 +68,7 @@ struct mcp23s08 {
        struct mutex            lock;
 
        struct gpio_chip        chip;
+       struct irq_chip         irq_chip;
 
        struct regmap           *regmap;
        struct device           *dev;
@@ -607,15 +608,6 @@ static void mcp23s08_irq_bus_unlock(struct irq_data *data)
        mutex_unlock(&mcp->lock);
 }
 
-static struct irq_chip mcp23s08_irq_chip = {
-       .name = "gpio-mcp23xxx",
-       .irq_mask = mcp23s08_irq_mask,
-       .irq_unmask = mcp23s08_irq_unmask,
-       .irq_set_type = mcp23s08_irq_set_type,
-       .irq_bus_lock = mcp23s08_irq_bus_lock,
-       .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
-};
-
 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
 {
        struct gpio_chip *chip = &mcp->chip;
@@ -645,7 +637,7 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp)
        int err;
 
        err =  gpiochip_irqchip_add_nested(chip,
-                                          &mcp23s08_irq_chip,
+                                          &mcp->irq_chip,
                                           0,
                                           handle_simple_irq,
                                           IRQ_TYPE_NONE);
@@ -656,7 +648,7 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp)
        }
 
        gpiochip_set_nested_irqchip(chip,
-                                   &mcp23s08_irq_chip,
+                                   &mcp->irq_chip,
                                    mcp->irq);
 
        return 0;
@@ -1047,6 +1039,13 @@ static int mcp230xx_probe(struct i2c_client *client,
                return -ENOMEM;
 
        mcp->irq = client->irq;
+       mcp->irq_chip.name = dev_name(&client->dev);
+       mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
+       mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
+       mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
+       mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
+       mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
+
        status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
                                    id->driver_data, pdata->base, 0);
        if (status)
@@ -1144,8 +1143,7 @@ static int mcp23s08_probe(struct spi_device *spi)
                return -ENODEV;
 
        data = devm_kzalloc(&spi->dev,
-                           sizeof(*data) + chips * sizeof(struct mcp23s08),
-                           GFP_KERNEL);
+                           struct_size(data, chip, chips), GFP_KERNEL);
        if (!data)
                return -ENOMEM;
 
@@ -1157,6 +1155,13 @@ static int mcp23s08_probe(struct spi_device *spi)
                chips--;
                data->mcp[addr] = &data->chip[chips];
                data->mcp[addr]->irq = spi->irq;
+               data->mcp[addr]->irq_chip.name = dev_name(&spi->dev);
+               data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask;
+               data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask;
+               data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type;
+               data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
+               data->mcp[addr]->irq_chip.irq_bus_sync_unlock =
+                       mcp23s08_irq_bus_unlock;
                status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
                                            0x40 | (addr << 1), type,
                                            pdata->base, addr);
index 4ffd56ff809eb143437830de1aa829d4ab431708..1c6ba978c69f6f96375d4a0201da4df3ffa61dda 100644 (file)
@@ -95,31 +95,6 @@ enum {
                .intr_detection_width = -1,             \
        }
 
-#define UFS_RESET(pg_name, offset)                             \
-       {                                               \
-               .name = #pg_name,                       \
-               .pins = pg_name##_pins,                 \
-               .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),      \
-               .ctl_reg = offset,                      \
-               .io_reg = offset + 0x4,                 \
-               .intr_cfg_reg = 0,                      \
-               .intr_status_reg = 0,                   \
-               .intr_target_reg = 0,                   \
-               .tile = NORTH,                          \
-               .mux_bit = -1,                          \
-               .pull_bit = 3,                          \
-               .drv_bit = 0,                           \
-               .oe_bit = -1,                           \
-               .in_bit = -1,                           \
-               .out_bit = 0,                           \
-               .intr_enable_bit = -1,                  \
-               .intr_status_bit = -1,                  \
-               .intr_target_bit = -1,                  \
-               .intr_raw_status_bit = -1,              \
-               .intr_polarity_bit = -1,                \
-               .intr_detection_bit = -1,               \
-               .intr_detection_width = -1,             \
-       }
 static const struct pinctrl_pin_desc qcs404_pins[] = {
        PINCTRL_PIN(0, "GPIO_0"),
        PINCTRL_PIN(1, "GPIO_1"),
index cb512c7a52513165a390da33b4e9958e16d6f463..76e57ae2f6e84b8b7cdf5b71965aab0be258d005 100644 (file)
@@ -675,11 +675,11 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
                else
                        seq_printf(s, " %-4s",
                                        pad->output_enabled ? "out" : "in");
+               seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
                seq_printf(s, " %-7s", pmic_gpio_functions[function]);
                seq_printf(s, " vin-%d", pad->power_source);
                seq_printf(s, " %-27s", biases[pad->pullup]);
                seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
-               seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
                seq_printf(s, " %-7s", strengths[pad->strength]);
                seq_printf(s, " atest-%d", pad->atest);
                seq_printf(s, " dtest-%d", pad->dtest_buffer);
index f49ea3d92aa1e3eab716721cf2f5a12ea45a1ccd..ebc27b06718c0b64e24d2d2008f06ab0947c6a33 100644 (file)
@@ -325,13 +325,6 @@ err_domains:
        return ret;
 }
 
-static u32 exynos_eint_wake_mask = 0xffffffff;
-
-u32 exynos_get_eint_wake_mask(void)
-{
-       return exynos_eint_wake_mask;
-}
-
 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 {
        struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -342,10 +335,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
        pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
 
        if (!on)
-               exynos_eint_wake_mask |= bit;
+               our_chip->eint_wake_mask_value |= bit;
        else
-               exynos_eint_wake_mask &= ~bit;
-       our_chip->eint_wake_mask_value = exynos_eint_wake_mask;
+               our_chip->eint_wake_mask_value &= ~bit;
 
        return 0;
 }
index dc271c3243df5ebfbbe36b3823ccc0b686727b1f..310c6f3ee7ccda30003987b96f44fd7c01491cb9 100644 (file)
@@ -1260,6 +1260,14 @@ static const char * const dtv_groups[] = {
        "dtv_b",
 };
 
+static const char * const err_rst_reqb_groups[] = {
+       "err_rst_reqb",
+};
+
+static const char * const ext_clki_groups[] = {
+       "ext_clki",
+};
+
 static const char * const iic0_groups[] = {
        "iic0",
 };
@@ -1282,6 +1290,10 @@ static const char * const lcd_groups[] = {
        "yuv3",
 };
 
+static const char * const lowpwr_groups[] = {
+       "lowpwr",
+};
+
 static const char * const ntsc_groups[] = {
        "ntsc_clk",
        "ntsc_data",
@@ -1295,6 +1307,10 @@ static const char * const pwm1_groups[] = {
        "pwm1",
 };
 
+static const char * const ref_clko_groups[] = {
+       "ref_clko",
+};
+
 static const char * const sd_groups[] = {
        "sd_cki",
 };
@@ -1388,13 +1404,17 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(cam),
        SH_PFC_FUNCTION(cf),
        SH_PFC_FUNCTION(dtv),
+       SH_PFC_FUNCTION(err_rst_reqb),
+       SH_PFC_FUNCTION(ext_clki),
        SH_PFC_FUNCTION(iic0),
        SH_PFC_FUNCTION(iic1),
        SH_PFC_FUNCTION(jtag),
        SH_PFC_FUNCTION(lcd),
+       SH_PFC_FUNCTION(lowpwr),
        SH_PFC_FUNCTION(ntsc),
        SH_PFC_FUNCTION(pwm0),
        SH_PFC_FUNCTION(pwm1),
+       SH_PFC_FUNCTION(ref_clko),
        SH_PFC_FUNCTION(sd),
        SH_PFC_FUNCTION(sdi0),
        SH_PFC_FUNCTION(sdi1),
index 6bcdb4b5e69e7ff1cfc9ab368f825ef4f796f0e3..068b5e6334d148d4255d3711c3f8d8c22f01af67 100644 (file)
@@ -1264,8 +1264,8 @@ static const struct sh_pfc_pin pinmux_pins[] = {
 
        /* Pins not associated with a GPIO port */
        SH_PFC_PIN_NAMED(3, 20, C20),
-       SH_PFC_PIN_NAMED(20, 1, T1),
-       SH_PFC_PIN_NAMED(25, 2, Y2),
+       SH_PFC_PIN_NAMED(1, 20, A20),
+       SH_PFC_PIN_NAMED(2, 25, B25),
 };
 
 /* - macro */
@@ -1400,7 +1400,7 @@ HSPI_PFC_DAT(hspi1_a,     HSPI_CLK1_A,            HSPI_CS1_A,
                        HSPI_RX1_A,             HSPI_TX1_A);
 
 HSPI_PFC_PIN(hspi1_b,  RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
-                       PIN_NUMBER(20, 1),      PIN_NUMBER(25, 2));
+                       PIN_NUMBER(1, 20),      PIN_NUMBER(2, 25));
 HSPI_PFC_DAT(hspi1_b,  HSPI_CLK1_B,            HSPI_CS1_B,
                        HSPI_RX1_B,             HSPI_TX1_B);
 
index ab7a35392cd816c58d2788ec2b72778c7999f42f..a84229cb8cd4c8a70d52b746ce468082899736fc 100644 (file)
@@ -10,7 +10,9 @@
 
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/sys_soc.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 /*
@@ -5691,7 +5693,22 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
        return 31 - (pin & 0x1f);
 }
 
+static const struct soc_device_attribute r8a7790_tdsel[] = {
+       { .soc_id = "r8a7790", .revision = "ES1.0" },
+       { /* sentinel */ }
+};
+
+static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
+{
+       /* Initialize TDSEL on old revisions */
+       if (soc_device_match(r8a7790_tdsel))
+               sh_pfc_write(pfc, 0xe6060088, 0x00155554);
+
+       return 0;
+}
+
 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
+       .init = r8a7790_pinmux_soc_init,
        .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
 };
 
index 2859231aaffc4546cb176cd51611bf7e4159aaa2..d8b13d4e9bbff7cb935dba68d727c4917d650e61 100644 (file)
@@ -4317,7 +4317,7 @@ static const unsigned int vin1_clk_pins[] = {
 static const unsigned int vin1_clk_mux[] = {
        VI1_CLK_MARK,
 };
-static const union vin_data vin1_b_data_pins = {
+static const union vin_data vin1_data_b_pins = {
        .data24 = {
                /* B */
                RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
@@ -4336,7 +4336,7 @@ static const union vin_data vin1_b_data_pins = {
                RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
        },
 };
-static const union vin_data vin1_b_data_mux = {
+static const union vin_data vin1_data_b_mux = {
        .data24 = {
                /* B */
                VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
@@ -4355,7 +4355,7 @@ static const union vin_data vin1_b_data_mux = {
                VI1_R6_B_MARK, VI1_R7_B_MARK,
        },
 };
-static const unsigned int vin1_b_data18_pins[] = {
+static const unsigned int vin1_data18_b_pins[] = {
        /* B */
        RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
@@ -4369,7 +4369,7 @@ static const unsigned int vin1_b_data18_pins[] = {
        RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
        RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
 };
-static const unsigned int vin1_b_data18_mux[] = {
+static const unsigned int vin1_data18_b_mux[] = {
        /* B */
        VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
        VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
@@ -4383,30 +4383,30 @@ static const unsigned int vin1_b_data18_mux[] = {
        VI1_R4_B_MARK, VI1_R5_B_MARK,
        VI1_R6_B_MARK, VI1_R7_B_MARK,
 };
-static const unsigned int vin1_b_sync_pins[] = {
+static const unsigned int vin1_sync_b_pins[] = {
        RCAR_GP_PIN(3, 17), /* HSYNC */
        RCAR_GP_PIN(3, 18), /* VSYNC */
 };
-static const unsigned int vin1_b_sync_mux[] = {
+static const unsigned int vin1_sync_b_mux[] = {
        VI1_HSYNC_N_B_MARK,
        VI1_VSYNC_N_B_MARK,
 };
-static const unsigned int vin1_b_field_pins[] = {
+static const unsigned int vin1_field_b_pins[] = {
        RCAR_GP_PIN(3, 20),
 };
-static const unsigned int vin1_b_field_mux[] = {
+static const unsigned int vin1_field_b_mux[] = {
        VI1_FIELD_B_MARK,
 };
-static const unsigned int vin1_b_clkenb_pins[] = {
+static const unsigned int vin1_clkenb_b_pins[] = {
        RCAR_GP_PIN(3, 19),
 };
-static const unsigned int vin1_b_clkenb_mux[] = {
+static const unsigned int vin1_clkenb_b_mux[] = {
        VI1_CLKENB_B_MARK,
 };
-static const unsigned int vin1_b_clk_pins[] = {
+static const unsigned int vin1_clk_b_pins[] = {
        RCAR_GP_PIN(3, 16),
 };
-static const unsigned int vin1_b_clk_mux[] = {
+static const unsigned int vin1_clk_b_mux[] = {
        VI1_CLK_B_MARK,
 };
 /* - VIN2 ----------------------------------------------------------------- */
@@ -4784,17 +4784,17 @@ static const struct {
                SH_PFC_PIN_GROUP(vin1_field),
                SH_PFC_PIN_GROUP(vin1_clkenb),
                SH_PFC_PIN_GROUP(vin1_clk),
-               VIN_DATA_PIN_GROUP(vin1_b_data, 24),
-               VIN_DATA_PIN_GROUP(vin1_b_data, 20),
-               SH_PFC_PIN_GROUP(vin1_b_data18),
-               VIN_DATA_PIN_GROUP(vin1_b_data, 16),
-               VIN_DATA_PIN_GROUP(vin1_b_data, 12),
-               VIN_DATA_PIN_GROUP(vin1_b_data, 10),
-               VIN_DATA_PIN_GROUP(vin1_b_data, 8),
-               SH_PFC_PIN_GROUP(vin1_b_sync),
-               SH_PFC_PIN_GROUP(vin1_b_field),
-               SH_PFC_PIN_GROUP(vin1_b_clkenb),
-               SH_PFC_PIN_GROUP(vin1_b_clk),
+               VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+               VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+               SH_PFC_PIN_GROUP(vin1_data18_b),
+               VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
+               VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
+               VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
+               VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
+               SH_PFC_PIN_GROUP(vin1_sync_b),
+               SH_PFC_PIN_GROUP(vin1_field_b),
+               SH_PFC_PIN_GROUP(vin1_clkenb_b),
+               SH_PFC_PIN_GROUP(vin1_clk_b),
                SH_PFC_PIN_GROUP(vin2_data8),
                SH_PFC_PIN_GROUP(vin2_sync),
                SH_PFC_PIN_GROUP(vin2_field),
@@ -5236,7 +5236,7 @@ static const char * const scifb2_groups[] = {
        "scifb2_data_b",
        "scifb2_clk_b",
        "scifb2_ctrl_b",
-       "scifb0_data_c",
+       "scifb2_data_c",
        "scifb2_clk_c",
        "scifb2_data_d",
 };
@@ -5335,17 +5335,17 @@ static const char * const vin1_groups[] = {
        "vin1_field",
        "vin1_clkenb",
        "vin1_clk",
-       "vin1_b_data24",
-       "vin1_b_data20",
-       "vin1_b_data18",
-       "vin1_b_data16",
-       "vin1_b_data12",
-       "vin1_b_data10",
-       "vin1_b_data8",
-       "vin1_b_sync",
-       "vin1_b_field",
-       "vin1_b_clkenb",
-       "vin1_b_clk",
+       "vin1_data24_b",
+       "vin1_data20_b",
+       "vin1_data18_b",
+       "vin1_data16_b",
+       "vin1_data12_b",
+       "vin1_data10_b",
+       "vin1_data8_b",
+       "vin1_sync_b",
+       "vin1_field_b",
+       "vin1_clkenb_b",
+       "vin1_clk_b",
 };
 
 static const char * const vin2_groups[] = {
index a623459b234e048e24dc4a9cac590347cf6f2970..d36da5652de6c6d371b7f41907c90de9d26f3566 100644 (file)
@@ -1913,6 +1913,7 @@ static const char * const vin1_groups[] = {
        "vin1_data8",
        "vin1_data24_b",
        "vin1_data20_b",
+       "vin1_data18_b",
        "vin1_data16_b",
        "vin1_sync",
        "vin1_field",
index fcf1339c40584385eed6747dcbced42b59271387..958a5f714c93d9678cfe7171557425adaa0fe546 100644 (file)
@@ -8,6 +8,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/sys_soc.h>
 
 #include "core.h"
 #include "sh_pfc.h"
@@ -5560,7 +5561,22 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
        return -EINVAL;
 }
 
+static const struct soc_device_attribute r8a7794_tdsel[] = {
+       { .soc_id = "r8a7794", .revision = "ES1.0" },
+       { /* sentinel */ }
+};
+
+static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
+{
+       /* Initialize TDSEL on old revisions */
+       if (soc_device_match(r8a7794_tdsel))
+               sh_pfc_write(pfc, 0xe6060068, 0x55555500);
+
+       return 0;
+}
+
 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
+       .init = r8a7794_pinmux_soc_init,
        .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
 };
 
index 01105bb8359882fc3b57f52112dadeefa7eb21ff..db9add1405c54ff72f66c1c25b954f101caa7cd6 100644 (file)
@@ -4098,67 +4098,29 @@ static const unsigned int vin4_clk_mux[] = {
 };
 
 /* - VIN5 ------------------------------------------------------------------- */
-static const unsigned int vin5_data8_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin5_data8_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-};
-static const unsigned int vin5_data10_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int vin5_data10_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-       VI5_DATA8_MARK,  VI5_DATA9_MARK,
-};
-static const unsigned int vin5_data12_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-};
-static const unsigned int vin5_data12_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-       VI5_DATA8_MARK,  VI5_DATA9_MARK,
-       VI5_DATA10_MARK, VI5_DATA11_MARK,
-};
-static const unsigned int vin5_data16_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-       RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+static const union vin_data16 vin5_data_pins = {
+       .data16 = {
+               RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+               RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+               RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+               RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+               RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+               RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+               RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+               RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+       },
 };
-static const unsigned int vin5_data16_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-       VI5_DATA8_MARK,  VI5_DATA9_MARK,
-       VI5_DATA10_MARK, VI5_DATA11_MARK,
-       VI5_DATA12_MARK, VI5_DATA13_MARK,
-       VI5_DATA14_MARK, VI5_DATA15_MARK,
+static const union vin_data16 vin5_data_mux = {
+       .data16 = {
+               VI5_DATA0_MARK, VI5_DATA1_MARK,
+               VI5_DATA2_MARK, VI5_DATA3_MARK,
+               VI5_DATA4_MARK, VI5_DATA5_MARK,
+               VI5_DATA6_MARK, VI5_DATA7_MARK,
+               VI5_DATA8_MARK,  VI5_DATA9_MARK,
+               VI5_DATA10_MARK, VI5_DATA11_MARK,
+               VI5_DATA12_MARK, VI5_DATA13_MARK,
+               VI5_DATA14_MARK, VI5_DATA15_MARK,
+       },
 };
 static const unsigned int vin5_sync_pins[] = {
        /* HSYNC#, VSYNC# */
@@ -4530,10 +4492,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(vin4_field),
        SH_PFC_PIN_GROUP(vin4_clkenb),
        SH_PFC_PIN_GROUP(vin4_clk),
-       SH_PFC_PIN_GROUP(vin5_data8),
-       SH_PFC_PIN_GROUP(vin5_data10),
-       SH_PFC_PIN_GROUP(vin5_data12),
-       SH_PFC_PIN_GROUP(vin5_data16),
+       VIN_DATA_PIN_GROUP(vin5_data, 8),
+       VIN_DATA_PIN_GROUP(vin5_data, 10),
+       VIN_DATA_PIN_GROUP(vin5_data, 12),
+       VIN_DATA_PIN_GROUP(vin5_data, 16),
        SH_PFC_PIN_GROUP(vin5_sync),
        SH_PFC_PIN_GROUP(vin5_field),
        SH_PFC_PIN_GROUP(vin5_clkenb),
index 4b98ad8d93d9e5459fd1f9f44cf8d32ba0cb2341..72348a4f2ece13b6bec5149a8f82fe4c79e61b4f 100644 (file)
@@ -4070,67 +4070,29 @@ static const unsigned int vin4_clk_mux[] = {
 };
 
 /* - VIN5 ------------------------------------------------------------------- */
-static const unsigned int vin5_data8_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int vin5_data8_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-};
-static const unsigned int vin5_data10_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-};
-static const unsigned int vin5_data10_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-       VI5_DATA8_MARK,  VI5_DATA9_MARK,
-};
-static const unsigned int vin5_data12_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-};
-static const unsigned int vin5_data12_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-       VI5_DATA8_MARK,  VI5_DATA9_MARK,
-       VI5_DATA10_MARK, VI5_DATA11_MARK,
-};
-static const unsigned int vin5_data16_pins[] = {
-       RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-       RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-       RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-       RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-       RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
-       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-       RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+static const union vin_data16 vin5_data_pins = {
+       .data16 = {
+               RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+               RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+               RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+               RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+               RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+               RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+               RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+               RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+       },
 };
-static const unsigned int vin5_data16_mux[] = {
-       VI5_DATA0_MARK, VI5_DATA1_MARK,
-       VI5_DATA2_MARK, VI5_DATA3_MARK,
-       VI5_DATA4_MARK, VI5_DATA5_MARK,
-       VI5_DATA6_MARK, VI5_DATA7_MARK,
-       VI5_DATA8_MARK,  VI5_DATA9_MARK,
-       VI5_DATA10_MARK, VI5_DATA11_MARK,
-       VI5_DATA12_MARK, VI5_DATA13_MARK,
-       VI5_DATA14_MARK, VI5_DATA15_MARK,
+static const union vin_data16 vin5_data_mux = {
+       .data16 = {
+               VI5_DATA0_MARK, VI5_DATA1_MARK,
+               VI5_DATA2_MARK, VI5_DATA3_MARK,
+               VI5_DATA4_MARK, VI5_DATA5_MARK,
+               VI5_DATA6_MARK, VI5_DATA7_MARK,
+               VI5_DATA8_MARK,  VI5_DATA9_MARK,
+               VI5_DATA10_MARK, VI5_DATA11_MARK,
+               VI5_DATA12_MARK, VI5_DATA13_MARK,
+               VI5_DATA14_MARK, VI5_DATA15_MARK,
+       },
 };
 static const unsigned int vin5_sync_pins[] = {
        /* HSYNC#, VSYNC# */
@@ -4468,10 +4430,10 @@ static const struct {
                SH_PFC_PIN_GROUP(vin4_field),
                SH_PFC_PIN_GROUP(vin4_clkenb),
                SH_PFC_PIN_GROUP(vin4_clk),
-               SH_PFC_PIN_GROUP(vin5_data8),
-               SH_PFC_PIN_GROUP(vin5_data10),
-               SH_PFC_PIN_GROUP(vin5_data12),
-               SH_PFC_PIN_GROUP(vin5_data16),
+               VIN_DATA_PIN_GROUP(vin5_data, 8),
+               VIN_DATA_PIN_GROUP(vin5_data, 10),
+               VIN_DATA_PIN_GROUP(vin5_data, 12),
+               VIN_DATA_PIN_GROUP(vin5_data, 16),
                SH_PFC_PIN_GROUP(vin5_sync),
                SH_PFC_PIN_GROUP(vin5_field),
                SH_PFC_PIN_GROUP(vin5_clkenb),
index a7c4882de09e3bd69bba7da47d4b173415765592..14c4b671cddf46a1f929a709c9795f6af5d0a439 100644 (file)
@@ -554,7 +554,7 @@ MOD_SEL0_4_3                MOD_SEL1_4 \
        FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
        FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
        FM(PRESETOUT) \
-       FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
+       FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
        FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 
 enum {
@@ -1566,7 +1566,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
-       SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
+       SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
@@ -1850,6 +1850,280 @@ static const unsigned int canfd1_data_mux[] = {
        CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
 
+/* - DRIF0 --------------------------------------------------------------- */
+static const unsigned int drif0_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+
+static const unsigned int drif0_ctrl_a_mux[] = {
+       RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
+};
+
+static const unsigned int drif0_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(6, 10),
+};
+
+static const unsigned int drif0_data0_a_mux[] = {
+       RIF0_D0_A_MARK,
+};
+
+static const unsigned int drif0_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(6, 7),
+};
+
+static const unsigned int drif0_data1_a_mux[] = {
+       RIF0_D1_A_MARK,
+};
+
+static const unsigned int drif0_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
+};
+
+static const unsigned int drif0_ctrl_b_mux[] = {
+       RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
+};
+
+static const unsigned int drif0_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(5, 1),
+};
+
+static const unsigned int drif0_data0_b_mux[] = {
+       RIF0_D0_B_MARK,
+};
+
+static const unsigned int drif0_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int drif0_data1_b_mux[] = {
+       RIF0_D1_B_MARK,
+};
+
+static const unsigned int drif0_ctrl_c_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
+};
+
+static const unsigned int drif0_ctrl_c_mux[] = {
+       RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
+};
+
+static const unsigned int drif0_data0_c_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(5, 13),
+};
+
+static const unsigned int drif0_data0_c_mux[] = {
+       RIF0_D0_C_MARK,
+};
+
+static const unsigned int drif0_data1_c_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(5, 14),
+};
+
+static const unsigned int drif0_data1_c_mux[] = {
+       RIF0_D1_C_MARK,
+};
+
+/* - DRIF1 --------------------------------------------------------------- */
+static const unsigned int drif1_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
+};
+
+static const unsigned int drif1_ctrl_a_mux[] = {
+       RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
+};
+
+static const unsigned int drif1_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(6, 19),
+};
+
+static const unsigned int drif1_data0_a_mux[] = {
+       RIF1_D0_A_MARK,
+};
+
+static const unsigned int drif1_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(6, 20),
+};
+
+static const unsigned int drif1_data1_a_mux[] = {
+       RIF1_D1_A_MARK,
+};
+
+static const unsigned int drif1_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
+};
+
+static const unsigned int drif1_ctrl_b_mux[] = {
+       RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
+};
+
+static const unsigned int drif1_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int drif1_data0_b_mux[] = {
+       RIF1_D0_B_MARK,
+};
+
+static const unsigned int drif1_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(5, 8),
+};
+
+static const unsigned int drif1_data1_b_mux[] = {
+       RIF1_D1_B_MARK,
+};
+
+static const unsigned int drif1_ctrl_c_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int drif1_ctrl_c_mux[] = {
+       RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
+};
+
+static const unsigned int drif1_data0_c_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int drif1_data0_c_mux[] = {
+       RIF1_D0_C_MARK,
+};
+
+static const unsigned int drif1_data1_c_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(5, 10),
+};
+
+static const unsigned int drif1_data1_c_mux[] = {
+       RIF1_D1_C_MARK,
+};
+
+/* - DRIF2 --------------------------------------------------------------- */
+static const unsigned int drif2_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+
+static const unsigned int drif2_ctrl_a_mux[] = {
+       RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
+};
+
+static const unsigned int drif2_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(6, 7),
+};
+
+static const unsigned int drif2_data0_a_mux[] = {
+       RIF2_D0_A_MARK,
+};
+
+static const unsigned int drif2_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(6, 10),
+};
+
+static const unsigned int drif2_data1_a_mux[] = {
+       RIF2_D1_A_MARK,
+};
+
+static const unsigned int drif2_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+
+static const unsigned int drif2_ctrl_b_mux[] = {
+       RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
+};
+
+static const unsigned int drif2_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(6, 30),
+};
+
+static const unsigned int drif2_data0_b_mux[] = {
+       RIF2_D0_B_MARK,
+};
+
+static const unsigned int drif2_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(6, 31),
+};
+
+static const unsigned int drif2_data1_b_mux[] = {
+       RIF2_D1_B_MARK,
+};
+
+/* - DRIF3 --------------------------------------------------------------- */
+static const unsigned int drif3_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
+};
+
+static const unsigned int drif3_ctrl_a_mux[] = {
+       RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
+};
+
+static const unsigned int drif3_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(6, 19),
+};
+
+static const unsigned int drif3_data0_a_mux[] = {
+       RIF3_D0_A_MARK,
+};
+
+static const unsigned int drif3_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(6, 20),
+};
+
+static const unsigned int drif3_data1_a_mux[] = {
+       RIF3_D1_A_MARK,
+};
+
+static const unsigned int drif3_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+
+static const unsigned int drif3_ctrl_b_mux[] = {
+       RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
+};
+
+static const unsigned int drif3_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(6, 28),
+};
+
+static const unsigned int drif3_data0_b_mux[] = {
+       RIF3_D0_B_MARK,
+};
+
+static const unsigned int drif3_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(6, 29),
+};
+
+static const unsigned int drif3_data1_b_mux[] = {
+       RIF3_D1_B_MARK,
+};
+
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
        /* R[7:2], G[7:2], B[7:2] */
@@ -3760,6 +4034,42 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
        SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(6, 23),
+};
+
+static const unsigned int tmu_tclk1_a_mux[] = {
+       TCLK1_A_MARK,
+};
+
+static const unsigned int tmu_tclk1_b_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(5, 19),
+};
+
+static const unsigned int tmu_tclk1_b_mux[] = {
+       TCLK1_B_MARK,
+};
+
+static const unsigned int tmu_tclk2_a_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(6, 19),
+};
+
+static const unsigned int tmu_tclk2_a_mux[] = {
+       TCLK2_A_MARK,
+};
+
+static const unsigned int tmu_tclk2_b_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(6, 28),
+};
+
+static const unsigned int tmu_tclk2_b_mux[] = {
+       TCLK2_B_MARK,
+};
 
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
@@ -4037,6 +4347,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(canfd0_data_a),
        SH_PFC_PIN_GROUP(canfd0_data_b),
        SH_PFC_PIN_GROUP(canfd1_data),
+       SH_PFC_PIN_GROUP(drif0_ctrl_a),
+       SH_PFC_PIN_GROUP(drif0_data0_a),
+       SH_PFC_PIN_GROUP(drif0_data1_a),
+       SH_PFC_PIN_GROUP(drif0_ctrl_b),
+       SH_PFC_PIN_GROUP(drif0_data0_b),
+       SH_PFC_PIN_GROUP(drif0_data1_b),
+       SH_PFC_PIN_GROUP(drif0_ctrl_c),
+       SH_PFC_PIN_GROUP(drif0_data0_c),
+       SH_PFC_PIN_GROUP(drif0_data1_c),
+       SH_PFC_PIN_GROUP(drif1_ctrl_a),
+       SH_PFC_PIN_GROUP(drif1_data0_a),
+       SH_PFC_PIN_GROUP(drif1_data1_a),
+       SH_PFC_PIN_GROUP(drif1_ctrl_b),
+       SH_PFC_PIN_GROUP(drif1_data0_b),
+       SH_PFC_PIN_GROUP(drif1_data1_b),
+       SH_PFC_PIN_GROUP(drif1_ctrl_c),
+       SH_PFC_PIN_GROUP(drif1_data0_c),
+       SH_PFC_PIN_GROUP(drif1_data1_c),
+       SH_PFC_PIN_GROUP(drif2_ctrl_a),
+       SH_PFC_PIN_GROUP(drif2_data0_a),
+       SH_PFC_PIN_GROUP(drif2_data1_a),
+       SH_PFC_PIN_GROUP(drif2_ctrl_b),
+       SH_PFC_PIN_GROUP(drif2_data0_b),
+       SH_PFC_PIN_GROUP(drif2_data1_b),
+       SH_PFC_PIN_GROUP(drif3_ctrl_a),
+       SH_PFC_PIN_GROUP(drif3_data0_a),
+       SH_PFC_PIN_GROUP(drif3_data1_a),
+       SH_PFC_PIN_GROUP(drif3_ctrl_b),
+       SH_PFC_PIN_GROUP(drif3_data0_b),
+       SH_PFC_PIN_GROUP(drif3_data1_b),
        SH_PFC_PIN_GROUP(du_rgb666),
        SH_PFC_PIN_GROUP(du_rgb888),
        SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -4280,6 +4620,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(ssi9_data_b),
        SH_PFC_PIN_GROUP(ssi9_ctrl_a),
        SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+       SH_PFC_PIN_GROUP(tmu_tclk1_a),
+       SH_PFC_PIN_GROUP(tmu_tclk1_b),
+       SH_PFC_PIN_GROUP(tmu_tclk2_a),
+       SH_PFC_PIN_GROUP(tmu_tclk2_b),
        SH_PFC_PIN_GROUP(usb0),
        SH_PFC_PIN_GROUP(usb1),
        SH_PFC_PIN_GROUP(usb30),
@@ -4367,6 +4711,48 @@ static const char * const canfd1_groups[] = {
        "canfd1_data",
 };
 
+static const char * const drif0_groups[] = {
+       "drif0_ctrl_a",
+       "drif0_data0_a",
+       "drif0_data1_a",
+       "drif0_ctrl_b",
+       "drif0_data0_b",
+       "drif0_data1_b",
+       "drif0_ctrl_c",
+       "drif0_data0_c",
+       "drif0_data1_c",
+};
+
+static const char * const drif1_groups[] = {
+       "drif1_ctrl_a",
+       "drif1_data0_a",
+       "drif1_data1_a",
+       "drif1_ctrl_b",
+       "drif1_data0_b",
+       "drif1_data1_b",
+       "drif1_ctrl_c",
+       "drif1_data0_c",
+       "drif1_data1_c",
+};
+
+static const char * const drif2_groups[] = {
+       "drif2_ctrl_a",
+       "drif2_data0_a",
+       "drif2_data1_a",
+       "drif2_ctrl_b",
+       "drif2_data0_b",
+       "drif2_data1_b",
+};
+
+static const char * const drif3_groups[] = {
+       "drif3_ctrl_a",
+       "drif3_data0_a",
+       "drif3_data1_a",
+       "drif3_ctrl_b",
+       "drif3_data0_b",
+       "drif3_data1_b",
+};
+
 static const char * const du_groups[] = {
        "du_rgb666",
        "du_rgb888",
@@ -4711,6 +5097,13 @@ static const char * const ssi_groups[] = {
        "ssi9_ctrl_b",
 };
 
+static const char * const tmu_groups[] = {
+       "tmu_tclk1_a",
+       "tmu_tclk1_b",
+       "tmu_tclk2_a",
+       "tmu_tclk2_b",
+};
+
 static const char * const usb0_groups[] = {
        "usb0",
 };
@@ -4763,6 +5156,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(can_clk),
        SH_PFC_FUNCTION(canfd0),
        SH_PFC_FUNCTION(canfd1),
+       SH_PFC_FUNCTION(drif0),
+       SH_PFC_FUNCTION(drif1),
+       SH_PFC_FUNCTION(drif2),
+       SH_PFC_FUNCTION(drif3),
        SH_PFC_FUNCTION(du),
        SH_PFC_FUNCTION(hscif0),
        SH_PFC_FUNCTION(hscif1),
@@ -4797,6 +5194,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(sdhi2),
        SH_PFC_FUNCTION(sdhi3),
        SH_PFC_FUNCTION(ssi),
+       SH_PFC_FUNCTION(tmu),
        SH_PFC_FUNCTION(usb0),
        SH_PFC_FUNCTION(usb1),
        SH_PFC_FUNCTION(usb30),
@@ -5740,7 +6138,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
                [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
        } },
        { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-               [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
+               [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
                [ 1] = PIN_NONE,
                [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
                [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
index 4a7ab84b366be9867590fa1b2efaa04e3ce28f4f..c5e67ba29f7c88cdc0024e732c7f9458146dba38 100644 (file)
@@ -1578,47 +1578,25 @@ static const unsigned int tmu_tclk2_b_mux[] = {
 };
 
 /* - VIN0 ------------------------------------------------------------------- */
-static const unsigned int vin0_data8_pins[] = {
-       RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-       RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-       RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-};
-static const unsigned int vin0_data8_mux[] = {
-       VI0_DATA0_MARK, VI0_DATA1_MARK,
-       VI0_DATA2_MARK, VI0_DATA3_MARK,
-       VI0_DATA4_MARK, VI0_DATA5_MARK,
-       VI0_DATA6_MARK, VI0_DATA7_MARK,
+static const union vin_data12 vin0_data_pins = {
+       .data12 = {
+               RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+               RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+               RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+               RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+               RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+               RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+       },
 };
-static const unsigned int vin0_data10_pins[] = {
-       RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-       RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-       RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-       RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-};
-static const unsigned int vin0_data10_mux[] = {
-       VI0_DATA0_MARK, VI0_DATA1_MARK,
-       VI0_DATA2_MARK, VI0_DATA3_MARK,
-       VI0_DATA4_MARK, VI0_DATA5_MARK,
-       VI0_DATA6_MARK, VI0_DATA7_MARK,
-       VI0_DATA8_MARK,  VI0_DATA9_MARK,
-};
-static const unsigned int vin0_data12_pins[] = {
-       RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-       RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-       RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-       RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
-       RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-};
-static const unsigned int vin0_data12_mux[] = {
-       VI0_DATA0_MARK, VI0_DATA1_MARK,
-       VI0_DATA2_MARK, VI0_DATA3_MARK,
-       VI0_DATA4_MARK, VI0_DATA5_MARK,
-       VI0_DATA6_MARK, VI0_DATA7_MARK,
-       VI0_DATA8_MARK,  VI0_DATA9_MARK,
-       VI0_DATA10_MARK, VI0_DATA11_MARK,
+static const union vin_data12 vin0_data_mux = {
+       .data12 = {
+               VI0_DATA0_MARK, VI0_DATA1_MARK,
+               VI0_DATA2_MARK, VI0_DATA3_MARK,
+               VI0_DATA4_MARK, VI0_DATA5_MARK,
+               VI0_DATA6_MARK, VI0_DATA7_MARK,
+               VI0_DATA8_MARK,  VI0_DATA9_MARK,
+               VI0_DATA10_MARK, VI0_DATA11_MARK,
+       },
 };
 static const unsigned int vin0_sync_pins[] = {
        /* HSYNC#, VSYNC# */
@@ -1650,47 +1628,25 @@ static const unsigned int vin0_clk_mux[] = {
 };
 
 /* - VIN1 ------------------------------------------------------------------- */
-static const unsigned int vin1_data8_pins[] = {
-       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-       RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int vin1_data8_mux[] = {
-       VI1_DATA0_MARK, VI1_DATA1_MARK,
-       VI1_DATA2_MARK, VI1_DATA3_MARK,
-       VI1_DATA4_MARK, VI1_DATA5_MARK,
-       VI1_DATA6_MARK, VI1_DATA7_MARK,
-};
-static const unsigned int vin1_data10_pins[] = {
-       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-       RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-       RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int vin1_data10_mux[] = {
-       VI1_DATA0_MARK, VI1_DATA1_MARK,
-       VI1_DATA2_MARK, VI1_DATA3_MARK,
-       VI1_DATA4_MARK, VI1_DATA5_MARK,
-       VI1_DATA6_MARK, VI1_DATA7_MARK,
-       VI1_DATA8_MARK,  VI1_DATA9_MARK,
-};
-static const unsigned int vin1_data12_pins[] = {
-       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-       RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-       RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-       RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+static const union vin_data12 vin1_data_pins = {
+       .data12 = {
+               RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+               RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+               RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+               RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+               RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+               RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+       },
 };
-static const unsigned int vin1_data12_mux[] = {
-       VI1_DATA0_MARK, VI1_DATA1_MARK,
-       VI1_DATA2_MARK, VI1_DATA3_MARK,
-       VI1_DATA4_MARK, VI1_DATA5_MARK,
-       VI1_DATA6_MARK, VI1_DATA7_MARK,
-       VI1_DATA8_MARK,  VI1_DATA9_MARK,
-       VI1_DATA10_MARK, VI1_DATA11_MARK,
+static const union vin_data12 vin1_data_mux = {
+       .data12 = {
+               VI1_DATA0_MARK, VI1_DATA1_MARK,
+               VI1_DATA2_MARK, VI1_DATA3_MARK,
+               VI1_DATA4_MARK, VI1_DATA5_MARK,
+               VI1_DATA6_MARK, VI1_DATA7_MARK,
+               VI1_DATA8_MARK,  VI1_DATA9_MARK,
+               VI1_DATA10_MARK, VI1_DATA11_MARK,
+       },
 };
 static const unsigned int vin1_sync_pins[] = {
        /* HSYNC#, VSYNC# */
@@ -1831,16 +1787,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(tmu_tclk1_b),
        SH_PFC_PIN_GROUP(tmu_tclk2_a),
        SH_PFC_PIN_GROUP(tmu_tclk2_b),
-       SH_PFC_PIN_GROUP(vin0_data8),
-       SH_PFC_PIN_GROUP(vin0_data10),
-       SH_PFC_PIN_GROUP(vin0_data12),
+       VIN_DATA_PIN_GROUP(vin0_data, 8),
+       VIN_DATA_PIN_GROUP(vin0_data, 10),
+       VIN_DATA_PIN_GROUP(vin0_data, 12),
        SH_PFC_PIN_GROUP(vin0_sync),
        SH_PFC_PIN_GROUP(vin0_field),
        SH_PFC_PIN_GROUP(vin0_clkenb),
        SH_PFC_PIN_GROUP(vin0_clk),
-       SH_PFC_PIN_GROUP(vin1_data8),
-       SH_PFC_PIN_GROUP(vin1_data10),
-       SH_PFC_PIN_GROUP(vin1_data12),
+       VIN_DATA_PIN_GROUP(vin1_data, 8),
+       VIN_DATA_PIN_GROUP(vin1_data, 10),
+       VIN_DATA_PIN_GROUP(vin1_data, 12),
        SH_PFC_PIN_GROUP(vin1_sync),
        SH_PFC_PIN_GROUP(vin1_field),
        SH_PFC_PIN_GROUP(vin1_clkenb),
index 8bef24502f0c608d5bd18c5b668978b861158067..b807b67ae143e30b7374a3394c6e49cf2f4f634e 100644 (file)
@@ -1970,47 +1970,25 @@ static const unsigned int vin0_clk_mux[] = {
 };
 
 /* - VIN1 ------------------------------------------------------------------- */
-static const unsigned int vin1_data8_pins[] = {
-       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-       RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int vin1_data8_mux[] = {
-       VI1_DATA0_MARK, VI1_DATA1_MARK,
-       VI1_DATA2_MARK, VI1_DATA3_MARK,
-       VI1_DATA4_MARK, VI1_DATA5_MARK,
-       VI1_DATA6_MARK, VI1_DATA7_MARK,
-};
-static const unsigned int vin1_data10_pins[] = {
-       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-       RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-       RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int vin1_data10_mux[] = {
-       VI1_DATA0_MARK, VI1_DATA1_MARK,
-       VI1_DATA2_MARK, VI1_DATA3_MARK,
-       VI1_DATA4_MARK, VI1_DATA5_MARK,
-       VI1_DATA6_MARK, VI1_DATA7_MARK,
-       VI1_DATA8_MARK, VI1_DATA9_MARK,
-};
-static const unsigned int vin1_data12_pins[] = {
-       RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-       RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-       RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-       RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-       RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
-       RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+static const union vin_data12 vin1_data_pins = {
+       .data12 = {
+               RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+               RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+               RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+               RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+               RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+               RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+       },
 };
-static const unsigned int vin1_data12_mux[] = {
-       VI1_DATA0_MARK, VI1_DATA1_MARK,
-       VI1_DATA2_MARK, VI1_DATA3_MARK,
-       VI1_DATA4_MARK, VI1_DATA5_MARK,
-       VI1_DATA6_MARK, VI1_DATA7_MARK,
-       VI1_DATA8_MARK,  VI1_DATA9_MARK,
-       VI1_DATA10_MARK, VI1_DATA11_MARK,
+static const union vin_data12 vin1_data_mux = {
+       .data12 = {
+               VI1_DATA0_MARK, VI1_DATA1_MARK,
+               VI1_DATA2_MARK, VI1_DATA3_MARK,
+               VI1_DATA4_MARK, VI1_DATA5_MARK,
+               VI1_DATA6_MARK, VI1_DATA7_MARK,
+               VI1_DATA8_MARK,  VI1_DATA9_MARK,
+               VI1_DATA10_MARK, VI1_DATA11_MARK,
+       },
 };
 static const unsigned int vin1_sync_pins[] = {
        /* VI1_VSYNC#, VI1_HSYNC# */
@@ -2182,9 +2160,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(vin0_field),
        SH_PFC_PIN_GROUP(vin0_clkenb),
        SH_PFC_PIN_GROUP(vin0_clk),
-       SH_PFC_PIN_GROUP(vin1_data8),
-       SH_PFC_PIN_GROUP(vin1_data10),
-       SH_PFC_PIN_GROUP(vin1_data12),
+       VIN_DATA_PIN_GROUP(vin1_data, 8),
+       VIN_DATA_PIN_GROUP(vin1_data, 10),
+       VIN_DATA_PIN_GROUP(vin1_data, 12),
        SH_PFC_PIN_GROUP(vin1_sync),
        SH_PFC_PIN_GROUP(vin1_field),
        SH_PFC_PIN_GROUP(vin1_clkenb),
index e40908dc37e06264f48b61475d71d3e4092ba550..151640c30e9dc791965a38e076cbca6f27d4e7f3 100644 (file)
        PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
        PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
        PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
-       PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
+       PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+       PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
+       PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
 /*
  * F_() : just information
  * FM() : macro for FN_xxx / xxx_MARK
@@ -391,29 +400,33 @@ FM(IP12_23_20)    IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM
 FM(IP12_27_24) IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 FM(IP12_31_28) IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28
 
+/* The bit numbering in MOD_SEL fields is reversed */
+#define REV4(f0, f1, f2, f3)                   f0 f2 f1 f3
+#define REV8(f0, f1, f2, f3, f4, f5, f6, f7)   f0 f4 f2 f6 f1 f5 f3 f7
+
 /* MOD_SEL0 */                 /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
-#define MOD_SEL0_30_29         FM(SEL_ADGB_0)                  FM(SEL_ADGB_1)                  FM(SEL_ADGB_2)                  F_(0, 0)
+#define MOD_SEL0_30_29    REV4(FM(SEL_ADGB_0),                 FM(SEL_ADGB_1),                 FM(SEL_ADGB_2),                 F_(0, 0))
 #define MOD_SEL0_28            FM(SEL_DRIF0_0)                 FM(SEL_DRIF0_1)
-#define MOD_SEL0_27_26         FM(SEL_FM_0)                    FM(SEL_FM_1)                    FM(SEL_FM_2)                    F_(0, 0)
+#define MOD_SEL0_27_26    REV4(FM(SEL_FM_0),                   FM(SEL_FM_1),                   FM(SEL_FM_2),                   F_(0, 0))
 #define MOD_SEL0_25            FM(SEL_FSO_0)                   FM(SEL_FSO_1)
 #define MOD_SEL0_24            FM(SEL_HSCIF0_0)                FM(SEL_HSCIF0_1)
 #define MOD_SEL0_23            FM(SEL_HSCIF1_0)                FM(SEL_HSCIF1_1)
 #define MOD_SEL0_22            FM(SEL_HSCIF2_0)                FM(SEL_HSCIF2_1)
-#define MOD_SEL0_21_20         FM(SEL_I2C1_0)                  FM(SEL_I2C1_1)                  FM(SEL_I2C1_2)                  FM(SEL_I2C1_3)
-#define MOD_SEL0_19_18_17      FM(SEL_I2C2_0)                  FM(SEL_I2C2_1)                  FM(SEL_I2C2_2)                  FM(SEL_I2C2_3)          FM(SEL_I2C2_4)          F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL0_21_20    REV4(FM(SEL_I2C1_0),                 FM(SEL_I2C1_1),                 FM(SEL_I2C1_2),                 FM(SEL_I2C1_3))
+#define MOD_SEL0_19_18_17  REV8(FM(SEL_I2C2_0),                        FM(SEL_I2C2_1),                 FM(SEL_I2C2_2),                 FM(SEL_I2C2_3),         FM(SEL_I2C2_4),         F_(0, 0),       F_(0, 0),       F_(0, 0))
 #define MOD_SEL0_16            FM(SEL_NDFC_0)                  FM(SEL_NDFC_1)
 #define MOD_SEL0_15            FM(SEL_PWM0_0)                  FM(SEL_PWM0_1)
 #define MOD_SEL0_14            FM(SEL_PWM1_0)                  FM(SEL_PWM1_1)
-#define MOD_SEL0_13_12         FM(SEL_PWM2_0)                  FM(SEL_PWM2_1)                  FM(SEL_PWM2_2)                  F_(0, 0)
-#define MOD_SEL0_11_10         FM(SEL_PWM3_0)                  FM(SEL_PWM3_1)                  FM(SEL_PWM3_2)                  F_(0, 0)
+#define MOD_SEL0_13_12    REV4(FM(SEL_PWM2_0),                 FM(SEL_PWM2_1),                 FM(SEL_PWM2_2),                 F_(0, 0))
+#define MOD_SEL0_11_10    REV4(FM(SEL_PWM3_0),                 FM(SEL_PWM3_1),                 FM(SEL_PWM3_2),                 F_(0, 0))
 #define MOD_SEL0_9             FM(SEL_PWM4_0)                  FM(SEL_PWM4_1)
 #define MOD_SEL0_8             FM(SEL_PWM5_0)                  FM(SEL_PWM5_1)
 #define MOD_SEL0_7             FM(SEL_PWM6_0)                  FM(SEL_PWM6_1)
-#define MOD_SEL0_6_5           FM(SEL_REMOCON_0)               FM(SEL_REMOCON_1)               FM(SEL_REMOCON_2)               F_(0, 0)
+#define MOD_SEL0_6_5      REV4(FM(SEL_REMOCON_0),              FM(SEL_REMOCON_1),              FM(SEL_REMOCON_2),              F_(0, 0))
 #define MOD_SEL0_4             FM(SEL_SCIF_0)                  FM(SEL_SCIF_1)
 #define MOD_SEL0_3             FM(SEL_SCIF0_0)                 FM(SEL_SCIF0_1)
 #define MOD_SEL0_2             FM(SEL_SCIF2_0)                 FM(SEL_SCIF2_1)
-#define MOD_SEL0_1_0           FM(SEL_SPEED_PULSE_IF_0)        FM(SEL_SPEED_PULSE_IF_1)        FM(SEL_SPEED_PULSE_IF_2)        F_(0, 0)
+#define MOD_SEL0_1_0      REV4(FM(SEL_SPEED_PULSE_IF_0),       FM(SEL_SPEED_PULSE_IF_1),       FM(SEL_SPEED_PULSE_IF_2),       F_(0, 0))
 
 /* MOD_SEL1 */                 /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
 #define MOD_SEL1_31            FM(SEL_SIMCARD_0)               FM(SEL_SIMCARD_1)
@@ -422,18 +435,18 @@ FM(IP12_31_28)    IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM
 #define MOD_SEL1_28            FM(SEL_USB_20_CH0_0)            FM(SEL_USB_20_CH0_1)
 #define MOD_SEL1_26            FM(SEL_DRIF2_0)                 FM(SEL_DRIF2_1)
 #define MOD_SEL1_25            FM(SEL_DRIF3_0)                 FM(SEL_DRIF3_1)
-#define MOD_SEL1_24_23_22      FM(SEL_HSCIF3_0)                FM(SEL_HSCIF3_1)                FM(SEL_HSCIF3_2)                FM(SEL_HSCIF3_3)        FM(SEL_HSCIF3_4)        F_(0, 0)        F_(0, 0)        F_(0, 0)
-#define MOD_SEL1_21_20_19      FM(SEL_HSCIF4_0)                FM(SEL_HSCIF4_1)                FM(SEL_HSCIF4_2)                FM(SEL_HSCIF4_3)        FM(SEL_HSCIF4_4)        F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL1_24_23_22  REV8(FM(SEL_HSCIF3_0),              FM(SEL_HSCIF3_1),               FM(SEL_HSCIF3_2),               FM(SEL_HSCIF3_3),       FM(SEL_HSCIF3_4),       F_(0, 0),       F_(0, 0),       F_(0, 0))
+#define MOD_SEL1_21_20_19  REV8(FM(SEL_HSCIF4_0),              FM(SEL_HSCIF4_1),               FM(SEL_HSCIF4_2),               FM(SEL_HSCIF4_3),       FM(SEL_HSCIF4_4),       F_(0, 0),       F_(0, 0),       F_(0, 0))
 #define MOD_SEL1_18            FM(SEL_I2C6_0)                  FM(SEL_I2C6_1)
 #define MOD_SEL1_17            FM(SEL_I2C7_0)                  FM(SEL_I2C7_1)
 #define MOD_SEL1_16            FM(SEL_MSIOF2_0)                FM(SEL_MSIOF2_1)
 #define MOD_SEL1_15            FM(SEL_MSIOF3_0)                FM(SEL_MSIOF3_1)
-#define MOD_SEL1_14_13         FM(SEL_SCIF3_0)                 FM(SEL_SCIF3_1)                 FM(SEL_SCIF3_2)                 F_(0, 0)
-#define MOD_SEL1_12_11         FM(SEL_SCIF4_0)                 FM(SEL_SCIF4_1)                 FM(SEL_SCIF4_2)                 F_(0, 0)
-#define MOD_SEL1_10_9          FM(SEL_SCIF5_0)                 FM(SEL_SCIF5_1)                 FM(SEL_SCIF5_2)                 F_(0, 0)
+#define MOD_SEL1_14_13    REV4(FM(SEL_SCIF3_0),                FM(SEL_SCIF3_1),                FM(SEL_SCIF3_2),                F_(0, 0))
+#define MOD_SEL1_12_11    REV4(FM(SEL_SCIF4_0),                FM(SEL_SCIF4_1),                FM(SEL_SCIF4_2),                F_(0, 0))
+#define MOD_SEL1_10_9     REV4(FM(SEL_SCIF5_0),                FM(SEL_SCIF5_1),                FM(SEL_SCIF5_2),                F_(0, 0))
 #define MOD_SEL1_8             FM(SEL_VIN4_0)                  FM(SEL_VIN4_1)
 #define MOD_SEL1_7             FM(SEL_VIN5_0)                  FM(SEL_VIN5_1)
-#define MOD_SEL1_6_5           FM(SEL_ADGC_0)                  FM(SEL_ADGC_1)                  FM(SEL_ADGC_2)                  F_(0, 0)
+#define MOD_SEL1_6_5      REV4(FM(SEL_ADGC_0),                 FM(SEL_ADGC_1),                 FM(SEL_ADGC_2),                 F_(0, 0))
 #define MOD_SEL1_4             FM(SEL_SSI9_0)                  FM(SEL_SSI9_1)
 
 #define PINMUX_MOD_SELS        \
@@ -1060,7 +1073,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP11_11_8,             RIF1_SYNC),
        PINMUX_IPSR_GPSR(IP11_11_8,             TS_SCK1),
 
-       PINMUX_IPSR_GPSR(IP11_15_12,            TX0_A),
+       PINMUX_IPSR_MSEL(IP11_15_12,            TX0_A,          SEL_SCIF0_0),
        PINMUX_IPSR_GPSR(IP11_15_12,            HTX1_A),
        PINMUX_IPSR_MSEL(IP11_15_12,            SSI_WS2_A,      SEL_SSI2_0),
        PINMUX_IPSR_GPSR(IP11_15_12,            RIF1_D0),
@@ -1099,7 +1112,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP12_3_0,              SSI_WS9_B,      SEL_SSI9_1),
        PINMUX_IPSR_GPSR(IP12_3_0,              AUDIO_CLKOUT3_B),
 
-       PINMUX_IPSR_GPSR(IP12_7_4,              SCK2_A),
+       PINMUX_IPSR_MSEL(IP12_7_4,              SCK2_A,         SEL_SCIF2_0),
        PINMUX_IPSR_MSEL(IP12_7_4,              HSCK0_A,        SEL_HSCIF0_0),
        PINMUX_IPSR_MSEL(IP12_7_4,              AUDIO_CLKB_A,   SEL_ADGB_0),
        PINMUX_IPSR_GPSR(IP12_7_4,              CTS1_N),
@@ -1107,14 +1120,14 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP12_7_4,              REMOCON_A,      SEL_REMOCON_0),
        PINMUX_IPSR_MSEL(IP12_7_4,              SCIF_CLK_B,     SEL_SCIF_1),
 
-       PINMUX_IPSR_GPSR(IP12_11_8,             TX2_A),
+       PINMUX_IPSR_MSEL(IP12_11_8,             TX2_A,          SEL_SCIF2_0),
        PINMUX_IPSR_MSEL(IP12_11_8,             HRX0_A,         SEL_HSCIF0_0),
        PINMUX_IPSR_GPSR(IP12_11_8,             AUDIO_CLKOUT2_A),
        PINMUX_IPSR_MSEL(IP12_11_8,             SCL1_A,         SEL_I2C1_0),
        PINMUX_IPSR_MSEL(IP12_11_8,             FSO_CFE_0_N_A,  SEL_FSO_0),
        PINMUX_IPSR_GPSR(IP12_11_8,             TS_SDEN1),
 
-       PINMUX_IPSR_GPSR(IP12_15_12,            RX2_A),
+       PINMUX_IPSR_MSEL(IP12_15_12,            RX2_A,          SEL_SCIF2_0),
        PINMUX_IPSR_GPSR(IP12_15_12,            HTX0_A),
        PINMUX_IPSR_GPSR(IP12_15_12,            AUDIO_CLKOUT3_A),
        PINMUX_IPSR_MSEL(IP12_15_12,            SDA1_A,         SEL_I2C1_0),
@@ -1126,11 +1139,11 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP12_23_20,            MSIOF0_RXD),
        PINMUX_IPSR_GPSR(IP12_23_20,            SSI_WS78),
-       PINMUX_IPSR_GPSR(IP12_23_20,            TX2_B),
+       PINMUX_IPSR_MSEL(IP12_23_20,            TX2_B,          SEL_SCIF2_1),
 
        PINMUX_IPSR_GPSR(IP12_27_24,            MSIOF0_TXD),
        PINMUX_IPSR_GPSR(IP12_27_24,            SSI_SDATA7),
-       PINMUX_IPSR_GPSR(IP12_27_24,            RX2_B),
+       PINMUX_IPSR_MSEL(IP12_27_24,            RX2_B,          SEL_SCIF2_1),
 
        PINMUX_IPSR_GPSR(IP12_31_28,            MSIOF0_SYNC),
        PINMUX_IPSR_GPSR(IP12_31_28,            AUDIO_CLKOUT_B),
@@ -1170,7 +1183,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP13_19_16,            SIM0_D_A,       SEL_SIMCARD_0),
 
        PINMUX_IPSR_GPSR(IP13_23_20,            MLB_DAT),
-       PINMUX_IPSR_GPSR(IP13_23_20,            TX0_B),
+       PINMUX_IPSR_MSEL(IP13_23_20,            TX0_B,          SEL_SCIF0_1),
        PINMUX_IPSR_MSEL(IP13_23_20,            RIF0_SYNC_A,    SEL_DRIF0_0),
        PINMUX_IPSR_GPSR(IP13_23_20,            SIM0_CLK_A),
 
@@ -1586,6 +1599,199 @@ static const unsigned int canfd1_data_mux[] = {
        CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 
+/* - DRIF0 --------------------------------------------------------------- */
+static const unsigned int drif0_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
+};
+
+static const unsigned int drif0_ctrl_a_mux[] = {
+       RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
+};
+
+static const unsigned int drif0_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(5, 17),
+};
+
+static const unsigned int drif0_data0_a_mux[] = {
+       RIF0_D0_A_MARK,
+};
+
+static const unsigned int drif0_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int drif0_data1_a_mux[] = {
+       RIF0_D1_A_MARK,
+};
+
+static const unsigned int drif0_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int drif0_ctrl_b_mux[] = {
+       RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
+};
+
+static const unsigned int drif0_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int drif0_data0_b_mux[] = {
+       RIF0_D0_B_MARK,
+};
+
+static const unsigned int drif0_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int drif0_data1_b_mux[] = {
+       RIF0_D1_B_MARK,
+};
+
+/* - DRIF1 --------------------------------------------------------------- */
+static const unsigned int drif1_ctrl_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
+};
+
+static const unsigned int drif1_ctrl_mux[] = {
+       RIF1_CLK_MARK, RIF1_SYNC_MARK,
+};
+
+static const unsigned int drif1_data0_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int drif1_data0_mux[] = {
+       RIF1_D0_MARK,
+};
+
+static const unsigned int drif1_data1_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(5, 3),
+};
+
+static const unsigned int drif1_data1_mux[] = {
+       RIF1_D1_MARK,
+};
+
+/* - DRIF2 --------------------------------------------------------------- */
+static const unsigned int drif2_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+
+static const unsigned int drif2_ctrl_a_mux[] = {
+       RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
+};
+
+static const unsigned int drif2_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(2, 8),
+};
+
+static const unsigned int drif2_data0_a_mux[] = {
+       RIF2_D0_A_MARK,
+};
+
+static const unsigned int drif2_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int drif2_data1_a_mux[] = {
+       RIF2_D1_A_MARK,
+};
+
+static const unsigned int drif2_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+};
+
+static const unsigned int drif2_ctrl_b_mux[] = {
+       RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
+};
+
+static const unsigned int drif2_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(1, 6),
+};
+
+static const unsigned int drif2_data0_b_mux[] = {
+       RIF2_D0_B_MARK,
+};
+
+static const unsigned int drif2_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(1, 7),
+};
+
+static const unsigned int drif2_data1_b_mux[] = {
+       RIF2_D1_B_MARK,
+};
+
+/* - DRIF3 --------------------------------------------------------------- */
+static const unsigned int drif3_ctrl_a_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int drif3_ctrl_a_mux[] = {
+       RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
+};
+
+static const unsigned int drif3_data0_a_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(2, 12),
+};
+
+static const unsigned int drif3_data0_a_mux[] = {
+       RIF3_D0_A_MARK,
+};
+
+static const unsigned int drif3_data1_a_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(2, 13),
+};
+
+static const unsigned int drif3_data1_a_mux[] = {
+       RIF3_D1_A_MARK,
+};
+
+static const unsigned int drif3_ctrl_b_pins[] = {
+       /* CLK, SYNC */
+       RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+};
+
+static const unsigned int drif3_ctrl_b_mux[] = {
+       RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
+};
+
+static const unsigned int drif3_data0_b_pins[] = {
+       /* D0 */
+       RCAR_GP_PIN(0, 10),
+};
+
+static const unsigned int drif3_data0_b_mux[] = {
+       RIF3_D0_B_MARK,
+};
+
+static const unsigned int drif3_data1_b_pins[] = {
+       /* D1 */
+       RCAR_GP_PIN(0, 11),
+};
+
+static const unsigned int drif3_data1_b_mux[] = {
+       RIF3_D1_B_MARK,
+};
+
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
        /* R[7:2], G[7:2], B[7:2] */
@@ -3243,6 +3449,43 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
        SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int tmu_tclk1_a_mux[] = {
+       TCLK1_A_MARK,
+};
+
+static const unsigned int tmu_tclk1_b_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(5, 17),
+};
+
+static const unsigned int tmu_tclk1_b_mux[] = {
+       TCLK1_B_MARK,
+};
+
+static const unsigned int tmu_tclk2_a_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int tmu_tclk2_a_mux[] = {
+       TCLK2_A_MARK,
+};
+
+static const unsigned int tmu_tclk2_b_pins[] = {
+       /* TCLK */
+       RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int tmu_tclk2_b_mux[] = {
+       TCLK2_B_MARK,
+};
+
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_a_pins[] = {
        /* PWEN, OVC */
@@ -3523,8 +3766,8 @@ static const unsigned int vin5_clk_b_mux[] = {
 };
 
 static const struct {
-       struct sh_pfc_pin_group common[241];
-       struct sh_pfc_pin_group automotive[2];
+       struct sh_pfc_pin_group common[245];
+       struct sh_pfc_pin_group automotive[23];
 } pinmux_groups = {
        .common = {
                SH_PFC_PIN_GROUP(audio_clk_a),
@@ -3735,6 +3978,10 @@ static const struct {
                SH_PFC_PIN_GROUP(ssi9_data),
                SH_PFC_PIN_GROUP(ssi9_ctrl_a),
                SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+               SH_PFC_PIN_GROUP(tmu_tclk1_a),
+               SH_PFC_PIN_GROUP(tmu_tclk1_b),
+               SH_PFC_PIN_GROUP(tmu_tclk2_a),
+               SH_PFC_PIN_GROUP(tmu_tclk2_b),
                SH_PFC_PIN_GROUP(usb0_a),
                SH_PFC_PIN_GROUP(usb0_b),
                SH_PFC_PIN_GROUP(usb0_id),
@@ -3772,6 +4019,27 @@ static const struct {
        .automotive = {
                SH_PFC_PIN_GROUP(canfd0_data),
                SH_PFC_PIN_GROUP(canfd1_data),
+               SH_PFC_PIN_GROUP(drif0_ctrl_a),
+               SH_PFC_PIN_GROUP(drif0_data0_a),
+               SH_PFC_PIN_GROUP(drif0_data1_a),
+               SH_PFC_PIN_GROUP(drif0_ctrl_b),
+               SH_PFC_PIN_GROUP(drif0_data0_b),
+               SH_PFC_PIN_GROUP(drif0_data1_b),
+               SH_PFC_PIN_GROUP(drif1_ctrl),
+               SH_PFC_PIN_GROUP(drif1_data0),
+               SH_PFC_PIN_GROUP(drif1_data1),
+               SH_PFC_PIN_GROUP(drif2_ctrl_a),
+               SH_PFC_PIN_GROUP(drif2_data0_a),
+               SH_PFC_PIN_GROUP(drif2_data1_a),
+               SH_PFC_PIN_GROUP(drif2_ctrl_b),
+               SH_PFC_PIN_GROUP(drif2_data0_b),
+               SH_PFC_PIN_GROUP(drif2_data1_b),
+               SH_PFC_PIN_GROUP(drif3_ctrl_a),
+               SH_PFC_PIN_GROUP(drif3_data0_a),
+               SH_PFC_PIN_GROUP(drif3_data1_a),
+               SH_PFC_PIN_GROUP(drif3_ctrl_b),
+               SH_PFC_PIN_GROUP(drif3_data0_b),
+               SH_PFC_PIN_GROUP(drif3_data1_b),
        }
 };
 
@@ -3826,6 +4094,39 @@ static const char * const canfd1_groups[] = {
        "canfd1_data",
 };
 
+static const char * const drif0_groups[] = {
+       "drif0_ctrl_a",
+       "drif0_data0_a",
+       "drif0_data1_a",
+       "drif0_ctrl_b",
+       "drif0_data0_b",
+       "drif0_data1_b",
+};
+
+static const char * const drif1_groups[] = {
+       "drif1_ctrl",
+       "drif1_data0",
+       "drif1_data1",
+};
+
+static const char * const drif2_groups[] = {
+       "drif2_ctrl_a",
+       "drif2_data0_a",
+       "drif2_data1_a",
+       "drif2_ctrl_b",
+       "drif2_data0_b",
+       "drif2_data1_b",
+};
+
+static const char * const drif3_groups[] = {
+       "drif3_ctrl_a",
+       "drif3_data0_a",
+       "drif3_data1_a",
+       "drif3_ctrl_b",
+       "drif3_data0_b",
+       "drif3_data1_b",
+};
+
 static const char * const du_groups[] = {
        "du_rgb666",
        "du_rgb888",
@@ -4111,6 +4412,13 @@ static const char * const ssi_groups[] = {
        "ssi9_ctrl_b",
 };
 
+static const char * const tmu_groups[] = {
+       "tmu_tclk1_a",
+       "tmu_tclk1_b",
+       "tmu_tclk2_a",
+       "tmu_tclk2_b",
+};
+
 static const char * const usb0_groups[] = {
        "usb0_a",
        "usb0_b",
@@ -4157,8 +4465,8 @@ static const char * const vin5_groups[] = {
 };
 
 static const struct {
-       struct sh_pfc_function common[44];
-       struct sh_pfc_function automotive[2];
+       struct sh_pfc_function common[45];
+       struct sh_pfc_function automotive[6];
 } pinmux_functions = {
        .common = {
                SH_PFC_FUNCTION(audio_clk),
@@ -4201,6 +4509,7 @@ static const struct {
                SH_PFC_FUNCTION(sdhi1),
                SH_PFC_FUNCTION(sdhi3),
                SH_PFC_FUNCTION(ssi),
+               SH_PFC_FUNCTION(tmu),
                SH_PFC_FUNCTION(usb0),
                SH_PFC_FUNCTION(usb30),
                SH_PFC_FUNCTION(vin4),
@@ -4209,6 +4518,10 @@ static const struct {
        .automotive = {
                SH_PFC_FUNCTION(canfd0),
                SH_PFC_FUNCTION(canfd1),
+               SH_PFC_FUNCTION(drif0),
+               SH_PFC_FUNCTION(drif1),
+               SH_PFC_FUNCTION(drif2),
+               SH_PFC_FUNCTION(drif3),
        }
 };
 
@@ -4914,17 +5227,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
        { /* sentinel */ },
 };
 
-static bool pin_has_pud(unsigned int pin)
-{
-       /* Some pins are pull-up only */
-       switch (pin) {
-       case RCAR_GP_PIN(6, 9): /* USB30_OVC  */
-               return false;
-       }
-
-       return true;
-}
-
 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
                                             unsigned int pin)
 {
@@ -4937,7 +5239,7 @@ static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
 
        if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
                return PIN_CONFIG_BIAS_DISABLE;
-       else if (!pin_has_pud(pin) || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
+       else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
                return PIN_CONFIG_BIAS_PULL_UP;
        else
                return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -4958,13 +5260,11 @@ static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
        if (bias != PIN_CONFIG_BIAS_DISABLE)
                enable |= BIT(bit);
 
-       if (pin_has_pud(pin)) {
-               updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
-               if (bias == PIN_CONFIG_BIAS_PULL_UP)
-                       updown |= BIT(bit);
+       updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+       if (bias == PIN_CONFIG_BIAS_PULL_UP)
+               updown |= BIT(bit);
 
-               sh_pfc_write(pfc, reg->pud, updown);
-       }
+       sh_pfc_write(pfc, reg->pud, updown);
        sh_pfc_write(pfc, reg->puen, enable);
 }
 
index 84d78db381e302492b457f70c6e3d86a390fb56a..9e377e3b9cb3c20c8953f71e1784e9bd0d3fde87 100644 (file)
@@ -381,6 +381,9 @@ FM(IP12_23_20)      IP12_23_20 \
 FM(IP12_27_24) IP12_27_24 \
 FM(IP12_31_28) IP12_31_28 \
 
+/* The bit numbering in MOD_SEL fields is reversed */
+#define REV4(f0, f1, f2, f3)                   f0 f2 f1 f3
+
 /* MOD_SEL0 */                 /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 #define MOD_SEL0_30            FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)
 #define MOD_SEL0_29            FM(SEL_I2C3_0)          FM(SEL_I2C3_1)
@@ -388,10 +391,10 @@ FM(IP12_31_28)    IP12_31_28 \
 #define MOD_SEL0_27            FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)
 #define MOD_SEL0_26            FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)
 #define MOD_SEL0_25            FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)
-#define MOD_SEL0_24_23         FM(SEL_PWM0_0)          FM(SEL_PWM0_1)          FM(SEL_PWM0_2)          F_(0, 0)
-#define MOD_SEL0_22_21         FM(SEL_PWM1_0)          FM(SEL_PWM1_1)          FM(SEL_PWM1_2)          F_(0, 0)
-#define MOD_SEL0_20_19         FM(SEL_PWM2_0)          FM(SEL_PWM2_1)          FM(SEL_PWM2_2)          F_(0, 0)
-#define MOD_SEL0_18_17         FM(SEL_PWM3_0)          FM(SEL_PWM3_1)          FM(SEL_PWM3_2)          F_(0, 0)
+#define MOD_SEL0_24_23    REV4(FM(SEL_PWM0_0),         FM(SEL_PWM0_1),         FM(SEL_PWM0_2),         F_(0, 0))
+#define MOD_SEL0_22_21    REV4(FM(SEL_PWM1_0),         FM(SEL_PWM1_1),         FM(SEL_PWM1_2),         F_(0, 0))
+#define MOD_SEL0_20_19    REV4(FM(SEL_PWM2_0),         FM(SEL_PWM2_1),         FM(SEL_PWM2_2),         F_(0, 0))
+#define MOD_SEL0_18_17    REV4(FM(SEL_PWM3_0),         FM(SEL_PWM3_1),         FM(SEL_PWM3_2),         F_(0, 0))
 #define MOD_SEL0_15            FM(SEL_IRQ_0_0)         FM(SEL_IRQ_0_1)
 #define MOD_SEL0_14            FM(SEL_IRQ_1_0)         FM(SEL_IRQ_1_1)
 #define MOD_SEL0_13            FM(SEL_IRQ_2_0)         FM(SEL_IRQ_2_1)
index 085770e66895680a5bd32728b6e98352f597ea4f..ef3da8bf1d8700fa4e8819708be899a8514acf21 100644 (file)
@@ -3354,7 +3354,8 @@ static const char * const fsic_groups[] = {
        "fsic_sclk_out",
        "fsic_data_in",
        "fsic_data_out",
-       "fsic_spdif",
+       "fsic_spdif_0",
+       "fsic_spdif_1",
 };
 
 static const char * const fsid_groups[] = {
index 274d5ff87078645727df13e0796287bfa154dda4..c97d2ba7677c91e9f613ccfce22efc6fa0ebcc64 100644 (file)
@@ -347,6 +347,8 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
        unsigned int i;
        int ret = 0;
 
+       dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
+
        spin_lock_irqsave(&pfc->lock, flags);
 
        for (i = 0; i < grp->nr_pins; ++i) {
index 46d477ff510921f36036b92bf8778296fbf3b081..56016cb76769c97bd1298b38eaeb329dde09da17 100644 (file)
@@ -126,7 +126,8 @@ struct pinmux_cfg_reg {
  * one for each possible combination of the register field bit values.
  */
 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
-       .reg = r, .reg_width = r_width, .field_width = f_width,         \
+       .reg = r, .reg_width = r_width,                                 \
+       .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width),  \
        .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
 
 /*
index 4ba171827428b3bbcc882c9ecacded69e10a3639..8a0eee0442641b18452339528c1a1d1c0c28a7c3 100644 (file)
@@ -6007,8 +6007,8 @@ static int atlas7_gpio_probe(struct platform_device *pdev)
        }
 
        /* retrieve gpio descriptor data */
-       a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
-                       sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
+       a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
+                           GFP_KERNEL);
        if (!a7gc)
                return -ENOMEM;
 
index 2e42d738b58977865279501d03f0093dd820a0f2..2b3bd1a41f21f27f9f8b076b0cc98a8a1eea41da 100644 (file)
@@ -782,7 +782,7 @@ static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
 static int sirfsoc_gpio_probe(struct device_node *np)
 {
        int i, err = 0;
-       static struct sirfsoc_gpio_chip *sgpio;
+       struct sirfsoc_gpio_chip *sgpio;
        struct sirfsoc_gpio_bank *bank;
        void __iomem *regs;
        struct platform_device *pdev;
index 813eccbb9aafadc01a90caec136356b70ddcb3e1..0b9ff5aa6bb5b85c2fe9f490a4e30c29e4f88e9d 100644 (file)
@@ -414,7 +414,7 @@ static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
        unsigned int num_configs;
        bool has_config = 0;
        unsigned reserve = 0;
-       int num_pins, num_funcs, maps_per_pin, i, err;
+       int num_pins, num_funcs, maps_per_pin, i, err = 0;
 
        pctl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -441,41 +441,45 @@ static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
        if (has_config && num_pins >= 1)
                maps_per_pin++;
 
-       if (!num_pins || !maps_per_pin)
-               return -EINVAL;
+       if (!num_pins || !maps_per_pin) {
+               err = -EINVAL;
+               goto exit;
+       }
 
        reserve = num_pins * maps_per_pin;
 
        err = pinctrl_utils_reserve_map(pctldev, map,
                        reserved_maps, num_maps, reserve);
        if (err)
-               return err;
+               goto exit;
 
        for (i = 0; i < num_pins; i++) {
                err = of_property_read_u32_index(node, "pinmux",
                                i, &pinfunc);
                if (err)
-                       return err;
+                       goto exit;
 
                pin = STM32_GET_PIN_NO(pinfunc);
                func = STM32_GET_PIN_FUNC(pinfunc);
 
                if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
                        dev_err(pctl->dev, "invalid function.\n");
-                       return -EINVAL;
+                       err = -EINVAL;
+                       goto exit;
                }
 
                grp = stm32_pctrl_find_group_by_pin(pctl, pin);
                if (!grp) {
                        dev_err(pctl->dev, "unable to match pin %d to group\n",
                                        pin);
-                       return -EINVAL;
+                       err = -EINVAL;
+                       goto exit;
                }
 
                err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
                                reserved_maps, num_maps);
                if (err)
-                       return err;
+                       goto exit;
 
                if (has_config) {
                        err = pinctrl_utils_add_map_configs(pctldev, map,
@@ -483,11 +487,13 @@ static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
                                        configs, num_configs,
                                        PIN_MAP_TYPE_CONFIGS_GROUP);
                        if (err)
-                               return err;
+                               goto exit;
                }
        }
 
-       return 0;
+exit:
+       kfree(configs);
+       return err;
 }
 
 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
@@ -577,8 +583,8 @@ static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
        return 0;
 }
 
-static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
-               int pin, u32 mode, u32 alt)
+static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
+                             int pin, u32 mode, u32 alt)
 {
        struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
        u32 val;
@@ -614,6 +620,8 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
 unlock:
        spin_unlock_irqrestore(&bank->lock, flags);
        clk_disable(bank->clk);
+
+       return err;
 }
 
 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
@@ -670,9 +678,7 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
        mode = stm32_gpio_get_mode(function);
        alt = stm32_gpio_get_alt(function);
 
-       stm32_pmx_set_mode(bank, pin, mode, alt);
-
-       return 0;
+       return stm32_pmx_set_mode(bank, pin, mode, alt);
 }
 
 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -682,9 +688,7 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
        struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
        int pin = stm32_gpio_pin(gpio);
 
-       stm32_pmx_set_mode(bank, pin, !input, 0);
-
-       return 0;
+       return stm32_pmx_set_mode(bank, pin, !input, 0);
 }
 
 static const struct pinmux_ops stm32_pmx_ops = {
@@ -698,8 +702,8 @@ static const struct pinmux_ops stm32_pmx_ops = {
 
 /* Pinconf functions */
 
-static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
-       unsigned offset, u32 drive)
+static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
+                                  unsigned offset, u32 drive)
 {
        struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
        unsigned long flags;
@@ -728,6 +732,8 @@ static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
 unlock:
        spin_unlock_irqrestore(&bank->lock, flags);
        clk_disable(bank->clk);
+
+       return err;
 }
 
 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
@@ -748,8 +754,8 @@ static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
        return (val >> offset);
 }
 
-static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
-       unsigned offset, u32 speed)
+static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
+                                unsigned offset, u32 speed)
 {
        struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
        unsigned long flags;
@@ -778,6 +784,8 @@ static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
 unlock:
        spin_unlock_irqrestore(&bank->lock, flags);
        clk_disable(bank->clk);
+
+       return err;
 }
 
 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
@@ -798,8 +806,8 @@ static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
        return (val >> (offset * 2));
 }
 
-static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
-       unsigned offset, u32 bias)
+static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
+                               unsigned offset, u32 bias)
 {
        struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
        unsigned long flags;
@@ -828,6 +836,8 @@ static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
 unlock:
        spin_unlock_irqrestore(&bank->lock, flags);
        clk_disable(bank->clk);
+
+       return err;
 }
 
 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
@@ -890,22 +900,22 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
 
        switch (param) {
        case PIN_CONFIG_DRIVE_PUSH_PULL:
-               stm32_pconf_set_driving(bank, offset, 0);
+               ret = stm32_pconf_set_driving(bank, offset, 0);
                break;
        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-               stm32_pconf_set_driving(bank, offset, 1);
+               ret = stm32_pconf_set_driving(bank, offset, 1);
                break;
        case PIN_CONFIG_SLEW_RATE:
-               stm32_pconf_set_speed(bank, offset, arg);
+               ret = stm32_pconf_set_speed(bank, offset, arg);
                break;
        case PIN_CONFIG_BIAS_DISABLE:
-               stm32_pconf_set_bias(bank, offset, 0);
+               ret = stm32_pconf_set_bias(bank, offset, 0);
                break;
        case PIN_CONFIG_BIAS_PULL_UP:
-               stm32_pconf_set_bias(bank, offset, 1);
+               ret = stm32_pconf_set_bias(bank, offset, 1);
                break;
        case PIN_CONFIG_BIAS_PULL_DOWN:
-               stm32_pconf_set_bias(bank, offset, 2);
+               ret = stm32_pconf_set_bias(bank, offset, 2);
                break;
        case PIN_CONFIG_OUTPUT:
                __stm32_gpio_set(bank, offset, arg);
index c63086c9833575e3535f5c63678dfbd94857c7ac..e05dd9a5551d470c12226bd44c1909a45c363640 100644 (file)
@@ -153,6 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
        .pin_base = PL_BASE,
        .irq_banks = 2,
        .disable_strict_mode = true,
+       .has_io_bias_cfg = true,
 };
 
 static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
index 5553c0eb0f41c420e422686bdacb6ea3c1c2c14a..da37d594a13da813b6405fa371f6cae2c9b5cae8 100644 (file)
@@ -722,6 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
        .npins = ARRAY_SIZE(sun9i_a80_pins),
        .irq_banks = 5,
        .disable_strict_mode = true,
+       .has_io_bias_cfg = true,
 };
 
 static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
index 0e7fa69e93dfd32aa74182d90ac07a517f1a32db..8dd25caea2cf7ca54a7b385f772756b30668e35f 100644 (file)
@@ -603,6 +603,45 @@ static const struct pinconf_ops sunxi_pconf_ops = {
        .pin_config_group_set   = sunxi_pconf_group_set,
 };
 
+static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
+                                        unsigned pin,
+                                        struct regulator *supply)
+{
+       u32 val, reg;
+       int uV;
+
+       if (!pctl->desc->has_io_bias_cfg)
+               return 0;
+
+       uV = regulator_get_voltage(supply);
+       if (uV < 0)
+               return uV;
+
+       /* Might be dummy regulator with no voltage set */
+       if (uV == 0)
+               return 0;
+
+       /* Configured value must be equal or greater to actual voltage */
+       if (uV <= 1800000)
+               val = 0x0; /* 1.8V */
+       else if (uV <= 2500000)
+               val = 0x6; /* 2.5V */
+       else if (uV <= 2800000)
+               val = 0x9; /* 2.8V */
+       else if (uV <= 3000000)
+               val = 0xA; /* 3.0V */
+       else
+               val = 0xD; /* 3.3V */
+
+       pin -= pctl->desc->pin_base;
+
+       reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
+       reg &= ~IO_BIAS_MASK;
+       writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
+
+       return 0;
+}
+
 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 {
        struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@@ -725,6 +764,8 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
                goto out;
        }
 
+       sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
+
        s_reg->regulator = reg;
        refcount_set(&s_reg->refcount, 1);
 
index 034c0317c8d61694c39e8afc127e34dbe5e4c931..ee15ab067b5fd0692e5ba4c010f1db1d88bd4d85 100644 (file)
 #define IRQ_LEVEL_LOW          0x03
 #define IRQ_EDGE_BOTH          0x04
 
+#define GRP_CFG_REG            0x300
+
+#define IO_BIAS_MASK           GENMASK(3, 0)
+
 #define SUN4I_FUNC_INPUT       0
 #define SUN4I_FUNC_IRQ         6
 
@@ -113,6 +117,7 @@ struct sunxi_pinctrl_desc {
        const unsigned int              *irq_bank_map;
        bool                            irq_read_needs_mux;
        bool                            disable_strict_mode;
+       bool                            has_io_bias_cfg;
 };
 
 struct sunxi_pinctrl_function {
@@ -338,6 +343,13 @@ static inline u32 sunxi_irq_status_offset(u16 irq)
        return irq_num * IRQ_STATUS_IRQ_BITS;
 }
 
+static inline u32 sunxi_grp_config_reg(u16 pin)
+{
+       u8 bank = pin / PINS_PER_BANK;
+
+       return GRP_CFG_REG + bank * 0x4;
+}
+
 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
                                    const struct sunxi_pinctrl_desc *desc,
                                    unsigned long variant);
index a4bc506a01a3f336fd4e7e56a3f8ff68505139c3..e5e7f1f228138328a684d7190265fe168af41ebd 100644 (file)
@@ -263,9 +263,9 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod,
        reg_val |= reg->unlock_val << __ffs(reg->lock_mask);
        r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);
 
-       dev_info(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n",
-                cfg->offset, cfg->a_delay, cfg->g_delay, c_elements,
-                f_elements, reg_val);
+       dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n",
+               cfg->offset, cfg->a_delay, cfg->g_delay, c_elements,
+               f_elements, reg_val);
 
        return r;
 }
@@ -923,7 +923,6 @@ static struct platform_driver ti_iodelay_driver = {
        .probe = ti_iodelay_probe,
        .remove = ti_iodelay_remove,
        .driver = {
-                  .owner = THIS_MODULE,
                   .name = DRIVER_NAME,
                   .of_match_table = ti_iodelay_of_match,
        },
index eb81867eac77eda6901aa1c7bdbdc0bc3a0313a2..8dc10e00c62729505f61e01f31a29dc61a2f8d29 100644 (file)
@@ -17,6 +17,7 @@
 #define AT91_PINCTRL_DIS_SCHMIT                (1 << 4)
 #define AT91_PINCTRL_OUTPUT            (1 << 7)
 #define AT91_PINCTRL_OUTPUT_VAL(x)     ((x & 0x1) << 8)
+#define AT91_PINCTRL_SLEWRATE          (1 << 9)
 #define AT91_PINCTRL_DEBOUNCE          (1 << 16)
 #define AT91_PINCTRL_DEBOUNCE_VAL(x)   (x << 17)
 
@@ -27,6 +28,9 @@
 #define AT91_PINCTRL_DRIVE_STRENGTH_MED                        (0x2 << 5)
 #define AT91_PINCTRL_DRIVE_STRENGTH_HI                 (0x3 << 5)
 
+#define AT91_PINCTRL_SLEWRATE_DIS      (0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA      (0x1 << 9)
+
 #define AT91_PIOA      0
 #define AT91_PIOB      1
 #define AT91_PIOC      2
index 8dd85d302b9095332137985439e40464d4aa4571..93c9dd133e9d1a55ca62d68f7f752ddf001b8051 100644 (file)
@@ -14,8 +14,6 @@
 
 #ifdef CONFIG_PINCONF
 
-#include <linux/pinctrl/machine.h>
-
 struct pinctrl_dev;
 struct seq_file;
 
@@ -31,7 +29,6 @@ struct seq_file;
  * @pin_config_group_get: get configurations for an entire pin group; should
  *     return -ENOTSUPP and -EINVAL using the same rules as pin_config_get.
  * @pin_config_group_set: configure all pins in a group
- * @pin_config_dbg_parse_modify: optional debugfs to modify a pin configuration
  * @pin_config_dbg_show: optional debugfs display hook that will provide
  *     per-device info for a certain pin in debugfs
  * @pin_config_group_dbg_show: optional debugfs display hook that will provide
@@ -57,9 +54,6 @@ struct pinconf_ops {
                                     unsigned selector,
                                     unsigned long *configs,
                                     unsigned num_configs);
-       int (*pin_config_dbg_parse_modify) (struct pinctrl_dev *pctldev,
-                                          const char *arg,
-                                          unsigned long *config);
        void (*pin_config_dbg_show) (struct pinctrl_dev *pctldev,
                                     struct seq_file *s,
                                     unsigned offset);