RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler

The existing mechanism for handling IRQs on RISC-V is pretty ugly: the irq
entry code selects the handler via Kconfig dependencies.

Use the new generic IRQ handling infastructure, which allows boot time
registration of the low level entry handler.

This does add an additional load to the interrupt latency, but there's a
lot of tuning left to be done there on RISC-V so it's OK for now.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Acked-by: Stafford Horne <shorne@gmail.com>
Cc: jonas@southpole.se
Cc: catalin.marinas@arm.com
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux@armlinux.org.uk
Cc: stefan.kristiansson@saunalahti.fi
Cc: openrisc@lists.librecores.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20180307235731.22627-3-palmer@sifive.com

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 04807c7f64cc58f7b2e4be1ec1d10b4cf1b018a8..148865de1692f54478796d74bdccbcb459f069f8 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -33,6 +33,7 @@ config RISCV
        select MODULES_USE_ELF_RELA if MODULES
        select THREAD_INFO_IN_TASK
        select RISCV_TIMER
+       select GENERIC_IRQ_MULTI_HANDLER
 
 config MMU
        def_bool y

diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 4286a5f838760c7ad4d922ddd2b49286c374df56..1e5fd280fb4d150ebc5a593b7f249af0330a7228 100644 (file)
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -15,6 +15,7 @@ generic-y += fcntl.h
 generic-y += futex.h
 generic-y += hardirq.h
 generic-y += hash.h
+generic-y += handle_irq.h
 generic-y += hw_irq.h
 generic-y += ioctl.h
 generic-y += ioctls.h

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 56fa592cfa349b9cbf1e2e9e580bbd4c27bb9d51..9aaf6c98677192ddacbcb2745dd55c8f630b3330 100644 (file)
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -167,10 +167,9 @@ ENTRY(handle_exception)
        bge s4, zero, 1f
 
        /* Handle interrupts */
-       slli a0, s4, 1
-       srli a0, a0, 1
-       move a1, sp /* pt_regs */
-       tail do_IRQ
+       move a0, sp /* pt_regs */
+       REG_L a1, handle_arch_irq
+       jr a1
 1:
        /* Exceptions run with interrupts enabled */
        csrs sstatus, SR_SIE

diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 328718e8026e174a6887df75cbc1c7d08082d852..b74cbfbce2d0dd9df65ba779ab9dd8feb0d38eed 100644 (file)
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -24,16 +24,3 @@ void __init init_IRQ(void)
 {
        irqchip_init();
 }
-
-asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs)
-{
-#ifdef CONFIG_RISCV_INTC
-       /*
-        * FIXME: We don't want a direct call to riscv_intc_irq here.  The plan
-        * is to put an IRQ domain here and let the interrupt controller
-        * register with that, but I poked around the arm64 code a bit and
-        * there might be a better way to do it (ie, something fully generic).
-        */
-       riscv_intc_irq(cause, regs);
-#endif
-}