allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
+ allwinner,suniv-f1c100s
nextthing,gr8
"allwinner,sun4i-a10-wdt"
"allwinner,sun6i-a31-wdt"
"allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
+ "allwinner,suniv-f1c100s-wdt", "allwinner,sun4i-a10-wdt"
- reg : Specifies base physical address and size of the registers.
Optional properties:
F: Documentation/devicetree/bindings/clock/amlogic*
ARM/Amlogic Meson SoC support
-M: Carlo Caione <carlo@caione.org>
M: Kevin Hilman <khilman@baylibre.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-amlogic@lists.infradead.org
F: arch/arm64/boot/dts/amlogic/
F: drivers/pinctrl/meson/
F: drivers/mmc/host/meson*
+F: drivers/soc/amlogic/
N: meson
ARM/Annapurna Labs ALPINE ARCHITECTURE
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
- config DEBUG_SOCFPGA_UART1
+ config DEBUG_SOCFPGA_ARRIA10_UART1
depends on ARCH_SOCFPGA
- bool "Use SOCFPGA UART1 for low-level debug"
+ bool "Use SOCFPGA Arria10 UART1 for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Arria 10) based platforms.
+ config DEBUG_SOCFPGA_CYCLONE5_UART1
+ depends on ARCH_SOCFPGA
+ bool "Use SOCFPGA Cyclone 5 UART1 for low-level debug"
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
config DEBUG_SUN9I_UART0
bool "Kernel low-level debugging messages via sun9i UART0"
If unsure, say N.
+ config STM32F4_DEBUG_UART
+ bool "Use STM32F4 UART for low-level debug"
+ depends on ARCH_STM32
+ select DEBUG_STM32_UART
+ help
+ Say Y here if you want kernel low-level debugging support
+ on STM32F4 based platforms, which default UART is wired on
+ USART1.
+
+ If unsure, say N.
+
+ config STM32F7_DEBUG_UART
+ bool "Use STM32F7 UART for low-level debug"
+ depends on ARCH_STM32
+ select DEBUG_STM32_UART
+ help
+ Say Y here if you want kernel low-level debugging support
+ on STM32F7 based platforms, which default UART is wired on
+ USART1.
+
+ If unsure, say N.
+
config TEGRA_DEBUG_UART_AUTO_ODMDATA
bool "Kernel low-level debugging messages via Tegra UART via ODMDATA"
depends on ARCH_TEGRA
depends on ARCH_OMAP2PLUS
config DEBUG_IMX_UART_PORT
- int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
- DEBUG_IMX25_UART || \
- DEBUG_IMX21_IMX27_UART || \
- DEBUG_IMX31_UART || \
- DEBUG_IMX35_UART || \
- DEBUG_IMX50_UART || \
- DEBUG_IMX51_UART || \
- DEBUG_IMX53_UART || \
- DEBUG_IMX6Q_UART || \
- DEBUG_IMX6SL_UART || \
- DEBUG_IMX6SX_UART || \
- DEBUG_IMX6UL_UART || \
- DEBUG_IMX7D_UART
+ int "i.MX Debug UART Port Selection"
+ depends on DEBUG_IMX1_UART || \
+ DEBUG_IMX25_UART || \
+ DEBUG_IMX21_IMX27_UART || \
+ DEBUG_IMX31_UART || \
+ DEBUG_IMX35_UART || \
+ DEBUG_IMX50_UART || \
+ DEBUG_IMX51_UART || \
+ DEBUG_IMX53_UART || \
+ DEBUG_IMX6Q_UART || \
+ DEBUG_IMX6SL_UART || \
+ DEBUG_IMX6SX_UART || \
+ DEBUG_IMX6UL_UART || \
+ DEBUG_IMX7D_UART
default 1
- depends on ARCH_MXC
help
Choose UART port on which kernel low-level debug messages
should be output.
bool
depends on ARCH_STI
+config DEBUG_STM32_UART
+ bool
+ depends on ARCH_STM32
+
config DEBUG_SIRFSOC_UART
bool
depends on ARCH_SIRF
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFSOC_UART
default "debug/sti.S" if DEBUG_STI_UART
+ default "debug/stm32.S" if DEBUG_STM32_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT
default 0xfe800000 if ARCH_IOP32X
default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART0
- default 0xffc02100 if DEBUG_SOCFPGA_UART1
+ default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1
+ default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
default 0xfec02000 if DEBUG_SOCFPGA_UART0
- default 0xfec02100 if DEBUG_SOCFPGA_UART1
+ default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1
+ default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
default y if DEBUG_PICOXCELL_UART || \
- DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_UART1 || \
- DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \
- DEBUG_ALPINE_UART0 || \
+ DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
+ DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
+ DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
#define UARTA_3390 REG_PHYS_ADDR(0x40a900)
#define UARTA_7250 REG_PHYS_ADDR(0x40b400)
-#define UARTA_7260 REG_PHYS_ADDR(0x40c000)
-#define UARTA_7268 UARTA_7260
+#define UARTA_7255 REG_PHYS_ADDR(0x40c000)
+#define UARTA_7260 UARTA_7255
+#define UARTA_7268 UARTA_7255
#define UARTA_7271 UARTA_7268
#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
/* Chip specific detection starts here */
20: checkuart(\rp, \rv, 0x33900000, 3390)
21: checkuart(\rp, \rv, 0x72500000, 7250)
-22: checkuart(\rp, \rv, 0x72600000, 7260)
-23: checkuart(\rp, \rv, 0x72680000, 7268)
-24: checkuart(\rp, \rv, 0x72710000, 7271)
-25: checkuart(\rp, \rv, 0x73640000, 7364)
-26: checkuart(\rp, \rv, 0x73660000, 7366)
-27: checkuart(\rp, \rv, 0x07437100, 74371)
-28: checkuart(\rp, \rv, 0x74390000, 7439)
-29: checkuart(\rp, \rv, 0x74450000, 7445)
-30: checkuart(\rp, \rv, 0x72780000, 7278)
+22: checkuart(\rp, \rv, 0x72550000, 7255)
+23: checkuart(\rp, \rv, 0x72600000, 7260)
+24: checkuart(\rp, \rv, 0x72680000, 7268)
+25: checkuart(\rp, \rv, 0x72710000, 7271)
+26: checkuart(\rp, \rv, 0x72780000, 7278)
+27: checkuart(\rp, \rv, 0x73640000, 7364)
+28: checkuart(\rp, \rv, 0x73660000, 7366)
+29: checkuart(\rp, \rv, 0x07437100, 74371)
+30: checkuart(\rp, \rv, 0x74390000, 7439)
+31: checkuart(\rp, \rv, 0x74450000, 7445)
/* No valid UART found */
90: mov \rp, #0
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) STMicroelectronics SA 2017 - All Rights Reserved
+ * Author: Gerald Baeza <gerald.baeza@st.com> for STMicroelectronics.
+ */
+
+#define STM32_UART_BASE 0x40011000 /* USART1 */
+
+#ifdef CONFIG_STM32F4_DEBUG_UART
+#define STM32_USART_SR_OFF 0x00
+#define STM32_USART_TDR_OFF 0x04
+#endif
+
+#ifdef CONFIG_STM32F7_DEBUG_UART
+#define STM32_USART_SR_OFF 0x1C
+#define STM32_USART_TDR_OFF 0x28
+#endif
+
+#define STM32_USART_TC (1 << 6) /* Tx complete */
+#define STM32_USART_TXE (1 << 7) /* Tx data reg empty */
+
+.macro addruart, rp, rv, tmp
+ ldr \rp, =STM32_UART_BASE @ physical base
+ ldr \rv, =STM32_UART_BASE @ virt base /* NoMMU */
+.endm
+
+.macro senduart,rd,rx
+ strb \rd, [\rx, #STM32_USART_TDR_OFF]
+.endm
+
+.macro waituart,rd,rx
+1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
+ tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty
+ beq 1001b
+.endm
+
+.macro busyuart,rd,rx
+1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
+ tst \rd, #STM32_USART_TC @ TC = 1 = tx complete
+ beq 1001b
+.endm
bool "Broadcom BCM63xx DSL SoC"
depends on ARCH_MULTI_V7
depends on MMU
+ select ARCH_HAS_RESET_CONTROLLER
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/init.h>
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014-2015 Broadcom Corporation
* Copyright 2014 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/cpumask.h>
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
*/
extern const struct smp_operations bcm2836_smp_ops;
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_data/ti-aemif.h>
#include <linux/regulator/machine.h>
+#include <linux/nvmem-provider.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static inline void da830_evm_init_lcdc(int mux_mode) { }
#endif
+static struct nvmem_cell_info da830_evm_nvmem_cells[] = {
+ {
+ .name = "macaddr",
+ .offset = 0x7f00,
+ .bytes = ETH_ALEN,
+ }
+};
+
+static struct nvmem_cell_table da830_evm_nvmem_cell_table = {
+ .nvmem_name = "1-00500",
+ .cells = da830_evm_nvmem_cells,
+ .ncells = ARRAY_SIZE(da830_evm_nvmem_cells),
+};
+
+static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = {
+ .nvmem_name = "1-00500",
+ .cell_name = "macaddr",
+ .dev_id = "davinci_emac.1",
+ .con_id = "mac-address",
+};
+
static struct at24_platform_data da830_evm_i2c_eeprom_info = {
.byte_len = SZ_256K / 8,
.page_size = 64,
__func__, ret);
davinci_serial_init(da8xx_serial_device);
+
+ nvmem_add_cell_table(&da830_evm_nvmem_cell_table);
+ nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1);
+
i2c_register_board_info(1, da830_evm_i2c_devices,
ARRAY_SIZE(da830_evm_i2c_devices));
#include <linux/kernel.h>
#include <linux/leds.h>
#include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
#include <linux/platform_data/pca953x.h>
#include <linux/input.h>
#include <linux/input/tps6507x-ts.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
+#include <linux/nvmem-provider.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/platform_data/gpio-davinci.h>
},
};
+static struct nvmem_cell_info da850evm_nvmem_cells[] = {
+ {
+ .name = "macaddr",
+ .offset = 0x0,
+ .bytes = ETH_ALEN,
+ }
+};
+
+static struct nvmem_cell_table da850evm_nvmem_cell_table = {
+ /*
+ * The nvmem name differs from the partition name because of the
+ * internal works of the nvmem framework.
+ */
+ .nvmem_name = "MAC-Address0",
+ .cells = da850evm_nvmem_cells,
+ .ncells = ARRAY_SIZE(da850evm_nvmem_cells),
+};
+
+static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = {
+ .nvmem_name = "MAC-Address0",
+ .cell_name = "macaddr",
+ .dev_id = "davinci_emac.1",
+ .con_id = "mac-address",
+};
+
static struct flash_platform_data da850evm_spiflash_data = {
.name = "m25p80",
.parts = da850evm_spiflash_part,
davinci_serial_init(da8xx_serial_device);
+ nvmem_add_cell_table(&da850evm_nvmem_cell_table);
+ nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1);
+
i2c_register_board_info(1, da850_evm_i2c_devices,
ARRAY_SIZE(da850_evm_i2c_devices));
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
#include <linux/mtd/rawnand.h>
+#include <linux/nvmem-provider.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
.num_resources = ARRAY_SIZE(davinci_aemif_resources),
};
+static struct nvmem_cell_info davinci_nvmem_cells[] = {
+ {
+ .name = "macaddr",
+ .offset = 0x7f00,
+ .bytes = ETH_ALEN,
+ }
+};
+
+static struct nvmem_cell_table davinci_nvmem_cell_table = {
+ .nvmem_name = "1-00500",
+ .cells = davinci_nvmem_cells,
+ .ncells = ARRAY_SIZE(davinci_nvmem_cells),
+};
+
+static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
+ .nvmem_name = "1-00500",
+ .cell_name = "macaddr",
+ .dev_id = "davinci_emac.1",
+ .con_id = "mac-address",
+};
+
static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
+ nvmem_add_cell_table(&davinci_nvmem_cell_table);
+ nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
+
evm_init_i2c();
davinci_serial_init(dm365_serial_device);
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
+#include <linux/nvmem-provider.h>
#include <linux/phy.h>
#include <linux/clk.h>
#include <linux/videodev2.h>
* - ... newer boards may have more
*/
+static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
+ {
+ .name = "macaddr",
+ .offset = 0x7f00,
+ .bytes = ETH_ALEN,
+ }
+};
+
+static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
+ .nvmem_name = "1-00500",
+ .cells = dm644evm_nvmem_cells,
+ .ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
+};
+
+static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
+ .nvmem_name = "1-00500",
+ .cell_name = "macaddr",
+ .dev_id = "davinci_emac.1",
+ .con_id = "mac-address",
+};
+
static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
platform_add_devices(davinci_evm_devices,
ARRAY_SIZE(davinci_evm_devices));
#ifdef CONFIG_I2C
+ nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
+ nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
evm_init_i2c();
davinci_setup_mmc(0, &dm6446evm_mmc_config);
#endif
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
+#include <linux/nvmem-provider.h>
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/platform_data/gpio-davinci.h>
* - ... newer boards may have more
*/
+static struct nvmem_cell_info dm646x_evm_nvmem_cells[] = {
+ {
+ .name = "macaddr",
+ .offset = 0x7f00,
+ .bytes = ETH_ALEN,
+ }
+};
+
+static struct nvmem_cell_table dm646x_evm_nvmem_cell_table = {
+ .nvmem_name = "1-00500",
+ .cells = dm646x_evm_nvmem_cells,
+ .ncells = ARRAY_SIZE(dm646x_evm_nvmem_cells),
+};
+
+static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = {
+ .nvmem_name = "1-00500",
+ .cell_name = "macaddr",
+ .dev_id = "davinci_emac.1",
+ .con_id = "mac-address",
+};
+
static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8,
.page_size = 64,
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
#ifdef CONFIG_I2C
+ nvmem_add_cell_table(&dm646x_evm_nvmem_cell_table);
+ nvmem_add_cell_lookups(&dm646x_evm_nvmem_cell_lookup, 1);
evm_init_i2c();
#endif
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
+#include <linux/nvmem-provider.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
mityomapl138_cpufreq_init(partnum);
}
+/*
+ * We don't define a cell for factory config as it will be accessed from the
+ * board file using the nvmem notifier chain.
+ */
+static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
+ {
+ .name = "macaddr",
+ .offset = 0x64,
+ .bytes = ETH_ALEN,
+ }
+};
+
+static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
+ .nvmem_name = "1-00500",
+ .cells = mityomapl138_nvmem_cells,
+ .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
+};
+
+static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
+ .nvmem_name = "1-00500",
+ .cell_name = "macaddr",
+ .dev_id = "davinci_emac.1",
+ .con_id = "mac-address",
+};
+
static struct at24_platform_data mityomapl138_fd_chip = {
.byte_len = 256,
.page_size = 8,
davinci_serial_init(da8xx_serial_device);
+ nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
+ nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
+
ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
if (ret)
pr_warn("i2c0 registration failed: %d\n", ret);
void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
-extern u32 exynos_get_eint_wake_mask(void);
-
#ifdef CONFIG_PM_SLEEP
extern void __init exynos_pm_init(void);
#else
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
{
- int i;
-
exynos_sysram_init();
exynos_set_delayed_reset_assertion(true);
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_scu_enable();
-
- /*
- * Write the address of secondary startup into the
- * system-wide flags register. The boot monitor waits
- * until it receives a soft interrupt, and then the
- * secondary CPU branches to this address.
- *
- * Try using firmware operation first and fall back to
- * boot register if it fails.
- */
- for (i = 1; i < max_cpus; ++i) {
- unsigned long boot_addr;
- u32 mpidr;
- u32 core_id;
- int ret;
-
- mpidr = cpu_logical_map(i);
- core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- boot_addr = __pa_symbol(exynos4_secondary_startup);
-
- ret = exynos_set_boot_addr(core_id, boot_addr);
- if (ret)
- break;
- }
}
#ifdef CONFIG_HOTPLUG_CPU
#include <asm/smp_scu.h>
#include <asm/suspend.h>
-#include <plat/pm-common.h>
-
#include "common.h"
#define REG_TABLE_END (-1U)
{ /* sentinel */ },
};
+static u32 exynos_read_eint_wakeup_mask(void)
+{
+ return pmu_raw_readl(EXYNOS_EINT_WAKEUP_MASK);
+}
+
static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
const struct exynos_wkup_irq *wkup_irq;
static void exynos_pm_set_wakeup_mask(void)
{
- /* Set wake-up mask registers */
- pmu_raw_writel(exynos_get_eint_wake_mask(), EXYNOS_EINT_WAKEUP_MASK);
+ /*
+ * Set wake-up mask registers
+ * EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
+ */
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
static int exynos_suspend_enter(suspend_state_t state)
{
+ u32 eint_wakeup_mask = exynos_read_eint_wakeup_mask();
int ret;
- s3c_pm_debug_init();
-
- S3C_PMDBG("%s: suspending the system...\n", __func__);
+ pr_debug("%s: suspending the system...\n", __func__);
- S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
- exynos_irqwake_intmask, exynos_get_eint_wake_mask());
+ pr_debug("%s: wakeup masks: %08x,%08x\n", __func__,
+ exynos_irqwake_intmask, eint_wakeup_mask);
if (exynos_irqwake_intmask == -1U
- && exynos_get_eint_wake_mask() == -1U) {
+ && eint_wakeup_mask == EXYNOS_EINT_WAKEUP_MASK_DISABLED) {
pr_err("%s: No wake-up sources!\n", __func__);
pr_err("%s: Aborting sleep\n", __func__);
return -EINVAL;
}
- s3c_pm_save_uarts();
if (pm_data->pm_prepare)
pm_data->pm_prepare();
flush_cache_all();
- s3c_pm_check_store();
ret = call_firmware_op(suspend);
if (ret == -ENOSYS)
if (pm_data->pm_resume_prepare)
pm_data->pm_resume_prepare();
- s3c_pm_restore_uarts();
- S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
+ pr_debug("%s: wakeup stat: %08x\n", __func__,
pmu_raw_readl(S5P_WAKEUP_STAT));
- s3c_pm_check_restore();
-
- S3C_PMDBG("%s: resuming the system...\n", __func__);
+ pr_debug("%s: resuming the system...\n", __func__);
return 0;
}
return ret;
}
- s3c_pm_check_prepare();
-
return 0;
}
{
int ret;
- s3c_pm_check_cleanup();
-
ret = regulator_suspend_finish();
if (ret)
pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
help
This enables support for Freescale i.MX7 Dual processor.
+config SOC_IMX7ULP
+ bool "i.MX7ULP support"
+ select CLKSRC_IMX_TPM
+ select PINCTRL_IMX7ULP
+ select SOC_IMX7D_CA7 if ARCH_MULTI_V7
+ select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
+ help
+ This enables support for Freescale i.MX7 Ultra Low Power processor.
+
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
void imx6sl_pm_init(void);
void imx6sx_pm_init(void);
void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
#ifdef CONFIG_PM
void imx51_pm_init(void);
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
+ case MXC_CPU_IMX7ULP:
+ soc_id = "i.MX7ULP";
+ break;
default:
soc_id = "Unknown";
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+ imx7ulp_pm_init();
+
+ mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+ of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+ "fsl,imx7ulp",
+ NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+ .init_machine = imx7ulp_init_machine,
+ .dt_compat = imx7ulp_dt_compat,
+MACHINE_END
#define MXC_CPU_IMX6ULZ 0x6b
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
+#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL 0x10
+#define BP_PMCTRL_PSTOPO 16
+#define PSTOPO_PSTOP3 0x3
+
+void __init imx7ulp_pm_init(void)
+{
+ struct device_node *np;
+ void __iomem *smc1_base;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+ smc1_base = of_iomap(np, 0);
+ WARN_ON(!smc1_base);
+
+ /* Partial Stop mode 3 with system/bus clock enabled */
+ writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
+ smc1_base + SMC_PMCTRL);
+ iounmap(smc1_base);
+}
},
};
-static void acs5k_i2c_init(void)
+static void __init acs5k_i2c_init(void)
{
/* The gpio interface */
gpiod_add_lookup_table(&acs5k_i2c_gpiod_table);
select GPIOLIB
select GENERIC_IRQ_CHIP
select ARM_GIC
+ select ARM_GLOBAL_TIMER
select CACHE_L2X0
select PINCTRL
select PINCTRL_MESON
select COMMON_CLK
select COMMON_CLK_AMLOGIC
select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
if ARCH_MESON
#include "addr-map.h"
#include "mfp-pxa168.h"
#include "pxa168.h"
+#include "pxa910.h"
#include "irqs.h"
#include "common.h"
/* off-chip devices */
platform_device_register(&smc91x_device);
+#if IS_ENABLED(CONFIG_USB_SUPPORT)
+#if IS_ENABLED(CONFIG_PHY_PXA_USB)
+ platform_device_register(&pxa168_device_usb_phy);
+#endif
+
#if IS_ENABLED(CONFIG_USB_EHCI_MV)
pxa168_add_usb_host(&pxa168_sph_pdata);
#endif
+#endif
}
MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
#include <linux/reboot.h>
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
-extern void timer_init(int irq);
+extern void mmp_timer_init(int irq, unsigned long rate);
extern void __init mmp_map_io(void);
extern void mmp_restart(enum reboot_mode, const char *);
#if IS_ENABLED(CONFIG_USB_SUPPORT)
static u64 __maybe_unused usb_dma_mask = ~(u32)0;
+#if IS_ENABLED(CONFIG_PHY_PXA_USB)
+struct resource pxa168_usb_phy_resources[] = {
+ [0] = {
+ .start = PXA168_U2O_PHYBASE,
+ .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device pxa168_device_usb_phy = {
+ .name = "pxa-usb-phy",
+ .id = -1,
+ .resource = pxa168_usb_phy_resources,
+ .num_resources = ARRAY_SIZE(pxa168_usb_phy_resources),
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ }
+};
+#endif /* CONFIG_PHY_PXA_USB */
+
#if IS_ENABLED(CONFIG_USB_MV_UDC)
struct resource pxa168_u2o_resources[] = {
/* regbase */
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
- mmp_dt_init_timer();
of_clk_init(NULL);
+ mmp_dt_init_timer();
}
static const char *const mmp2_dt_board_compat[] __initconst = {
clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
__raw_writel(clk_rst, APBC_TIMERS);
- timer_init(IRQ_MMP2_TIMER1);
+ mmp_timer_init(IRQ_MMP2_TIMER1, 6500000);
}
/* on-chip devices */
/* 3.25MHz, bus/functional clock enabled, release reset */
__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
- timer_init(IRQ_PXA168_TIMER1);
+ mmp_timer_init(IRQ_PXA168_TIMER1, 3250000);
}
void pxa168_clear_keypad_wakeup(void)
__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
- timer_init(IRQ_PXA910_AP1_TIMER1);
+ mmp_timer_init(IRQ_PXA910_AP1_TIMER1, 3250000);
}
/* on-chip devices */
extern struct pxa_device_desc pxa910_device_pwm3;
extern struct pxa_device_desc pxa910_device_pwm4;
extern struct pxa_device_desc pxa910_device_nand;
+extern struct platform_device pxa168_device_usb_phy;
extern struct platform_device pxa168_device_u2o;
extern struct platform_device pxa168_device_u2ootg;
extern struct platform_device pxa168_device_u2oehci;
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include "cputype.h"
#include "clock.h"
-#ifdef CONFIG_CPU_MMP2
-#define MMP_CLOCK_FREQ 6500000
-#else
-#define MMP_CLOCK_FREQ 3250000
-#endif
-
#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
#define MAX_DELTA (0xfffffffe)
.dev_id = &ckevt,
};
-void __init timer_init(int irq)
+void __init mmp_timer_init(int irq, unsigned long rate)
{
timer_config();
- sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
+ sched_clock_register(mmp_read_sched_clock, 32, rate);
ckevt.cpumask = cpumask_of(0);
setup_irq(irq, &timer_irq);
- clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
- clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
- MIN_DELTA, MAX_DELTA);
+ clocksource_register_hz(&cksrc, rate);
+ clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
}
#ifdef CONFIG_OF
void __init mmp_dt_init_timer(void)
{
struct device_node *np;
+ struct clk *clk;
int irq, ret;
+ unsigned long rate;
np = of_find_matching_node(NULL, mmp_timer_dt_ids);
if (!np) {
goto out;
}
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ goto out;
+ rate = clk_get_rate(clk) / 2;
+ } else if (cpu_is_pj4()) {
+ rate = 6500000;
+ } else {
+ rate = 3250000;
+ }
+
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
ret = -EINVAL;
ret = -ENOMEM;
goto out;
}
- timer_init(irq);
+ mmp_timer_init(irq, rate);
return;
out:
pr_err("Failed to get timer from device tree with error:%d\n", ret);
sizeof(struct pxa_gpio_platform_data));
platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
+#if IS_ENABLED(CONFIG_USB_SUPPORT)
+#if IS_ENABLED(CONFIG_PHY_PXA_USB)
+ platform_device_register(&pxa168_device_usb_phy);
+#endif
+
#if IS_ENABLED(CONFIG_USB_MV_UDC)
pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2o);
pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2ootg);
#endif
+#endif
#if IS_ENABLED(CONFIG_MMP_DISP)
add_disp();
led-y := leds.o
-usb-fs-$(CONFIG_USB) := usb.o
+usb-fs-$(CONFIG_USB_SUPPORT) := usb.o
obj-y += $(usb-fs-m) $(usb-fs-y)
# Specific board support
#include <linux/platform_data/gpio-omap.h>
#include <asm/assembler.h>
-#include <mach/board-ams-delta.h>
#include "ams-delta-fiq.h"
+#include "board-ams-delta.h"
#include "iomap.h"
#include "soc.h"
#include <linux/platform_data/ams-delta-fiq.h>
#include <linux/platform_device.h>
-#include <mach/board-ams-delta.h>
-
#include <asm/fiq.h>
#include "ams-delta-fiq.h"
+#include "board-ams-delta.h"
static struct fiq_handler fh = {
.name = "ams-delta-fiq"
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/board-ams-delta.h>
#include <linux/platform_data/keypad-omap.h>
#include <mach/mux.h>
#include <mach/usb.h>
#include "ams-delta-fiq.h"
+#include "board-ams-delta.h"
#include "iomap.h"
#include "common.h"
.pins[0] = 2,
};
-#define LATCH1_GPIO_BASE 232
#define LATCH1_NGPIO 8
static struct resource latch1_resources[] = {
static struct bgpio_pdata latch1_pdata = {
.label = LATCH1_LABEL,
- .base = LATCH1_GPIO_BASE,
.ngpio = LATCH1_NGPIO,
};
#define LATCH1_PIN_DOCKIT1 6
#define LATCH1_PIN_DOCKIT2 7
+#define LATCH2_NGPIO 16
+
static struct resource latch2_resources[] = {
[0] = {
.name = "dat",
.start = LATCH2_PHYS,
- .end = LATCH2_PHYS + (AMS_DELTA_LATCH2_NGPIO - 1) / 8,
+ .end = LATCH2_PHYS + (LATCH2_NGPIO - 1) / 8,
.flags = IORESOURCE_MEM,
},
};
static struct bgpio_pdata latch2_pdata = {
.label = LATCH2_LABEL,
- .base = AMS_DELTA_LATCH2_GPIO_BASE,
- .ngpio = AMS_DELTA_LATCH2_NGPIO,
+ .ngpio = LATCH2_NGPIO,
};
static struct platform_device latch2_gpio_device = {
},
};
-/*
- * Dynamically allocated GPIO numbers must be obtained fromm GPIO device
- * before they can be put in the gpio_led table. Before that happens,
- * initialize the table with invalid GPIO numbers, not 0.
- */
static struct gpio_led gpio_leds[] __initdata = {
[LATCH1_PIN_LED_CAMERA] = {
.name = "camera",
- .gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
#ifdef CONFIG_LEDS_TRIGGERS
.default_trigger = "ams_delta_camera",
},
[LATCH1_PIN_LED_ADVERT] = {
.name = "advert",
- .gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_MAIL] = {
.name = "email",
- .gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_HANDSFREE] = {
.name = "handsfree",
- .gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_VOICEMAIL] = {
.name = "voicemail",
- .gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
[LATCH1_PIN_LED_VOICE] = {
.name = "voice",
- .gpio = -EINVAL,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
};
.num_leds = ARRAY_SIZE(gpio_leds),
};
+static struct gpiod_lookup_table leds_gpio_table = {
+ .table = {
+ GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_CAMERA, NULL,
+ LATCH1_PIN_LED_CAMERA, 0),
+ GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_ADVERT, NULL,
+ LATCH1_PIN_LED_ADVERT, 0),
+ GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_MAIL, NULL,
+ LATCH1_PIN_LED_MAIL, 0),
+ GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_HANDSFREE, NULL,
+ LATCH1_PIN_LED_HANDSFREE, 0),
+ GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_VOICEMAIL, NULL,
+ LATCH1_PIN_LED_VOICEMAIL, 0),
+ GPIO_LOOKUP_IDX(LATCH1_LABEL, LATCH1_PIN_LED_VOICE, NULL,
+ LATCH1_PIN_LED_VOICE, 0),
+ { },
+ },
+};
+
static struct i2c_board_info ams_delta_camera_board_info[] = {
{
I2C_BOARD_INFO("ov6650", 0x60),
static void __init ams_delta_init(void)
{
+ struct platform_device *leds_pdev;
+
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
gpiod_add_lookup_tables(ams_delta_gpio_tables,
ARRAY_SIZE(ams_delta_gpio_tables));
+ leds_pdev = gpio_led_register_device(PLATFORM_DEVID_NONE, &leds_pdata);
+ if (!IS_ERR(leds_pdev)) {
+ leds_gpio_table.dev_id = dev_name(&leds_pdev->dev);
+ gpiod_add_lookup_table(&leds_gpio_table);
+ }
+
omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
omapfb_set_lcd_config(&ams_delta_lcd_config);
},
};
-/*
- * leds-gpio driver doesn't make use of GPIO lookup tables,
- * it has to be provided with GPIO numbers over platform data
- * if GPIO descriptor info can't be obtained from device tree.
- * We could either define GPIO lookup tables and use them on behalf
- * of the leds-gpio device, or we can use GPIO driver level methods
- * for identification of GPIO numbers as long as we don't support
- * device tree. Let's do the latter.
- */
-static void __init ams_delta_led_init(struct gpio_chip *chip)
-{
- struct gpio_desc *gpiod;
- int i;
-
- for (i = LATCH1_PIN_LED_CAMERA; i < LATCH1_PIN_DOCKIT1; i++) {
- gpiod = gpiochip_request_own_desc(chip, i, NULL);
- if (IS_ERR(gpiod)) {
- pr_warn("%s: %s GPIO %d request failed (%ld)\n",
- __func__, LATCH1_LABEL, i, PTR_ERR(gpiod));
- continue;
- }
-
- /* Assign GPIO numbers to LED device. */
- gpio_leds[i].gpio = desc_to_gpio(gpiod);
-
- gpiochip_free_own_desc(gpiod);
- }
-
- gpio_led_register_device(PLATFORM_DEVID_NONE, &leds_pdata);
-}
-
-/*
- * The purpose of this function is to take care of assignment of GPIO numbers
- * to platform devices which depend on GPIO lines provided by Amstrad Delta
- * latch1 and/or latch2 GPIO devices but don't use GPIO lookup tables.
- * The function may be called as soon as latch1/latch2 GPIO devices are
- * initilized. Since basic-mmio-gpio driver is not registered before
- * device_initcall, this may happen at erliest during device_initcall_sync.
- * Dependent devices shouldn't be registered before that, their
- * registration may be performed from within this function or later.
- */
-static int __init ams_delta_gpio_init(void)
-{
- struct gpio_chip *chip;
-
- if (!machine_is_ams_delta())
- return -ENODEV;
-
- chip = gpiochip_find(LATCH1_LABEL, gpiochip_match_by_label);
- if (!chip)
- pr_err("%s: latch1 GPIO chip not found\n", __func__);
- else
- ams_delta_led_init(chip);
-
- return 0;
-}
-device_initcall_sync(ams_delta_gpio_init);
-
static int __init modem_nreset_init(void)
{
int err;
/*
- * arch/arm/plat-omap/include/mach/board-ams-delta.h
+ * arch/arm/mach-omap1/board-ams-delta.h
*
* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
*
#if defined (CONFIG_MACH_AMS_DELTA)
-#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
-#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
-#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
-
#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
#define AMS_DELTA_GPIO_PIN_CONFIG 11
#define AMS_DELTA_GPIO_PIN_NAND_RB 12
-#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
-#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
-#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
-#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
-#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
-#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
-#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
-#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
-#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
-#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
-#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
-#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
-#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
-#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
-
-#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
-#define AMS_DELTA_LATCH2_NGPIO 16
-
#endif /* CONFIG_MACH_AMS_DELTA */
#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
#include <mach/hardware.h>
#include <mach/usb.h>
+#include "mmc.h"
#include "common.h"
#define PALMTE_USBDETECT_GPIO 0
gpio_direction_input(PALMTE_USB_OR_DC_GPIO);
}
+#if IS_ENABLED(CONFIG_MMC_OMAP)
+
+static struct omap_mmc_platform_data _palmte_mmc_config = {
+ .nr_slots = 1,
+ .slots[0] = {
+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+ .name = "mmcblk",
+ },
+};
+
+static struct omap_mmc_platform_data *palmte_mmc_config[OMAP15XX_NR_MMC] = {
+ [0] = &_palmte_mmc_config,
+};
+
+static void palmte_mmc_init(void)
+{
+ omap1_init_mmc(palmte_mmc_config, OMAP15XX_NR_MMC);
+}
+
+#else /* CONFIG_MMC_OMAP */
+
+static void palmte_mmc_init(void)
+{
+}
+
+#endif /* CONFIG_MMC_OMAP */
+
static void __init omap_palmte_init(void)
{
/* mux pins for uarts */
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&palmte_lcd_config);
+ palmte_mmc_init();
}
MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
static struct dentry *clk_debugfs_root;
-static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+static int debug_clock_show(struct seq_file *s, void *unused)
{
struct clk *c;
struct clk *pa;
return 0;
}
-static int clk_dbg_open(struct inode *inode, struct file *file)
-{
- return single_open(file, clk_dbg_show_summary, inode->i_private);
-}
-
-static const struct file_operations debug_clock_fops = {
- .open = clk_dbg_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(debug_clock);
static int clk_debugfs_register_one(struct clk *c)
{
static void omap_init_spi100k(void)
{
+ if (!cpu_is_omap7xx())
+ return;
+
omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
if (omap_spi1.dev.platform_data)
platform_device_register(&omap_spi1);
printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type);
}
- printk(KERN_INFO "OMAP%04x", omap_revision >> 16);
+ pr_info("OMAP%04x", omap_revision >> 16);
if ((omap_revision >> 8) & 0xff)
- printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff);
- printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n",
+ pr_cont("%x", (omap_revision >> 8) & 0xff);
+ pr_cont(" revision %i handled as %02xxx id: %08x%08x\n",
die_rev, omap_revision & 0xff, system_serial_low,
system_serial_high);
}
#include <linux/platform_data/usb-omap1.h>
-#if IS_ENABLED(CONFIG_USB)
+#if IS_ENABLED(CONFIG_USB_SUPPORT)
void omap1_usb_init(struct omap_usb_config *pdata);
#else
static inline void omap1_usb_init(struct omap_usb_config *pdata)
return 0;
}
-static int omap_pm_debug_open(struct inode *inode, struct file *file)
-{
- return single_open(file, omap_pm_debug_show,
- &inode->i_private);
-}
-
-static const struct file_operations omap_pm_debug_fops = {
- .open = omap_pm_debug_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(omap_pm_debug);
static void omap_pm_init_debugfs(void)
{
pr_info("%s", soc_name);
if ((omap_rev() >> 8) & 0x0f)
- pr_info("%s", soc_rev);
- pr_info("\n");
+ pr_cont("%s", soc_rev);
+ pr_cont("\n");
}
#define OMAP3_SHOW_FEATURE(feat) \
* a stub; implementing this properly requires iclk autoidle usecounting in
* the clock code. No return value.
*/
-static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
+static void _setup_iclk_autoidle(struct omap_hwmod *oh)
{
struct omap_hwmod_ocp_if *os;
* reset. Returns 0 upon success or a negative error code upon
* failure.
*/
-static int __init _setup_reset(struct omap_hwmod *oh)
+static int _setup_reset(struct omap_hwmod *oh)
{
int r;
*
* No return value.
*/
-static void __init _setup_postsetup(struct omap_hwmod *oh)
+static void _setup_postsetup(struct omap_hwmod *oh)
{
u8 postsetup_state;
static void __iomem *scu_base;
static struct omap_hwmod *rtc_oh;
-static int __init am43xx_map_scu(void)
+static int am43xx_map_scu(void)
{
scu_base = ioremap(scu_a9_get_base(), SZ_256);
#include <linux/sched_clock.h>
#include <asm/mach/time.h>
-#include <asm/smp_twd.h>
#include "omap_hwmod.h"
#include "omap_device.h"
.exit = cm_x300_u2d_exit,
};
-static void cm_x300_init_u2d(void)
+static void __init cm_x300_init_u2d(void)
{
pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
}
.lcd_conn = LCD_COLOR_TFT_16BPP,
};
-static void littleton_init_lcd(void)
+static void __init littleton_init_lcd(void)
{
pxa_set_fb_info(NULL, &littleton_lcd_info);
}
.flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
};
-static void zeus_register_ohci(void)
+static void __init zeus_register_ohci(void)
{
/* Port 2 is shared between host and client interface. */
UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
#define __ARCH_ARM_MACH_S5PV210_COMMON_H
#ifdef CONFIG_PM_SLEEP
-u32 exynos_get_eint_wake_mask(void);
void s5pv210_cpu_resume(void);
void s5pv210_pm_init(void);
#else
*/
static u32 s5pv210_irqwake_intmask = 0xffffffff;
+static u32 s5pv210_read_eint_wakeup_mask(void)
+{
+ return __raw_readl(S5P_EINT_WAKEUP_MASK);
+}
+
/*
* Suspend helpers.
*/
{
unsigned int tmp;
- /* Set wake-up mask registers */
- __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+ /*
+ * Set wake-up mask registers
+ * S5P_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
+ */
__raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
/* ensure at least INFORM0 has the resume address */
*/
static int s5pv210_suspend_enter(suspend_state_t state)
{
+ u32 eint_wakeup_mask = s5pv210_read_eint_wakeup_mask();
int ret;
s3c_pm_debug_init();
S3C_PMDBG("%s: suspending the system...\n", __func__);
S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
- s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
+ s5pv210_irqwake_intmask, eint_wakeup_mask);
if (s5pv210_irqwake_intmask == -1U
- && exynos_get_eint_wake_mask() == -1U) {
+ && eint_wakeup_mask == -1U) {
pr_err("%s: No wake-up sources!\n", __func__);
pr_err("%s: Aborting sleep\n", __func__);
return -EINVAL;
# SPDX-License-Identifier: GPL-2.0
-config PM_RMOBILE
- bool
- select PM
- select PM_GENERIC_DOMAINS
-
-config ARCH_RCAR_GEN1
- bool
- select PM
- select PM_GENERIC_DOMAINS
- select RENESAS_INTC_IRQPIN
- select SYS_SUPPORTS_SH_TMU
-
-config ARCH_RCAR_GEN2
- bool
- select HAVE_ARM_ARCH_TIMER
- select PM
- select PM_GENERIC_DOMAINS
- select RENESAS_IRQC
- select SYS_SUPPORTS_SH_CMT
-
-config ARCH_RMOBILE
- bool
- select PM_RMOBILE
- select SYS_SUPPORTS_SH_CMT
- select SYS_SUPPORTS_SH_TMU
-
menuconfig ARCH_RENESAS
bool "Renesas ARM SoCs"
depends on ARCH_MULTI_V7 && MMU
select ARM_GIC
select GPIOLIB
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
select NO_IOPORT_MAP
select PINCTRL
select SOC_BUS
select ZONE_DMA if ARM_LPAE
-
-if ARCH_RENESAS
-
-#comment "Renesas ARM SoCs System Type"
-
-config ARCH_EMEV2
- bool "Emma Mobile EV2"
- select SYS_SUPPORTS_EM_STI
-
-config ARCH_R7S72100
- bool "RZ/A1H (R7S72100)"
- select PM
- select PM_GENERIC_DOMAINS
- select SYS_SUPPORTS_SH_MTU2
- select RENESAS_OSTM
-
-config ARCH_R7S9210
- bool "RZ/A2 (R7S9210)"
- select PM
- select PM_GENERIC_DOMAINS
- select RENESAS_OSTM
-
-config ARCH_R8A73A4
- bool "R-Mobile APE6 (R8A73A40)"
- select ARCH_RMOBILE
- select ARM_ERRATA_798181 if SMP
- select HAVE_ARM_ARCH_TIMER
- select RENESAS_IRQC
-
-config ARCH_R8A7740
- bool "R-Mobile A1 (R8A77400)"
- select ARCH_RMOBILE
- select RENESAS_INTC_IRQPIN
-
-config ARCH_R8A7743
- bool "RZ/G1M (R8A77430)"
- select ARCH_RCAR_GEN2
- select ARM_ERRATA_798181 if SMP
-
-config ARCH_R8A7744
- bool "RZ/G1N (R8A77440)"
- select ARCH_RCAR_GEN2
- select ARM_ERRATA_798181 if SMP
-
-config ARCH_R8A7745
- bool "RZ/G1E (R8A77450)"
- select ARCH_RCAR_GEN2
-
-config ARCH_R8A77470
- bool "RZ/G1C (R8A77470)"
- select ARCH_RCAR_GEN2
-
-config ARCH_R8A7778
- bool "R-Car M1A (R8A77781)"
- select ARCH_RCAR_GEN1
-
-config ARCH_R8A7779
- bool "R-Car H1 (R8A77790)"
- select ARCH_RCAR_GEN1
-
-config ARCH_R8A7790
- bool "R-Car H2 (R8A77900)"
- select ARCH_RCAR_GEN2
- select ARM_ERRATA_798181 if SMP
- select I2C
-
-config ARCH_R8A7791
- bool "R-Car M2-W (R8A77910)"
- select ARCH_RCAR_GEN2
- select ARM_ERRATA_798181 if SMP
- select I2C
-
-config ARCH_R8A7792
- bool "R-Car V2H (R8A77920)"
- select ARCH_RCAR_GEN2
- select ARM_ERRATA_798181 if SMP
-
-config ARCH_R8A7793
- bool "R-Car M2-N (R8A7793)"
- select ARCH_RCAR_GEN2
- select ARM_ERRATA_798181 if SMP
- select I2C
-
-config ARCH_R8A7794
- bool "R-Car E2 (R8A77940)"
- select ARCH_RCAR_GEN2
-
-config ARCH_R9A06G032
- bool "RZ/N1D (R9A06G032)"
- select ARCH_RZN1
-
-config ARCH_RZN1
- bool "RZ/N1 (R9A06G0xx) Family"
- select ARM_AMBA
- select CPU_V7
-
-config ARCH_SH73A0
- bool "SH-Mobile AG5 (R8A73A00)"
- select ARCH_RMOBILE
- select RENESAS_INTC_IRQPIN
-endif
# PM objects
obj-$(CONFIG_SUSPEND) += suspend.o
-obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
# Framework support
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- */
-#ifndef PM_RMOBILE_H
-#define PM_RMOBILE_H
-
-#include <linux/pm_domain.h>
-
-struct rmobile_pm_domain {
- struct generic_pm_domain genpd;
- struct dev_power_governor *gov;
- int (*suspend)(void);
- void (*resume)(void);
- void __iomem *base;
- unsigned int bit_shift;
- bool no_debug;
-};
-
-#endif /* PM_RMOBILE_H */
#include <linux/delay.h>
#include <asm/smp_plat.h>
-#include <asm/smp_twd.h>
#include "common.h"
#include "sh73a0.h"
select HAVE_ARM_TWD if SMP
select MFD_SYSCON
select PCI_DOMAINS if PCI
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369 if SMP
+ select ARM_ERRATA_775420
+ select PL310_ERRATA_588369
+ select PL310_ERRATA_727915
+ select PL310_ERRATA_753970 if PL310
+ select PL310_ERRATA_769419
if ARCH_SOCFPGA
config SOCFPGA_SUSPEND
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
-extern void socfpga_init_clocks(void);
-extern void socfpga_sysmgr_init(void);
void socfpga_init_l2_ecc(void);
void socfpga_init_ocram_ecc(void);
void socfpga_init_arria10_l2_ecc(void);
void __iomem *sdr_ctl_base_addr;
unsigned long socfpga_cpu1start_addr;
-void __init socfpga_sysmgr_init(void)
+static void __init socfpga_sysmgr_init(void)
{
struct device_node *np;
menuconfig ARCH_SUNXI
bool "Allwinner SoCs"
- depends on ARCH_MULTI_V7
+ depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select PM_OPP
select SUN4I_TIMER
select RESET_CONTROLLER
+ help
+ Support for Allwinner ARM-based family of processors
if ARCH_SUNXI
+if ARCH_MULTI_V7
+
config MACH_SUN4I
bool "Allwinner A10 (sun4i) SoCs support"
default ARCH_SUNXI
select ARM_CPU_SUSPEND
endif
+
+if ARCH_MULTI_V5
+
+config MACH_SUNIV
+ bool "Allwinner ARMv5 F-series (suniv) SoCs support"
+ default ARCH_SUNXI
+ help
+ Support for Allwinner suniv ARMv5 SoCs.
+ (F1C100A, F1C100s, F1C200s, F1C500, F1C600)
+
+endif
+
+endif
DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
.dt_compat = sun9i_board_dt_compat,
MACHINE_END
+
+static const char * const suniv_board_dt_compat[] = {
+ "allwinner,suniv-f1c100s",
+ NULL,
+};
+
+DT_MACHINE_START(SUNIV_DT, "Allwinner suniv Family")
+ .dt_compat = suniv_board_dt_compat,
+MACHINE_END
{ }
};
-static void tegra114_gic_cpu_pm_registration(void)
+static void __init tegra114_gic_cpu_pm_registration(void)
{
struct device_node *dn;
cpu_pm_register_notifier(&tegra_gic_notifier_block);
}
#else
-static void tegra114_gic_cpu_pm_registration(void) { }
+static void __init tegra114_gic_cpu_pm_registration(void) { }
#endif
static const struct of_device_id tegra_ictlr_match[] __initconst = {
config SAMSUNG_PM_DEBUG
bool "Samsung PM Suspend debug"
depends on PM && DEBUG_KERNEL
+ depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART
help
Say Y here if you want verbose debugging from the PM Suspend and
config ARCH_RENESAS
bool "Renesas SoC Platforms"
+ select GPIOLIB
select PINCTRL
- select PM
- select PM_GENERIC_DOMAINS
- select RENESAS_IRQC
select SOC_BUS
- select SYS_SUPPORTS_SH_CMT
- select SYS_SUPPORTS_SH_TMU
help
This enables support for the ARMv8 based Renesas SoCs.
-config ARCH_R8A774A1
- bool "Renesas RZ/G2M SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas RZ/G2M SoC.
-
-config ARCH_R8A774C0
- bool "Renesas RZ/G2E SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas RZ/G2E SoC.
-
-config ARCH_R8A7795
- bool "Renesas R-Car H3 SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car H3 SoC.
-
-config ARCH_R8A7796
- bool "Renesas R-Car M3-W SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car M3-W SoC.
-
-config ARCH_R8A77965
- bool "Renesas R-Car M3-N SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car M3-N SoC.
-
-config ARCH_R8A77970
- bool "Renesas R-Car V3M SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car V3M SoC.
-
-config ARCH_R8A77980
- bool "Renesas R-Car V3H SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car V3H SoC.
-
-config ARCH_R8A77990
- bool "Renesas R-Car E3 SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car E3 SoC.
-
-config ARCH_R8A77995
- bool "Renesas R-Car D3 SoC Platform"
- depends on ARCH_RENESAS
- help
- This enables support for the Renesas R-Car D3 SoC.
-
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
- select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
- ARCH_R8A774A1 || ARCH_R8A774C0 || ARCH_R8A7795 || \
- ARCH_R8A7796 || ARCH_R8A77965 || ARCH_R8A77970 || \
- ARCH_R8A77980 || ARCH_R8A77990 || ARCH_R8A77995
- select SYSC_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
- select SYSC_R8A7745 if ARCH_R8A7745
- select SYSC_R8A77470 if ARCH_R8A77470
- select SYSC_R8A774A1 if ARCH_R8A774A1
- select SYSC_R8A774C0 if ARCH_R8A774C0
- select SYSC_R8A7779 if ARCH_R8A7779
- select SYSC_R8A7790 if ARCH_R8A7790
- select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
- select SYSC_R8A7792 if ARCH_R8A7792
- select SYSC_R8A7794 if ARCH_R8A7794
- select SYSC_R8A7795 if ARCH_R8A7795
- select SYSC_R8A7796 if ARCH_R8A7796
- select SYSC_R8A77965 if ARCH_R8A77965
- select SYSC_R8A77970 if ARCH_R8A77970
- select SYSC_R8A77980 if ARCH_R8A77980
- select SYSC_R8A77990 if ARCH_R8A77990
- select SYSC_R8A77995 if ARCH_R8A77995
if SOC_RENESAS
+config ARCH_RCAR_GEN1
+ bool
+ select PM
+ select PM_GENERIC_DOMAINS
+ select RENESAS_INTC_IRQPIN
+ select RST_RCAR
+ select SYS_SUPPORTS_SH_TMU
+
+config ARCH_RCAR_GEN2
+ bool
+ select HAVE_ARM_ARCH_TIMER
+ select PM
+ select PM_GENERIC_DOMAINS
+ select RENESAS_IRQC
+ select RST_RCAR
+ select SYS_SUPPORTS_SH_CMT
+
+config ARCH_RCAR_GEN3
+ bool
+ select PM
+ select PM_GENERIC_DOMAINS
+ select RENESAS_IRQC
+ select RST_RCAR
+ select SYS_SUPPORTS_SH_CMT
+ select SYS_SUPPORTS_SH_TMU
+
+config ARCH_RMOBILE
+ bool
+ select PM
+ select PM_GENERIC_DOMAINS
+ select SYS_SUPPORTS_SH_CMT
+ select SYS_SUPPORTS_SH_TMU
+ select SYSC_RMOBILE
+
+config ARCH_RZN1
+ bool
+ select ARM_AMBA
+
+if ARM
+
+#comment "Renesas ARM SoCs System Type"
+
+config ARCH_EMEV2
+ bool "Emma Mobile EV2"
+ select HAVE_ARM_SCU if SMP
+ select SYS_SUPPORTS_EM_STI
+
+config ARCH_R7S72100
+ bool "RZ/A1H (R7S72100)"
+ select PM
+ select PM_GENERIC_DOMAINS
+ select SYS_SUPPORTS_SH_MTU2
+ select RENESAS_OSTM
+
+config ARCH_R7S9210
+ bool "RZ/A2 (R7S9210)"
+ select PM
+ select PM_GENERIC_DOMAINS
+ select RENESAS_OSTM
+
+config ARCH_R8A73A4
+ bool "R-Mobile APE6 (R8A73A40)"
+ select ARCH_RMOBILE
+ select ARM_ERRATA_798181 if SMP
+ select HAVE_ARM_ARCH_TIMER
+ select RENESAS_IRQC
+
+config ARCH_R8A7740
+ bool "R-Mobile A1 (R8A77400)"
+ select ARCH_RMOBILE
+ select RENESAS_INTC_IRQPIN
+
+config ARCH_R8A7743
+ bool "RZ/G1M (R8A77430)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select SYSC_R8A7743
+
+config ARCH_R8A7744
+ bool "RZ/G1N (R8A77440)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select SYSC_R8A7743
+
+config ARCH_R8A7745
+ bool "RZ/G1E (R8A77450)"
+ select ARCH_RCAR_GEN2
+ select SYSC_R8A7745
+
+config ARCH_R8A77470
+ bool "RZ/G1C (R8A77470)"
+ select ARCH_RCAR_GEN2
+ select SYSC_R8A77470
+
+config ARCH_R8A7778
+ bool "R-Car M1A (R8A77781)"
+ select ARCH_RCAR_GEN1
+
+config ARCH_R8A7779
+ bool "R-Car H1 (R8A77790)"
+ select ARCH_RCAR_GEN1
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select SYSC_R8A7779
+
+config ARCH_R8A7790
+ bool "R-Car H2 (R8A77900)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select I2C
+ select SYSC_R8A7790
+
+config ARCH_R8A7791
+ bool "R-Car M2-W (R8A77910)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select I2C
+ select SYSC_R8A7791
+
+config ARCH_R8A7792
+ bool "R-Car V2H (R8A77920)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select SYSC_R8A7792
+
+config ARCH_R8A7793
+ bool "R-Car M2-N (R8A7793)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select I2C
+ select SYSC_R8A7791
+
+config ARCH_R8A7794
+ bool "R-Car E2 (R8A77940)"
+ select ARCH_RCAR_GEN2
+ select SYSC_R8A7794
+
+config ARCH_R9A06G032
+ bool "RZ/N1D (R9A06G032)"
+ select ARCH_RZN1
+
+config ARCH_SH73A0
+ bool "SH-Mobile AG5 (R8A73A00)"
+ select ARCH_RMOBILE
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select RENESAS_INTC_IRQPIN
+
+endif # ARM
+
+if ARM64
+
+config ARCH_R8A774A1
+ bool "Renesas RZ/G2M SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A774A1
+ help
+ This enables support for the Renesas RZ/G2M SoC.
+
+config ARCH_R8A774C0
+ bool "Renesas RZ/G2E SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A774C0
+ help
+ This enables support for the Renesas RZ/G2E SoC.
+
+config ARCH_R8A7795
+ bool "Renesas R-Car H3 SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A7795
+ help
+ This enables support for the Renesas R-Car H3 SoC.
+
+config ARCH_R8A7796
+ bool "Renesas R-Car M3-W SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A7796
+ help
+ This enables support for the Renesas R-Car M3-W SoC.
+
+config ARCH_R8A77965
+ bool "Renesas R-Car M3-N SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A77965
+ help
+ This enables support for the Renesas R-Car M3-N SoC.
+
+config ARCH_R8A77970
+ bool "Renesas R-Car V3M SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A77970
+ help
+ This enables support for the Renesas R-Car V3M SoC.
+
+config ARCH_R8A77980
+ bool "Renesas R-Car V3H SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A77980
+ help
+ This enables support for the Renesas R-Car V3H SoC.
+
+config ARCH_R8A77990
+ bool "Renesas R-Car E3 SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A77990
+ help
+ This enables support for the Renesas R-Car E3 SoC.
+
+config ARCH_R8A77995
+ bool "Renesas R-Car D3 SoC Platform"
+ select ARCH_RCAR_GEN3
+ select SYSC_R8A77995
+ help
+ This enables support for the Renesas R-Car D3 SoC.
+
+endif # ARM64
+
# SoC
config SYSC_R8A7743
bool "RZ/G1M System Controller support" if COMPILE_TEST
config SYSC_RCAR
bool "R-Car System Controller support" if COMPILE_TEST
+config SYSC_RMOBILE
+ bool "R-Mobile System Controller support" if COMPILE_TEST
+
endif # SOC_RENESAS
# Family
obj-$(CONFIG_RST_RCAR) += rcar-rst.o
obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o
+obj-$(CONFIG_SYSC_RMOBILE) += rmobile-sysc.o
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <asm/io.h>
-#include "pm-rmobile.h"
-
/* SYSC */
#define SPDCR 0x08 /* SYS Power Down Control Register */
#define SWUCR 0x14 /* SYS Wakeup Control Register */
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
+struct rmobile_pm_domain {
+ struct generic_pm_domain genpd;
+ struct dev_power_governor *gov;
+ int (*suspend)(void);
+ void __iomem *base;
+ unsigned int bit_shift;
+};
+
static inline
struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
{
}
}
- if (!rmobile_pd->no_debug)
- pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
- genpd->name, mask,
- __raw_readl(rmobile_pd->base + PSTR));
+ pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask,
+ __raw_readl(rmobile_pd->base + PSTR));
return 0;
}
-static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
- bool do_resume)
+static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd)
{
unsigned int mask;
unsigned int retry_count;
mask = BIT(rmobile_pd->bit_shift);
if (__raw_readl(rmobile_pd->base + PSTR) & mask)
- goto out;
+ return ret;
__raw_writel(mask, rmobile_pd->base + SWUCR);
if (!retry_count)
ret = -EIO;
- if (!rmobile_pd->no_debug)
- pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
- rmobile_pd->genpd.name, mask,
- __raw_readl(rmobile_pd->base + PSTR));
-
-out:
- if (ret == 0 && rmobile_pd->resume && do_resume)
- rmobile_pd->resume();
+ pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
+ rmobile_pd->genpd.name, mask,
+ __raw_readl(rmobile_pd->base + PSTR));
return ret;
}
static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
{
- return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
+ return __rmobile_pd_power_up(to_rmobile_pd(genpd));
}
static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
genpd->power_on = rmobile_pd_power_up;
genpd->attach_dev = cpg_mstp_attach_dev;
genpd->detach_dev = cpg_mstp_detach_dev;
- __rmobile_pd_power_up(rmobile_pd, false);
+ __rmobile_pd_power_up(rmobile_pd);
pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
}
git.samba.org / sfrench / cifs-2.6.git / commitdiff