net/mlx5: Implement PCAM, MCAM access register commands
authorGal Pressman <galp@mellanox.com>
Thu, 8 Dec 2016 13:56:00 +0000 (15:56 +0200)
committerSaeed Mahameed <saeedm@mellanox.com>
Thu, 19 Jan 2017 21:19:58 +0000 (23:19 +0200)
Introduced registers will expose capabilities of new registers and
features related to port/management.
Driver will query MCAM and PCAM in order to avoid failing on old
firmwares with lack of support.

Signed-off-by: Gal Pressman <galp@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
drivers/net/ethernet/mellanox/mlx5/core/port.c

index 090e3a1dedc2284dcd0a60d8492382047aeceb63..b3dabe6e88366133fd07dab68f059d4f5d7e5e3a 100644 (file)
@@ -113,6 +113,11 @@ u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx);
 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn);
 void mlx5_cq_tasklet_cb(unsigned long data);
 
 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn);
 void mlx5_cq_tasklet_cb(unsigned long data);
 
+int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
+                       u8 access_reg_group);
+int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
+                       u8 access_reg_group);
+
 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
 void mlx5_lag_remove(struct mlx5_core_dev *dev);
 
 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
 void mlx5_lag_remove(struct mlx5_core_dev *dev);
 
index 5ea85336b2e4cfc9b0e361e8e72bc6f865a03b5a..969e352435ee96276c77c3e260872a2b14e1ccf0 100644 (file)
@@ -74,6 +74,30 @@ out:
 }
 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
 
 }
 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
 
+int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
+                       u8 access_reg_group)
+{
+       u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
+       int sz = MLX5_ST_SZ_BYTES(pcam_reg);
+
+       MLX5_SET(pcam_reg, in, feature_group, feature_group);
+       MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
+
+       return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
+}
+
+int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
+                       u8 access_reg_group)
+{
+       u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
+       int sz = MLX5_ST_SZ_BYTES(mcam_reg);
+
+       MLX5_SET(mcam_reg, in, feature_group, feature_group);
+       MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
+
+       return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
+}
+
 struct mlx5_reg_pcap {
        u8                      rsvd0;
        u8                      port_num;
 struct mlx5_reg_pcap {
        u8                      rsvd0;
        u8                      port_num;