drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro define

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index e2d330eed952cade98142d943ce2ceafa3c5e461..7a8e4e28abb2a9bf3b68933f80c21596920c4781 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
                (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
                (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
 
+#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
+       WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
+               (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
+               (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
+               (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
+               (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
+
 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
        WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
                (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \