Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 5 Aug 2010 15:53:20 +0000 (08:53 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 5 Aug 2010 15:53:20 +0000 (08:53 -0700)
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (150 commits)
  MIPS: PowerTV: Separate PowerTV USB support from non-USB code
  MIPS: strip the un-needed sections of vmlinuz
  MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS
  MIPS: Clean up arch/mips/boot/compressed/decompress.c
  MIPS: Clean up arch/mips/boot/compressed/ld.script
  MIPS: Unify the suffix of compressed vmlinux.bin
  MIPS: PowerTV: Add Gaia platform definitions.
  MIPS: BCM47xx: Fix nvram_getenv return value.
  MIPS: Octeon: Allow more than 3.75GB of memory with PCIe
  MIPS: Clean up notify_die() usage.
  MIPS: Remove unused task_struct.trap_no field.
  Documentation: Mention that KProbes is supported on MIPS
  SAMPLES: kprobe_example: Make it print something on MIPS.
  MIPS: kprobe: Add support.
  MIPS: Add instrunction format for BREAK and SYSCALL
  MIPS: kprobes: Define regs_return_value()
  MIPS: Ritually kill stupid printk.
  MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts.
  MIPS: Octeon: Support 256 MSI on PCIe
  MIPS: Decode core number for R2 CPUs.
  ...

297 files changed:
Documentation/kprobes.txt
arch/mips/Kbuild [new file with mode: 0644]
arch/mips/Kbuild.platforms [new file with mode: 0644]
arch/mips/Kconfig
arch/mips/Makefile
arch/mips/alchemy/Kconfig
arch/mips/alchemy/Platform [new file with mode: 0644]
arch/mips/alchemy/common/Makefile
arch/mips/alchemy/common/clocks.c
arch/mips/alchemy/common/platform.c
arch/mips/alchemy/devboards/Makefile
arch/mips/alchemy/devboards/db1200/platform.c
arch/mips/alchemy/devboards/db1x00/board_setup.c
arch/mips/alchemy/devboards/pb1000/board_setup.c
arch/mips/alchemy/devboards/pb1200/Makefile
arch/mips/alchemy/gpr/Makefile [new file with mode: 0644]
arch/mips/alchemy/gpr/board_setup.c [new file with mode: 0644]
arch/mips/alchemy/gpr/init.c [new file with mode: 0644]
arch/mips/alchemy/gpr/platform.c [new file with mode: 0644]
arch/mips/alchemy/mtx-1/Makefile
arch/mips/alchemy/mtx-1/board_setup.c
arch/mips/alchemy/xxs1500/Makefile
arch/mips/alchemy/xxs1500/board_setup.c
arch/mips/ar7/Makefile
arch/mips/ar7/Platform [new file with mode: 0644]
arch/mips/ar7/platform.c
arch/mips/bcm47xx/Platform [new file with mode: 0644]
arch/mips/bcm47xx/nvram.c
arch/mips/bcm47xx/prom.c
arch/mips/bcm63xx/Makefile
arch/mips/bcm63xx/Platform [new file with mode: 0644]
arch/mips/boot/.gitignore
arch/mips/boot/Makefile
arch/mips/boot/compressed/Makefile
arch/mips/boot/compressed/calc_vmlinuz_load_addr.c [new file with mode: 0644]
arch/mips/boot/compressed/decompress.c
arch/mips/boot/compressed/ld.script
arch/mips/cavium-octeon/Makefile
arch/mips/cavium-octeon/Platform [new file with mode: 0644]
arch/mips/cavium-octeon/cpu.c
arch/mips/cavium-octeon/csrc-octeon.c
arch/mips/cavium-octeon/dma-octeon.c
arch/mips/cavium-octeon/octeon-irq.c
arch/mips/cavium-octeon/octeon_boot.h
arch/mips/cavium-octeon/serial.c
arch/mips/cavium-octeon/setup.c
arch/mips/cavium-octeon/smp.c
arch/mips/cobalt/Makefile
arch/mips/cobalt/Platform [new file with mode: 0644]
arch/mips/configs/db1000_defconfig
arch/mips/configs/db1100_defconfig
arch/mips/configs/db1200_defconfig
arch/mips/configs/db1500_defconfig
arch/mips/configs/db1550_defconfig
arch/mips/configs/gpr_defconfig [new file with mode: 0644]
arch/mips/configs/mtx1_defconfig
arch/mips/configs/pb1100_defconfig
arch/mips/configs/pb1200_defconfig
arch/mips/configs/pb1500_defconfig
arch/mips/configs/pb1550_defconfig
arch/mips/configs/powertv_defconfig
arch/mips/dec/Makefile
arch/mips/dec/Platform [new file with mode: 0644]
arch/mips/dec/promcon.c
arch/mips/emma/Makefile [new file with mode: 0644]
arch/mips/emma/Platform [new file with mode: 0644]
arch/mips/emma/markeins/irq.c
arch/mips/emma/markeins/setup.c
arch/mips/include/asm/arch_hweight.h [new file with mode: 0644]
arch/mips/include/asm/bitops.h
arch/mips/include/asm/bootinfo.h
arch/mips/include/asm/break.h
arch/mips/include/asm/cacheops.h
arch/mips/include/asm/cop2.h
arch/mips/include/asm/cpu-features.h
arch/mips/include/asm/cpu.h
arch/mips/include/asm/elf.h
arch/mips/include/asm/emma/emma2rh.h
arch/mips/include/asm/emma/markeins.h
arch/mips/include/asm/hazards.h
arch/mips/include/asm/inst.h
arch/mips/include/asm/kdebug.h
arch/mips/include/asm/kprobes.h [new file with mode: 0644]
arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
arch/mips/include/asm/mach-bcm47xx/nvram.h
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
arch/mips/include/asm/mach-cavium-octeon/irq.h
arch/mips/include/asm/mach-jz4740/base.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/clock.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/dma.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/gpio.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/irq.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/jz4740_fb.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/jz4740_mmc.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/jz4740_nand.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/platform.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/timer.h [new file with mode: 0644]
arch/mips/include/asm/mach-jz4740/war.h [new file with mode: 0644]
arch/mips/include/asm/mach-loongson/loongson.h
arch/mips/include/asm/mach-pb1x00/pb1550.h
arch/mips/include/asm/mach-powertv/asic.h
arch/mips/include/asm/mach-powertv/asic_reg_map.h
arch/mips/include/asm/mach-powertv/asic_regs.h
arch/mips/include/asm/mach-powertv/dma-coherence.h
arch/mips/include/asm/mach-powertv/ioremap.h
arch/mips/include/asm/mach-tx49xx/kmalloc.h
arch/mips/include/asm/mipsregs.h
arch/mips/include/asm/octeon/octeon.h
arch/mips/include/asm/octeon/pci-octeon.h
arch/mips/include/asm/pci.h
arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
arch/mips/include/asm/processor.h
arch/mips/include/asm/ptrace.h
arch/mips/include/asm/sn/agent.h
arch/mips/include/asm/uasm.h
arch/mips/jazz/Makefile
arch/mips/jazz/Platform [new file with mode: 0644]
arch/mips/jz4740/Kconfig [new file with mode: 0644]
arch/mips/jz4740/Makefile [new file with mode: 0644]
arch/mips/jz4740/Platform [new file with mode: 0644]
arch/mips/jz4740/board-qi_lb60.c [new file with mode: 0644]
arch/mips/jz4740/clock-debugfs.c [new file with mode: 0644]
arch/mips/jz4740/clock.c [new file with mode: 0644]
arch/mips/jz4740/clock.h [new file with mode: 0644]
arch/mips/jz4740/dma.c [new file with mode: 0644]
arch/mips/jz4740/gpio.c [new file with mode: 0644]
arch/mips/jz4740/irq.c [new file with mode: 0644]
arch/mips/jz4740/irq.h [new file with mode: 0644]
arch/mips/jz4740/platform.c [new file with mode: 0644]
arch/mips/jz4740/pm.c [new file with mode: 0644]
arch/mips/jz4740/prom.c [new file with mode: 0644]
arch/mips/jz4740/pwm.c [new file with mode: 0644]
arch/mips/jz4740/reset.c [new file with mode: 0644]
arch/mips/jz4740/reset.h [new file with mode: 0644]
arch/mips/jz4740/serial.c [new file with mode: 0644]
arch/mips/jz4740/serial.h [new file with mode: 0644]
arch/mips/jz4740/setup.c [new file with mode: 0644]
arch/mips/jz4740/time.c [new file with mode: 0644]
arch/mips/jz4740/timer.c [new file with mode: 0644]
arch/mips/jz4740/timer.h [new file with mode: 0644]
arch/mips/kernel/Makefile
arch/mips/kernel/asm-offsets.c
arch/mips/kernel/cevt-r4k.c
arch/mips/kernel/cpu-bugs64.c
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/kprobes.c [new file with mode: 0644]
arch/mips/kernel/mcount.S
arch/mips/kernel/scall64-n32.S
arch/mips/kernel/smp.c
arch/mips/kernel/smtc.c
arch/mips/kernel/syscall.c
arch/mips/kernel/traps.c
arch/mips/lasat/Makefile
arch/mips/lasat/Platform [new file with mode: 0644]
arch/mips/loongson/Platform [new file with mode: 0644]
arch/mips/loongson/common/cs5536/Makefile
arch/mips/loongson/common/irq.c
arch/mips/loongson/fuloong-2e/Makefile
arch/mips/loongson/fuloong-2e/irq.c
arch/mips/loongson/lemote-2f/irq.c
arch/mips/math-emu/Makefile
arch/mips/math-emu/dp_modf.c
arch/mips/math-emu/dp_tint.c
arch/mips/math-emu/dp_tlong.c
arch/mips/math-emu/sp_modf.c
arch/mips/math-emu/sp_tint.c
arch/mips/math-emu/sp_tlong.c
arch/mips/mipssim/Makefile
arch/mips/mipssim/Platform [new file with mode: 0644]
arch/mips/mm/Makefile
arch/mips/mm/fault.c
arch/mips/mm/sc-rm7k.c
arch/mips/mm/tlbex.c
arch/mips/mm/uasm.c
arch/mips/mti-malta/Makefile
arch/mips/mti-malta/Platform [new file with mode: 0644]
arch/mips/nxp/pnx833x/stb22x/Makefile [deleted file]
arch/mips/nxp/pnx8550/jbs/Makefile [deleted file]
arch/mips/nxp/pnx8550/stb810/Makefile [deleted file]
arch/mips/pci/msi-octeon.c
arch/mips/pci/ops-titan-ht.c
arch/mips/pci/pcie-octeon.c
arch/mips/pmc-sierra/Platform [new file with mode: 0644]
arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
arch/mips/pmc-sierra/yosemite/ht-irq.c
arch/mips/pmc-sierra/yosemite/irq.c
arch/mips/pnx833x/Makefile [new file with mode: 0644]
arch/mips/pnx833x/Platform [new file with mode: 0644]
arch/mips/pnx833x/common/Makefile [moved from arch/mips/nxp/pnx833x/common/Makefile with 69% similarity]
arch/mips/pnx833x/common/interrupts.c [moved from arch/mips/nxp/pnx833x/common/interrupts.c with 100% similarity]
arch/mips/pnx833x/common/platform.c [moved from arch/mips/nxp/pnx833x/common/platform.c with 100% similarity]
arch/mips/pnx833x/common/prom.c [moved from arch/mips/nxp/pnx833x/common/prom.c with 100% similarity]
arch/mips/pnx833x/common/reset.c [moved from arch/mips/nxp/pnx833x/common/reset.c with 100% similarity]
arch/mips/pnx833x/common/setup.c [moved from arch/mips/nxp/pnx833x/common/setup.c with 100% similarity]
arch/mips/pnx833x/stb22x/Makefile [new file with mode: 0644]
arch/mips/pnx833x/stb22x/board.c [moved from arch/mips/nxp/pnx833x/stb22x/board.c with 100% similarity]
arch/mips/pnx8550/Makefile [new file with mode: 0644]
arch/mips/pnx8550/Platform [new file with mode: 0644]
arch/mips/pnx8550/common/Makefile [moved from arch/mips/nxp/pnx8550/common/Makefile with 97% similarity]
arch/mips/pnx8550/common/int.c [moved from arch/mips/nxp/pnx8550/common/int.c with 100% similarity]
arch/mips/pnx8550/common/pci.c [new file with mode: 0644]
arch/mips/pnx8550/common/platform.c [moved from arch/mips/nxp/pnx8550/common/platform.c with 100% similarity]
arch/mips/pnx8550/common/proc.c [moved from arch/mips/nxp/pnx8550/common/proc.c with 100% similarity]
arch/mips/pnx8550/common/prom.c [moved from arch/mips/nxp/pnx8550/common/prom.c with 100% similarity]
arch/mips/pnx8550/common/reset.c [moved from arch/mips/nxp/pnx8550/common/reset.c with 100% similarity]
arch/mips/pnx8550/common/setup.c [new file with mode: 0644]
arch/mips/pnx8550/common/time.c [moved from arch/mips/nxp/pnx8550/common/time.c with 100% similarity]
arch/mips/pnx8550/jbs/Makefile [new file with mode: 0644]
arch/mips/pnx8550/jbs/board_setup.c [moved from arch/mips/nxp/pnx8550/jbs/board_setup.c with 100% similarity]
arch/mips/pnx8550/jbs/init.c [moved from arch/mips/nxp/pnx8550/jbs/init.c with 100% similarity]
arch/mips/pnx8550/jbs/irqmap.c [moved from arch/mips/nxp/pnx8550/jbs/irqmap.c with 100% similarity]
arch/mips/pnx8550/stb810/Makefile [new file with mode: 0644]
arch/mips/pnx8550/stb810/board_setup.c [moved from arch/mips/nxp/pnx8550/stb810/board_setup.c with 100% similarity]
arch/mips/pnx8550/stb810/irqmap.c [moved from arch/mips/nxp/pnx8550/stb810/irqmap.c with 100% similarity]
arch/mips/pnx8550/stb810/prom_init.c [moved from arch/mips/nxp/pnx8550/stb810/prom_init.c with 100% similarity]
arch/mips/powertv/Makefile
arch/mips/powertv/Platform [new file with mode: 0644]
arch/mips/powertv/asic/Makefile
arch/mips/powertv/asic/asic-calliope.c
arch/mips/powertv/asic/asic-cronus.c
arch/mips/powertv/asic/asic-gaia.c [new file with mode: 0644]
arch/mips/powertv/asic/asic-zeus.c
arch/mips/powertv/asic/asic_devices.c
arch/mips/powertv/asic/prealloc-gaia.c [new file with mode: 0644]
arch/mips/powertv/init.c
arch/mips/powertv/ioremap.c [new file with mode: 0644]
arch/mips/powertv/memory.c
arch/mips/powertv/powertv-usb.c [new file with mode: 0644]
arch/mips/powertv/powertv_setup.c
arch/mips/rb532/Makefile
arch/mips/rb532/Platform [new file with mode: 0644]
arch/mips/sgi-ip22/Makefile
arch/mips/sgi-ip22/Platform [new file with mode: 0644]
arch/mips/sgi-ip27/Makefile
arch/mips/sgi-ip27/Platform [new file with mode: 0644]
arch/mips/sgi-ip27/ip27-klconfig.c
arch/mips/sgi-ip32/Makefile
arch/mips/sgi-ip32/Platform [new file with mode: 0644]
arch/mips/sibyte/Makefile [new file with mode: 0644]
arch/mips/sibyte/Platform [new file with mode: 0644]
arch/mips/sibyte/bcm1480/Makefile
arch/mips/sibyte/common/Makefile
arch/mips/sibyte/sb1250/Makefile
arch/mips/sni/Makefile
arch/mips/sni/Platform [new file with mode: 0644]
arch/mips/txx9/Makefile [new file with mode: 0644]
arch/mips/txx9/Platform [new file with mode: 0644]
arch/mips/txx9/generic/Makefile
arch/mips/txx9/jmr3927/Makefile
arch/mips/txx9/rbtx4927/Makefile
arch/mips/txx9/rbtx4938/Makefile
arch/mips/txx9/rbtx4939/Makefile
arch/mips/vr41xx/Platform [new file with mode: 0644]
arch/mips/vr41xx/common/Makefile
arch/mips/wrppmc/Makefile [moved from arch/mips/gt64120/wrppmc/Makefile with 80% similarity]
arch/mips/wrppmc/Platform [new file with mode: 0644]
arch/mips/wrppmc/irq.c [moved from arch/mips/gt64120/wrppmc/irq.c with 100% similarity]
arch/mips/wrppmc/pci.c [moved from arch/mips/gt64120/wrppmc/pci.c with 100% similarity]
arch/mips/wrppmc/reset.c [moved from arch/mips/gt64120/wrppmc/reset.c with 100% similarity]
arch/mips/wrppmc/serial.c [moved from arch/mips/gt64120/wrppmc/serial.c with 100% similarity]
arch/mips/wrppmc/setup.c [moved from arch/mips/gt64120/wrppmc/setup.c with 100% similarity]
arch/mips/wrppmc/time.c [moved from arch/mips/gt64120/wrppmc/time.c with 100% similarity]
drivers/hwmon/Kconfig
drivers/hwmon/Makefile
drivers/hwmon/jz4740-hwmon.c [new file with mode: 0644]
drivers/mmc/host/Kconfig
drivers/mmc/host/Makefile
drivers/mmc/host/jz4740_mmc.c [new file with mode: 0644]
drivers/mtd/nand/Kconfig
drivers/mtd/nand/Makefile
drivers/mtd/nand/jz4740_nand.c [new file with mode: 0644]
drivers/net/Kconfig
drivers/net/au1000_eth.c
drivers/pcmcia/Kconfig
drivers/power/Kconfig
drivers/power/Makefile
drivers/power/jz4740-battery.c [new file with mode: 0644]
drivers/rtc/Kconfig
drivers/rtc/Makefile
drivers/rtc/rtc-jz4740.c [new file with mode: 0644]
drivers/serial/8250.c
drivers/serial/Kconfig
drivers/usb/Kconfig
drivers/usb/host/ohci-hcd.c
drivers/usb/host/ohci-jz4740.c [new file with mode: 0644]
drivers/video/Kconfig
drivers/video/Makefile
drivers/video/jz4740_fb.c [new file with mode: 0644]
drivers/video/tdfxfb.c
drivers/watchdog/Kconfig
drivers/watchdog/Makefile
drivers/watchdog/octeon-wdt-main.c [new file with mode: 0644]
drivers/watchdog/octeon-wdt-nmi.S [new file with mode: 0644]
include/linux/power/jz4740-battery.h [new file with mode: 0644]
kernel/printk.c
samples/kprobes/kprobe_example.c

index 6653017680ddcd0d813b074245de53c3b59310fb..1762b81fcdf2ec4a235423687865453a16196aed 100644 (file)
@@ -285,6 +285,7 @@ architectures:
 - sparc64 (Return probes not yet implemented.)
 - arm
 - ppc
+- mips
 
 3. Configuring Kprobes
 
diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
new file mode 100644 (file)
index 0000000..e322d65
--- /dev/null
@@ -0,0 +1,15 @@
+# Fail on warnings - also for files referenced in subdirs
+# -Werror can be disabled for specific files using:
+# CFLAGS_<file.o> := -Wno-error
+subdir-ccflags-y := -Werror
+
+# platform specific definitions
+include arch/mips/Kbuild.platforms
+obj-y := $(platform-y)
+
+# mips object files
+# The object files are linked as core-y files would be linked
+
+obj-y += kernel/
+obj-y += mm/
+obj-y += math-emu/
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
new file mode 100644 (file)
index 0000000..78439b8
--- /dev/null
@@ -0,0 +1,32 @@
+# All platforms listed in alphabetic order
+
+platforms += alchemy
+platforms += ar7
+platforms += bcm47xx
+platforms += bcm63xx
+platforms += cavium-octeon
+platforms += cobalt
+platforms += dec
+platforms += emma
+platforms += jazz
+platforms += jz4740
+platforms += lasat
+platforms += loongson
+platforms += mipssim
+platforms += mti-malta
+platforms += pmc-sierra
+platforms += pnx833x
+platforms += pnx8550
+platforms += powertv
+platforms += rb532
+platforms += sgi-ip22
+platforms += sgi-ip27
+platforms += sgi-ip32
+platforms += sibyte
+platforms += sni
+platforms += txx9
+platforms += vr41xx
+platforms += wrppmc
+
+# include the platform specific files
+include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
index cdaae942623d0e46e96df91b4dffc21439fdf25f..36642df7d5f6117ed0d8d8fd1c991a3237ddb8b9 100644 (file)
@@ -10,6 +10,8 @@ config MIPS
        select HAVE_DYNAMIC_FTRACE
        select HAVE_FTRACE_MCOUNT_RECORD
        select HAVE_FUNCTION_GRAPH_TRACER
+       select HAVE_KPROBES
+       select HAVE_KRETPROBES
        select RTC_LIB if !MACH_LOONGSON
 
 mainmenu "Linux/MIPS Kernel Configuration"
@@ -23,8 +25,17 @@ choice
        prompt "System type"
        default SGI_IP22
 
-config MACH_ALCHEMY
+config MIPS_ALCHEMY
        bool "Alchemy processor based machines"
+       select 64BIT_PHYS_ADDR
+       select CEVT_R4K_LIB
+       select CSRC_R4K_LIB
+       select IRQ_CPU
+       select SYS_HAS_CPU_MIPS32_R1
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_APM_EMULATION
+       select GENERIC_GPIO
+       select ARCH_WANT_OPTIONAL_GPIOLIB
        select SYS_SUPPORTS_ZBOOT
 
 config AR7
@@ -62,6 +73,7 @@ config BCM47XX
        select SSB_DRIVER_MIPS
        select SSB_DRIVER_EXTIF
        select SSB_EMBEDDED
+       select SSB_B43_PCI_BRIDGE if PCI
        select SSB_PCICORE_HOSTMODE if PCI
        select GENERIC_GPIO
        select SYS_HAS_EARLY_PRINTK
@@ -162,6 +174,18 @@ config MACH_JAZZ
         Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
         Olivetti M700-10 workstations.
 
+config MACH_JZ4740
+       bool "Ingenic JZ4740 based machines"
+       select SYS_HAS_CPU_MIPS32_R1
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+       select DMA_NONCOHERENT
+       select IRQ_CPU
+       select GENERIC_GPIO
+       select ARCH_REQUIRE_GPIOLIB
+       select SYS_HAS_EARLY_PRINTK
+       select HAVE_PWM
+
 config LASAT
        bool "LASAT Networks platforms"
        select CEVT_R4K
@@ -686,6 +710,7 @@ endchoice
 source "arch/mips/alchemy/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
+source "arch/mips/jz4740/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
 source "arch/mips/powertv/Kconfig"
@@ -892,6 +917,9 @@ config CPU_LITTLE_ENDIAN
 
 endchoice
 
+config EXPORT_UASM
+       bool
+
 config SYS_SUPPORTS_APM_EMULATION
        bool
 
index 0b9c01add0a06d91b49ff813f8eb127c70ae112a..f0d196090e944b1c0af943a97322d0b033ba3d57 100644 (file)
@@ -130,26 +130,6 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)    += -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)     += -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_TX49XX)    += -march=r4600 -Wa,--trap
-# only gcc >= 4.4 have the loongson-specific support
-cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2E) += \
-       $(call cc-option,-march=loongson2e,-march=r4600)
-cflags-$(CONFIG_CPU_LOONGSON2F) += \
-       $(call cc-option,-march=loongson2f,-march=r4600)
-# enable the workarounds for loongson2f
-ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
-  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
-    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
-  else
-    cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
-  endif
-  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
-    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
-  else
-    cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
-  endif
-endif
-
 cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
                        -Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -209,455 +189,7 @@ endif
 #
 # Board-dependent options and extra files
 #
-
-#
-# Texas Instruments AR7
-#
-core-$(CONFIG_AR7)             += arch/mips/ar7/
-cflags-$(CONFIG_AR7)           += -I$(srctree)/arch/mips/include/asm/mach-ar7
-load-$(CONFIG_AR7)             += 0xffffffff94100000
-
-#
-# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
-#
-core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
-cflags-$(CONFIG_MACH_JAZZ)     += -I$(srctree)/arch/mips/include/asm/mach-jazz
-load-$(CONFIG_MACH_JAZZ)       += 0xffffffff80080000
-
-#
-# Common Alchemy Au1x00 stuff
-#
-core-$(CONFIG_SOC_AU1X00)      += arch/mips/alchemy/common/
-
-#
-# AMD Alchemy Pb1000 eval board
-#
-core-$(CONFIG_MIPS_PB1000)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1000)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1000)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1100 eval board
-#
-core-$(CONFIG_MIPS_PB1100)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1100)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1100)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1500 eval board
-#
-core-$(CONFIG_MIPS_PB1500)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1500)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1500)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1550 eval board
-#
-core-$(CONFIG_MIPS_PB1550)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1550)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1550)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1200 eval board
-#
-core-$(CONFIG_MIPS_PB1200)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1200)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1200)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1000 eval board
-#
-core-$(CONFIG_MIPS_DB1000)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1000)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1000)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1100 eval board
-#
-core-$(CONFIG_MIPS_DB1100)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1100)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1100)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1500 eval board
-#
-core-$(CONFIG_MIPS_DB1500)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1500)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1500)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1550 eval board
-#
-core-$(CONFIG_MIPS_DB1550)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1550)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1550)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1200 eval board
-#
-core-$(CONFIG_MIPS_DB1200)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1200)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1200)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Bosporus eval board
-#
-core-$(CONFIG_MIPS_BOSPORUS)   += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_BOSPORUS)   += 0xffffffff80100000
-
-#
-# AMD Alchemy Mirage eval board
-#
-core-$(CONFIG_MIPS_MIRAGE)     += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_MIRAGE)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_MIRAGE)     += 0xffffffff80100000
-
-#
-# 4G-Systems eval board
-#
-libs-$(CONFIG_MIPS_MTX1)       += arch/mips/alchemy/mtx-1/
-load-$(CONFIG_MIPS_MTX1)       += 0xffffffff80100000
-
-#
-# MyCable eval board
-#
-libs-$(CONFIG_MIPS_XXS1500)    += arch/mips/alchemy/xxs1500/
-load-$(CONFIG_MIPS_XXS1500)    += 0xffffffff80100000
-
-# must be last for Alchemy systems for GPIO to work properly
-cflags-$(CONFIG_SOC_AU1X00)    += -I$(srctree)/arch/mips/include/asm/mach-au1x00
-
-
-#
-# Cobalt Server
-#
-core-$(CONFIG_MIPS_COBALT)     += arch/mips/cobalt/
-cflags-$(CONFIG_MIPS_COBALT)   += -I$(srctree)/arch/mips/include/asm/mach-cobalt
-load-$(CONFIG_MIPS_COBALT)     += 0xffffffff80080000
-
-#
-# DECstation family
-#
-core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
-cflags-$(CONFIG_MACH_DECSTATION)+= -I$(srctree)/arch/mips/include/asm/mach-dec
-libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/
-load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
-
-#
-# Wind River PPMC Board (4KC + GT64120)
-#
-core-$(CONFIG_WR_PPMC)         += arch/mips/gt64120/wrppmc/
-cflags-$(CONFIG_WR_PPMC)               += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
-load-$(CONFIG_WR_PPMC)         += 0xffffffff80100000
-
-#
-# Loongson family
-#
-core-$(CONFIG_MACH_LOONGSON) += arch/mips/loongson/
-cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
-                    -mno-branch-likely
-load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
-load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
-
-#
-# MIPS Malta board
-#
-core-$(CONFIG_MIPS_MALTA)      += arch/mips/mti-malta/
-cflags-$(CONFIG_MIPS_MALTA)    += -I$(srctree)/arch/mips/include/asm/mach-malta
-load-$(CONFIG_MIPS_MALTA)      += 0xffffffff80100000
-all-$(CONFIG_MIPS_MALTA)       := $(COMPRESSION_FNAME).bin
-
-#
-# MIPS SIM
-#
-core-$(CONFIG_MIPS_SIM)                += arch/mips/mipssim/
-cflags-$(CONFIG_MIPS_SIM)      += -I$(srctree)/arch/mips/include/asm/mach-mipssim
-load-$(CONFIG_MIPS_SIM)                += 0x80100000
-
-#
-# PMC-Sierra MSP SOCs
-#
-core-$(CONFIG_PMC_MSP)         += arch/mips/pmc-sierra/msp71xx/
-cflags-$(CONFIG_PMC_MSP)       += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
-                                       -mno-branch-likely
-load-$(CONFIG_PMC_MSP)         += 0xffffffff80100000
-
-#
-# PMC-Sierra Yosemite
-#
-core-$(CONFIG_PMC_YOSEMITE)    += arch/mips/pmc-sierra/yosemite/
-cflags-$(CONFIG_PMC_YOSEMITE)  += -I$(srctree)/arch/mips/include/asm/mach-yosemite
-load-$(CONFIG_PMC_YOSEMITE)    += 0xffffffff80100000
-
-#
-# LASAT platforms
-#
-core-$(CONFIG_LASAT)           += arch/mips/lasat/
-cflags-$(CONFIG_LASAT)         += -I$(srctree)/arch/mips/include/asm/mach-lasat
-load-$(CONFIG_LASAT)           += 0xffffffff80000000
-
-#
-# Common VR41xx
-#
-core-$(CONFIG_MACH_VR41XX)     += arch/mips/vr41xx/common/
-cflags-$(CONFIG_MACH_VR41XX)   += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
-
-#
-# ZAO Networks Capcella (VR4131)
-#
-load-$(CONFIG_ZAO_CAPCELLA)    += 0xffffffff80000000
-
-#
-# Victor MP-C303/304 (VR4122)
-#
-load-$(CONFIG_VICTOR_MPC30X)   += 0xffffffff80001000
-
-#
-# IBM WorkPad z50 (VR4121)
-#
-core-$(CONFIG_IBM_WORKPAD)     += arch/mips/vr41xx/ibm-workpad/
-load-$(CONFIG_IBM_WORKPAD)     += 0xffffffff80004000
-
-#
-# CASIO CASSIPEIA E-55/65 (VR4111)
-#
-core-$(CONFIG_CASIO_E55)       += arch/mips/vr41xx/casio-e55/
-load-$(CONFIG_CASIO_E55)       += 0xffffffff80004000
-
-#
-# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
-#
-load-$(CONFIG_TANBAC_TB022X)   += 0xffffffff80000000
-
-# NXP STB225
-core-$(CONFIG_SOC_PNX833X)             += arch/mips/nxp/pnx833x/common/
-cflags-$(CONFIG_SOC_PNX833X)   += -Iarch/mips/include/asm/mach-pnx833x
-libs-$(CONFIG_NXP_STB220)              += arch/mips/nxp/pnx833x/stb22x/
-load-$(CONFIG_NXP_STB220)              += 0xffffffff80001000
-libs-$(CONFIG_NXP_STB225)              += arch/mips/nxp/pnx833x/stb22x/
-load-$(CONFIG_NXP_STB225)              += 0xffffffff80001000
-
-#
-# Common NXP PNX8550
-#
-core-$(CONFIG_SOC_PNX8550)     += arch/mips/nxp/pnx8550/common/
-cflags-$(CONFIG_SOC_PNX8550)   += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
-
-#
-# NXP PNX8550 JBS board
-#
-libs-$(CONFIG_PNX8550_JBS)     += arch/mips/nxp/pnx8550/jbs/
-#cflags-$(CONFIG_PNX8550_JBS)  += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
-load-$(CONFIG_PNX8550_JBS)     += 0xffffffff80060000
-
-# NXP PNX8550 STB810 board
-#
-libs-$(CONFIG_PNX8550_STB810)  += arch/mips/nxp/pnx8550/stb810/
-load-$(CONFIG_PNX8550_STB810)  += 0xffffffff80060000
-
-#
-# Common NEC EMMAXXX
-#
-core-$(CONFIG_SOC_EMMA2RH)     += arch/mips/emma/common/
-cflags-$(CONFIG_SOC_EMMA2RH)   += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
-
-#
-# NEC EMMA2RH Mark-eins
-#
-core-$(CONFIG_NEC_MARKEINS)    += arch/mips/emma/markeins/
-load-$(CONFIG_NEC_MARKEINS)    += 0xffffffff88100000
-
-#
-# Cisco PowerTV Platform
-#
-core-$(CONFIG_POWERTV)         += arch/mips/powertv/
-cflags-$(CONFIG_POWERTV)        += -I$(srctree)/arch/mips/include/asm/mach-powertv
-load-$(CONFIG_POWERTV)         += 0xffffffff90800000
-
-#
-# SGI IP22 (Indy/Indigo2)
-#
-# Set the load address to >= 0xffffffff88069000 if you want to leave space for
-# symmon, 0xffffffff80002000 for production kernels.  Note that the value must
-# be aligned to a multiple of the kernel stack size or the handling of the
-# current variable will break so for 64-bit kernels we have to raise the start
-# address by 8kb.
-#
-core-$(CONFIG_SGI_IP22)                += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP22)      += -I$(srctree)/arch/mips/include/asm/mach-ip22
-ifdef CONFIG_32BIT
-load-$(CONFIG_SGI_IP22)                += 0xffffffff88002000
-endif
-ifdef CONFIG_64BIT
-load-$(CONFIG_SGI_IP22)                += 0xffffffff88004000
-endif
-
-#
-# SGI-IP27 (Origin200/2000)
-#
-# Set the load address to >= 0xc000000000300000 if you want to leave space for
-# symmon, 0xc00000000001c000 for production kernels.  Note that the value must
-# be 16kb aligned or the handling of the current variable will break.
-#
-ifdef CONFIG_SGI_IP27
-core-$(CONFIG_SGI_IP27)                += arch/mips/sgi-ip27/
-cflags-$(CONFIG_SGI_IP27)      += -I$(srctree)/arch/mips/include/asm/mach-ip27
-ifdef CONFIG_MAPPED_KERNEL
-load-$(CONFIG_SGI_IP27)                += 0xc00000004001c000
-OBJCOPYFLAGS                   := --change-addresses=0x3fffffff80000000
-dataoffset-$(CONFIG_SGI_IP27)  += 0x01000000
-else
-load-$(CONFIG_SGI_IP27)                += 0xa80000000001c000
-OBJCOPYFLAGS                   := --change-addresses=0x57ffffff80000000
-endif
-endif
-
-#
-# SGI IP28 (Indigo2 R10k)
-#
-# Set the load address to >= 0xa800000020080000 if you want to leave space for
-# symmon, 0xa800000020004000 for production kernels ?  Note that the value must
-# be 16kb aligned or the handling of the current variable will break.
-# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
-#
-ifdef CONFIG_SGI_IP28
-  ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
-      $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
-  endif
-endif
-core-$(CONFIG_SGI_IP28)                += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP28)      += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
-load-$(CONFIG_SGI_IP28)                += 0xa800000020004000
-
-#
-# SGI-IP32 (O2)
-#
-# Set the load address to >= 80069000 if you want to leave space for symmon,
-# 0xffffffff80004000 for production kernels.  Note that the value must be aligned to
-# a multiple of the kernel stack size or the handling of the current variable
-# will break.
-#
-core-$(CONFIG_SGI_IP32)                += arch/mips/sgi-ip32/
-cflags-$(CONFIG_SGI_IP32)      += -I$(srctree)/arch/mips/include/asm/mach-ip32
-load-$(CONFIG_SGI_IP32)                += 0xffffffff80004000
-
-#
-# Sibyte SB1250/BCM1480 SOC
-#
-# This is a LIB so that it links at the end, and initcalls are later
-# the sequence; but it is built as an object so that modules don't get
-# removed (as happens, even if they have __initcall/module_init)
-#
-core-$(CONFIG_SIBYTE_BCM112X)  += arch/mips/sibyte/sb1250/
-core-$(CONFIG_SIBYTE_BCM112X)  += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM112X)        += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                       -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
-
-core-$(CONFIG_SIBYTE_SB1250)   += arch/mips/sibyte/sb1250/
-core-$(CONFIG_SIBYTE_SB1250)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_SB1250) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                       -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
-
-core-$(CONFIG_SIBYTE_BCM1x55)  += arch/mips/sibyte/bcm1480/
-core-$(CONFIG_SIBYTE_BCM1x55)  += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x55)        += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                       -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
-
-core-$(CONFIG_SIBYTE_BCM1x80)  += arch/mips/sibyte/bcm1480/
-core-$(CONFIG_SIBYTE_BCM1x80)  += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x80)        += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                       -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
-
-#
-# Sibyte BCM91120x (Carmel) board
-# Sibyte BCM91120C (CRhine) board
-# Sibyte BCM91125C (CRhone) board
-# Sibyte BCM91125E (Rhone) board
-# Sibyte SWARM board
-# Sibyte BCM91x80 (BigSur) board
-#
-core-$(CONFIG_SIBYTE_CARMEL)   += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CARMEL)   := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_CRHINE)   += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CRHINE)   := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_CRHONE)   += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CRHONE)   := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_RHONE)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_RHONE)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_SENTOSA)  += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_SENTOSA)  := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_SWARM)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_SWARM)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_BIGSUR)   += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_BIGSUR)   := 0xffffffff80100000
-
-#
-# Broadcom BCM47XX boards
-#
-core-$(CONFIG_BCM47XX)         += arch/mips/bcm47xx/
-cflags-$(CONFIG_BCM47XX)       += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
-load-$(CONFIG_BCM47XX)         := 0xffffffff80001000
-
-#
-# Broadcom BCM63XX boards
-#
-core-$(CONFIG_BCM63XX)         += arch/mips/bcm63xx/
-cflags-$(CONFIG_BCM63XX)       += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
-load-$(CONFIG_BCM63XX)         := 0xffffffff80010000
-
-#
-# SNI RM
-#
-core-$(CONFIG_SNI_RM)          += arch/mips/sni/
-cflags-$(CONFIG_SNI_RM)                += -I$(srctree)/arch/mips/include/asm/mach-rm
-ifdef CONFIG_CPU_LITTLE_ENDIAN
-load-$(CONFIG_SNI_RM)          += 0xffffffff80600000
-else
-load-$(CONFIG_SNI_RM)          += 0xffffffff80030000
-endif
-all-$(CONFIG_SNI_RM)           := $(COMPRESSION_FNAME).ecoff
-
-#
-# Common TXx9
-#
-core-$(CONFIG_MACH_TX39XX)     += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX39XX) += -I$(srctree)/arch/mips/include/asm/mach-tx39xx
-load-$(CONFIG_MACH_TX39XX)     += 0xffffffff80050000
-core-$(CONFIG_MACH_TX49XX)     += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX49XX) += -I$(srctree)/arch/mips/include/asm/mach-tx49xx
-load-$(CONFIG_MACH_TX49XX)     += 0xffffffff80100000
-
-#
-# Toshiba JMR-TX3927 board
-#
-core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
-
-#
-# Routerboard 532 board
-#
-core-$(CONFIG_MIKROTIK_RB532)  += arch/mips/rb532/
-cflags-$(CONFIG_MIKROTIK_RB532) += -I$(srctree)/arch/mips/include/asm/mach-rc32434
-load-$(CONFIG_MIKROTIK_RB532)  += 0xffffffff80101000
-
-#
-# Toshiba RBTX49XX boards
-#
-core-$(CONFIG_TOSHIBA_RBTX4927)        += arch/mips/txx9/rbtx4927/
-core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
-core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
-
-#
-# Cavium Octeon
-#
-core-$(CONFIG_CPU_CAVIUM_OCTEON)       += arch/mips/cavium-octeon/
-cflags-$(CONFIG_CPU_CAVIUM_OCTEON)     += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
-core-$(CONFIG_CPU_CAVIUM_OCTEON)       += arch/mips/cavium-octeon/executive/
-ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
-load-$(CONFIG_CPU_CAVIUM_OCTEON)       += 0xffffffff84100000
-else
-load-$(CONFIG_CPU_CAVIUM_OCTEON)       += 0xffffffff81100000
-endif
+include $(srctree)/arch/mips/Kbuild.platforms
 
 cflags-y                       += -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)          += arch/mips/pci/
@@ -706,7 +238,8 @@ head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
 
 libs-y                 += arch/mips/lib/
 
-core-y                 += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
+# See arch/mips/Kbuild for content of core part of the kernel
+core-y += arch/mips/
 
 drivers-$(CONFIG_OPROFILE)     += arch/mips/oprofile/
 
@@ -726,6 +259,9 @@ endif
 vmlinux.32: vmlinux
        $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 
+
+#obj-$(CONFIG_KPROBES)         += kprobes.o
+
 #
 # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
 # ELF files from 32-bit files by conversion.
@@ -733,35 +269,19 @@ vmlinux.32: vmlinux
 vmlinux.64: vmlinux
        $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
 
-makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
-makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
-          VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
-
 all:   $(all-y)
 
-vmlinuz: vmlinux FORCE
-       +@$(call makezboot,$@)
+# boot
+vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE
+       $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@
 
-vmlinuz.bin: vmlinux
-       +@$(call makezboot,$@)
+# boot/compressed
+vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
+       $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
+          VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
 
-vmlinuz.ecoff: vmlinux
-       +@$(call makezboot,$@)
 
-vmlinuz.srec: vmlinux
-       +@$(call makezboot,$@)
-
-vmlinux.bin: $(vmlinux-32)
-       +@$(call makeboot,$@)
-
-vmlinux.ecoff: $(vmlinux-32)
-       +@$(call makeboot,$@)
-
-vmlinux.srec: $(vmlinux-32)
-       +@$(call makeboot,$@)
-
-CLEAN_FILES += vmlinux.ecoff \
-              vmlinux.srec
+CLEAN_FILES += vmlinux.32 vmlinux.64
 
 archprepare:
 ifdef CONFIG_MIPS32_N32
@@ -780,9 +300,9 @@ install:
        $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
 
 archclean:
-       @$(MAKE) $(clean)=arch/mips/boot
-       @$(MAKE) $(clean)=arch/mips/boot/compressed
-       @$(MAKE) $(clean)=arch/mips/lasat
+       $(Q)$(MAKE) $(clean)=arch/mips/boot
+       $(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
+       $(Q)$(MAKE) $(clean)=arch/mips/lasat
 
 define archhelp
        echo '  install              - install kernel into $(INSTALL_PATH)'
@@ -796,11 +316,3 @@ define archhelp
        echo
        echo '  These will be default as apropriate for a configured platform.'
 endef
-
-CLEAN_FILES += vmlinux.32 \
-              vmlinux.64 \
-              vmlinux.ecoff \
-              vmlinuz \
-              vmlinuz.ecoff \
-              vmlinuz.bin \
-              vmlinuz.srec
index df3b1a7eb15d98b7d5643ee940aef5a90d04bd9a..2ccfd4a135bce633d3fcefba360faeceeae3724e 100644 (file)
@@ -11,7 +11,7 @@ config ALCHEMY_GPIO_INDIRECT
 
 choice
        prompt "Machine type"
-       depends on MACH_ALCHEMY
+       depends on MIPS_ALCHEMY
        default MIPS_DB1000
 
 config MIPS_MTX1
@@ -128,41 +128,33 @@ config MIPS_XXS1500
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_HAS_EARLY_PRINTK
 
+config MIPS_GPR
+       bool "Trapeze ITS GPR board"
+       select SOC_AU1550
+       select HW_HAS_PCI
+       select DMA_NONCOHERENT
+       select MIPS_DISABLE_OBSOLETE_IDE
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+       select SYS_HAS_EARLY_PRINTK
+
 endchoice
 
 config SOC_AU1000
        bool
-       select SOC_AU1X00
        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1100
        bool
-       select SOC_AU1X00
        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1500
        bool
-       select SOC_AU1X00
        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1550
        bool
-       select SOC_AU1X00
        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1200
        bool
-       select SOC_AU1X00
        select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1X00
-       bool
-       select 64BIT_PHYS_ADDR
-       select CEVT_R4K_LIB
-       select CSRC_R4K_LIB
-       select IRQ_CPU
-       select SYS_HAS_CPU_MIPS32_R1
-       select SYS_SUPPORTS_32BIT_KERNEL
-       select SYS_SUPPORTS_APM_EMULATION
-       select GENERIC_GPIO
-       select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
new file mode 100644 (file)
index 0000000..96e9e41
--- /dev/null
@@ -0,0 +1,114 @@
+#
+# Core Alchemy code
+#
+platform-$(CONFIG_MIPS_ALCHEMY)        += alchemy/common/
+
+
+#
+# AMD Alchemy Pb1000 eval board
+#
+platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1000)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1000)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1100 eval board
+#
+platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1100)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1100)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1500 eval board
+#
+platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1500)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1500)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1550 eval board
+#
+platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1550)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1550)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1200 eval board
+#
+platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1200)   += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1200)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1000 eval board
+#
+platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1000)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1000)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1100 eval board
+#
+platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1100)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1100)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1500 eval board
+#
+platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1500)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1500)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1550 eval board
+#
+platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1550)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1550)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1200 eval board
+#
+platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1200)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1200)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Bosporus eval board
+#
+platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_BOSPORUS)  += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_BOSPORUS)    += 0xffffffff80100000
+
+#
+# AMD Alchemy Mirage eval board
+#
+platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_MIRAGE)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_MIRAGE)     += 0xffffffff80100000
+
+#
+# 4G-Systems eval board
+#
+platform-$(CONFIG_MIPS_MTX1)   += alchemy/mtx-1/
+load-$(CONFIG_MIPS_MTX1)       += 0xffffffff80100000
+
+#
+# MyCable eval board
+#
+platform-$(CONFIG_MIPS_XXS1500)        += alchemy/xxs1500/
+load-$(CONFIG_MIPS_XXS1500)    += 0xffffffff80100000
+
+#
+# Trapeze ITS GRP board
+#
+platform-$(CONFIG_MIPS_GPR)    += alchemy/gpr/
+load-$(CONFIG_MIPS_GPR)                += 0xffffffff80100000
+
+# boards can specify their own <gpio.h> in one of their include dirs.
+# If they do, placing this line here at the end will make sure the
+# compiler picks the board one.  If they don't, it will make sure
+# the alchemy generic gpio header is picked up.
+
+cflags-$(CONFIG_MIPS_ALCHEMY)  += -I$(srctree)/arch/mips/include/asm/mach-au1x00
index 06c0e65a54b5e079c1fd4f52ed71e289e68874c9..27811fe341d6e732353a55243ee7b49d916eb482 100644 (file)
@@ -18,5 +18,3 @@ ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
 endif
 
 obj-$(CONFIG_PCI)              += pci.o
-
-EXTRA_CFLAGS += -Werror
index 460c6285c1bbe00cda3f0f89b2da1b5867d6f223..af0fe41055af7eb421bf08fabc2959d282842f53 100644 (file)
@@ -89,11 +89,7 @@ unsigned long au1xxx_calc_clock(void)
         * over backwards trying to determine the frequency.
         */
        if (au1xxx_cpu_has_pll_wo())
-#ifdef CONFIG_SOC_AU1000_FREQUENCY
-               cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
-#else
                cpu_speed = 396000000;
-#endif
        else
                cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
 
index f9e5622ebc95b8e37a42ac96d3556176c44b11c9..1dc55ee2681b01ee5841524083c78b2360245966 100644 (file)
@@ -12,6 +12,7 @@
  */
 
 #include <linux/dma-mapping.h>
+#include <linux/etherdevice.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/init.h>
@@ -21,6 +22,8 @@
 #include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-au1x00/au1xxx_eth.h>
 
+#include <prom.h>
+
 #define PORT(_base, _irq)                                      \
        {                                                       \
                .mapbase        = _base,                        \
@@ -33,7 +36,6 @@
        }
 
 static struct plat_serial8250_port au1x00_uart_data[] = {
-#if defined(CONFIG_SERIAL_8250_AU1X00)
 #if defined(CONFIG_SOC_AU1000)
        PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
        PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
@@ -54,7 +56,6 @@ static struct plat_serial8250_port au1x00_uart_data[] = {
        PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
        PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
 #endif
-#endif /* CONFIG_SERIAL_8250_AU1X00 */
        { },
 };
 
@@ -436,17 +437,27 @@ static int __init au1xxx_platform_init(void)
 {
        unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
        int err, i;
+       unsigned char ethaddr[6];
 
        /* Fill up uartclk. */
        for (i = 0; au1x00_uart_data[i].flags; i++)
                au1x00_uart_data[i].uartclk = uartclk;
 
+       /* use firmware-provided mac addr if available and necessary */
+       i = prom_get_ethernet_addr(ethaddr);
+       if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
+               memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
+
        err = platform_add_devices(au1xxx_platform_devices,
                                   ARRAY_SIZE(au1xxx_platform_devices));
 #ifndef CONFIG_SOC_AU1100
+       ethaddr[5] += 1;        /* next addr for 2nd MAC */
+       if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
+               memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
+
        /* Register second MAC if enabled in pinfunc */
        if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
-               platform_device_register(&au1xxx_eth1_device);
+               err = platform_device_register(&au1xxx_eth1_device);
 #endif
 
        return err;
index ecbd37f9ee873f77b37d52d11d1532c67cb80afa..826449c817c3acef53919a17b4d73b60e449f8d3 100644 (file)
@@ -16,5 +16,3 @@ obj-$(CONFIG_MIPS_DB1500)     += db1x00/
 obj-$(CONFIG_MIPS_DB1550)      += db1x00/
 obj-$(CONFIG_MIPS_BOSPORUS)    += db1x00/
 obj-$(CONFIG_MIPS_MIRAGE)      += db1x00/
-
-EXTRA_CFLAGS += -Werror
index 3cb95a98ab31bc107b3a994401841c9189efa251..3fa34c3abc0408a04d668c262e03360506b4d861 100644 (file)
@@ -216,14 +216,14 @@ static struct resource db1200_ide_res[] = {
        }
 };
 
-static u64 ide_dmamask = DMA_32BIT_MASK;
+static u64 ide_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_ide_dev = {
        .name           = "au1200-ide",
        .id             = 0,
        .dev = {
                .dma_mask               = &ide_dmamask,
-               .coherent_dma_mask      = DMA_32BIT_MASK,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
        },
        .num_resources  = ARRAY_SIZE(db1200_ide_res),
        .resource       = db1200_ide_res,
@@ -385,12 +385,12 @@ static struct au1550_spi_info db1200_spi_platdata = {
        .activate_cs    = db1200_spi_cs_en,
 };
 
-static u64 spi_dmamask = DMA_32BIT_MASK;
+static u64 spi_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_spi_dev = {
        .dev    = {
                .dma_mask               = &spi_dmamask,
-               .coherent_dma_mask      = DMA_32BIT_MASK,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
                .platform_data          = &db1200_spi_platdata,
        },
        .name           = "au1550-spi",
index 50c9bef99daa58e93842cfd87926e3bcd07dd5be..9e45971343edcd3a751f470bbefdce595e1e0adf 100644 (file)
@@ -79,7 +79,6 @@ static struct au1000_eth_platform_data eth0_pdata = {
 
 static void bosporus_power_off(void)
 {
-       printk(KERN_INFO "It's now safe to turn off power\n");
        while (1)
                asm volatile (".set mips3 ; wait ; .set mips0");
 }
index 4ef50d86b18127c0dae904127cba9bec5c31520c..f6540ec47a64412d982aee01f9e92acd161d363c 100644 (file)
@@ -47,9 +47,11 @@ static void board_reset(char *c)
 
 static void board_power_off(void)
 {
-       printk(KERN_ALERT "It's now safe to remove power\n");
        while (1)
-               asm volatile (".set mips3 ; wait ; .set mips1");
+               asm volatile (
+               "       .set    mips32                                  \n"
+               "       wait                                            \n"
+               "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
index 2ea9b02ef09f4c9f0ca25c1ea23fae3af7e63a7c..18c1bd53e4c0e5464b972fc994c0838c5fd75cb0 100644 (file)
@@ -3,5 +3,3 @@
 #
 
 obj-y := board_setup.o platform.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
new file mode 100644 (file)
index 0000000..cb73fe2
--- /dev/null
@@ -0,0 +1,8 @@
+#
+#  Copyright 2003 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for Trapeze ITS GPR board.
+#
+
+obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
new file mode 100644 (file)
index 0000000..ad2e3f1
--- /dev/null
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2000-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+#define UART1_ADDR     KSEG1ADDR(UART1_PHYS_ADDR)
+#define UART3_ADDR     KSEG1ADDR(UART3_PHYS_ADDR)
+
+char irq_tab_alchemy[][5] __initdata = {
+       [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
+};
+
+static void gpr_reset(char *c)
+{
+       /* switch System-LED to orange (red# and green# on) */
+       alchemy_gpio_direction_output(4, 0);
+       alchemy_gpio_direction_output(5, 0);
+
+       /* trigger watchdog to reset board in 200ms */
+       printk(KERN_EMERG "Triggering watchdog soft reset...\n");
+       raw_local_irq_disable();
+       alchemy_gpio_direction_output(1, 0);
+       udelay(1);
+       alchemy_gpio_set_value(1, 1);
+       while (1)
+               cpu_wait();
+}
+
+static void gpr_power_off(void)
+{
+       while (1)
+               cpu_wait();
+}
+
+void __init board_setup(void)
+{
+       printk(KERN_INFO "Tarpeze ITS GPR board\n");
+
+       pm_power_off = gpr_power_off;
+       _machine_halt = gpr_power_off;
+       _machine_restart = gpr_reset;
+
+       /* Enable UART3 */
+       au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
+       au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
+       /* Enable UART1 */
+       au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
+       au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
+
+       /* Take away Reset of UMTS-card */
+       alchemy_gpio_direction_output(215, 1);
+
+#ifdef CONFIG_PCI
+#if defined(__MIPSEB__)
+       au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+       au_writel(0xf, Au1500_PCI_CFG);
+#endif
+#endif
+}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
new file mode 100644 (file)
index 0000000..f044f4c
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+       return "GPR";
+}
+
+void __init prom_init(void)
+{
+       unsigned char *memsize_str;
+       unsigned long memsize;
+
+       prom_argc = fw_arg0;
+       prom_argv = (char **)fw_arg1;
+       prom_envp = (char **)fw_arg2;
+
+       prom_init_cmdline();
+
+       memsize_str = prom_getenv("memsize");
+       if (!memsize_str)
+               memsize = 0x04000000;
+       else
+               strict_strtoul(memsize_str, 0, &memsize);
+       add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+       alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
new file mode 100644 (file)
index 0000000..14b4662
--- /dev/null
@@ -0,0 +1,183 @@
+/*
+ * GPR board platform device registration
+ *
+ * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+/*
+ * Watchdog
+ */
+static struct resource gpr_wdt_resource[] = {
+       [0] = {
+               .start  = 1,
+               .end    = 1,
+               .name   = "gpr-adm6320-wdt",
+               .flags  = IORESOURCE_IRQ,
+       }
+};
+
+static struct platform_device gpr_wdt_device = {
+       .name = "adm6320-wdt",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(gpr_wdt_resource),
+       .resource = gpr_wdt_resource,
+};
+
+/*
+ * FLASH
+ *
+ * 0x00000000-0x00200000 : "kernel"
+ * 0x00200000-0x00a00000 : "rootfs"
+ * 0x01d00000-0x01f00000 : "config"
+ * 0x01c00000-0x01d00000 : "yamon"
+ * 0x01d00000-0x01d40000 : "yamon env vars"
+ * 0x00000000-0x00a00000 : "kernel+rootfs"
+ */
+static struct mtd_partition gpr_mtd_partitions[] = {
+       {
+               .name   = "kernel",
+               .size   = 0x00200000,
+               .offset = 0,
+       },
+       {
+               .name   = "rootfs",
+               .size   = 0x00800000,
+               .offset = MTDPART_OFS_APPEND,
+               .mask_flags = MTD_WRITEABLE,
+       },
+       {
+               .name   = "config",
+               .size   = 0x00200000,
+               .offset = 0x01d00000,
+       },
+       {
+               .name   = "yamon",
+               .size   = 0x00100000,
+               .offset = 0x01c00000,
+       },
+       {
+               .name   = "yamon env vars",
+               .size   = 0x00040000,
+               .offset = MTDPART_OFS_APPEND,
+       },
+       {
+               .name   = "kernel+rootfs",
+               .size   = 0x00a00000,
+               .offset = 0,
+       },
+};
+
+static struct physmap_flash_data gpr_flash_data = {
+       .width          = 4,
+       .nr_parts       = ARRAY_SIZE(gpr_mtd_partitions),
+       .parts          = gpr_mtd_partitions,
+};
+
+static struct resource gpr_mtd_resource = {
+       .start  = 0x1e000000,
+       .end    = 0x1fffffff,
+       .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device gpr_mtd_device = {
+       .name           = "physmap-flash",
+       .dev            = {
+               .platform_data  = &gpr_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &gpr_mtd_resource,
+};
+
+/*
+ * LEDs
+ */
+static struct gpio_led gpr_gpio_leds[] = {
+       {       /* green */
+               .name                   = "gpr:green",
+               .gpio                   = 4,
+               .active_low             = 1,
+       },
+       {       /* red */
+               .name                   = "gpr:red",
+               .gpio                   = 5,
+               .active_low             = 1,
+       }
+};
+
+static struct gpio_led_platform_data gpr_led_data = {
+       .num_leds = ARRAY_SIZE(gpr_gpio_leds),
+       .leds = gpr_gpio_leds,
+};
+
+static struct platform_device gpr_led_devices = {
+       .name = "leds-gpio",
+       .id = -1,
+       .dev = {
+               .platform_data = &gpr_led_data,
+       }
+};
+
+/*
+ * I2C
+ */
+static struct i2c_gpio_platform_data gpr_i2c_data = {
+       .sda_pin                = 209,
+       .sda_is_open_drain      = 1,
+       .scl_pin                = 210,
+       .scl_is_open_drain      = 1,
+       .udelay                 = 2,            /* ~100 kHz */
+       .timeout                = HZ,
+ };
+
+static struct platform_device gpr_i2c_device = {
+       .name                   = "i2c-gpio",
+       .id                     = -1,
+       .dev.platform_data      = &gpr_i2c_data,
+};
+
+static struct i2c_board_info gpr_i2c_info[] __initdata = {
+       {
+               I2C_BOARD_INFO("lm83", 0x18),
+               .type = "lm83"
+       }
+};
+
+static struct platform_device *gpr_devices[] __initdata = {
+       &gpr_wdt_device,
+       &gpr_mtd_device,
+       &gpr_i2c_device,
+       &gpr_led_devices,
+};
+
+static int __init gpr_dev_init(void)
+{
+       i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
+
+       return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
+}
+device_initcall(gpr_dev_init);
index 4a53815b3c6c53558f4abf7f1f8a82819fbddd1c..81b540ceaf888d797042c12f6b8eb7d586594a3d 100644 (file)
@@ -6,7 +6,4 @@
 # Makefile for 4G Systems MTX-1 board.
 #
 
-lib-y := init.o board_setup.o
-obj-y := platform.o
-
-EXTRA_CFLAGS += -Werror
+obj-y += init.o board_setup.o platform.o
index 52d883d37dd7e4b69a82ab89e724c7b0c2cca7d4..6398fa95905c9036518aa728292b16fe925eee39 100644 (file)
@@ -60,9 +60,11 @@ static void mtx1_reset(char *c)
 
 static void mtx1_power_off(void)
 {
-       printk(KERN_ALERT "It's now safe to remove power\n");
        while (1)
-               asm volatile (".set mips3 ; wait ; .set mips1");
+               asm volatile (
+               "       .set    mips32                                  \n"
+               "       wait                                            \n"
+               "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
@@ -105,14 +107,10 @@ void __init board_setup(void)
 int
 mtx1_pci_idsel(unsigned int devsel, int assert)
 {
-#define MTX_IDSEL_ONLY_0_AND_3 0
-#if MTX_IDSEL_ONLY_0_AND_3
-       if (devsel != 0 && devsel != 3) {
-               printk(KERN_ERR "*** not 0 or 3\n");
-               return 0;
-       }
-#endif
-
+       /* This function is only necessary to support a proprietary Cardbus
+        * adapter on the mtx-1 "singleboard" variant. It triggers a custom
+        * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
+        */
        if (assert && devsel != 0)
                /* Suppress signal to Cardbus */
                alchemy_gpio_set_value(1, 0);   /* set EXT_IO3 OFF */
index 4dc81d794cb8dc65b4af71868e3c5eed267d081f..91defcf4f335e8d51ffc8551264f8ef0a2850d74 100644 (file)
@@ -5,6 +5,4 @@
 # Makefile for MyCable XXS1500 board.
 #
 
-lib-y := init.o board_setup.o platform.o
-
-EXTRA_CFLAGS += -Werror
+obj-y += init.o board_setup.o platform.o
index 47b42927607b2eb11d98a1cf8345515260538747..b43c918925d36406cd0903afb95f6c2d6abe546f 100644 (file)
@@ -42,9 +42,11 @@ static void xxs1500_reset(char *c)
 
 static void xxs1500_power_off(void)
 {
-       printk(KERN_ALERT "It's now safe to remove power\n");
        while (1)
-               asm volatile (".set mips3 ; wait ; .set mips1");
+               asm volatile (
+               "       .set    mips32                                  \n"
+               "       wait                                            \n"
+               "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
index 26bc5da189971c1714174c82e0c4f8a72f6d4fa6..7435e44b396404b355fe60dc1bf7e9de96e33665 100644 (file)
@@ -8,4 +8,3 @@ obj-y := \
        platform.o \
        gpio.o \
        clock.o
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ar7/Platform b/arch/mips/ar7/Platform
new file mode 100644 (file)
index 0000000..0bf85c4
--- /dev/null
@@ -0,0 +1,6 @@
+#
+# Texas Instruments AR7
+#
+platform-$(CONFIG_AR7)          += ar7/
+cflags-$(CONFIG_AR7)            += -I$(srctree)/arch/mips/include/asm/mach-ar7
+load-$(CONFIG_AR7)              += 0xffffffff94100000
index 8f31d1d59683383124035708659089ced9a804a2..0da5b2b8dd88a4a08d75b4eaf9aa3965b1af655f 100644 (file)
@@ -292,40 +292,28 @@ static struct platform_device cpmac_high = {
        .num_resources  = ARRAY_SIZE(cpmac_high_res),
 };
 
-static inline unsigned char char2hex(char h)
+static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
 {
-       switch (h) {
-       case '0': case '1': case '2': case '3': case '4':
-       case '5': case '6': case '7': case '8': case '9':
-               return h - '0';
-       case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
-               return h - 'A' + 10;
-       case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
-               return h - 'a' + 10;
-       default:
-               return 0;
-       }
-}
-
-static void cpmac_get_mac(int instance, unsigned char *dev_addr)
-{
-       int i;
-       char name[5], default_mac[ETH_ALEN], *mac;
+       char name[5], *mac;
 
-       mac = NULL;
        sprintf(name, "mac%c", 'a' + instance);
        mac = prom_getenv(name);
-       if (!mac) {
+       if (!mac && instance) {
                sprintf(name, "mac%c", 'a');
                mac = prom_getenv(name);
        }
-       if (!mac) {
-               random_ether_addr(default_mac);
-               mac = default_mac;
-       }
-       for (i = 0; i < 6; i++)
-               dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
-                       char2hex(mac[i * 3 + 1]);
+
+       if (mac) {
+               if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
+                                       &dev_addr[0], &dev_addr[1],
+                                       &dev_addr[2], &dev_addr[3],
+                                       &dev_addr[4], &dev_addr[5]) != 6) {
+                       pr_warning("cannot parse mac address, "
+                                       "using random address\n");
+                       random_ether_addr(dev_addr);
+               }
+       } else
+               random_ether_addr(dev_addr);
 }
 
 /*****************************************************************************
diff --git a/arch/mips/bcm47xx/Platform b/arch/mips/bcm47xx/Platform
new file mode 100644 (file)
index 0000000..874b7ca
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Broadcom BCM47XX boards
+#
+platform-$(CONFIG_BCM47XX)     += bcm47xx/
+cflags-$(CONFIG_BCM47XX)       +=                                      \
+               -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
+load-$(CONFIG_BCM47XX)         := 0xffffffff80001000
index 06e03b222f6dee5962fbd7fb2be6073e9f903708..e5b6615731e5c24dd963190bc2d244930ba08299 100644 (file)
@@ -69,7 +69,7 @@ int nvram_getenv(char *name, char *val, size_t val_len)
        char *var, *value, *end, *eq;
 
        if (!name)
-               return 1;
+               return NVRAM_ERR_INV_PARAM;
 
        if (!nvram_buf[0])
                early_nvram_init();
@@ -89,6 +89,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
                        return 0;
                }
        }
-       return 1;
+       return NVRAM_ERR_ENVNOTFOUND;
 }
 EXPORT_SYMBOL(nvram_getenv);
index 0fa646c5a844bfb18186db1625c26e1b6f6e5114..f6e9063cc4c2011f057f468a30a8ab7c4c0e4ecd 100644 (file)
@@ -126,6 +126,7 @@ static __init void prom_init_cmdline(void)
 static __init void prom_init_mem(void)
 {
        unsigned long mem;
+       unsigned long max;
 
        /* Figure out memory size by finding aliases.
         *
@@ -134,21 +135,26 @@ static __init void prom_init_mem(void)
         * want to reuse the memory used by CFE (around 4MB). That means cfe_*
         * functions stop to work at some point during the boot, we should only
         * call them at the beginning of the boot.
+        *
+        * BCM47XX uses 128MB for addressing the ram, if the system contains
+        * less that that amount of ram it remaps the ram more often into the
+        * available space.
+        * Accessing memory after 128MB will cause an exception.
+        * max contains the biggest possible address supported by the platform.
+        * If the method wants to try something above we assume 128MB ram.
         */
+       max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
        for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
+               if (((unsigned long)(prom_init) + mem) > max) {
+                       mem = (128 << 20);
+                       printk(KERN_DEBUG "assume 128MB RAM\n");
+                       break;
+               }
                if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
                    *(unsigned long *)(prom_init))
                        break;
        }
 
-       /* Ignoring the last page when ddr size is 128M. Cached
-        * accesses to last page is causing the processor to prefetch
-        * using address above 128M stepping out of the ddr address
-        * space.
-        */
-       if (mem == 0x8000000)
-               mem -= 0x1000;
-
        add_memory_region(0, mem, BOOT_MEM_RAM);
 }
 
index 00064b6608096f1cd8722cf832cae7b353e39eec..6dfdc69928accdfc1d062cf9315b04f8bc28a9c2 100644 (file)
@@ -3,5 +3,3 @@ obj-y           += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 
 obj-y          += boards/
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/Platform b/arch/mips/bcm63xx/Platform
new file mode 100644 (file)
index 0000000..5f86b2f
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Broadcom BCM63XX boards
+#
+platform-$(CONFIG_BCM63XX)     += bcm63xx/
+cflags-$(CONFIG_BCM63XX)       +=                                      \
+               -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
+load-$(CONFIG_BCM63XX)         := 0xffffffff80010000
index 4667a5f9280bece570f5845b8781dd9d8b69084b..f210b09ececcf0fe9ab0ee282da0f9332c050394 100644 (file)
@@ -3,3 +3,4 @@ elf2ecoff
 vmlinux.*
 zImage
 zImage.tmp
+calc_vmlinuz_load_addr
index e39a08edcaaa02b02790944cc5d64cd199e3a23b..85bcb5adc7cb16531a4ea93d41a101a83ee786ba 100644 (file)
 # Some DECstations need all possible sections of an ECOFF executable
 #
 ifdef CONFIG_MACH_DECSTATION
-  E2EFLAGS = -a
-else
-  E2EFLAGS =
+  e2eflag := -a
 endif
 
 #
 # Drop some uninteresting sections in the kernel.
 # This is only relevant for ELF kernels but doesn't hurt a.out
 #
-drop-sections  = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
-strip-flags    = $(addprefix --remove-section=,$(drop-sections))
-
-VMLINUX = vmlinux
-
-all: vmlinux.ecoff vmlinux.srec
-
-vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
-       $(obj)/elf2ecoff $(VMLINUX) $(obj)/vmlinux.ecoff $(E2EFLAGS)
-
-$(obj)/elf2ecoff: $(obj)/elf2ecoff.c
-       $(HOSTCC) -o $@ $^
-
-vmlinux.bin: $(VMLINUX)
-       $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin
-
-vmlinux.srec: $(VMLINUX)
-       $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
-
-clean-files += elf2ecoff \
-              vmlinux.bin \
-              vmlinux.ecoff \
-              vmlinux.srec
+drop-sections := .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags   := $(addprefix --remove-section=,$(drop-sections))
+
+hostprogs-y := elf2ecoff
+
+targets := vmlinux.ecoff
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
+$(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
+       $(call if_changed,ecoff)
+
+targets += vmlinux.bin
+quiet_cmd_bin = OBJCOPY $@
+      cmd_bin = $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.bin: $(VMLINUX) FORCE
+       $(call if_changed,bin)
+
+targets += vmlinux.srec
+quiet_cmd_srec = OBJCOPY $@
+      cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.srec: $(VMLINUX) FORCE
+       $(call if_changed,srec)
index 790ddd39762080b9e0900f3c3b1e32b51ad7860b..ed9bb709c9a3816a4738d0ceef91db8c8de20cd4 100644 (file)
 # Author: Wu Zhangjin <wuzhangjin@gmail.com>
 #
 
-# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
-VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
-VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
-# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
-HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
-LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
-VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
-
 # set the default size of the mallocing area for decompressing
 BOOT_HEAP_SIZE := 0x400000
 
@@ -33,49 +25,61 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
        -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
 
-obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
+
+# decompressor objects (linked with vmlinuz)
+vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
 
 ifdef CONFIG_DEBUG_ZBOOT
-obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
-obj-$(CONFIG_MACH_ALCHEMY)                += $(obj)/uart-alchemy.o
+vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY)                += $(obj)/uart-alchemy.o
 endif
 
+targets += vmlinux.bin
 OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
-$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
        $(call if_changed,objcopy)
 
-suffix_$(CONFIG_KERNEL_GZIP)  = gz
-suffix_$(CONFIG_KERNEL_BZIP2) = bz2
-suffix_$(CONFIG_KERNEL_LZMA)  = lzma
-suffix_$(CONFIG_KERNEL_LZO)   = lzo
 tool_$(CONFIG_KERNEL_GZIP)    = gzip
 tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
 tool_$(CONFIG_KERNEL_LZMA)    = lzma
 tool_$(CONFIG_KERNEL_LZO)     = lzo
-$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
+
+targets += vmlinux.bin.z
+$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
        $(call if_changed,$(tool_y))
 
-$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
-       $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
-               --add-section=.image=$< \
-               --set-section-flags=.image=contents,alloc,load,readonly,data \
-               $(obj)/dummy.o $@
+targets += piggy.o
+OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
+                        --set-section-flags=.image=contents,alloc,load,readonly,data
+$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
+       $(call if_changed,objcopy)
+
+# Calculate the load address of the compressed kernel image
+hostprogs-y := calc_vmlinuz_load_addr
+
+VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
+               $(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
 
-LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
-vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
-       $(call if_changed,ld)
-       $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) $@
+vmlinuzobjs-y += $(obj)/piggy.o
+
+quiet_cmd_zld = LD      $@
+      cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
+quiet_cmd_strip = STRIP   $@
+      cmd_strip = $(STRIP) -s $@
+vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
+       $(call cmd,zld)
+       $(call cmd,strip)
 
 #
 # Some DECstations need all possible sections of an ECOFF executable
 #
 ifdef CONFIG_MACH_DECSTATION
-  E2EFLAGS = -a
-else
-  E2EFLAGS =
+  e2eflag := -a
 endif
 
 # elf2ecoff can only handle 32bit image
+hostprogs-y += ../elf2ecoff
 
 ifdef CONFIG_32BIT
        VMLINUZ = vmlinuz
@@ -83,23 +87,22 @@ else
        VMLINUZ = vmlinuz.32
 endif
 
+quiet_cmd_32 = OBJCOPY $@
+      cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 vmlinuz.32: vmlinuz
-       $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+       $(call cmd,32)
 
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
 vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
-       $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
-
-$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
-       $(Q)$(HOSTCC) -o $@ $^
+       $(call cmd,ecoff)
 
 OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
 vmlinuz.bin: vmlinuz
-       $(call if_changed,objcopy)
+       $(call cmd,objcopy)
 
 OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
 vmlinuz.srec: vmlinuz
-       $(call if_changed,objcopy)
+       $(call cmd,objcopy)
 
-clean:
-clean-files += *.o \
-              vmlinu*
+clean-files := $(objtree)/vmlinuz.*
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
new file mode 100644 (file)
index 0000000..88c9d96
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+       struct stat sb;
+       uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
+
+       if (argc != 3) {
+               fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
+                               argv[0]);
+               return EXIT_FAILURE;
+       }
+
+       if (stat(argv[1], &sb) == -1) {
+               perror("stat");
+               return EXIT_FAILURE;
+       }
+
+       /* Convert hex characters to dec number */
+       errno = 0;
+       if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
+               if (errno != 0)
+                       perror("sscanf");
+               else
+                       fprintf(stderr, "No matching characters\n");
+
+               return EXIT_FAILURE;
+       }
+
+       vmlinux_size = (uint64_t)sb.st_size;
+       vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
+
+       /*
+        * Align with 16 bytes: "greater than that used for any standard data
+        * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
+        */
+
+       vmlinuz_load_addr += (16 - vmlinux_size % 16);
+
+       printf("0x%llx\n", vmlinuz_load_addr);
+
+       return EXIT_SUCCESS;
+}
index 5db43c58b1bf7e844eeaa683d3a61d45c0ea340a..5cad0faefa17cdcd7425eb07e93e48554cc99f2f 100644 (file)
@@ -1,9 +1,6 @@
 /*
- * Misc. bootloader code for many machines.
- *
  * Copyright 2001 MontaVista Software Inc.
- * Author: Matt Porter <mporter@mvista.com> Derived from
- * arch/ppc/boot/prep/misc.c
+ * Author: Matt Porter <mporter@mvista.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
 
 #include <asm/addrspace.h>
 
-/* These two variables specify the free mem region
+/*
+ * These two variables specify the free mem region
  * that can be used for temporary malloc area
  */
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
-char *zimage_start;
 
 /* The linker tells us where the image is. */
 extern unsigned char __image_begin, __image_end;
@@ -83,38 +80,31 @@ void *memset(void *s, int c, size_t n)
 
 void decompress_kernel(unsigned long boot_heap_start)
 {
-       int zimage_size;
-
-       /*
-        * We link ourself to an arbitrary low address.  When we run, we
-        * relocate outself to that address.  __image_beign points to
-        * the part of the image where the zImage is. -- Tom
-        */
-       zimage_start = (char *)(unsigned long)(&__image_begin);
+       unsigned long zimage_start, zimage_size;
+
+       zimage_start = (unsigned long)(&__image_begin);
        zimage_size = (unsigned long)(&__image_end) -
            (unsigned long)(&__image_begin);
 
-       /*
-        * The zImage and initrd will be between start and _end, so they've
-        * already been moved once.  We're good to go now. -- Tom
-        */
        puts("zimage at:     ");
-       puthex((unsigned long)zimage_start);
+       puthex(zimage_start);
        puts(" ");
-       puthex((unsigned long)(zimage_size + zimage_start));
+       puthex(zimage_size + zimage_start);
        puts("\n");
 
-       /* this area are prepared for mallocing when decompressing */
+       /* This area are prepared for mallocing when decompressing */
        free_mem_ptr = boot_heap_start;
        free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
 
-       /* Display standard Linux/MIPS boot prompt for kernel args */
+       /* Display standard Linux/MIPS boot prompt */
        puts("Uncompressing Linux at load address ");
        puthex(VMLINUX_LOAD_ADDRESS_ULL);
        puts("\n");
+
        /* Decompress the kernel with according algorithm */
-       decompress(zimage_start, zimage_size, 0, 0,
+       decompress((char *)zimage_start, zimage_size, 0, 0,
                   (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
-       /* FIXME: is there a need to flush cache here? */
+
+       /* FIXME: should we flush cache here? */
        puts("Now, booting the kernel...\n");
 }
index 613a35b02f50b8f372f4a701c2b589c134a0e5ed..8e6b07ca2f5e6924b68b8ce177aa7c9e7119e80e 100644 (file)
@@ -2,61 +2,44 @@
  * ld.script for compressed kernel support of MIPS
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhanjing@gmail.com>
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
  */
 
 OUTPUT_ARCH(mips)
 ENTRY(start)
 SECTIONS
 {
-       /* . = VMLINUZ_LOAD_ADDRESS */
-       /* read-only */
-       _text = .;      /* Text and read-only data */
-       .text   : {
-               _ftext = . ;
+       /* Text and read-only data */
+       /* . = VMLINUZ_LOAD_ADDRESS; */
+       .text : {
                *(.text)
                *(.rodata)
-       } = 0
-       _etext = .;     /* End of text section */
+       }
+       /* End of text section */
 
-       /* writable */
-       .data   : {     /* Data */
-               _fdata = . ;
+       /* Writable data */
+       .data : {
                *(.data)
-               /* Put the compressed image here, so bss is on the end. */
+               /* Put the compressed image here */
                __image_begin = .;
                *(.image)
                __image_end = .;
                CONSTRUCTORS
        }
-       .sdata  : { *(.sdata) }
-       . = ALIGN(4);
-       _edata  =  .;   /* End of data section */
+       . = ALIGN(16);
+       _edata = .;
+       /* End of data section */
 
        /* BSS */
-       __bss_start = .;
-       _fbss = .;
-       .sbss   : { *(.sbss) *(.scommon) }
-       .bss    : {
-               *(.dynbss)
+       .bss : {
                *(.bss)
-               *(COMMON)
        }
-       .  = ALIGN(4);
-       _end = . ;
-
-       /* These are needed for ELF backends which have not yet been converted
-        * to the new style linker.  */
-
-       .stab 0 : { *(.stab) }
-       .stabstr 0 : { *(.stabstr) }
-
-       /* These must appear regardless of  .  */
-       .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
-       .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+       . = ALIGN(16);
+       _end = .;
 
        /* Sections to be discarded */
-       /DISCARD/       : {
+       /DISCARD/ : {
                *(.MIPS.options)
                *(.options)
                *(.pdr)
index 3e9876317e61c2c040021a6b3e91a7e7f3b2bb2a..19eb0434269ffc6017bb79da7f00485d2cb13813 100644 (file)
@@ -12,7 +12,6 @@
 obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
+obj-y += executive/
 
 obj-$(CONFIG_SMP)                     += smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
new file mode 100644 (file)
index 0000000..1e43ccf
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# Cavium Octeon
+#
+platform-$(CONFIG_CPU_CAVIUM_OCTEON)   += cavium-octeon/
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON)     +=                              \
+               -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
+ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+load-$(CONFIG_CPU_CAVIUM_OCTEON)       += 0xffffffff84100000
+else
+load-$(CONFIG_CPU_CAVIUM_OCTEON)       += 0xffffffff81100000
+endif
index b6df5387e855d10ad1d483851f3f3d553ef1335c..c664c8cc2b42cb8970b9f57531a03e2998075566 100644 (file)
@@ -41,12 +41,8 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
        return NOTIFY_OK;               /* Let default notifier send signals */
 }
 
-static struct notifier_block cnmips_cu2_notifier = {
-       .notifier_call = cnmips_cu2_call,
-};
-
 static int cnmips_cu2_setup(void)
 {
-       return register_cu2_notifier(&cnmips_cu2_notifier);
+       return cu2_notifier(cnmips_cu2_call, 0);
 }
 early_initcall(cnmips_cu2_setup);
index 0bf4bbe04ae2219b66fd032e52c82b8ee1350a97..b6847c8e0ddd3784b4050b7dee6558cfd595e119 100644 (file)
@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
 unsigned long long notrace sched_clock(void)
 {
        /* 64-bit arithmatic can overflow, so use 128-bit.  */
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
        u64 t1, t2, t3;
        unsigned long long rv;
        u64 mult = clocksource_mips.mult;
@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
                : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
                : "hi", "lo");
        return rv;
-#else
-       /* GCC > 4.3 do it the easy way.  */
-       unsigned int __attribute__((mode(TI))) t;
-       t = read_c0_cvmcount();
-       t = t * clocksource_mips.mult;
-       return (unsigned long long)(t >> clocksource_mips.shift);
-#endif
 }
 
 void __init plat_time_init(void)
@@ -88,3 +80,58 @@ void __init plat_time_init(void)
        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
        clocksource_register(&clocksource_mips);
 }
+
+static u64 octeon_udelay_factor;
+static u64 octeon_ndelay_factor;
+
+void __init octeon_setup_delays(void)
+{
+       octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
+       /*
+        * For __ndelay we divide by 2^16, so the factor is multiplied
+        * by the same amount.
+        */
+       octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
+
+       preset_lpj = octeon_get_clock_rate() / HZ;
+}
+
+void __udelay(unsigned long us)
+{
+       u64 cur, end, inc;
+
+       cur = read_c0_cvmcount();
+
+       inc = us * octeon_udelay_factor;
+       end = cur + inc;
+
+       while (end > cur)
+               cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__udelay);
+
+void __ndelay(unsigned long ns)
+{
+       u64 cur, end, inc;
+
+       cur = read_c0_cvmcount();
+
+       inc = ((ns * octeon_ndelay_factor) >> 16);
+       end = cur + inc;
+
+       while (end > cur)
+               cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__ndelay);
+
+void __delay(unsigned long loops)
+{
+       u64 cur, end;
+
+       cur = read_c0_cvmcount();
+       end = cur + loops;
+
+       while (end > cur)
+               cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__delay);
index be531ec1f2064b590b58dfe8b4db4f5534999bab..d22b5a2d64f47988659f55d2998925ff569b0711 100644 (file)
@@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
                        panic("dma_map_single: "
                              "Attempt to map illegal memory address 0x%llx\n",
                              physical);
-               else if ((physical + size >=
-                         (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
-                        && physical < (4ull<<30))
-                       pr_warning("dma_map_single: Warning: "
-                                  "Mapping memory address that might "
-                                  "conflict with devices 0x%llx-0x%llx\n",
-                                  physical, physical+size-1);
+               else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
+                        physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
+                       result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+
+                       if (((result+size-1) & dma_mask) != result+size-1)
+                               panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
+                                     physical, physical+size-1, dma_mask);
+                       goto done;
+               }
+
                /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
                if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
                        result = physical - 0x400000000ull;
index c424cd158dc6c7f195a3c4c3a29f8e4793da8493..ce7500cdf5b709de9755d94f6b07b41eeca17359 100644 (file)
@@ -3,15 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
 #include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-pexp-defs.h>
-#include <asm/octeon/cvmx-npi-defs.h>
 
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
@@ -41,14 +39,14 @@ static void octeon_irq_core_ack(unsigned int irq)
 
 static void octeon_irq_core_eoi(unsigned int irq)
 {
-       struct irq_desc *desc = irq_desc + irq;
+       struct irq_desc *desc = irq_to_desc(irq);
        unsigned int bit = irq - OCTEON_IRQ_SW0;
        /*
         * If an IRQ is being processed while we are disabling it the
         * handler will attempt to unmask the interrupt after it has
         * been disabled.
         */
-       if (desc->status & IRQ_DISABLED)
+       if ((unlikely(desc->status & IRQ_DISABLED)))
                return;
        /*
         * We don't need to disable IRQs to make these atomic since
@@ -106,6 +104,29 @@ static struct irq_chip octeon_irq_chip_core = {
 
 static void octeon_irq_ciu0_ack(unsigned int irq)
 {
+       switch (irq) {
+       case OCTEON_IRQ_GMX_DRP0:
+       case OCTEON_IRQ_GMX_DRP1:
+       case OCTEON_IRQ_IPD_DRP:
+       case OCTEON_IRQ_KEY_ZERO:
+       case OCTEON_IRQ_TIMER0:
+       case OCTEON_IRQ_TIMER1:
+       case OCTEON_IRQ_TIMER2:
+       case OCTEON_IRQ_TIMER3:
+       {
+               int index = cvmx_get_core_num() * 2;
+               u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+               /*
+                * CIU timer type interrupts must be acknoleged by
+                * writing a '1' bit to their sum0 bit.
+                */
+               cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+               break;
+       }
+       default:
+               break;
+       }
+
        /*
         * In order to avoid any locking accessing the CIU, we
         * acknowledge CIU interrupts by disabling all of them.  This
@@ -130,7 +151,53 @@ static void octeon_irq_ciu0_eoi(unsigned int irq)
        set_c0_status(0x100 << 2);
 }
 
+static int next_coreid_for_irq(struct irq_desc *desc)
+{
+
+#ifdef CONFIG_SMP
+       int coreid;
+       int weight = cpumask_weight(desc->affinity);
+
+       if (weight > 1) {
+               int cpu = smp_processor_id();
+               for (;;) {
+                       cpu = cpumask_next(cpu, desc->affinity);
+                       if (cpu >= nr_cpu_ids) {
+                               cpu = -1;
+                               continue;
+                       } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
+                               break;
+                       }
+               }
+               coreid = octeon_coreid_for_cpu(cpu);
+       } else if (weight == 1) {
+               coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
+       } else {
+               coreid = cvmx_get_core_num();
+       }
+       return coreid;
+#else
+       return cvmx_get_core_num();
+#endif
+}
+
 static void octeon_irq_ciu0_enable(unsigned int irq)
+{
+       struct irq_desc *desc = irq_to_desc(irq);
+       int coreid = next_coreid_for_irq(desc);
+       unsigned long flags;
+       uint64_t en0;
+       int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
+
+       raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+       en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+       en0 |= 1ull << bit;
+       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+       cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+       raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+}
+
+static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
 {
        int coreid = cvmx_get_core_num();
        unsigned long flags;
@@ -167,63 +234,76 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the next core in the affinity set for chips that
+ * have the EN*_W1{S,C} registers.
  */
 static void octeon_irq_ciu0_enable_v2(unsigned int irq)
 {
-       int index = cvmx_get_core_num() * 2;
+       int index;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+       struct irq_desc *desc = irq_to_desc(irq);
 
-       cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+       if ((desc->status & IRQ_DISABLED) == 0) {
+               index = next_coreid_for_irq(desc) * 2;
+               cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+       }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the current CPU for chips that
+ * have the EN*_W1{S,C} registers.
  */
-static void octeon_irq_ciu0_ack_v2(unsigned int irq)
+static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
 {
-       int index = cvmx_get_core_num() * 2;
+       int index;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-       cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+       index = cvmx_get_core_num() * 2;
+       cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
 }
 
 /*
- * CIU timer type interrupts must be acknoleged by writing a '1' bit
- * to their sum0 bit.
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
  */
-static void octeon_irq_ciu0_timer_ack(unsigned int irq)
+static void octeon_irq_ciu0_ack_v2(unsigned int irq)
 {
        int index = cvmx_get_core_num() * 2;
-       uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-       cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
-}
+       u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
-{
-       octeon_irq_ciu0_timer_ack(irq);
-       octeon_irq_ciu0_ack(irq);
-}
+       switch (irq) {
+       case OCTEON_IRQ_GMX_DRP0:
+       case OCTEON_IRQ_GMX_DRP1:
+       case OCTEON_IRQ_IPD_DRP:
+       case OCTEON_IRQ_KEY_ZERO:
+       case OCTEON_IRQ_TIMER0:
+       case OCTEON_IRQ_TIMER1:
+       case OCTEON_IRQ_TIMER2:
+       case OCTEON_IRQ_TIMER3:
+               /*
+                * CIU timer type interrupts must be acknoleged by
+                * writing a '1' bit to their sum0 bit.
+                */
+               cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+               break;
+       default:
+               break;
+       }
 
-static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
-{
-       octeon_irq_ciu0_timer_ack(irq);
-       octeon_irq_ciu0_ack_v2(irq);
+       cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
 }
 
 /*
  * Enable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu0_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
 {
-       struct irq_desc *desc = irq_desc + irq;
+       struct irq_desc *desc = irq_to_desc(irq);
        int index = cvmx_get_core_num() * 2;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-       if ((desc->status & IRQ_DISABLED) == 0)
+       if (likely((desc->status & IRQ_DISABLED) == 0))
                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
 }
 
@@ -246,18 +326,30 @@ static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
 static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
 {
        int cpu;
+       struct irq_desc *desc = irq_to_desc(irq);
+       int enable_one = (desc->status & IRQ_DISABLED) == 0;
        unsigned long flags;
        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
 
+       /*
+        * For non-v2 CIU, we will allow only single CPU affinity.
+        * This removes the need to do locking in the .ack/.eoi
+        * functions.
+        */
+       if (cpumask_weight(dest) != 1)
+               return -EINVAL;
+
        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
        for_each_online_cpu(cpu) {
                int coreid = octeon_coreid_for_cpu(cpu);
                uint64_t en0 =
                        cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-               if (cpumask_test_cpu(cpu, dest))
+               if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                       enable_one = 0;
                        en0 |= 1ull << bit;
-               else
+               } else {
                        en0 &= ~(1ull << bit);
+               }
                cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
        }
        /*
@@ -279,13 +371,18 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
 {
        int cpu;
        int index;
+       struct irq_desc *desc = irq_to_desc(irq);
+       int enable_one = (desc->status & IRQ_DISABLED) == 0;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
        for_each_online_cpu(cpu) {
                index = octeon_coreid_for_cpu(cpu) * 2;
-               if (cpumask_test_cpu(cpu, dest))
+               if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                       enable_one = 0;
                        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
-               else
+               } else {
                        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+               }
        }
        return 0;
 }
@@ -298,8 +395,7 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
        .name = "CIU0",
        .enable = octeon_irq_ciu0_enable_v2,
        .disable = octeon_irq_ciu0_disable_all_v2,
-       .ack = octeon_irq_ciu0_ack_v2,
-       .eoi = octeon_irq_ciu0_eoi_v2,
+       .eoi = octeon_irq_ciu0_enable_v2,
 #ifdef CONFIG_SMP
        .set_affinity = octeon_irq_ciu0_set_affinity_v2,
 #endif
@@ -309,36 +405,27 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
        .name = "CIU0",
        .enable = octeon_irq_ciu0_enable,
        .disable = octeon_irq_ciu0_disable,
-       .ack = octeon_irq_ciu0_ack,
        .eoi = octeon_irq_ciu0_eoi,
 #ifdef CONFIG_SMP
        .set_affinity = octeon_irq_ciu0_set_affinity,
 #endif
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
-       .name = "CIU0-T",
-       .enable = octeon_irq_ciu0_enable_v2,
-       .disable = octeon_irq_ciu0_disable_all_v2,
-       .ack = octeon_irq_ciu0_timer_ack_v2,
-       .eoi = octeon_irq_ciu0_eoi_v2,
-#ifdef CONFIG_SMP
-       .set_affinity = octeon_irq_ciu0_set_affinity_v2,
-#endif
+/* The mbox versions don't do any affinity or round-robin. */
+static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
+       .name = "CIU0-M",
+       .enable = octeon_irq_ciu0_enable_mbox_v2,
+       .disable = octeon_irq_ciu0_disable,
+       .eoi = octeon_irq_ciu0_eoi_mbox_v2,
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_timer = {
-       .name = "CIU0-T",
-       .enable = octeon_irq_ciu0_enable,
+static struct irq_chip octeon_irq_chip_ciu0_mbox = {
+       .name = "CIU0-M",
+       .enable = octeon_irq_ciu0_enable_mbox,
        .disable = octeon_irq_ciu0_disable,
-       .ack = octeon_irq_ciu0_timer_ack_v1,
        .eoi = octeon_irq_ciu0_eoi,
-#ifdef CONFIG_SMP
-       .set_affinity = octeon_irq_ciu0_set_affinity,
-#endif
 };
 
-
 static void octeon_irq_ciu1_ack(unsigned int irq)
 {
        /*
@@ -365,10 +452,30 @@ static void octeon_irq_ciu1_eoi(unsigned int irq)
 
 static void octeon_irq_ciu1_enable(unsigned int irq)
 {
-       int coreid = cvmx_get_core_num();
+       struct irq_desc *desc = irq_to_desc(irq);
+       int coreid = next_coreid_for_irq(desc);
+       unsigned long flags;
+       uint64_t en1;
+       int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+
+       raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+       en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+       en1 |= 1ull << bit;
+       cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+       cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+       raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+}
+
+/*
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
+ */
+static void octeon_irq_ciu1_wd_enable(unsigned int irq)
+{
        unsigned long flags;
        uint64_t en1;
        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+       int coreid = bit;
 
        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
        en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
@@ -405,36 +512,43 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
  */
 static void octeon_irq_ciu1_enable_v2(unsigned int irq)
 {
-       int index = cvmx_get_core_num() * 2 + 1;
+       int index;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+       struct irq_desc *desc = irq_to_desc(irq);
 
-       cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+       if ((desc->status & IRQ_DISABLED) == 0) {
+               index = next_coreid_for_irq(desc) * 2 + 1;
+               cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+       }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
  */
-static void octeon_irq_ciu1_ack_v2(unsigned int irq)
+static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
 {
-       int index = cvmx_get_core_num() * 2 + 1;
+       int index;
+       int coreid = irq - OCTEON_IRQ_WDOG0;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+       struct irq_desc *desc = irq_to_desc(irq);
 
-       cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+       if ((desc->status & IRQ_DISABLED) == 0) {
+               index = coreid * 2 + 1;
+               cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+       }
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu1_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu1_ack_v2(unsigned int irq)
 {
-       struct irq_desc *desc = irq_desc + irq;
        int index = cvmx_get_core_num() * 2 + 1;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
 
-       if ((desc->status & IRQ_DISABLED) == 0)
-               cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+       cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
 }
 
 /*
@@ -457,19 +571,30 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
                                        const struct cpumask *dest)
 {
        int cpu;
+       struct irq_desc *desc = irq_to_desc(irq);
+       int enable_one = (desc->status & IRQ_DISABLED) == 0;
        unsigned long flags;
        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
 
+       /*
+        * For non-v2 CIU, we will allow only single CPU affinity.
+        * This removes the need to do locking in the .ack/.eoi
+        * functions.
+        */
+       if (cpumask_weight(dest) != 1)
+               return -EINVAL;
+
        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
        for_each_online_cpu(cpu) {
                int coreid = octeon_coreid_for_cpu(cpu);
                uint64_t en1 =
-                       cvmx_read_csr(CVMX_CIU_INTX_EN1
-                               (coreid * 2 + 1));
-               if (cpumask_test_cpu(cpu, dest))
+                       cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+               if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                       enable_one = 0;
                        en1 |= 1ull << bit;
-               else
+               } else {
                        en1 &= ~(1ull << bit);
+               }
                cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
        }
        /*
@@ -491,13 +616,17 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
 {
        int cpu;
        int index;
+       struct irq_desc *desc = irq_to_desc(irq);
+       int enable_one = (desc->status & IRQ_DISABLED) == 0;
        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
        for_each_online_cpu(cpu) {
                index = octeon_coreid_for_cpu(cpu) * 2 + 1;
-               if (cpumask_test_cpu(cpu, dest))
+               if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                       enable_one = 0;
                        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
-               else
+               } else {
                        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+               }
        }
        return 0;
 }
@@ -507,11 +636,10 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
  * Newer octeon chips have support for lockless CIU operation.
  */
 static struct irq_chip octeon_irq_chip_ciu1_v2 = {
-       .name = "CIU0",
+       .name = "CIU1",
        .enable = octeon_irq_ciu1_enable_v2,
        .disable = octeon_irq_ciu1_disable_all_v2,
-       .ack = octeon_irq_ciu1_ack_v2,
-       .eoi = octeon_irq_ciu1_eoi_v2,
+       .eoi = octeon_irq_ciu1_enable_v2,
 #ifdef CONFIG_SMP
        .set_affinity = octeon_irq_ciu1_set_affinity_v2,
 #endif
@@ -521,103 +649,36 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
        .name = "CIU1",
        .enable = octeon_irq_ciu1_enable,
        .disable = octeon_irq_ciu1_disable,
-       .ack = octeon_irq_ciu1_ack,
        .eoi = octeon_irq_ciu1_eoi,
 #ifdef CONFIG_SMP
        .set_affinity = octeon_irq_ciu1_set_affinity,
 #endif
 };
 
-#ifdef CONFIG_PCI_MSI
-
-static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
-
-static void octeon_irq_msi_ack(unsigned int irq)
-{
-       if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-               /* These chips have PCI */
-               cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
-                              1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-       } else {
-               /*
-                * These chips have PCIe. Thankfully the ACK doesn't
-                * need any locking.
-                */
-               cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
-                              1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-       }
-}
-
-static void octeon_irq_msi_eoi(unsigned int irq)
-{
-       /* Nothing needed */
-}
-
-static void octeon_irq_msi_enable(unsigned int irq)
-{
-       if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-               /*
-                * Octeon PCI doesn't have the ability to mask/unmask
-                * MSI interrupts individually.  Instead of
-                * masking/unmasking them in groups of 16, we simple
-                * assume MSI devices are well behaved.  MSI
-                * interrupts are always enable and the ACK is assumed
-                * to be enough.
-                */
-       } else {
-               /* These chips have PCIe.  Note that we only support
-                * the first 64 MSI interrupts.  Unfortunately all the
-                * MSI enables are in the same register.  We use
-                * MSI0's lock to control access to them all.
-                */
-               uint64_t en;
-               unsigned long flags;
-               raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
-               en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-               en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
-               cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
-               cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-               raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
-       }
-}
-
-static void octeon_irq_msi_disable(unsigned int irq)
-{
-       if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-               /* See comment in enable */
-       } else {
-               /*
-                * These chips have PCIe.  Note that we only support
-                * the first 64 MSI interrupts.  Unfortunately all the
-                * MSI enables are in the same register.  We use
-                * MSI0's lock to control access to them all.
-                */
-               uint64_t en;
-               unsigned long flags;
-               raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
-               en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-               en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-               cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
-               cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-               raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
-       }
-}
+static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
+       .name = "CIU1-W",
+       .enable = octeon_irq_ciu1_wd_enable_v2,
+       .disable = octeon_irq_ciu1_disable_all_v2,
+       .eoi = octeon_irq_ciu1_wd_enable_v2,
+};
 
-static struct irq_chip octeon_irq_chip_msi = {
-       .name = "MSI",
-       .enable = octeon_irq_msi_enable,
-       .disable = octeon_irq_msi_disable,
-       .ack = octeon_irq_msi_ack,
-       .eoi = octeon_irq_msi_eoi,
+static struct irq_chip octeon_irq_chip_ciu1_wd = {
+       .name = "CIU1-W",
+       .enable = octeon_irq_ciu1_wd_enable,
+       .disable = octeon_irq_ciu1_disable,
+       .eoi = octeon_irq_ciu1_eoi,
 };
-#endif
+
+static void (*octeon_ciu0_ack)(unsigned int);
+static void (*octeon_ciu1_ack)(unsigned int);
 
 void __init arch_init_irq(void)
 {
-       int irq;
+       unsigned int irq;
        struct irq_chip *chip0;
-       struct irq_chip *chip0_timer;
+       struct irq_chip *chip0_mbox;
        struct irq_chip *chip1;
+       struct irq_chip *chip1_wd;
 
 #ifdef CONFIG_SMP
        /* Set the default affinity to the boot cpu. */
@@ -631,13 +692,19 @@ void __init arch_init_irq(void)
        if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
+               octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
+               octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
                chip0 = &octeon_irq_chip_ciu0_v2;
-               chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
+               chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
                chip1 = &octeon_irq_chip_ciu1_v2;
+               chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
        } else {
+               octeon_ciu0_ack = octeon_irq_ciu0_ack;
+               octeon_ciu1_ack = octeon_irq_ciu1_ack;
                chip0 = &octeon_irq_chip_ciu0;
-               chip0_timer = &octeon_irq_chip_ciu0_timer;
+               chip0_mbox = &octeon_irq_chip_ciu0_mbox;
                chip1 = &octeon_irq_chip_ciu1;
+               chip1_wd = &octeon_irq_chip_ciu1_wd;
        }
 
        /* 0 - 15 reserved for i8259 master and slave controller. */
@@ -651,34 +718,23 @@ void __init arch_init_irq(void)
        /* 24 - 87 CIU_INT_SUM0 */
        for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
                switch (irq) {
-               case OCTEON_IRQ_GMX_DRP0:
-               case OCTEON_IRQ_GMX_DRP1:
-               case OCTEON_IRQ_IPD_DRP:
-               case OCTEON_IRQ_KEY_ZERO:
-               case OCTEON_IRQ_TIMER0:
-               case OCTEON_IRQ_TIMER1:
-               case OCTEON_IRQ_TIMER2:
-               case OCTEON_IRQ_TIMER3:
-                       set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
+               case OCTEON_IRQ_MBOX0:
+               case OCTEON_IRQ_MBOX1:
+                       set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
                        break;
                default:
-                       set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
+                       set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
                        break;
                }
        }
 
        /* 88 - 151 CIU_INT_SUM1 */
-       for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
-               set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
-       }
+       for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
+               set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
+
+       for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
+               set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
 
-#ifdef CONFIG_PCI_MSI
-       /* 152 - 215 PCI/PCIe MSI interrupts */
-       for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
-               set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
-                                        handle_percpu_irq);
-       }
-#endif
        set_c0_status(0x300 << 2);
 }
 
@@ -693,6 +749,7 @@ asmlinkage void plat_irq_dispatch(void)
        unsigned long cop0_status;
        uint64_t ciu_en;
        uint64_t ciu_sum;
+       unsigned int irq;
 
        while (1) {
                cop0_cause = read_c0_cause();
@@ -704,18 +761,24 @@ asmlinkage void plat_irq_dispatch(void)
                        ciu_sum = cvmx_read_csr(ciu_sum0_address);
                        ciu_en = cvmx_read_csr(ciu_en0_address);
                        ciu_sum &= ciu_en;
-                       if (likely(ciu_sum))
-                               do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
-                       else
+                       if (likely(ciu_sum)) {
+                               irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
+                               octeon_ciu0_ack(irq);
+                               do_IRQ(irq);
+                       } else {
                                spurious_interrupt();
+                       }
                } else if (unlikely(cop0_cause & STATUSF_IP3)) {
                        ciu_sum = cvmx_read_csr(ciu_sum1_address);
                        ciu_en = cvmx_read_csr(ciu_en1_address);
                        ciu_sum &= ciu_en;
-                       if (likely(ciu_sum))
-                               do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
-                       else
+                       if (likely(ciu_sum)) {
+                               irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
+                               octeon_ciu1_ack(irq);
+                               do_IRQ(irq);
+                       } else {
                                spurious_interrupt();
+                       }
                } else if (likely(cop0_cause)) {
                        do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
                } else {
@@ -725,54 +788,84 @@ asmlinkage void plat_irq_dispatch(void)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
-{
-       unsigned int isset;
-       int coreid = octeon_coreid_for_cpu(cpu);
-       int bit = (irq < OCTEON_IRQ_WDOG0) ?
-                  irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
-       if (irq < 64) {
-               isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
-                       (1ull << bit)) >> bit;
-       } else {
-              isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
-                       (1ull << bit)) >> bit;
-       }
-       return isset;
-}
 
 void fixup_irqs(void)
 {
-       int irq;
+       int irq;
+       struct irq_desc *desc;
+       cpumask_t new_affinity;
+       unsigned long flags;
+       int do_set_affinity;
+       int cpu;
+
+       cpu = smp_processor_id();
 
        for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
                octeon_irq_core_disable_local(irq);
 
-       for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
-               if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                       /* ciu irq migrates to next cpu */
-                       octeon_irq_chip_ciu0.disable(irq);
-                       octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
-               }
-       }
-
-#if 0
-       for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
-               octeon_irq_mailbox_mask(irq);
-#endif
-       for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
-               if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                       /* ciu irq migrates to next cpu */
-                       octeon_irq_chip_ciu0.disable(irq);
-                       octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
-               }
-       }
+       for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
+               desc = irq_to_desc(irq);
+               switch (irq) {
+               case OCTEON_IRQ_MBOX0:
+               case OCTEON_IRQ_MBOX1:
+                       /* The eoi function will disable them on this CPU. */
+                       desc->chip->eoi(irq);
+                       break;
+               case OCTEON_IRQ_WDOG0:
+               case OCTEON_IRQ_WDOG1:
+               case OCTEON_IRQ_WDOG2:
+               case OCTEON_IRQ_WDOG3:
+               case OCTEON_IRQ_WDOG4:
+               case OCTEON_IRQ_WDOG5:
+               case OCTEON_IRQ_WDOG6:
+               case OCTEON_IRQ_WDOG7:
+               case OCTEON_IRQ_WDOG8:
+               case OCTEON_IRQ_WDOG9:
+               case OCTEON_IRQ_WDOG10:
+               case OCTEON_IRQ_WDOG11:
+               case OCTEON_IRQ_WDOG12:
+               case OCTEON_IRQ_WDOG13:
+               case OCTEON_IRQ_WDOG14:
+               case OCTEON_IRQ_WDOG15:
+                       /*
+                        * These have special per CPU semantics and
+                        * are handled in the watchdog driver.
+                        */
+                       break;
+               default:
+                       raw_spin_lock_irqsave(&desc->lock, flags);
+                       /*
+                        * If this irq has an action, it is in use and
+                        * must be migrated if it has affinity to this
+                        * cpu.
+                        */
+                       if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
+                               if (cpumask_weight(desc->affinity) > 1) {
+                                       /*
+                                        * It has multi CPU affinity,
+                                        * just remove this CPU from
+                                        * the affinity set.
+                                        */
+                                       cpumask_copy(&new_affinity, desc->affinity);
+                                       cpumask_clear_cpu(cpu, &new_affinity);
+                               } else {
+                                       /*
+                                        * Otherwise, put it on lowest
+                                        * numbered online CPU.
+                                        */
+                                       cpumask_clear(&new_affinity);
+                                       cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
+                               }
+                               do_set_affinity = 1;
+                       } else {
+                               do_set_affinity = 0;
+                       }
+                       raw_spin_unlock_irqrestore(&desc->lock, flags);
+
+                       if (do_set_affinity)
+                               irq_set_affinity(irq, &new_affinity);
 
-       for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
-               if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                       /* ciu irq migrates to next cpu */
-                       octeon_irq_chip_ciu1.disable(irq);
-                       octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
+                       break;
                }
        }
 }
index 0f7f84accf9a88b9fec5ccd56172ba6f74cc14e9..428864b2ba4133070c563023f9c170346e24c4ca 100644 (file)
 #include <linux/types.h>
 
 struct boot_init_vector {
-       uint32_t stack_addr;
-       uint32_t code_addr;
+       /* First stage address - in ram instead of flash */
+       uint64_t code_addr;
+       /* Setup code for application, NOT application entry point */
        uint32_t app_start_func_addr;
+       /* k0 is used for global data - needs to be passed to other cores */
        uint32_t k0_val;
-       uint32_t flags;
-       uint32_t boot_info_addr;
+       /* Address of boot info block structure */
+       uint64_t boot_info_addr;
+       uint32_t flags;         /* flags */
        uint32_t pad;
-       uint32_t pad2;
 };
 
 /* similar to bootloader's linux_app_boot_info but without global data */
@@ -40,7 +42,7 @@ struct linux_app_boot_info {
        uint32_t avail_coremask;
        uint32_t pci_console_active;
        uint32_t icache_prefetch_disable;
-       uint32_t InitTLBStart_addr;
+       uint64_t InitTLBStart_addr;
        uint32_t start_app_addr;
        uint32_t cur_exception_base;
        uint32_t no_mark_private_data;
@@ -58,7 +60,7 @@ struct linux_app_boot_info {
 
 #define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
 
-#define LABI_SIGNATURE 0xAABBCCDD
+#define LABI_SIGNATURE 0xAABBCC01
 
 /*  from uboot-headers/octeon_mem_map.h */
 #define EXCEPTION_BASE_INCR     (4 * 1024)
index 83eac37a1ff976a92bca4134b21591dfa179997a..638adab028428002186bb83c589b553a0c40545b 100644 (file)
 
 #include <asm/octeon/octeon.h>
 
-#ifdef CONFIG_GDB_CONSOLE
-#define DEBUG_UART 0
-#else
 #define DEBUG_UART 1
-#endif
 
 unsigned int octeon_serial_in(struct uart_port *up, int offset)
 {
index d1b5ffaf02819f75d8a123cdeea74e3430aa2025..69197cb6c7ea106349a23ad5b81f615a8c70c614 100644 (file)
@@ -32,6 +32,7 @@
 #include <asm/time.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/pci-octeon.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -578,9 +579,6 @@ void __init prom_init(void)
        }
 
        if (strstr(arcs_cmdline, "console=") == NULL) {
-#ifdef CONFIG_GDB_CONSOLE
-               strcat(arcs_cmdline, " console=gdb");
-#else
 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
                strcat(arcs_cmdline, " console=ttyS0,115200");
 #else
@@ -588,7 +586,6 @@ void __init prom_init(void)
                        strcat(arcs_cmdline, " console=ttyS1,115200");
                else
                        strcat(arcs_cmdline, " console=ttyS0,115200");
-#endif
 #endif
        }
 
@@ -598,13 +595,13 @@ void __init prom_init(void)
                 * the filesystem. Also specify the calibration delay
                 * to avoid calculating it every time.
                 */
-               strcat(arcs_cmdline, " rw root=1f00"
-                      " lpj=60176 slram=root,0x40000000,+1073741824");
+               strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
        }
 
        mips_hpt_frequency = octeon_get_clock_rate();
 
        octeon_init_cvmcount();
+       octeon_setup_delays();
 
        _machine_restart = octeon_restart;
        _machine_halt = octeon_halt;
@@ -613,6 +610,22 @@ void __init prom_init(void)
        register_smp_ops(&octeon_smp_ops);
 }
 
+/* Exclude a single page from the regions obtained in plat_mem_setup. */
+static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
+{
+       if (addr > *mem && addr < *mem + *size) {
+               u64 inc = addr - *mem;
+               add_memory_region(*mem, inc, BOOT_MEM_RAM);
+               *mem += inc;
+               *size -= inc;
+       }
+
+       if (addr == *mem && *size > PAGE_SIZE) {
+               *mem += PAGE_SIZE;
+               *size -= PAGE_SIZE;
+       }
+}
+
 void __init plat_mem_setup(void)
 {
        uint64_t mem_alloc_size;
@@ -663,12 +676,27 @@ void __init plat_mem_setup(void)
                                                CVMX_BOOTMEM_FLAG_NO_LOCKING);
 #endif
                if (memory >= 0) {
+                       u64 size = mem_alloc_size;
+
+                       /*
+                        * exclude a page at the beginning and end of
+                        * the 256MB PCIe 'hole' so the kernel will not
+                        * try to allocate multi-page buffers that
+                        * span the discontinuity.
+                        */
+                       memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
+                                           &memory, &size);
+                       memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
+                                           CVMX_PCIE_BAR1_PHYS_SIZE,
+                                           &memory, &size);
+
                        /*
                         * This function automatically merges address
                         * regions next to each other if they are
                         * received in incrementing order.
                         */
-                       add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+                       if (size)
+                               add_memory_region(memory, size, BOOT_MEM_RAM);
                        total += mem_alloc_size;
                } else {
                        break;
@@ -691,7 +719,10 @@ void __init plat_mem_setup(void)
                      "cvmx_bootmem_phy_alloc\n");
 }
 
-
+/*
+ * Emit one character to the boot UART.  Exported for use by the
+ * watchdog timer.
+ */
 int prom_putchar(char c)
 {
        uint64_t lsrval;
@@ -705,6 +736,7 @@ int prom_putchar(char c)
        cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
        return 1;
 }
+EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
index 6d99b9d8887dd3d77ab4f94d79170fc0eacfbc25..391cefe556b3d025872b36b1ad38eb1ae850234c 100644 (file)
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/cpu.h>
 #include <linux/init.h>
@@ -27,7 +27,8 @@ volatile unsigned long octeon_processor_sp;
 volatile unsigned long octeon_processor_gp;
 
 #ifdef CONFIG_HOTPLUG_CPU
-static unsigned int InitTLBStart_addr;
+uint64_t octeon_bootloader_entry_addr;
+EXPORT_SYMBOL(octeon_bootloader_entry_addr);
 #endif
 
 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
@@ -80,20 +81,13 @@ static inline void octeon_send_ipi_mask(const struct cpumask *mask,
 static void octeon_smp_hotplug_setup(void)
 {
 #ifdef CONFIG_HOTPLUG_CPU
-       uint32_t labi_signature;
-
-       labi_signature =
-               cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                       LABI_ADDR_IN_BOOTLOADER +
-                                       offsetof(struct linux_app_boot_info,
-                                                   labi_signature)));
-       if (labi_signature != LABI_SIGNATURE)
-               pr_err("The bootloader version on this board is incorrect\n");
-       InitTLBStart_addr =
-               cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                  LABI_ADDR_IN_BOOTLOADER +
-                                          offsetof(struct linux_app_boot_info,
-                                                   InitTLBStart_addr)));
+       struct linux_app_boot_info *labi;
+
+       labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+       if (labi->labi_signature != LABI_SIGNATURE)
+               panic("The bootloader version on this board is incorrect.");
+
+       octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
 #endif
 }
 
@@ -102,24 +96,47 @@ static void octeon_smp_setup(void)
        const int coreid = cvmx_get_core_num();
        int cpus;
        int id;
-
        int core_mask = octeon_get_boot_coremask();
+#ifdef CONFIG_HOTPLUG_CPU
+       unsigned int num_cores = cvmx_octeon_num_cores();
+#endif
+
+       /* The present CPUs are initially just the boot cpu (CPU 0). */
+       for (id = 0; id < NR_CPUS; id++) {
+               set_cpu_possible(id, id == 0);
+               set_cpu_present(id, id == 0);
+       }
 
-       cpus_clear(cpu_possible_map);
        __cpu_number_map[coreid] = 0;
        __cpu_logical_map[0] = coreid;
-       cpu_set(0, cpu_possible_map);
 
+       /* The present CPUs get the lowest CPU numbers. */
        cpus = 1;
-       for (id = 0; id < 16; id++) {
+       for (id = 0; id < NR_CPUS; id++) {
                if ((id != coreid) && (core_mask & (1 << id))) {
-                       cpu_set(cpus, cpu_possible_map);
+                       set_cpu_possible(cpus, true);
+                       set_cpu_present(cpus, true);
                        __cpu_number_map[id] = cpus;
                        __cpu_logical_map[cpus] = id;
                        cpus++;
                }
        }
-       cpu_present_map = cpu_possible_map;
+
+#ifdef CONFIG_HOTPLUG_CPU
+       /*
+        * The possible CPUs are all those present on the chip.  We
+        * will assign CPU numbers for possible cores as well.  Cores
+        * are always consecutively numberd from 0.
+        */
+       for (id = 0; id < num_cores && id < NR_CPUS; id++) {
+               if (!(core_mask & (1 << id))) {
+                       set_cpu_possible(cpus, true);
+                       __cpu_number_map[id] = cpus;
+                       __cpu_logical_map[cpus] = id;
+                       cpus++;
+               }
+       }
+#endif
 
        octeon_smp_hotplug_setup();
 }
@@ -158,18 +175,21 @@ static void octeon_init_secondary(void)
 {
        const int coreid = cvmx_get_core_num();
        union cvmx_ciu_intx_sum0 interrupt_enable;
+       unsigned int sr;
 
 #ifdef CONFIG_HOTPLUG_CPU
-       unsigned int cur_exception_base;
-
-       cur_exception_base = cvmx_read64_uint32(
-               CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                            LABI_ADDR_IN_BOOTLOADER +
-                            offsetof(struct linux_app_boot_info,
-                                     cur_exception_base)));
-       /* cur_exception_base is incremented in bootloader after setting */
-       write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
+       struct linux_app_boot_info *labi;
+
+       labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+       if (labi->labi_signature != LABI_SIGNATURE)
+               panic("The bootloader version on this board is incorrect.");
 #endif
+
+       sr = set_c0_status(ST0_BEV);
+       write_c0_ebase((u32)ebase);
+       write_c0_status(sr);
+
        octeon_check_cpu_bist();
        octeon_init_cvmcount();
        /*
@@ -276,8 +296,8 @@ static int octeon_cpu_disable(void)
 static void octeon_cpu_die(unsigned int cpu)
 {
        int coreid = cpu_logical_map(cpu);
-       uint32_t avail_coremask;
-       struct cvmx_bootmem_named_block_desc *block_desc;
+       uint32_t mask, new_mask;
+       const struct cvmx_bootmem_named_block_desc *block_desc;
 
        while (per_cpu(cpu_state, cpu) != CPU_DEAD)
                cpu_relax();
@@ -286,52 +306,40 @@ static void octeon_cpu_die(unsigned int cpu)
         * This is a bit complicated strategics of getting/settig available
         * cores mask, copied from bootloader
         */
+
+       mask = 1 << coreid;
        /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
        block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 
        if (!block_desc) {
-               avail_coremask =
-                       cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                  LABI_ADDR_IN_BOOTLOADER +
-                                                  offsetof
-                                                  (struct linux_app_boot_info,
-                                                   avail_coremask)));
-       } else {                       /* alternative, already initialized */
-              avail_coremask =
-                  cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                  block_desc->base_addr +
-                                                 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
-       }
+               struct linux_app_boot_info *labi;
 
-       avail_coremask |= 1 << coreid;
+               labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 
-       /* Setting avail_coremask for bootoct binary */
-       if (!block_desc) {
-               cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                               LABI_ADDR_IN_BOOTLOADER +
-                                               offsetof(struct linux_app_boot_info,
-                                                        avail_coremask)),
-                                  avail_coremask);
-       } else {
-               cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                               block_desc->base_addr +
-                                               AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
-                                  avail_coremask);
+               labi->avail_coremask |= mask;
+               new_mask = labi->avail_coremask;
+       } else {                       /* alternative, already initialized */
+               uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
+                                                              AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
+               *p |= mask;
+               new_mask = *p;
        }
 
-       pr_info("Reset core %d. Available Coremask = %x\n", coreid,
-               avail_coremask);
+       pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
+       mb();
        cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
        cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 }
 
 void play_dead(void)
 {
-       int coreid = cvmx_get_core_num();
+       int cpu = cpu_number_map(cvmx_get_core_num());
 
        idle_task_exit();
        octeon_processor_boot = 0xff;
-       per_cpu(cpu_state, coreid) = CPU_DEAD;
+       per_cpu(cpu_state, cpu) = CPU_DEAD;
+
+       mb();
 
        while (1)       /* core will be reset here */
                ;
@@ -344,29 +352,27 @@ static void start_after_reset(void)
        kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
 }
 
-int octeon_update_boot_vector(unsigned int cpu)
+static int octeon_update_boot_vector(unsigned int cpu)
 {
 
        int coreid = cpu_logical_map(cpu);
-       unsigned int avail_coremask;
-       struct cvmx_bootmem_named_block_desc *block_desc;
+       uint32_t avail_coremask;
+       const struct cvmx_bootmem_named_block_desc *block_desc;
        struct boot_init_vector *boot_vect =
-               (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
-                                                 BOOTLOADER_BOOT_VECTOR);
+               (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
 
        block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 
        if (!block_desc) {
-               avail_coremask =
-                       cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                          LABI_ADDR_IN_BOOTLOADER +
-                                               offsetof(struct linux_app_boot_info,
-                                               avail_coremask)));
+               struct linux_app_boot_info *labi;
+
+               labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+               avail_coremask = labi->avail_coremask;
+               labi->avail_coremask &= ~(1 << coreid);
        } else {                       /* alternative, already initialized */
-              avail_coremask =
-                  cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                  block_desc->base_addr +
-                                                  AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
+               avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
+                       block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
        }
 
        if (!(avail_coremask & (1 << coreid))) {
@@ -377,9 +383,9 @@ int octeon_update_boot_vector(unsigned int cpu)
 
        boot_vect[coreid].app_start_func_addr =
                (uint32_t) (unsigned long) start_after_reset;
-       boot_vect[coreid].code_addr = InitTLBStart_addr;
+       boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
 
-       CVMX_SYNC;
+       mb();
 
        cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
 
@@ -405,17 +411,11 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
        return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
-       .notifier_call = octeon_cpu_callback,
-};
-
 static int __cpuinit register_cavium_notifier(void)
 {
-       register_hotcpu_notifier(&octeon_cpu_notifier);
-
+       hotcpu_notifier(octeon_cpu_callback, 0);
        return 0;
 }
-
 late_initcall(register_cavium_notifier);
 
 #endif  /* CONFIG_HOTPLUG_CPU */
index 237926288d6d57ff5fb15feebeadda3a0cedf505..61a334ac43ac7c52565713e4a45ed882da57132d 100644 (file)
@@ -7,5 +7,3 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
 obj-$(CONFIG_PCI)              += pci.o
 obj-$(CONFIG_EARLY_PRINTK)     += console.o
 obj-$(CONFIG_MTD_PHYSMAP)      += mtd.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cobalt/Platform b/arch/mips/cobalt/Platform
new file mode 100644 (file)
index 0000000..34123ef
--- /dev/null
@@ -0,0 +1,6 @@
+#
+# Cobalt Server
+#
+platform-$(CONFIG_MIPS_COBALT) += cobalt/
+cflags-$(CONFIG_MIPS_COBALT)   += -I$(srctree)/arch/mips/include/asm/mach-cobalt
+load-$(CONFIG_MIPS_COBALT)     += 0xffffffff80080000
index f66d406aadceac31d47599bd88e480adf120eb3e..3a9ec6ccd40df637f1d8676eb83aa45fa0f2c572 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1000=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index abb9a5805adcca5ef362eb620bcd24d0aa0f4dac..4589b84301f3f59545920374f81f7ee9ac6a09c6 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index 991c20adf471cbf25035d5065d550c7774e534b1..9950f2aabd318d8b166ca32c015f48699ed5fb5a 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1200=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index 5424c9167bf2b891e2e711d81c85c863aeb95679..346ae631d1ef9c7451a53191beb2bae1ec782ffb 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index 949b6dcf634b873e75cc9e2a49fe322dfc368641..10eafb942af3306d361c44e5a5d37a75b62fdda4 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1550=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
new file mode 100644 (file)
index 0000000..17e2e62
--- /dev/null
@@ -0,0 +1,2060 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.35-rc6
+# Fri Jul 23 19:28:52 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+CONFIG_MIPS_ALCHEMY=y
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_MIPS_GPR=y
+CONFIG_SOC_AU1550=y
+CONFIG_LOONGSON_UART_BASE=y
+# CONFIG_LOONGSON_MC146818 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_HL=m
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+# CONFIG_IP_VS_PROTO_SCTP is not set
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DECnet: Netfilter Configuration
+#
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=y
+CONFIG_ATM_CLIP=y
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+CONFIG_DECNET=m
+# CONFIG_DECNET_ROUTER is not set
+CONFIG_LLC=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_ECONET=m
+CONFIG_ECONET_AUNUDP=y
+CONFIG_ECONET_NATIVE=y
+CONFIG_WAN_ROUTER=m
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_MULTIQ is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+# CONFIG_NET_SCH_DRR is not set
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+CONFIG_AX25=m
+# CONFIG_AX25_DAMA_SLAVE is not set
+CONFIG_NETROM=m
+CONFIG_ROSE=m
+
+#
+# AX.25 network device drivers
+#
+CONFIG_MKISS=m
+CONFIG_6PACK=m
+CONFIG_BPQETHER=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_YAM=m
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=m
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+CONFIG_TIFM_CORE=m
+CONFIG_TIFM_7XX1=m
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# The newer stack is recommended.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=y
+CONFIG_ATH_DEBUG=y
+CONFIG_ATH5K=y
+CONFIG_ATH5K_DEBUG=y
+# CONFIG_ATH9K is not set
+# CONFIG_ATH9K_HTC is not set
+# CONFIG_AR9170_USB is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+CONFIG_WAN=y
+CONFIG_LANMEDIA=m
+CONFIG_HDLC=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_X25=m
+CONFIG_PCI200SYN=m
+CONFIG_WANXL=m
+# CONFIG_PC300TOO is not set
+CONFIG_FARSYNC=m
+CONFIG_DSCC4=m
+CONFIG_DSCC4_PCISYNC=y
+CONFIG_DSCC4_PCI_RST=y
+CONFIG_DLCI=m
+CONFIG_DLCI_MAX=8
+CONFIG_WAN_ROUTER_DRIVERS=m
+CONFIG_CYCLADES_SYNC=m
+CONFIG_CYCLOMX_X25=y
+CONFIG_LAPBETHER=m
+CONFIG_X25_ASY=m
+CONFIG_ATM_DRIVERS=y
+# CONFIG_ATM_DUMMY is not set
+CONFIG_ATM_TCP=m
+CONFIG_ATM_LANAI=m
+CONFIG_ATM_ENI=m
+# CONFIG_ATM_ENI_DEBUG is not set
+# CONFIG_ATM_ENI_TUNE_BURST is not set
+CONFIG_ATM_FIRESTREAM=m
+CONFIG_ATM_ZATM=m
+# CONFIG_ATM_ZATM_DEBUG is not set
+CONFIG_ATM_NICSTAR=m
+# CONFIG_ATM_NICSTAR_USE_SUNI is not set
+# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
+CONFIG_ATM_IDT77252=m
+# CONFIG_ATM_IDT77252_DEBUG is not set
+# CONFIG_ATM_IDT77252_RCV_ALL is not set
+CONFIG_ATM_IDT77252_USE_SUNI=y
+CONFIG_ATM_AMBASSADOR=m
+# CONFIG_ATM_AMBASSADOR_DEBUG is not set
+CONFIG_ATM_HORIZON=m
+# CONFIG_ATM_HORIZON_DEBUG is not set
+CONFIG_ATM_IA=m
+# CONFIG_ATM_IA_DEBUG is not set
+CONFIG_ATM_FORE200E=m
+# CONFIG_ATM_FORE200E_USE_TASKLET is not set
+CONFIG_ATM_FORE200E_TX_RETRY=16
+CONFIG_ATM_FORE200E_DEBUG=0
+CONFIG_ATM_HE=m
+CONFIG_ATM_HE_USE_SUNI=y
+# CONFIG_ATM_SOLOS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOATM=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_NET_FC=y
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_AU1550 is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_SCH is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_CS5535 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_LANGWELL is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+CONFIG_SENSORS_LM83=y
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=y
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ATM is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_LKDTM is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_SPINLOCK_TEST is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
index cff8f4c0e57c4a5a8c666333b32e6a85676e94a9..10d20aa731d3a1493117e13c47a373209dcc65d1 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_MTX1=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index 97382b698b9be94c1c68961f912eea7341db9b77..778f726af8e079320b2ac91cd0c231279673e73f 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index e9ad77320f168f5a7d4d11e246cda843a082ab99..0f908c6921114630aa9269d8e673bf1a61bfa76e 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1200=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index 7497d3306b91f4a1c52862579432c6c9ccb84fc5..1c5fe6f06c0e9573af846934fbf91948b4e5455e 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index aa526f53cb1b1db8c179fdc350a731eba84c655a..49494b01138b6a8824394870923ca263bf749858 100644 (file)
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_ALCHEMY_GPIOINT_AU1000=y
 CONFIG_MIPS_PB1550=y
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
index 7291633d81ccf9f80962fa95ba569293bff24fd5..af0ab73bfce8feeeda03b192b9ef5f9a1c7e09c9 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc5
-# Fri Aug 28 14:49:33 2009
+# Linux kernel version: 2.6.35-rc3
+# Thu Jul  1 11:03:28 2010
 #
 CONFIG_MIPS=y
 
@@ -11,11 +11,12 @@ CONFIG_MIPS=y
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
 # CONFIG_LASAT is not set
-# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_NEC_MARKEINS is not set
@@ -50,7 +51,6 @@ CONFIG_POWERTV=y
 # CONFIG_MIN_RUNTIME_RESOURCES is not set
 # CONFIG_BOOTLOADER_DRIVER is not set
 CONFIG_BOOTLOADER_FAMILY="R2"
-CONFIG_CSRC_POWERTV=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -65,9 +65,9 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_CEVT_R4K_LIB=y
 CONFIG_CEVT_R4K=y
+CONFIG_CSRC_POWERTV=y
 CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_SYS_HAS_EARLY_PRINTK=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_CPU_BIG_ENDIAN=y
@@ -79,7 +79,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
 #
 # CPU selection
 #
-# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 # CONFIG_CPU_MIPS32_R1 is not set
 CONFIG_CPU_MIPS32_R2=y
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -122,7 +123,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-CONFIG_CPU_HAS_LLSC=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
 CONFIG_CPU_MIPSR2_IRQ_VI=y
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_HAS_SYNC=y
@@ -144,8 +145,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
@@ -177,6 +177,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="mips-linux-"
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
@@ -190,19 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 CONFIG_RELAY=y
 # CONFIG_NAMESPACES is not set
@@ -211,6 +208,7 @@ CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_RD_GZIP is not set
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -234,18 +232,16 @@ CONFIG_SHMEM=y
 CONFIG_AIO=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
 # CONFIG_VM_EVENT_COUNTERS is not set
 CONFIG_PCI_QUIRKS=y
 # CONFIG_SLUB_DEBUG is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 
 #
@@ -253,7 +249,7 @@ CONFIG_HAVE_OPROFILE=y
 #
 # CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
@@ -271,15 +267,41 @@ CONFIG_LBDAF=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
-# CONFIG_PROBE_INITRD_HEADER is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -289,7 +311,6 @@ CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCI_IOV is not set
@@ -318,7 +339,6 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
@@ -390,12 +410,26 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_NETFILTER_NETLINK_LOG is not set
 # CONFIG_NF_CONNTRACK is not set
 CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+
+#
+# Xtables targets
+#
 # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
 # CONFIG_NETFILTER_XT_TARGET_MARK is not set
 # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
 # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
 # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
 # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
 # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
 # CONFIG_NETFILTER_XT_MATCH_DCCP is not set
 # CONFIG_NETFILTER_XT_MATCH_DSCP is not set
@@ -465,10 +499,13 @@ CONFIG_IP6_NF_FILTER=y
 # CONFIG_IP6_NF_RAW is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+# CONFIG_L2TP is not set
 CONFIG_STP=y
 CONFIG_BRIDGE=y
+CONFIG_BRIDGE_IGMP_SNOOPING=y
 # CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
@@ -526,10 +563,21 @@ CONFIG_NET_SCH_FIFO=y
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_WIRELESS is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+
+#
+# Some wireless drivers require a rate control algorithm
+#
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
 
 #
 # Device Drivers
@@ -539,6 +587,7 @@ CONFIG_NET_SCH_FIFO=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
@@ -550,9 +599,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
@@ -568,6 +617,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
 # CONFIG_MTD_OOPS is not set
 
 #
@@ -611,11 +661,16 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_SM_COMMON is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_DENALI is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
 CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_RICOH is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
@@ -641,6 +696,10 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
@@ -658,6 +717,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -693,64 +753,95 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
 CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
 # CONFIG_SATA_SIL24 is not set
 CONFIG_ATA_SFF=y
-# CONFIG_SATA_SVW is not set
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
 # CONFIG_SATA_NV is not set
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
 # CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
 # CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
 # CONFIG_SATA_VITESSE is not set
-# CONFIG_SATA_INIC162X is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
 # CONFIG_PATA_ALI is not set
 # CONFIG_PATA_AMD is not set
 # CONFIG_PATA_ARTOP is not set
 # CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_ATP867X is not set
 # CONFIG_PATA_CMD64X is not set
 # CONFIG_PATA_CS5520 is not set
 # CONFIG_PATA_CS5530 is not set
 # CONFIG_PATA_CYPRESS is not set
 # CONFIG_PATA_EFAR is not set
-# CONFIG_ATA_GENERIC is not set
 # CONFIG_PATA_HPT366 is not set
 # CONFIG_PATA_HPT37X is not set
 # CONFIG_PATA_HPT3X2N is not set
 # CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
 # CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87410 is not set
 # CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
 # CONFIG_PATA_PDC_OLD is not set
 # CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_RDC is not set
 # CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_PDC2027X is not set
 # CONFIG_PATA_SIL680 is not set
 # CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_PLATFORM is not set
-# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
@@ -763,7 +854,7 @@ CONFIG_ATA_SFF=y
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -787,6 +878,7 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
@@ -800,6 +892,7 @@ CONFIG_MII=y
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
@@ -829,6 +922,8 @@ CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T4_DEPENDS=y
+# CONFIG_CHELSIO_T4 is not set
 # CONFIG_ENIC is not set
 # CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
@@ -841,16 +936,12 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
+# CONFIG_QLCNIC is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
 # CONFIG_BE2NET is not set
 # CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+# CONFIG_WLAN is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -864,6 +955,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_USB_PEGASUS is not set
 CONFIG_USB_RTL8150=y
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -873,6 +965,7 @@ CONFIG_USB_RTL8150=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
@@ -882,6 +975,7 @@ CONFIG_USB_RTL8150=y
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -913,6 +1007,7 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
 # CONFIG_NOZOMI is not set
 
 #
@@ -924,6 +1019,9 @@ CONFIG_INPUT_EVDEV=y
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -934,6 +1032,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
 
@@ -945,7 +1044,6 @@ CONFIG_DEVPORT=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -953,20 +1051,14 @@ CONFIG_SSB_POSSIBLE=y
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_SUPPORT is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGA_ARB is not set
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -980,7 +1072,6 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
 
 #
@@ -993,31 +1084,43 @@ CONFIG_USB_HIDDEV=y
 #
 # Special HID drivers
 #
+# CONFIG_HID_3M_PCT is not set
 # CONFIG_HID_A4TECH is not set
 # CONFIG_HID_APPLE is not set
 # CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
 # CONFIG_HID_CHERRY is not set
 # CONFIG_HID_CHICONY is not set
 # CONFIG_HID_CYPRESS is not set
 # CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
 # CONFIG_HID_EZKEY is not set
 # CONFIG_HID_KYE is not set
 # CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
 # CONFIG_HID_KENSINGTON is not set
 # CONFIG_HID_LOGITECH is not set
 # CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
 # CONFIG_HID_MONTEREY is not set
 # CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
 # CONFIG_HID_PANTHERLORD is not set
 # CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
 # CONFIG_HID_SAMSUNG is not set
 # CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
 # CONFIG_HID_SUNPLUS is not set
 # CONFIG_HID_GREENASIA is not set
 # CONFIG_HID_SMARTJOYPLUS is not set
 # CONFIG_HID_TOPSEED is not set
 # CONFIG_HID_THRUSTMASTER is not set
 # CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1032,7 +1135,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_MON is not set
@@ -1050,6 +1152,7 @@ CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1133,6 +1236,7 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
 # CONFIG_USB_SERIAL_QUALCOMM is not set
 # CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
@@ -1146,6 +1250,8 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 # CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 
 #
@@ -1158,7 +1264,6 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -1171,7 +1276,6 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 
 #
@@ -1189,10 +1293,6 @@ CONFIG_RTC_LIB=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
 # CONFIG_STAGING is not set
 
 #
@@ -1214,6 +1314,7 @@ CONFIG_JBD=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
@@ -1274,6 +1375,7 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1284,7 +1386,6 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1299,6 +1400,7 @@ CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
@@ -1360,6 +1462,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1393,15 +1496,25 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
 # CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_TRACING_SUPPORT=y
 CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_PREEMPT_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
@@ -1410,19 +1523,22 @@ CONFIG_FTRACE=y
 CONFIG_BRANCH_PROFILE_NONE=y
 # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
 # CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-# CONFIG_KMEMCHECK is not set
+# CONFIG_EARLY_PRINTK is not set
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
+CONFIG_CMDLINE=""
 # CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_SPINLOCK_TEST is not set
 
 #
 # Security options
@@ -1430,13 +1546,16 @@ CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
@@ -1479,11 +1598,13 @@ CONFIG_CRYPTO_CBC=y
 #
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
index c530208ee15494ce22c09ca247ed1ba32b70ce1d..9eb2f9c036aad596584427a5512255aab1769f8b 100644 (file)
@@ -8,5 +8,3 @@ obj-y           := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
 obj-$(CONFIG_PROM_CONSOLE)     += promcon.o
 obj-$(CONFIG_TC)               += tc.o
 obj-$(CONFIG_CPU_HAS_WB)       += wbflush.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/dec/Platform b/arch/mips/dec/Platform
new file mode 100644 (file)
index 0000000..3adbcbd
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# DECstation family
+#
+platform-$(CONFIG_MACH_DECSTATION)     = dec/
+cflags-$(CONFIG_MACH_DECSTATION)       += \
+                       -I$(srctree)/arch/mips/include/asm/mach-dec
+libs-$(CONFIG_MACH_DECSTATION)         += arch/mips/dec/prom/
+load-$(CONFIG_MACH_DECSTATION)         += 0xffffffff80040000
index 9f0972f5a7023f8ff416cb44700d1c5872026650..c239c25b79ff90bcfb1bb3f43648570d81d10138 100644 (file)
@@ -33,8 +33,7 @@ static int __init prom_console_setup(struct console *co, char *options)
        return 0;
 }
 
-static struct console sercons =
-{
+static struct console sercons = {
        .name   = "ttyS",
        .write  = prom_console_write,
        .setup  = prom_console_setup,
diff --git a/arch/mips/emma/Makefile b/arch/mips/emma/Makefile
new file mode 100644 (file)
index 0000000..4254a31
--- /dev/null
@@ -0,0 +1,6 @@
+obj-$(CONFIG_SOC_EMMA2RH)      += common/
+
+#
+# NEC EMMA2RH Mark-eins
+#
+obj-$(CONFIG_NEC_MARKEINS)     += markeins/
diff --git a/arch/mips/emma/Platform b/arch/mips/emma/Platform
new file mode 100644 (file)
index 0000000..0282f7f
--- /dev/null
@@ -0,0 +1,4 @@
+platform-$(CONFIG_SOC_EMMA2RH) += emma/
+cflags-$(CONFIG_SOC_EMMA2RH)   +=                                      \
+               -I$(srctree)/arch/mips/include/asm/mach-emma2rh
+load-$(CONFIG_NEC_MARKEINS)    += 0xffffffff88100000
index 9504b7ee0b7c0d51a5adf1c3fd4fa702d414b660..3a96799eb65fec6b25b87e53fbf13b74c12464de 100644 (file)
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
        /* setup cascade interrupts */
        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-       setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+       setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
        if (pending & STATUSF_IP7)
-               do_IRQ(CPU_IRQ_BASE + 7);
+               do_IRQ(MIPS_CPU_IRQ_BASE + 7);
        else if (pending & STATUSF_IP2)
                emma2rh_irq_dispatch();
        else if (pending & STATUSF_IP1)
-               do_IRQ(CPU_IRQ_BASE + 1);
+               do_IRQ(MIPS_CPU_IRQ_BASE + 1);
        else if (pending & STATUSF_IP0)
-               do_IRQ(CPU_IRQ_BASE + 0);
+               do_IRQ(MIPS_CPU_IRQ_BASE + 0);
        else
                spurious_interrupt();
 }
index 9b3f51e5f140219120c8cdfe2df85487d5bf7ab4..feceebcfff4269bd9d740749d080aae7831673ba 100644 (file)
@@ -52,7 +52,6 @@ static void markeins_machine_halt(void)
 
 static void markeins_machine_power_off(void)
 {
-       printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
        markeins_led("poweroff.");
        while (1) ;
 }
diff --git a/arch/mips/include/asm/arch_hweight.h b/arch/mips/include/asm/arch_hweight.h
new file mode 100644 (file)
index 0000000..712a744
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef _ASM_ARCH_HWEIGHT_H
+#define _ASM_ARCH_HWEIGHT_H
+
+#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
+
+#include <asm/types.h>
+
+static inline unsigned int __arch_hweight32(unsigned int w)
+{
+       return __builtin_popcount(w);
+}
+
+static inline unsigned int __arch_hweight16(unsigned int w)
+{
+       return __builtin_popcount(w & 0xffff);
+}
+
+static inline unsigned int __arch_hweight8(unsigned int w)
+{
+       return __builtin_popcount(w & 0xff);
+}
+
+static inline unsigned long __arch_hweight64(__u64 w)
+{
+       return __builtin_popcountll(w);
+}
+
+#else
+#include <asm-generic/bitops/arch_hweight.h>
+#endif
+
+#endif /* _ASM_ARCH_HWEIGHT_H */
index 9255cfbee4596b2281a470a740d8bb0d493d5700..b0ce7ca2851f8fc32413e407942cc7367d6643d9 100644 (file)
@@ -700,7 +700,10 @@ static inline int ffs(int word)
 #ifdef __KERNEL__
 
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
+
+#include <asm/arch_hweight.h>
+#include <asm-generic/bitops/const_hweight.h>
+
 #include <asm-generic/bitops/ext2-non-atomic.h>
 #include <asm-generic/bitops/ext2-atomic.h>
 #include <asm-generic/bitops/minix.h>
index 09eee09780f2335b0153fe656b4aafcac8d217ec..15a8ef0707c695538fa5463d1ac05893e91f55b4 100644 (file)
 #define MACH_LEMOTE_LL2F       7
 #define MACH_LOONGSON_END      8
 
+/*
+ * Valid machtype for group INGENIC
+ */
+#define  MACH_INGENIC_JZ4730   0       /* JZ4730 SOC           */
+#define  MACH_INGENIC_JZ4740   1       /* JZ4740 SOC           */
+
 extern char *system_type;
 const char *get_system_type(void);
 
index 44437ed765e899a52caa04bd81f0c8036a9c2f64..9161e684cb4c6ce81cf9875024e0301893c8063d 100644 (file)
@@ -30,6 +30,8 @@
 #define BRK_BUG                512     /* Used by BUG() */
 #define BRK_KDB                513     /* Used in KDB_ENTER() */
 #define BRK_MEMU       514     /* Used by FPU emulator */
+#define BRK_KPROBE_BP  515     /* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
 #define BRK_MULOVF     1023    /* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
index 256ad2cc6eb8f8a4bb242ae383f50266eea47270..8f99c11ab6657d8f8ab68a61155f01b1ff20bfdb 100644 (file)
@@ -62,6 +62,8 @@
  * RM7000-specific cacheops
  */
 #define Page_Invalidate_T      0x16
+#define Index_Store_Tag_T      0x0a
+#define Index_Load_Tag_T       0x06
 
 /*
  * R10000-specific cacheops
index 6b04c98b7fad1dd5be1ff7a64e9cda1b88537835..2cb2f0c2c4f89342ae5256a79d8082f01af4d319 100644 (file)
@@ -9,6 +9,8 @@
 #ifndef __ASM_COP2_H
 #define __ASM_COP2_H
 
+#include <linux/notifier.h>
+
 enum cu2_ops {
        CU2_EXCEPTION,
        CU2_LWC2_OP,
@@ -20,4 +22,14 @@ enum cu2_ops {
 extern int register_cu2_notifier(struct notifier_block *nb);
 extern int cu2_notifier_call_chain(unsigned long val, void *v);
 
+#define cu2_notifier(fn, pri)                                          \
+({                                                                     \
+       static struct notifier_block fn##_nb __cpuinitdata = {          \
+               .notifier_call = fn,                                    \
+               .priority = pri                                         \
+       };                                                              \
+                                                                       \
+       register_cu2_notifier(&fn##_nb);                                \
+})
+
 #endif /* __ASM_COP2_H */
index ac73cede3a0a5eec6487b97433e618daa5efea39..ca400f7c3f594944d31a7b1341b6aa04d7e4c757 100644 (file)
 
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
- * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
+ * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
 # ifndef cpu_has_clo_clz
index a5acda41694696f598c957e0a1d8124dfb7d40cf..b201a8f5b127898ff645cfe0da800158a3b6595d 100644 (file)
@@ -34,7 +34,7 @@
 #define PRID_COMP_LSI          0x080000
 #define PRID_COMP_LEXRA                0x0b0000
 #define PRID_COMP_CAVIUM       0x0d0000
-
+#define PRID_COMP_INGENIC      0xd00000
 
 /*
  * Assigned values for the product ID register.  In order to detect a
 #define PRID_IMP_CAVIUM_CN50XX 0x0600
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
+ */
+
+#define PRID_IMP_JZRISC        0x0200
+
 /*
  * Definitions for 7:0 on legacy processors
  */
@@ -219,6 +225,7 @@ enum cpu_type_enum {
        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
        CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
        CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
+       CPU_JZRISC,
 
        /*
         * MIPS64 class processors
index ea77a42c5f8cb1bfc6ae03e131b60dde810f87bf..fd1d39eb74319b60473daf46cb5e4ecf1bcacb2e 100644 (file)
@@ -372,4 +372,9 @@ extern const char *__elf_platform;
 struct linux_binprm;
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                       int uses_interp);
+
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif /* _ASM_ELF_H */
index 2afb2fe11b300a84d4332970788058b78c35eeb2..c1449d20ef0e3022e5e3ee9c229b800f4c017bbc 100644 (file)
 #define EMMA2RH_PCI_CONFIG_BASE        EMMA2RH_PCI_IO_BASE
 #define EMMA2RH_PCI_CONFIG_SIZE        EMMA2RH_PCI_IO_SIZE
 
-#define NUM_CPU_IRQ            8
 #define NUM_EMMA2RH_IRQ                96
 
-#define CPU_EMMA2RH_CASCADE    2
-#define CPU_IRQ_BASE           MIPS_CPU_IRQ_BASE
-#define EMMA2RH_IRQ_BASE       (CPU_IRQ_BASE + NUM_CPU_IRQ)
+#define EMMA2RH_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
 
 /*
  * emma2rh irq defs
  */
 
-#define EMMA2RH_IRQ_INT0       (0 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT1       (1 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT2       (2 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT3       (3 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT4       (4 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT5       (5 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT6       (6 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT7       (7 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT8       (8 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT9       (9 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT10      (10 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT11      (11 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT12      (12 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT13      (13 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT14      (14 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT15      (15 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT16      (16 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT17      (17 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT18      (18 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT19      (19 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT20      (20 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT21      (21 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT22      (22 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT23      (23 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT24      (24 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT25      (25 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT26      (26 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT27      (27 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT28      (28 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT29      (29 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT30      (30 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT31      (31 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT32      (32 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT33      (33 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT34      (34 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT35      (35 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT36      (36 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT37      (37 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT38      (38 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT39      (39 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT40      (40 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT41      (41 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT42      (42 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT43      (43 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT44      (44 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT45      (45 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT46      (46 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT47      (47 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT48      (48 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT49      (49 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT50      (50 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT51      (51 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT52      (52 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT53      (53 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT54      (54 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT55      (55 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT56      (56 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT57      (57 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT58      (58 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT59      (59 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT60      (60 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT61      (61 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT62      (62 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT63      (63 + EMMA2RH_IRQ_BASE)
-
-#define EMMA2RH_IRQ_PFUR0      EMMA2RH_IRQ_INT49
-#define EMMA2RH_IRQ_PFUR1      EMMA2RH_IRQ_INT50
-#define EMMA2RH_IRQ_PFUR2      EMMA2RH_IRQ_INT51
-#define EMMA2RH_IRQ_PIIC0      EMMA2RH_IRQ_INT56
-#define EMMA2RH_IRQ_PIIC1      EMMA2RH_IRQ_INT57
-#define EMMA2RH_IRQ_PIIC2      EMMA2RH_IRQ_INT58
+#define EMMA2RH_IRQ_INT(n)     (EMMA2RH_IRQ_BASE + (n))
+
+#define EMMA2RH_IRQ_PFUR0      EMMA2RH_IRQ_INT(49)
+#define EMMA2RH_IRQ_PFUR1      EMMA2RH_IRQ_INT(50)
+#define EMMA2RH_IRQ_PFUR2      EMMA2RH_IRQ_INT(51)
+#define EMMA2RH_IRQ_PIIC0      EMMA2RH_IRQ_INT(56)
+#define EMMA2RH_IRQ_PIIC1      EMMA2RH_IRQ_INT(57)
+#define EMMA2RH_IRQ_PIIC2      EMMA2RH_IRQ_INT(58)
 
 /*
  *  EMMA2RH Register Access
index 2618bf230248b5e1711e7a2a83bae5f7eae9f9d1..bf2d229c2dae602738fc3ff3c14274d065881fbd 100644 (file)
 #define NUM_EMMA2RH_IRQ_SW     32
 #define NUM_EMMA2RH_IRQ_GPIO   32
 
-#define EMMA2RH_SW_CASCADE     (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-#define EMMA2RH_GPIO_CASCADE   (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
+#define EMMA2RH_SW_CASCADE     (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
+#define EMMA2RH_GPIO_CASCADE   (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
 
 #define EMMA2RH_SW_IRQ_BASE    (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
 #define EMMA2RH_GPIO_IRQ_BASE  (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
 
-#define EMMA2RH_SW_IRQ_INT0    (0+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT1    (1+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT2    (2+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT3    (3+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT4    (4+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT5    (5+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT6    (6+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT7    (7+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT8    (8+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT9    (9+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT10   (10+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT11   (11+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT12   (12+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT13   (13+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT14   (14+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT15   (15+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT16   (16+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT17   (17+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT18   (18+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT19   (19+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT20   (20+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT21   (21+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT22   (22+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT23   (23+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT24   (24+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT25   (25+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT26   (26+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT27   (27+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT28   (28+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT29   (29+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT30   (30+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT31   (31+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT(n)  (EMMA2RH_SW_IRQ_BASE + (n))
 
 #define MARKEINS_PCI_IRQ_INTA  EMMA2RH_GPIO_IRQ_BASE+15
 #define MARKEINS_PCI_IRQ_INTB  EMMA2RH_GPIO_IRQ_BASE+16
index 0eaf77ffbc4f1df94606f27dccd0c1a6f9a3a882..4e332165d7b710a8e4327c7d820c66883d12b89c 100644 (file)
@@ -87,7 +87,7 @@ do {                                                                  \
        : "=r" (tmp));                                                  \
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,7 @@ do {                                                                        \
                __instruction_hazard();                                 \
 } while (0)
 
-#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
       defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
       defined(CONFIG_CPU_R5500)
 
index 6489f00731caad3e904850dbbcf8d97f30afcd10..444ff71aa0e8d2759b85fb56c6955806234ef4e0 100644 (file)
@@ -247,6 +247,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */
        unsigned int fmt : 2;
<