Blackfin arch: base SIC_IWR# programming on whether the MMR exists

base SIC_IWR# programming on whether the MMR exists
rather than having to maintain another list of processors

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1bba6030dce97e7d3521e6cf43c45e03c9118755..202494568c6c0303b76cafb279b1b06f97fc9963 100644 (file)
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1101,10 +1101,9 @@ int __init init_arch_irq(void)
            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
-       || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
+#ifdef SIC_IWR0
        bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
+# ifdef SIC_IWR1
        /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
         * will screw up the bootrom as it relies on MDMA0/1 waking it
         * up from IDLE instructions.  See this report for more info:
@@ -1114,10 +1113,8 @@ int __init init_arch_irq(void)
                bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
        else
                bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-#else
-       bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-#endif
-# ifdef CONFIG_BF54x
+# endif
+# ifdef SIC_IWR2
        bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif
 #else

diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index d3d70fd67c16190519693867521890acb95a62e9..f48a6aebb49b4e75abb7919a209c742f3e2b4369 100644 (file)
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -82,10 +82,9 @@ void bfin_pm_suspend_standby_enter(void)
 
        bfin_pm_standby_restore();
 
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561) || \
-       defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
+#ifdef SIC_IWR0
        bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
+# ifdef SIC_IWR1
        /* BF52x system reset does not properly reset SIC_IWR1 which
         * will screw up the bootrom as it relies on MDMA0/1 waking it
         * up from IDLE instructions.  See this report for more info:
@@ -95,10 +94,8 @@ void bfin_pm_suspend_standby_enter(void)
                bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
        else
                bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-#else
-       bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-#endif
-# ifdef CONFIG_BF54x
+# endif
+# ifdef SIC_IWR2
        bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif
 #else