Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
authorDavid Woodhouse <David.Woodhouse@intel.com>
Tue, 21 Oct 2008 18:42:20 +0000 (19:42 +0100)
committerDavid Woodhouse <David.Woodhouse@intel.com>
Tue, 21 Oct 2008 18:42:20 +0000 (19:42 +0100)
Conflicts:

drivers/pci/dmar.c

471 files changed:
CREDITS
Documentation/DocBook/kernel-hacking.tmpl
Documentation/MSI-HOWTO.txt
Documentation/PCI/pci.txt
Documentation/PCI/pcieaer-howto.txt
Documentation/kernel-parameters.txt
Documentation/markers.txt
Documentation/sysrq.txt
Documentation/tracepoints.txt [new file with mode: 0644]
Documentation/tracers/mmiotrace.txt
MAINTAINERS
arch/alpha/kernel/sys_sable.c
arch/arm/mach-iop13xx/include/mach/time.h
arch/arm/mach-ixp2000/ixdp2x00.c
arch/arm/mach-omap2/irq.c
arch/arm/mach-pxa/include/mach/zylonite.h
arch/arm/mach-sa1100/include/mach/ide.h [deleted file]
arch/avr32/mach-at32ap/extint.c
arch/ia64/include/asm/pci.h
arch/ia64/pci/pci.c
arch/m32r/kernel/smpboot.c
arch/parisc/Kconfig
arch/parisc/include/asm/Kbuild [moved from include/asm-parisc/Kbuild with 100% similarity]
arch/parisc/include/asm/agp.h [moved from include/asm-parisc/agp.h with 100% similarity]
arch/parisc/include/asm/asmregs.h [moved from include/asm-parisc/asmregs.h with 100% similarity]
arch/parisc/include/asm/assembly.h [moved from include/asm-parisc/assembly.h with 100% similarity]
arch/parisc/include/asm/atomic.h [moved from include/asm-parisc/atomic.h with 100% similarity]
arch/parisc/include/asm/auxvec.h [moved from include/asm-parisc/auxvec.h with 100% similarity]
arch/parisc/include/asm/bitops.h [moved from include/asm-parisc/bitops.h with 100% similarity]
arch/parisc/include/asm/bug.h [moved from include/asm-parisc/bug.h with 100% similarity]
arch/parisc/include/asm/bugs.h [moved from include/asm-parisc/bugs.h with 100% similarity]
arch/parisc/include/asm/byteorder.h [moved from include/asm-parisc/byteorder.h with 100% similarity]
arch/parisc/include/asm/cache.h [moved from include/asm-parisc/cache.h with 100% similarity]
arch/parisc/include/asm/cacheflush.h [moved from include/asm-parisc/cacheflush.h with 100% similarity]
arch/parisc/include/asm/checksum.h [moved from include/asm-parisc/checksum.h with 100% similarity]
arch/parisc/include/asm/compat.h [moved from include/asm-parisc/compat.h with 100% similarity]
arch/parisc/include/asm/compat_rt_sigframe.h [moved from include/asm-parisc/compat_rt_sigframe.h with 100% similarity]
arch/parisc/include/asm/compat_signal.h [moved from include/asm-parisc/compat_signal.h with 100% similarity]
arch/parisc/include/asm/compat_ucontext.h [moved from include/asm-parisc/compat_ucontext.h with 100% similarity]
arch/parisc/include/asm/cputime.h [moved from include/asm-parisc/cputime.h with 100% similarity]
arch/parisc/include/asm/current.h [moved from include/asm-parisc/current.h with 100% similarity]
arch/parisc/include/asm/delay.h [moved from include/asm-parisc/delay.h with 100% similarity]
arch/parisc/include/asm/device.h [moved from include/asm-parisc/device.h with 100% similarity]
arch/parisc/include/asm/div64.h [moved from include/asm-parisc/div64.h with 100% similarity]
arch/parisc/include/asm/dma-mapping.h [moved from include/asm-parisc/dma-mapping.h with 100% similarity]
arch/parisc/include/asm/dma.h [moved from include/asm-parisc/dma.h with 100% similarity]
arch/parisc/include/asm/eisa_bus.h [moved from include/asm-parisc/eisa_bus.h with 100% similarity]
arch/parisc/include/asm/eisa_eeprom.h [moved from include/asm-parisc/eisa_eeprom.h with 100% similarity]
arch/parisc/include/asm/elf.h [moved from include/asm-parisc/elf.h with 100% similarity]
arch/parisc/include/asm/emergency-restart.h [moved from include/asm-parisc/emergency-restart.h with 100% similarity]
arch/parisc/include/asm/errno.h [moved from include/asm-parisc/errno.h with 100% similarity]
arch/parisc/include/asm/fb.h [moved from include/asm-parisc/fb.h with 100% similarity]
arch/parisc/include/asm/fcntl.h [moved from include/asm-parisc/fcntl.h with 100% similarity]
arch/parisc/include/asm/fixmap.h [moved from include/asm-parisc/fixmap.h with 100% similarity]
arch/parisc/include/asm/floppy.h [moved from include/asm-parisc/floppy.h with 100% similarity]
arch/parisc/include/asm/futex.h [moved from include/asm-parisc/futex.h with 100% similarity]
arch/parisc/include/asm/grfioctl.h [moved from include/asm-parisc/grfioctl.h with 100% similarity]
arch/parisc/include/asm/hardirq.h [moved from include/asm-parisc/hardirq.h with 100% similarity]
arch/parisc/include/asm/hardware.h [moved from include/asm-parisc/hardware.h with 100% similarity]
arch/parisc/include/asm/hw_irq.h [moved from include/asm-parisc/hw_irq.h with 100% similarity]
arch/parisc/include/asm/ide.h [moved from include/asm-parisc/ide.h with 77% similarity]
arch/parisc/include/asm/io.h [moved from include/asm-parisc/io.h with 100% similarity]
arch/parisc/include/asm/ioctl.h [moved from include/asm-parisc/ioctl.h with 100% similarity]
arch/parisc/include/asm/ioctls.h [moved from include/asm-parisc/ioctls.h with 100% similarity]
arch/parisc/include/asm/ipcbuf.h [moved from include/asm-parisc/ipcbuf.h with 100% similarity]
arch/parisc/include/asm/irq.h [moved from include/asm-parisc/irq.h with 100% similarity]
arch/parisc/include/asm/irq_regs.h [moved from include/asm-parisc/irq_regs.h with 100% similarity]
arch/parisc/include/asm/kdebug.h [moved from include/asm-parisc/kdebug.h with 100% similarity]
arch/parisc/include/asm/kmap_types.h [moved from include/asm-parisc/kmap_types.h with 100% similarity]
arch/parisc/include/asm/led.h [moved from include/asm-parisc/led.h with 100% similarity]
arch/parisc/include/asm/linkage.h [moved from include/asm-parisc/linkage.h with 100% similarity]
arch/parisc/include/asm/local.h [moved from include/asm-parisc/local.h with 100% similarity]
arch/parisc/include/asm/machdep.h [moved from include/asm-parisc/machdep.h with 100% similarity]
arch/parisc/include/asm/mc146818rtc.h [moved from include/asm-parisc/mc146818rtc.h with 100% similarity]
arch/parisc/include/asm/mckinley.h [moved from include/asm-parisc/mckinley.h with 100% similarity]
arch/parisc/include/asm/mman.h [moved from include/asm-parisc/mman.h with 100% similarity]
arch/parisc/include/asm/mmu.h [moved from include/asm-parisc/mmu.h with 100% similarity]
arch/parisc/include/asm/mmu_context.h [moved from include/asm-parisc/mmu_context.h with 100% similarity]
arch/parisc/include/asm/mmzone.h [moved from include/asm-parisc/mmzone.h with 100% similarity]
arch/parisc/include/asm/module.h [moved from include/asm-parisc/module.h with 100% similarity]
arch/parisc/include/asm/msgbuf.h [moved from include/asm-parisc/msgbuf.h with 100% similarity]
arch/parisc/include/asm/mutex.h [moved from include/asm-parisc/mutex.h with 100% similarity]
arch/parisc/include/asm/page.h [moved from include/asm-parisc/page.h with 100% similarity]
arch/parisc/include/asm/param.h [moved from include/asm-parisc/param.h with 100% similarity]
arch/parisc/include/asm/parisc-device.h [moved from include/asm-parisc/parisc-device.h with 100% similarity]
arch/parisc/include/asm/parport.h [moved from include/asm-parisc/parport.h with 100% similarity]
arch/parisc/include/asm/pci.h [moved from include/asm-parisc/pci.h with 100% similarity]
arch/parisc/include/asm/pdc.h [moved from include/asm-parisc/pdc.h with 99% similarity]
arch/parisc/include/asm/pdc_chassis.h [moved from include/asm-parisc/pdc_chassis.h with 100% similarity]
arch/parisc/include/asm/pdcpat.h [moved from include/asm-parisc/pdcpat.h with 100% similarity]
arch/parisc/include/asm/percpu.h [moved from include/asm-parisc/percpu.h with 100% similarity]
arch/parisc/include/asm/perf.h [moved from include/asm-parisc/perf.h with 100% similarity]
arch/parisc/include/asm/pgalloc.h [moved from include/asm-parisc/pgalloc.h with 100% similarity]
arch/parisc/include/asm/pgtable.h [moved from include/asm-parisc/pgtable.h with 100% similarity]
arch/parisc/include/asm/poll.h [moved from include/asm-parisc/poll.h with 100% similarity]
arch/parisc/include/asm/posix_types.h [moved from include/asm-parisc/posix_types.h with 100% similarity]
arch/parisc/include/asm/prefetch.h [moved from include/asm-parisc/prefetch.h with 100% similarity]
arch/parisc/include/asm/processor.h [moved from include/asm-parisc/processor.h with 100% similarity]
arch/parisc/include/asm/psw.h [moved from include/asm-parisc/psw.h with 100% similarity]
arch/parisc/include/asm/ptrace.h [moved from include/asm-parisc/ptrace.h with 85% similarity]
arch/parisc/include/asm/real.h [moved from include/asm-parisc/real.h with 100% similarity]
arch/parisc/include/asm/resource.h [moved from include/asm-parisc/resource.h with 100% similarity]
arch/parisc/include/asm/ropes.h [moved from include/asm-parisc/ropes.h with 99% similarity]
arch/parisc/include/asm/rt_sigframe.h [moved from include/asm-parisc/rt_sigframe.h with 100% similarity]
arch/parisc/include/asm/rtc.h [moved from include/asm-parisc/rtc.h with 100% similarity]
arch/parisc/include/asm/runway.h [moved from include/asm-parisc/runway.h with 100% similarity]
arch/parisc/include/asm/scatterlist.h [moved from include/asm-parisc/scatterlist.h with 100% similarity]
arch/parisc/include/asm/sections.h [moved from include/asm-parisc/sections.h with 100% similarity]
arch/parisc/include/asm/segment.h [moved from include/asm-parisc/segment.h with 100% similarity]
arch/parisc/include/asm/sembuf.h [moved from include/asm-parisc/sembuf.h with 100% similarity]
arch/parisc/include/asm/serial.h [moved from include/asm-parisc/serial.h with 100% similarity]
arch/parisc/include/asm/setup.h [moved from include/asm-parisc/setup.h with 100% similarity]
arch/parisc/include/asm/shmbuf.h [moved from include/asm-parisc/shmbuf.h with 100% similarity]
arch/parisc/include/asm/shmparam.h [moved from include/asm-parisc/shmparam.h with 100% similarity]
arch/parisc/include/asm/sigcontext.h [moved from include/asm-parisc/sigcontext.h with 100% similarity]
arch/parisc/include/asm/siginfo.h [moved from include/asm-parisc/siginfo.h with 100% similarity]
arch/parisc/include/asm/signal.h [moved from include/asm-parisc/signal.h with 100% similarity]
arch/parisc/include/asm/smp.h [moved from include/asm-parisc/smp.h with 100% similarity]
arch/parisc/include/asm/socket.h [moved from include/asm-parisc/socket.h with 100% similarity]
arch/parisc/include/asm/sockios.h [moved from include/asm-parisc/sockios.h with 100% similarity]
arch/parisc/include/asm/spinlock.h [moved from include/asm-parisc/spinlock.h with 100% similarity]
arch/parisc/include/asm/spinlock_types.h [moved from include/asm-parisc/spinlock_types.h with 100% similarity]
arch/parisc/include/asm/stat.h [moved from include/asm-parisc/stat.h with 100% similarity]
arch/parisc/include/asm/statfs.h [moved from include/asm-parisc/statfs.h with 100% similarity]
arch/parisc/include/asm/string.h [moved from include/asm-parisc/string.h with 100% similarity]
arch/parisc/include/asm/superio.h [moved from include/asm-parisc/superio.h with 100% similarity]
arch/parisc/include/asm/system.h [moved from include/asm-parisc/system.h with 100% similarity]
arch/parisc/include/asm/termbits.h [moved from include/asm-parisc/termbits.h with 100% similarity]
arch/parisc/include/asm/termios.h [moved from include/asm-parisc/termios.h with 100% similarity]
arch/parisc/include/asm/thread_info.h [moved from include/asm-parisc/thread_info.h with 100% similarity]
arch/parisc/include/asm/timex.h [moved from include/asm-parisc/timex.h with 100% similarity]
arch/parisc/include/asm/tlb.h [moved from include/asm-parisc/tlb.h with 100% similarity]
arch/parisc/include/asm/tlbflush.h [moved from include/asm-parisc/tlbflush.h with 100% similarity]
arch/parisc/include/asm/topology.h [moved from include/asm-parisc/topology.h with 100% similarity]
arch/parisc/include/asm/traps.h [moved from include/asm-parisc/traps.h with 100% similarity]
arch/parisc/include/asm/types.h [moved from include/asm-parisc/types.h with 100% similarity]
arch/parisc/include/asm/uaccess.h [moved from include/asm-parisc/uaccess.h with 100% similarity]
arch/parisc/include/asm/ucontext.h [moved from include/asm-parisc/ucontext.h with 100% similarity]
arch/parisc/include/asm/unaligned.h [moved from include/asm-parisc/unaligned.h with 100% similarity]
arch/parisc/include/asm/unistd.h [moved from include/asm-parisc/unistd.h with 99% similarity]
arch/parisc/include/asm/unwind.h [moved from include/asm-parisc/unwind.h with 99% similarity]
arch/parisc/include/asm/user.h [moved from include/asm-parisc/user.h with 100% similarity]
arch/parisc/include/asm/vga.h [moved from include/asm-parisc/vga.h with 100% similarity]
arch/parisc/include/asm/xor.h [moved from include/asm-parisc/xor.h with 100% similarity]
arch/parisc/kernel/.gitignore [new file with mode: 0644]
arch/parisc/kernel/asm-offsets.c
arch/parisc/kernel/firmware.c
arch/parisc/kernel/head.S
arch/parisc/kernel/ptrace.c
arch/parisc/kernel/real2.S
arch/parisc/kernel/setup.c
arch/parisc/kernel/syscall_table.S
arch/parisc/kernel/time.c
arch/parisc/kernel/unwind.c
arch/powerpc/include/asm/page.h
arch/powerpc/include/asm/pci-bridge.h
arch/powerpc/include/asm/pci.h
arch/powerpc/include/asm/ptrace.h
arch/powerpc/kernel/pci-common.c
arch/powerpc/platforms/cell/spufs/sputrace.c
arch/x86/Kconfig
arch/x86/configs/i386_defconfig
arch/x86/kernel/Makefile
arch/x86/kernel/acpi/boot.c
arch/x86/kernel/acpi/sleep.c
arch/x86/kernel/apic.c [moved from arch/x86/kernel/apic_32.c with 79% similarity]
arch/x86/kernel/apic_64.c [deleted file]
arch/x86/kernel/bios_uv.c
arch/x86/kernel/cpu/amd.c
arch/x86/kernel/cpu/cpufreq/longhaul.c
arch/x86/kernel/cpu/cpufreq/powernow-k6.c
arch/x86/kernel/cpu/cpufreq/powernow-k7.c
arch/x86/kernel/cpu/cpufreq/powernow-k8.c
arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
arch/x86/kernel/cpu/intel.c
arch/x86/kernel/cpu/mcheck/k7.c
arch/x86/kernel/cpu/mcheck/mce_32.c
arch/x86/kernel/cpu/mcheck/non-fatal.c
arch/x86/kernel/cpu/perfctr-watchdog.c
arch/x86/kernel/efi.c
arch/x86/kernel/entry_32.S
arch/x86/kernel/entry_64.S
arch/x86/kernel/ftrace.c
arch/x86/kernel/genapic_flat_64.c
arch/x86/kernel/genx2apic_uv_x.c
arch/x86/kernel/hpet.c
arch/x86/kernel/io_apic.c [moved from arch/x86/kernel/io_apic_64.c with 68% similarity]
arch/x86/kernel/io_apic_32.c [deleted file]
arch/x86/kernel/irq.c [new file with mode: 0644]
arch/x86/kernel/irq_32.c
arch/x86/kernel/irq_64.c
arch/x86/kernel/irqinit_32.c
arch/x86/kernel/irqinit_64.c
arch/x86/kernel/quirks.c
arch/x86/kernel/setup.c
arch/x86/kernel/setup_percpu.c
arch/x86/kernel/smpboot.c
arch/x86/kernel/uv_irq.c [new file with mode: 0644]
arch/x86/kernel/uv_sysfs.c [new file with mode: 0644]
arch/x86/kernel/visws_quirks.c
arch/x86/kernel/vmiclock_32.c
arch/x86/lguest/boot.c
arch/x86/mach-generic/bigsmp.c
arch/x86/mach-generic/es7000.c
arch/x86/mach-generic/numaq.c
arch/x86/mach-generic/summit.c
arch/x86/mach-voyager/voyager_smp.c
arch/x86/mm/mmio-mod.c
arch/x86/mm/pf_in.c
arch/x86/mm/testmmiotrace.c
arch/x86/pci/irq.c
arch/x86/xen/irq.c
arch/x86/xen/spinlock.c
crypto/async_tx/async_tx.c
drivers/char/agp/ali-agp.c
drivers/char/agp/amd64-agp.c
drivers/char/agp/ati-agp.c
drivers/char/agp/backend.c
drivers/char/agp/intel-agp.c
drivers/char/agp/nvidia-agp.c
drivers/char/agp/parisc-agp.c
drivers/char/agp/via-agp.c
drivers/char/hpet.c
drivers/char/random.c
drivers/char/sysrq.c
drivers/char/vr41xx_giu.c
drivers/clocksource/acpi_pm.c
drivers/dma/Kconfig
drivers/dma/dmatest.c
drivers/dma/fsldma.c
drivers/dma/fsldma.h
drivers/dma/ioat_dma.c
drivers/gpio/gpiolib.c
drivers/gpu/drm/Kconfig
drivers/gpu/drm/drm_proc.c
drivers/gpu/drm/i915/i915_gem.c
drivers/i2c/busses/i2c-amd756.c
drivers/i2c/busses/i2c-viapro.c
drivers/ide/Kconfig
drivers/ide/Makefile
drivers/ide/ide-atapi.c
drivers/ide/ide-cd.c
drivers/ide/ide-cd_ioctl.c
drivers/ide/ide-disk.c
drivers/ide/ide-disk.h
drivers/ide/ide-disk_ioctl.c
drivers/ide/ide-disk_proc.c
drivers/ide/ide-dma-sff.c
drivers/ide/ide-floppy.c
drivers/ide/ide-floppy.h
drivers/ide/ide-floppy_ioctl.c
drivers/ide/ide-floppy_proc.c
drivers/ide/ide-gd.c [new file with mode: 0644]
drivers/ide/ide-gd.h [new file with mode: 0644]
drivers/ide/ide-iops.c
drivers/ide/ide-probe.c
drivers/ide/ide-proc.c
drivers/ide/ide-tape.c
drivers/ide/pci/Makefile
drivers/ide/pci/delkin_cb.c
drivers/ide/pci/hpt34x.c [deleted file]
drivers/ide/pci/hpt366.c
drivers/ide/pci/scc_pata.c
drivers/ide/pci/sgiioc4.c
drivers/leds/Kconfig
drivers/mfd/asic3.c
drivers/mfd/htc-egpio.c
drivers/net/3c59x.c
drivers/net/hamradio/baycom_ser_fdx.c
drivers/net/hamradio/scc.c
drivers/net/usb/pegasus.c
drivers/net/wan/sbni.c
drivers/parisc/ccio-dma.c
drivers/parisc/dino.c
drivers/parisc/eisa.c
drivers/parisc/gsc.c
drivers/parisc/iosapic.c
drivers/parisc/superio.c
drivers/pci/bus.c
drivers/pci/dmar.c
drivers/pci/hotplug/ibmphp_ebda.c
drivers/pci/hotplug/pci_hotplug_core.c
drivers/pci/hotplug/pciehp.h
drivers/pci/hotplug/pciehp_core.c
drivers/pci/hotplug/pciehp_ctrl.c
drivers/pci/hotplug/pciehp_hpc.c
drivers/pci/hotplug/pciehp_pci.c
drivers/pci/hotplug/rpaphp.h
drivers/pci/hotplug/rpaphp_core.c
drivers/pci/hotplug/rpaphp_pci.c
drivers/pci/htirq.c
drivers/pci/intr_remapping.c
drivers/pci/msi.c
drivers/pci/pci-driver.c
drivers/pci/pci-sysfs.c
drivers/pci/pci.c
drivers/pci/pci.h
drivers/pci/pcie/aer/aerdrv.c
drivers/pci/pcie/aer/aerdrv_core.c
drivers/pci/pcie/aspm.c
drivers/pci/pcie/portdrv.h
drivers/pci/pcie/portdrv_core.c
drivers/pci/pcie/portdrv_pci.c
drivers/pci/probe.c
drivers/pci/quirks.c
drivers/pci/remove.c
drivers/pci/setup-bus.c
drivers/pci/setup-res.c
drivers/pci/slot.c
drivers/pcmcia/at91_cf.c
drivers/pcmcia/hd64465_ss.c
drivers/pcmcia/vrc4171_card.c
drivers/rtc/Kconfig
drivers/rtc/Makefile
drivers/rtc/rtc-parisc.c [new file with mode: 0644]
drivers/rtc/rtc-vr41xx.c
drivers/scsi/aha152x.c
drivers/scsi/ide-scsi.c
drivers/scsi/ipr.c
drivers/scsi/qla2xxx/qla_def.h
drivers/scsi/qla2xxx/qla_os.c
drivers/serial/68328serial.c
drivers/serial/8250.c
drivers/serial/amba-pl010.c
drivers/serial/amba-pl011.c
drivers/serial/cpm_uart/cpm_uart_core.c
drivers/serial/m32r_sio.c
drivers/serial/serial_core.c
drivers/serial/serial_lh7a40x.c
drivers/serial/sh-sci.c
drivers/serial/ucc_uart.c
drivers/uio/uio.c
drivers/usb/host/ehci-hcd.c
drivers/watchdog/ib700wdt.c
drivers/xen/events.c
fs/Kconfig
fs/binfmt_elf.c
fs/binfmt_elf_fdpic.c
fs/fuse/file.c
fs/fuse/fuse_i.h
fs/fuse/inode.c
fs/proc/array.c
fs/proc/proc_misc.c
include/asm-frv/ide.h
include/asm-generic/bug.h
include/asm-generic/vmlinux.lds.h
include/asm-m68k/ide.h
include/asm-x86/apic.h
include/asm-x86/bigsmp/apic.h
include/asm-x86/efi.h
include/asm-x86/es7000/apic.h
include/asm-x86/ftrace.h
include/asm-x86/genapic_32.h
include/asm-x86/hpet.h
include/asm-x86/hw_irq.h
include/asm-x86/io_apic.h
include/asm-x86/irq_vectors.h
include/asm-x86/mach-default/entry_arch.h
include/asm-x86/mach-default/mach_apic.h
include/asm-x86/mach-generic/irq_vectors_limits.h [deleted file]
include/asm-x86/mach-generic/mach_apic.h
include/asm-x86/numaq/apic.h
include/asm-x86/summit/apic.h
include/asm-x86/summit/irq_vectors_limits.h [deleted file]
include/asm-x86/uv/bios.h
include/asm-x86/uv/uv_irq.h [new file with mode: 0644]
include/linux/aer.h
include/linux/clocksource.h
include/linux/compiler.h
include/linux/dmar.h
include/linux/efi.h
include/linux/ftrace.h
include/linux/fuse.h
include/linux/hrtimer.h
include/linux/ide.h
include/linux/init.h
include/linux/interrupt.h
include/linux/irq.h
include/linux/irqnr.h [new file with mode: 0644]
include/linux/kernel.h
include/linux/kernel_stat.h
include/linux/kprobes.h
include/linux/linkage.h
include/linux/marker.h
include/linux/mmiotrace.h
include/linux/module.h
include/linux/pci.h
include/linux/pci_ids.h
include/linux/pci_regs.h
include/linux/posix-timers.h
include/linux/ring_buffer.h [new file with mode: 0644]
include/linux/sched.h
include/linux/tick.h
include/linux/time.h
include/linux/timex.h
include/linux/tracepoint.h [new file with mode: 0644]
include/trace/sched.h [new file with mode: 0644]
init/Kconfig
init/main.c
kernel/Makefile
kernel/compat.c
kernel/exit.c
kernel/fork.c
kernel/hrtimer.c
kernel/irq/autoprobe.c
kernel/irq/chip.c
kernel/irq/handle.c
kernel/irq/internals.h
kernel/irq/manage.c
kernel/irq/migration.c
kernel/irq/proc.c
kernel/irq/resend.c
kernel/irq/spurious.c
kernel/itimer.c
kernel/kexec.c
kernel/kthread.c
kernel/marker.c
kernel/module.c
kernel/notifier.c
kernel/posix-cpu-timers.c
kernel/posix-timers.c
kernel/rcutorture.c
kernel/sched.c
kernel/sched_fair.c
kernel/sched_rt.c
kernel/sched_stats.h
kernel/signal.c
kernel/softirq.c
kernel/sys.c
kernel/time/clocksource.c
kernel/time/jiffies.c
kernel/time/ntp.c
kernel/time/tick-broadcast.c
kernel/time/tick-internal.h
kernel/time/tick-sched.c
kernel/time/timekeeping.c
kernel/time/timer_list.c
kernel/timer.c
kernel/trace/Kconfig
kernel/trace/Makefile
kernel/trace/ftrace.c
kernel/trace/ring_buffer.c [new file with mode: 0644]
kernel/trace/trace.c
kernel/trace/trace.h
kernel/trace/trace_boot.c [new file with mode: 0644]
kernel/trace/trace_functions.c
kernel/trace/trace_irqsoff.c
kernel/trace/trace_mmiotrace.c
kernel/trace/trace_nop.c [new file with mode: 0644]
kernel/trace/trace_sched_switch.c
kernel/trace/trace_sched_wakeup.c
kernel/trace/trace_selftest.c
kernel/trace/trace_stack.c [new file with mode: 0644]
kernel/trace/trace_sysprof.c
kernel/tracepoint.c [new file with mode: 0644]
mm/memory.c
mm/tiny-shmem.c
mm/vmalloc.c
samples/Kconfig
samples/Makefile
samples/markers/probe-example.c
samples/tracepoints/Makefile [new file with mode: 0644]
samples/tracepoints/tp-samples-trace.h [new file with mode: 0644]
samples/tracepoints/tracepoint-probe-sample.c [new file with mode: 0644]
samples/tracepoints/tracepoint-probe-sample2.c [new file with mode: 0644]
samples/tracepoints/tracepoint-sample.c [new file with mode: 0644]
scripts/Makefile.build
scripts/bootgraph.pl
scripts/checkpatch.pl
scripts/recordmcount.pl [new file with mode: 0755]
security/selinux/hooks.c

diff --git a/CREDITS b/CREDITS
index c62dcb3b7e2621d918815a656f2682fda044afcb..2358846f06be53807ccbd54b2e3615eb5814c4dc 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -1653,14 +1653,14 @@ S: Chapel Hill, North Carolina 27514-4818
 S: USA
 
 N: Dave Jones
-E: davej@codemonkey.org.uk
+E: davej@redhat.com
 W: http://www.codemonkey.org.uk
-D: x86 errata/setup maintenance.
-D: AGPGART driver.
+D: Assorted VIA x86 support.
+D: 2.5 AGPGART overhaul.
 D: CPUFREQ maintenance.
-D: Backport/Forwardport merge monkey.
-D: Various Janitor work.
-S: United Kingdom
+D: Fedora kernel maintainence.
+D: Misc/Other.
+S: 314 Littleton Rd, Westford, MA 01886, USA
 
 N: Martin Josfsson
 E: gandalf@wlug.westbo.se
index 4c63e5864160f159fd073039ba80efefb161ff68..ae15d55350ec8bf93e2eb79dac2ee730cd6de054 100644 (file)
@@ -1105,7 +1105,7 @@ static struct block_device_operations opt_fops = {
     </listitem>
     <listitem>
      <para>
-      Function names as strings (__FUNCTION__).
+      Function names as strings (__func__).
      </para>
     </listitem>
     <listitem>
index a51f693c15419e9b2da87df025b69d898f648b51..256defd7e1742be45497e1bcc8912d493241c5af 100644 (file)
@@ -236,10 +236,8 @@ software system can set different pages for controlling accesses to the
 MSI-X structure. The implementation of MSI support requires the PCI
 subsystem, not a device driver, to maintain full control of the MSI-X
 table/MSI-X PBA (Pending Bit Array) and MMIO address space of the MSI-X
-table/MSI-X PBA.  A device driver is prohibited from requesting the MMIO
-address space of the MSI-X table/MSI-X PBA. Otherwise, the PCI subsystem
-will fail enabling MSI-X on its hardware device when it calls the function
-pci_enable_msix().
+table/MSI-X PBA.  A device driver should not access the MMIO address
+space of the MSI-X table/MSI-X PBA.
 
 5.3.2 API pci_enable_msix
 
index 8d4dc6250c582821ccca5b89127833e2b14bd4ee..fd4907a2968cb3fab71e92286c24da0244dcfcae 100644 (file)
@@ -163,6 +163,10 @@ need pass only as many optional fields as necessary:
        o class and classmask fields default to 0
        o driver_data defaults to 0UL.
 
+Note that driver_data must match the value used by any of the pci_device_id
+entries defined in the driver. This makes the driver_data field mandatory
+if all the pci_device_id entries have a non-zero driver_data value.
+
 Once added, the driver probe routine will be invoked for any unclaimed
 PCI devices listed in its (newly updated) pci_ids list.
 
index 16c251230c82398a1ad26a3754762e49fc819922..ddeb14beacc8fe8592334ba11303ef6fcd2a7404 100644 (file)
@@ -203,22 +203,17 @@ to mmio_enabled.
 
 3.3 helper functions
 
-3.3.1 int pci_find_aer_capability(struct pci_dev *dev);
-pci_find_aer_capability locates the PCI Express AER capability
-in the device configuration space. If the device doesn't support
-PCI-Express AER, the function returns 0.
-
-3.3.2 int pci_enable_pcie_error_reporting(struct pci_dev *dev);
+3.3.1 int pci_enable_pcie_error_reporting(struct pci_dev *dev);
 pci_enable_pcie_error_reporting enables the device to send error
 messages to root port when an error is detected. Note that devices
 don't enable the error reporting by default, so device drivers need
 call this function to enable it.
 
-3.3.3 int pci_disable_pcie_error_reporting(struct pci_dev *dev);
+3.3.2 int pci_disable_pcie_error_reporting(struct pci_dev *dev);
 pci_disable_pcie_error_reporting disables the device to send error
 messages to root port when an error is detected.
 
-3.3.4 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
+3.3.3 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
 pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable
 error status register.
 
index 0f1544f67400b4288887649bf73b9fb09449b92c..53ba7c7d82b342d50053f6458225b29123bee747 100644 (file)
@@ -101,6 +101,7 @@ parameter is applicable:
        X86-64  X86-64 architecture is enabled.
                        More X86-64 boot options can be found in
                        Documentation/x86_64/boot-options.txt .
+       X86     Either 32bit or 64bit x86 (same as X86-32+X86-64)
 
 In addition, the following text indicates that the option:
 
@@ -1588,7 +1589,7 @@ and is between 256 and 4096 characters. It is defined in the file
                        See also Documentation/paride.txt.
 
        pci=option[,option...]  [PCI] various PCI subsystem options:
-               off             [X86-32] don't probe for the PCI bus
+               off             [X86] don't probe for the PCI bus
                bios            [X86-32] force use of PCI BIOS, don't access
                                the hardware directly. Use this if your machine
                                has a non-standard PCI host bridge.
@@ -1596,9 +1597,9 @@ and is between 256 and 4096 characters. It is defined in the file
                                hardware access methods are allowed. Use this
                                if you experience crashes upon bootup and you
                                suspect they are caused by the BIOS.
-               conf1           [X86-32] Force use of PCI Configuration
+               conf1           [X86] Force use of PCI Configuration
                                Mechanism 1.
-               conf2           [X86-32] Force use of PCI Configuration
+               conf2           [X86] Force use of PCI Configuration
                                Mechanism 2.
                noaer           [PCIE] If the PCIEAER kernel config parameter is
                                enabled, this kernel boot option can be used to
@@ -1618,37 +1619,37 @@ and is between 256 and 4096 characters. It is defined in the file
                                this option if the kernel is unable to allocate
                                IRQs or discover secondary PCI buses on your
                                motherboard.
-               rom             [X86-32] Assign address space to expansion ROMs.
+               rom             [X86] Assign address space to expansion ROMs.
                                Use with caution as certain devices share
                                address decoders between ROMs and other
                                resources.
-               norom           [X86-32,X86_64] Do not assign address space to
+               norom           [X86] Do not assign address space to
                                expansion ROMs that do not already have
                                BIOS assigned address ranges.
-               irqmask=0xMMMM  [X86-32] Set a bit mask of IRQs allowed to be
+               irqmask=0xMMMM  [X86] Set a bit mask of IRQs allowed to be
                                assigned automatically to PCI devices. You can
                                make the kernel exclude IRQs of your ISA cards
                                this way.
-               pirqaddr=0xAAAAA        [X86-32] Specify the physical address
+               pirqaddr=0xAAAAA        [X86] Specify the physical address
                                of the PIRQ table (normally generated
                                by the BIOS) if it is outside the
                                F0000h-100000h range.
-               lastbus=N       [X86-32] Scan all buses thru bus #N. Can be
+               lastbus=N       [X86] Scan all buses thru bus #N. Can be
                                useful if the kernel is unable to find your
                                secondary buses and you want to tell it
                                explicitly which ones they are.
-               assign-busses   [X86-32] Always assign all PCI bus
+               assign-busses   [X86] Always assign all PCI bus
                                numbers ourselves, overriding
                                whatever the firmware may have done.
-               usepirqmask     [X86-32] Honor the possible IRQ mask stored
+               usepirqmask     [X86] Honor the possible IRQ mask stored
                                in the BIOS $PIR table. This is needed on
                                some systems with broken BIOSes, notably
                                some HP Pavilion N5400 and Omnibook XE3
                                notebooks. This will have no effect if ACPI
                                IRQ routing is enabled.
-               noacpi          [X86-32] Do not use ACPI for IRQ routing
+               noacpi          [X86] Do not use ACPI for IRQ routing
                                or for PCI scanning.
-               use_crs         [X86-32] Use _CRS for PCI resource
+               use_crs         [X86] Use _CRS for PCI resource
                                allocation.
                routeirq        Do IRQ routing for all PCI devices.
                                This is normally done in pci_enable_device(),
@@ -1677,6 +1678,12 @@ and is between 256 and 4096 characters. It is defined in the file
                                reserved for the CardBus bridge's memory
                                window. The default value is 64 megabytes.
 
+       pcie_aspm=      [PCIE] Forcibly enable or disable PCIe Active State Power
+                       Management.
+               off     Disable ASPM.
+               force   Enable ASPM even on devices that claim not to support it.
+                       WARNING: Forcing ASPM on may cause system lockups.
+
        pcmv=           [HW,PCMCIA] BadgePAD 4
 
        pd.             [PARIDE]
index d9f50a19fa0c48185968e875aa2c9163bae3e6fa..089f6138fcd94249a6444ca3a932a50c263098e1 100644 (file)
@@ -50,10 +50,12 @@ Connecting a function (probe) to a marker is done by providing a probe (function
 to call) for the specific marker through marker_probe_register() and can be
 activated by calling marker_arm(). Marker deactivation can be done by calling
 marker_disarm() as many times as marker_arm() has been called. Removing a probe
-is done through marker_probe_unregister(); it will disarm the probe and make
-sure there is no caller left using the probe when it returns. Probe removal is
-preempt-safe because preemption is disabled around the probe call. See the
-"Probe example" section below for a sample probe module.
+is done through marker_probe_unregister(); it will disarm the probe.
+marker_synchronize_unregister() must be called before the end of the module exit
+function to make sure there is no caller left using the probe. This, and the
+fact that preemption is disabled around the probe call, make sure that probe
+removal and module unload are safe. See the "Probe example" section below for a
+sample probe module.
 
 The marker mechanism supports inserting multiple instances of the same marker.
 Markers can be put in inline functions, inlined static functions, and
index 49378a9f2b5f276c4a050e76b0898c25a74303e0..10a0263ebb3f01e832c7827cc75d7fe54b341a6f 100644 (file)
@@ -95,8 +95,9 @@ On all -  write a character to /proc/sysrq-trigger.  e.g.:
 
 'p'     - Will dump the current registers and flags to your console.
 
-'q'     - Will dump a list of all running hrtimers.
-         WARNING: Does not cover any other timers
+'q'     - Will dump per CPU lists of all armed hrtimers (but NOT regular
+          timer_list timers) and detailed information about all
+          clockevent devices.
 
 'r'     - Turns off keyboard raw mode and sets it to XLATE.
 
diff --git a/Documentation/tracepoints.txt b/Documentation/tracepoints.txt
new file mode 100644 (file)
index 0000000..5d354e1
--- /dev/null
@@ -0,0 +1,101 @@
+                    Using the Linux Kernel Tracepoints
+
+                           Mathieu Desnoyers
+
+
+This document introduces Linux Kernel Tracepoints and their use. It provides
+examples of how to insert tracepoints in the kernel and connect probe functions
+to them and provides some examples of probe functions.
+
+
+* Purpose of tracepoints
+
+A tracepoint placed in code provides a hook to call a function (probe) that you
+can provide at runtime. A tracepoint can be "on" (a probe is connected to it) or
+"off" (no probe is attached). When a tracepoint is "off" it has no effect,
+except for adding a tiny time penalty (checking a condition for a branch) and
+space penalty (adding a few bytes for the function call at the end of the
+instrumented function and adds a data structure in a separate section).  When a
+tracepoint is "on", the function you provide is called each time the tracepoint
+is executed, in the execution context of the caller. When the function provided
+ends its execution, it returns to the caller (continuing from the tracepoint
+site).
+
+You can put tracepoints at important locations in the code. They are
+lightweight hooks that can pass an arbitrary number of parameters,
+which prototypes are described in a tracepoint declaration placed in a header
+file.
+
+They can be used for tracing and performance accounting.
+
+
+* Usage
+
+Two elements are required for tracepoints :
+
+- A tracepoint definition, placed in a header file.
+- The tracepoint statement, in C code.
+
+In order to use tracepoints, you should include linux/tracepoint.h.
+
+In include/trace/subsys.h :
+
+#include <linux/tracepoint.h>
+
+DEFINE_TRACE(subsys_eventname,
+       TPPTOTO(int firstarg, struct task_struct *p),
+       TPARGS(firstarg, p));
+
+In subsys/file.c (where the tracing statement must be added) :
+
+#include <trace/subsys.h>
+
+void somefct(void)
+{
+       ...
+       trace_subsys_eventname(arg, task);
+       ...
+}
+
+Where :
+- subsys_eventname is an identifier unique to your event
+    - subsys is the name of your subsystem.
+    - eventname is the name of the event to trace.
+- TPPTOTO(int firstarg, struct task_struct *p) is the prototype of the function
+  called by this tracepoint.
+- TPARGS(firstarg, p) are the parameters names, same as found in the prototype.
+
+Connecting a function (probe) to a tracepoint is done by providing a probe
+(function to call) for the specific tracepoint through
+register_trace_subsys_eventname().  Removing a probe is done through
+unregister_trace_subsys_eventname(); it will remove the probe sure there is no
+caller left using the probe when it returns. Probe removal is preempt-safe
+because preemption is disabled around the probe call. See the "Probe example"
+section below for a sample probe module.
+
+The tracepoint mechanism supports inserting multiple instances of the same
+tracepoint, but a single definition must be made of a given tracepoint name over
+all the kernel to make sure no type conflict will occur. Name mangling of the
+tracepoints is done using the prototypes to make sure typing is correct.
+Verification of probe type correctness is done at the registration site by the
+compiler. Tracepoints can be put in inline functions, inlined static functions,
+and unrolled loops as well as regular functions.
+
+The naming scheme "subsys_event" is suggested here as a convention intended
+to limit collisions. Tracepoint names are global to the kernel: they are
+considered as being the same whether they are in the core kernel image or in
+modules.
+
+
+* Probe / tracepoint example
+
+See the example provided in samples/tracepoints/src
+
+Compile them with your kernel.
+
+Run, as root :
+modprobe tracepoint-example (insmod order is not important)
+modprobe tracepoint-probe-example
+cat /proc/tracepoint-example (returns an expected error)
+rmmod tracepoint-example tracepoint-probe-example
+dmesg
index a4afb560a45bfa9c7429f18d54d0f8b4c194b116..5bbbe2096223f69bc1f0d7007f6d07a3385e4fd4 100644 (file)
@@ -36,7 +36,7 @@ $ mount -t debugfs debugfs /debug
 $ echo mmiotrace > /debug/tracing/current_tracer
 $ cat /debug/tracing/trace_pipe > mydump.txt &
 Start X or whatever.
-$ echo "X is up" > /debug/tracing/marker
+$ echo "X is up" > /debug/tracing/trace_marker
 $ echo none > /debug/tracing/current_tracer
 Check for lost events.
 
@@ -59,9 +59,8 @@ The 'cat' process should stay running (sleeping) in the background.
 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
 accesses to areas that are ioremapped while mmiotrace is active.
 
-[Unimplemented feature:]
 During tracing you can place comments (markers) into the trace by
-$ echo "X is up" > /debug/tracing/marker
+$ echo "X is up" > /debug/tracing/trace_marker
 This makes it easier to see which part of the (huge) trace corresponds to
 which action. It is recommended to place descriptive markers about what you
 do.
index 22303e5fe4ce41986bc14a6b2a68cc20b418f845..6d51f00dcdc0ba8349469d04005bb8435463f8e2 100644 (file)
@@ -1198,7 +1198,7 @@ S:        Maintained
 
 CPU FREQUENCY DRIVERS
 P:     Dave Jones
-M:     davej@codemonkey.org.uk
+M:     davej@redhat.com
 L:     cpufreq@vger.kernel.org
 W:     http://www.codemonkey.org.uk/projects/cpufreq/
 T:     git kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git
index 99a7f19da13aae935ae8b25ca9a590e8d5e02272..a4555f497639fa0c68e7da3e0284ce221005cee9 100644 (file)
@@ -47,7 +47,7 @@ typedef struct irq_swizzle_struct
 
 static irq_swizzle_t *sable_lynx_irq_swizzle;
 
-static void sable_lynx_init_irq(int nr_irqs);
+static void sable_lynx_init_irq(int nr_of_irqs);
 
 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
 
@@ -530,11 +530,11 @@ sable_lynx_srm_device_interrupt(unsigned long vector)
 }
 
 static void __init
-sable_lynx_init_irq(int nr_irqs)
+sable_lynx_init_irq(int nr_of_irqs)
 {
        long i;
 
-       for (i = 0; i < nr_irqs; ++i) {
+       for (i = 0; i < nr_of_irqs; ++i) {
                irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
                irq_desc[i].chip = &sable_lynx_irq_type;
        }
index 49213d9d7cad5c6538f4999de573fe2d50e2b82d..d6d52527589dc7c6ad1f45053b8f2a08e7d3dfc6 100644 (file)
@@ -41,7 +41,7 @@ static inline unsigned long iop13xx_core_freq(void)
                return 1200000000;
        default:
                printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
-                       __FUNCTION__);
+                       __func__);
        }
 
        return 800000000;
@@ -60,7 +60,7 @@ static inline unsigned long iop13xx_xsi_bus_ratio(void)
                return 4;
        default:
                printk("%s: warning unknown ratio, defaulting to 2\n",
-                       __FUNCTION__);
+                       __func__);
        }
 
        return 2;
index b0653a87159a89b36b67da7674b8163e80439f0e..30451300751beb360ca41cf6e6f46814db1215f9 100644 (file)
@@ -143,7 +143,7 @@ static struct irq_chip ixdp2x00_cpld_irq_chip = {
        .unmask = ixdp2x00_irq_unmask
 };
 
-void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_irqs)
+void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
 {
        unsigned int irq;
 
@@ -154,7 +154,7 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
 
        board_irq_stat = stat_reg;
        board_irq_mask = mask_reg;
-       board_irq_count = nr_irqs;
+       board_irq_count = nr_of_irqs;
 
        *board_irq_mask = 0xffffffff;
 
index d354e0fe4477ad450668b16e462258e26b2b4853..c40fc378a251244bce6e6c0ad9f0e177c7326a75 100644 (file)
@@ -119,7 +119,7 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 
 void __init omap_init_irq(void)
 {
-       unsigned long nr_irqs = 0;
+       unsigned long nr_of_irqs = 0;
        unsigned int nr_banks = 0;
        int i;
 
@@ -133,14 +133,14 @@ void __init omap_init_irq(void)
 
                omap_irq_bank_init_one(bank);
 
-               nr_irqs += bank->nr_irqs;
+               nr_of_irqs += bank->nr_irqs;
                nr_banks++;
        }
 
        printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-              nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+              nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 
-       for (i = 0; i < nr_irqs; i++) {
+       for (i = 0; i < nr_of_irqs; i++) {
                set_irq_chip(i, &omap_irq_chip);
                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID);
index 0d35ca04731e485fa655c5dccd087c59fd58fb0d..bf6785adccf45a02e725422994d17d77138d2bf9 100644 (file)
@@ -30,7 +30,7 @@ extern void zylonite_pxa300_init(void);
 static inline void zylonite_pxa300_init(void)
 {
        if (cpu_is_pxa300() || cpu_is_pxa310())
-               panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
+               panic("%s: PXA300/PXA310 not supported\n", __func__);
 }
 #endif
 
@@ -40,7 +40,7 @@ extern void zylonite_pxa320_init(void);
 static inline void zylonite_pxa320_init(void)
 {
        if (cpu_is_pxa320())
-               panic("%s: PXA320 not supported\n", __FUNCTION__);
+               panic("%s: PXA320 not supported\n", __func__);
 }
 #endif
 
diff --git a/arch/arm/mach-sa1100/include/mach/ide.h b/arch/arm/mach-sa1100/include/mach/ide.h
deleted file mode 100644 (file)
index 4c99c8f..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/ide.h
- *
- * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre
- *
- * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *              Get rid of the special ide_init_hwif_ports() functions
- *              and make a generalised function that can be used by all
- *              architectures.
- */
-
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-
-#error "This code is broken and needs update to match with current ide support"
-
-
-/*
- * Set up a hw structure for a specified data port, control port and IRQ.
- * This should follow whatever the default interface uses.
- */
-static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
-                                      unsigned long ctrl_port, int *irq)
-{
-       unsigned long reg = data_port;
-       int i;
-       int regincr = 1;
-
-       /* The Empeg board has the first two address lines unused */
-       if (machine_is_empeg())
-               regincr = 1 << 2;
-
-       /* The LART doesn't use A0 for IDE */
-       if (machine_is_lart())
-               regincr = 1 << 1;
-
-       memset(hw, 0, sizeof(*hw));
-
-       for (i = 0; i <= 7; i++) {
-               hw->io_ports_array[i] = reg;
-               reg += regincr;
-       }
-
-       hw->io_ports.ctl_addr = ctrl_port;
-
-       if (irq)
-               *irq = 0;
-}
-
-/*
- * This registers the standard ports for this architecture with the IDE
- * driver.
- */
-static __inline__ void
-ide_init_default_hwifs(void)
-{
-    if (machine_is_lart()) {
-#ifdef CONFIG_SA1100_LART
-        hw_regs_t hw;
-
-        /* Enable GPIO as interrupt line */
-        GPDR &= ~LART_GPIO_IDE;
-       set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
-
-        /* set PCMCIA interface timing */
-        MECR = 0x00060006;
-
-        /* init the interface */
-       ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL);
-        hw.irq = LART_IRQ_IDE;
-        ide_register_hw(&hw);
-#endif
-    }
-}
index c36a6d59d6f0785e900a7e905189e577bd4693bc..310477ba1bbf170a47af4e68bfc4bfa26d836a8d 100644 (file)
@@ -191,7 +191,7 @@ static int __init eic_probe(struct platform_device *pdev)
        struct eic *eic;
        struct resource *regs;
        unsigned int i;
-       unsigned int nr_irqs;
+       unsigned int nr_of_irqs;
        unsigned int int_irq;
        int ret;
        u32 pattern;
@@ -224,7 +224,7 @@ static int __init eic_probe(struct platform_device *pdev)
        eic_writel(eic, IDR, ~0UL);
        eic_writel(eic, MODE, ~0UL);
        pattern = eic_readl(eic, MODE);
-       nr_irqs = fls(pattern);
+       nr_of_irqs = fls(pattern);
 
        /* Trigger on low level unless overridden by driver */
        eic_writel(eic, EDGE, 0UL);
@@ -232,7 +232,7 @@ static int __init eic_probe(struct platform_device *pdev)
 
        eic->chip = &eic_chip;
 
-       for (i = 0; i < nr_irqs; i++) {
+       for (i = 0; i < nr_of_irqs; i++) {
                set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
                                         handle_level_irq);
                set_irq_chip_data(eic->first_irq + i, eic);
@@ -256,7 +256,7 @@ static int __init eic_probe(struct platform_device *pdev)
                 eic->regs, int_irq);
        dev_info(&pdev->dev,
                 "Handling %u external IRQs, starting with IRQ %u\n",
-                nr_irqs, eic->first_irq);
+                nr_of_irqs, eic->first_irq);
 
        return 0;
 
index 0149097b736d70bd5e4d2f73801b5805ffe8a88a..ce342fb74246240d14c789a8cc4f40ad182552c9 100644 (file)
@@ -95,16 +95,8 @@ extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
 #define HAVE_PCI_LEGACY
 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
-                                     struct vm_area_struct *vma);
-extern ssize_t pci_read_legacy_io(struct kobject *kobj,
-                                 struct bin_attribute *bin_attr,
-                                 char *buf, loff_t off, size_t count);
-extern ssize_t pci_write_legacy_io(struct kobject *kobj,
-                                  struct bin_attribute *bin_attr,
-                                  char *buf, loff_t off, size_t count);
-extern int pci_mmap_legacy_mem(struct kobject *kobj,
-                              struct bin_attribute *attr,
-                              struct vm_area_struct *vma);
+                                     struct vm_area_struct *vma,
+                                     enum pci_mmap_state mmap_state);
 
 #define pci_get_legacy_mem platform_pci_get_legacy_mem
 #define pci_legacy_read platform_pci_legacy_read
index 7545037a86254f1f5da925f9b96f80fafcfc1a33..211fcfd115f91f1e6ec169e8abd9849c257b975f 100644 (file)
@@ -614,12 +614,17 @@ char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
  * vector to get the base address.
  */
 int
-pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
+pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
+                          enum pci_mmap_state mmap_state)
 {
        unsigned long size = vma->vm_end - vma->vm_start;
        pgprot_t prot;
        char *addr;
 
+       /* We only support mmap'ing of legacy memory space */
+       if (mmap_state != pci_mmap_mem)
+               return -ENOSYS;
+
        /*
         * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
         * for more details.
index fc2994811f150c991986b6294538ca5b9c6a64ab..39cb6da72dcbef3358d04e2b419a150f88c299ba 100644 (file)
@@ -40,6 +40,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
index 2bd1f6ef5db0c6bd45269701b36b4713c0a6def3..644a70b1b04e4fd9ecf16d2e73d6e22ea5227115 100644 (file)
@@ -9,6 +9,8 @@ config PARISC
        def_bool y
        select HAVE_IDE
        select HAVE_OPROFILE
+       select RTC_CLASS
+       select RTC_DRV_PARISC
        help
          The PA-RISC microprocessor is designed by Hewlett-Packard and used
          in many of their workstations & servers (HP9000 700 and 800 series,
similarity index 77%
rename from include/asm-parisc/ide.h
rename to arch/parisc/include/asm/ide.h
index c246ef75017db7fc048699577c0603121bb19f51..81700a2321cff3926bbf60320a2bed1cba248118 100644 (file)
 
 #ifdef __KERNEL__
 
-#define ide_request_irq(irq,hand,flg,dev,id)   request_irq((irq),(hand),(flg),(dev),(id))
-#define ide_free_irq(irq,dev_id)               free_irq((irq), (dev_id))
-#define ide_request_region(from,extent,name)   request_region((from), (extent), (name))
-#define ide_release_region(from,extent)                release_region((from), (extent))
 /* Generic I/O and MEMIO string operations.  */
 
 #define __ide_insw     insw
similarity index 99%
rename from include/asm-parisc/pdc.h
rename to arch/parisc/include/asm/pdc.h
index 9eaa794c3e4a3f1de70716e450896e1cddf8d570..c584b00c6074af9419ac31badf1e432f38262815 100644 (file)
 #define BOOT_CONSOLE_SPA_OFFSET  0x3c4
 #define BOOT_CONSOLE_PATH_OFFSET 0x3a8
 
+/* size of the pdc_result buffer for firmware.c */
+#define NUM_PDC_RESULT 32
+
 #if !defined(__ASSEMBLY__)
 #ifdef __KERNEL__
 
@@ -600,6 +603,7 @@ int pdc_chassis_info(struct pdc_chassis_info *chassis_info, void *led_info, unsi
 int pdc_chassis_disp(unsigned long disp);
 int pdc_chassis_warn(unsigned long *warn);
 int pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info);
+int pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info);
 int pdc_iodc_read(unsigned long *actcnt, unsigned long hpa, unsigned int index,
                  void *iodc_data, unsigned int iodc_data_size);
 int pdc_system_map_find_mods(struct pdc_system_map_mod_info *pdc_mod_info,
@@ -638,6 +642,7 @@ int pdc_mem_mem_table(struct pdc_memory_table_raddr *r_addr,
 #endif
 
 void set_firmware_width(void);
+void set_firmware_width_unlocked(void);
 int pdc_do_firm_test_reset(unsigned long ftc_bitmap);
 int pdc_do_reset(void);
 int pdc_soft_power_info(unsigned long *power_reg);
similarity index 85%
rename from include/asm-parisc/ptrace.h
rename to arch/parisc/include/asm/ptrace.h
index 3e94c5d85ff5715a3d95af8e6444b27ae081a1fd..afa5333187b4519126d2556b008e9fdfaba0fde5 100644 (file)
@@ -47,6 +47,16 @@ struct pt_regs {
 
 #define task_regs(task) ((struct pt_regs *) ((char *)(task) + TASK_REGS))
 
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
+struct task_struct;
+#define arch_has_single_step() 1
+void user_disable_single_step(struct task_struct *task);
+void user_enable_single_step(struct task_struct *task);
+
+#define arch_has_block_step()  1
+void user_enable_block_step(struct task_struct *task);
+
 /* XXX should we use iaoq[1] or iaoq[0] ? */
 #define user_mode(regs)                        (((regs)->iaoq[0] & 3) ? 1 : 0)
 #define user_space(regs)               (((regs)->iasq[1] != 0) ? 1 : 0)
similarity index 99%
rename from include/asm-parisc/ropes.h
rename to arch/parisc/include/asm/ropes.h
index 007a880615eb80d766863f8e0b3708750c2ebbef..09f51d5ab57c254d78693b633d9077fd26454856 100644 (file)
@@ -1,7 +1,7 @@
 #ifndef _ASM_PARISC_ROPES_H_
 #define _ASM_PARISC_ROPES_H_
 
-#include <asm-parisc/parisc-device.h>
+#include <asm/parisc-device.h>
 
 #ifdef CONFIG_64BIT
 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
similarity index 99%
rename from include/asm-parisc/unistd.h
rename to arch/parisc/include/asm/unistd.h
index a7d857f0e4f404963c86f2baeb240f80d7a6f110..ef26b009dc5da1f323a7fc77d329e6c520b5e40f 100644 (file)
 #define __NR_timerfd_create    (__NR_Linux + 306)
 #define __NR_timerfd_settime   (__NR_Linux + 307)
 #define __NR_timerfd_gettime   (__NR_Linux + 308)
-
-#define __NR_Linux_syscalls    (__NR_timerfd_gettime + 1)
+#define __NR_signalfd4         (__NR_Linux + 309)
+#define __NR_eventfd2          (__NR_Linux + 310)
+#define __NR_epoll_create1     (__NR_Linux + 311)
+#define __NR_dup3              (__NR_Linux + 312)
+#define __NR_pipe2             (__NR_Linux + 313)
+#define __NR_inotify_init1     (__NR_Linux + 314)
+
+#define __NR_Linux_syscalls    (__NR_inotify_init1 + 1)
 
 
 #define __IGNORE_select                /* newselect */
similarity index 99%
rename from include/asm-parisc/unwind.h
rename to arch/parisc/include/asm/unwind.h
index 2f7e6e50a1580de34d23216018cc015d1bf7780f..52482e4fc20d1f11407243915968523160839fbb 100644 (file)
@@ -74,4 +74,6 @@ void unwind_frame_init_running(struct unwind_frame_info *info, struct pt_regs *r
 int unwind_once(struct unwind_frame_info *info);
 int unwind_to_user(struct unwind_frame_info *info);
 
+int unwind_init(void);
+
 #endif
diff --git a/arch/parisc/kernel/.gitignore b/arch/parisc/kernel/.gitignore
new file mode 100644 (file)
index 0000000..c5f676c
--- /dev/null
@@ -0,0 +1 @@
+vmlinux.lds
index 3efc0b73e4ff9ce71efd7bf93550af12f1710394..699cf8ef211816576c5ee10d29c7bc67257580fc 100644 (file)
@@ -290,5 +290,8 @@ int main(void)
        DEFINE(EXCDATA_IP, offsetof(struct exception_data, fault_ip));
        DEFINE(EXCDATA_SPACE, offsetof(struct exception_data, fault_space));
        DEFINE(EXCDATA_ADDR, offsetof(struct exception_data, fault_addr));
+       BLANK();
+       DEFINE(ASM_PDC_RESULT_SIZE, NUM_PDC_RESULT * sizeof(unsigned long));
+       BLANK();
        return 0;
 }
index 7177a6cd1b7f58b0fcc83f60ea5c11cf1bd96e1a..03f26bd75bd8ebcb301beb7a7e90c07454d08412 100644 (file)
@@ -71,8 +71,8 @@
 #include <asm/processor.h>     /* for boot_cpu_data */
 
 static DEFINE_SPINLOCK(pdc_lock);
-static unsigned long pdc_result[32] __attribute__ ((aligned (8)));
-static unsigned long pdc_result2[32] __attribute__ ((aligned (8)));
+extern unsigned long pdc_result[NUM_PDC_RESULT];
+extern unsigned long pdc_result2[NUM_PDC_RESULT];
 
 #ifdef CONFIG_64BIT
 #define WIDE_FIRMWARE 0x1
@@ -150,26 +150,40 @@ static void convert_to_wide(unsigned long *addr)
 #endif
 }
 
+#ifdef CONFIG_64BIT
+void __init set_firmware_width_unlocked(void)
+{
+       int ret;
+
+       ret = mem_pdc_call(PDC_MODEL, PDC_MODEL_CAPABILITIES,
+               __pa(pdc_result), 0);
+       convert_to_wide(pdc_result);
+       if (pdc_result[0] != NARROW_FIRMWARE)
+               parisc_narrow_firmware = 0;
+}
+       
 /**
  * set_firmware_width - Determine if the firmware is wide or narrow.
  * 
- * This function must be called before any pdc_* function that uses the convert_to_wide
- * function.
+ * This function must be called before any pdc_* function that uses the
+ * convert_to_wide function.
  */
 void __init set_firmware_width(void)
 {
-#ifdef CONFIG_64BIT
-       int retval;
        unsigned long flags;
+       spin_lock_irqsave(&pdc_lock, flags);
+       set_firmware_width_unlocked();
+       spin_unlock_irqrestore(&pdc_lock, flags);
+}
+#else
+void __init set_firmware_width_unlocked(void) {
+       return;
+}
 
-        spin_lock_irqsave(&pdc_lock, flags);
-       retval = mem_pdc_call(PDC_MODEL, PDC_MODEL_CAPABILITIES, __pa(pdc_result), 0);
-       convert_to_wide(pdc_result);
-       if(pdc_result[0] != NARROW_FIRMWARE)
-               parisc_narrow_firmware = 0;
-        spin_unlock_irqrestore(&pdc_lock, flags);
-#endif
+void __init set_firmware_width(void) {
+       return;
 }
+#endif /*CONFIG_64BIT*/
 
 /**
  * pdc_emergency_unlock - Unlock the linux pdc lock
@@ -288,6 +302,20 @@ int pdc_chassis_warn(unsigned long *warn)
        return retval;
 }
 
+int __init pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info)
+{
+       int ret;
+
+       ret = mem_pdc_call(PDC_COPROC, PDC_COPROC_CFG, __pa(pdc_result));
+       convert_to_wide(pdc_result);
+       pdc_coproc_info->ccr_functional = pdc_result[0];
+       pdc_coproc_info->ccr_present = pdc_result[1];
+       pdc_coproc_info->revision = pdc_result[17];
+       pdc_coproc_info->model = pdc_result[18];
+
+       return ret;
+}
+
 /**
  * pdc_coproc_cfg - To identify coprocessors attached to the processor.
  * @pdc_coproc_info: Return buffer address.
@@ -297,19 +325,14 @@ int pdc_chassis_warn(unsigned long *warn)
  */
 int __init pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info)
 {
-        int retval;
+       int ret;
        unsigned long flags;
 
-        spin_lock_irqsave(&pdc_lock, flags);
-        retval = mem_pdc_call(PDC_COPROC, PDC_COPROC_CFG, __pa(pdc_result));
-        convert_to_wide(pdc_result);
-        pdc_coproc_info->ccr_functional = pdc_result[0];
-        pdc_coproc_info->ccr_present = pdc_result[1];
-        pdc_coproc_info->revision = pdc_result[17];
-        pdc_coproc_info->model = pdc_result[18];
-        spin_unlock_irqrestore(&pdc_lock, flags);
+       spin_lock_irqsave(&pdc_lock, flags);
+       ret = pdc_coproc_cfg_unlocked(pdc_coproc_info);
+       spin_unlock_irqrestore(&pdc_lock, flags);
 
-        return retval;
+       return ret;
 }
 
 /**
index a84e31e828768943a7ac288ccb26aa49499b275c..0e3d9f9b9e33e97680190e3752cea063fce9c251 100644 (file)
@@ -121,7 +121,7 @@ $pgt_fill_loop:
        copy            %r0,%r2
 
        /* And the RFI Target address too */
-       load32          start_kernel,%r11
+       load32          start_parisc,%r11
 
        /* And the initial task pointer */
        load32          init_thread_union,%r6
index 49c637970789ba81da5741a75817ef1274e3b1ac..90904f9dfc504fb1e0337abb196b1617006ce514 100644 (file)
@@ -4,6 +4,7 @@
  * Copyright (C) 2000 Hewlett-Packard Co, Linuxcare Inc.
  * Copyright (C) 2000 Matthew Wilcox <matthew@wil.cx>
  * Copyright (C) 2000 David Huggins-Daines <dhd@debian.org>
+ * Copyright (C) 2008 Helge Deller <deller@gmx.de>
  */
 
 #include <linux/kernel.h>
 /* PSW bits we allow the debugger to modify */
 #define USER_PSW_BITS  (PSW_N | PSW_V | PSW_CB)
 
-#undef DEBUG_PTRACE
+/*
+ * Called by kernel/ptrace.c when detaching..
+ *
+ * Make sure single step bits etc are not set.
+ */
+void ptrace_disable(struct task_struct *task)
+{
+       task->ptrace &= ~(PT_SINGLESTEP|PT_BLOCKSTEP);
 
-#ifdef DEBUG_PTRACE
-#define DBG(x...)      printk(x)
-#else
-#define DBG(x...)
-#endif
+       /* make sure the trap bits are not set */
+       pa_psw(task)->r = 0;
+       pa_psw(task)->t = 0;
+       pa_psw(task)->h = 0;
+       pa_psw(task)->l = 0;
+}
+
+/*
+ * The following functions are called by ptrace_resume() when
+ * enabling or disabling single/block tracing.
+ */
+void user_disable_single_step(struct task_struct *task)
+{
+       ptrace_disable(task);
+}
+
+void user_enable_single_step(struct task_struct *task)
+{
+       task->ptrace &= ~PT_BLOCKSTEP;
+       task->ptrace |= PT_SINGLESTEP;
+
+       if (pa_psw(task)->n) {
+               struct siginfo si;
+
+               /* Nullified, just crank over the queue. */
+               task_regs(task)->iaoq[0] = task_regs(task)->iaoq[1];
+               task_regs(task)->iasq[0] = task_regs(task)->iasq[1];
+               task_regs(task)->iaoq[1] = task_regs(task)->iaoq[0] + 4;
+               pa_psw(task)->n = 0;
+               pa_psw(task)->x = 0;
+               pa_psw(task)->y = 0;
+               pa_psw(task)->z = 0;
+               pa_psw(task)->b = 0;
+               ptrace_disable(task);
+               /* Don't wake up the task, but let the
+                  parent know something happened. */
+               si.si_code = TRAP_TRACE;
+               si.si_addr = (void __user *) (task_regs(task)->iaoq[0] & ~3);
+               si.si_signo = SIGTRAP;
+               si.si_errno = 0;
+               force_sig_info(SIGTRAP, &si, task);
+               /* notify_parent(task, SIGCHLD); */
+               return;
+       }
+
+       /* Enable recovery counter traps.  The recovery counter
+        * itself will be set to zero on a task switch.  If the
+        * task is suspended on a syscall then the syscall return
+        * path will overwrite the recovery counter with a suitable
+        * value such that it traps once back in user space.  We
+        * disable interrupts in the tasks PSW here also, to avoid
+        * interrupts while the recovery counter is decrementing.
+        */
+       pa_psw(task)->r = 1;
+       pa_psw(task)->t = 0;
+       pa_psw(task)->h = 0;
+       pa_psw(task)->l = 0;
+}
+
+void user_enable_block_step(struct task_struct *task)
+{
+       task->ptrace &= ~PT_SINGLESTEP;
+       task->ptrace |= PT_BLOCKSTEP;
+
+       /* Enable taken branch trap. */
+       pa_psw(task)->r = 0;
+       pa_psw(task)->t = 1;
+       pa_psw(task)->h = 0;
+       pa_psw(task)->l = 0;
+}
+
+long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+{
+       unsigned long tmp;
+       long ret = -EIO;
 
-#ifdef CONFIG_64BIT
+       switch (request) {
+
+       /* Read the word at location addr in the USER area.  For ptraced
+          processes, the kernel saves all regs on a syscall. */
+       case PTRACE_PEEKUSR:
+               if ((addr & (sizeof(long)-1)) ||
+                   (unsigned long) addr >= sizeof(struct pt_regs))
+                       break;
+               tmp = *(unsigned long *) ((char *) task_regs(child) + addr);
+               ret = put_user(tmp, (unsigned long *) data);
+               break;
+
+       /* Write the word at location addr in the USER area.  This will need
+          to change when the kernel no longer saves all regs on a syscall.
+          FIXME.  There is a problem at the moment in that r3-r18 are only
+          saved if the process is ptraced on syscall entry, and even then
+          those values are overwritten by actual register values on syscall
+          exit. */
+       case PTRACE_POKEUSR:
+               /* Some register values written here may be ignored in
+                * entry.S:syscall_restore_rfi; e.g. iaoq is written with
+                * r31/r31+4, and not with the values in pt_regs.
+                */
+               if (addr == PT_PSW) {
+                       /* Allow writing to Nullify, Divide-step-correction,
+                        * and carry/borrow bits.
+                        * BEWARE, if you set N, and then single step, it won't
+                        * stop on the nullified instruction.
+                        */
+                       data &= USER_PSW_BITS;
+                       task_regs(child)->gr[0] &= ~USER_PSW_BITS;
+                       task_regs(child)->gr[0] |= data;
+                       ret = 0;
+                       break;
+               }
+
+               if ((addr & (sizeof(long)-1)) ||
+                   (unsigned long) addr >= sizeof(struct pt_regs))
+                       break;
+               if ((addr >= PT_GR1 && addr <= PT_GR31) ||
+                               addr == PT_IAOQ0 || addr == PT_IAOQ1 ||
+                               (addr >= PT_FR0 && addr <= PT_FR31 + 4) ||
+                               addr == PT_SAR) {
+                       *(unsigned long *) ((char *) task_regs(child) + addr) = data;
+                       ret = 0;
+               }
+               break;
+
+       default:
+               ret = ptrace_request(child, request, addr, data);
+               break;
+       }
+
+       return ret;
+}
+
+
+#ifdef CONFIG_COMPAT
 
 /* This function is needed to translate 32 bit pt_regs offsets in to
  * 64 bit pt_regs offsets.  For example, a 32 bit gdb under a 64 bit kernel
@@ -61,106 +196,25 @@ static long translate_usr_offset(long offset)
        else
                return -1;
 }
-#endif
 
-/*
- * Called by kernel/ptrace.c when detaching..
- *
- * Make sure single step bits etc are not set.
- */
-void ptrace_disable(struct task_struct *child)
+long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
+                       compat_ulong_t addr, compat_ulong_t data)
 {
-       /* make sure the trap bits are not set */
-       pa_psw(child)->r = 0;
-       pa_psw(child)->t = 0;
-       pa_psw(child)->h = 0;
-       pa_psw(child)->l = 0;
-}
-
-long arch_ptrace(struct task_struct *child, long request, long addr, long data)
-{
-       long ret;
-#ifdef DEBUG_PTRACE
-       long oaddr=addr, odata=data;
-#endif
+       compat_uint_t tmp;
+       long ret = -EIO;
 
        switch (request) {
-       case PTRACE_PEEKTEXT: /* read word at location addr. */ 
-       case PTRACE_PEEKDATA: {
-#ifdef CONFIG_64BIT
-               if (__is_compat_task(child)) {
-                       int copied;
-                       unsigned int tmp;
-
-                       addr &= 0xffffffffL;
-                       copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
-                       ret = -EIO;
-                       if (copied != sizeof(tmp))
-                               goto out_tsk;
-                       ret = put_user(tmp,(unsigned int *) data);
-                       DBG("sys_ptrace(PEEK%s, %d, %lx, %lx) returning %ld, data %x\n",
-                               request == PTRACE_PEEKTEXT ? "TEXT" : "DATA",
-                               pid, oaddr, odata, ret, tmp);
-               }
-               else
-#endif
-                       ret = generic_ptrace_peekdata(child, addr, data);
-               goto out_tsk;
-       }
 
-       /* when I and D space are separate, this will have to be fixed. */
-       case PTRACE_POKETEXT: /* write the word at location addr. */
-       case PTRACE_POKEDATA:
-               ret = 0;
-#ifdef CONFIG_64BIT
-               if (__is_compat_task(child)) {
-                       unsigned int tmp = (unsigned int)data;
-                       DBG("sys_ptrace(POKE%s, %d, %lx, %lx)\n",
-                               request == PTRACE_POKETEXT ? "TEXT" : "DATA",
-                               pid, oaddr, odata);
-                       addr &= 0xffffffffL;
-                       if (access_process_vm(child, addr, &tmp, sizeof(tmp), 1) == sizeof(tmp))
-                               goto out_tsk;
-               }
-               else
-#endif
-               {
-                       if (access_process_vm(child, addr, &data, sizeof(data), 1) == sizeof(data))
-                               goto out_tsk;
-               }
-               ret = -EIO;
-               goto out_tsk;
-
-       /* Read the word at location addr in the USER area.  For ptraced
-          processes, the kernel saves all regs on a syscall. */
-       case PTRACE_PEEKUSR: {
-               ret = -EIO;
-#ifdef CONFIG_64BIT
-               if (__is_compat_task(child)) {
-                       unsigned int tmp;
-
-                       if (addr & (sizeof(int)-1))
-                               goto out_tsk;
-                       if ((addr = translate_usr_offset(addr)) < 0)
-                               goto out_tsk;
-
-                       tmp = *(unsigned int *) ((char *) task_regs(child) + addr);
-                       ret = put_user(tmp, (unsigned int *) data);
-                       DBG("sys_ptrace(PEEKUSR, %d, %lx, %lx) returning %ld, addr %lx, data %x\n",
-                               pid, oaddr, odata, ret, addr, tmp);
-               }
-               else
-#endif
-               {
-                       unsigned long tmp;
+       case PTRACE_PEEKUSR:
+               if (addr & (sizeof(compat_uint_t)-1))
+                       break;
+               addr = translate_usr_offset(addr);
+               if (addr < 0)
+                       break;
 
-                       if ((addr & (sizeof(long)-1)) || (unsigned long) addr >= sizeof(struct pt_regs))
-                               goto out_tsk;
-                       tmp = *(unsigned long *) ((char *) task_regs(child) + addr);
-                       ret = put_user(tmp, (unsigned long *) data);
-               }
-               goto out_tsk;
-       }
+               tmp = *(compat_uint_t *) ((char *) task_regs(child) + addr);
+               ret = put_user(tmp, (compat_uint_t *) (unsigned long) data);
+               break;
 
        /* Write the word at location addr in the USER area.  This will need
           to change when the kernel no longer saves all regs on a syscall.
@@ -169,185 +223,46 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
           those values are overwritten by actual register values on syscall
           exit. */
        case PTRACE_POKEUSR:
-               ret = -EIO;
                /* Some register values written here may be ignored in
                 * entry.S:syscall_restore_rfi; e.g. iaoq is written with
                 * r31/r31+4, and not with the values in pt_regs.
                 */
-                /* PT_PSW=0, so this is valid for 32 bit processes under 64
-                * bit kernels.
-                */
                if (addr == PT_PSW) {
-                       /* PT_PSW=0, so this is valid for 32 bit processes
-                        * under 64 bit kernels.
-                        *
-                        * Allow writing to Nullify, Divide-step-correction,
-                        * and carry/borrow bits.
-                        * BEWARE, if you set N, and then single step, it won't
-                        * stop on the nullified instruction.
+                       /* Since PT_PSW==0, it is valid for 32 bit processes
+                        * under 64 bit kernels as well.
                         */
-                       DBG("sys_ptrace(POKEUSR, %d, %lx, %lx)\n",
-                               pid, oaddr, odata);
-                       data &= USER_PSW_BITS;
-                       task_regs(child)->gr[0] &= ~USER_PSW_BITS;
-                       task_regs(child)->gr[0] |= data;
-                       ret = 0;
-                       goto out_tsk;
-               }
-#ifdef CONFIG_64BIT
-               if (__is_compat_task(child)) {
-                       if (addr & (sizeof(int)-1))
-                               goto out_tsk;
-                       if ((addr = translate_usr_offset(addr)) < 0)
-                               goto out_tsk;
-                       DBG("sys_ptrace(POKEUSR, %d, %lx, %lx) addr %lx\n",
-                               pid, oaddr, odata, addr);
+                       ret = arch_ptrace(child, request, addr, data);
+               } else {
+                       if (addr & (sizeof(compat_uint_t)-1))
+                               break;
+                       addr = translate_usr_offset(addr);
+                       if (addr < 0)
+                               break;
                        if (addr >= PT_FR0 && addr <= PT_FR31 + 4) {
                                /* Special case, fp regs are 64 bits anyway */
-                               *(unsigned int *) ((char *) task_regs(child) + addr) = data;
+                               *(__u64 *) ((char *) task_regs(child) + addr) = data;
                                ret = 0;
                        }
                        else if ((addr >= PT_GR1+4 && addr <= PT_GR31+4) ||
                                        addr == PT_IAOQ0+4 || addr == PT_IAOQ1+4 ||
                                        addr == PT_SAR+4) {
                                /* Zero the top 32 bits */
-                               *(unsigned int *) ((char *) task_regs(child) + addr - 4) = 0;
-                               *(unsigned int *) ((char *) task_regs(child) + addr) = data;
+                               *(__u32 *) ((char *) task_regs(child) + addr - 4) = 0;
+                               *(__u32 *) ((char *) task_regs(child) + addr) = data;
                                ret = 0;
                        }
-                       goto out_tsk;
                }
-               else
-#endif
-               {
-                       if ((addr & (sizeof(long)-1)) || (unsigned long) addr >= sizeof(struct pt_regs))
-                               goto out_tsk;
-                       if ((addr >= PT_GR1 && addr <= PT_GR31) ||
-                                       addr == PT_IAOQ0 || addr == PT_IAOQ1 ||
-                                       (addr >= PT_FR0 && addr <= PT_FR31 + 4) ||
-                                       addr == PT_SAR) {
-                               *(unsigned long *) ((char *) task_regs(child) + addr) = data;
-                               ret = 0;
-                       }
-                       goto out_tsk;
-               }
-
-       case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
-       case PTRACE_CONT:
-               ret = -EIO;
-               DBG("sys_ptrace(%s)\n",
-                       request == PTRACE_SYSCALL ? "SYSCALL" : "CONT");
-               if (!valid_signal(data))
-                       goto out_tsk;
-               child->ptrace &= ~(PT_SINGLESTEP|PT_BLOCKSTEP);
-               if (request == PTRACE_SYSCALL) {
-                       set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-               } else {
-                       clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-               }               
-               child->exit_code = data;
-               goto out_wake_notrap;
-
-       case PTRACE_KILL:
-               /*
-                * make the child exit.  Best I can do is send it a
-                * sigkill.  perhaps it should be put in the status
-                * that it wants to exit.
-                */
-               ret = 0;
-               DBG("sys_ptrace(KILL)\n");
-               if (child->exit_state == EXIT_ZOMBIE)   /* already dead */
-                       goto out_tsk;
-               child->exit_code = SIGKILL;
-               goto out_wake_notrap;
-
-       case PTRACE_SINGLEBLOCK:
-               DBG("sys_ptrace(SINGLEBLOCK)\n");
-               ret = -EIO;
-               if (!valid_signal(data))
-                       goto out_tsk;
-               clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-               child->ptrace &= ~PT_SINGLESTEP;
-               child->ptrace |= PT_BLOCKSTEP;
-               child->exit_code = data;
-
-               /* Enable taken branch trap. */
-               pa_psw(child)->r = 0;
-               pa_psw(child)->t = 1;
-               pa_psw(child)->h = 0;
-               pa_psw(child)->l = 0;
-               goto out_wake;
-
-       case PTRACE_SINGLESTEP:
-               DBG("sys_ptrace(SINGLESTEP)\n");
-               ret = -EIO;
-               if (!valid_signal(data))
-                       goto out_tsk;
-
-               clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-               child->ptrace &= ~PT_BLOCKSTEP;
-               child->ptrace |= PT_SINGLESTEP;
-               child->exit_code = data;
-
-               if (pa_psw(child)->n) {
-                       struct siginfo si;
-
-                       /* Nullified, just crank over the queue. */
-                       task_regs(child)->iaoq[0] = task_regs(child)->iaoq[1];
-                       task_regs(child)->iasq[0] = task_regs(child)->iasq[1];
-                       task_regs(child)->iaoq[1] = task_regs(child)->iaoq[0] + 4;
-                       pa_psw(child)->n = 0;
-                       pa_psw(child)->x = 0;
-                       pa_psw(child)->y = 0;
-                       pa_psw(child)->z = 0;
-                       pa_psw(child)->b = 0;
-                       ptrace_disable(child);
-                       /* Don't wake up the child, but let the
-                          parent know something happened. */
-                       si.si_code = TRAP_TRACE;
-                       si.si_addr = (void __user *) (task_regs(child)->iaoq[0] & ~3);
-                       si.si_signo = SIGTRAP;
-                       si.si_errno = 0;
-                       force_sig_info(SIGTRAP, &si, child);
-                       //notify_parent(child, SIGCHLD);
-                       //ret = 0;
-                       goto out_wake;
-               }
-
-               /* Enable recovery counter traps.  The recovery counter
-                * itself will be set to zero on a task switch.  If the
-                * task is suspended on a syscall then the syscall return
-                * path will overwrite the recovery counter with a suitable
-                * value such that it traps once back in user space.  We
-                * disable interrupts in the childs PSW here also, to avoid
-                * interrupts while the recovery counter is decrementing.
-                */
-               pa_psw(child)->r = 1;
-               pa_psw(child)->t = 0;
-               pa_psw(child)->h = 0;
-               pa_psw(child)->l = 0;
-               /* give it a chance to run. */
-               goto out_wake;
-
-       case PTRACE_GETEVENTMSG:
-                ret = put_user(child->ptrace_message, (unsigned int __user *) data);
-               goto out_tsk;
+               break;
 
        default:
-               ret = ptrace_request(child, request, addr, data);
-               goto out_tsk;
+               ret = compat_ptrace_request(child, request, addr, data);
+               break;
        }
 
-out_wake_notrap:
-       ptrace_disable(child);
-out_wake:
-       wake_up_process(child);
-       ret = 0;
-out_tsk:
-       DBG("arch_ptrace(%ld, %d, %lx, %lx) returning %ld\n",
-               request, pid, oaddr, odata, ret);
        return ret;
 }
+#endif
+
 
 void syscall_trace(void)
 {
index 7a92695d95a6bf814a72803da7d02403953eacd4..5f3d3a1f9037c7438b980c3e5f8d23589c4a5461 100644 (file)
@@ -8,12 +8,24 @@
  *
  */
 
+#include <asm/pdc.h>
 #include <asm/psw.h>
 #include <asm/assembly.h>
+#include <asm/asm-offsets.h>
 
 #include <linux/linkage.h>
 
+
        .section        .bss
+
+       .export pdc_result
+       .export pdc_result2
+       .align 8
+pdc_result:
+       .block  ASM_PDC_RESULT_SIZE
+pdc_result2:
+       .block  ASM_PDC_RESULT_SIZE
+
        .export real_stack
        .export real32_stack
        .export real64_stack
index 39e7c5a5946a8981deee1afa1296efc7cff9eadc..7d27853ff8c8b6233ec4a0e1f2fe3747fbbf88aa 100644 (file)
@@ -44,6 +44,7 @@
 #include <asm/pdc_chassis.h>
 #include <asm/io.h>
 #include <asm/setup.h>
+#include <asm/unwind.h>
 
 static char __initdata command_line[COMMAND_LINE_SIZE];
 
@@ -123,6 +124,7 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_64BIT
        extern int parisc_narrow_firmware;
 #endif
+       unwind_init();
 
        init_per_cpu(smp_processor_id());       /* Set Modes & Enable FP */
 
@@ -368,6 +370,31 @@ static int __init parisc_init(void)
 
        return 0;
 }
-
 arch_initcall(parisc_init);
 
+void start_parisc(void)
+{
+       extern void start_kernel(void);
+
+       int ret, cpunum;
+       struct pdc_coproc_cfg coproc_cfg;
+
+       cpunum = smp_processor_id();
+
+       set_firmware_width_unlocked();
+
+       ret = pdc_coproc_cfg_unlocked(&coproc_cfg);
+       if (ret >= 0 && coproc_cfg.ccr_functional) {
+               mtctl(coproc_cfg.ccr_functional, 10);
+
+               cpu_data[cpunum].fp_rev = coproc_cfg.revision;
+               cpu_data[cpunum].fp_model = coproc_cfg.model;
+
+               asm volatile ("fstd     %fr0,8(%sp)");
+       } else {
+               panic("must have an fpu to boot linux");
+       }
+
+       start_kernel();
+       // not reached
+}
index c7e59f548817fb36554954d663bfedcdf5e3b2f6..303d2b647e418daab682f586565ade19e5420325 100644 (file)
@@ -87,7 +87,7 @@
        ENTRY_SAME(setuid)
        ENTRY_SAME(getuid)
        ENTRY_COMP(stime)               /* 25 */
-       ENTRY_SAME(ptrace)
+       ENTRY_COMP(ptrace)
        ENTRY_SAME(alarm)
        /* see stat comment */
        ENTRY_COMP(newfstat)
        ENTRY_SAME(timerfd_create)
        ENTRY_COMP(timerfd_settime)
        ENTRY_COMP(timerfd_gettime)
+       ENTRY_COMP(signalfd4)
+       ENTRY_SAME(eventfd2)            /* 310 */
+       ENTRY_SAME(epoll_create1)
+       ENTRY_SAME(dup3)
+       ENTRY_SAME(pipe2)
+       ENTRY_SAME(inotify_init1)
 
        /* Nothing yet */
 
index 24be86bba94d6bdf93618109bb490bf6fbe68205..4d09203bc69307275afcb92f5f3a53d2bdff5057 100644 (file)
@@ -23,6 +23,7 @@
 #include <linux/smp.h>
 #include <linux/profile.h>
 #include <linux/clocksource.h>
+#include <linux/platform_device.h>
 
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -215,6 +216,24 @@ void __init start_cpu_itimer(void)
        cpu_data[cpu].it_value = next_tick;
 }
 
+struct platform_device rtc_parisc_dev = {
+       .name = "rtc-parisc",
+       .id = -1,
+};
+
+static int __init rtc_init(void)
+{
+       int ret;
+
+       ret = platform_device_register(&rtc_parisc_dev);
+       if (ret < 0)
+               printk(KERN_ERR "unable to register rtc device...\n");
+
+       /* not necessarily an error */
+       return 0;
+}
+module_init(rtc_init);
+
 void __init time_init(void)
 {
        static struct pdc_tod tod_data;
@@ -245,4 +264,3 @@ void __init time_init(void)
                xtime.tv_nsec = 0;
        }
 }
-
index 701b2d2d88823f55fb2d18a2c03c1e91b2b3f2a9..6773c582e457a15b3e9ddb5006e462754bddd06e 100644 (file)
@@ -170,7 +170,7 @@ void unwind_table_remove(struct unwind_table *table)
 }
 
 /* Called from setup_arch to import the kernel unwind info */
-static int unwind_init(void)
+int unwind_init(void)
 {
        long start, stop;
        register unsigned long gp __asm__ ("r27");
@@ -417,5 +417,3 @@ int unwind_to_user(struct unwind_frame_info *info)
 
        return ret;
 }
-
-module_init(unwind_init);
index 64e144505f653e0ae1d4f190690ef458e9aad5e7..5ac51e6efc1d860ea0d72702d60e63fa42a20c81 100644 (file)
  * 2 of the License, or (at your option) any later version.
  */
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#else
+#include <asm/types.h>
+#endif
 #include <asm/asm-compat.h>
 #include <asm/kdump.h>
-#include <asm/types.h>
 
 /*
  * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
index ae2ea803a0f2502daff6e2ffcd24359c1f602675..9047af7baa697afad42e89b19f2cfdd893ad7430 100644 (file)
@@ -74,6 +74,13 @@ struct pci_controller {
        unsigned long pci_io_size;
 #endif
 
+       /* Some machines have a special region to forward the ISA
+        * "memory" cycles such as VGA memory regions. Left to 0
+        * if unsupported
+        */
+       resource_size_t isa_mem_phys;
+       resource_size_t isa_mem_size;
+
        struct pci_ops *ops;
        unsigned int __iomem *cfg_addr;
        void __iomem *cfg_data;
index 0e52c7828ea498d48c34a37155dba0f57b39a349..39d547fde956a66f9dc3cb5d26914c3e01cb387b 100644 (file)
@@ -123,6 +123,16 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 #define HAVE_PCI_MMAP  1
 
+extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
+                          size_t count);
+extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
+                          size_t count);
+extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
+                                     struct vm_area_struct *vma,
+                                     enum pci_mmap_state mmap_state);
+
+#define HAVE_PCI_LEGACY        1
+
 #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
 /*
  * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
@@ -226,5 +236,6 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
 extern void pcibios_do_bus_setup(struct pci_bus *bus);
 extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
 
+
 #endif /* __KERNEL__ */
 #endif /* __ASM_POWERPC_PCI_H */
index 734e0754fb9bec39a0d8533d77c30ad1c02d1103..280a90cc9894c6ed3f6a2e2611b9d53623218a2f 100644 (file)
@@ -129,7 +129,7 @@ extern int ptrace_put_reg(struct task_struct *task, int regno,
 #define CHECK_FULL_REGS(regs)                                                \
 do {                                                                         \
        if ((regs)->trap & 1)                                                 \
-               printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
+               printk(KERN_CRIT "%s: partial register set\n", __func__); \
 } while (0)
 #endif /* __powerpc64__ */
 
index 01ce8c38bae635334b6b3b9d104f0bb26d5861fe..3815d84a1ef4b8beb71dab7c8a26d90834320ee9 100644 (file)
@@ -451,7 +451,8 @@ pgprot_t pci_phys_mem_access_prot(struct file *file,
                pci_dev_put(pdev);
        }
 
-       DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
+       DBG("non-PCI map for %llx, prot: %lx\n",
+           (unsigned long long)offset, prot);
 
        return __pgprot(prot);
 }
@@ -490,6 +491,131 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
        return ret;
 }
 
+/* This provides legacy IO read access on a bus */
+int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
+{
+       unsigned long offset;
+       struct pci_controller *hose = pci_bus_to_host(bus);
+       struct resource *rp = &hose->io_resource;
+       void __iomem *addr;
+
+       /* Check if port can be supported by that bus. We only check
+        * the ranges of the PHB though, not the bus itself as the rules
+        * for forwarding legacy cycles down bridges are not our problem
+        * here. So if the host bridge supports it, we do it.
+        */
+       offset = (unsigned long)hose->io_base_virt - _IO_BASE;
+       offset += port;
+
+       if (!(rp->flags & IORESOURCE_IO))
+               return -ENXIO;
+       if (offset < rp->start || (offset + size) > rp->end)
+               return -ENXIO;
+       addr = hose->io_base_virt + port;
+
+       switch(size) {
+       case 1:
+               *((u8 *)val) = in_8(addr);
+               return 1;
+       case 2:
+               if (port & 1)
+                       return -EINVAL;
+               *((u16 *)val) = in_le16(addr);
+               return 2;
+       case 4:
+               if (port & 3)
+                       return -EINVAL;
+               *((u32 *)val) = in_le32(addr);
+               return 4;
+       }
+       return -EINVAL;
+}
+
+/* This provides legacy IO write access on a bus */
+int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
+{
+       unsigned long offset;
+       struct pci_controller *hose = pci_bus_to_host(bus);
+       struct resource *rp = &hose->io_resource;
+       void __iomem *addr;
+
+       /* Check if port can be supported by that bus. We only check
+        * the ranges of the PHB though, not the bus itself as the rules
+        * for forwarding legacy cycles down bridges are not our problem
+        * here. So if the host bridge supports it, we do it.
+        */
+       offset = (unsigned long)hose->io_base_virt - _IO_BASE;
+       offset += port;
+
+       if (!(rp->flags & IORESOURCE_IO))
+               return -ENXIO;
+       if (offset < rp->start || (offset + size) > rp->end)
+               return -ENXIO;
+       addr = hose->io_base_virt + port;
+
+       /* WARNING: The generic code is idiotic. It gets passed a pointer
+        * to what can be a 1, 2 or 4 byte quantity and always reads that
+        * as a u32, which means that we have to correct the location of
+        * the data read within those 32 bits for size 1 and 2
+        */
+       switch(size) {
+       case 1:
+               out_8(addr, val >> 24);
+               return 1;
+       case 2:
+               if (port & 1)
+                       return -EINVAL;
+               out_le16(addr, val >> 16);
+               return 2;
+       case 4:
+               if (port & 3)
+                       return -EINVAL;
+               out_le32(addr, val);
+               return 4;
+       }
+       return -EINVAL;
+}
+
+/* This provides legacy IO or memory mmap access on a bus */
+int pci_mmap_legacy_page_range(struct pci_bus *bus,
+                              struct vm_area_struct *vma,
+                              enum pci_mmap_state mmap_state)
+{
+       struct pci_controller *hose = pci_bus_to_host(bus);
+       resource_size_t offset =
+               ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
+       resource_size_t size = vma->vm_end - vma->vm_start;
+       struct resource *rp;
+
+       pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
+                pci_domain_nr(bus), bus->number,
+                mmap_state == pci_mmap_mem ? "MEM" : "IO",
+                (unsigned long long)offset,
+                (unsigned long long)(offset + size - 1));
+
+       if (mmap_state == pci_mmap_mem) {
+               if ((offset + size) > hose->isa_mem_size)
+                       return -ENXIO;
+               offset += hose->isa_mem_phys;
+       } else {
+               unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
+               unsigned long roffset = offset + io_offset;
+               rp = &hose->io_resource;
+               if (!(rp->flags & IORESOURCE_IO))
+                       return -ENXIO;
+               if (roffset < rp->start || (roffset + size) > rp->end)
+                       return -ENXIO;
+               offset += hose->io_base_phys;
+       }
+       pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
+
+       vma->vm_pgoff = offset >> PAGE_SHIFT;
+       vma->vm_page_prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
+       return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+                              vma->vm_end - vma->vm_start,
+                              vma->vm_page_prot);
+}
+
 void pci_resource_to_user(const struct pci_dev *dev, int bar,
                          const struct resource *rsrc,
                          resource_size_t *start, resource_size_t *end)
@@ -592,6 +718,12 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
                cpu_addr = of_translate_address(dev, ranges + 3);
                size = of_read_number(ranges + pna + 3, 2);
                ranges += np;
+
+               /* If we failed translation or got a zero-sized region
+                * (some FW try to feed us with non sensical zero sized regions
+                * such as power3 which look like some kind of attempt at exposing
+                * the VGA memory hole)
+                */
                if (cpu_addr == OF_BAD_ADDR || size == 0)
                        continue;
 
@@ -665,6 +797,8 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
                                isa_hole = memno;
                                if (primary || isa_mem_base == 0)
                                        isa_mem_base = cpu_addr;
+                               hose->isa_mem_phys = cpu_addr;
+                               hose->isa_mem_size = size;
                        }
 
                        /* We get the PCI/Mem offset from the first range or
index 92d20e993ede097d5e732a2bf0b751f9931eb7d1..2ece399f2862361aaa0789f08a49a4bae169043e 100644 (file)
@@ -232,6 +232,7 @@ static void __exit sputrace_exit(void)
 
        remove_proc_entry("sputrace", NULL);
        kfree(sputrace_log);
+       marker_synchronize_unregister();
 }
 
 module_init(sputrace_init);
index 49349ba77d80b81141deb6065510e54fc74eb077..5b9b12321ad132ed1987ae7e5a9bdf278cc4be7a 100644 (file)
@@ -26,6 +26,7 @@ config X86
        select HAVE_KPROBES
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select HAVE_KRETPROBES
+       select HAVE_FTRACE_MCOUNT_RECORD
        select HAVE_DYNAMIC_FTRACE
        select HAVE_FTRACE
        select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64)
@@ -1242,14 +1243,6 @@ config EFI
        resultant kernel should continue to boot on existing non-EFI
        platforms.
 
-config IRQBALANCE
-       def_bool y
-       prompt "Enable kernel irq balancing"
-       depends on X86_32 && SMP && X86_IO_APIC
-       help
-         The default yes will allow the kernel to do irq load balancing.
-         Saying no will keep the kernel from doing irq load balancing.
-
 config SECCOMP
        def_bool y
        prompt "Enable seccomp to safely compute untrusted bytecode"
index 52d0359719d7dda3c15ec870be577e653d829896..13b8c86ae98570f67375b505e9d106374e24b574 100644 (file)
@@ -287,7 +287,6 @@ CONFIG_MTRR=y
 # CONFIG_MTRR_SANITIZER is not set
 CONFIG_X86_PAT=y
 CONFIG_EFI=y
-# CONFIG_IRQBALANCE is not set
 CONFIG_SECCOMP=y
 # CONFIG_HZ_100 is not set
 # CONFIG_HZ_250 is not set
index 0d41f0343dc0753e5be4c97fd8b36460bc0ab2a5..d7e5a58ee22f376c13caab451ac1dcf6d4e33b08 100644 (file)
@@ -23,7 +23,7 @@ CFLAGS_hpet.o         := $(nostackp)
 CFLAGS_tsc.o           := $(nostackp)
 
 obj-y                  := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
-obj-y                  += traps.o irq_$(BITS).o dumpstack_$(BITS).o
+obj-y                  += traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o
 obj-y                  += time_$(BITS).o ioport.o ldt.o
 obj-y                  += setup.o i8259.o irqinit_$(BITS).o setup_percpu.o
 obj-$(CONFIG_X86_VISWS)        += visws_quirks.o
@@ -60,8 +60,8 @@ obj-$(CONFIG_X86_32_SMP)      += smpcommon.o
 obj-$(CONFIG_X86_64_SMP)       += tsc_sync.o smpcommon.o
 obj-$(CONFIG_X86_TRAMPOLINE)   += trampoline_$(BITS).o
 obj-$(CONFIG_X86_MPPARSE)      += mpparse.o
-obj-$(CONFIG_X86_LOCAL_APIC)   += apic_$(BITS).o nmi.o
-obj-$(CONFIG_X86_IO_APIC)      += io_apic_$(BITS).o
+obj-$(CONFIG_X86_LOCAL_APIC)   += apic.o nmi.o
+obj-$(CONFIG_X86_IO_APIC)      += io_apic.o
 obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o
 obj-$(CONFIG_DYNAMIC_FTRACE)   += ftrace.o
 obj-$(CONFIG_KEXEC)            += machine_kexec_$(BITS).o
@@ -108,7 +108,7 @@ obj-$(CONFIG_MICROCODE)                     += microcode.o
 # 64 bit specific files
 ifeq ($(CONFIG_X86_64),y)
         obj-y                          += genapic_64.o genapic_flat_64.o genx2apic_uv_x.o tlb_uv.o
-       obj-y                           += bios_uv.o
+       obj-y                           += bios_uv.o uv_irq.o uv_sysfs.o
         obj-y                          += genx2apic_cluster.o
         obj-y                          += genx2apic_phys.o
         obj-$(CONFIG_X86_PM_TIMER)     += pmtimer_64.o
index eb875cdc7367c3aee3fcb285606c1e993cc808af..0d1c26a583c59fb3329503b0f44d15fe148ec122 100644 (file)
@@ -1256,7 +1256,7 @@ static int __init acpi_parse_madt_ioapic_entries(void)
 
        count =
            acpi_table_parse_madt(ACPI_MADT_TYPE_INTERRUPT_OVERRIDE, acpi_parse_int_src_ovr,
-                                 NR_IRQ_VECTORS);
+                                 nr_irqs);
        if (count < 0) {
                printk(KERN_ERR PREFIX
                       "Error parsing interrupt source overrides entry\n");
@@ -1276,7 +1276,7 @@ static int __init acpi_parse_madt_ioapic_entries(void)
 
        count =
            acpi_table_parse_madt(ACPI_MADT_TYPE_NMI_SOURCE, acpi_parse_nmi_src,
-                                 NR_IRQ_VECTORS);
+                                 nr_irqs);
        if (count < 0) {
                printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n");
                /* TBD: Cleanup to allow fallback to MPS */
index 426e5d91b63a55d9b49d3387e2c40bb56306f104..c44cd6dbfa1414187213854db2ce3a1129298c76 100644 (file)
@@ -10,6 +10,7 @@
 #include <linux/dmi.h>
 #include <linux/cpumask.h>
 #include <asm/segment.h>
+#include <asm/desc.h>
 
 #include "realmode/wakeup.h"
 #include "sleep.h"
@@ -98,6 +99,8 @@ int acpi_save_state_mem(void)
        header->trampoline_segment = setup_trampoline() >> 4;
 #ifdef CONFIG_SMP
        stack_start.sp = temp_stack + 4096;
+       early_gdt_descr.address =
+                       (unsigned long)get_cpu_gdt_table(smp_processor_id());
 #endif
        initial_code = (unsigned long)wakeup_long64;
        saved_magic = 0x123456789abcdef0;
similarity index 79%
rename from arch/x86/kernel/apic_32.c
rename to arch/x86/kernel/apic.c
index 21c831d96af3d8f8ef63e6403f56fd0e71f5730c..04a7f960bbc0a2408907a959af527382dae477a5 100644 (file)
 #include <linux/mc146818rtc.h>
 #include <linux/kernel_stat.h>
 #include <linux/sysdev.h>
+#include <linux/ioport.h>
 #include <linux/cpu.h>
 #include <linux/clockchips.h>
 #include <linux/acpi_pmtmr.h>
 #include <linux/module.h>
 #include <linux/dmi.h>
+#include <linux/dmar.h>
 
 #include <asm/atomic.h>
 #include <asm/smp.h>
 #include <asm/desc.h>
 #include <asm/arch_hooks.h>
 #include <asm/hpet.h>
+#include <asm/pgalloc.h>
 #include <asm/i8253.h>
 #include <asm/nmi.h>
+#include <asm/idle.h>
+#include <asm/proto.h>
+#include <asm/timex.h>
+#include <asm/apic.h>
+#include <asm/i8259.h>
 
 #include <mach_apic.h>
 #include <mach_apicdef.h>
 # error SPURIOUS_APIC_VECTOR definition error
 #endif
 
-unsigned long mp_lapic_addr;
-
+#ifdef CONFIG_X86_32
 /*
  * Knob to control our willingness to enable the local APIC.
  *
  * +1=force-enable
  */
 static int force_enable_local_apic;
-int disable_apic;
+/*
+ * APIC command line parameters
+ */
+static int __init parse_lapic(char *arg)
+{
+       force_enable_local_apic = 1;
+       return 0;
+}
+early_param("lapic", parse_lapic);
+/* Local APIC was disabled by the BIOS and enabled by the kernel */
+static int enabled_via_apicbase;
+
+#endif
+
+#ifdef CONFIG_X86_64
+static int apic_calibrate_pmtmr __initdata;
+static __init int setup_apicpmtimer(char *s)
+{
+       apic_calibrate_pmtmr = 1;
+       notsc_setup(NULL);
+       return 0;
+}
+__setup("apicpmtimer", setup_apicpmtimer);
+#endif
+
+#ifdef CONFIG_X86_64
+#define HAVE_X2APIC
+#endif
+
+#ifdef HAVE_X2APIC
+int x2apic;
+/* x2apic enabled before OS handover */
+int x2apic_preenabled;
+int disable_x2apic;
+static __init int setup_nox2apic(char *str)
+{
+       disable_x2apic = 1;
+       setup_clear_cpu_cap(X86_FEATURE_X2APIC);
+       return 0;
+}
+early_param("nox2apic", setup_nox2apic);
+#endif
 
+unsigned long mp_lapic_addr;
+int disable_apic;
 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
 static int disable_apic_timer __cpuinitdata;
 /* Local APIC timer works in C2 */
@@ -110,9 +160,6 @@ static struct clock_event_device lapic_clockevent = {
 };
 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
 
-/* Local APIC was disabled by the BIOS and enabled by the kernel */
-static int enabled_via_apicbase;
-
 static unsigned long apic_phys;
 
 /*
@@ -202,6 +249,42 @@ static struct apic_ops xapic_ops = {
 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
 EXPORT_SYMBOL_GPL(apic_ops);
 
+#ifdef HAVE_X2APIC
+static void x2apic_wait_icr_idle(void)
+{
+       /* no need to wait for icr idle in x2apic */
+       return;
+}
+
+static u32 safe_x2apic_wait_icr_idle(void)
+{
+       /* no need to wait for icr idle in x2apic */
+       return 0;
+}
+
+void x2apic_icr_write(u32 low, u32 id)
+{
+       wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
+}
+
+u64 x2apic_icr_read(void)
+{
+       unsigned long val;
+
+       rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
+       return val;
+}
+
+static struct apic_ops x2apic_ops = {
+       .read = native_apic_msr_read,
+       .write = native_apic_msr_write,
+       .icr_read = x2apic_icr_read,
+       .icr_write = x2apic_icr_write,
+       .wait_icr_idle = x2apic_wait_icr_idle,
+       .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
+};
+#endif
+
 /**
  * enable_NMI_through_LVT0 - enable NMI through local vector table 0
  */
@@ -219,6 +302,7 @@ void __cpuinit enable_NMI_through_LVT0(void)
        apic_write(APIC_LVT0, v);
 }
 
+#ifdef CONFIG_X86_32
 /**
  * get_physical_broadcast - Get number of physical broadcast IDs
  */
@@ -226,6 +310,7 @@ int get_physical_broadcast(void)
 {
        return modern_apic() ? 0xff : 0xf;
 }
+#endif
 
 /**
  * lapic_get_maxlvt - get the maximum number of local vector table entries
@@ -247,11 +332,7 @@ int lapic_get_maxlvt(void)
  */
 
 /* Clock divisor */
-#ifdef CONFG_X86_64
-#define APIC_DIVISOR 1
-#else
 #define APIC_DIVISOR 16
-#endif
 
 /*
  * This function sets up the local APIC timer, with a timeout of
@@ -383,7 +464,7 @@ static void lapic_timer_broadcast(cpumask_t mask)
  * Setup the local APIC timer for this CPU. Copy the initilized values
  * of the boot CPU and register the clock event in the framework.
  */
-static void __devinit setup_APIC_timer(void)
+static void __cpuinit setup_APIC_timer(void)
 {
        struct clock_event_device *levt = &__get_cpu_var(lapic_events);
 
@@ -453,14 +534,51 @@ static void __init lapic_cal_handler(struct clock_event_device *dev)
        }
 }
 
+static int __init calibrate_by_pmtimer(long deltapm, long *delta)
+{
+       const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
+       const long pm_thresh = pm_100ms / 100;
+       unsigned long mult;
+       u64 res;
+
+#ifndef CONFIG_X86_PM_TIMER
+       return -1;
+#endif
+
+       apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
+
+       /* Check, if the PM timer is available */
+       if (!deltapm)
+               return -1;
+
+       mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
+
+       if (deltapm > (pm_100ms - pm_thresh) &&
+           deltapm < (pm_100ms + pm_thresh)) {
+               apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
+       } else {
+               res = (((u64)deltapm) *  mult) >> 22;
+               do_div(res, 1000000);
+               printk(KERN_WARNING "APIC calibration not consistent "
+                       "with PM Timer: %ldms instead of 100ms\n",
+                       (long)res);
+               /* Correct the lapic counter value */
+               res = (((u64)(*delta)) * pm_100ms);
+               do_div(res, deltapm);
+               printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
+                       "%lu (%ld)\n", (unsigned long)res, *delta);
+               *delta = (long)res;
+       }
+
+       return 0;
+}
+
 static int __init calibrate_APIC_clock(void)
 {
        struct clock_event_device *levt = &__get_cpu_var(lapic_events);
-       const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
-       const long pm_thresh = pm_100ms/100;
        void (*real_handler)(struct clock_event_device *dev);
        unsigned long deltaj;
-       long delta, deltapm;
+       long delta;
        int pm_referenced = 0;
 
        local_irq_disable();
@@ -470,10 +588,10 @@ static int __init calibrate_APIC_clock(void)
        global_clock_event->event_handler = lapic_cal_handler;
 
        /*
-        * Setup the APIC counter to 1e9. There is no way the lapic
+        * Setup the APIC counter to maximum. There is no way the lapic
         * can underflow in the 100ms detection time frame
         */
-       __setup_APIC_LVTT(1000000000, 0, 0);
+       __setup_APIC_LVTT(0xffffffff, 0, 0);
 
        /* Let the interrupts run */
        local_irq_enable();
@@ -490,34 +608,9 @@ static int __init calibrate_APIC_clock(void)
        delta = lapic_cal_t1 - lapic_cal_t2;
        apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
 
-       /* Check, if the PM timer is available */
-       deltapm = lapic_cal_pm2 - lapic_cal_pm1;
-       apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
-
-       if (deltapm) {
-               unsigned long mult;
-               u64 res;
-
-               mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
-
-               if (deltapm > (pm_100ms - pm_thresh) &&
-                   deltapm < (pm_100ms + pm_thresh)) {
-                       apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
-               } else {
-                       res = (((u64) deltapm) *  mult) >> 22;
-                       do_div(res, 1000000);
-                       printk(KERN_WARNING "APIC calibration not consistent "
-                              "with PM Timer: %ldms instead of 100ms\n",
-                              (long)res);
-                       /* Correct the lapic counter value */
-                       res = (((u64) delta) * pm_100ms);
-                       do_div(res, deltapm);
-                       printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
-                              "%lu (%ld)\n", (unsigned long) res, delta);
-                       delta = (long) res;
-               }
-               pm_referenced = 1;
-       }
+       /* we trust the PM based calibration if possible */
+       pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
+                                       &delta);
 
        /* Calculate the scaled math multiplication factor */
        lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
@@ -559,7 +652,10 @@ static int __init calibrate_APIC_clock(void)
 
        levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
 
-       /* We trust the pm timer based calibration */
+       /*
+        * PM timer calibration failed or not turned on
+        * so lets try APIC timer based calibration
+        */
        if (!pm_referenced) {
                apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
 
@@ -652,7 +748,7 @@ void __init setup_boot_APIC_clock(void)
        setup_APIC_timer();
 }
 
-void __devinit setup_secondary_APIC_clock(void)
+void __cpuinit setup_secondary_APIC_clock(void)
 {
        setup_APIC_timer();
 }
@@ -718,6 +814,9 @@ void smp_apic_timer_interrupt(struct pt_regs *regs)
         * Besides, if we don't timer interrupts ignore the global
         * interrupt lock, which is the WrongThing (tm) to do.
         */
+#ifdef CONFIG_X86_64
+       exit_idle();
+#endif
        irq_enter();
        local_apic_timer_interrupt();
        irq_exit();
@@ -991,40 +1090,43 @@ void __init init_bsp_APIC(void)
 
 static void __cpuinit lapic_setup_esr(void)
 {
-       unsigned long oldvalue, value, maxlvt;
-       if (lapic_is_integrated() && !esr_disable) {
-               if (esr_disable) {
-                       /*
-                        * Something untraceable is creating bad interrupts on
-                        * secondary quads ... for the moment, just leave the
-                        * ESR disabled - we can't do anything useful with the
-                        * errors anyway - mbligh
-                        */
-                       printk(KERN_INFO "Leaving ESR disabled.\n");
-                       return;
-               }
-               /* !82489DX */
-               maxlvt = lapic_get_maxlvt();
-               if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
-                       apic_write(APIC_ESR, 0);
-               oldvalue = apic_read(APIC_ESR);
+       unsigned int oldvalue, value, maxlvt;
+
+       if (!lapic_is_integrated()) {
+               printk(KERN_INFO "No ESR for 82489DX.\n");
+               return;
+       }
 
-               /* enables sending errors */
-               value = ERROR_APIC_VECTOR;
-               apic_write(APIC_LVTERR, value);
+       if (esr_disable) {
                /*
-                * spec says clear errors after enabling vector.
+                * Something untraceable is creating bad interrupts on
+                * secondary quads ... for the moment, just leave the
+                * ESR disabled - we can't do anything useful with the
+                * errors anyway - mbligh
                 */
-               if (maxlvt > 3)
-                       apic_write(APIC_ESR, 0);
-               value = apic_read(APIC_ESR);
-               if (value != oldvalue)
-                       apic_printk(APIC_VERBOSE, "ESR value before enabling "
-                               "vector: 0x%08lx  after: 0x%08lx\n",
-                               oldvalue, value);
-       } else {
-               printk(KERN_INFO "No ESR for 82489DX.\n");
+               printk(KERN_INFO "Leaving ESR disabled.\n");
+               return;
        }
+
+       maxlvt = lapic_get_maxlvt();
+       if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
+               apic_write(APIC_ESR, 0);
+       oldvalue = apic_read(APIC_ESR);
+
+       /* enables sending errors */
+       value = ERROR_APIC_VECTOR;
+       apic_write(APIC_LVTERR, value);
+
+       /*
+        * spec says clear errors after enabling vector.
+        */
+       if (maxlvt > 3)
+               apic_write(APIC_ESR, 0);
+       value = apic_read(APIC_ESR);
+       if (value != oldvalue)
+               apic_printk(APIC_VERBOSE, "ESR value before enabling "
+                       "vector: 0x%08x  after: 0x%08x\n",
+                       oldvalue, value);
 }
 
 
@@ -1033,24 +1135,27 @@ static void __cpuinit lapic_setup_esr(void)
  */
 void __cpuinit setup_local_APIC(void)
 {
-       unsigned long value, integrated;
+       unsigned int value;
        int i, j;
 
+#ifdef CONFIG_X86_32
        /* Pound the ESR really hard over the head with a big hammer - mbligh */
-       if (esr_disable) {
+       if (lapic_is_integrated() && esr_disable) {
                apic_write(APIC_ESR, 0);
                apic_write(APIC_ESR, 0);
                apic_write(APIC_ESR, 0);
                apic_write(APIC_ESR, 0);
        }
+#endif
 
-       integrated = lapic_is_integrated();
+       preempt_disable();
 
        /*
         * Double-check whether this APIC is really registered.
+        * This is meaningless in clustered apic mode, so we skip it.
         */
        if (!apic_id_registered())
-               WARN_ON_ONCE(1);
+               BUG();
 
        /*
         * Intel recommends to set DFR, LDR and TPR before enabling
@@ -1096,6 +1201,7 @@ void __cpuinit setup_local_APIC(void)
         */
        value |= APIC_SPIV_APIC_ENABLED;
 
+#ifdef CONFIG_X86_32
        /*
         * Some unknown Intel IO/APIC (or APIC) errata is biting us with
         * certain networking cards. If high frequency interrupts are
@@ -1116,8 +1222,13 @@ void __cpuinit setup_local_APIC(void)
         * See also the comment in end_level_ioapic_irq().  --macro
         */
 
-       /* Enable focus processor (bit==0) */
+       /*
+        * - enable focus processor (bit==0)
+        * - 64bit mode always use processor focus
+        *   so no need to set it
+        */
        value &= ~APIC_SPIV_FOCUS_DISABLED;
+#endif
 
        /*
         * Set spurious IRQ vector
@@ -1154,9 +1265,11 @@ void __cpuinit setup_local_APIC(void)
                value = APIC_DM_NMI;
        else
                value = APIC_DM_NMI | APIC_LVT_MASKED;
-       if (!integrated)                /* 82489DX */
+       if (!lapic_is_integrated())             /* 82489DX */
                value |= APIC_LVT_LEVEL_TRIGGER;
        apic_write(APIC_LVT1, value);
+
+       preempt_enable();
 }
 
 void __cpuinit end_local_APIC_setup(void)
@@ -1177,6 +1290,153 @@ void __cpuinit end_local_APIC_setup(void)
        apic_pm_activate();
 }
 
+#ifdef HAVE_X2APIC
+void check_x2apic(void)
+{
+       int msr, msr2;
+
+       rdmsr(MSR_IA32_APICBASE, msr, msr2);
+
+       if (msr & X2APIC_ENABLE) {
+               printk("x2apic enabled by BIOS, switching to x2apic ops\n");
+               x2apic_preenabled = x2apic = 1;
+               apic_ops = &x2apic_ops;
+       }
+}
+
+void enable_x2apic(void)
+{
+       int msr, msr2;
+
+       rdmsr(MSR_IA32_APICBASE, msr, msr2);
+       if (!(msr & X2APIC_ENABLE)) {
+               printk("Enabling x2apic\n");
+               wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+       }
+}
+
+void enable_IR_x2apic(void)
+{
+#ifdef CONFIG_INTR_REMAP
+       int ret;
+       unsigned long flags;
+
+       if (!cpu_has_x2apic)
+               return;
+
+       if (!x2apic_preenabled && disable_x2apic) {
+               printk(KERN_INFO
+                      "Skipped enabling x2apic and Interrupt-remapping "
+                      "because of nox2apic\n");
+               return;
+       }
+
+       if (x2apic_preenabled && disable_x2apic)
+               panic("Bios already enabled x2apic, can't enforce nox2apic");
+
+       if (!x2apic_preenabled && skip_ioapic_setup) {
+               printk(KERN_INFO
+                      "Skipped enabling x2apic and Interrupt-remapping "
+                      "because of skipping io-apic setup\n");
+               return;
+       }
+
+       ret = dmar_table_init();
+       if (ret) {
+               printk(KERN_INFO
+                      "dmar_table_init() failed with %d:\n", ret);
+
+               if (x2apic_preenabled)
+                       panic("x2apic enabled by bios. But IR enabling failed");
+               else
+                       printk(KERN_INFO
+                              "Not enabling x2apic,Intr-remapping\n");
+               return;
+       }
+
+       local_irq_save(flags);
+       mask_8259A();
+
+       ret = save_mask_IO_APIC_setup();
+       if (ret) {
+               printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret);
+               goto end;
+       }
+
+       ret = enable_intr_remapping(1);
+
+       if (ret && x2apic_preenabled) {
+               local_irq_restore(flags);
+               panic("x2apic enabled by bios. But IR enabling failed");
+       }
+
+       if (ret)
+               goto end_restore;
+
+       if (!x2apic) {
+               x2apic = 1;
+               apic_ops = &x2apic_ops;
+               enable_x2apic();
+       }
+
+end_restore:
+       if (ret)
+               /*
+                * IR enabling failed
+                */
+               restore_IO_APIC_setup();
+       else
+               reinit_intr_remapped_IO_APIC(x2apic_preenabled);
+
+end:
+       unmask_8259A();
+       local_irq_restore(flags);
+
+       if (!ret) {
+               if (!x2apic_preenabled)
+                       printk(KERN_INFO
+                              "Enabled x2apic and interrupt-remapping\n");
+               else
+                       printk(KERN_INFO
+                              "Enabled Interrupt-remapping\n");
+       } else
+               printk(KERN_ERR
+                      "Failed to enable Interrupt-remapping and x2apic\n");
+#else
+       if (!cpu_has_x2apic)
+               return;
+
+       if (x2apic_preenabled)
+               panic("x2apic enabled prior OS handover,"
+                     " enable CONFIG_INTR_REMAP");
+
+       printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
+              " and x2apic\n");
+#endif
+
+       return;
+}
+#endif /* HAVE_X2APIC */
+
+#ifdef CONFIG_X86_64
+/*
+ * Detect and enable local APICs on non-SMP boards.
+ * Original code written by Keir Fraser.
+ * On AMD64 we trust the BIOS - if it says no APIC it is likely
+ * not correctly set up (usually the APIC timer won't work etc.)
+ */
+static int __init detect_init_APIC(void)
+{
+       if (!cpu_has_apic) {
+               printk(KERN_INFO "No local APIC present\n");
+               return -1;
+       }
+
+       mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
+       boot_cpu_physical_apicid = 0;
+       return 0;
+}
+#else
 /*
  * Detect and initialize APIC
  */
@@ -1255,12 +1515,46 @@ no_apic:
        printk(KERN_INFO "No local APIC present or hardware disabled\n");
        return -1;
 }
+#endif
+
+#ifdef CONFIG_X86_64
+void __init early_init_lapic_mapping(void)
+{
+       unsigned long phys_addr;
+
+       /*
+        * If no local APIC can be found then go out
+        * : it means there is no mpatable and MADT
+        */
+       if (!smp_found_config)
+               return;
+
+       phys_addr = mp_lapic_addr;
+
+       set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
+       apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
+                   APIC_BASE, phys_addr);
+
+       /*
+        * Fetch the APIC ID of the BSP in case we have a
+        * default configuration (or the MP table is broken).
+        */
+       boot_cpu_physical_apicid = read_apic_id();
+}
+#endif
 
 /**
  * init_apic_mappings - initialize APIC mappings
  */
 void __init init_apic_mappings(void)
 {
+#ifdef HAVE_X2APIC
+       if (x2apic) {
+               boot_cpu_physical_apicid = read_apic_id();
+               return;
+       }
+#endif
+
        /*
         * If no local APIC can be found then set up a fake all
         * zeroes page to simulate the local APIC and another
@@ -1273,8 +1567,8 @@ void __init init_apic_mappings(void)
                apic_phys = mp_lapic_addr;
 
        set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
-       printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
-              apic_phys);
+       apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
+                               APIC_BASE, apic_phys);
 
        /*
         * Fetch the APIC ID of the BSP in case we have a
@@ -1282,18 +1576,27 @@ void __init init_apic_mappings(void)
         */
        if (boot_cpu_physical_apicid == -1U)
                boot_cpu_physical_apicid = read_apic_id();
-
 }
 
 /*
  * This initializes the IO-APIC and APIC hardware if this is
  * a UP kernel.
  */
-
 int apic_version[MAX_APICS];
 
 int __init APIC_init_uniprocessor(void)
 {
+#ifdef CONFIG_X86_64
+       if (disable_apic) {
+               printk(KERN_INFO "Apic disabled\n");
+               return -1;
+       }
+       if (!cpu_has_apic) {
+               disable_apic = 1;
+               printk(KERN_INFO "Apic disabled by BIOS\n");
+               return -1;
+       }
+#else
        if (!smp_found_config && !cpu_has_apic)
                return -1;
 
@@ -1302,39 +1605,68 @@ int __init APIC_init_uniprocessor(void)
         */
        if (!cpu_has_apic &&
            APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
-               printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
+               printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n",
                       boot_cpu_physical_apicid);
                clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
                return -1;
        }
+#endif
 
-       verify_local_APIC();
+#ifdef HAVE_X2APIC
+       enable_IR_x2apic();
+#endif
+#ifdef CONFIG_X86_64
+       setup_apic_routing();
+#endif
 
+       verify_local_APIC();
        connect_bsp_APIC();
 
+#ifdef CONFIG_X86_64
+       apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
+#else
        /*
         * Hack: In case of kdump, after a crash, kernel might be booting
         * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
         * might be zero if read from MP tables. Get it from LAPIC.
         */
-#ifdef CONFIG_CRASH_DUMP
+# ifdef CONFIG_CRASH_DUMP
        boot_cpu_physical_apicid = read_apic_id();
+# endif
 #endif
        physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
-
        setup_local_APIC();
 
+#ifdef CONFIG_X86_64
+       /*
+        * Now enable IO-APICs, actually call clear_IO_APIC
+        * We need clear_IO_APIC before enabling vector on BP
+        */
+       if (!skip_ioapic_setup && nr_ioapics)
+               enable_IO_APIC();
+#endif
+
 #ifdef CONFIG_X86_IO_APIC
        if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
 #endif
                localise_nmi_watchdog();
        end_local_APIC_setup();
+
 #ifdef CONFIG_X86_IO_APIC
-       if (smp_found_config)
-               if (!skip_ioapic_setup && nr_ioapics)
-                       setup_IO_APIC();
+       if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
+               setup_IO_APIC();
+# ifdef CONFIG_X86_64
+       else
+               nr_ioapics = 0;
+# endif
 #endif
+
+#ifdef CONFIG_X86_64
+       setup_boot_APIC_clock();
+       check_nmi_watchdog();
+#else
        setup_boot_clock();
+#endif
 
        return 0;
 }
@@ -1348,8 +1680,11 @@ int __init APIC_init_uniprocessor(void)
  */
 void smp_spurious_interrupt(struct pt_regs *regs)
 {
-       unsigned long v;
+       u32 v;
 
+#ifdef CONFIG_X86_64
+       exit_idle();
+#endif
        irq_enter();
        /*
         * Check if this really is a spurious interrupt and ACK it
@@ -1360,10 +1695,14 @@ void smp_spurious_interrupt(struct pt_regs *regs)
        if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
                ack_APIC_irq();
 
+#ifdef CONFIG_X86_64
+       add_pda(irq_spurious_count, 1);
+#else
        /* see sw-dev-man vol 3, chapter 7.4.13.5 */
        printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
               "should never happen.\n", smp_processor_id());
        __get_cpu_var(irq_stat).irq_spurious_count++;
+#endif
        irq_exit();
 }
 
@@ -1372,8 +1711,11 @@ void smp_spurious_interrupt(struct pt_regs *regs)
  */
 void smp_error_interrupt(struct pt_regs *regs)
 {
-       unsigned long v, v1;
+       u32 v, v1;
 
+#ifdef CONFIG_X86_64
+       exit_idle();
+#endif
        irq_enter();
        /* First tickle the hardware, only then report what went on. -- REW */
        v = apic_read(APIC_ESR);
@@ -1392,7 +1734,7 @@ void smp_error_interrupt(struct pt_regs *regs)
           6: Received illegal vector
           7: Illegal register address
        */
-       printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
+       printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
                smp_processor_id(), v , v1);
        irq_exit();
 }
@@ -1565,6 +1907,13 @@ void __cpuinit generic_processor_info(int apicid, int version)
        cpu_set(cpu, cpu_present_map);
 }
 
+#ifdef CONFIG_X86_64
+int hard_smp_processor_id(void)
+{
+       return read_apic_id();
+}
+#endif
+
 /*
  * Power management
  */
@@ -1640,7 +1989,7 @@ static int lapic_resume(struct sys_device *dev)
 
        local_irq_save(flags);
 
-#ifdef CONFIG_X86_64
+#ifdef HAVE_X2APIC
        if (x2apic)
                enable_x2apic();
        else
@@ -1702,7 +2051,7 @@ static struct sys_device device_lapic = {
        .cls    = &lapic_sysclass,
 };
 
-static void __devinit apic_pm_activate(void)
+static void __cpuinit apic_pm_activate(void)
 {
        apic_pm_state.active = 1;
 }
@@ -1728,16 +2077,87 @@ static void apic_pm_activate(void) { }
 
 #endif /* CONFIG_PM */
 
+#ifdef CONFIG_X86_64
 /*
- * APIC command line parameters
+ * apic_is_clustered_box() -- Check if we can expect good TSC
+ *
+ * Thus far, the major user of this is IBM's Summit2 series:
+ *
+ * Clustered boxes may have unsynced TSC problems if they are
+ * multi-chassis. Use available data to take a good guess.
+ * If in doubt, go HPET.
  */
-static int __init parse_lapic(char *arg)
+__cpuinit int apic_is_clustered_box(void)
 {
-       force_enable_local_apic = 1;
-       return 0;
+       int i, clusters, zeros;
+       unsigned id;
+       u16 *bios_cpu_apicid;
+       DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
+
+       /*
+        * there is not this kind of box with AMD CPU yet.
+        * Some AMD box with quadcore cpu and 8 sockets apicid
+        * will be [4, 0x23] or [8, 0x27] could be thought to
+        * vsmp box still need checking...
+        */
+       if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
+               return 0;
+
+       bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
+       bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
+
+       for (i = 0; i < NR_CPUS; i++) {
+               /* are we being called early in kernel startup? */
+               if (bios_cpu_apicid) {
+                       id = bios_cpu_apicid[i];
+               }
+               else if (i < nr_cpu_ids) {
+                       if (cpu_present(i))
+                               id = per_cpu(x86_bios_cpu_apicid, i);
+                       else
+                               continue;
+               }
+               else
+                       break;
+
+               if (id != BAD_APICID)
+                       __set_bit(APIC_CLUSTERID(id), clustermap);
+       }
+
+       /* Problem:  Partially populated chassis may not have CPUs in some of
+        * the APIC clusters they have been allocated.  Only present CPUs have
+        * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
+        * Since clusters are allocated sequentially, count zeros only if
+        * they are bounded by ones.
+        */
+       clusters = 0;
+       zeros = 0;
+       for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
+               if (test_bit(i, clustermap)) {
+                       clusters += 1 + zeros;
+                       zeros = 0;
+               } else
+                       ++zeros;
+       }
+
+       /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
+        * not guaranteed to be synced between boards
+        */
+       if (is_vsmp_box() && clusters > 1)
+               return 1;
+
+       /*
+        * If clusters > 2, then should be multi-chassis.
+        * May have to revisit this when multi-core + hyperthreaded CPUs come
+        * out, but AFAIK this will work even for them.
+        */
+       return (clusters > 2);
 }
-early_param("lapic", parse_lapic);
+#endif
 
+/*
+ * APIC command line parameters
+ */
 static int __init setup_disableapic(char *arg)
 {
        disable_apic = 1;
@@ -1779,7 +2199,6 @@ static int __init apic_set_verbosity(char *arg)
        if (!arg)  {
 #ifdef CONFIG_X86_64
                skip_ioapic_setup = 0;
-               ioapic_force = 1;
                return 0;
 #endif
                return -EINVAL;
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
deleted file mode 100644 (file)
index 94ddb69..0000000
+++ /dev/null
@@ -1,1848 +0,0 @@
-/*
- *     Local APIC handling, local APIC timers
- *
- *     (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
- *
- *     Fixes
- *     Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
- *                                     thanks to Eric Gilmore
- *                                     and Rolf G. Tews
- *                                     for testing these extensively.
- *     Maciej W. Rozycki       :       Various updates and fixes.
- *     Mikael Pettersson       :       Power Management for UP-APIC.
- *     Pavel Machek and
- *     Mikael Pettersson       :       PM converted to driver model.
- */
-
-#include <linux/init.h>
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/bootmem.h>
-#include <linux/interrupt.h>
-#include <linux/mc146818rtc.h>
-#include <linux/kernel_stat.h>
-#include <linux/sysdev.h>
-#include <linux/ioport.h>
-#include <linux/clockchips.h>
-#include <linux/acpi_pmtmr.h>
-#include <linux/module.h>
-#include <linux/dmar.h>
-
-#include <asm/atomic.h>
-#include <asm/smp.h>
-#include <asm/mtrr.h>
-#include <asm/mpspec.h>
-#include <asm/hpet.h>
-#include <asm/pgalloc.h>
-#include <asm/nmi.h>
-#include <asm/idle.h>
-#include <asm/proto.h>
-#include <asm/timex.h>
-#include <asm/apic.h>
-#include <asm/i8259.h>
-
-#include <mach_ipi.h>
-#include <mach_apic.h>
-
-/* Disable local APIC timer from the kernel commandline or via dmi quirk */
-static int disable_apic_timer __cpuinitdata;
-static int apic_calibrate_pmtmr __initdata;
-int disable_apic;
-int disable_x2apic;
-int x2apic;
-
-/* x2apic enabled before OS handover */
-int x2apic_preenabled;
-
-/* Local APIC timer works in C2 */
-int local_apic_timer_c2_ok;
-EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
-
-/*
- * Debug level, exported for io_apic.c
- */
-unsigned int apic_verbosity;
-
-/* Have we found an MP table */
-int smp_found_config;
-
-static struct resource lapic_resource = {
-       .name = "Local APIC",
-       .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
-};
-
-static unsigned int calibration_result;
-
-static int lapic_next_event(unsigned long delta,
-                           struct clock_event_device *evt);
-static void lapic_timer_setup(enum clock_event_mode mode,
-                             struct clock_event_device *evt);
-static void lapic_timer_broadcast(cpumask_t mask);
-static void apic_pm_activate(void);
-
-/*
- * The local apic timer can be used for any function which is CPU local.
- */
-static struct clock_event_device lapic_clockevent = {
-       .name           = "lapic",
-       .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
-                       | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
-       .shift          = 32,
-       .set_mode       = lapic_timer_setup,
-       .set_next_event = lapic_next_event,
-       .broadcast      = lapic_timer_broadcast,
-       .rating         = 100,
-       .irq            = -1,
-};
-static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
-
-static unsigned long apic_phys;
-
-unsigned long mp_lapic_addr;
-
-/*
- * Get the LAPIC version
- */
-static inline int lapic_get_version(void)
-{
-       return GET_APIC_VERSION(apic_read(APIC_LVR));
-}
-
-/*
- * Check, if the APIC is integrated or a separate chip
- */
-static inline int lapic_is_integrated(void)
-{
-#ifdef CONFIG_X86_64
-       return 1;
-#else
-       return APIC_INTEGRATED(lapic_get_version());
-#endif
-}
-
-/*
- * Check, whether this is a modern or a first generation APIC
- */
-static int modern_apic(void)
-{
-       /* AMD systems use old APIC versions, so check the CPU */
-       if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-           boot_cpu_data.x86 >= 0xf)
-               return 1;
-       return lapic_get_version() >= 0x14;
-}
-
-/*
- * Paravirt kernels also might be using these below ops. So we still
- * use generic apic_read()/apic_write(), which might be pointing to different
- * ops in PARAVIRT case.
- */
-void xapic_wait_icr_idle(void)
-{
-       while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
-               cpu_relax();
-}
-
-u32 safe_xapic_wait_icr_idle(void)
-{
-       u32 send_status;
-       int timeout;
-
-       timeout = 0;
-       do {
-               send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-               if (!send_status)
-                       break;
-               udelay(100);
-       } while (timeout++ < 1000);
-
-       return send_status;
-}
-
-void xapic_icr_write(u32 low, u32 id)
-{
-       apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
-       apic_write(APIC_ICR, low);
-}
-
-u64 xapic_icr_read(void)
-{
-       u32 icr1, icr2;
-
-       icr2 = apic_read(APIC_ICR2);
-       icr1 = apic_read(APIC_ICR);
-
-       return icr1 | ((u64)icr2 << 32);
-}
-
-static struct apic_ops xapic_ops = {
-       .read = native_apic_mem_read,
-       .write = native_apic_mem_write,
-       .icr_read = xapic_icr_read,
-       .icr_write = xapic_icr_write,
-       .wait_icr_idle = xapic_wait_icr_idle,
-       .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
-};
-
-struct apic_ops __read_mostly *apic_ops = &xapic_ops;
-EXPORT_SYMBOL_GPL(apic_ops);
-
-static void x2apic_wait_icr_idle(void)
-{
-       /* no need to wait for icr idle in x2apic */
-       return;
-}
-
-static u32 safe_x2apic_wait_icr_idle(void)
-{
-       /* no need to wait for icr idle in x2apic */
-       return 0;
-}
-
-void x2apic_icr_write(u32 low, u32 id)
-{
-       wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
-}
-
-u64 x2apic_icr_read(void)
-{
-       unsigned long val;
-
-       rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
-       return val;
-}
-
-static struct apic_ops x2apic_ops = {
-       .read = native_apic_msr_read,
-       .write = native_apic_msr_write,
-       .icr_read = x2apic_icr_read,
-       .icr_write = x2apic_icr_write,
-       .wait_icr_idle = x2apic_wait_icr_idle,
-       .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
-};
-
-/**
- * enable_NMI_through_LVT0 - enable NMI through local vector table 0
- */
-void __cpuinit enable_NMI_through_LVT0(void)
-{
-       unsigned int v;
-
-       /* unmask and set to NMI */
-       v = APIC_DM_NMI;
-
-       /* Level triggered for 82489DX (32bit mode) */
-       if (!lapic_is_integrated())
-               v |= APIC_LVT_LEVEL_TRIGGER;
-
-       apic_write(APIC_LVT0, v);
-}
-
-/**
- * lapic_get_maxlvt - get the maximum number of local vector table entries
- */
-int lapic_get_maxlvt(void)
-{
-       unsigned int v;
-
-       v = apic_read(APIC_LVR);
-       /*
-        * - we always have APIC integrated on 64bit mode
-        * - 82489DXs do not report # of LVT entries
-        */
-       return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
-}
-
-/*
- * Local APIC timer
- */
-
-/* Clock divisor */
-#ifdef CONFG_X86_64
-#define APIC_DIVISOR 1
-#else
-#define APIC_DIVISOR 16
-#endif
-
-/*
- * This function sets up the local APIC timer, with a timeout of
- * 'clocks' APIC bus clock. During calibration we actually call
- * this function twice on the boot CPU, once with a bogus timeout
- * value, second time for real. The other (noncalibrating) CPUs
- * call this function only once, with the real, calibrated value.
- *
- * We do reads before writes even if unnecessary, to get around the
- * P5 APIC double write bug.
- */
-static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
-{
-       unsigned int lvtt_value, tmp_value;
-
-       lvtt_value = LOCAL_TIMER_VECTOR;
-       if (!oneshot)
-               lvtt_value |= APIC_LVT_TIMER_PERIODIC;
-       if (!lapic_is_integrated())
-               lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
-
-       if (!irqen)
-               lvtt_value |= APIC_LVT_MASKED;
-
-       apic_write(APIC_LVTT, lvtt_value);
-
-       /*
-        * Divide PICLK by 16
-        */
-       tmp_value = apic_read(APIC_TDCR);
-       apic_write(APIC_TDCR,
-               (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
-               APIC_TDR_DIV_16);
-
-       if (!oneshot)
-               apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
-}
-
-/*
- * Setup extended LVT, AMD specific (K8, family 10h)
- *
- * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
- * MCE interrupts are supported. Thus MCE offset must be set to 0.
- *
- * If mask=1, the LVT entry does not generate interrupts while mask=0
- * enables the vector. See also the BKDGs.
- */
-
-#define APIC_EILVT_LVTOFF_MCE 0
-#define APIC_EILVT_LVTOFF_IBS 1
-
-static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
-{
-       unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
-       unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
-
-       apic_write(reg, v);
-}
-
-u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
-{
-       setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
-       return APIC_EILVT_LVTOFF_MCE;
-}
-
-u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
-{
-       setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
-       return APIC_EILVT_LVTOFF_IBS;
-}
-EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
-
-/*
- * Program the next event, relative to now
- */
-static int lapic_next_event(unsigned long delta,
-                           struct clock_event_device *evt)
-{
-       apic_write(APIC_TMICT, delta);
-       return 0;
-}
-
-/*
- * Setup the lapic timer in periodic or oneshot mode
- */
-static void lapic_timer_setup(enum clock_event_mode mode,
-                             struct clock_event_device *evt)
-{
-       unsigned long flags;
-       unsigned int v;
-
-       /* Lapic used as dummy for broadcast ? */
-       if (evt->features & CLOCK_EVT_FEAT_DUMMY)
-               return;
-
-       local_irq_save(flags);
-
-       switch (mode) {
-       case CLOCK_EVT_MODE_PERIODIC:
-       case CLOCK_EVT_MODE_ONESHOT:
-               __setup_APIC_LVTT(calibration_result,
-                                 mode != CLOCK_EVT_MODE_PERIODIC, 1);
-               break;
-       case CLOCK_EVT_MODE_UNUSED:
-       case CLOCK_EVT_MODE_SHUTDOWN:
-               v = apic_read(APIC_LVTT);
-               v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
-               apic_write(APIC_LVTT, v);
-               break;
-       case CLOCK_EVT_MODE_RESUME:
-               /* Nothing to do here */
-               break;
-       }
-
-       local_irq_restore(flags);
-}
-
-/*
- * Local APIC timer broadcast function
- */
-static void lapic_timer_broadcast(cpumask_t mask)
-{
-#ifdef CONFIG_SMP
-       send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
-#endif
-}
-
-/*
- * Setup the local APIC timer for this CPU. Copy the initilized values
- * of the boot CPU and register the clock event in the framework.
- */
-static void setup_APIC_timer(void)
-{
-       struct clock_event_device *levt = &__get_cpu_var(lapic_events);
-
-       memcpy(levt, &lapic_clockevent, sizeof(*levt));
-       levt->cpumask = cpumask_of_cpu(smp_processor_id());
-
-       clockevents_register_device(levt);
-}
-
-/*
- * In this function we calibrate APIC bus clocks to the external
- * timer. Unfortunately we cannot use jiffies and the timer irq
- * to calibrate, since some later bootup code depends on getting
- * the first irq? Ugh.
- *
- * We want to do the calibration only once since we
- * want to have local timer irqs syncron. CPUs connected
- * by the same APIC bus have the very same bus frequency.
- * And we want to have irqs off anyways, no accidental
- * APIC irq that way.
- */
-
-#define TICK_COUNT 100000000
-
-static int __init calibrate_APIC_clock(void)
-{
-       unsigned apic, apic_start;
-       unsigned long tsc, tsc_start;
-       int result;
-
-       local_irq_disable();
-
-       /*
-        * Put whatever arbitrary (but long enough) timeout
-        * value into the APIC clock, we just want to get the
-        * counter running for calibration.
-        *
-        * No interrupt enable !
-        */
-       __setup_APIC_LVTT(250000000, 0, 0);
-
-       apic_start = apic_read(APIC_TMCCT);
-#ifdef CONFIG_X86_PM_TIMER
-       if (apic_calibrate_pmtmr && pmtmr_ioport) {
-               pmtimer_wait(5000);  /* 5ms wait */
-               apic = apic_read(APIC_TMCCT);
-               result = (apic_start - apic) * 1000L / 5;
-       } else
-#endif
-       {
-               rdtscll(tsc_start);
-
-               do {
-                       apic = apic_read(APIC_TMCCT);
-                       rdtscll(tsc);
-               } while ((tsc - tsc_start) < TICK_COUNT &&
-                               (apic_start - apic) < TICK_COUNT);
-
-               result = (apic_start - apic) * 1000L * tsc_khz /
-                                       (tsc - tsc_start);
-       }
-
-       local_irq_enable();
-
-       printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
-
-       printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
-               result / 1000 / 1000, result / 1000 % 1000);
-
-       /* Calculate the scaled math multiplication factor */
-       lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
-                                      lapic_clockevent.shift);
-       lapic_clockevent.max_delta_ns =
-               clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
-       lapic_clockevent.min_delta_ns =
-               clockevent_delta2ns(0xF, &lapic_clockevent);
-
-       calibration_result = (result * APIC_DIVISOR) / HZ;
-
-       /*
-        * Do a sanity check on the APIC calibration result
-        */
-       if (calibration_result < (1000000 / HZ)) {
-               printk(KERN_WARNING
-                       "APIC frequency too slow, disabling apic timer\n");
-               return -1;
-       }
-
-       return 0;
-}
-
-/*
- * Setup the boot APIC
- *
- * Calibrate and verify the result.
- */
-void __init setup_boot_APIC_clock(void)
-{
-       /*
-        * The local apic timer can be disabled via the kernel
-        * commandline or from the CPU detection code. Register the lapic
-        * timer as a dummy clock event source on SMP systems, so the
-        * broadcast mechanism is used. On UP systems simply ignore it.
-        */
-       if (disable_apic_timer) {
-               printk(KERN_INFO "Disabling APIC timer\n");
-               /* No broadcast on UP ! */
-               if (num_possible_cpus() > 1) {
-                       lapic_clockevent.mult = 1;
-                       setup_APIC_timer();
-               }
-               return;
-       }
-
-       apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
-                   "calibrating APIC timer ...\n");
-
-       if (calibrate_APIC_clock()) {
-               /* No broadcast on UP ! */
-               if (num_possible_cpus() > 1)
-                       setup_APIC_timer();
-               return;
-       }
-
-       /*
-        * If nmi_watchdog is set to IO_APIC, we need the
-        * PIT/HPET going.  Otherwise register lapic as a dummy
-        * device.
-        */
-       if (nmi_watchdog != NMI_IO_APIC)
-               lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
-       else
-               printk(KERN_WARNING "APIC timer registered as dummy,"
-                       " due to nmi_watchdog=%d!\n", nmi_watchdog);
-
-       /* Setup the lapic or request the broadcast */
-       setup_APIC_timer();
-}
-
-void __cpuinit setup_secondary_APIC_clock(void)
-{
-       setup_APIC_timer();
-}
-
-/*
- * The guts of the apic timer interrupt
- */
-static void local_apic_timer_interrupt(void)
-{
-       int cpu = smp_processor_id();
-       struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
-
-       /*
-        * Normally we should not be here till LAPIC has been initialized but
-        * in some cases like kdump, its possible that there is a pending LAPIC
-        * timer interrupt from previous kernel's context and is delivered in
-        * new kernel the moment interrupts are enabled.
-        *
-        * Interrupts are enabled early and LAPIC is setup much later, hence
-        * its possible that when we get here evt->event_handler is NULL.
-        * Check for event_handler being NULL and discard the interrupt as
-        * spurious.
-        */
-       if (!evt->event_handler) {
-               printk(KERN_WARNING
-                      "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
-               /* Switch it off */
-               lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
-               return;
-       }
-
-       /*
-        * the NMI deadlock-detector uses this.
-        */
-#ifdef CONFIG_X86_64
-       add_pda(apic_timer_irqs, 1);
-#else
-       per_cpu(irq_stat, cpu).apic_timer_irqs++;
-#endif
-
-       evt->event_handler(evt);
-}
-
-/*
- * Local APIC timer interrupt. This is the most natural way for doing
- * local interrupts, but local timer interrupts can be emulated by
- * broadcast interrupts too. [in case the hw doesn't support APIC timers]
- *
- * [ if a single-CPU system runs an SMP kernel then we call the local
- *   interrupt as well. Thus we cannot inline the local irq ... ]
- */
-void smp_apic_timer_interrupt(struct pt_regs *regs)
-{
-       struct pt_regs *old_regs = set_irq_regs(regs);
-
-       /*
-        * NOTE! We'd better ACK the irq immediately,
-        * because timer handling can be slow.
-        */
-       ack_APIC_irq();
-       /*
-        * update_process_times() expects us to have done irq_enter().
-        * Besides, if we don't timer interrupts ignore the global
-        * interrupt lock, which is the WrongThing (tm) to do.
-        */
-       exit_idle();
-       irq_enter();
-       local_apic_timer_interrupt();
-       irq_exit();
-
-       set_irq_regs(old_regs);
-}
-
-int setup_profiling_timer(unsigned int multiplier)
-{
-       return -EINVAL;
-}
-
-
-/*
- * Local APIC start and shutdown
- */
-
-/**
- * clear_local_APIC - shutdown the local APIC
- *
- * This is called, when a CPU is disabled and before rebooting, so the state of
- * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
- * leftovers during boot.
- */
-void clear_local_APIC(void)
-{
-       int maxlvt;
-       u32 v;
-
-       /* APIC hasn't been mapped yet */
-       if (!apic_phys)
-               return;
-
-       maxlvt = lapic_get_maxlvt();
-       /*
-        * Masking an LVT entry can trigger a local APIC error
-        * if the vector is zero. Mask LVTERR first to prevent this.
-        */
-       if (maxlvt >= 3) {
-               v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
-               apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
-       }
-       /*
-        * Careful: we have to set masks only first to deassert
-        * any level-triggered sources.
-        */
-       v = apic_read(APIC_LVTT);
-       apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
-       v = apic_read(APIC_LVT0);
-       apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
-       v = apic_read(APIC_LVT1);
-       apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
-       if (maxlvt >= 4) {
-               v = apic_read(APIC_LVTPC);
-               apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
-       }
-
-       /* lets not touch this if we didn't frob it */
-#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
-       if (maxlvt >= 5) {
-               v = apic_read(APIC_LVTTHMR);
-               apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
-       }
-#endif
-       /*
-        * Clean APIC state for other OSs:
-        */
-       apic_write(APIC_LVTT, APIC_LVT_MASKED);
-       apic_write(APIC_LVT0, APIC_LVT_MASKED);
-       apic_write(APIC_LVT1, APIC_LVT_MASKED);
-       if (maxlvt >= 3)
-               apic_write(APIC_LVTERR, APIC_LVT_MASKED);
-       if (maxlvt >= 4)
-               apic_write(APIC_LVTPC, APIC_LVT_MASKED);
-
-       /* Integrated APIC (!82489DX) ? */
-       if (lapic_is_integrated()) {
-               if (maxlvt > 3)
-                       /* Clear ESR due to Pentium errata 3AP and 11AP */
-                       apic_write(APIC_ESR, 0);
-               apic_read(APIC_ESR);
-       }
-}
-
-/**
- * disable_local_APIC - clear and disable the local APIC
- */
-void disable_local_APIC(void)
-{
-       unsigned int value;
-
-       clear_local_APIC();
-
-       /*
-        * Disable APIC (implies clearing of registers
-        * for 82489DX!).
-        */
-       value = apic_read(APIC_SPIV);
-       value &= ~APIC_SPIV_APIC_ENABLED;
-       apic_write(APIC_SPIV, value);
-
-#ifdef CONFIG_X86_32
-       /*
-        * When LAPIC was disabled by the BIOS and enabled by the kernel,
-        * restore the disabled state.
-        */
-       if (enabled_via_apicbase) {
-               unsigned int l, h;
-
-               rdmsr(MSR_IA32_APICBASE, l, h);
-               l &= ~MSR_IA32_APICBASE_ENABLE;
-               wrmsr(MSR_IA32_APICBASE, l, h);
-       }
-#endif
-}
-
-/*
- * If Linux enabled the LAPIC against the BIOS default disable it down before
- * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
- * not power-off.  Additionally clear all LVT entries before disable_local_APIC
- * for the case where Linux didn't enable the LAPIC.
- */
-void lapic_shutdown(void)
-{
-       unsigned long flags;
-
-       if (!cpu_has_apic)
-               return;
-
-       local_irq_save(flags);
-
-#ifdef CONFIG_X86_32
-       if (!enabled_via_apicbase)
-               clear_local_APIC();
-       else
-#endif
-               disable_local_APIC();
-
-
-       local_irq_restore(flags);
-}
-
-/*
- * This is to verify that we're looking at a real local APIC.
- * Check these against your board if the CPUs aren't getting
- * started for no apparent reason.
- */
-int __init verify_local_APIC(void)
-{
-       unsigned int reg0, reg1;
-
-       /*
-        * The version register is read-only in a real APIC.
-        */
-       reg0 = apic_read(APIC_LVR);
-       apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
-       apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
-       reg1 = apic_read(APIC_LVR);
-       apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
-
-       /*
-        * The two version reads above should print the same
-        * numbers.  If the second one is different, then we
-        * poke at a non-APIC.
-        */
-       if (reg1 != reg0)
-               return 0;
-
-       /*
-        * Check if the version looks reasonably.
-        */
-       reg1 = GET_APIC_VERSION(reg0);
-       if (reg1 == 0x00 || reg1 == 0xff)
-               return 0;
-       reg1 = lapic_get_maxlvt();
-       if (reg1 < 0x02 || reg1 == 0xff)
-               return 0;
-
-       /*
-        * The ID register is read/write in a real APIC.
-        */
-       reg0 = apic_read(APIC_ID);
-       apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
-       apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
-       reg1 = apic_read(APIC_ID);
-       apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
-       apic_write(APIC_ID, reg0);
-       if (reg1 != (reg0 ^ APIC_ID_MASK))
-               return 0;
-
-       /*
-        * The next two are just to see if we have sane values.
-        * They're only really relevant if we're in Virtual Wire
-        * compatibility mode, but most boxes are anymore.
-        */
-       reg0 = apic_read(APIC_LVT0);
-       apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
-       reg1 = apic_read(APIC_LVT1);
-       apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
-
-       return 1;
-}
-
-/**
- * sync_Arb_IDs - synchronize APIC bus arbitration IDs
- */
-void __init sync_Arb_IDs(void)
-{
-       /*
-        * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
-        * needed on AMD.
-        */
-       if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
-               return;
-
-       /*
-        * Wait for idle.
-        */
-       apic_wait_icr_idle();
-
-       apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
-       apic_write(APIC_ICR, APIC_DEST_ALLINC |
-                       APIC_INT_LEVELTRIG | APIC_DM_INIT);
-}
-
-/*
- * An initial setup of the virtual wire mode.
- */
-void __init init_bsp_APIC(void)
-{
-       unsigned int value;
-
-       /*
-        * Don't do the setup now if we have a SMP BIOS as the
-        * through-I/O-APIC virtual wire mode might be active.
-        */
-       if (smp_found_config || !cpu_has_apic)
-               return;
-
-       /*
-        * Do not trust the local APIC being empty at bootup.
-        */
-       clear_local_APIC();
-
-       /*
-        * Enable APIC.
-        */
-       value = apic_read(APIC_SPIV);
-       value &= ~APIC_VECTOR_MASK;
-       value |= APIC_SPIV_APIC_ENABLED;
-
-#ifdef CONFIG_X86_32
-       /* This bit is reserved on P4/Xeon and should be cleared */
-       if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
-           (boot_cpu_data.x86 == 15))
-               value &= ~APIC_SPIV_FOCUS_DISABLED;
-       else
-#endif
-               value |= APIC_SPIV_FOCUS_DISABLED;
-       value |= SPURIOUS_APIC_VECTOR;
-       apic_write(APIC_SPIV, value);
-
-       /*
-        * Set up the virtual wire mode.
-        */
-       apic_write(APIC_LVT0, APIC_DM_EXTINT);
-       value = APIC_DM_NMI;
-       if (!lapic_is_integrated())             /* 82489DX */
-               value |= APIC_LVT_LEVEL_TRIGGER;
-       apic_write(APIC_LVT1, value);
-}
-
-static void __cpuinit lapic_setup_esr(void)
-{
-       unsigned long oldvalue, value, maxlvt;
-       if (lapic_is_integrated()&nb