Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 28 Jan 2010 20:56:23 +0000 (12:56 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 28 Jan 2010 20:56:23 +0000 (12:56 -0800)
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394-2.6:
  firewire: ohci: fix crashes with TSB43AB23 on 64bit systems
  firewire: core: fix use-after-free regression in FCP handler
  firewire: cdev: add_descriptor documentation fix
  firewire: core: add_descriptor size check

247 files changed:
MAINTAINERS
arch/arm/mach-omap1/clock.c
arch/arm/mach-omap2/clock34xx_data.c
arch/arm/mach-omap2/clock44xx_data.c
arch/arm/mach-omap2/cpuidle34xx.c
arch/arm/mach-omap2/gpmc.c
arch/arm/mach-omap2/id.c
arch/arm/mach-omap2/irq.c
arch/arm/mach-omap2/mux.c
arch/arm/mach-omap2/mux.h
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/pm-debug.c
arch/arm/mach-omap2/pm.h
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/prcm.c
arch/arm/mach-omap2/prm.h
arch/arm/mach-omap2/prm44xx.h
arch/arm/mach-omap2/sleep34xx.S
arch/arm/mach-s3c6410/mach-hmt.c
arch/arm/plat-omap/common.c
arch/arm/plat-omap/dma.c
arch/arm/plat-omap/dmtimer.c
arch/arm/plat-omap/include/plat/cpu.h
arch/arm/plat-omap/include/plat/irqs.h
arch/arm/plat-omap/include/plat/omap_hwmod.h
arch/powerpc/kvm/Kconfig
arch/s390/include/asm/irqflags.h
arch/s390/kernel/entry.S
arch/s390/kernel/entry64.S
arch/s390/kernel/signal.c
arch/s390/kvm/intercept.c
arch/sparc/Kconfig
arch/sparc/configs/sparc32_defconfig
arch/sparc/configs/sparc64_defconfig
arch/sparc/include/asm/io_32.h
arch/sparc/include/asm/page_32.h
arch/sparc/include/asm/param.h
arch/sparc/include/asm/timex_32.h
arch/sparc/include/asm/topology_64.h
arch/sparc/include/asm/uaccess_32.h
arch/sparc/include/asm/uaccess_64.h
arch/sparc/kernel/central.c
arch/sparc/kernel/irq_64.c
arch/sparc/kernel/pcic.c
arch/sparc/kernel/perf_event.c
arch/sparc/kernel/sys_sparc_64.c
arch/sparc/kernel/time_32.c
arch/sparc/mm/fault_32.c
arch/sparc/mm/fault_64.c
arch/x86/Kconfig
arch/x86/include/asm/cpu_debug.h [deleted file]
arch/x86/include/asm/hpet.h
arch/x86/include/asm/microcode.h
arch/x86/kernel/cpu/Makefile
arch/x86/kernel/cpu/cpu_debug.c [deleted file]
arch/x86/kernel/cpuid.c
arch/x86/kernel/hpet.c
arch/x86/kernel/microcode_amd.c
arch/x86/kernel/microcode_core.c
arch/x86/kernel/msr.c
arch/x86/kernel/quirks.c
arch/x86/kvm/lapic.c
arch/x86/kvm/mmu.c
arch/x86/kvm/paging_tmpl.h
arch/x86/kvm/x86.c
arch/x86/mm/srat_64.c
drivers/gpu/drm/drm_edid.c
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/drm_gem.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/nouveau/nouveau_bios.c
drivers/gpu/drm/nouveau/nouveau_bo.c
drivers/gpu/drm/nouveau/nouveau_connector.c
drivers/gpu/drm/nouveau/nouveau_dma.c
drivers/gpu/drm/nouveau/nouveau_dp.c
drivers/gpu/drm/nouveau/nouveau_drv.c
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_gem.c
drivers/gpu/drm/nouveau/nouveau_irq.c
drivers/gpu/drm/nouveau/nouveau_mem.c
drivers/gpu/drm/nouveau/nouveau_state.c
drivers/gpu/drm/nouveau/nv04_instmem.c
drivers/gpu/drm/nouveau/nv50_crtc.c
drivers/gpu/drm/nouveau/nv50_fifo.c
drivers/gpu/drm/nouveau/nv50_graph.c
drivers/gpu/drm/nouveau/nv50_sor.c
drivers/gpu/drm/radeon/atom.c
drivers/gpu/drm/radeon/atom.h
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r200.c
drivers/gpu/drm/radeon/r420.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600_blit_kms.c
drivers/gpu/drm/radeon/r600_cs.c
drivers/gpu/drm/radeon/r600d.h
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_agp.c
drivers/gpu/drm/radeon/radeon_clocks.c
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_object.c
drivers/gpu/drm/radeon/reg_srcs/r200
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/ttm/ttm_bo.c
drivers/gpu/drm/ttm/ttm_lock.c
drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
drivers/hwmon/amc6821.c
drivers/hwmon/asus_atk0110.c
drivers/hwmon/fschmd.c
drivers/hwmon/smsc47m1.c
drivers/i2c/busses/i2c-imx.c
drivers/message/fusion/mptbase.c
drivers/mtd/maps/Kconfig
drivers/mtd/maps/pismo.c [new file with mode: 0644]
drivers/mtd/mtdoops.c
drivers/mtd/tests/mtd_readtest.c
drivers/mtd/tests/mtd_speedtest.c
drivers/mtd/tests/mtd_stresstest.c
drivers/mtd/ubi/kapi.c
drivers/mtd/ubi/upd.c
drivers/mtd/ubi/vtbl.c
drivers/net/benet/be_cmds.c
drivers/net/benet/be_main.c
drivers/net/bfin_mac.c
drivers/net/e1000/e1000.h
drivers/net/e1000/e1000_main.c
drivers/net/e1000e/e1000.h
drivers/net/e1000e/netdev.c
drivers/net/igb/igb_main.c
drivers/net/igbvf/netdev.c
drivers/net/ixgb/ixgb_main.c
drivers/net/ixgbe/ixgbe_main.c
drivers/net/pcmcia/fmvj18x_cs.c
drivers/net/phy/phy.c
drivers/net/phy/phy_device.c
drivers/net/qlge/qlge_main.c
drivers/net/s2io.c
drivers/net/sfc/mcdi.c
drivers/net/sfc/mcdi.h
drivers/net/sfc/mcdi_pcol.h
drivers/net/sfc/mtd.c
drivers/net/sfc/qt202x_phy.c
drivers/net/sky2.c
drivers/net/tulip/tulip_core.c
drivers/net/ucc_geth.c
drivers/net/virtio_net.c
drivers/net/wimax/i2400m/i2400m-usb.h
drivers/net/wimax/i2400m/usb.c
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/iwlwifi/iwl-devtrace.c
drivers/net/wireless/iwlwifi/iwl-devtrace.h
drivers/net/wireless/iwmc3200wifi/commands.c
drivers/net/wireless/iwmc3200wifi/commands.h
drivers/net/wireless/p54/p54pci.c
drivers/net/wireless/zd1211rw/zd_usb.c
drivers/s390/block/dasd.c
drivers/s390/block/dasd_eckd.c
drivers/s390/block/dasd_ioctl.c
drivers/s390/block/dasd_proc.c
drivers/s390/char/sclp_vt220.c
drivers/s390/crypto/zcrypt_pcicc.c
drivers/s390/crypto/zcrypt_pcixcc.c
drivers/s390/scsi/zfcp_cfdc.c
drivers/s390/scsi/zfcp_dbf.c
drivers/s390/scsi/zfcp_ext.h
drivers/s390/scsi/zfcp_fc.c
drivers/s390/scsi/zfcp_fc.h
drivers/s390/scsi/zfcp_fsf.c
drivers/s390/scsi/zfcp_scsi.c
drivers/scsi/aacraid/aachba.c
drivers/scsi/aacraid/aacraid.h
drivers/scsi/aacraid/commctrl.c
drivers/scsi/aacraid/comminit.c
drivers/scsi/aacraid/commsup.c
drivers/scsi/aacraid/dpcsup.c
drivers/scsi/aic7xxx/aic79xx_core.c
drivers/scsi/lpfc/lpfc_hbadisc.c [changed mode: 0755->0644]
drivers/scsi/lpfc/lpfc_hw4.h [changed mode: 0755->0644]
drivers/scsi/qla2xxx/qla_def.h
drivers/scsi/qla2xxx/qla_init.c
drivers/scsi/qla2xxx/qla_os.c
drivers/scsi/qla2xxx/qla_sup.c
drivers/scsi/qla2xxx/qla_version.h
drivers/scsi/scsi_lib.c
drivers/scsi/scsi_transport_fc.c
drivers/serial/serial_cs.c
drivers/watchdog/Kconfig
drivers/watchdog/ixp2000_wdt.c
drivers/watchdog/sbc_fitpc2_wdt.c
fs/eventfd.c
fs/ext4/ext4.h
fs/ext4/extents.c
fs/ext4/inode.c
fs/fcntl.c
include/drm/ttm/ttm_bo_driver.h
include/linux/eventfd.h
include/linux/kmsg_dump.h
include/linux/mtd/pismo.h [new file with mode: 0644]
include/linux/pagemap.h
include/linux/phy.h
include/net/netns/xfrm.h
include/net/netrom.h
include/net/xfrm.h
include/scsi/scsi_bsg_fc.h
kernel/kexec.c
kernel/panic.c
kernel/printk.c
kernel/time/clockevents.c
mm/filemap.c
net/8021q/vlan_dev.c
net/appletalk/aarp.c
net/ax25/ax25_out.c
net/dccp/ccid.c
net/dccp/ccid.h
net/dccp/probe.c
net/ipv4/inet_diag.c
net/ipv4/route.c
net/ipv4/tcp_probe.c
net/ipv4/xfrm4_policy.c
net/ipv6/xfrm6_policy.c
net/mac80211/cfg.c
net/mac80211/rc80211_pid_algo.c
net/netrom/nr_route.c
net/rose/rose_link.c
net/rose/rose_route.c
net/wireless/sme.c
net/xfrm/xfrm_policy.c
net/xfrm/xfrm_state.c
net/xfrm/xfrm_user.c
sound/pci/hda/patch_realtek.c
sound/soc/codecs/wm8903.c
virt/kvm/eventfd.c
virt/kvm/irq_comm.c

index 1858646b52e345246ef2d603279a92bff520080e..03f38c18f3236718bf4bff40fa5ffaffce5bbcbe 100644 (file)
@@ -987,7 +987,6 @@ F:  drivers/platform/x86/asus-laptop.c
 
 ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API
 M:     Dan Williams <dan.j.williams@intel.com>
-M:     Maciej Sosnowski <maciej.sosnowski@intel.com>
 W:     http://sourceforge.net/projects/xscaleiop
 S:     Supported
 F:     Documentation/crypto/async-tx-api.txt
@@ -1823,7 +1822,6 @@ S:        Supported
 F:     fs/dlm/
 
 DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
-M:     Maciej Sosnowski <maciej.sosnowski@intel.com>
 M:     Dan Williams <dan.j.williams@intel.com>
 S:     Supported
 F:     drivers/dma/
@@ -2786,7 +2784,7 @@ F:        arch/x86/kernel/microcode_core.c
 F:     arch/x86/kernel/microcode_intel.c
 
 INTEL I/OAT DMA DRIVER
-M:     Maciej Sosnowski <maciej.sosnowski@intel.com>
+M:     Dan Williams <dan.j.williams@intel.com>
 S:     Supported
 F:     drivers/dma/ioat*
 
@@ -2824,10 +2822,11 @@ L:      netdev@vger.kernel.org
 S:     Maintained
 F:     drivers/net/ixp2000/
 
-INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/ixgb/ixgbe)
+INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe)
 M:     Jeff Kirsher <jeffrey.t.kirsher@intel.com>
 M:     Jesse Brandeburg <jesse.brandeburg@intel.com>
 M:     Bruce Allan <bruce.w.allan@intel.com>
+M:     Alex Duyck <alexander.h.duyck@intel.com>
 M:     PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>
 M:     John Ronciak <john.ronciak@intel.com>
 L:     e1000-devel@lists.sourceforge.net
@@ -2837,6 +2836,7 @@ F:        drivers/net/e100.c
 F:     drivers/net/e1000/
 F:     drivers/net/e1000e/
 F:     drivers/net/igb/
+F:     drivers/net/igbvf/
 F:     drivers/net/ixgb/
 F:     drivers/net/ixgbe/
 
index 2ba9ab95373114507acd51460b0406cb59be8b2b..04f1d29cba2c231033133da8d6ae7eb3c360c6ab 100644 (file)
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
        struct mpu_rate * ptr;
        unsigned long dpll1_rate, ref_rate;
 
-       dpll1_rate = clk_get_rate(ck_dpll1_p);
-       ref_rate = clk_get_rate(ck_ref_p);
+       dpll1_rate = ck_dpll1_p->rate;
+       ref_rate = ck_ref_p->rate;
 
        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
                if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
        long highest_rate;
        unsigned long ref_rate;
 
-       ref_rate = clk_get_rate(ck_ref_p);
+       ref_rate = ck_ref_p->rate;
 
        highest_rate = -EINVAL;
 
index c6031d74d6f68bd5710d85e0c87c30f80c7cec47..74930e3158e30b146f722a17c3de92b419b84d2d 100644 (file)
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
        .name           = "dpll4_m3x2_ck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &dpll4_m3_ck,
-       .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
        .flags          = INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
        .name           = "dpll4_m6x2_ck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &dpll4_m6_ck,
-       .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
        .flags          = INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
        .name           = "iva2_ck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &dpll2_m2_ck,
-       .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
        .clkdm_name     = "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
        .name           = "gfx_l3_ck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l3_ick,
-       .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
        .enable_bit     = OMAP_EN_GFX_SHIFT,
        .recalc         = &followparent_recalc,
index 2210e227d78a2b93fdd9ccba0d84f94a26cbb0bd..9d882bcb56e38b976b085a44dd12132e533aa127 100644 (file)
@@ -346,37 +346,37 @@ static struct clk aess_fclk = {
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
-       { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-       { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-       { .div = 3, .val = 2, .flags = RATE_IN_4430 },
-       { .div = 4, .val = 3, .flags = RATE_IN_4430 },
-       { .div = 5, .val = 4, .flags = RATE_IN_4430 },
-       { .div = 6, .val = 5, .flags = RATE_IN_4430 },
-       { .div = 7, .val = 6, .flags = RATE_IN_4430 },
-       { .div = 8, .val = 7, .flags = RATE_IN_4430 },
-       { .div = 9, .val = 8, .flags = RATE_IN_4430 },
-       { .div = 10, .val = 9, .flags = RATE_IN_4430 },
-       { .div = 11, .val = 10, .flags = RATE_IN_4430 },
-       { .div = 12, .val = 11, .flags = RATE_IN_4430 },
-       { .div = 13, .val = 12, .flags = RATE_IN_4430 },
-       { .div = 14, .val = 13, .flags = RATE_IN_4430 },
-       { .div = 15, .val = 14, .flags = RATE_IN_4430 },
-       { .div = 16, .val = 15, .flags = RATE_IN_4430 },
-       { .div = 17, .val = 16, .flags = RATE_IN_4430 },
-       { .div = 18, .val = 17, .flags = RATE_IN_4430 },
-       { .div = 19, .val = 18, .flags = RATE_IN_4430 },
-       { .div = 20, .val = 19, .flags = RATE_IN_4430 },
-       { .div = 21, .val = 20, .flags = RATE_IN_4430 },
-       { .div = 22, .val = 21, .flags = RATE_IN_4430 },
-       { .div = 23, .val = 22, .flags = RATE_IN_4430 },
-       { .div = 24, .val = 23, .flags = RATE_IN_4430 },
-       { .div = 25, .val = 24, .flags = RATE_IN_4430 },
-       { .div = 26, .val = 25, .flags = RATE_IN_4430 },
-       { .div = 27, .val = 26, .flags = RATE_IN_4430 },
-       { .div = 28, .val = 27, .flags = RATE_IN_4430 },
-       { .div = 29, .val = 28, .flags = RATE_IN_4430 },
-       { .div = 30, .val = 29, .flags = RATE_IN_4430 },
-       { .div = 31, .val = 30, .flags = RATE_IN_4430 },
+       { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+       { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+       { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+       { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+       { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+       { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+       { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+       { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+       { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+       { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+       { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+       { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+       { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+       { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+       { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+       { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+       { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+       { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+       { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+       { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+       { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+       { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+       { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+       { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+       { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+       { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+       { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+       { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+       { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+       { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+       { .div = 31, .val = 31, .flags = RATE_IN_4430 },
        { .div = 0 },
 };
 
index a26d6a08ae3f86dd49f3098772c36d481a570c34..12f0cbfc2894483ae10160efbad4d86406fb1e34 100644 (file)
@@ -137,7 +137,7 @@ return_sleep_time:
        local_irq_enable();
        local_fiq_enable();
 
-       return (u32)timespec_to_ns(&ts_idle)/1000;
+       return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
 }
 
 /**
index bd8cb5974726bb670da33dd078965eb49ef96471..3f1334f62e7af42b521533b7edb80260d6e3faad 100644 (file)
@@ -534,6 +534,8 @@ void __init gpmc_init(void)
                BUG();
        }
 
+       clk_enable(gpmc_l3_clk);
+
        l = gpmc_read_reg(GPMC_REVISION);
        printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
        /* Set smart idle mode and automatic L3 clock gating */
index a091b53657b9744514dc1683e32194cccb261888..3d65c50bd0174bba7a209b80f4b02f6edf19abb3 100644 (file)
@@ -188,6 +188,8 @@ void __init omap3_check_revision(void)
        u16 hawkeye;
        u8 rev;
 
+       omap_chip.oc = CHIP_IS_OMAP3430;
+
        /*
         * We cannot access revision registers on ES1.0.
         * If the processor type is Cortex-A8 and the revision is 0x0
@@ -196,6 +198,7 @@ void __init omap3_check_revision(void)
        cpuid = read_cpuid(CPUID_ID);
        if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                omap_revision = OMAP3430_REV_ES1_0;
+               omap_chip.oc |= CHIP_IS_OMAP3430ES1;
                return;
        }
 
@@ -216,18 +219,28 @@ void __init omap3_check_revision(void)
                case 0: /* Take care of early samples */
                case 1:
                        omap_revision = OMAP3430_REV_ES2_0;
+                       omap_chip.oc |= CHIP_IS_OMAP3430ES2;
                        break;
                case 2:
                        omap_revision = OMAP3430_REV_ES2_1;
+                       omap_chip.oc |= CHIP_IS_OMAP3430ES2;
                        break;
                case 3:
                        omap_revision = OMAP3430_REV_ES3_0;
+                       omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
                        break;
                case 4:
+                       omap_revision = OMAP3430_REV_ES3_1;
+                       omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+                       break;
+               case 7:
                /* FALLTHROUGH */
                default:
                        /* Use the latest known revision as default */
-                       omap_revision = OMAP3430_REV_ES3_1;
+                       omap_revision = OMAP3430_REV_ES3_1_2;
+
+                       /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
+                       omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
                }
                break;
        case 0xb868:
@@ -235,14 +248,18 @@ void __init omap3_check_revision(void)
                 *
                 * Set the device to be OMAP3505 here. Actual device
                 * is identified later based on the features.
+                *
+                * REVISIT: AM3505/AM3517 should have their own CHIP_IS
                 */
                omap_revision = OMAP3505_REV(rev);
+               omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
                break;
        case 0xb891:
        /* FALLTHROUGH */
        default:
                /* Unknown default to latest silicon rev as default*/
                omap_revision = OMAP3630_REV_ES1_0;
+               omap_chip.oc |= CHIP_IS_OMAP3630ES1;
        }
 }
 
@@ -360,6 +377,7 @@ void __init omap2_check_revision(void)
                omap3_check_revision();
                omap3_check_features();
                omap3_cpuinfo();
+               return;
        } else if (cpu_is_omap44xx()) {
                omap4_check_revision();
                return;
@@ -374,27 +392,14 @@ void __init omap2_check_revision(void)
        if (cpu_is_omap243x()) {
                /* Currently only supports 2430ES2.1 and 2430-all */
                omap_chip.oc |= CHIP_IS_OMAP2430;
+               return;
        } else if (cpu_is_omap242x()) {
                /* Currently only supports 2420ES2.1.1 and 2420-all */
                omap_chip.oc |= CHIP_IS_OMAP2420;
-       } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
-               omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
-       } else if (cpu_is_omap343x()) {
-               omap_chip.oc = CHIP_IS_OMAP3430;
-               if (omap_rev() == OMAP3430_REV_ES1_0)
-                       omap_chip.oc |= CHIP_IS_OMAP3430ES1;
-               else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
-                        omap_rev() <= OMAP3430_REV_ES2_1)
-                       omap_chip.oc |= CHIP_IS_OMAP3430ES2;
-               else if (omap_rev() == OMAP3430_REV_ES3_0)
-                       omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
-               else if (omap_rev() == OMAP3430_REV_ES3_1)
-                       omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
-               else if (omap_rev() == OMAP3630_REV_ES1_0)
-                       omap_chip.oc |= CHIP_IS_OMAP3630ES1;
-       } else {
-               pr_err("Uninitialized omap_chip, please fix!\n");
+               return;
        }
+
+       pr_err("Uninitialized omap_chip, please fix!\n");
 }
 
 /*
index e9bc782fa414fad906db2740ac274d119910f894..27054025da2b5056ad6f15fe0223446f48e8359f 100644 (file)
@@ -274,4 +274,22 @@ void omap_intc_restore_context(void)
        }
        /* MIRs are saved and restore with other PRCM registers */
 }
+
+void omap3_intc_suspend(void)
+{
+       /* A pending interrupt would prevent OMAP from entering suspend */
+       omap_ack_irq(0);
+}
+
+void omap3_intc_prepare_idle(void)
+{
+       /* Disable autoidle as it can stall interrupt controller */
+       intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
+}
+
+void omap3_intc_resume_idle(void)
+{
+       /* Re-enable autoidle */
+       intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
index 459ef23ab8a818539aaa0da0464d5cf9e7af49bd..3f59bd12cbbfe857b34cae75ebe6bfd8c3996f35 100644 (file)
@@ -51,7 +51,7 @@ struct omap_mux_entry {
 static unsigned long mux_phys;
 static void __iomem *mux_base;
 
-static inline u16 omap_mux_read(u16 reg)
+u16 omap_mux_read(u16 reg)
 {
        if (cpu_is_omap24xx())
                return __raw_readb(mux_base + reg);
@@ -59,7 +59,7 @@ static inline u16 omap_mux_read(u16 reg)
                return __raw_readw(mux_base + reg);
 }
 
-static inline void omap_mux_write(u16 val, u16 reg)
+void omap_mux_write(u16 val, u16 reg)
 {
        if (cpu_is_omap24xx())
                __raw_writeb(val, mux_base + reg);
@@ -67,6 +67,14 @@ static inline void omap_mux_write(u16 val, u16 reg)
                __raw_writew(val, mux_base + reg);
 }
 
+void omap_mux_write_array(struct omap_board_mux *board_mux)
+{
+       while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
+               omap_mux_write(board_mux->value, board_mux->reg_offset);
+               board_mux++;
+       }
+}
+
 #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
 
 static struct omap_mux_cfg arch_mux_cfg;
@@ -833,14 +841,6 @@ static void __init omap_mux_set_cmdline_signals(void)
        kfree(options);
 }
 
-static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
-{
-       while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
-               omap_mux_write(board_mux->value, board_mux->reg_offset);
-               board_mux++;
-       }
-}
-
 static int __init omap_mux_copy_names(struct omap_mux *src,
                                        struct omap_mux *dst)
 {
@@ -998,12 +998,15 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
                omap_mux_package_fixup(package_subset, superset);
        if (package_balls)
                omap_mux_package_init_balls(package_balls, superset);
-       omap_mux_set_cmdline_signals();
-       omap_mux_set_board_signals(board_mux);
 #endif
 
        omap_mux_init_list(superset);
 
+#ifdef CONFIG_OMAP_MUX
+       omap_mux_set_cmdline_signals();
+       omap_mux_write_array(board_mux);
+#endif
+
        return 0;
 }
 
index d8b4d5ad22783ffe342611ba801a07a709ce6b18..f8c2e7a8f063afc4cc46284c7556c0bd482a17e7 100644 (file)
@@ -146,6 +146,30 @@ u16 omap_mux_get_gpio(int gpio);
  */
 void omap_mux_set_gpio(u16 val, int gpio);
 
+/**
+ * omap_mux_read() - read mux register
+ * @mux_offset:                Offset of the mux register
+ *
+ */
+u16 omap_mux_read(u16 mux_offset);
+
+/**
+ * omap_mux_write() - write mux register
+ * @val:               New mux register value
+ * @mux_offset:                Offset of the mux register
+ *
+ * This should be only needed for dynamic remuxing of non-gpio signals.
+ */
+void omap_mux_write(u16 val, u16 mux_offset);
+
+/**
+ * omap_mux_write_array() - write an array of mux registers
+ * @board_mux:         Array of mux registers terminated by MAP_MUX_TERMINATOR
+ *
+ * This should be only needed for dynamic remuxing of non-gpio signals.
+ */
+void omap_mux_write_array(struct omap_board_mux *board_mux);
+
 /**
  * omap3_mux_init() - initialize mux system with board specific set
  * @board_mux:         Board specific mux table
index d8c8545875b18b84aa89449ffa87911d687d129e..478ae585ca39666327500057fd1a85e014e19657 100644 (file)
@@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
 
        oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
 
-       oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
+       if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
+               oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
 
        return 0;
 }
index 860b755d222074ce1bb061510f3a16fbc2cafa5b..a0866268aa41d1cdfe49a623b2265601f2ef75f6 100644 (file)
@@ -54,8 +54,6 @@ int omap2_pm_debug;
        regs[reg_count++].val = \
                         __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
 
-static int __init pm_dbg_init(void);
-
 void omap2_pm_dump(int mode, int resume, unsigned int us)
 {
        struct reg {
@@ -167,6 +165,8 @@ struct dentry *pm_dbg_dir;
 
 static int pm_dbg_init_done;
 
+static int __init pm_dbg_init(void);
+
 enum {
        DEBUG_FILE_COUNTERS = 0,
        DEBUG_FILE_TIMERS,
@@ -488,9 +488,11 @@ int pm_dbg_regset_init(int reg_set)
 
 static int pwrdm_suspend_get(void *data, u64 *val)
 {
-       *val = omap3_pm_get_suspend_state((struct powerdomain *)data);
+       int ret;
+       ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
+       *val = ret;
 
-       if (*val >= 0)
+       if (ret >= 0)
                return 0;
        return *val;
 }
@@ -604,6 +606,4 @@ static int __init pm_dbg_init(void)
 }
 arch_initcall(pm_dbg_init);
 
-#else
-void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
 #endif
index 0bf345db7147bc2ad88da43cfaab0e80db328f56..7a9c2d004511f9afff6c03636ef64751dd5a5036 100644 (file)
@@ -32,12 +32,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
+#else
+#define omap2_pm_dump(mode, resume, us)                do {} while (0);
+#define omap2_pm_debug                         0
+#endif
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
 extern int pm_dbg_regset_save(int reg_set);
 extern int pm_dbg_regset_init(int reg_set);
 #else
-#define omap2_pm_dump(mode, resume, us)                do {} while (0);
-#define omap2_pm_debug                         0
 #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
 #define pm_dbg_regset_save(reg_set) do {} while (0);
 #define pm_dbg_regset_init(reg_set) do {} while (0);
index c6cc809afb790fa5a0624f5a3e2f118c4aba3fa3..910a7acf542d1bd1257cfeff37cbf23403eaf7b5 100644 (file)
@@ -26,6 +26,7 @@
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 
 #include <plat/sram.h>
 #include <plat/clockdomain.h>
@@ -126,7 +127,15 @@ static void omap3_core_save_context(void)
        /* wait for the save to complete */
        while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
                        & PADCONF_SAVE_DONE))
-               ;
+               udelay(1);
+
+       /*
+        * Force write last pad into memory, as this can fail in some
+        * cases according to erratas 1.157, 1.185
+        */
+       omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
+               OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
+
        /* Save the Interrupt controller context */
        omap_intc_save_context();
        /* Save the GPMC context */
@@ -392,6 +401,7 @@ void omap_sram_idle(void)
                prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
                omap3_enable_io_chain();
        }
+       omap3_intc_prepare_idle();
 
        /*
        * On EMU/HS devices ROM code restores a SRDC value
@@ -438,6 +448,7 @@ void omap_sram_idle(void)
                                               OMAP3430_GR_MOD,
                                               OMAP3_PRM_VOLTCTRL_OFFSET);
        }
+       omap3_intc_resume_idle();
 
        /* PER */
        if (per_next_state < PWRDM_POWER_ON) {
@@ -578,6 +589,8 @@ static int omap3_pm_suspend(void)
        }
 
        omap_uart_prepare_suspend();
+       omap3_intc_suspend();
+
        omap_sram_idle();
 
 restore:
@@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void)
                        CM_AUTOIDLE);
        }
 
+       omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
+
        /*
         * Set all plls to autoidle. This is needed until autoidle is
         * enabled by clockfw
@@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void)
        prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
                          OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
+       /* Enable PM_WKEN to support DSS LPR */
+       prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
+                               OMAP3430_DSS_MOD, PM_WKEN);
+
        /* Enable wakeups in PER */
        prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
                          OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
-                         OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
+                         OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
+                         OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
+                         OMAP3430_EN_MCBSP4,
                          OMAP3430_PER_MOD, PM_WKEN);
        /* and allow them to wake up MPU */
        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
                          OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
-                         OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
+                         OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
+                         OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
+                         OMAP3430_EN_MCBSP4,
                          OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
        /* Don't attach IVA interrupts */
@@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void)
        /* Clear any pending PRCM interrupts */
        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-       /* Don't attach IVA interrupts */
-       prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-       prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-       prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-       prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
-
-       /* Clear any pending 'reset' flags */
-       prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
-       prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
-       prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
-       prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
-       prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
-       prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
-       prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
-
-       /* Clear any pending PRCM interrupts */
-       prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-
        omap3_iva_idle();
        omap3_d2d_idle();
 }
index 3ea8177ffb2508be4a2b821ff09e05b0ac826bed..cf466ea1dffcb3f867921452b19fb2a4c6dd68c3 100644 (file)
@@ -44,7 +44,6 @@ struct omap3_prcm_regs {
        u32 iva2_cm_clksel2;
        u32 cm_sysconfig;
        u32 sgx_cm_clksel;
-       u32 wkup_cm_clksel;
        u32 dss_cm_clksel;
        u32 cam_cm_clksel;
        u32 per_cm_clksel;
@@ -53,7 +52,6 @@ struct omap3_prcm_regs {
        u32 pll_cm_autoidle2;
        u32 pll_cm_clksel4;
        u32 pll_cm_clksel5;
-       u32 pll_cm_clken;
        u32 pll_cm_clken2;
        u32 cm_polctrl;
        u32 iva2_cm_fclken;
@@ -77,7 +75,6 @@ struct omap3_prcm_regs {
        u32 usbhost_cm_iclken;
        u32 iva2_cm_autiidle2;
        u32 mpu_cm_autoidle2;
-       u32 pll_cm_autoidle;
        u32 iva2_cm_clkstctrl;
        u32 mpu_cm_clkstctrl;
        u32 core_cm_clkstctrl;
@@ -274,7 +271,6 @@ void omap3_prcm_save_context(void)
        prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
        prcm_context.sgx_cm_clksel =
                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
-       prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
        prcm_context.dss_cm_clksel =
                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
        prcm_context.cam_cm_clksel =
@@ -291,8 +287,6 @@ void omap3_prcm_save_context(void)
                        cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
        prcm_context.pll_cm_clksel5 =
                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
-       prcm_context.pll_cm_clken =
-                       cm_read_mod_reg(PLL_MOD, CM_CLKEN);
        prcm_context.pll_cm_clken2 =
                        cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
        prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
@@ -338,8 +332,6 @@ void omap3_prcm_save_context(void)
                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
        prcm_context.mpu_cm_autoidle2 =
                         cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
-       prcm_context.pll_cm_autoidle =
-                        cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
        prcm_context.iva2_cm_clkstctrl =
                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
        prcm_context.mpu_cm_clkstctrl =
@@ -431,7 +423,6 @@ void omap3_prcm_restore_context(void)
        __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
        cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
                                         CM_CLKSEL);
-       cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
        cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
                                         CM_CLKSEL);
        cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
@@ -448,7 +439,6 @@ void omap3_prcm_restore_context(void)
                                        OMAP3430ES2_CM_CLKSEL4);
        cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
                                         OMAP3430ES2_CM_CLKSEL5);
-       cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
        cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
                                        OMAP3430ES2_CM_CLKEN2);
        __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
@@ -487,7 +477,6 @@ void omap3_prcm_restore_context(void)
        cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
                                        CM_AUTOIDLE2);
        cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
-       cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
        cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
                                        CM_CLKSTCTRL);
        cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
index ea050ce188a7f9ea484649c489a480755e89b9da..40f006285163c95720a66bcd5f6893c1ccd570ef 100644 (file)
@@ -24,6 +24,8 @@
                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)                              \
                OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+#define OMAP44XX_CHIRONSS_REGADDR(module, reg)                         \
+               OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
 
 #include "prm44xx.h"
 
index 89be97f0589dd026b14629581c5dde7f911eea04..adb2558bb121740a0d0658a38c7c6eb020a50665 100644 (file)
 
 
 /* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
-#define OMAP4430_REVISION_PRCM                         OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
+#define OMAP4430_REVISION_PRCM                         OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
 
 /* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
-#define OMAP4430_CHIRON_PRCM_PRM_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
+#define OMAP4430_CHIRON_PRCM_PRM_RSTST                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
 
 /* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
-#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU0_PWRSTST                   OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
+#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU0_PWRSTST                   OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT              OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL              OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                        OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL              OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
 
 /* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
-#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU1_PWRSTST                   OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
+#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU1_PWRSTST                   OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT              OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL              OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                        OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL              OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
 #endif
index 15268f8b61de4c1958413be48add223834207f5d..c3626ea4814330fb64abbb0fdd5e91fd51d99d51 100644 (file)
@@ -245,7 +245,8 @@ restore:
        mov     r1, #0          @ set task id for ROM code in r1
        mov     r2, #4          @ set some flags in r2, r6
        mov     r6, #0xff
-       adr     r3, write_aux_control_params    @ r3 points to parameters
+       ldr     r4, scratchpad_base
+       ldr     r3, [r4, #0xBC] @ r3 points to parameters
        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
        .word   0xE1600071              @ call SMI monitor (smi #1)
@@ -253,14 +254,14 @@ restore:
        b       logic_l1_restore
 l2_inv_api_params:
        .word   0x1, 0x00
-write_aux_control_params:
-       .word   0x1, 0x72
 l2_inv_gp:
        /* Execute smi to invalidate L2 cache */
        mov r12, #0x1                         @ set up to invalide L2
 smi:    .word 0xE1600070               @ Call SMI monitor (smieq)
        /* Write to Aux control register to set some bits */
-       mov     r0, #0x72
+       ldr     r4, scratchpad_base
+       ldr     r3, [r4,#0xBC]
+       ldr     r0, [r3,#4]
        mov     r12, #0x3
        .word 0xE1600070        @ Call SMI monitor (smieq)
 logic_l1_restore:
@@ -271,6 +272,7 @@ logic_l1_restore:
 
        ldr     r4, scratchpad_base
        ldr     r3, [r4,#0xBC]
+       adds    r3, r3, #8
        ldmia   r3!, {r4-r6}
        mov     sp, r4
        msr     spsr_cxsf, r5
@@ -387,6 +389,9 @@ usettbr0:
 save_context_wfi:
        /*b     save_context_wfi*/      @ enable to debug save code
        mov     r8, r0 /* Store SDRAM address in r8 */
+       mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
+       mov     r4, #0x1                @ Number of parameters for restore call
+       stmia   r8!, {r4-r5}
         /* Check what that target sleep state is:stored in r1*/
         /* 1 - Only L1 and logic lost */
         /* 2 - Only L2 lost */
index cdd4b5378552a9a30d699046838d906b87ae4b47..7619456f2ae839bb100c6a41ea1069ee8dfa80f8 100644 (file)
@@ -82,7 +82,7 @@ static int hmt_bl_init(struct device *dev)
        return ret;
 }
 
-static int hmt_bl_notify(int brightness)
+static int hmt_bl_notify(struct device *dev, int brightness)
 {
        /*
         * translate from CIELUV/CIELAB L*->brightness, E.G. from
index bf1eaf3a27d452e915a83fb381ccc54490a4a88b..dddc0273bc8bc4157248c6677925bc3de3cc4446 100644 (file)
@@ -172,6 +172,32 @@ unsigned long long sched_clock(void)
                                  clocksource_32k.mult, clocksource_32k.shift);
 }
 
+/**
+ * read_persistent_clock -  Return time from a persistent clock.
+ *
+ * Reads the time from a source which isn't disabled during PM, the
+ * 32k sync timer.  Convert the cycles elapsed since last read into
+ * nsecs and adds to a monotonically increasing timespec.
+ */
+static struct timespec persistent_ts;
+static cycles_t cycles, last_cycles;
+void read_persistent_clock(struct timespec *ts)
+{
+       unsigned long long nsecs;
+       cycles_t delta;
+       struct timespec *tsp = &persistent_ts;
+
+       last_cycles = cycles;
+       cycles = clocksource_32k.read(&clocksource_32k);
+       delta = cycles - last_cycles;
+
+       nsecs = clocksource_cyc2ns(delta,
+                                  clocksource_32k.mult, clocksource_32k.shift);
+
+       timespec_add_ns(tsp, nsecs);
+       *ts = *tsp;
+}
+
 static int __init omap_init_clocksource_32k(void)
 {
        static char err[] __initdata = KERN_ERR
index 09d82b3c66ce3f2331e9581dadea3f804bf075fd..728c642041847a8e91c1c22294c4f338af8308dc 100644 (file)
@@ -1183,7 +1183,7 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
        }
 
        if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
-           (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
+           (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
                printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
                       "before unlinking\n");
                dump_stack();
index 64f407ee0f4e61394cf47673abb082f3300e2d74..08ccf89225202d512de9242e5ceab12457087309 100644 (file)
@@ -551,6 +551,19 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
        if (l & OMAP_TIMER_CTRL_ST) {
                l &= ~0x1;
                omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                       defined(CONFIG_ARCH_OMAP4)
+               /* Readback to make sure write has completed */
+               omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+                /*
+                 * Wait for functional clock period x 3.5 to make sure that
+                 * timer is stopped
+                 */
+               udelay(3500000 / clk_get_rate(timer->fclk) + 1);
+               /* Ack possibly pending interrupt */
+               omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+                               OMAP_TIMER_INT_OVERFLOW);
+#endif
        }
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
index 9a028bdebb06797166f2a3fff44e0aacd685740b..a162f585b1e3bdf0652088eb1929aea836857aa0 100644 (file)
@@ -434,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3430_REV_ES2_1     0x34302034
 #define OMAP3430_REV_ES3_0     0x34303034
 #define OMAP3430_REV_ES3_1     0x34304034
+#define OMAP3430_REV_ES3_1_2   0x34305034
 
 #define OMAP3630_REV_ES1_0     0x36300034
 
index 97d6c50c3dcb00b24d1d43551e6a4a3b8402621f..c0ab7c80f72e75b1ec113acbb5147806c7623369 100644 (file)
@@ -499,6 +499,9 @@ extern void omap_init_irq(void);
 extern int omap_irq_pending(void);
 void omap_intc_save_context(void);
 void omap_intc_restore_context(void);
+void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
 #endif
 
 #include <mach/hardware.h>
index 007935a921eaeaa4efd69ab1a0b53d757ad90587..33933256a2265815351307749768e73435d6cc01 100644 (file)
@@ -227,6 +227,7 @@ struct omap_hwmod_ocp_if {
 #define SYSC_HAS_SIDLEMODE     (1 << 5)
 #define SYSC_HAS_MIDLEMODE     (1 << 6)
 #define SYSS_MISSING           (1 << 7)
+#define SYSC_NO_CACHE          (1 << 8)  /* XXX SW flag, belongs elsewhere */
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH     0x0
index 07703f72330e1f0f468be6a0ce75d4b19a12daa8..6fb6e8aa389039a4258d4a2935817cf1c8428e3e 100644 (file)
@@ -53,7 +53,7 @@ config KVM_440
 
 config KVM_EXIT_TIMING
        bool "Detailed exit timing"
-       depends on KVM
+       depends on KVM_440 || KVM_E500
        ---help---
          Calculate elapsed time for every exit/enter cycle. A per-vcpu
          report is available in debugfs kvm/vm#_vcpu#_timing.
index 3f26131120b746c47c81e7d370d76a2422b46153..c2fb432f576a67c1c9789dfb0f6763d14d004e34 100644 (file)
@@ -1,14 +1,12 @@
 /*
- *  include/asm-s390/irqflags.h
- *
- *    Copyright (C) IBM Corp. 2006
- *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ *    Copyright IBM Corp. 2006,2010
+ *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
 
 #ifndef __ASM_IRQFLAGS_H
 #define __ASM_IRQFLAGS_H
 
-#ifdef __KERNEL__
+#include <linux/types.h>
 
 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
 
@@ -102,5 +100,4 @@ static inline int raw_irqs_disabled_flags(unsigned long flags)
 /* For spinlocks etc */
 #define raw_local_irq_save(x)  ((x) = raw_local_irq_disable())
 
-#endif /* __KERNEL__ */
 #endif /* __ASM_IRQFLAGS_H */
index 48215d15762b2d3d6a3be7eaf6fe509a45268567..e8ef21c51bbed02be140f797e24cec0e6c059fce 100644 (file)
@@ -571,6 +571,7 @@ pgm_svcper:
        mvc     __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
        oi      __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
        TRACE_IRQS_ON
+       lm      %r2,%r6,SP_R2(%r15)     # load svc arguments
        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
        b       BASED(sysc_do_svc)
 
index 9aff1d449b6e83c2be03275ad46cf6f3e3599a7c..f33658f09dd7ef97262ce6abc01d3d1833a461f4 100644 (file)
@@ -549,6 +549,7 @@ pgm_svcper:
        mvc     __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
        oi      __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
        TRACE_IRQS_ON
+       lmg     %r2,%r6,SP_R2(%r15)     # load svc arguments
        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
        j       sysc_do_svc
 
index 1675c48b9145289bb2adbd82a102ae3d76cb8376..6289945562b01d4278bea7286ded246eb13efe3c 100644 (file)
@@ -64,7 +64,7 @@ SYSCALL_DEFINE3(sigsuspend, int, history0, int, history1, old_sigset_t, mask)
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
 
-       current->state = TASK_INTERRUPTIBLE;
+       set_current_state(TASK_INTERRUPTIBLE);
        schedule();
        set_thread_flag(TIF_RESTORE_SIGMASK);
 
index ba9d8a7bc1ac93d6b41fff692ec4f3e3b2e30e9d..b40096494e469f6018146b517c54b7c5228ad7b1 100644 (file)
@@ -213,7 +213,7 @@ static int handle_instruction_and_prog(struct kvm_vcpu *vcpu)
        return rc2;
 }
 
-static const intercept_handler_t intercept_funcs[0x48 >> 2] = {
+static const intercept_handler_t intercept_funcs[] = {
        [0x00 >> 2] = handle_noop,
        [0x04 >> 2] = handle_instruction,
        [0x08 >> 2] = handle_prog,
@@ -230,7 +230,7 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu)
        intercept_handler_t func;
        u8 code = vcpu->arch.sie_block->icptcode;
 
-       if (code & 3 || code > 0x48)
+       if (code & 3 || (code >> 2) >= ARRAY_SIZE(intercept_funcs))
                return -ENOTSUPP;
        func = intercept_funcs[code >> 2];
        if (func)
index 108197ac0d56eda5d0effb398560629f6a276352..4097f6a10860c764bb2b4981bc32bef506c9ef28 100644 (file)
@@ -64,8 +64,11 @@ config BITS
        default 64 if SPARC64
 
 config GENERIC_TIME
+       def_bool y
+
+config ARCH_USES_GETTIMEOFFSET
        bool
-       default y if SPARC64
+       default y if SPARC32
 
 config GENERIC_CMOS_UPDATE
        bool
index 983d59824a286d0cba34fa48ce078c7ab70eaa04..99a1f191497be29ce8e1cae10b5db72272551214 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31
-# Wed Sep 16 00:03:43 2009
+# Linux kernel version: 2.6.33-rc2
+# Mon Jan 11 23:20:31 2010
 #
 # CONFIG_64BIT is not set
 CONFIG_SPARC=y
@@ -41,6 +41,7 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y
 #
 CONFIG_TREE_RCU=y
 # CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
 # CONFIG_RCU_TRACE is not set
 CONFIG_RCU_FANOUT=32
 # CONFIG_RCU_FANOUT_EXACT is not set
@@ -88,21 +89,21 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
-CONFIG_HAVE_PERF_COUNTERS=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
 # CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_DMA_ATTRS=y
@@ -131,14 +132,41 @@ CONFIG_LBDAF=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -168,8 +196,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_SUN_PM=y
 # CONFIG_SPARC_LED is not set
@@ -257,6 +284,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m
 CONFIG_INET6_XFRM_MODE_BEET=m
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
 CONFIG_IPV6_NDISC_NODETYPE=y
 CONFIG_IPV6_TUNNEL=m
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
@@ -295,9 +323,6 @@ CONFIG_NET_PKTGEN=m
 # CONFIG_AF_RXRPC is not set
 CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
-CONFIG_WIRELESS_OLD_REGULATORY=y
-# CONFIG_WIRELESS_EXT is not set
 # CONFIG_LIB80211 is not set
 
 #
@@ -335,6 +360,10 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 CONFIG_BLK_DEV_RAM=y
@@ -398,8 +427,11 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_CXGB3_ISCSI is not set
 # CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
 # CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
 # CONFIG_SCSI_ACARD is not set
 # CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
@@ -434,7 +466,9 @@ CONFIG_SCSI_QLOGICPTI=m
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_SCSI_SUNESP=y
 # CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
 # CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
@@ -450,7 +484,7 @@ CONFIG_SCSI_SUNESP=y
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -487,6 +521,7 @@ CONFIG_SUNQE=m
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
@@ -546,6 +581,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
@@ -555,6 +591,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -574,6 +611,7 @@ CONFIG_INPUT_KEYBOARD=y
 CONFIG_KEYBOARD_ATKBD=m
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_KEYBOARD_SUNKBD=m
 # CONFIG_KEYBOARD_XTKBD is not set
@@ -604,6 +642,7 @@ CONFIG_SERIO_SERPORT=m
 # CONFIG_SERIO_PCIPS2 is not set
 CONFIG_SERIO_LIBPS2=m
 # CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -636,6 +675,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_CONSOLE_POLL=y
 # CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -661,6 +701,11 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
 # CONFIG_SENSORS_I5K_AMB is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
@@ -675,9 +720,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_VT8231 is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -699,6 +742,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Graphics support
 #
+CONFIG_VGA_ARB=y
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
@@ -776,7 +820,9 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T35 is not set
 CONFIG_RTC_DRV_M48T59=y
+# CONFIG_RTC_DRV_MSM6242 is not set
 # CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
@@ -955,6 +1001,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
@@ -1003,9 +1050,9 @@ CONFIG_KGDB=y
 CONFIG_KGDB_SERIAL_CONSOLE=y
 CONFIG_KGDB_TESTS=y
 # CONFIG_KGDB_TESTS_ON_BOOT is not set
-# CONFIG_KMEMCHECK is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_STACK_DEBUG is not set
+# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
 
 #
 # Security options
@@ -1013,7 +1060,11 @@ CONFIG_KGDB_TESTS=y
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
 
 #
index f80b881dfea77be89459b343c71fdeaa61a1ad68..41c5a56aa6f28b5a20c6c9e25215dafde9b3099b 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31
-# Tue Sep 15 17:06:03 2009
+# Linux kernel version: 2.6.33-rc2
+# Wed Jan 20 16:31:47 2010
 #
 CONFIG_64BIT=y
 CONFIG_SPARC=y
@@ -20,6 +20,7 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 CONFIG_AUDIT_ARCH=y
 CONFIG_HAVE_SETUP_PER_CPU_AREA=y
 CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_MMU=y
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
@@ -50,6 +51,7 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y
 #
 CONFIG_TREE_RCU=y
 # CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
 # CONFIG_RCU_TRACE is not set
 CONFIG_RCU_FANOUT=64
 # CONFIG_RCU_FANOUT_EXACT is not set
@@ -62,8 +64,7 @@ CONFIG_RT_GROUP_SCHED=y
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 CONFIG_RELAY=y
 CONFIG_NAMESPACES=y
 # CONFIG_UTS_NS is not set
@@ -97,24 +98,25 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
-CONFIG_HAVE_PERF_COUNTERS=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 CONFIG_EVENT_PROFILE=y
+CONFIG_PERF_COUNTERS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
-# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
 CONFIG_TRACEPOINTS=y
-CONFIG_MARKERS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
@@ -152,14 +154,41 @@ CONFIG_BLOCK_COMPAT=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
 # CONFIG_FREEZER is not set
 
 #
@@ -179,6 +208,7 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_MAY_HAVE_PC_FDC=y
 CONFIG_SPARC64_SMP=y
+CONFIG_EARLYFB=y
 CONFIG_SPARC64_PAGE_SIZE_8KB=y
 # CONFIG_SPARC64_PAGE_SIZE_64KB is not set
 CONFIG_SECCOMP=y
@@ -216,8 +246,7 @@ CONFIG_MIGRATION=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_NR_QUICK=1
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=8192
 CONFIG_SCHED_SMT=y
 CONFIG_SCHED_MC=y
@@ -315,6 +344,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m
 CONFIG_INET6_XFRM_MODE_BEET=m
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
 CONFIG_IPV6_NDISC_NODETYPE=y
 CONFIG_IPV6_TUNNEL=m
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
@@ -356,9 +386,6 @@ CONFIG_NET_TCPPROBE=m
 # CONFIG_AF_RXRPC is not set
 CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
-CONFIG_WIRELESS_OLD_REGULATORY=y
-# CONFIG_WIRELESS_EXT is not set
 # CONFIG_LIB80211 is not set
 
 #
@@ -376,6 +403,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_FW_LOADER=y
@@ -397,6 +425,11 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_DRBD is not set
 CONFIG_BLK_DEV_NBD=m
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
@@ -408,6 +441,7 @@ CONFIG_ATA_OVER_ETH=m
 CONFIG_SUNVDC=m
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
 # CONFIG_PHANTOM is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
@@ -415,6 +449,7 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_HP_ILO is not set
 # CONFIG_ISL29003 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_C2PORT is not set
 
 #
@@ -522,8 +557,11 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_CXGB3_ISCSI is not set
 # CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
 # CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
 # CONFIG_SCSI_ACARD is not set
 # CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
@@ -557,7 +595,9 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SUNESP is not set
 # CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
 # CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
@@ -568,7 +608,9 @@ CONFIG_MD_RAID0=m
 CONFIG_MD_RAID1=m
 CONFIG_MD_RAID10=m
 CONFIG_MD_RAID456=m
+# CONFIG_MULTICORE_RAID456 is not set
 CONFIG_MD_RAID6_PQ=m
+# CONFIG_ASYNC_RAID6_TEST is not set
 CONFIG_MD_MULTIPATH=m
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
@@ -592,7 +634,7 @@ CONFIG_DM_ZERO=m
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -664,6 +706,7 @@ CONFIG_NET_PCI=y
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
 # CONFIG_ATL2 is not set
@@ -745,6 +788,7 @@ CONFIG_SLHC=m
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
@@ -754,6 +798,7 @@ CONFIG_SLHC=m
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -770,9 +815,13 @@ CONFIG_INPUT_EVDEV=y
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
 CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_QT2160 is not set
 CONFIG_KEYBOARD_LKKBD=m
+# CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_KEYBOARD_SUNKBD=y
 # CONFIG_KEYBOARD_XTKBD is not set
@@ -812,6 +861,7 @@ CONFIG_SERIO_I8042=y
 CONFIG_SERIO_PCIPS2=m
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
+# CONFIG_SERIO_ALTERA_PS2 is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -844,6 +894,7 @@ CONFIG_SERIAL_SUNHV=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -858,6 +909,7 @@ CONFIG_HW_RANDOM_N2RNG=m
 CONFIG_DEVPORT=y
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
 # CONFIG_I2C_CHARDEV is not set
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=y
@@ -897,11 +949,6 @@ CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_TINY_USB is not set
 
-#
-# Graphics adapter I2C/DDC channel drivers
-#
-# CONFIG_I2C_VOODOO3 is not set
-
 #
 # Other I2C/SMBus bus drivers
 #
@@ -911,10 +958,6 @@ CONFIG_I2C_ALGOBIT=y
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -932,6 +975,11 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
 # CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
@@ -955,6 +1003,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM73 is not set
 # CONFIG_SENSORS_LM75 is not set
 # CONFIG_SENSORS_LM77 is not set
 # CONFIG_SENSORS_LM78 is not set
@@ -981,6 +1030,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_VT8231 is not set
@@ -993,9 +1043,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_SENSORS_ULTRA45 is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -1013,16 +1062,20 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
+# CONFIG_MFD_88PM8607 is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+CONFIG_VGA_ARB=y
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -1176,6 +1229,7 @@ CONFIG_SND_ALI5451=m
 # CONFIG_SND_OXYGEN is not set
 # CONFIG_SND_CS4281 is not set
 # CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
 # CONFIG_SND_CTXFI is not set
 # CONFIG_SND_DARLA20 is not set
 # CONFIG_SND_GINA20 is not set
@@ -1311,6 +1365,7 @@ CONFIG_USB_EHCI_HCD=m
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1426,6 +1481,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
@@ -1447,7 +1503,9 @@ CONFIG_RTC_DRV_CMOS=y
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T35 is not set
 CONFIG_RTC_DRV_M48T59=y
+# CONFIG_RTC_DRV_MSM6242 is not set
 CONFIG_RTC_DRV_BQ4802=y
+# CONFIG_RTC_DRV_RP5C01 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
@@ -1625,6 +1683,7 @@ CONFIG_PRINTK_TIME=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=2048
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1678,9 +1737,11 @@ CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
 CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
 CONFIG_TRACING=y
 CONFIG_GENERIC_TRACER=y
 CONFIG_TRACING_SUPPORT=y
@@ -1688,6 +1749,7 @@ CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
+# CONFIG_FTRACE_SYSCALLS is not set
 # CONFIG_BOOT_TRACER is not set
 CONFIG_BRANCH_PROFILE_NONE=y
 # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
@@ -1706,6 +1768,7 @@ CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_DEBUG_DCFLUSH is not set
 # CONFIG_STACK_DEBUG is not set
+# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
 
 #
 # Security options
@@ -1714,11 +1777,17 @@ CONFIG_KEYS=y
 # CONFIG_KEYS_DEBUG_PROC_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_XOR_BLOCKS=m
 CONFIG_ASYNC_CORE=m
 CONFIG_ASYNC_MEMCPY=m
 CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
 CONFIG_CRYPTO=y
 
 #
index 93fe21e02c86b0c7607f06c813532223220a68cf..679c7504625acc86deab57d1e1feada4ef408317 100644 (file)
@@ -8,7 +8,7 @@
 #include <asm/page.h>      /* IO address mapping routines need this */
 #include <asm/system.h>
 
-#define page_to_phys(page)     (((page) - mem_map) << PAGE_SHIFT)
+#define page_to_phys(page)     (page_to_pfn(page) << PAGE_SHIFT)
 
 static inline u32 flip_dword (u32 l)
 {
index f72080bdda947ec81edce5206842d836755f4521..156707b0f18d1ba4a5fbd01fc972fbec8c529c0d 100644 (file)
@@ -143,7 +143,7 @@ extern unsigned long pfn_base;
 #define phys_to_virt           __va
 
 #define ARCH_PFN_OFFSET                (pfn_base)
-#define virt_to_page(kaddr)    (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT)))
+#define virt_to_page(kaddr)    pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 
 #define pfn_valid(pfn)         (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
 #define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
index 9836d9a3cb9abd31b17ac51a5da51209ea72fa5d..0bc356bf8c505d1087d1668de130b30ef1234d40 100644 (file)
@@ -1,22 +1,7 @@
 #ifndef _ASMSPARC_PARAM_H
 #define _ASMSPARC_PARAM_H
 
-#ifdef __KERNEL__
-# define HZ            CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ       100     /* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
 #define EXEC_PAGESIZE  8192    /* Thanks for sun4's we carry baggage... */
+#include <asm-generic/param.h>
 
-#ifndef NOGROUP
-#define NOGROUP                (-1)
-#endif
-
-#define MAXHOSTNAMELEN 64      /* max length of hostname */
-
-#endif
+#endif /* _ASMSPARC_PARAM_H */
index b6ccdb0d6f7de3fb23b8691c036be8acaa62e91f..a254750e4c03715c57389a4767928af18feb0593 100644 (file)
@@ -12,4 +12,5 @@
 typedef unsigned long cycles_t;
 #define get_cycles()   (0)
 
+extern u32 (*do_arch_gettimeoffset)(void);
 #endif
index 600a79035fa1066038861b0f435e9a44f8c4e49d..1c79f32734a05694a5297c7034ff0e6b93fe83f6 100644 (file)
@@ -12,7 +12,9 @@ static inline int cpu_to_node(int cpu)
 
 #define parent_node(node)      (node)
 
-#define cpumask_of_node(node) (&numa_cpumask_lookup_table[node])
+#define cpumask_of_node(node) ((node) == -1 ?                          \
+                              cpu_all_mask :                           \
+                              &numa_cpumask_lookup_table[node])
 
 struct pci_bus;
 #ifdef CONFIG_PCI
index 489d2ba92bcb504e3d6243e36cef99bddf08e4c3..25f1d10155e8a3d6c0a9de590d9e14b2664508ba 100644 (file)
@@ -274,7 +274,7 @@ static inline unsigned long copy_from_user(void *to, const void __user *from, un
 
        if (unlikely(sz != -1 && sz < n)) {
                copy_from_user_overflow();
-               return -EFAULT;
+               return n;
        }
 
        if (n && __access_ok((unsigned long) from, n))
index dbc141660994915c23c059b844772ae855681bdc..2406788bfe5f6b1a65c90dde46029ffbeb065807 100644 (file)
@@ -221,8 +221,8 @@ extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
 static inline unsigned long __must_check
 copy_from_user(void *to, const void __user *from, unsigned long size)
 {
-       unsigned long ret = (unsigned long) -EFAULT;
        int sz = __compiletime_object_size(to);
+       unsigned long ret = size;
 
        if (likely(sz == -1 || sz >= size)) {
                ret = ___copy_from_user(to, from, size);
index f3b5466c389cc5fe1a4e44decf12b3e1a65bae9c..4589ca33220ff6463dbd7191259d01debb5fb13f 100644 (file)
@@ -99,7 +99,7 @@ static int __devinit clock_board_probe(struct of_device *op,
 
        p->leds_resource.start = (unsigned long)
                (p->clock_regs + CLOCK_CTRL);
-       p->leds_resource.end = p->leds_resource.end;
+       p->leds_resource.end = p->leds_resource.start;
        p->leds_resource.name = "leds";
 
        p->leds_pdev.name = "sunfire-clockboard-leds";
@@ -194,7 +194,7 @@ static int __devinit fhc_probe(struct of_device *op,
        if (!p->central) {
                p->leds_resource.start = (unsigned long)
                        (p->pregs + FHC_PREGS_CTRL);
-               p->leds_resource.end = p->leds_resource.end;
+               p->leds_resource.end = p->leds_resource.start;
                p->leds_resource.name = "leds";
 
                p->leds_pdev.name = "sunfire-fhc-leds";
index 8d6882bb480a7b9aea91eabc7aee588db563055f..e1cbdb94d97bc10030e7ac5add8f1b22a54cc47e 100644 (file)
@@ -250,12 +250,12 @@ struct irq_handler_data {
 };
 
 #ifdef CONFIG_SMP
-static int irq_choose_cpu(unsigned int virt_irq)
+static int irq_choose_cpu(unsigned int virt_irq, const struct cpumask *affinity)
 {
        cpumask_t mask;
        int cpuid;
 
-       cpumask_copy(&mask, irq_desc[virt_irq].affinity);
+       cpumask_copy(&mask, affinity);
        if (cpus_equal(mask, cpu_online_map)) {
                cpuid = map_to_cpu(virt_irq);
        } else {
@@ -268,10 +268,8 @@ static int irq_choose_cpu(unsigned int virt_irq)
        return cpuid;
 }
 #else
-static int irq_choose_cpu(unsigned int virt_irq)
-{
-       return real_hard_smp_processor_id();
-}
+#define irq_choose_cpu(virt_irq, affinity)     \
+       real_hard_smp_processor_id()
 #endif
 
 static void sun4u_irq_enable(unsigned int virt_irq)
@@ -282,7 +280,8 @@ static void sun4u_irq_enable(unsigned int virt_irq)
                unsigned long cpuid, imap, val;
                unsigned int tid;
 
-               cpuid = irq_choose_cpu(virt_irq);
+               cpuid = irq_choose_cpu(virt_irq,
+                                      irq_desc[virt_irq].affinity);
                imap = data->imap;
 
                tid = sun4u_compute_tid(imap, cpuid);
@@ -299,7 +298,24 @@ static void sun4u_irq_enable(unsigned int virt_irq)
 static int sun4u_set_affinity(unsigned int virt_irq,
                               const struct cpumask *mask)
 {
-       sun4u_irq_enable(virt_irq);
+       struct irq_handler_data *data = get_irq_chip_data(virt_irq);
+
+       if (likely(data)) {
+               unsigned long cpuid, imap, val;
+               unsigned int tid;
+
+               cpuid = irq_choose_cpu(virt_irq, mask);
+               imap = data->imap;
+
+               tid = sun4u_compute_tid(imap, cpuid);
+
+               val = upa_readq(imap);
+               val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
+                        IMAP_AID_SAFARI | IMAP_NID_SAFARI);
+               val |= tid | IMAP_VALID;
+               upa_writeq(val, imap);
+               upa_writeq(ICLR_IDLE, data->iclr);
+       }
 
        return 0;
 }
@@ -340,7 +356,8 @@ static void sun4u_irq_eoi(unsigned int virt_irq)
 static void sun4v_irq_enable(unsigned int virt_irq)
 {
        unsigned int ino = virt_irq_table[virt_irq].dev_ino;
-       unsigned long cpuid = irq_choose_cpu(virt_irq);
+       unsigned long cpuid = irq_choose_cpu(virt_irq,
+                                            irq_desc[virt_irq].affinity);
        int err;
 
        err = sun4v_intr_settarget(ino, cpuid);
@@ -361,7 +378,7 @@ static int sun4v_set_affinity(unsigned int virt_irq,
                               const struct cpumask *mask)
 {
        unsigned int ino = virt_irq_table[virt_irq].dev_ino;
-       unsigned long cpuid = irq_choose_cpu(virt_irq);
+       unsigned long cpuid = irq_choose_cpu(virt_irq, mask);
        int err;
 
        err = sun4v_intr_settarget(ino, cpuid);
@@ -403,7 +420,7 @@ static void sun4v_virq_enable(unsigned int virt_irq)
        unsigned long cpuid, dev_handle, dev_ino;
        int err;
 
-       cpuid = irq_choose_cpu(virt_irq);
+       cpuid = irq_choose_cpu(virt_irq, irq_desc[virt_irq].affinity);
 
        dev_handle = virt_irq_table[virt_irq].dev_handle;
        dev_ino = virt_irq_table[virt_irq].dev_ino;
@@ -433,7 +450,7 @@ static int sun4v_virt_set_affinity(unsigned int virt_irq,
        unsigned long cpuid, dev_handle, dev_ino;
        int err;
 
-       cpuid = irq_choose_cpu(virt_irq);
+       cpuid = irq_choose_cpu(virt_irq, mask);
 
        dev_handle = virt_irq_table[virt_irq].dev_handle;
        dev_ino = virt_irq_table[virt_irq].dev_ino;
index 85e7037429b97cac7a9d5eedebe80bab00eb5eee..4e2724ec2bb6d6c3e660cf06feb7c62b1953fed1 100644 (file)
@@ -30,6 +30,7 @@
 #include <asm/oplib.h>
 #include <asm/prom.h>
 #include <asm/pcic.h>
+#include <asm/timex.h>
 #include <asm/timer.h>
 #include <asm/uaccess.h>
 #include <asm/irq_regs.h>
@@ -163,8 +164,6 @@ void __iomem *pcic_regs;
 volatile int pcic_speculative;
 volatile int pcic_trapped;
 
-static void pci_do_gettimeofday(struct timeval *tv);
-static int pci_do_settimeofday(struct timespec *tv);
 
 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
 
@@ -716,19 +715,27 @@ static irqreturn_t pcic_timer_handler (int irq, void *h)
 #define USECS_PER_JIFFY  10000  /* We have 100HZ "standard" timer for sparc */
 #define TICK_TIMER_LIMIT ((100*1000000/4)/100)
 
+u32 pci_gettimeoffset(void)
+{
+       /*
+        * We divide all by 100
+        * to have microsecond resolution and to avoid overflow
+        */
+       unsigned long count =
+           readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;
+       count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100);
+       return count * 1000;
+}
+
+
 void __init pci_time_init(void)
 {
        struct linux_pcic *pcic = &pcic0;
        unsigned long v;
        int timer_irq, irq;
 
-       /* A hack until do_gettimeofday prototype is moved to arch specific headers
-          and btfixupped. Patch do_gettimeofday with ba pci_do_gettimeofday; nop */
-       ((unsigned int *)do_gettimeofday)[0] = 
-           0x10800000 | ((((unsigned long)pci_do_gettimeofday -
-            (unsigned long)do_gettimeofday) >> 2) & 0x003fffff);
-       ((unsigned int *)do_gettimeofday)[1] = 0x01000000;
-       BTFIXUPSET_CALL(bus_do_settimeofday, pci_do_settimeofday, BTFIXUPCALL_NORM);
+       do_arch_gettimeoffset = pci_gettimeoffset;
+
        btfixup();
 
        writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
@@ -746,84 +753,6 @@ void __init pci_time_init(void)
        local_irq_enable();
 }
 
-static inline unsigned long do_gettimeoffset(void)
-{
-       /*
-        * We divide all by 100
-        * to have microsecond resolution and to avoid overflow
-        */
-       unsigned long count =
-           readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;
-       count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100);
-       return count;
-}
-
-static void pci_do_gettimeofday(struct timeval *tv)
-{
-       unsigned long flags;
-       unsigned long seq;
-       unsigned long usec, sec;
-       unsigned long max_ntp_tick = tick_usec - tickadj;
-
-       do {
-               seq = read_seqbegin_irqsave(&xtime_lock, flags);
-               usec = do_gettimeoffset();
-
-               /*
-                * If time_adjust is negative then NTP is slowing the clock
-                * so make sure not to go into next possible interval.
-                * Better to lose some accuracy than have time go backwards..
-                */
-               if (unlikely(time_adjust < 0))
-                       usec = min(usec, max_ntp_tick);
-
-               sec = xtime.tv_sec;
-               usec += (xtime.tv_nsec / 1000);
-       } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
-
-       while (usec >= 1000000) {
-               usec -= 1000000;
-               sec++;
-       }
-
-       tv->tv_sec = sec;
-       tv->tv_usec = usec;
-}
-
-static int pci_do_settimeofday(struct timespec *tv)
-{
-       if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
-               return -EINVAL;
-
-       /*
-        * This is revolting. We need to set "xtime" correctly. However, the
-        * value in this location is the value at the most recent update of
-        * wall time.  Discover what correction gettimeofday() would have
-        * made, and then undo it!
-        */
-       tv->tv_nsec -= 1000 * do_gettimeoffset();
-       while (tv->tv_nsec < 0) {
-               tv->tv_nsec += NSEC_PER_SEC;
-               tv->tv_sec--;
-       }
-
-       wall_to_monotonic.tv_sec += xtime.tv_sec - tv->tv_sec;
-       wall_to_monotonic.tv_nsec += xtime.tv_nsec - tv->tv_nsec;
-
-       if (wall_to_monotonic.tv_nsec > NSEC_PER_SEC) {
-               wall_to_monotonic.tv_nsec -= NSEC_PER_SEC;
-               wall_to_monotonic.tv_sec++;
-       }
-       if (wall_to_monotonic.tv_nsec < 0) {
-               wall_to_monotonic.tv_nsec += NSEC_PER_SEC;
-               wall_to_monotonic.tv_sec--;
-       }
-
-       xtime.tv_sec = tv->tv_sec;
-       xtime.tv_nsec = tv->tv_nsec;
-       ntp_clear();
-       return 0;
-}
 
 #if 0
 static void watchdog_reset() {
index 198fb4e79ba2875289a58cae60acb47c3442fb23..e856456ec02fcc172ebeb57a01bf675f477e5006 100644 (file)
@@ -1,6 +1,6 @@
 /* Performance event support for sparc64.
  *
- * Copyright (C) 2009 David S. Miller <davem@davemloft.net>
+ * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
  *
  * This code is based almost entirely upon the x86 perf event
  * code, which is:
 #include <linux/kdebug.h>
 #include <linux/mutex.h>
 
+#include <asm/stacktrace.h>
 #include <asm/cpudata.h>
+#include <asm/uaccess.h>
 #include <asm/atomic.h>
 #include <asm/nmi.h>
 #include <asm/pcr.h>
 
+#include "kstack.h"
+
 /* Sparc64 chips have two performance counters, 32-bits each, with
  * overflow interrupts generated on transition from 0xffffffff to 0.
  * The counters are accessed in one go using a 64-bit register.
 
 #define PIC_UPPER_INDEX                        0
 #define PIC_LOWER_INDEX                        1
+#define PIC_NO_INDEX                   -1
 
 struct cpu_hw_events {
-       struct perf_event       *events[MAX_HWEVENTS];
-       unsigned long           used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-       unsigned long           active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
+       /* Number of events currently scheduled onto this cpu.
+        * This tells how many entries in the arrays below
+        * are valid.
+        */
+       int                     n_events;
+
+       /* Number of new events added since the last hw_perf_disable().
+        * This works because the perf event layer always adds new
+        * events inside of a perf_{disable,enable}() sequence.
+        */
+       int                     n_added;
+
+       /* Array of events current scheduled on this cpu.  */
+       struct perf_event       *event[MAX_HWEVENTS];
+
+       /* Array of encoded longs, specifying the %pcr register
+        * encoding and the mask of PIC counters this even can
+        * be scheduled on.  See perf_event_encode() et al.
+        */
+       unsigned long           events[MAX_HWEVENTS];
+
+       /* The current counter index assigned to an event.  When the
+        * event hasn't been programmed into the cpu yet, this will
+        * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
+        * we ought to schedule the event.
+        */
+       int                     current_idx[MAX_HWEVENTS];
+
+       /* Software copy of %pcr register on this cpu.  */
        u64                     pcr;
+
+       /* Enabled/disable state.  */
        int                     enabled;
 };
 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
 
+/* An event map describes the characteristics of a performance
+ * counter event.  In particular it gives the encoding as well as
+ * a mask telling which counters the event can be measured on.
+ */
 struct perf_event_map {
        u16     encoding;
        u8      pic_mask;
@@ -69,15 +106,20 @@ struct perf_event_map {
 #define PIC_LOWER      0x02
 };
 
+/* Encode a perf_event_map entry into a long.  */
 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
 {
        return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
 }
 
-static void perf_event_decode(unsigned long val, u16 *enc, u8 *msk)
+static u8 perf_event_get_msk(unsigned long val)
 {
-       *msk = val & 0xff;
-       *enc = val >> 16;
+       return val & 0xff;
+}
+
+static u64 perf_event_get_enc(unsigned long val)
+{
+       return val >> 16;
 }
 
 #define C(x) PERF_COUNT_HW_CACHE_##x
@@ -491,53 +533,6 @@ static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw
        pcr_ops->write(cpuc->pcr);
 }
 
-void hw_perf_enable(void)
-{
-       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-       u64 val;
-       int i;
-
-       if (cpuc->enabled)
-               return;
-
-       cpuc->enabled = 1;
-       barrier();
-
-       val = cpuc->pcr;
-
-       for (i = 0; i < MAX_HWEVENTS; i++) {
-               struct perf_event *cp = cpuc->events[i];
-               struct hw_perf_event *hwc;
-
-               if (!cp)
-                       continue;
-               hwc = &cp->hw;
-               val |= hwc->config_base;
-       }
-
-       cpuc->pcr = val;
-
-       pcr_ops->write(cpuc->pcr);
-}
-
-void hw_perf_disable(void)
-{
-       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-       u64 val;
-
-       if (!cpuc->enabled)
-               return;
-
-       cpuc->enabled = 0;
-
-       val = cpuc->pcr;
-       val &= ~(PCR_UTRACE | PCR_STRACE |
-                sparc_pmu->hv_bit | sparc_pmu->irq_bit);
-       cpuc->pcr = val;
-
-       pcr_ops->write(cpuc->pcr);
-}
-
 static u32 read_pmc(int idx)
 {
        u64 val;
@@ -566,6 +561,30 @@ static void write_pmc(int idx, u64 val)
        write_pic(pic);
 }
 
+static u64 sparc_perf_event_update(struct perf_event *event,
+                                  struct hw_perf_event *hwc, int idx)
+{
+       int shift = 64 - 32;
+       u64 prev_raw_count, new_raw_count;
+       s64 delta;
+
+again:
+       prev_raw_count = atomic64_read(&hwc->prev_count);
+       new_raw_count = read_pmc(idx);
+
+       if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                            new_raw_count) != prev_raw_count)
+               goto again;
+
+       delta = (new_raw_count << shift) - (prev_raw_count << shift);
+       delta >>= shift;
+
+       atomic64_add(delta, &event->count);
+       atomic64_sub(delta, &hwc->period_left);
+
+       return new_raw_count;
+}
+
 static int sparc_perf_event_set_period(struct perf_event *event,
                                       struct hw_perf_event *hwc, int idx)
 {
@@ -598,81 +617,166 @@ static int sparc_perf_event_set_period(struct perf_event *event,
        return ret;
 }
 
-static int sparc_pmu_enable(struct perf_event *event)
+/* If performance event entries have been added, move existing
+ * events around (if necessary) and then assign new entries to
+ * counters.
+ */
+static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
 {
-       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-       struct hw_perf_event *hwc = &event->hw;
-       int idx = hwc->idx;
+       int i;
 
-       if (test_and_set_bit(idx, cpuc->used_mask))
-               return -EAGAIN;
+       if (!cpuc->n_added)
+               goto out;
 
-       sparc_pmu_disable_event(cpuc, hwc, idx);
+       /* Read in the counters which are moving.  */
+       for (i = 0; i < cpuc->n_events; i++) {
+               struct perf_event *cp = cpuc->event[i];
 
-       cpuc->events[idx] = event;
-       set_bit(idx, cpuc->active_mask);
+               if (cpuc->current_idx[i] != PIC_NO_INDEX &&
+                   cpuc->current_idx[i] != cp->hw.idx) {
+                       sparc_perf_event_update(cp, &cp->hw,
+                                               cpuc->current_idx[i]);
+                       cpuc->current_idx[i] = PIC_NO_INDEX;
+               }
+       }
 
-       sparc_perf_event_set_period(event, hwc, idx);
-       sparc_pmu_enable_event(cpuc, hwc, idx);
-       perf_event_update_userpage(event);
-       return 0;
+       /* Assign to counters all unassigned events.  */
+       for (i = 0; i < cpuc->n_events; i++) {
+               struct perf_event *cp = cpuc->event[i];
+               struct hw_perf_event *hwc = &cp->hw;
+               int idx = hwc->idx;
+               u64 enc;
+
+               if (cpuc->current_idx[i] != PIC_NO_INDEX)
+                       continue;
+
+               sparc_perf_event_set_period(cp, hwc, idx);
+               cpuc->current_idx[i] = idx;
+
+               enc = perf_event_get_enc(cpuc->events[i]);
+               pcr |= event_encoding(enc, idx);
+       }
+out:
+       return pcr;
 }
 
-static u64 sparc_perf_event_update(struct perf_event *event,
-                                  struct hw_perf_event *hwc, int idx)
+void hw_perf_enable(void)
 {
-       int shift = 64 - 32;
-       u64 prev_raw_count, new_raw_count;
-       s64 delta;
+       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       u64 pcr;
 
-again:
-       prev_raw_count = atomic64_read(&hwc->prev_count);
-       new_raw_count = read_pmc(idx);
+       if (cpuc->enabled)
+               return;
 
-       if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
-                            new_raw_count) != prev_raw_count)
-               goto again;
+       cpuc->enabled = 1;
+       barrier();
 
-       delta = (new_raw_count << shift) - (prev_raw_count << shift);
-       delta >>= shift;
+       pcr = cpuc->pcr;
+       if (!cpuc->n_events) {
+               pcr = 0;
+       } else {
+               pcr = maybe_change_configuration(cpuc, pcr);
 
-       atomic64_add(delta, &event->count);
-       atomic64_sub(delta, &hwc->period_left);
+               /* We require that all of the events have the same
+                * configuration, so just fetch the settings from the
+                * first entry.
+                */
+               cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
+       }
 
-       return new_raw_count;
+       pcr_ops->write(cpuc->pcr);
+}
+
+void hw_perf_disable(void)
+{
+       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       u64 val;
+
+       if (!cpuc->enabled)
+               return;
+
+       cpuc->enabled = 0;
+       cpuc->n_added = 0;
+
+       val = cpuc->pcr;
+       val &= ~(PCR_UTRACE | PCR_STRACE |
+                sparc_pmu->hv_bit | sparc_pmu->irq_bit);
+       cpuc->pcr = val;
+
+       pcr_ops->write(cpuc->pcr);
 }
 
 static void sparc_pmu_disable(struct perf_event *event)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        struct hw_perf_event *hwc = &event->hw;
-       int idx = hwc->idx;
+       unsigned long flags;
+       int i;
 
-       clear_bit(idx, cpuc->active_mask);
-       sparc_pmu_disable_event(cpuc, hwc, idx);
+       local_irq_save(flags);
+       perf_disable();
+
+       for (i = 0; i < cpuc->n_events; i++) {
+               if (event == cpuc->event[i]) {
+                       int idx = cpuc->current_idx[i];
+
+                       /* Shift remaining entries down into
+                        * the existing slot.
+                        */
+                       while (++i < cpuc->n_events) {
+                               cpuc->event[i - 1] = cpuc->event[i];
+                               cpuc->events[i - 1] = cpuc->events[i];
+                               cpuc->current_idx[i - 1] =
+                                       cpuc->current_idx[i];
+                       }
+
+                       /* Absorb the final count and turn off the
+                        * event.
+                        */
+                       sparc_pmu_disable_event(cpuc, hwc, idx);
+                       barrier();
+                       sparc_perf_event_update(event, hwc, idx);
 
-       barrier();
+                       perf_event_update_userpage(event);
 
-       sparc_perf_event_update(event, hwc, idx);
-       cpuc->events[idx] = NULL;
-       clear_bit(idx, cpuc->used_mask);
+                       cpuc->n_events--;
+                       break;
+               }
+       }
 
-       perf_event_update_userpage(event);
+       perf_enable();
+       local_irq_restore(flags);
+}
+
+static int active_event_index(struct cpu_hw_events *cpuc,
+                             struct perf_event *event)
+{
+       int i;
+
+       for (i = 0; i < cpuc->n_events; i++) {
+               if (cpuc->event[i] == event)
+                       break;
+       }
+       BUG_ON(i == cpuc->n_events);
+       return cpuc->current_idx[i];
 }
 
 static void sparc_pmu_read(struct perf_event *event)
 {
+       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       int idx = active_event_index(cpuc, event);
        struct hw_perf_event *hwc = &event->hw;
 
-       sparc_perf_event_update(event, hwc, hwc->idx);
+       sparc_perf_event_update(event, hwc, idx);
 }
 
 static void sparc_pmu_unthrottle(struct perf_event *event)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       int idx = active_event_index(cpuc, event);
        struct hw_perf_event *hwc = &event->hw;
 
-       sparc_pmu_enable_event(cpuc, hwc, hwc->idx);
+       sparc_pmu_enable_event(cpuc, hwc, idx);
 }
 
 static atomic_t active_events = ATOMIC_INIT(0);
@@ -750,43 +854,75 @@ static void hw_perf_event_destroy(struct perf_event *event)
 /* Make sure all events can be scheduled into the hardware at
  * the same time.  This is simplified by the fact that we only
  * need to support 2 simultaneous HW events.
+ *
+ * As a side effect, the evts[]->hw.idx values will be assigned
+ * on success.  These are pending indexes.  When the events are
+ * actually programmed into the chip, these values will propagate
+ * to the per-cpu cpuc->current_idx[] slots, see the code in
+ * maybe_change_configuration() for details.
  */
-static int sparc_check_constraints(unsigned long *events, int n_ev)
+static int sparc_check_constraints(struct perf_event **evts,
+                                  unsigned long *events, int n_ev)
 {
-       if (n_ev <= perf_max_events) {
-               u8 msk1, msk2;
-               u16 dummy;
-
-               if (n_ev == 1)
-                       return 0;
-               BUG_ON(n_ev != 2);
-               perf_event_decode(events[0], &dummy, &msk1);
-               perf_event_decode(events[1], &dummy, &msk2);
-
-               /* If both events can go on any counter, OK.  */
-               if (msk1 == (PIC_UPPER | PIC_LOWER) &&
-                   msk2 == (PIC_UPPER | PIC_LOWER))
-                       return 0;
-
-               /* If one event is limited to a specific counter,
-                * and the other can go on both, OK.
-                */
-               if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
-                   msk2 == (PIC_UPPER | PIC_LOWER))
-                       return 0;
-               if ((msk2 == PIC_UPPER || msk2 == PIC_LOWER) &&
-                   msk1 == (PIC_UPPER | PIC_LOWER))
-                       return 0;
-
-               /* If the events are fixed to different counters, OK.  */
-               if ((msk1 == PIC_UPPER && msk2 == PIC_LOWER) ||
-                   (msk1 == PIC_LOWER && msk2 == PIC_UPPER))
-                       return 0;
-
-               /* Otherwise, there is a conflict.  */
+       u8 msk0 = 0, msk1 = 0;
+       int idx0 = 0;
+
+       /* This case is possible when we are invoked from
+        * hw_perf_group_sched_in().
+        */
+       if (!n_ev)
+               return 0;
+
+       if (n_ev > perf_max_events)
+               return -1;
+
+       msk0 = perf_event_get_msk(events[0]);
+       if (n_ev == 1) {
+               if (msk0 & PIC_LOWER)
+                       idx0 = 1;
+               goto success;
        }
+       BUG_ON(n_ev != 2);
+       msk1 = perf_event_get_msk(events[1]);
+
+       /* If both events can go on any counter, OK.  */
+       if (msk0 == (PIC_UPPER | PIC_LOWER) &&
+           msk1 == (PIC_UPPER | PIC_LOWER))
+               goto success;
 
+       /* If one event is limited to a specific counter,
+        * and the other can go on both, OK.
+        */
+       if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
+           msk1 == (PIC_UPPER | PIC_LOWER)) {
+               if (msk0 & PIC_LOWER)
+                       idx0 = 1;
+               goto success;
+       }
+
+       if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
+           msk0 == (PIC_UPPER | PIC_LOWER)) {
+               if (msk1 & PIC_UPPER)
+                       idx0 = 1;
+               goto success;
+       }
+
+       /* If the events are fixed to different counters, OK.  */
+       if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
+           (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
+               if (msk0 & PIC_LOWER)
+                       idx0 = 1;
+               goto success;
+       }
+
+       /* Otherwise, there is a conflict.  */
        return -1;
+
+success:
+       evts[0]->hw.idx = idx0;
+       if (n_ev == 2)
+               evts[1]->hw.idx = idx0 ^ 1;
+       return 0;
 }
 
 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
@@ -818,7 +954,8 @@ static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
 }
 
 static int collect_events(struct perf_event *group, int max_count,
-                         struct perf_event *evts[], unsigned long *events)
+                         struct perf_event *evts[], unsigned long *events,
+                         int *current_idx)
 {
        struct perf_event *event;
        int n = 0;
@@ -827,7 +964,8 @@ static int collect_events(struct perf_event *group, int max_count,
                if (n >= max_count)
                        return -1;
                evts[n] = group;
-               events[n++] = group->hw.event_base;
+               events[n] = group->hw.event_base;
+               current_idx[n++] = PIC_NO_INDEX;
        }
        list_for_each_entry(event, &group->sibling_list, group_entry) {
                if (!is_software_event(event) &&
@@ -835,20 +973,100 @@ static int collect_events(struct perf_event *group, int max_count,
                        if (n >= max_count)
                                return -1;
                        evts[n] = event;
-                       events[n++] = event->hw.event_base;
+                       events[n] = event->hw.event_base;
+                       current_idx[n++] = PIC_NO_INDEX;
                }
        }
        return n;
 }
 
+static void event_sched_in(struct perf_event *event, int cpu)
+{
+       event->state = PERF_EVENT_STATE_ACTIVE;
+       event->oncpu = cpu;
+       event->tstamp_running += event->ctx->time - event->tstamp_stopped;
+       if (is_software_event(event))
+               event->pmu->enable(event);
+}
+
+int hw_perf_group_sched_in(struct perf_event *group_leader,
+                          struct perf_cpu_context *cpuctx,
+                          struct perf_event_context *ctx, int cpu)
+{
+       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       struct perf_event *sub;
+       int n0, n;
+
+       if (!sparc_pmu)
+               return 0;
+
+       n0 = cpuc->n_events;
+       n = collect_events(group_leader, perf_max_events - n0,
+                          &cpuc->event[n0], &cpuc->events[n0],
+                          &cpuc->current_idx[n0]);
+       if (n < 0)
+               return -EAGAIN;
+       if (check_excludes(cpuc->event, n0, n))
+               return -EINVAL;
+       if (sparc_check_constraints(cpuc->event, cpuc->events, n + n0))
+               return -EAGAIN;
+       cpuc->n_events = n0 + n;
+       cpuc->n_added += n;
+
+       cpuctx->active_oncpu += n;
+       n = 1;
+       event_sched_in(group_leader, cpu);
+       list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
+               if (sub->state != PERF_EVENT_STATE_OFF) {
+                       event_sched_in(sub, cpu);
+                       n++;
+               }
+       }
+       ctx->nr_active += n;
+
+       return 1;
+}
+
+static int sparc_pmu_enable(struct perf_event *event)
+{
+       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       int n0, ret = -EAGAIN;
+       unsigned long flags;
+
+       local_irq_save(flags);
+       perf_disable();
+
+       n0 = cpuc->n_events;
+       if (n0 >= perf_max_events)
+               goto out;
+
+       cpuc->event[n0] = event;
+       cpuc->events[n0] = event->hw.event_base;
+       cpuc->current_idx[n0] = PIC_NO_INDEX;
+
+       if (check_excludes(cpuc->event, n0, 1))
+               goto out;
+       if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
+               goto out;
+
+       cpuc->n_events++;
+       cpuc->n_added++;
+
+       ret = 0;
+out:
+       perf_enable();
+       local_irq_restore(flags);
+       return ret;
+}
+
 static int __hw_perf_event_init(struct perf_event *event)
 {
        struct perf_event_attr *attr = &event->attr;
        struct perf_event *evts[MAX_HWEVENTS];
        struct hw_perf_event *hwc = &event->hw;
        unsigned long events[MAX_HWEVENTS];
+       int current_idx_dmy[MAX_HWEVENTS];
        const struct perf_event_map *pmap;
-       u64 enc;
        int n;
 
        if (atomic_read(&nmi_active) < 0)
@@ -865,10 +1083,7 @@ static int __hw_perf_event_init(struct perf_event *event)
        } else
                return -EOPNOTSUPP;
 
-       /* We save the enable bits in the config_base.  So to
-        * turn off sampling just write 'config', and to enable
-        * things write 'config | config_base'.
-        */
+       /* We save the enable bits in the config_base.  */
        hwc->config_base = sparc_pmu->irq_bit;
        if (!attr->exclude_user)
                hwc->config_base |= PCR_UTRACE;
@@ -879,13 +1094,11 @@ static int __hw_perf_event_init(struct perf_event *event)
 
        hwc->event_base = perf_event_encode(pmap);
 
-       enc = pmap->encoding;
-
        n = 0;
        if (event->group_leader != event) {
                n = collect_events(event->group_leader,
                                   perf_max_events - 1,
-                                  evts, events);
+                                  evts, events, current_idx_dmy);
                if (n < 0)
                        return -EINVAL;
        }
@@ -895,9 +1108,11 @@ static int __hw_perf_event_init(struct perf_event *event)
        if (check_excludes(evts, n, 1))
                return -EINVAL;
 
-       if (sparc_check_constraints(events, n + 1))
+       if (sparc_check_constraints(evts, events, n + 1))
                return -EINVAL;
 
+       hwc->idx = PIC_NO_INDEX;
+
        /* Try to do all error checking before this point, as unwinding
         * state after grabbing the PMC is difficult.
         */
@@ -910,15 +1125,6 @@ static int __hw_perf_event_init(struct perf_event *event)
                atomic64_set(&hwc->period_left, hwc->sample_period);
        }
 
-       if (pmap->pic_mask & PIC_UPPER) {
-               hwc->idx = PIC_UPPER_INDEX;
-               enc <<= sparc_pmu->upper_shift;
-       } else {
-               hwc->idx = PIC_LOWER_INDEX;
-               enc <<= sparc_pmu->lower_shift;
-       }
-
-       hwc->config |= enc;
        return 0;
 }
 
@@ -968,7 +1174,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
        struct perf_sample_data data;
        struct cpu_hw_events *cpuc;
        struct pt_regs *regs;
-       int idx;
+       int i;
 
        if (!atomic_read(&active_events))
                return NOTIFY_DONE;
@@ -997,13 +1203,12 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
        if (sparc_pmu->irq_bit)
                pcr_ops->write(cpuc->pcr);
 
-       for (idx = 0; idx < MAX_HWEVENTS; idx++) {
-               struct perf_event *event = cpuc->events[idx];
+       for (i = 0; i < cpuc->n_events; i++) {
+               struct perf_event *event = cpuc->event[i];
+               int idx = cpuc->current_idx[i];
                struct hw_perf_event *hwc;
                u64 val;
 
-               if (!test_bit(idx, cpuc->active_mask))
-                       continue;
                hwc = &event->hw;
                val = sparc_perf_event_update(event, hwc, idx);
                if (val & (1ULL << 31))
@@ -1055,10 +1260,122 @@ void __init init_hw_perf_events(void)
 
        pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
 
-       /* All sparc64 PMUs currently have 2 events.  But this simple
-        * driver only supports one active event at a time.
-        */
-       perf_max_events = 1;
+       /* All sparc64 PMUs currently have 2 events.  */
+       perf_max_events = 2;
 
        register_die_notifier(&perf_event_nmi_notifier);
 }
+
+static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip)
+{
+       if (entry->nr < PERF_MAX_STACK_DEPTH)
+               entry->ip[entry->nr++] = ip;
+}
+
+static void perf_callchain_kernel(struct pt_regs *regs,
+                                 struct perf_callchain_entry *entry)
+{
+       unsigned long ksp, fp;
+
+       callchain_store(entry, PERF_CONTEXT_KERNEL);
+       callchain_store(entry, regs->tpc);
+
+       ksp = regs->u_regs[UREG_I6];
+       fp = ksp + STACK_BIAS;
+       do {
+               struct sparc_stackf *sf;
+               struct pt_regs *regs;
+               unsigned long pc;
+
+               if (!kstack_valid(current_thread_info(), fp))
+                       break;
+
+               sf = (struct sparc_stackf *) fp;
+               regs = (struct pt_regs *) (sf + 1);
+
+               if (kstack_is_trap_frame(current_thread_info(), regs)) {
+                       if (user_mode(regs))
+                               break;
+                       pc = regs->tpc;
+                       fp = regs->u_regs[UREG_I6] + STACK_BIAS;
+               } else {
+                       pc = sf->callers_pc;
+                       fp = (unsigned long)sf->fp + STACK_BIAS;
+               }
+               callchain_store(entry, pc);
+       } while (entry->nr < PERF_MAX_STACK_DEPTH);
+}
+
+static void perf_callchain_user_64(struct pt_regs *regs,
+                                  struct perf_callchain_entry *entry)
+{
+       unsigned long ufp;
+
+       callchain_store(entry, PERF_CONTEXT_USER);
+       callchain_store(entry, regs->tpc);
+
+       ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
+       do {
+               struct sparc_stackf *usf, sf;
+               unsigned long pc;
+
+               usf = (struct sparc_stackf *) ufp;
+               if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
+                       break;
+
+               pc = sf.callers_pc;
+               ufp = (unsigned long)sf.fp + STACK_BIAS;
+               callchain_store(entry, pc);
+       } while (entry->nr < PERF_MAX_STACK_DEPTH);
+}
+
+static void perf_callchain_user_32(struct pt_regs *regs,
+                                  struct perf_callchain_entry *entry)
+{
+       unsigned long ufp;
+
+       callchain_store(entry, PERF_CONTEXT_USER);
+       callchain_store(entry, regs->tpc);
+
+       ufp = regs->u_regs[UREG_I6];
+       do {
+               struct sparc_stackf32 *usf, sf;
+               unsigned long pc;
+
+               usf = (struct sparc_stackf32 *) ufp;
+               if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
+                       break;
+
+               pc = sf.callers_pc;
+               ufp = (unsigned long)sf.fp;
+               callchain_store(entry, pc);
+       } while (entry->nr < PERF_MAX_STACK_DEPTH);
+}
+
+/* Like powerpc we can't get PMU interrupts within the PMU handler,
+ * so no need for seperate NMI and IRQ chains as on x86.
+ */
+static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
+
+struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
+{
+       struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
+
+       entry->nr = 0;
+       if (!user_mode(regs)) {
+               stack_trace_flush();
+               perf_callchain_kernel(regs, entry);
+               if (current->mm)
+                       regs = task_pt_regs(current);
+               else
+                       regs = NULL;
+       }
+       if (regs) {
+               flushw_user();
+               if (test_thread_flag(TIF_32BIT))
+                       perf_callchain_user_32(regs, entry);
+               else
+                       perf_callchain_user_64(regs, entry);
+       }
+       return entry;
+}
index cfa0e19abe3bd62b2e0f64f2b5b5d15499b0b9c9..d77f54316948e83cdc035c9e04d76cbd8d4702a1 100644 (file)
@@ -365,6 +365,7 @@ EXPORT_SYMBOL(get_fb_unmapped_area);
 void arch_pick_mmap_layout(struct mm_struct *mm)
 {
        unsigned long random_factor = 0UL;
+       unsigned long gap;
 
        if (current->flags & PF_RANDOMIZE) {
                random_factor = get_random_int();
@@ -379,9 +380,10 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
         * Fall back to the standard layout if the personality
         * bit is set, or if the expected stack growth is unlimited:
         */
+       gap = rlimit(RLIMIT_STACK);
        if (!test_thread_flag(TIF_32BIT) ||
            (current->personality & ADDR_COMPAT_LAYOUT) ||
-           current->signal->rlim[RLIMIT_STACK].rlim_cur == RLIM_INFINITY ||
+           gap == RLIM_INFINITY ||
            sysctl_legacy_va_layout) {
                mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
                mm->get_unmapped_area = arch_get_unmapped_area;
@@ -389,9 +391,7 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
        } else {
                /* We know it's 32-bit */
                unsigned long task_size = STACK_TOP32;
-               unsigned long gap;
 
-               gap = current->signal->rlim[RLIMIT_STACK].rlim_cur;
                if (gap < 128 * 1024 * 1024)
                        gap = 128 * 1024 * 1024;
                if (gap > (task_size / 6 * 5))
index 5b2f595fe65b58aad400fafc876bca36bef4ce07..0d4c09b15efc9da4edf6b9354d003384b1f405d9 100644 (file)
@@ -35,6 +35,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/oplib.h>
+#include <asm/timex.h>
 #include <asm/timer.h>
 #include <asm/system.h>
 #include <asm/irq.h>
@@ -51,7 +52,6 @@ DEFINE_SPINLOCK(rtc_lock);
 EXPORT_SYMBOL(rtc_lock);
 
 static int set_rtc_mmss(unsigned long);
-static int sbus_do_settimeofday(struct timespec *tv);
 
 unsigned long profile_pc(struct pt_regs *regs)
 {
@@ -76,6 +76,8 @@ EXPORT_SYMBOL(profile_pc);
 
 __volatile__ unsigned int *master_l10_counter;
 
+u32 (*do_arch_gettimeoffset)(void);
+
 /*
  * timer_interrupt() needs to keep up the real-time clock,
  * as well as call the "do_timer()" routine every clocktick
@@ -196,35 +198,14 @@ static int __init clock_init(void)
 {
        return of_register_driver(&clock_driver, &of_platform_bus_type);
 }
-
 /* Must be after subsys_initcall() so that busses are probed.  Must
  * be before device_initcall() because things like the RTC driver
  * need to see the clock registers.
  */
 fs_initcall(clock_init);
 
-static void __init sbus_time_init(void)
-{
-
-       BTFIXUPSET_CALL(bus_do_settimeofday, sbus_do_settimeofday, BTFIXUPCALL_NORM);
-       btfixup();
-
-       sparc_init_timers(timer_interrupt);
-}
-
-void __init time_init(void)
-{
-#ifdef CONFIG_PCI
-       extern void pci_time_init(void);
-       if (pcic_present()) {
-               pci_time_init();
-               return;
-       }
-#endif
-       sbus_time_init();
-}
 
-static inline unsigned long do_gettimeoffset(void)
+u32 sbus_do_gettimeoffset(void)
 {
        unsigned long val = *master_l10_counter;
        unsigned long usec = (val >> 10) & 0x1fffff;
@@ -233,86 +214,39 @@ static inline unsigned long do_gettimeoffset(void)
        if (val & 0x80000000)
                usec += 1000000 / HZ;
 
-       return usec;
+       return usec * 1000;
 }
 
-/* Ok, my cute asm atomicity trick doesn't work anymore.
- * There are just too many variables that need to be protected
- * now (both members of xtime, et al.)
- */
-void do_gettimeofday(struct timeval *tv)
-{
-       unsigned long flags;
-       unsigned long seq;
-       unsigned long usec, sec;
-       unsigned long max_ntp_tick = tick_usec - tickadj;
-
-       do {
-               seq = read_seqbegin_irqsave(&xtime_lock, flags);
-               usec = do_gettimeoffset();
-
-               /*
-                * If time_adjust is negative then NTP is slowing the clock
-                * so make sure not to go into next possible interval.
-                * Better to lose some accuracy than have time go backwards..
-                */
-               if (unlikely(time_adjust < 0))
-                       usec = min(usec, max_ntp_tick);
-
-               sec = xtime.tv_sec;
-               usec += (xtime.tv_nsec / 1000);
-       } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
-
-       while (usec >= 1000000) {
-               usec -= 1000000;
-               sec++;
-       }
 
-       tv->tv_sec = sec;
-       tv->tv_usec = usec;
-}
-
-EXPORT_SYMBOL(do_gettimeofday);
-
-int do_settimeofday(struct timespec *tv)
+u32 arch_gettimeoffset(void)
 {
-       int ret;
-
-       write_seqlock_irq(&xtime_lock);
-       ret = bus_do_settimeofday(tv);
-       write_sequnlock_irq(&xtime_lock);
-       clock_was_set();
-       return ret;
+       if (unlikely(!do_arch_gettimeoffset))
+               return 0;
+       return do_arch_gettimeoffset();
 }
 
-EXPORT_SYMBOL(do_settimeofday);
-
-static int sbus_do_settimeofday(struct timespec *tv)
+static void __init sbus_time_init(void)
 {
-       time_t wtm_sec, sec = tv->tv_sec;
-       long wtm_nsec, nsec = tv->tv_nsec;
+       do_arch_gettimeoffset = sbus_do_gettimeoffset;
 
-       if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
-               return -EINVAL;
-
-       /*
-        * This is revolting. We need to set "xtime" correctly. However, the
-        * value in this location is the value at the most recent update of
-        * wall time.  Discover what correction gettimeofday() would have
-        * made, and then undo it!
-        */
-       nsec -= 1000 * do_gettimeoffset();
-
-       wtm_sec  = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
-       wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
+       btfixup();
 
-       set_normalized_timespec(&xtime, sec, nsec);
-       set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
+       sparc_init_timers(timer_interrupt);
+}
 
-       ntp_clear();
-       return 0;
+void __init time_init(void)
+{
+#ifdef CONFIG_PCI
+       extern void pci_time_init(void);
+       if (pcic_present()) {
+               pci_time_init();
+               return;
+       }
+#endif
+       sbus_time_init();
 }
 
+
 static int set_rtc_mmss(unsigned long secs)
 {
        struct rtc_device *rtc = rtc_class_open("rtc0");
index b99f81c4906f72ae3486c54d3cc1e69d15822383..a3413acb8f127ce4bbd92d6305a83a9e428819fe 100644 (file)
@@ -18,6 +18,7 @@
 #include <linux/signal.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
+#include <linux/perf_event.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/kdebug.h>
@@ -203,6 +204,8 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
         if (in_atomic() || !mm)
                 goto no_context;
 
+       perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+
        down_read(&mm->mmap_sem);
 
        /*
@@ -249,10 +252,15 @@ good_area:
                        goto do_sigbus;
                BUG();
        }
-       if (fault & VM_FAULT_MAJOR)
+       if (fault & VM_FAULT_MAJOR) {
                current->maj_flt++;
-       else
+               perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                             regs, address);
+       } else {
                current->min_flt++;
+               perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                             regs, address);
+       }
        up_read(&mm->mmap_sem);
        return;
 
index 6081936bf03b84579ce488b7488b8bc7c6e395ac..b9d4ff02b8fc2229a9f0028e38fb621f5376b7b6 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/perf_event.h>
 #include <linux/interrupt.h>
 #include <linux/kprobes.h>
 #include <linux/kdebug.h>
@@ -296,6 +297,8 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
        if (in_atomic() || !mm)
                goto intr_or_no_mm;
 
+       perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+
        if (!down_read_trylock(&mm->mmap_sem)) {
                if ((regs->tstate & TSTATE_PRIV) &&
                    !search_exception_tables(regs->tpc)) {
@@ -400,11 +403,15 @@ good_area:
                        goto do_sigbus;
                BUG();
        }
-       if (fault & VM_FAULT_MAJOR)
+       if (fault & VM_FAULT_MAJOR) {
                current->maj_flt++;
-       else
+               perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                             regs, address);
+       } else {
                current->min_flt++;
-
+               perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                             regs, address);
+       }
        up_read(&mm->mmap_sem);
 
        mm_rss = get_mm_rss(mm);
index cbcbfdee3ee08695b8dbdbf873755dac7762d324..eb4092568f9e53f737bbf902f26fb4aeeb423bf6 100644 (file)
@@ -989,12 +989,6 @@ config X86_CPUID
          with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to
          /dev/cpu/31/cpuid.
 
-config X86_CPU_DEBUG
-       tristate "/sys/kernel/debug/x86/cpu/* - CPU Debug support"
-       ---help---
-         If you select this option, this will provide various x86 CPUs
-         information through debugfs.
-
 choice
        prompt "High Memory Support"
        default HIGHMEM4G if !X86_NUMAQ
diff --git a/arch/x86/include/asm/cpu_debug.h b/arch/x86/include/asm/cpu_debug.h
deleted file mode 100644 (file)
index d96c1ee..0000000
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _ASM_X86_CPU_DEBUG_H
-#define _ASM_X86_CPU_DEBUG_H
-
-/*
- * CPU x86 architecture debug
- *
- * Copyright(C) 2009 Jaswinder Singh Rajput
- */
-
-/* Register flags */
-enum cpu_debug_bit {
-/* Model Specific Registers (MSRs)                                     */
-       CPU_MC_BIT,                             /* Machine Check        */
-       CPU_MONITOR_BIT,                        /* Monitor              */
-       CPU_TIME_BIT,                           /* Time                 */
-       CPU_PMC_BIT,                            /* Performance Monitor  */
-       CPU_PLATFORM_BIT,                       /* Platform             */
-       CPU_APIC_BIT,                           /* APIC                 */
-       CPU_POWERON_BIT,                        /* Power-on             */
-       CPU_CONTROL_BIT,                        /* Control              */
-       CPU_FEATURES_BIT,                       /* Features control     */
-       CPU_LBRANCH_BIT,                        /* Last Branch          */
-       CPU_BIOS_BIT,                           /* BIOS                 */
-       CPU_FREQ_BIT,                           /* Frequency            */
-       CPU_MTTR_BIT,                           /* MTRR                 */
-       CPU_PERF_BIT,                           /* Performance          */
-       CPU_CACHE_BIT,                          /* Cache                */
-       CPU_SYSENTER_BIT,                       /* Sysenter             */
-       CPU_THERM_BIT,                          /* Thermal              */
-       CPU_MISC_BIT,                           /* Miscellaneous        */
-       CPU_DEBUG_BIT,                          /* Debug                */
-       CPU_PAT_BIT,                            /* PAT                  */
-       CPU_VMX_BIT,                            /* VMX                  */
-       CPU_CALL_BIT,                           /* System Call          */
-       CPU_BASE_BIT,                           /* BASE Address         */
-       CPU_VER_BIT,                            /* Version ID           */
-       CPU_CONF_BIT,                           /* Configuration        */
-       CPU_SMM_BIT,                            /* System mgmt mode     */
-       CPU_SVM_BIT,                            /*Secure Virtual Machine*/
-       CPU_OSVM_BIT,                           /* OS-Visible Workaround*/
-/* Standard Registers                                                  */
-       CPU_TSS_BIT,                            /* Task Stack Segment   */
-       CPU_CR_BIT,                             /* Control Registers    */
-       CPU_DT_BIT,                             /* Descriptor Table     */
-/* End of Registers flags                                              */
-       CPU_REG_ALL_BIT,                        /* Select all Registers */
-};
-
-#define        CPU_REG_ALL             (~0)            /* Select all Registers */
-
-#define        CPU_MC                  (1 << CPU_MC_BIT)
-#define        CPU_MONITOR             (1 << CPU_MONITOR_BIT)
-#define        CPU_TIME                (1 << CPU_TIME_BIT)
-#define        CPU_PMC                 (1 << CPU_PMC_BIT)
-#define        CPU_PLATFORM            (1 << CPU_PLATFORM_BIT)
-#define        CPU_APIC                (1 << CPU_APIC_BIT)
-#define        CPU_POWERON             (1 << CPU_POWERON_BIT)
-#define        CPU_CONTROL             (1 << CPU_CONTROL_BIT)
-#define        CPU_FEATURES            (1 << CPU_FEATURES_BIT)
-#define        CPU_LBRANCH             (1 << CPU_LBRANCH_BIT)
-#define        CPU_BIOS                (1 << CPU_BIOS_BIT)
-#define        CPU_FREQ                (1 << CPU_FREQ_BIT)
-#define        CPU_MTRR                (1 << CPU_MTTR_BIT)
-#define        CPU_PERF                (1 << CPU_PERF_BIT)
-#define        CPU_CACHE               (1 << CPU_CACHE_BIT)
-#define        CPU_SYSENTER            (1 << CPU_SYSENTER_BIT)
-#define        CPU_THERM               (1 << CPU_THERM_BIT)
-#define        CPU_MISC                (1 << CPU_MISC_BIT)
-#define        CPU_DEBUG               (1 << CPU_DEBUG_BIT)
-#define        CPU_PAT                 (1 << CPU_PAT_BIT)
-#define        CPU_VMX                 (1 << CPU_VMX_BIT)
-#define        CPU_CALL                (1 << CPU_CALL_BIT)
-#define        CPU_BASE                (1 << CPU_BASE_BIT)
-#define        CPU_VER                 (1 << CPU_VER_BIT)
-#define        CPU_CONF                (1 << CPU_CONF_BIT)
-#define        CPU_SMM                 (1 << CPU_SMM_BIT)
-#define        CPU_SVM                 (1 << CPU_SVM_BIT)
-#define        CPU_OSVM                (1 << CPU_OSVM_BIT)
-#define        CPU_TSS                 (1 << CPU_TSS_BIT)
-#define        CPU_CR                  (1 << CPU_CR_BIT)
-#define        CPU_DT                  (1 << CPU_DT_BIT)
-
-/* Register file flags */
-enum cpu_file_bit {
-       CPU_INDEX_BIT,                          /* index                */
-       CPU_VALUE_BIT,                          /* value                */
-};
-
-#define        CPU_FILE_VALUE          (1 << CPU_VALUE_BIT)
-
-#define MAX_CPU_FILES          512
-
-struct cpu_private {
-       unsigned                cpu;
-       unsigned                type;
-       unsigned                reg;
-       unsigned                file;
-};
-
-struct cpu_debug_base {
-       char                    *name;          /* Register name        */
-       unsigned                flag;           /* Register flag        */
-       unsigned                write;          /* Register write flag  */
-};
-
-/*
- * Currently it looks similar to cpu_debug_base but once we add more files
- * cpu_file_base will go in different direction
- */
-struct cpu_file_base {
-       char                    *name;          /* Register file name   */
-       unsigned                flag;           /* Register file flag   */
-       unsigned                write;          /* Register write flag  */
-};
-
-struct cpu_cpuX_base {
-       struct dentry           *dentry;        /* Register dentry      */
-       int                     init;           /* Register index file  */
-};
-
-struct cpu_debug_range {
-       unsigned                min;            /* Register range min   */
-       unsigned                max;            /* Register range max   */
-       unsigned                flag;           /* Supported flags      */
-};
-
-#endif /* _ASM_X86_CPU_DEBUG_H */
index 5d89fd2a3690664e5dc205b915e2ddf65f97b231..1d5c08a1bdfdb5b61c72cb286dfb0ac382c17e76 100644 (file)
@@ -67,6 +67,7 @@ extern unsigned long hpet_address;
 extern unsigned long force_hpet_address;
 extern u8 hpet_blockid;
 extern int hpet_force_user;
+extern u8 hpet_msi_disable;
 extern int is_hpet_enabled(void);
 extern int hpet_enable(void);
 extern void hpet_disable(void);
index c24ca9a56458e029da2e3c107f9a0fc2c80908eb..ef51b501e22a6e53bf4ae7e2d9e2566760f72ee1 100644 (file)
@@ -12,8 +12,6 @@ struct device;
 enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };
 
 struct microcode_ops {
-       void (*init)(struct device *device);
-       void (*fini)(void);
        enum ucode_state (*request_microcode_user) (int cpu,
                                const void __user *buf, size_t size);
 
index 1d2cb383410ebef206fb48e2ccecbe8fd03f90ce..c202b62f36719b1c00ca635e75f91e996d55c4e3 100644 (file)
@@ -19,8 +19,6 @@ obj-y                 += vmware.o hypervisor.o sched.o
 obj-$(CONFIG_X86_32)   += bugs.o cmpxchg.o
 obj-$(CONFIG_X86_64)   += bugs_64.o
 
-obj-$(CONFIG_X86_CPU_DEBUG)            += cpu_debug.o
-
 obj-$(CONFIG_CPU_SUP_INTEL)            += intel.o
 obj-$(CONFIG_CPU_SUP_AMD)              += amd.o
 obj-$(CONFIG_CPU_SUP_CYRIX_32)         += cyrix.o
diff --git a/arch/x86/kernel/cpu/cpu_debug.c b/arch/x86/kernel/cpu/cpu_debug.c
deleted file mode 100644 (file)
index b368cd8..0000000
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * CPU x86 architecture debug code
- *
- * Copyright(C) 2009 Jaswinder Singh Rajput
- *
- * For licencing details see kernel-base/COPYING
- */
-
-#include <linux/interrupt.h>
-#include <linux/compiler.h>
-#include <linux/seq_file.h>
-#include <linux/debugfs.h>
-#include <linux/kprobes.h>
-#include <linux/uaccess.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/percpu.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/smp.h>
-
-#include <asm/cpu_debug.h>
-#include <asm/paravirt.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/apic.h>
-#include <asm/desc.h>
-
-static DEFINE_PER_CPU(struct cpu_cpuX_base [CPU_REG_ALL_BIT], cpud_arr);
-static DEFINE_PER_CPU(struct cpu_private * [MAX_CPU_FILES], cpud_priv_arr);
-static DEFINE_PER_CPU(int, cpud_priv_count);
-
-static DEFINE_MUTEX(cpu_debug_lock);
-
-static struct dentry *cpu_debugfs_dir;
-
-static struct cpu_debug_base cpu_base[] = {
-       { "mc",         CPU_MC,         0       },
-       { "monitor",    CPU_MONITOR,    0       },
-       { "time",       CPU_TIME,       0       },
-       { "pmc",        CPU_PMC,        1       },
-       { "platform",   CPU_PLATFORM,   0       },
-       { "apic",       CPU_APIC,       0       },
-       { "poweron",    CPU_POWERON,    0       },
-       { "control",    CPU_CONTROL,    0       },
-       { "features",   CPU_FEATURES,   0       },
-       { "lastbranch", CPU_LBRANCH,    0       },
-       { "bios",       CPU_BIOS,       0       },
-       { "freq",       CPU_FREQ,       0       },
-       { "mtrr",       CPU_MTRR,       0       },
-       { "perf",       CPU_PERF,       0       },
-       { "cache",      CPU_CACHE,      0       },
-       { "sysenter",   CPU_SYSENTER,   0       },
-       { "therm",      CPU_THERM,      0       },
-       { "misc",       CPU_MISC,       0       },
-       { "debug",      CPU_DEBUG,      0       },
-       { "pat",        CPU_PAT,        0       },
-       { "vmx",        CPU_VMX,        0       },
-       { "call",       CPU_CALL,       0       },
-       { "base",       CPU_BASE,       0       },
-       { "ver",        CPU_VER,        0       },
-       { "conf",       CPU_CONF,       0       },
-       { "smm",        CPU_SMM,        0       },
-       { "svm",        CPU_SVM,        0       },
-       { "osvm",       CPU_OSVM,       0       },
-       { "tss",        CPU_TSS,        0       },
-       { "cr",         CPU_CR,         0       },
-       { "dt",         CPU_DT,         0       },
-       { "registers",  CPU_REG_ALL,    0       },
-};
-
-static struct cpu_file_base cpu_file[] = {
-       { "index",      CPU_REG_ALL,    0       },
-       { "value",      CPU_REG_ALL,    1       },
-};
-
-/* CPU Registers Range */
-static struct cpu_debug_range cpu_reg_range[] = {
-       { 0x00000000, 0x00000001, CPU_MC,       },
-       { 0x00000006, 0x00000007, CPU_MONITOR,  },
-       { 0x00000010, 0x00000010, CPU_TIME,     },
-       { 0x00000011, 0x00000013, CPU_PMC,      },
-       { 0x00000017, 0x00000017, CPU_PLATFORM, },
-       { 0x0000001B, 0x0000001B, CPU_APIC,     },
-       { 0x0000002A, 0x0000002B, CPU_POWERON,  },
-       { 0x0000002C, 0x0000002C, CPU_FREQ,     },
-       { 0x0000003A, 0x0000003A, CPU_CONTROL,  },
-       { 0x00000040, 0x00000047, CPU_LBRANCH,  },
-       { 0x00000060, 0x00000067, CPU_LBRANCH,  },
-       { 0x00000079, 0x00000079, CPU_BIOS,     },
-       { 0x00000088, 0x0000008A, CPU_CACHE,    },
-       { 0x0000008B, 0x0000008B, CPU_BIOS,     },
-       { 0x0000009B, 0x0000009B, CPU_MONITOR,  },
-       { 0x000000C1, 0x000000C4, CPU_PMC,      },
-       { 0x000000CD, 0x000000CD, CPU_FREQ,     },
-       { 0x000000E7, 0x000000E8, CPU_PERF,     },
-       { 0x000000FE, 0x000000FE, CPU_MTRR,     },
-
-       { 0x00000116, 0x0000011E, CPU_CACHE,    },
-       { 0x00000174, 0x00000176, CPU_SYSENTER, },
-       { 0x00000179, 0x0000017B, CPU_MC,       },
-       { 0x00000186, 0x00000189, CPU_PMC,      },
-       { 0x00000198, 0x00000199, CPU_PERF,     },
-       { 0x0000019A, 0x0000019A, CPU_TIME,     },
-       { 0x0000019B, 0x0000019D, CPU_THERM,    },
-       { 0x000001A0, 0x000001A0, CPU_MISC,     },
-       { 0x000001C9, 0x000001C9, CPU_LBRANCH,  },
-       { 0x000001D7, 0x000001D8, CPU_LBRANCH,  },
-       { 0x000001D9, 0x000001D9, CPU_DEBUG,    },
-       { 0x000001DA, 0x000001E0, CPU_LBRANCH,  },
-
-       { 0x00000200, 0x0000020F, CPU_MTRR,     },
-       { 0x00000250, 0x00000250, CPU_MTRR,     },
-       { 0x00000258, 0x00000259, CPU_MTRR,     },
-       { 0x00000268, 0x0000026F, CPU_MTRR,     },
-       { 0x00000277, 0x00000277, CPU_PAT,      },
-       { 0x000002FF, 0x000002FF, CPU_MTRR,     },
-
-       { 0x00000300, 0x00000311, CPU_PMC,      },
-       { 0x00000345, 0x00000345, CPU_PMC,      },
-       { 0x00000360, 0x00000371, CPU_PMC,      },
-       { 0x0000038D, 0x00000390, CPU_PMC,      },
-       { 0x000003A0, 0x000003BE, CPU_PMC,      },
-       { 0x000003C0, 0x000003CD, CPU_PMC,      },
-       { 0x000003E0, 0x000003E1, CPU_PMC,      },
-       { 0x000003F0, 0x000003F2, CPU_PMC,      },
-
-       { 0x00000400, 0x00000417, CPU_MC,       },
-       { 0x00000480, 0x0000048B, CPU_VMX,      },
-
-       { 0x00000600, 0x00000600, CPU_DEBUG,    },
-       { 0x00000680, 0x0000068F, CPU_LBRANCH,  },
-       { 0x000006C0, 0x000006CF, CPU_LBRANCH,  },
-
-       { 0x000107CC, 0x000107D3, CPU_PMC,      },
-
-       { 0xC0000080, 0xC0000080, CPU_FEATURES, },
-       { 0xC0000081, 0xC0000084, CPU_CALL,     },
-       { 0xC0000100, 0xC0000102, CPU_BASE,     },
-       { 0xC0000103, 0xC0000103, CPU_TIME,     },
-
-       { 0xC0010000, 0xC0010007, CPU_PMC,      },
-       { 0xC0010010, 0xC0010010, CPU_CONF,     },
-       { 0xC0010015, 0xC0010015, CPU_CONF,     },
-       { 0xC0010016, 0xC001001A, CPU_MTRR,     },
-       { 0xC001001D, 0xC001001D, CPU_MTRR,     },
-       { 0xC001001F, 0xC001001F, CPU_CONF,     },
-       { 0xC0010030, 0xC0010035, CPU_BIOS,     },
-       { 0xC0010044, 0xC0010048, CPU_MC,       },
-       { 0xC0010050, 0xC0010056, CPU_SMM,      },
-       { 0xC0010058, 0xC0010058, CPU_CONF,     },
-       { 0xC0010060, 0xC0010060, CPU_CACHE,    },
-       { 0xC0010061, 0xC0010068, CPU_SMM,      },
-       { 0xC0010069, 0xC001006B, CPU_SMM,      },
-       { 0xC0010070, 0xC0010071, CPU_SMM,      },
-       { 0xC0010111, 0xC0010113, CPU_SMM,      },
-       { 0xC0010114, 0xC0010118, CPU_SVM,      },
-       { 0xC0010140, 0xC0010141, CPU_OSVM,     },
-       { 0xC0011022, 0xC0011023, CPU_CONF,     },
-};
-
-static int is_typeflag_valid(unsigned cpu, unsigned flag)
-{
-       int i;
-
-       /* Standard Registers should be always valid */
-       if (flag >= CPU_TSS)
-               return 1;
-
-       for (i = 0; i < ARRAY_SIZE(cpu_reg_range); i++) {
-               if (cpu_reg_range[i].flag == flag)
-                       return 1;
-       }
-
-       /* Invalid */
-       return 0;
-}
-
-static unsigned get_cpu_range(unsigned cpu, unsigned *min, unsigned *max,
-                             int index, unsigned flag)
-{
-       if (cpu_reg_range[index].flag == flag) {
-               *min = cpu_reg_range[index].min;
-               *max = cpu_reg_range[index].max;
-       } else
-               *max = 0;
-
-       return *max;
-}
-
-/* This function can also be called with seq = NULL for printk */
-static void print_cpu_data(struct seq_file *seq, unsigned type,
-                          u32 low, u32 high)
-{
-       struct cpu_private *priv;
-       u64 val = high;
-
-       if (seq) {
-               priv = seq->private;
-               if (priv->file) {
-                       val = (val << 32) | low;
-                       seq_printf(seq, "0x%llx\n", val);
-               } else
-                       seq_printf(seq, " %08x: %08x_%08x\n",
-                                  type, high, low);
-       } else
-               printk(KERN_INFO " %08x: %08x_%08x\n", type, high, low);
-}
-
-/* This function can also be called with seq = NULL for printk */
-static void print_msr(struct seq_file *seq, unsigned cpu, unsigned flag)
-{
-       unsigned msr, msr_min, msr_max;
-       struct cpu_private *priv;
-       u32 low, high;
-       int i;
-
-       if (seq) {
-               priv = seq->private;
-               if (priv->file) {
-                       if (!rdmsr_safe_on_cpu(priv->cpu, priv->reg,
-                                              &low, &high))
-                               print_cpu_data(seq, priv->reg, low, high);
-                       return;
-               }
-       }
-
-       for (i = 0; i < ARRAY_SIZE(cpu_reg_range); i++) {
-               if (!get_cpu_range(cpu, &msr_min, &msr_max, i, flag))
-                       continue;
-
-               for (msr = msr_min; msr <= msr_max; msr++) {
-                       if (rdmsr_safe_on_cpu(cpu, msr, &low, &high))
-                               continue;
-                       print_cpu_data(seq, msr, low, high);
-               }
-       }
-}
-
-static void print_tss(void *arg)
-{
-       struct pt_regs *regs = task_pt_regs(current);
-       struct seq_file *seq = arg;
-       unsigned int seg;
-
-       seq_printf(seq, " RAX\t: %016lx\n", regs->ax);
-       seq_printf(seq, " RBX\t: %016lx\n", regs->bx);
-       seq_printf(seq, " RCX\t: %016lx\n", regs->cx);
-       seq_printf(seq, " RDX\t: %016lx\n", regs->dx);
-
-       seq_printf(seq, " RSI\t: %016lx\n", regs->si);
-       seq_printf(seq, " RDI\t: %016lx\n", regs->di);
-       seq_printf(seq, " RBP\t: %016lx\n", regs->bp);
-       seq_printf(seq, " ESP\t: %016lx\n", regs->sp);
-
-#ifdef CONFIG_X86_64
-       seq_printf(seq, " R08\t: %016lx\n", regs->r8);
-       seq_printf(seq, " R09\t: %016lx\n", regs->r9);
-       seq_printf(seq, " R10\t: %016lx\n", regs->r10);
-       seq_printf(seq, " R11\t: %016lx\n", regs->r11);
-       seq_printf(seq, " R12\t: %016lx\n", regs->r12);
-       seq_printf(seq, " R13\t: %016lx\n", regs->r13);
-       seq_printf(seq, " R14\t: %016lx\n", regs->r14);
-       seq_printf(seq, " R15\t: %016lx\n", regs->r15);
-#endif
-
-       asm("movl %%cs,%0" : "=r" (seg));
-       seq_printf(seq, " CS\t:             %04x\n", seg);
-       asm("movl %%ds,%0" : "=r" (seg));
-       seq_printf(seq, " DS\t:             %04x\n", seg);
-       seq_printf(seq, " SS\t:             %04lx\n", regs->ss & 0xffff);
-       asm("movl %%es,%0" : "=r" (seg));
-       seq_printf(seq, " ES\t:             %04x\n", seg);
-       asm("movl %%fs,%0" : "=r" (seg));
-       seq_printf(seq, " FS\t:             %04x\n", seg);
-       asm("movl %%gs,%0" : "=r" (seg));
-       seq_printf(seq, " GS\t:             %04x\n", seg);
-
-       seq_printf(seq, " EFLAGS\t: %016lx\n", regs->flags);
-
-       seq_printf(seq, " EIP\t: %016lx\n", regs->ip);
-}
-
-static void print_cr(void *arg)
-{
-       struct seq_file *seq = arg;
-
-       seq_printf(seq, " cr0\t: %016lx\n", read_cr0());
-       seq_printf(seq, " cr2\t: %016lx\n", read_cr2());
-       seq_printf(seq, " cr3\t: %016lx\n", read_cr3());
-       seq_printf(seq, " cr4\t: %016lx\n", read_cr4_safe());
-#ifdef CONFIG_X86_64
-       seq_printf(seq, " cr8\t: %016lx\n", read_cr8());
-#endif
-}
-
-static void print_desc_ptr(char *str, struct seq_file *seq, struct desc_ptr dt)
-{
-       seq_printf(seq, " %s\t: %016llx\n", str, (u64)(dt.address | dt.size));
-}
-
-static void print_dt(void *seq)
-{
-       struct desc_ptr dt;
-       unsigned long ldt;
-
-       /* IDT */
-       store_idt((struct desc_ptr *)&dt);
-       print_desc_ptr("IDT", seq, dt);
-
-       /* GDT */
-       store_gdt((struct desc_ptr *)&dt);
-       print_desc_ptr("GDT", seq, dt);
-
-       /* LDT */
-       store_ldt(ldt);
-       seq_printf(seq, " LDT\t: %016lx\n", ldt);
-
-       /* TR */
-       store_tr(ldt);
-       seq_printf(seq, " TR\t: %016lx\n", ldt);
-}
-
-static void print_dr(void *arg)
-{
-       struct seq_file *seq = arg;
-       unsigned long dr;
-       int i;
-
-       for (i = 0; i < 8; i++) {
-               /* Ignore db4, db5 */
-               if ((i == 4) || (i == 5))
-                       continue;
-               get_debugreg(dr, i);
-               seq_printf(seq, " dr%d\t: %016lx\n", i, dr);
-       }
-
-       seq_printf(seq, "\n MSR\t:\n");
-}
-
-static void print_apic(void *arg)
-{
-       struct seq_file *seq = arg;
-
-#ifdef CONFIG_X86_LOCAL_APIC
-       seq_printf(seq, " LAPIC\t:\n");
-       seq_printf(seq, " ID\t\t: %08x\n",  apic_read(APIC_ID) >> 24);
-       seq_printf(seq, " LVR\t\t: %08x\n",  apic_read(APIC_LVR));
-       seq_printf(seq, " TASKPRI\t: %08x\n",  apic_read(APIC_TASKPRI));
-       seq_printf(seq, " ARBPRI\t\t: %08x\n",  apic_read(APIC_ARBPRI));
-       seq_printf(seq, " PROCPRI\t: %08x\n",  apic_read(APIC_PROCPRI));
-       seq_printf(seq, " LDR\t\t: %08x\n",  apic_read(APIC_LDR));
-       seq_printf(seq, " DFR\t\t: %08x\n",  apic_read(APIC_DFR));
-       seq_printf(seq, " SPIV\t\t: %08x\n",  apic_read(APIC_SPIV));
-       seq_printf(seq, " ISR\t\t: %08x\n",  apic_read(APIC_ISR));
-       seq_printf(seq, " ESR\t\t: %08x\n",  apic_read(APIC_ESR));
-       seq_printf(seq, " ICR\t\t: %08x\n",  apic_read(APIC_ICR));
-       seq_printf(seq, " ICR2\t\t: %08x\n",  apic_read(APIC_ICR2));
-       seq_printf(seq, " LVTT\t\t: %08x\n",  apic_read(APIC_LVTT));
-       seq_printf(seq, " LVTTHMR\t: %08x\n",  apic_read(APIC_LVTTHMR));
-       seq_printf(seq, " LVTPC\t\t: %08x\n",  apic_read(APIC_LVTPC));
-       seq_printf(seq, " LVT0\t\t: %08x\n",  apic_read(APIC_LVT0));
-       seq_printf(seq, " LVT1\t\t: %08x\n",  apic_read(APIC_LVT1));
-       seq_printf(seq, " LVTERR\t\t: %08x\n",  apic_read(APIC_LVTERR));
-       seq_printf(seq, " TMICT\t\t: %08x\n",  apic_read(APIC_TMICT));
-       seq_printf(seq, " TMCCT\t\t: %08x\n",  apic_read(APIC_TMCCT));
-       seq_printf(seq, " TDCR\t\t: %08x\n",  apic_read(APIC_TDCR));
-       if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
-               unsigned int i, v, maxeilvt;
-
-               v = apic_read(APIC_EFEAT);
-               maxeilvt = (v >> 16) & 0xff;
-               seq_printf(seq, " EFEAT\t\t: %08x\n", v);
-               seq_printf(seq, " ECTRL\t\t: %08x\n", apic_read(APIC_ECTRL));
-
-               for (i = 0; i < maxeilvt; i++) {
-                       v = apic_read(APIC_EILVTn(i));
-                       seq_printf(seq, " EILVT%d\t\t: %08x\n", i, v);
-               }
-       }
-#endif /* CONFIG_X86_LOCAL_APIC */
-       seq_printf(seq, "\n MSR\t:\n");
-}
-
-static int cpu_seq_show(struct seq_file *seq, void *v)
-{
-       struct cpu_private *priv = seq->private;
-
-       if (priv == NULL)
-               return -EINVAL;
-
-       switch (cpu_base[priv->type].flag) {
-       case CPU_TSS:
-               smp_call_function_single(priv->cpu, print_tss, seq, 1);
-               break;
-       case CPU_CR:
-               smp_call_function_single(priv->cpu, print_cr, seq, 1);
-               break;
-       case CPU_DT:
-               smp_call_function_single(priv->cpu, print_dt, seq, 1);
-               break;
-       case CPU_DEBUG:
-               if (priv->file == CPU_INDEX_BIT)
-                       smp_call_function_single(priv->cpu, print_dr, seq, 1);
-               print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
-               break;
-       case CPU_APIC:
-               if (priv->file == CPU_INDEX_BIT)
-                       smp_call_function_single(priv->cpu, print_apic, seq, 1);
-               print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
-               break;
-
-       default:
-               print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
-               break;
-       }
-       seq_printf(seq, "\n");
-
-       return 0;
-}
-
-static void *cpu_seq_start(struct seq_file *seq, loff_t *pos)
-{
-       if (*pos == 0) /* One time is enough ;-) */
-               return seq;
-
-       return NULL;
-}
-
-static void *cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
-{
-       (*pos)++;
-
-       return cpu_seq_start(seq, pos);
-}
-
-static void cpu_seq_stop(struct seq_file *seq, void *v)
-{
-}
-
-static const struct seq_operations cpu_seq_ops = {
-       .start          = cpu_seq_start,
-       .next           = cpu_seq_next,
-       .stop           = cpu_seq_stop,
-       .show           = cpu_seq_show,
-};
-
-static int cpu_seq_open(struct inode *inode, struct file *file)
-{
-       struct cpu_private *priv = inode->i_private;
-       struct seq_file *seq;
-       int err;
-
-       err = seq_open(file, &cpu_seq_ops);
-       if (!err) {
-               seq = file->private_data;
-               seq->private = priv;
-       }
-
-       return err;
-}
-
-static int write_msr(struct cpu_private *priv, u64 val)
-{
-       u32 low, high;
-
-       high = (val >> 32) & 0xffffffff;
-       low = val & 0xffffffff;
-
-       if (!wrmsr_safe_on_cpu(priv->cpu, priv->reg, low, high))
-               return 0;
-
-       return -EPERM;
-}
-
-static int write_cpu_register(struct cpu_private *priv, const char *buf)
-{
-       int ret = -EPERM;
-       u64 val;
-
-       ret = strict_strtoull(buf, 0, &val);
-       if (ret < 0)
-               return ret;
-
-       /* Supporting only MSRs */
-       if (priv->type < CPU_TSS_BIT)
-               return write_msr(priv, val);
-
-       return ret;
-}
-
-static ssize_t cpu_write(struct file *file, const char __user *ubuf,
-                            size_t count, loff_t *off)
-{
-       struct seq_file *seq = file->private_data;
-       struct cpu_private *priv = seq->private;
-       char buf[19];
-
-       if ((priv == NULL) || (count >= sizeof(buf)))
-               return -EINVAL;
-
-       if (copy_from_user(&buf, ubuf, count))
-               return -EFAULT;
-
-       buf[count] = 0;
-
-       if ((cpu_base[priv->type].write) && (cpu_file[priv->file].write))
-               if (!write_cpu_register(priv, buf))
-                       return count;
-
-       return -EACCES;
-}
-
-static const struct file_operations cpu_fops = {
-       .owner          = THIS_MODULE,
-       .open           = cpu_seq_open,
-       .read           = seq_read,
-       .write          = cpu_write,
-       .llseek         = seq_lseek,
-       .release        = seq_release,
-};
-
-static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
-                          unsigned file, struct dentry *dentry)
-{
-       struct cpu_private *priv = NULL;
-
-       /* Already intialized */
-       if (file == CPU_INDEX_BIT)
-               if (per_cpu(cpud_arr[type].init, cpu))
-                       return 0;
-
-       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-       if (priv == NULL)
-               return -ENOMEM;
-
-       priv->cpu = cpu;
-       priv->type = type;
-       priv->reg = reg;
-       priv->file = file;
-       mutex_lock(&cpu_debug_lock);
-       per_cpu(cpud_priv_arr[type], cpu) = priv;
-       per_cpu(cpud_priv_count, cpu)++;
-       mutex_unlock(&cpu_debug_lock);
-
-       if (file)
-               debugfs_create_file(cpu_file[file].name, S_IRUGO,
-                                   dentry, (void *)priv, &cpu_fops);
-       else {
-               debugfs_create_file(cpu_base[type].name, S_IRUGO,
-                                   per_cpu(cpud_arr[type].dentry, cpu),
-                                   (void *)priv, &cpu_fops);
-               mutex_lock(&cpu_debug_lock);
-               per_cpu(cpud_arr[type].init, cpu) = 1;
-               mutex_unlock(&cpu_debug_lock);
-       }
-
-       return 0;
-}
-
-static int cpu_init_regfiles(unsigned cpu, unsigned int type, unsigned reg,
-                            struct dentry *dentry)
-{
-       unsigned file;
-       int err = 0;
-
-       for (file = 0; file <  ARRAY_SIZE(cpu_file); file++) {
-               err = cpu_create_file(cpu, type, reg, file, dentry);
-               if (err)
-                       return err;
-       }
-
-       return err;
-}
-
-static int cpu_init_msr(unsigned cpu, unsigned type, struct dentry *dentry)
-{
-       struct dentry *cpu_dentry = NULL;
-       unsigned reg, reg_min, reg_max;
-       int i, err = 0;
-       char reg_dir[12];
-       u32 low, high;
-
-       for (i = 0; i < ARRAY_SIZE(cpu_reg_range); i++) {
-               if (!get_cpu_range(cpu, &reg_min, &reg_max, i,
-                                  cpu_base[type].flag))
-                       continue;
-
-               for (reg = reg_min; reg <= reg_max; reg++) {
-                       if (rdmsr_safe_on_cpu(cpu, reg, &low, &high))
-                               continue;
-
-                       sprintf(reg_dir, "0x%x", reg);
-                       cpu_dentry = debugfs_create_dir(reg_dir, dentry);
-                       err = cpu_init_regfiles(cpu, type, reg, cpu_dentry);
-                       if (err)
-                               return err;
-               }
-       }
-
-       return err;
-}
-
-static int cpu_init_allreg(unsigned cpu, struct dentry *dentry)
-{
-       struct dentry *cpu_dentry = NULL;
-       unsigned type;
-       int err = 0;
-
-       for (type = 0; type <  ARRAY_SIZE(cpu_base) - 1; type++) {
-               if (!is_typeflag_valid(cpu, cpu_base[type].flag))
-                       continue;
-               cpu_dentry = debugfs_create_dir(cpu_base[type].name, dentry);
-               per_cpu(cpud_arr[type].dentry, cpu) = cpu_dentry;
-
-               if (type < CPU_TSS_BIT)
-                       err = cpu_init_msr(cpu, type, cpu_dentry);
-               else
-                       err = cpu_create_file(cpu, type, 0, CPU_INDEX_BIT,
-                                             cpu_dentry);
-               if (err)
-                       return err;
-       }
-
-       return err;
-}
-
-static int cpu_init_cpu(void)
-{
-       struct dentry *cpu_dentry = NULL;
-       struct cpuinfo_x86 *cpui;
-       char cpu_dir[12];
-       unsigned cpu;
-       int err = 0;
-
-       for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
-               cpui = &cpu_data(cpu);
-               if (!cpu_has(cpui, X86_FEATURE_MSR))
-                       continue;
-
-               sprintf(cpu_dir, "cpu%d", cpu);
-               cpu_dentry = debugfs_create_dir(cpu_dir, cpu_debugfs_dir);
-               err = cpu_init_allreg(cpu, cpu_dentry);
-
-               pr_info("cpu%d(%d) debug files %d\n",
-                       cpu, nr_cpu_ids, per_cpu(cpud_priv_count, cpu));
-               if (per_cpu(cpud_priv_count, cpu) > MAX_CPU_FILES) {
-                       pr_err("Register files count %d exceeds limit %d\n",
-                               per_cpu(cpud_priv_count, cpu), MAX_CPU_FILES);
-                       per_cpu(cpud_priv_count, cpu) = MAX_CPU_FILES;
-                       err = -ENFILE;
-               }
-               if (err)
-                       return err;
-       }
-
-       return err;
-}
-
-static int __init cpu_debug_init(void)
-{
-       cpu_debugfs_dir = debugfs_create_dir("cpu", arch_debugfs_dir);
-
-       return cpu_init_cpu();
-}
-
-static void __exit cpu_debug_exit(void)
-{
-       int i, cpu;
-
-       if (cpu_debugfs_dir)
-               debugfs_remove_recursive(cpu_debugfs_dir);
-
-       for (cpu = 0; cpu <  nr_cpu_ids; cpu++)
-               for (i = 0; i < per_cpu(cpud_priv_count, cpu); i++)
-                       kfree(per_cpu(cpud_priv_arr[i], cpu));
-}
-
-module_init(cpu_debug_init);
-module_exit(cpu_debug_exit);
-
-MODULE_AUTHOR("Jaswinder Singh Rajput");
-MODULE_DESCRIPTION("CPU Debug module");
-MODULE_LICENSE("GPL");
index cb27fd6136c9bec099b0a944ee59a8425d39d09c..83e5e628de73a7234f90c2f7130e98fa4df4fe4e 100644 (file)
@@ -229,7 +229,7 @@ static void __exit cpuid_exit(void)
        for_each_online_cpu(cpu)
                cpuid_device_destroy(cpu);
        class_destroy(cpuid_class);
-       unregister_chrdev(CPUID_MAJOR, "cpu/cpuid");
+       __unregister_chrdev(CPUID_MAJOR, 0, NR_CPUS, "cpu/cpuid");
        unregister_hotcpu_notifier(&cpuid_class_cpu_notifier);
 }
 
index ba6e658846035a75f17b16e5ee5cf1de82eb337f..ad80a1c718c6e53e9dd1b1cecac342393289ae73 100644 (file)
@@ -34,6 +34,8 @@
  */
 unsigned long                          hpet_address;
 u8                                     hpet_blockid; /* OS timer block num */
+u8                                     hpet_msi_disable;
+
 #ifdef CONFIG_PCI_MSI
 static unsigned long                   hpet_num_timers;
 #endif
@@ -596,6 +598,9 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
        unsigned int num_timers_used = 0;
        int i;
 
+       if (hpet_msi_disable)
+               return;
+
        if (boot_cpu_has(X86_FEATURE_ARAT))
                return;
        id = hpet_readl(HPET_ID);
@@ -928,6 +933,9 @@ static __init int hpet_late_init(void)
        hpet_reserve_platform_timers(hpet_readl(HPET_ID));
        hpet_print_config();
 
+       if (hpet_msi_disable)
+               return 0;
+
        if (boot_cpu_has(X86_FEATURE_ARAT))
                return 0;
 
index 37542b67c57e4299738d609c3e44206be251304e..e1af7c055c7d0c86c7e3a1fe789e597825185892 100644 (file)
@@ -36,9 +36,6 @@ MODULE_LICENSE("GPL v2");
 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
 #define UCODE_UCODE_TYPE           0x00000001
 
-const struct firmware *firmware;
-static int supported_cpu;
-
 struct equiv_cpu_entry {
        u32     installed_cpu;
        u32     fixed_errata_mask;
@@ -77,12 +74,15 @@ static struct equiv_cpu_entry *equiv_cpu_table;
 
 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 {
+       struct cpuinfo_x86 *c = &cpu_data(cpu);
        u32 dummy;
 
-       if (!supported_cpu)
-               return -1;
-
        memset(csig, 0, sizeof(*csig));
+       if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+               pr_warning("microcode: CPU%d: AMD CPU family 0x%x not "
+                          "supported\n", cpu, c->x86);
+               return -1;
+       }
        rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
        pr_info("CPU%d: patch_level=0x%x\n", cpu, csig->rev);
        return 0;
@@ -294,10 +294,14 @@ generic_load_microcode(int cpu, const u8 *data, size_t size)
 
 static enum ucode_state request_microcode_fw(int cpu, struct device *device)
 {
+       const char *fw_name = "amd-ucode/microcode_amd.bin";
+       const struct firmware *firmware;
        enum ucode_state ret;
 
-       if (firmware == NULL)
+       if (request_firmware(&firmware, fw_name, device)) {
+               printk(KERN_ERR "microcode: failed to load file %s\n", fw_name);
                return UCODE_NFOUND;
+       }
 
        if (*(u32 *)firmware->data != UCODE_MAGIC) {
                pr_err("invalid UCODE_MAGIC (0x%08x)\n",
@@ -307,6 +311,8 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device)
 
        ret = generic_load_microcode(cpu, firmware->data, firmware->size);
 
+       release_firmware(firmware);
+
        return ret;
 }
 
@@ -325,31 +331,7 @@ static void microcode_fini_cpu_amd(int cpu)
        uci->mc = NULL;
 }
 
-void init_microcode_amd(struct device *device)
-{
-       const char *fw_name = "amd-ucode/microcode_amd.bin";
-       struct cpuinfo_x86 *c = &boot_cpu_data;
-
-       WARN_ON(c->x86_vendor != X86_VENDOR_AMD);
-
-       if (c->x86 < 0x10) {
-               pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
-               return;
-       }
-       supported_cpu = 1;
-
-       if (request_firmware(&firmware, fw_name, device))
-               pr_err("failed to load file %s\n", fw_name);
-}
-
-void fini_microcode_amd(void)
-{
-       release_firmware(firmware);
-}
-
 static struct microcode_ops microcode_amd_ops = {
-       .init                             = init_microcode_amd,
-       .fini                             = fini_microcode_amd,
        .request_microcode_user           = request_microcode_user,
        .request_microcode_fw             = request_microcode_fw,
        .collect_cpu_info                 = collect_cpu_info_amd,
index 0c8632433090d6e90de8dff937f7fcf7719e6e0b..cceb5bc3c3c258c2a6f1957ee152f00c7310d462 100644 (file)
@@ -521,9 +521,6 @@ static int __init microcode_init(void)
                return PTR_ERR(microcode_pdev);
        }
 
-       if (microcode_ops->init)
-               microcode_ops->init(&microcode_pdev->dev);
-
        get_online_cpus();
        mutex_lock(&microcode_mutex);
 
@@ -566,9 +563,6 @@ static void __exit microcode_exit(void)
 
        platform_device_unregister(microcode_pdev);
 
-       if (microcode_ops->fini)
-               microcode_ops->fini();
-
        microcode_ops = NULL;
 
        pr_info("Microcode Update Driver: v" MICROCODE_VERSION " removed.\n");
index 4bd93c9b2b2716d86367c41631ffa1a0c4625a83..206735ac8cbdbaf053e039fb5f6e4fb5c50a5f8a 100644 (file)
@@ -285,7 +285,7 @@ static void __exit msr_exit(void)
        for_each_online_cpu(cpu)
                msr_device_destroy(cpu);
        class_destroy(msr_class);
-       unregister_chrdev(MSR_MAJOR, "cpu/msr");
+       __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
        unregister_hotcpu_notifier(&msr_class_cpu_notifier);
 }
 
index 18093d7498f0d70144c19cbc954a644decda597d..12e9feaa2f7aba947b65ca2fe3611be81321a8f1 100644 (file)
@@ -491,6 +491,19 @@ void force_hpet_resume(void)
                break;
        }
 }
+
+/*
+ * HPET MSI on some boards (ATI SB700/SB800) has side effect on
+ * floppy DMA. Disable HPET MSI on such platforms.
+ */
+static void force_disable_hpet_msi(struct pci_dev *unused)
+{
+       hpet_msi_disable = 1;
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
+                        force_disable_hpet_msi);
+
 #endif
 
 #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
index 3063a0c4858b462a23dd8e2b7d6b81342a203fc1..ba8c045da7820fceea3286b2a60c1378fe28265d 100644 (file)
@@ -373,6 +373,12 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                if (unlikely(!apic_enabled(apic)))
                        break;
 
+               if (trig_mode) {
+                       apic_debug("level trig mode for vector %d", vector);
+                       apic_set_vector(vector, apic->regs + APIC_TMR);
+               } else
+                       apic_clear_vector(vector, apic->regs + APIC_TMR);
+
                result = !apic_test_and_set_irr(vector, apic);
                trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
                                          trig_mode, vector, !result);
@@ -383,11 +389,6 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                        break;
                }
 
-               if (trig_mode) {
-                       apic_debug("level trig mode for vector %d", vector);
-                       apic_set_vector(vector, apic->regs + APIC_TMR);
-               } else
-                       apic_clear_vector(vector, apic->regs + APIC_TMR);
                kvm_vcpu_kick(vcpu);
                break;
 
index 4c3e5b2314cb1c8ca94ff13909af2061b702466d..89a49fb46a275e6eebcf2609f3870696b3a3945b 100644 (file)
@@ -477,7 +477,7 @@ static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
 
        addr = gfn_to_hva(kvm, gfn);
        if (kvm_is_error_hva(addr))
-               return page_size;
+               return PT_PAGE_TABLE_LEVEL;
 
        down_read(&current->mm->mmap_sem);
        vma = find_vma(current->mm, addr);
@@ -515,11 +515,9 @@ static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
        if (host_level == PT_PAGE_TABLE_LEVEL)
                return host_level;
 
-       for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level) {
-
+       for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level)
                if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
                        break;
-       }
 
        return level - 1;
 }
index 58a0f1e8859655154da07037604ebd5fb1872c7f..ede2131a9225eb00530aafb62962e383ab2a7101 100644 (file)
@@ -150,7 +150,9 @@ walk:
                walker->table_gfn[walker->level - 1] = table_gfn;
                walker->pte_gpa[walker->level - 1] = pte_gpa;
 
-               kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
+               if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
+                       goto not_present;
+
                trace_kvm_mmu_paging_element(pte, walker->level);
 
                if (!is_present_gpte(pte))
index 6651dbf58675ee7ec8d9e7f3e145dce09953e054..1ddcad452add0808b3c3aac39c291db32c3e620a 100644 (file)
@@ -5072,12 +5072,13 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
                                       GFP_KERNEL);
        if (!vcpu->arch.mce_banks) {
                r = -ENOMEM;
-               goto fail_mmu_destroy;
+               goto fail_free_lapic;
        }
        vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
 
        return 0;
-
+fail_free_lapic:
+       kvm_free_lapic(vcpu);
 fail_mmu_destroy:
        kvm_mmu_destroy(vcpu);
 fail_free_pio_data:
@@ -5088,6 +5089,7 @@ fail:
 
 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
 {
+       kfree(vcpu->arch.mce_banks);
        kvm_free_lapic(vcpu);
        down_read(&vcpu->kvm->slots_lock);
        kvm_mmu_destroy(vcpu);
index a27124185fc1eca178798d63378e2935688ba656..28c68762648f9e28e02a9bd598c613e9e953fc37 100644 (file)
@@ -229,9 +229,11 @@ update_nodes_add(int node, unsigned long start, unsigned long end)
                        printk(KERN_ERR "SRAT: Hotplug zone not continuous. Partly ignored\n");
        }
 
-       if (changed)
+       if (changed) {
+               node_set(node, cpu_nodes_parsed);
                printk(KERN_INFO "SRAT: hot plug zone found %Lx - %Lx\n",
                                 nd->start, nd->end);
+       }
 }
 
 /* Callback for parsing of the Proximity Domain <-> Memory Area mappings */
index defcaf108460b59ac9e5cba023d26e6e7bef6f13..f665b05592f3ea878760de1651600ef4d73a35b1 100644 (file)
@@ -633,8 +633,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
                return NULL;
        }
        if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
-               printk(KERN_WARNING "integrated sync not supported\n");
-               return NULL;
+               printk(KERN_WARNING "composite sync not supported\n");
        }
 
        /* it is incorrect if hsync/vsync width is zero */
index 1c2b7d44ec05c90bb295e35448b97c3cbda02a6f..0f9e90552dc44098589e8bf20a1154266c25db67 100644 (file)
@@ -389,7 +389,7 @@ int drm_fb_helper_blank(int blank, struct fb_info *info)
                break;
        /* Display: Off; HSync: On, VSync: On */
        case FB_BLANK_NORMAL:
-               drm_fb_helper_off(info, DRM_MODE_DPMS_ON);
+               drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY);
                break;
        /* Display: Off; HSync: Off, VSync: On */
        case FB_BLANK_HSYNC_SUSPEND:
index e9dbb481c469f4a0071256349bd7a5e7a1239dcd..8bf3770f294e12feb562d046a5de4ed281b9ce45 100644 (file)
@@ -142,19 +142,6 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size)
        if (IS_ERR(obj->filp))
                goto free;
 
-       /* Basically we want to disable the OOM killer and handle ENOMEM
-        * ourselves by sacrificing pages from cached buffers.
-        * XXX shmem_file_[gs]et_gfp_mask()
-        */
-       mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping,
-                            GFP_HIGHUSER |
-                            __GFP_COLD |
-                            __GFP_FS |
-                            __GFP_RECLAIMABLE |
-                            __GFP_NORETRY |
-                            __GFP_NOWARN |
-                            __GFP_NOMEMALLOC);
-
        kref_init(&obj->refcount);
        kref_init(&obj->handlecount);
        obj->size = size;
index 9c9998c4dcebba0fd4efffabc2da954ac46d2cc7..a894ade030937c506e13322c2687b3c93b30420f 100644 (file)
@@ -290,7 +290,7 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data)
        list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
                obj = obj_priv->obj;
                if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
-                   ret = i915_gem_object_get_pages(obj);
+                   ret = i915_gem_object_get_pages(obj, 0);
                    if (ret) {
                            DRM_ERROR("Failed to get pages: %d\n", ret);
                            spin_unlock(&dev_priv->mm.active_list_lock);
index 2c1669488b5af7de10e49682245fc5fed0ca3480..aaf934d96f2156c4bdf4cb501fb221c2b4c02354 100644 (file)
@@ -872,7 +872,7 @@ int i915_gem_attach_phys_object(struct drm_device *dev,
 void i915_gem_detach_phys_object(struct drm_device *dev,
                                 struct drm_gem_object *obj);
 void i915_gem_free_all_phys_object(struct drm_device *dev);
-int i915_gem_object_get_pages(struct drm_gem_object *obj);
+int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
 void i915_gem_object_put_pages(struct drm_gem_object *obj);
 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
index 0c67924ca80ca273d0072fd6b1a22bfc0013a20b..dda787aafcc626ce064c3d59daf183c588fb5b69 100644 (file)
@@ -277,7 +277,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 
        mutex_lock(&dev->struct_mutex);
 
-       ret = i915_gem_object_get_pages(obj);
+       ret = i915_gem_object_get_pages(obj, 0);
        if (ret != 0)
                goto fail_unlock;
 
@@ -321,40 +321,24 @@ fail_unlock:
        return ret;
 }
 
-static inline gfp_t
-i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
-{
-       return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
-}
-
-static inline void
-i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
-{
-       mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
-}
-
 static int
 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 {
        int ret;
 
-       ret = i915_gem_object_get_pages(obj);
+       ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 
        /* If we've insufficient memory to map in the pages, attempt
         * to make some space by throwing out some old buffers.
         */
        if (ret == -ENOMEM) {
                struct drm_device *dev = obj->dev;
-               gfp_t gfp;
 
                ret = i915_gem_evict_something(dev, obj->size);
                if (ret)
                        return ret;
 
-               gfp = i915_gem_object_get_page_gfp_mask(obj);
-               i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
-               ret = i915_gem_object_get_pages(obj);
-               i915_gem_object_set_page_gfp_mask (obj, gfp);
+               ret = i915_gem_object_get_pages(obj, 0);
        }
 
        return ret;
@@ -790,7 +774,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 
        mutex_lock(&dev->struct_mutex);
 
-       ret = i915_gem_object_get_pages(obj);
+       ret = i915_gem_object_get_pages(obj, 0);
        if (ret != 0)
                goto fail_unlock;
 
@@ -2230,7 +2214,8 @@ i915_gem_evict_something(struct drm_device *dev, int min_size)
 }
 
 int
-i915_gem_object_get_pages(struct drm_gem_object *obj)
+i915_gem_object_get_pages(struct drm_gem_object *obj,
+                         gfp_t gfpmask)
 {
        struct drm_i915_gem_object *obj_priv = obj->driver_private;
        int page_count, i;
@@ -2256,7 +2241,10 @@ i915_gem_object_get_pages(struct drm_gem_object *obj)
        inode = obj->filp->f_path.dentry->d_inode;
        mapping = inode->i_mapping;
        for (i = 0; i < page_count; i++) {
-               page = read_mapping_page(mapping, i, NULL);
+               page = read_cache_page_gfp(mapping, i,
+                                          mapping_gfp_mask (mapping) |
+                                          __GFP_COLD |
+                                          gfpmask);
                if (IS_ERR(page)) {
                        ret = PTR_ERR(page);
                        i915_gem_object_put_pages(obj);
@@ -2579,7 +2567,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
        drm_i915_private_t *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj_priv = obj->driver_private;
        struct drm_mm_node *free_space;
-       bool retry_alloc = false;
+       gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
        int ret;
 
        if (obj_priv->madv != I915_MADV_WILLNEED) {
@@ -2623,15 +2611,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
        DRM_INFO("Binding object of size %zd at 0x%08x\n",
                 obj->size, obj_priv->gtt_offset);
 #endif
-       if (retry_alloc) {
-               i915_gem_object_set_page_gfp_mask (obj,
-                                                  i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
-       }
-       ret = i915_gem_object_get_pages(obj);
-       if (retry_alloc) {
-               i915_gem_object_set_page_gfp_mask (obj,
-                                                  i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
-       }
+       ret = i915_gem_object_get_pages(obj, gfpmask);
        if (ret) {
                drm_mm_put_block(obj_priv->gtt_space);
                obj_priv->gtt_space = NULL;
@@ -2641,9 +2621,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
                        ret = i915_gem_evict_something(dev, obj->size);
                        if (ret) {
                                /* now try to shrink everyone else */
-                               if (! retry_alloc) {
-                                   retry_alloc = true;
-                                   goto search_free;
+                               if (gfpmask) {
+                                       gfpmask = 0;
+                                       goto search_free;
                                }
 
                                return ret;
@@ -4946,7 +4926,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
        if (!obj_priv->phys_obj)
                return;
 
-       ret = i915_gem_object_get_pages(obj);
+       ret = i915_gem_object_get_pages(obj, 0);
        if (ret)
                goto out;
 
@@ -5004,7 +4984,7 @@ i915_gem_attach_phys_object(struct drm_device *dev,
        obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
        obj_priv->phys_obj->cur_obj = obj;
 
-       ret = i915_gem_object_get_pages(obj);
+       ret = i915_gem_object_get_pages(obj, 0);
        if (ret) {
                DRM_ERROR("failed to get page list\n");
                goto out;
index ba143972769f20329322c360763611d6971a1d62..d7f8d8b4a4b8cbc7f60eaca77c7538ba2b867583 100644 (file)
@@ -310,63 +310,22 @@ valid_reg(struct nvbios *bios, uint32_t reg)
        struct drm_device *dev = bios->dev;
 
        /* C51 has misaligned regs on purpose. Marvellous */
-       if (reg & 0x2 || (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51)) {
-               NV_ERROR(dev, "========== misaligned reg 0x%08X ==========\n",
-                        reg);
-               return 0;
-       }
-       /*
-        * Warn on C51 regs that have not been verified accessible in
-        * mmiotracing
-        */
+       if (reg & 0x2 ||
+           (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51))
+               NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
+
+       /* warn on C51 regs that haven't been verified accessible in tracing */
        if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 &&
            reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
                NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
                        reg);
 
-       /* Trust the init scripts on G80 */
-       if (dev_priv->card_type >= NV_50)
-               return 1;
-
-       #define WITHIN(x, y, z) ((x >= y) && (x < y + z))
-       if (WITHIN(reg, NV_PMC_OFFSET, NV_PMC_SIZE))
-               return 1;
-       if (WITHIN(reg, NV_PBUS_OFFSET, NV_PBUS_SIZE))
-               return 1;
-       if (WITHIN(reg, NV_PFIFO_OFFSET, NV_PFIFO_SIZE))
-               return 1;
-       if (dev_priv->VBIOS.pub.chip_version >= 0x30 &&
-           (WITHIN(reg, 0x4000, 0x600) || reg == 0x00004600))
-               return 1;
-       if (dev_priv->VBIOS.pub.chip_version >= 0x40 &&
-                                               WITHIN(reg, 0xc000, 0x48))
-               return 1;
-       if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0000d204)
-               return 1;
-       if (dev_priv->VBIOS.pub.chip_version >= 0x40) {
-               if (reg == 0x00011014 || reg == 0x00020328)
-                       return 1;
-               if (WITHIN(reg, 0x88000, NV_PBUS_SIZE)) /* new PBUS */
-                       return 1;
+       if (reg >= (8*1024*1024)) {
+               NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
+               return 0;
        }
-       if (WITHIN(reg, NV_PFB_OFFSET, NV_PFB_SIZE))
-               return 1;
-       if (WITHIN(reg, NV_PEXTDEV_OFFSET, NV_PEXTDEV_SIZE))
-               return 1;
-       if (WITHIN(reg, NV_PCRTC0_OFFSET, NV_PCRTC0_SIZE * 2))
-               return 1;
-       if (WITHIN(reg, NV_PRAMDAC0_OFFSET, NV_PRAMDAC0_SIZE * 2))
-               return 1;
-       if (dev_priv->VBIOS.pub.chip_version >= 0x17 && reg == 0x0070fff0)
-               return 1;
-       if (dev_priv->VBIOS.pub.chip_version == 0x51 &&
-                               WITHIN(reg, NV_PRAMIN_OFFSET, NV_PRAMIN_SIZE))
-               return 1;
-       #undef WITHIN
 
-       NV_ERROR(dev, "========== unknown reg 0x%08X ==========\n", reg);
-
-       return 0;
+       return 1;
 }
 
 static bool
@@ -3196,16 +3155,25 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entr
        }
 #ifdef __powerpc__
        /* Powerbook specific quirks */
-       if (script == LVDS_RESET && ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0329))
-               nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
-       if ((dev->pci_device & 0xffff) == 0x0179 || (dev->pci_device & 0xffff) == 0x0189 || (dev->pci_device & 0xffff) == 0x0329) {
-               if (script == LVDS_PANEL_ON) {
-                       bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31));
-                       bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
-               }
-               if (script == LVDS_PANEL_OFF) {
-                       bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31));
-                       bios_wr32(bios, NV_PCRTC_GPIO_EXT, bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
+       if ((dev->pci_device & 0xffff) == 0x0179 ||
+           (dev->pci_device & 0xffff) == 0x0189 ||
+           (dev->pci_device & 0xffff) == 0x0329) {
+               if (script == LVDS_RESET) {
+                       nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
+
+               } else if (script == LVDS_PANEL_ON) {
+                       bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
+                                 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
+                                 | (1 << 31));
+                       bios_wr32(bios, NV_PCRTC_GPIO_EXT,
+                                 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
+
+               } else if (script == LVDS_PANEL_OFF) {
+                       bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
+                                 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
+                                 & ~(1 << 31));
+                       bios_wr32(bios, NV_PCRTC_GPIO_EXT,
+                                 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
                }
        }
 #endif
@@ -5434,52 +5402,49 @@ static bool
 parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
                  uint32_t conn, uint32_t conf, struct dcb_entry *entry)
 {
-       if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 &&
-           conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 &&
-           conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 &&
-           conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 &&
-           conn != 0xf2045ff2 && conn != 0xf2045f14 && conn != 0xf207df14 &&
-           conn != 0xf2205004 && conn != 0xf2209004) {
-               NV_ERROR(dev, "Unknown DCB 1.5 entry, please report\n");
-
-               /* cause output setting to fail for !TV, so message is seen */
-               if ((conn & 0xf) != 0x1)
-                       dcb->entries = 0;
-
-               return false;
-       }
-       /* most of the below is a "best guess" atm */
-       entry->type = conn & 0xf;
-       if (entry->type == 2)
-               /* another way of specifying straps based lvds... */
+       switch (conn & 0x0000000f) {
+       case 0:
+               entry->type = OUTPUT_ANALOG;
+               break;
+       case 1:
+               entry->type = OUTPUT_TV;
+               break;
+       case 2:
+       case 3:
                entry->type = OUTPUT_LVDS;
-       if (entry->type == 4) { /* digital */
-               if (conn & 0x10)
-                       entry->type = OUTPUT_LVDS;
-               else
+               break;
+       case 4:
+               switch ((conn & 0x000000f0) >> 4) {
+               case 0:
                        entry->type = OUTPUT_TMDS;
+                       break;
+               case 1:
+                       entry->type = OUTPUT_LVDS;
+                       break;
+               default:
+                       NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
+                                (conn & 0x000000f0) >> 4);
+                       return false;
+               }
+               break;
+       default:
+               NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
+               return false;
        }
-       /* what's in bits 5-13? could be some encoder maker thing, in tv case */
-       entry->i2c_index = (conn >> 14) & 0xf;
-       /* raw heads field is in range 0-1, so move to 1-2 */
-       entry->heads = ((conn >> 18) & 0x7) + 1;
-       entry->location = (conn >> 21) & 0xf;
-       /* unused: entry->bus = (conn >> 25) & 0x7; */
-       /* set or to be same as heads -- hopefully safe enough */
-       entry->or = entry->heads;
+
+       entry->i2c_index = (conn & 0x0003c000) >> 14;
+       entry->heads = ((conn & 0x001c0000) >> 18) + 1;
+       entry->or = entry->heads; /* same as heads, hopefully safe enough */
+       entry->location = (conn & 0x01e00000) >> 21;
+       entry->bus = (conn & 0x0e000000) >> 25;
        entry->duallink_possible = false;
 
        switch (entry->type) {
        case OUTPUT_ANALOG:
                entry->crtconf.maxfreq = (conf & 0xffff) * 10;
                break;
-       case OUTPUT_LVDS:
-               /*
-                * This is probably buried in conn's unknown bits.
-                * This will upset EDID-ful models, if they exist
-                */
-               entry->lvdsconf.use_straps_for_mode = true;
-               entry->lvdsconf.use_power_scripts = true;
+       case OUTPUT_TV:
+               entry->tvconf.has_component_output = false;
                break;
        case OUTPUT_TMDS:
                /*
@@ -5488,8 +5453,12 @@ parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
                 */
                fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
                break;
-       case OUTPUT_TV:
-               entry->tvconf.has_component_output = false;
+       case OUTPUT_LVDS:
+               if ((conn & 0x00003f00) != 0x10)
+                       entry->lvdsconf.use_straps_for_mode = true;
+               entry->lvdsconf.use_power_scripts = true;
+               break;
+       default:
                break;
        }
 
@@ -5564,11 +5533,13 @@ void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb)
        dcb->entries = newentries;
 }
 
-static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
+static int
+parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
 {
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct bios_parsed_dcb *bdcb = &bios->bdcb;
        struct parsed_dcb *dcb;
-       uint16_t dcbptr, i2ctabptr = 0;
+       uint16_t dcbptr = 0, i2ctabptr = 0;
        uint8_t *dcbtable;
        uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
        bool configblock = true;
@@ -5579,16 +5550,18 @@ static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool two
        dcb->entries = 0;
 
        /* get the offset from 0x36 */
-       dcbptr = ROM16(bios->data[0x36]);
+       if (dev_priv->card_type > NV_04) {
+               dcbptr = ROM16(bios->data[0x36]);
+               if (dcbptr == 0x0000)
+                       NV_WARN(dev, "No output data (DCB) found in BIOS\n");
+       }
 
+       /* this situation likely means a really old card, pre DCB */
        if (dcbptr == 0x0) {
-               NV_WARN(dev, "No output data (DCB) found in BIOS, "
-                              "assuming a CRT output exists\n");
-               /* this situation likely means a really old card, pre DCB */
+               NV_INFO(dev, "Assuming a CRT output exists\n");
                fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
 
-               if (nv04_tv_identify(dev,
-                                    bios->legacy.i2c_indices.tv) >= 0)
+               if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
                        fabricate_tv_output(dcb, twoHeads);
 
                return 0;
index e342a418d434d41b9807ad2dd27683e0d4744084..db0ed4c13f9888d28f24577cb94c4add63856617 100644 (file)
@@ -469,6 +469,8 @@ nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 
        ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
                                        evict, no_wait, new_mem);
+       if (nvbo->channel && nvbo->channel != chan)
+               ret = nouveau_fence_wait(fence, NULL, false, false);
        nouveau_fence_unref((void *)&fence);
        return ret;
 }
index 5a10deb8bdbdebc54a14dcc4be6abe78dcccfd37..7e6d673f3a23dd5b21086e062fd27906d01bb8cc 100644 (file)
  *
  */
 
+#include <acpi/button.h>
+
 #include "drmP.h"
 #include "drm_edid.h"
 #include "drm_crtc_helper.h"
+
 #include "nouveau_reg.h"
 #include "nouveau_drv.h"
 #include "nouveau_encoder.h"
@@ -83,14 +86,16 @@ nouveau_encoder_connector_get(struct nouveau_encoder *encoder)
 static void
 nouveau_connector_destroy(struct drm_connector *drm_connector)
 {
-       struct nouveau_connector *connector = nouveau_connector(drm_connector);
-       struct drm_device *dev = connector->base.dev;
+       struct nouveau_connector *nv_connector =
+               nouveau_connector(drm_connector);
+       struct drm_device *dev = nv_connector->base.dev;
 
        NV_DEBUG_KMS(dev, "\n");
 
-       if (!connector)
+       if (!nv_connector)
                return;
 
+       kfree(nv_connector->edid);
        drm_sysfs_connector_remove(drm_connector);
        drm_connector_cleanup(drm_connector);
        kfree(drm_connector);
@@ -233,10 +238,21 @@ nouveau_connector_detect(struct drm_connector *connector)
        if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
                nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS);
        if (nv_encoder && nv_connector->native_mode) {
+#ifdef CONFIG_ACPI
+               if (!nouveau_ignorelid && !acpi_lid_open())
+                       return connector_status_disconnected;
+#endif
                nouveau_connector_set_encoder(connector, nv_encoder);
                return connector_status_connected;
        }
 
+       /* Cleanup the previous EDID block. */
+       if (nv_connector->edid) {
+               drm_mode_connector_update_edid_property(connector, NULL);
+               kfree(nv_connector->edid);
+               nv_connector->edid = NULL;
+       }
+
        i2c = nouveau_connector_ddc_detect(connector, &nv_encoder);
        if (i2c) {
                nouveau_connector_ddc_prepare(connector, &flags);
@@ -247,7 +263,7 @@ nouveau_connector_detect(struct drm_connector *connector)
                if (!nv_connector->edid) {
                        NV_ERROR(dev, "DDC responded, but no EDID for %s\n",
                                 drm_get_connector_name(connector));
-                       return connector_status_disconnected;
+                       goto detect_analog;
                }
 
                if (nv_encoder->dcb->type == OUTPUT_DP &&
@@ -281,6 +297,7 @@ nouveau_connector_detect(struct drm_connector *connector)
                return connector_status_connected;
        }
 
+detect_analog:
        nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG);
        if (!nv_encoder)
                nv_encoder = find_encoder_by_type(connector, OUTPUT_TV);
@@ -687,8 +704,12 @@ nouveau_connector_create_lvds(struct drm_device *dev,
         */
        if (!nv_connector->edid && !nv_connector->native_mode &&
            !dev_priv->VBIOS.pub.fp_no_ddc) {
-               nv_connector->edid =
+               struct edid *edid =
                        (struct edid *)nouveau_bios_embedded_edid(dev);
+               if (edid) {
+                       nv_connector->edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
+                       *(nv_connector->edid) = *edid;
+               }
        }
 
        if (!nv_connector->edid)
index 7afbe8b40d511f39f034d29b62e971ac6eab2a79..50d9e67745af1e7d1c5872f39db736d2c76dfe05 100644 (file)
@@ -126,47 +126,52 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
        chan->dma.cur += nr_dwords;
 }
 
-static inline bool
-READ_GET(struct nouveau_channel *chan, uint32_t *get)
+/* Fetch and adjust GPU GET pointer
+ *
+ * Returns:
+ *  value >= 0, the adjusted GET pointer
+ *  -EINVAL if GET pointer currently outside main push buffer
+ *  -EBUSY if timeout exceeded
+ */
+static inline int
+READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
 {
        uint32_t val;
 
        val = nvchan_rd32(chan, chan->user_get);
-       if (val < chan->pushbuf_base ||
-           val > chan->pushbuf_base + (chan->dma.max << 2)) {
-               /* meaningless to dma_wait() except to know whether the
-                * GPU has stalled or not
-                */
-               *get = val;
-               return false;
+
+       /* reset counter as long as GET is still advancing, this is
+        * to avoid misdetecting a GPU lockup if the GPU happens to
+        * just be processing an operation that takes a long time
+        */
+       if (val != *prev_get) {
+               *prev_get = val;
+               *timeout = 0;
+       }
+
+       if ((++*timeout & 0xff) == 0) {
+               DRM_UDELAY(1);
+               if (*timeout > 100000)
+                       return -EBUSY;
        }
 
-       *get = (val - chan->pushbuf_base) >> 2;
-       return true;
+       if (val < chan->pushbuf_base ||
+           val > chan->pushbuf_base + (chan->dma.max << 2))
+               return -EINVAL;
+
+       return (val - chan->pushbuf_base) >> 2;
 }
 
 int
 nouveau_dma_wait(struct nouveau_channel *chan, int size)
 {
-       uint32_t get, prev_get = 0, cnt = 0;
-       bool get_valid;
+       uint32_t prev_get = 0, cnt = 0;
+       int get;
 
        while (chan->dma.free < size) {
-               /* reset counter as long as GET is still advancing, this is
-                * to avoid misdetecting a GPU lockup if the GPU happens to
-                * just be processing an operation that takes a long time
-                */
-               get_valid = READ_GET(chan, &get);
-               if (get != prev_get) {
-                       prev_get = get;
-                       cnt = 0;
-               }
-
-               if ((++cnt & 0xff) == 0) {
-                       DRM_UDELAY(1);
-                       if (cnt > 100000)
-                               return -EBUSY;
-               }
+               get = READ_GET(chan, &prev_get, &cnt);
+               if (unlikely(get == -EBUSY))
+                       return -EBUSY;
 
                /* loop until we have a usable GET pointer.  the value
                 * we read from the GPU may be outside the main ring if
@@ -177,7 +182,7 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
                 * from the SKIPS area, so the code below doesn't have to deal
                 * with some fun corner cases.
                 */
-               if (!get_valid || get < NOUVEAU_DMA_SKIPS)
+               if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
                        continue;
 
                if (get <= chan->dma.cur) {
@@ -203,6 +208,19 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
                         * after processing the currently pending commands.
                         */
                        OUT_RING(chan, chan->pushbuf_base | 0x20000000);
+
+                       /* wait for GET to depart from the skips area.
+                        * prevents writing GET==PUT and causing a race
+                        * condition that causes us to think the GPU is
+                        * idle when it's not.
+                        */
+                       do {
+                               get = READ_GET(chan, &prev_get, &cnt);
+                               if (unlikely(get == -EBUSY))
+                                       return -EBUSY;
+                               if (unlikely(get == -EINVAL))
+                                       continue;
+                       } while (get <= NOUVEAU_DMA_SKIPS);
                        WRITE_PUT(NOUVEAU_DMA_SKIPS);
 
                        /* we're now submitting commands at the start of
index 9e2926c485790f376fce5af52c50cf93922df9f1..dd4937224220429e42fbf4c36e1da04c3fea5e41 100644 (file)
@@ -490,7 +490,8 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
                if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
                        NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
                                 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
-                       return -EBUSY;
+                       ret = -EBUSY;
+                       goto out;
                }
 
                udelay(400);
@@ -501,6 +502,11 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
                        break;
        }
 
+       if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
+               ret = -EREMOTEIO;
+               goto out;
+       }
+
        if (cmd & 1) {
                for (i = 0; i < 4; i++) {
                        data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
index 06eb993e08835a247aa8ea669ee41f718f0addd5..343ab7f17ccc7980667a8d5c807c678fa148c981 100644 (file)
@@ -71,6 +71,10 @@ MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
 int nouveau_uscript_tmds = -1;
 module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
 
+MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
+int nouveau_ignorelid = 0;
+module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
+
 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
                 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
                 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
index 026419fe8791e3cb941874398872ad23ef7ce811..6b9690418bc73bbf580b4f54f60bdc838be81fce 100644 (file)
@@ -509,6 +509,8 @@ struct drm_nouveau_private {
        void __iomem *ramin;
        uint32_t ramin_size;
 
+       struct nouveau_bo *vga_ram;
+
        struct workqueue_struct *wq;
        struct work_struct irq_work;
 
@@ -675,6 +677,7 @@ extern char *nouveau_tv_norm;
 extern int nouveau_reg_debug;
 extern char *nouveau_vbios;
 extern int nouveau_ctxfw;
+extern int nouveau_ignorelid;
 
 /* nouveau_state.c */
 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
index 2009db2426c3a87fa21be873a22001eed25e8c35..6ac804b0c9f9d3f909de248563eae3093476a67f 100644 (file)
@@ -321,6 +321,7 @@ retry:
                else {
                        NV_ERROR(dev, "invalid valid domains: 0x%08x\n",
                                 b->valid_domains);
+                       list_add_tail(&nvbo->entry, &op->both_list);
                        validate_fini(op, NULL);
                        return -EINVAL;
                }
@@ -466,13 +467,14 @@ u_memcpya(uint64_t user, unsigned nmemb, unsigned size)
 static int
 nouveau_gem_pushbuf_reloc_apply(struct nouveau_channel *chan, int nr_bo,
                                struct drm_nouveau_gem_pushbuf_bo *bo,
-                               int nr_relocs, uint64_t ptr_relocs,
-                               int nr_dwords, int first_dword,
+                               unsigned nr_relocs, uint64_t ptr_relocs,
+                               unsigned nr_dwords, unsigned first_dword,
                                uint32_t *pushbuf, bool is_iomem)
 {
        struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL;
        struct drm_device *dev = chan->dev;
-       int ret = 0, i;
+       int ret = 0;
+       unsigned i;
 
        reloc = u_memcpya(ptr_relocs, nr_relocs, sizeof(*reloc));
        if (IS_ERR(reloc))
@@ -667,6 +669,18 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data,
        }
        pbbo = nouveau_gem_object(gem);
 
+       if ((req->offset & 3) || req->nr_dwords < 2 ||
+           (unsigned long)req->offset > (unsigned long)pbbo->bo.mem.size ||
+           (unsigned long)req->nr_dwords >
+            ((unsigned long)(pbbo->bo.mem.size - req->offset ) >> 2)) {
+               NV_ERROR(dev, "pb call misaligned or out of bounds: "
+                             "%d + %d * 4 > %ld\n",
+                        req->offset, req->nr_dwords, pbbo->bo.mem.size);
+               ret = -EINVAL;
+               drm_gem_object_unreference(gem);
+               goto out;
+       }
+
        ret = ttm_bo_reserve(&pbbo->bo, false, false, true,
                             chan->fence.sequence);
        if (ret) {
index 919a619ca7fa376c70f0a935df029935203e924d..3b9bad66162ac211518c51a9c01404e26e4032d0 100644 (file)
@@ -483,6 +483,13 @@ nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
        if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
                if (nouveau_pgraph_intr_swmthd(dev, &trap))
                        unhandled = 1;
+       } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
+               uint32_t v = nv_rd32(dev, 0x402000);
+               nv_wr32(dev, 0x402000, v);
+
+               /* dump the error anyway for now: it's useful for
+                  Gallium development */
+               unhandled = 1;
        } else {
                unhandled = 1;
        }
index fb9bdd6edf1f66a417cd0d209c6b9ab5667c0fec..8f3a12f614ed27e4bcade0cd1f76863af59c8d48 100644 (file)
@@ -383,9 +383,8 @@ void nouveau_mem_close(struct drm_device *dev)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-       if (dev_priv->ttm.bdev.man[TTM_PL_PRIV0].has_type)
-               ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_PRIV0);
-       ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
+       nouveau_bo_unpin(dev_priv->vga_ram);
+       nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 
        ttm_bo_device_release(&dev_priv->ttm.bdev);
 
@@ -622,6 +621,15 @@ nouveau_mem_init(struct drm_device *dev)
                return ret;
        }
 
+       ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
+                            0, 0, true, true, &dev_priv->vga_ram);
+       if (ret == 0)
+               ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
+       if (ret) {
+               NV_WARN(dev, "failed to reserve VGA memory\n");
+               nouveau_bo_ref(NULL, &dev_priv->vga_ram);
+       }
+
        /* GART */
 #if !defined(__powerpc__) && !defined(__ia64__)
        if (drm_device_is_agp(dev) && dev->agp) {
@@ -653,6 +661,7 @@ nouveau_mem_init(struct drm_device *dev)
        dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1),
                                         drm_get_resource_len(dev, 1),
                                         DRM_MTRR_WC);
+
        return 0;
 }
 
index 09b9a46dfc0ec0337f1ecf60b04585b8fddddff4..f2d0187ba152fb8c7018b7c0d925c1cc60704cf6 100644 (file)
@@ -525,6 +525,7 @@ static void nouveau_card_takedown(struct drm_device *dev)
                engine->mc.takedown(dev);
 
                mutex_lock(&dev->struct_mutex);
+               ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
                ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
                mutex_unlock(&dev->struct_mutex);
                nouveau_sgdma_takedown(dev);
index a20c206625a2616f64b6601efa959ee4b9badd77..a3b9563a6f60c4f933cd9caf687da307eaac90ae 100644 (file)
@@ -30,7 +30,7 @@ nv04_instmem_determine_amount(struct drm_device *dev)
                 * of vram.  For now, only reserve a small piece until we know
                 * more about what each chipset requires.
                 */
-               switch (dev_priv->chipset & 0xf0) {
+               switch (dev_priv->chipset) {
                case 0x40:
                case 0x47:
                case 0x49:
index 118d3285fd8c9e95d74d1f8f5ffb0f52ef49a6ee..40b7360841f883ffc803161e0b4236512f16d215 100644 (file)
@@ -432,6 +432,7 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
        struct drm_device *dev = crtc->dev;
        struct drm_encoder *encoder;
+       uint32_t dac = 0, sor = 0;
 
        NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
 
@@ -439,9 +440,28 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
-               if (drm_helper_encoder_in_use(encoder))
+               if (!drm_helper_encoder_in_use(encoder))
                        continue;
 
+               if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
+                   nv_encoder->dcb->type == OUTPUT_TV)
+                       dac |= (1 << nv_encoder->or);
+               else
+                       sor |= (1 << nv_encoder->or);
+       }
+
+       list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+               struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+
+               if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
+                   nv_encoder->dcb->type == OUTPUT_TV) {
+                       if (dac & (1 << nv_encoder->or))
+                               continue;
+               } else {
+                       if (sor & (1 << nv_encoder->or))
+                               continue;
+               }
+
                nv_encoder->disconnect(nv_encoder);
        }
 
index 39caf167587d130ae4bf6346342818550c653f80..32b244bcb482e5e71535391c7afcc68a7d63c008 100644 (file)
@@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
                        return ret;
                ramfc = chan->ramfc->gpuobj;
 
-               ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256,
+               ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
                                             0, &chan->cache);
                if (ret)
                        return ret;
index ca79f32be44c13bcaba47e00f189b8e3067bbf55..20319e59d368ca1bf6b3e2368b97ccfd7e782f6b 100644 (file)
@@ -84,7 +84,7 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
        nv_wr32(dev, 0x400804, 0xc0000000);
        nv_wr32(dev, 0x406800, 0xc0000000);
        nv_wr32(dev, 0x400c04, 0xc0000000);
-       nv_wr32(dev, 0x401804, 0xc0000000);
+       nv_wr32(dev, 0x401800, 0xc0000000);
        nv_wr32(dev, 0x405018, 0xc0000000);
        nv_wr32(dev, 0x402000, 0xc0000000);
 
@@ -282,6 +282,7 @@ nv50_graph_unload_context(struct drm_device *dev)
                return 0;
        inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 
+       nouveau_wait_for_idle(dev);
        nv_wr32(dev, 0x400500, fifo & ~1);
        nv_wr32(dev, 0x400784, inst);
        nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
index e395c16d30f548c29fe848f380019bf8f946ba3b..ecf1936b822416f5b6606a39054717af3a440846 100644 (file)
@@ -90,11 +90,24 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
 {
        struct drm_device *dev = encoder->dev;
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+       struct drm_encoder *enc;
        uint32_t val;
        int or = nv_encoder->or;
 
        NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
 
+       nv_encoder->last_dpms = mode;
+       list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
+               struct nouveau_encoder *nvenc = nouveau_encoder(enc);
+
+               if (nvenc == nv_encoder ||
+                   nvenc->dcb->or != nv_encoder->dcb->or)
+                       continue;
+
+               if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
+                       return;
+       }
+
        /* wait for it to be done */
        if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or),
                     NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
index 388140a7e651d4224abc2bf9ebfe234dd0805299..e3b44562d2654f7ab2c29da917d50a864db736ef 100644 (file)
@@ -246,6 +246,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
                case ATOM_WS_ATTRIBUTES:
                        val = gctx->io_attr;
                        break;
+               case ATOM_WS_REGPTR:
+                       val = gctx->reg_block;
+                       break;
                default:
                        val = ctx->ws[idx];
                }
@@ -385,6 +388,32 @@ static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
        return atom_get_src_int(ctx, attr, ptr, NULL, 1);
 }
 
+static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
+{
+       uint32_t val = 0xCDCDCDCD;
+
+       switch (align) {
+       case ATOM_SRC_DWORD:
+               val = U32(*ptr);
+               (*ptr) += 4;
+               break;
+       case ATOM_SRC_WORD0:
+       case ATOM_SRC_WORD8:
+       case ATOM_SRC_WORD16:
+               val = U16(*ptr);
+               (*ptr) += 2;
+               break;
+       case ATOM_SRC_BYTE0:
+       case ATOM_SRC_BYTE8:
+       case ATOM_SRC_BYTE16:
+       case ATOM_SRC_BYTE24:
+               val = U8(*ptr);
+               (*ptr)++;
+               break;
+       }
+       return val;
+}
+
 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
                             int *ptr, uint32_t *saved, int print)
 {
@@ -482,6 +511,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
                case ATOM_WS_ATTRIBUTES:
                        gctx->io_attr = val;
                        break;
+               case ATOM_WS_REGPTR:
+                       gctx->reg_block = val;
+                       break;
                default:
                        ctx->ws[idx] = val;
                }
@@ -677,7 +709,7 @@ static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
        SDEBUG("   src1: ");
-       src1 = atom_get_src(ctx, attr, ptr);
+       src1 = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
        SDEBUG("   src2: ");
        src2 = atom_get_src(ctx, attr, ptr);
        dst &= src1;
@@ -809,6 +841,38 @@ static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
        SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
 }
 
+static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++), shift;
+       uint32_t saved, dst;
+       int dptr = *ptr;
+       attr &= 0x38;
+       attr |= atom_def_dst[attr >> 3] << 6;
+       SDEBUG("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
+       SDEBUG("   shift: %d\n", shift);
+       dst <<= shift;
+       SDEBUG("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++), shift;
+       uint32_t saved, dst;
+       int dptr = *ptr;
+       attr &= 0x38;
+       attr |= atom_def_dst[attr >> 3] << 6;
+       SDEBUG("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
+       SDEBUG("   shift: %d\n", shift);
+       dst >>= shift;
+       SDEBUG("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
 {
        uint8_t attr = U8((*ptr)++), shift;
@@ -818,7 +882,7 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
        attr |= atom_def_dst[attr >> 3] << 6;
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
-       shift = U8((*ptr)++);
+       shift = atom_get_src(ctx, attr, ptr);
        SDEBUG("   shift: %d\n", shift);
        dst <<= shift;
        SDEBUG("   dst: ");
@@ -834,7 +898,7 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
        attr |= atom_def_dst[attr >> 3] << 6;
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
-       shift = U8((*ptr)++);
+       shift = atom_get_src(ctx, attr, ptr);
        SDEBUG("   shift: %d\n", shift);
        dst >>= shift;
        SDEBUG("   dst: ");
@@ -937,18 +1001,18 @@ static struct {
        atom_op_or, ATOM_ARG_FB}, {
        atom_op_or, ATOM_ARG_PLL}, {
        atom_op_or, ATOM_ARG_MC}, {
-       atom_op_shl, ATOM_ARG_REG}, {
-       atom_op_shl, ATOM_ARG_PS}, {
-       atom_op_shl, ATOM_ARG_WS}, {
-       atom_op_shl, ATOM_ARG_FB}, {
-       atom_op_shl, ATOM_ARG_PLL}, {
-       atom_op_shl, ATOM_ARG_MC}, {
-       atom_op_shr, ATOM_ARG_REG}, {
-       atom_op_shr, ATOM_ARG_PS}, {
-       atom_op_shr, ATOM_ARG_WS}, {
-       atom_op_shr, ATOM_ARG_FB}, {
-       atom_op_shr, ATOM_ARG_PLL}, {
-       atom_op_shr, ATOM_ARG_MC}, {
+       atom_op_shift_left, ATOM_ARG_REG}, {
+       atom_op_shift_left, ATOM_ARG_PS}, {
+       atom_op_