default y
select HAVE_AOUT
select HAVE_IDE
+++++ +++++ select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_ATOMIC64 if (!CPU_32v6K)
select HAVE_KERNEL_LZMA
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
+++ +++++++ select HAVE_REGS_AND_STACK_ACCESS_API
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
help
Support for Intel's IXP4XX (XScale) family of processors.
----------config ARCH_L7200
---------- bool "LinkUp-L7200"
---------- select CPU_ARM720T
---------- select FIQ
---------- select ARCH_USES_GETTIMEOFFSET
---------- help
---------- Say Y here if you intend to run this kernel on a LinkUp Systems
---------- L7200 Software Development Board which uses an ARM720T processor.
---------- Information on this board can be obtained at:
----------
---------- <http://www.linkupsys.com/>
----------
---------- If you have any questions or comments about the Linux kernel port
---------- to this board, send e-mail to <sjhill@cotw.com>.
----------
config ARCH_DOVE
bool "Marvell Dove"
select PCI
config ARCH_LH7A40X
bool "Sharp LH7A40X"
select CPU_ARM922T
----- ----- select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
select ARCH_USES_GETTIMEOFFSET
help
default y
config CPU_HAS_PMU
--- - depends on CPU_V6 || CPU_V7 || XSCALE_PMU
+++ + depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
+++ + (!ARCH_OMAP3 || OMAP3_EMU)
default y
bool
source "arch/arm/common/Kconfig"
--- -------config FORCE_MAX_ZONEORDER
--- ------- int
--- ------- depends on SA1111
--- ------- default "9"
--- -------
menu "Bus support"
config ARM_AMBA
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
---------- REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
++++++++++ REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
++++++++++ ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
default y
---------- select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
++++++++++ select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
config HZ
int
---------- default 128 if ARCH_L7200
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
++++++++++ default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
default 100
config THUMB2_KERNEL
config ARCH_HAS_HOLES_MEMORYMODEL
bool
----- -----# Discontigmem is deprecated
----- -----config ARCH_DISCONTIGMEM_ENABLE
----- ----- bool
----- -----
config ARCH_SPARSEMEM_ENABLE
bool
def_bool ARCH_SPARSEMEM_ENABLE
config ARCH_SELECT_MEMORY_MODEL
----- ----- def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
----- -----
----- -----config NODES_SHIFT
----- ----- int
----- ----- default "4" if ARCH_LH7A40X
----- ----- default "2"
----- ----- depends on NEED_MULTIPLE_NODES
+++++ +++++ def_bool ARCH_SPARSEMEM_ENABLE
config HIGHMEM
bool "High Memory Support (EXPERIMENTAL)"
Enable hardware performance counter support for perf events. If
disabled, perf events will use software events only.
+++ +++++++config SPARSE_IRQ
+++ +++++++ bool "Support sparse irq numbering"
+++ +++++++ depends on EXPERIMENTAL
+++ +++++++ help
+++ +++++++ This enables support for sparse irqs. This is useful in general
+++ +++++++ as most CPUs have a fairly sparse array of IRQ vectors, which
+++ +++++++ the irq_desc then maps directly on to. Systems with a high
+++ +++++++ number of off-chip IRQs will want to treat this as
+++ +++++++ experimental until they have been independently verified.
+++ +++++++
+++ +++++++ If you don't know what to do here, say N.
+++ +++++++
source "mm/Kconfig"
+++ +++++++config FORCE_MAX_ZONEORDER
+++ +++++++ int "Maximum zone order" if ARCH_SHMOBILE
+++ +++++++ range 11 64 if ARCH_SHMOBILE
+++ +++++++ default "9" if SA1111
+++ +++++++ default "11"
+++ +++++++ help
+++ +++++++ The kernel memory allocator divides physically contiguous memory
+++ +++++++ blocks into "zones", where each zone is a power of two number of
+++ +++++++ pages. This option selects the largest power of two that the kernel
+++ +++++++ keeps in the memory allocator. If you need to allocate very large
+++ +++++++ blocks of physically contiguous memory, then you may need to
+++ +++++++ increase this value.
+++ +++++++
+++ +++++++ This config option is actually maximum order plus one. For example,
+++ +++++++ a value of 11 means that the largest free memory block is 2^10 pages.
+++ +++++++
config LEDS
bool "Timer and CPU usage LEDs"
depends on ARCH_CDB89712 || ARCH_EBSA110 || \
* by assembler code in head.S, head-common.S
*/
unsigned int nr; /* architecture number */
+++ +++++++ unsigned int nr_irqs; /* number of IRQs */
unsigned int phys_io; /* start of physical io */
unsigned int io_pg_offst; /* byte offset for io
* page tabe entry */
void (*fixup)(struct machine_desc *,
struct tag *, char **,
struct meminfo *);
+++++ +++++ void (*reserve)(void);/* reserve mem blocks */
void (*map_io)(void);/* IO mapping function */
void (*init_irq)(void);
struct sys_timer *timer; /* system tick timer */
#include <asm/thread_notify.h>
#include <asm/unwind.h>
#include <asm/unistd.h>
+++ +++++++#include <asm/tls.h>
#include "entry-header.S"
@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
@
stmia r5, {r0 - r4}
--- - -
--- - - asm_trace_hardirqs_off
.endm
.align 5
@
@ IRQs off again before pulling preserved data off the stack
@
--- - - disable_irq
+++ + + disable_irq_notrace
@
@ restore SPSR and restart the instruction
__irq_svc:
svc_entry
+++ + +#ifdef CONFIG_TRACE_IRQFLAGS
+++ + + bl trace_hardirqs_off
+++ + +#endif
#ifdef CONFIG_PREEMPT
get_thread_info tsk
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
@
@ IRQs off again before pulling preserved data off the stack
@
--- - -1: disable_irq
+++ + +1: disable_irq_notrace
@
@ restore SPSR and restart the instruction
@
@ IRQs off again before pulling preserved data off the stack
@
--- - - disable_irq
+++ + + disable_irq_notrace
@
@ restore SPSR and restart the instruction
@ Clear FP to mark the first stack frame
@
zero_fp
--- - -
--- - - asm_trace_hardirqs_off
.endm
.macro kuser_cmpxchg_check
THUMB( movne r0, #0 )
THUMB( strne r0, [r0] )
#endif
--- - -#ifdef CONFIG_TRACE_IRQFLAGS
--- - - bl trace_hardirqs_on
--- - -#endif
mov why, #0
b ret_to_user
#ifdef CONFIG_MMU
ldr r6, [r2, #TI_CPU_DOMAIN]
#endif
--- -------#if defined(CONFIG_HAS_TLS_REG)
--- ------- mcr p15, 0, r3, c13, c0, 3 @ set TLS register
--- -------#elif !defined(CONFIG_TLS_REG_EMUL)
--- ------- mov r4, #0xffff0fff
--- ------- str r3, [r4, #-15] @ TLS val at 0xffff0ff0
--- -------#endif
+++ +++++++ set_tls r3, r4, r5
#ifdef CONFIG_MMU
mcr p15, 0, r6, c3, c0, 0 @ Set domain register
#endif
*/
__kuser_get_tls: @ 0xffff0fe0
--- -------
--- -------#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
--- ------- ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
--- -------#else
--- ------- mrc p15, 0, r0, c13, c0, 3 @ read TLS register
--- -------#endif
+++ +++++++ ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
usr_ret lr
--- -------
--- ------- .rep 5
--- ------- .word 0 @ pad up to __kuser_helper_version
--- ------- .endr
+++ +++++++ mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
+++ +++++++ .rep 4
+++ +++++++ .word 0 @ 0xffff0ff0 software TLS value, then
+++ +++++++ .endr @ pad up to __kuser_helper_version
/*
* Reference declaration:
#include <linux/seq_file.h>
#include <linux/screen_info.h>
#include <linux/init.h>
+++ +++++++#include <linux/kexec.h>
+++ +++++++#include <linux/crash_dump.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <linux/fs.h>
#include <linux/proc_fs.h>
+++++ +++++#include <linux/memblock.h>
#include <asm/unified.h>
#include <asm/cpu.h>
extern struct proc_info_list *lookup_processor_type(unsigned int);
extern struct machine_desc *lookup_machine_type(unsigned int);
+++ +++++++static void __init feat_v6_fixup(void)
+++ +++++++{
+++ +++++++ int id = read_cpuid_id();
+++ +++++++
+++ +++++++ if ((id & 0xff0f0000) != 0x41070000)
+++ +++++++ return;
+++ +++++++
+++ +++++++ /*
+++ +++++++ * HWCAP_TLS is available only on 1136 r1p0 and later,
+++ +++++++ * see also kuser_get_tls_init.
+++ +++++++ */
+++ +++++++ if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
+++ +++++++ elf_hwcap &= ~HWCAP_TLS;
+++ +++++++}
+++ +++++++
static void __init setup_processor(void)
{
struct proc_info_list *list;
elf_hwcap &= ~HWCAP_THUMB;
#endif
+++ +++++++ feat_v6_fixup();
+++ +++++++
cacheid_init();
cpu_proc_init();
}
size -= start & ~PAGE_MASK;
bank->start = PAGE_ALIGN(start);
bank->size = size & PAGE_MASK;
----- ----- bank->node = PHYS_TO_NID(start);
/*
* Check whether this memory region has non-zero size or
* invalid node number.
*/
----- ----- if (bank->size == 0 || bank->node >= MAX_NUMNODES)
+++++ +++++ if (bank->size == 0)
return -EINVAL;
meminfo.nr_banks++;
}
arch_initcall(customize_machine);
+++ +++++++#ifdef CONFIG_KEXEC
+++ +++++++static inline unsigned long long get_total_mem(void)
+++ +++++++{
+++ +++++++ unsigned long total;
+++ +++++++
+++ +++++++ total = max_low_pfn - min_low_pfn;
+++ +++++++ return total << PAGE_SHIFT;
+++ +++++++}
+++ +++++++
+++ +++++++/**
+++ +++++++ * reserve_crashkernel() - reserves memory are for crash kernel
+++ +++++++ *
+++ +++++++ * This function reserves memory area given in "crashkernel=" kernel command
+++ +++++++ * line parameter. The memory reserved is used by a dump capture kernel when
+++ +++++++ * primary kernel is crashing.
+++ +++++++ */
+++ +++++++static void __init reserve_crashkernel(void)
+++ +++++++{
+++ +++++++ unsigned long long crash_size, crash_base;
+++ +++++++ unsigned long long total_mem;
+++ +++++++ int ret;
+++ +++++++
+++ +++++++ total_mem = get_total_mem();
+++ +++++++ ret = parse_crashkernel(boot_command_line, total_mem,
+++ +++++++ &crash_size, &crash_base);
+++ +++++++ if (ret)
+++ +++++++ return;
+++ +++++++
+++ +++++++ ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
+++ +++++++ if (ret < 0) {
+++ +++++++ printk(KERN_WARNING "crashkernel reservation failed - "
+++ +++++++ "memory is in use (0x%lx)\n", (unsigned long)crash_base);
+++ +++++++ return;
+++ +++++++ }
+++ +++++++
+++ +++++++ printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
+++ +++++++ "for crashkernel (System RAM: %ldMB)\n",
+++ +++++++ (unsigned long)(crash_size >> 20),
+++ +++++++ (unsigned long)(crash_base >> 20),
+++ +++++++ (unsigned long)(total_mem >> 20));
+++ +++++++
+++ +++++++ crashk_res.start = crash_base;
+++ +++++++ crashk_res.end = crash_base + crash_size - 1;
+++ +++++++ insert_resource(&iomem_resource, &crashk_res);
+++ +++++++}
+++ +++++++#else
+++ +++++++static inline void reserve_crashkernel(void) {}
+++ +++++++#endif /* CONFIG_KEXEC */
+++ +++++++
+++ +++++++/*
+++ +++++++ * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
+++ +++++++ * is_kdump_kernel() to determine if we are booting after a panic. Hence
+++ +++++++ * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
+++ +++++++ */
+++ +++++++
+++ +++++++#ifdef CONFIG_CRASH_DUMP
+++ +++++++/*
+++ +++++++ * elfcorehdr= specifies the location of elf core header stored by the crashed
+++ +++++++ * kernel. This option will be passed by kexec loader to the capture kernel.
+++ +++++++ */
+++ +++++++static int __init setup_elfcorehdr(char *arg)
+++ +++++++{
+++ +++++++ char *end;
+++ +++++++
+++ +++++++ if (!arg)
+++ +++++++ return -EINVAL;
+++ +++++++
+++ +++++++ elfcorehdr_addr = memparse(arg, &end);
+++ +++++++ return end > arg ? 0 : -EINVAL;
+++ +++++++}
+++ +++++++early_param("elfcorehdr", setup_elfcorehdr);
+++ +++++++#endif /* CONFIG_CRASH_DUMP */
+++ +++++++
void __init setup_arch(char **cmdline_p)
{
struct tag *tags = (struct tag *)&init_tags;
parse_early_param();
+++++ +++++ arm_memblock_init(&meminfo, mdesc);
+++++ +++++
paging_init(mdesc);
request_standard_resources(&meminfo, mdesc);
#ifdef CONFIG_SMP
smp_init_cpus();
#endif
+++ +++++++ reserve_crashkernel();
cpu_init();
tcm_init();
/*
* Set up various architecture-specific pointers
*/
+++ +++++++ arch_nr_irqs = mdesc->nr_irqs;
init_arch_irq = mdesc->init_irq;
system_timer = mdesc->timer;
init_machine = mdesc->init_machine;
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+++++ +++++#include <linux/memblock.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/termios.h>
#include <asm/system.h>
#include <asm/leds.h>
#include <asm/mach/time.h>
+++++ +++++#include <asm/pgtable.h>
static struct amba_pl010_data integrator_uart_data;
.rate = 14745600,
};
++++++++ ++static struct clk dummy_apb_pclk;
++++++++ ++
static struct clk_lookup lookups[] = {
-------- -- { /* UART0 */
++++++++ ++ { /* Bus clock */
++++++++ ++ .con_id = "apb_pclk",
++++++++ ++ .clk = &dummy_apb_pclk,
++++++++ ++ }, { /* UART0 */
.dev_id = "mb:16",
.clk = &uartclk,
}, { /* UART1 */
}
EXPORT_SYMBOL(cm_control);
+++++ +++++
+++++ +++++/*
+++++ +++++ * We need to stop things allocating the low memory; ideally we need a
+++++ +++++ * better implementation of GFP_DMA which does not assume that DMA-able
+++++ +++++ * memory starts at zero.
+++++ +++++ */
+++++ +++++void __init integrator_reserve(void)
+++++ +++++{
+++++ +++++ memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
+++++ +++++}
static struct pxamci_platform_data corgi_mci_platform_data = {
.detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
---------- .gpio_card_detect = -1,
++++++++++ .gpio_card_detect = CORGI_GPIO_nSD_DETECT,
.gpio_card_ro = CORGI_GPIO_nSD_WP,
.gpio_power = CORGI_GPIO_SD_PWR,
};
sharpsl_save_param();
mi->nr_banks=1;
mi->bank[0].start = 0xa0000000;
----- ----- mi->bank[0].node = 0;
if (machine_is_corgi())
mi->bank[0].size = (32*1024*1024);
else
/*
* Adjust the zones if there are restrictions for DMA access.
*/
----- -----void __init realview_adjust_zones(int node, unsigned long *size,
----- ----- unsigned long *hole)
+++++ +++++void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
{
unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
----- ----- if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
+++++ +++++ if (!machine_is_realview_pbx() || size[0] <= dma_size)
return;
size[ZONE_NORMAL] = size[0] - dma_size;
struct amba_device *adev = container_of(dev, struct amba_device, dev);
u32 mask;
++++++++++ if (machine_is_realview_pb1176()) {
++++++++++ static bool inserted = false;
++++++++++
++++++++++ /*
++++++++++ * The PB1176 does not have the status register,
++++++++++ * assume it is inserted at startup, then invert
++++++++++ * for each call so card insertion/removal will
++++++++++ * be detected anyway. This will not be called if
++++++++++ * GPIO on PL061 is active, which is the proper
++++++++++ * way to do this on the PB1176.
++++++++++ */
++++++++++ inserted = !inserted;
++++++++++ return inserted ? 0 : 1;
++++++++++ }
++++++++++
if (adev->res.start == REALVIEW_MMCI0_BASE)
mask = 1;
else
.rate = 24000000,
};
++++++++ ++static struct clk dummy_apb_pclk;
++++++++ ++
static struct clk_lookup lookups[] = {
-------- -- { /* UART0 */
++++++++ ++ { /* Bus clock */
++++++++ ++ .con_id = "apb_pclk",
++++++++ ++ .clk = &dummy_apb_pclk,
++++++++ ++ }, { /* UART0 */
.dev_id = "dev:uart0",
.clk = &ref24_clk,
}, { /* UART1 */
}, { /* UART3 */
.dev_id = "fpga:uart3",
.clk = &ref24_clk,
++++++++++ }, { /* UART3 is on the dev chip in PB1176 */
++++++++++ .dev_id = "dev:uart3",
++++++++++ .clk = &ref24_clk,
++++++++++ }, { /* UART4 only exists in PB1176 */
++++++++++ .dev_id = "fpga:uart4",
++++++++++ .clk = &ref24_clk,
}, { /* KMI0 */
.dev_id = "fpga:kmi0",
.clk = &ref24_clk,
}, { /* MMC0 */
.dev_id = "fpga:mmc0",
.clk = &ref24_clk,
---------- }, { /* EB:CLCD */
++++++++++ }, { /* CLCD is in the PB1176 and EB DevChip */
.dev_id = "dev:clcd",
.clk = &oscvco_clk,
}, { /* PB:CLCD */
.dev_id = "issp:clcd",
.clk = &oscvco_clk,
++++++++++ }, { /* SSP */
++++++++++ .dev_id = "dev:ssp0",
++++++++++ .clk = &ref24_clk,
}
};
return 0;
}
-------- --arch_initcall(clk_init);
++++++++ ++core_initcall(clk_init);
/*
* CLCD support.
#include <linux/amba/clcd.h>
#include <linux/amba/pl061.h>
#include <linux/amba/mmci.h>
++++++++++ #include <linux/amba/pl022.h>
#include <linux/io.h>
#include <linux/gfp.h>
.gpio_cd = -1,
};
++++++++++ static struct resource char_lcd_resources[] = {
++++++++++ {
++++++++++ .start = VERSATILE_CHAR_LCD_BASE,
++++++++++ .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
++++++++++ .flags = IORESOURCE_MEM,
++++++++++ },
++++++++++ };
++++++++++
++++++++++ static struct platform_device char_lcd_device = {
++++++++++ .name = "arm-charlcd",
++++++++++ .id = -1,
++++++++++ .num_resources = ARRAY_SIZE(char_lcd_resources),
++++++++++ .resource = char_lcd_resources,
++++++++++ };
++++++++++
/*
* Clock handling
*/
.rate = 24000000,
};
++++++++ ++static struct clk dummy_apb_pclk;
++++++++ ++
static struct clk_lookup lookups[] = {
-------- -- { /* UART0 */
++++++++ ++ { /* AMBA bus clock */
++++++++ ++ .con_id = "apb_pclk",
++++++++ ++ .clk = &dummy_apb_pclk,
++++++++ ++ }, { /* UART0 */
.dev_id = "dev:f1",
.clk = &ref24_clk,
}, { /* UART1 */
}, { /* MMC1 */
.dev_id = "fpga:0b",
.clk = &ref24_clk,
++++++++++ }, { /* SSP */
++++++++++ .dev_id = "dev:f4",
++++++++++ .clk = &ref24_clk,
}, { /* CLCD */
.dev_id = "dev:20",
.clk = &osc4_clk,
.irq_base = IRQ_GPIO1_START,
};
++++++++++ static struct pl022_ssp_controller ssp0_plat_data = {
++++++++++ .bus_id = 0,
++++++++++ .enable_dma = 0,
++++++++++ .num_chipselect = 1,
++++++++++ };
++++++++++
#define AACI_IRQ { IRQ_AACI, NO_IRQ }
#define AACI_DMA { 0x80, 0x81 }
#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
---------- AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
++++++++++ AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
static struct amba_device *amba_devs[] __initdata = {
&dmac_device,
platform_device_register(&versatile_flash_device);
platform_device_register(&versatile_i2c_device);
platform_device_register(&smc91x_device);
++++++++++ platform_device_register(&char_lcd_device);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
a few prototypes like that in existence) and therefore access to
that required register must be emulated.
--- -------config HAS_TLS_REG
--- ------- bool
--- ------- depends on !TLS_REG_EMUL
--- ------- default y if SMP || CPU_32v7
--- ------- help
--- ------- This selects support for the CP15 thread register.
--- ------- It is defined to be available on some ARMv6 processors (including
--- ------- all SMP capable ARMv6's) or later processors. User space may
--- ------- assume directly accessing that register and always obtain the
--- ------- expected value only on ARMv7 and above.
--- -------
config NEEDS_SYSCALL_FOR_CMPXCHG
bool
help
Forget about fast user space cmpxchg support.
It is just not possible.
+++ + config DMA_CACHE_RWFO
+++ + bool "Enable read/write for ownership DMA cache maintenance"
+++ + depends on CPU_V6 && SMP
+++ + default y
+++ + help
+++ + The Snoop Control Unit on ARM11MPCore does not detect the
+++ + cache maintenance operations and the dma_{map,unmap}_area()
+++ + functions may leave stale cache entries on other CPUs. By
+++ + enabling this option, Read or Write For Ownership in the ARMv6
+++ + DMA cache maintenance functions is performed. These LDR/STR
+++ + instructions change the cache line state to shared or modified
+++ + so that the cache operation has the desired effect.
+++ +
+++ + Note that the workaround is only valid on processors that do
+++ + not perform speculative loads into the D-cache. For such
+++ + processors, if cache maintenance operations are not broadcast
+++ + in hardware, other workarounds are needed (e.g. cache
+++ + maintenance broadcasting in software via FIQ).
+++ +
config OUTER_CACHE
bool
config ARM_DMA_MEM_BUFFERABLE
bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+++ + depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+++ + MACH_REALVIEW_PB11MP)
default y if CPU_V6 || CPU_V7
help
Historically, the kernel has used strongly ordered mappings to
git.samba.org / sfrench / cifs-2.6.git / commitdiff