Merge tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
authorLinus Torvalds <torvalds@linux-foundation.org>
Tue, 23 Oct 2018 07:40:16 +0000 (08:40 +0100)
committerLinus Torvalds <torvalds@linux-foundation.org>
Tue, 23 Oct 2018 07:40:16 +0000 (08:40 +0100)
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.20 series:

  There were no significant changes to the core this time! Bur the new
  Qualcomm, Mediatek and Broadcom drivers are quite interesting as they
  will be used in a few million embedded devices the coming years as it
  seems.

  New drivers:

   - Broadcom Northstar pin control driver.

   - Mediatek MT8183 subdriver.

   - Mediatek MT7623 subdriver.

   - Mediatek MT6765 subdriver.

   - Meson g12a subdriver.

   - Nuvoton NPCM7xx pin control and GPIO driver.

   - Qualcomm QCS404 pin control and GPIO subdriver.

   - Qualcomm SDM660 pin control and GPIO subdriver.

   - Renesas R8A7744 PFC subdriver.

   - Renesas R8A774C0 PFC subdriver.

   - Renesas RZ/N1 pinctrl driver

  Major improvements:

   - Pulled the GPIO support for Ingenic over from the GPIO subsystem
     and consolidated it all in the Ingenic pin control driver.

   - Major cleanups and consolidation work in all Intel drivers.

   - Major cleanups and consolidation work in all Mediatek drivers.

   - Lots of incremental improvements to the Renesas PFC pin controller
     family.

   - All drivers doing GPIO now include <linux/gpio/driver.h> and
     nothing else"

* tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
  pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'
  gpio: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
  pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
  dt-bindings: pinctrl: bcm4708-pinmux: improve example binding
  pinctrl: geminilake: Sort register offsets by value
  pinctrl: geminilake: Get rid of unneeded ->probe() stub
  pinctrl: geminilake: Update pin list for B0 stepping
  pinctrl: renesas: Fix platform_no_drv_owner.cocci warnings
  pinctrl: mediatek: Make eint_m u16
  pinctrl: bcm: ns: Use uintptr_t for casting data
  pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_mux
  pinctrl: gemini: Fix up TVC clock group
  pinctrl: gemini: Drop noisy debug prints
  pinctrl: gemini: Mask and set properly
  pinctrl: mediatek: select GPIOLIB
  pinctrl: rza1: don't manually release devm managed resources
  MAINTAINERS: update entry for Mediatek pin controller
  pinctrl: bcm: add Northstar driver
  dt-bindings: pinctrl: document Broadcom Northstar pin mux controller
  pinctrl: qcom: fix 'const' pointer handling
  ...

150 files changed:
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt [deleted file]
Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt [new file with mode: 0644]
MAINTAINERS
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/gpio-ingenic.c [deleted file]
drivers/gpio/gpio-uniphier.c
drivers/pinctrl/Kconfig
drivers/pinctrl/Makefile
drivers/pinctrl/aspeed/pinctrl-aspeed.c
drivers/pinctrl/bcm/Kconfig
drivers/pinctrl/bcm/Makefile
drivers/pinctrl/bcm/pinctrl-ns.c [new file with mode: 0644]
drivers/pinctrl/berlin/berlin.c
drivers/pinctrl/cirrus/pinctrl-madera-core.c
drivers/pinctrl/core.c
drivers/pinctrl/freescale/pinctrl-imx.c
drivers/pinctrl/freescale/pinctrl-imx1-core.c
drivers/pinctrl/freescale/pinctrl-mxs.c
drivers/pinctrl/intel/pinctrl-baytrail.c
drivers/pinctrl/intel/pinctrl-broxton.c
drivers/pinctrl/intel/pinctrl-cannonlake.c
drivers/pinctrl/intel/pinctrl-cedarfork.c
drivers/pinctrl/intel/pinctrl-cherryview.c
drivers/pinctrl/intel/pinctrl-denverton.c
drivers/pinctrl/intel/pinctrl-geminilake.c
drivers/pinctrl/intel/pinctrl-icelake.c
drivers/pinctrl/intel/pinctrl-intel.c
drivers/pinctrl/intel/pinctrl-intel.h
drivers/pinctrl/intel/pinctrl-lewisburg.c
drivers/pinctrl/intel/pinctrl-merrifield.c
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
drivers/pinctrl/mediatek/Kconfig
drivers/pinctrl/mediatek/Makefile
drivers/pinctrl/mediatek/mtk-eint.c
drivers/pinctrl/mediatek/mtk-eint.h
drivers/pinctrl/mediatek/pinctrl-moore.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-moore.h [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mt6765.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mt7622.c
drivers/pinctrl/mediatek/pinctrl-mt7623.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mt8183.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-paris.c [new file with mode: 0644]
drivers/pinctrl/mediatek/pinctrl-paris.h [new file with mode: 0644]
drivers/pinctrl/meson/Kconfig
drivers/pinctrl/meson/Makefile
drivers/pinctrl/meson/pinctrl-meson-g12a.c [new file with mode: 0644]
drivers/pinctrl/meson/pinctrl-meson.c
drivers/pinctrl/meson/pinctrl-meson.h
drivers/pinctrl/mvebu/pinctrl-mvebu.c
drivers/pinctrl/nomadik/pinctrl-ab8500.c
drivers/pinctrl/nomadik/pinctrl-ab8505.c
drivers/pinctrl/nomadik/pinctrl-abx500.c
drivers/pinctrl/nomadik/pinctrl-nomadik.c
drivers/pinctrl/nuvoton/Kconfig [new file with mode: 0644]
drivers/pinctrl/nuvoton/Makefile [new file with mode: 0644]
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-amd.c
drivers/pinctrl/pinctrl-as3722.c
drivers/pinctrl/pinctrl-at91-pio4.c
drivers/pinctrl/pinctrl-at91.c
drivers/pinctrl/pinctrl-coh901.c
drivers/pinctrl/pinctrl-digicolor.c
drivers/pinctrl/pinctrl-falcon.c
drivers/pinctrl/pinctrl-gemini.c
drivers/pinctrl/pinctrl-ingenic.c
drivers/pinctrl/pinctrl-lantiq.c
drivers/pinctrl/pinctrl-lpc18xx.c
drivers/pinctrl/pinctrl-mcp23s08.c
drivers/pinctrl/pinctrl-pistachio.c
drivers/pinctrl/pinctrl-rockchip.c
drivers/pinctrl/pinctrl-rza1.c
drivers/pinctrl/pinctrl-rzn1.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-single.c
drivers/pinctrl/pinctrl-st.c
drivers/pinctrl/qcom/Kconfig
drivers/pinctrl/qcom/Makefile
drivers/pinctrl/qcom/pinctrl-msm.c
drivers/pinctrl/qcom/pinctrl-msm.h
drivers/pinctrl/qcom/pinctrl-qcs404.c [new file with mode: 0644]
drivers/pinctrl/qcom/pinctrl-sdm660.c [new file with mode: 0644]
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
drivers/pinctrl/samsung/pinctrl-samsung.c
drivers/pinctrl/samsung/pinctrl-samsung.h
drivers/pinctrl/sh-pfc/Kconfig
drivers/pinctrl/sh-pfc/Makefile
drivers/pinctrl/sh-pfc/core.c
drivers/pinctrl/sh-pfc/core.h
drivers/pinctrl/sh-pfc/gpio.c
drivers/pinctrl/sh-pfc/pfc-emev2.c
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
drivers/pinctrl/sh-pfc/pfc-sh7203.c
drivers/pinctrl/sh-pfc/pfc-sh7264.c
drivers/pinctrl/sh-pfc/pfc-sh7269.c
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
drivers/pinctrl/sh-pfc/pfc-sh7720.c
drivers/pinctrl/sh-pfc/pfc-sh7723.c
drivers/pinctrl/sh-pfc/pfc-sh7724.c
drivers/pinctrl/sh-pfc/pfc-sh7734.c
drivers/pinctrl/sh-pfc/pfc-sh7757.c
drivers/pinctrl/sh-pfc/pfc-sh7785.c
drivers/pinctrl/sh-pfc/pfc-sh7786.c
drivers/pinctrl/sh-pfc/pfc-shx3.c
drivers/pinctrl/sh-pfc/pinctrl.c
drivers/pinctrl/sh-pfc/sh_pfc.h
drivers/pinctrl/sirf/pinctrl-atlas7.c
drivers/pinctrl/sirf/pinctrl-sirf.c
drivers/pinctrl/spear/pinctrl-spear.h
drivers/pinctrl/sprd/pinctrl-sprd.c
drivers/pinctrl/stm32/pinctrl-stm32.c
drivers/pinctrl/sunxi/pinctrl-sunxi.c
drivers/pinctrl/tegra/pinctrl-tegra.c
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
drivers/pinctrl/uniphier/pinctrl-uniphier.h
drivers/pinctrl/vt8500/pinctrl-wmt.c
drivers/pinctrl/vt8500/pinctrl-wmt.h
include/dt-bindings/gpio/meson-g12a-gpio.h [new file with mode: 0644]
include/dt-bindings/pinctrl/rzn1-pinctrl.h [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt b/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
deleted file mode 100644 (file)
index 7988aeb..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-Ingenic jz47xx GPIO controller
-
-That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
-driver node.
-
-Required properties:
---------------------
-
- - compatible: Must contain one of:
-    - "ingenic,jz4740-gpio"
-    - "ingenic,jz4770-gpio"
-    - "ingenic,jz4780-gpio"
- - reg: The GPIO bank number.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - interrupts: Interrupt specifier for the controllers interrupt.
- - #interrupt-cells: Should be 2. Refer to
-   ../interrupt-controller/interrupts.txt for more details.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
-    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
-    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
-   'gpio.txt' in this directory for more details.
-
-Example:
---------
-
-&pinctrl {
-       #address-cells = <1>;
-       #size-cells = <0>;
-
-       gpa: gpio@0 {
-               compatible = "ingenic,jz4740-gpio";
-               reg = <0>;
-
-               gpio-controller;
-               gpio-ranges = <&pinctrl 0 0 32>;
-               #gpio-cells = <2>;
-
-               interrupt-controller;
-               #interrupt-cells = <2>;
-
-               interrupt-parent = <&intc>;
-               interrupts = <28>;
-       };
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt
new file mode 100644 (file)
index 0000000..4fa9539
--- /dev/null
@@ -0,0 +1,57 @@
+Broadcom Northstar pins mux controller
+
+Some of Northstar SoCs's pins can be used for various purposes thanks to the mux
+controller. This binding allows describing mux controller and listing available
+functions. They can be referenced later by other bindings to let system
+configure controller correctly.
+
+A list of pins varies across chipsets so few bindings are available.
+
+Required properties:
+- compatible: must be one of:
+       "brcm,bcm4708-pinmux"
+       "brcm,bcm4709-pinmux"
+       "brcm,bcm53012-pinmux"
+- reg: iomem address range of CRU (Central Resource Unit) pin registers
+- reg-names: "cru_gpio_control" - the only needed & supported reg right now
+
+Functions and their groups available for all chipsets:
+- "spi": "spi_grp"
+- "i2c": "i2c_grp"
+- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
+- "uart1": "uart1_grp"
+
+Additionally available on BCM4709 and BCM53012:
+- "mdio": "mdio_grp"
+- "uart2": "uart2_grp"
+- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
+
+For documentation of subnodes see:
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+Example:
+       dmu@1800c000 {
+               compatible = "simple-bus";
+               ranges = <0 0x1800c000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               cru@100 {
+                       compatible = "simple-bus";
+                       reg = <0x100 0x1a4>;
+                       ranges;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       pin-controller@1c0 {
+                               compatible = "brcm,bcm4708-pinmux";
+                               reg = <0x1c0 0x24>;
+                               reg-names = "cru_gpio_control";
+
+                               spi-pins {
+                                       function = "spi";
+                                       groups = "spi_grp";
+                               };
+                       };
+               };
+       };
index ca313a7aeaff67837d551e77b04edaabbfbf1ac7..af20b0ec715c8cd32260fc193b9047f266cc307e 100644 (file)
@@ -20,16 +20,30 @@ Required properties:
 
  - compatible: One of:
     - "ingenic,jz4740-pinctrl"
+    - "ingenic,jz4725b-pinctrl"
     - "ingenic,jz4770-pinctrl"
     - "ingenic,jz4780-pinctrl"
  - reg: Address range of the pinctrl registers.
 
 
-GPIO sub-nodes
---------------
+Required properties for sub-nodes (GPIO chips):
+-----------------------------------------------
 
-The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
-please refer to ../gpio/ingenic,gpio.txt.
+ - compatible: Must contain one of:
+    - "ingenic,jz4740-gpio"
+    - "ingenic,jz4770-gpio"
+    - "ingenic,jz4780-gpio"
+ - reg: The GPIO bank number.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - interrupts: Interrupt specifier for the controllers interrupt.
+ - #interrupt-cells: Should be 2. Refer to
+   ../interrupt-controller/interrupts.txt for more details.
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+ - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
+   ../gpio/gpio.txt for more details.
 
 
 Example:
@@ -38,4 +52,21 @@ Example:
 pinctrl: pin-controller@10010000 {
        compatible = "ingenic,jz4740-pinctrl";
        reg = <0x10010000 0x400>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       gpa: gpio@0 {
+               compatible = "ingenic,jz4740-gpio";
+               reg = <0>;
+
+               gpio-controller;
+               gpio-ranges = <&pinctrl 0 0 32>;
+               #gpio-cells = <2>;
+
+               interrupt-controller;
+               #interrupt-cells = <2>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <28>;
+       };
 };
index 54ecb8ab778836e7c6d6b95641b64a01d0ca3485..82ead40311f62ee1c6cb5009cefe9328e5869595 100644 (file)
@@ -13,6 +13,8 @@ Required properties for the root node:
                      "amlogic,meson-gxl-aobus-pinctrl"
                      "amlogic,meson-axg-periphs-pinctrl"
                      "amlogic,meson-axg-aobus-pinctrl"
+                     "amlogic,meson-g12a-periphs-pinctrl"
+                     "amlogic,meson-g12a-aobus-pinctrl"
  - reg: address and size of registers controlling irq functionality
 
 === GPIO sub-nodes ===
diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644 (file)
index 0000000..83f4bba
--- /dev/null
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells   : should be 1.
+- compatible    : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges        : defines mapping ranges between pin controller node (parent)
+                       to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg                  : specifies physical base address and size of the GPIO
+                               bank registers.
+- gpio-controller      : Marks the device node as a GPIO controller.
+- #gpio-cells          : Must be <2>. The first cell is the gpio pin number
+                               and the second cell is used for optional parameters.
+- interrupts           : contain the GPIO bank interrupt with flags for falling edge.
+- gpio-ranges          : defines the range of pins managed by the GPIO bank controller.
+
+For example, GPIO bank subnodes like the following:
+       gpio0: gpio@f0010000 {
+               gpio-controller;
+               #gpio-cells = <2>;
+               reg = <0x0 0x80>;
+               interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+               gpio-ranges = <&pinctrl 0 0 32>;
+       };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+       An array of strings, each string containing the name of a pin.
+       These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+       "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+       "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL", "GPIO6/IOX2CK/SMB2DSDA",
+       "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2", "GPIO10/IOXHLD",
+       "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+       "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+       "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA", "GPIO19/PSPI2CK/SMB4BSCL",
+       "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL", "GPIO22/SMB4DSDA/SMB14SDA",
+       "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI", "GPIO26/SMB5SDA",
+       "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+       "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3", "GPIO37/SMB3CSDA",
+       "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL", "GPIO41/BSPRXD",
+       "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD", "GPIO44/nCTS1/JTDI2/BU1CTS",
+       "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+       "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2", "GPO51/nRTS2/STRAP2",
+       "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2", "GPIO55/nRI2",
+       "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+       "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+       "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+       "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6", "GPIO71/FANIN7",
+       "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+       "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+       "GPIO80/PWM0", "GPIO81/PWM1", "GPIO82/PWM2", "GPIO83/PWM3", "GPIO84/R2TXD0",
+       "GPIO85/R2TXD1", "GPIO86/R2TXEN", "GPIO87/R2RXD0", "GPIO88/R2RXD1", "GPIO89/R2CRSDV",
+       "GPIO90/R2RXERR", "GPIO91/R2MDC", "GPIO92/R2MDIO", "GPIO93/GA20/SMB5DSCL",
+       "GPIO94/nKBRST/SMB5DSDA", "GPIO95/nLRESET/nESPIRST", "GPIO96/RG1TXD0",
+       "GPIO97/RG1TXD1", "GPIO98/RG1TXD2", "GPIO99/RG1TXD3","GPIO100/RG1TXC",
+       "GPIO101/RG1TXCTL", "GPIO102/RG1RXD0", "GPIO103/RG1RXD1", "GPIO104/RG1RXD2",
+       "GPIO105/RG1RXD3", "GPIO106/RG1RXC", "GPIO107/RG1RXCTL", "GPIO108/RG1MDC",
+       "GPIO109/RG1MDIO", "GPIO110/RG2TXD0/DDRV0", "GPIO111/RG2TXD1/DDRV1",
+       "GPIO112/RG2TXD2/DDRV2", "GPIO113/RG2TXD3/DDRV3", "GPIO114/SMB0SCL",
+       "GPIO115/SMB0SDA", "GPIO116/SMB1SCL", "GPIO117/SMB1SDA", "GPIO118/SMB2SCL",
+       "GPIO119/SMB2SDA", "GPIO120/SMB2CSDA", "GPIO121/SMB2CSCL", "GPIO122/SMB2BSDA",
+       "GPIO123/SMB2BSCL", "GPIO124/SMB1CSDA", "GPIO125/SMB1CSCL","GPIO126/SMB1BSDA",
+       "GPIO127/SMB1BSCL", "GPIO128/SMB8SCL", "GPIO129/SMB8SDA", "GPIO130/SMB9SCL",
+       "GPIO131/SMB9SDA", "GPIO132/SMB10SCL", "GPIO133/SMB10SDA","GPIO134/SMB11SCL",
+       "GPIO135/SMB11SDA", "GPIO136/SD1DT0", "GPIO137/SD1DT1", "GPIO138/SD1DT2",
+       "GPIO139/SD1DT3", "GPIO140/SD1CLK", "GPIO141/SD1WP", "GPIO142/SD1CMD",
+       "GPIO143/SD1CD/SD1PWR", "GPIO144/PWM4", "GPIO145/PWM5", "GPIO146/PWM6",
+       "GPIO147/PWM7", "GPIO148/MMCDT4", "GPIO149/MMCDT5", "GPIO150/MMCDT6",
+       "GPIO151/MMCDT7", "GPIO152/MMCCLK", "GPIO153/MMCWP", "GPIO154/MMCCMD",
+       "GPIO155/nMMCCD/nMMCRST", "GPIO156/MMCDT0", "GPIO157/MMCDT1", "GPIO158/MMCDT2",
+       "GPIO159/MMCDT3", "GPIO160/CLKOUT/RNGOSCOUT", "GPIO161/nLFRAME/nESPICS",
+       "GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0",
+       "GPIO165/LAD1/ESPI_IO1", "GPIO166/LAD2/ESPI_IO2", "GPIO167/LAD3/ESPI_IO3",
+       "GPIO168/nCLKRUN/nESPIALERT", "GPIO169/nSCIPME", "GPIO170/nSMI", "GPIO171/SMB6SCL",
+       "GPIO172/SMB6SDA", "GPIO173/SMB7SCL", "GPIO174/SMB7SDA", "GPIO175/PSPI1CK/FANIN19",
+       "GPIO176/PSPI1DO/FANIN18", "GPIO177/PSPI1DI/FANIN17", "GPIO178/R1TXD0",
+       "GPIO179/R1TXD1", "GPIO180/R1TXEN", "GPIO181/R1RXD0", "GPIO182/R1RXD1",
+       "GPIO183/SPI3CK", "GPO184/SPI3D0/STRAP9", "GPO185/SPI3D1/STRAP10",
+       "GPIO186/nSPI3CS0", "GPIO187/nSPI3CS1", "GPIO188/SPI3D2/nSPI3CS2",
+       "GPIO189/SPI3D3/nSPI3CS3", "GPIO190/nPRD_SMI", "GPIO191", "GPIO192", "GPIO193/R1CRSDV",
+       "GPIO194/SMB0BSCL", "GPIO195/SMB0BSDA", "GPIO196/SMB0CSCL", "GPIO197/SMB0DEN",
+       "GPIO198/SMB0DSDA", "GPIO199/SMB0DSCL", "GPIO200/R2CK", "GPIO201/R1CK",
+       "GPIO202/SMB0CSDA", "GPIO203/FANIN16", "GPIO204/DDC2SCL", "GPIO205/DDC2SDA",
+       "GPIO206/HSYNC2", "GPIO207/VSYNC2", "GPIO208/RG2TXC/DVCK", "GPIO209/RG2TXCTL/DDRV4",
+       "GPIO210/RG2RXD0/DDRV5", "GPIO211/RG2RXD1/DDRV6", "GPIO212/RG2RXD2/DDRV7",
+       "GPIO213/RG2RXD3/DDRV8", "GPIO214/RG2RXC/DDRV9", "GPIO215/RG2RXCTL/DDRV10",
+       "GPIO216/RG2MDC/DDRV11", "GPIO217/RG2MDIO/DVHSYNC", "GPIO218/nWDO1",
+       "GPIO219/nWDO2", "GPIO220/SMB12SCL", "GPIO221/SMB12SDA", "GPIO222/SMB13SCL",
+       "GPIO223/SMB13SDA", "GPIO224/SPIXCK", "GPO225/SPIXD0/STRAP12", "GPO226/SPIXD1/STRAP13",
+       "GPIO227/nSPIXCS0", "GPIO228/nSPIXCS1", "GPO229/SPIXD2/STRAP3", "GPIO230/SPIXD3",
+       "GPIO231/nCLKREQ", "GPI255/DACOSEL"
+
+Optional Properties:
+ bias-disable, bias-pull-down, bias-pull-up, input-enable,
+ input-disable, output-high, output-low, drive-push-pull,
+ drive-open-drain, input-debounce, slew-rate, drive-strength
+
+ slew-rate valid arguments are:
+                               <0> - slow
+                               <1> - fast
+ drive-strength valid arguments are:
+                               <2> - 2mA
+                               <4> - 4mA
+                               <8> - 8mA
+                               <12> - 12mA
+                               <16> - 16mA
+                               <24> - 24mA
+
+For example, pinctrl might have pinmux subnodes like the following:
+
+       gpio0_iox1d1_pin: gpio0-iox1d1-pin {
+               pins = "GPIO0/IOX1DI";
+               output-high;
+       };
+       gpio0_iox1ck_pin: gpio0-iox1ck-pin {
+               pins = "GPIO2/IOX1CK";
+               output_high;
+       };
+
+=== Pin Group Subnode ===
+
+Required pin group subnode-properties:
+- groups : A string containing the name of the group to mux.
+- function: A string containing the name of the function to mux to the
+  group.
+
+The following are the list of the available groups and functions :
+       smb0, smb0b, smb0c, smb0d, smb0den, smb1, smb1b, smb1c, smb1d,
+       smb2, smb2b, smb2c, smb2d, smb3, smb3b, smb3c, smb3d, smb4, smb4b,
+       smb4c, smb4d, smb4den, smb5, smb5b, smb5c, smb5d, ga20kbc, smb6,
+       smb7, smb8, smb9, smb10, smb11, smb12, smb13, smb14, smb15, fanin0,
+       fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8,
+       fanin9, fanin10, fanin11 fanin12 fanin13, fanin14, fanin15, faninx,
+       pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, rg1, rg1mdio, rg2,
+       rg2mdio, ddr, uart1, uart2, bmcuart0a, bmcuart0b, bmcuart1, iox1,
+       iox2, ioxh, gspi, mmc, mmcwp, mmccd, mmcrst, mmc8, r1, r1err, r1md,
+       r2, r2err, r2md, sd1, sd1pwr, wdog1, wdog2, scipme, sci, serirq,
+       jtag2, spix, spixcs1, pspi1, pspi2, ddc, clkreq, clkout, spi3, spi3cs1,
+       spi3quad, spi3cs2, spi3cs3, spi0cs1, lpc, lpcclk, espi, lkgpo0, lkgpo1,
+       lkgpo2, nprd_smi
+
+For example, pinctrl might have group subnodes like the following:
+       r1err_pins: r1err-pins {
+               groups = "r1err";
+               function = "r1err";
+       };
+       r1md_pins: r1md-pins {
+               groups = "r1md";
+               function = "r1md";
+       };
+       r1_pins: r1-pins {
+               groups = "r1";
+               function = "r1";
+       };
+
+Examples
+========
+pinctrl: pinctrl@f0800000 {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "nuvoton,npcm750-pinctrl";
+       ranges = <0 0xf0010000 0x8000>;
+
+       gpio0: gpio@f0010000 {
+               gpio-controller;
+               #gpio-cells = <2>;
+               reg = <0x0 0x80>;
+               interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+               gpio-ranges = <&pinctrl 0 0 32>;
+       };
+
+       ....
+
+       gpio7: gpio@f0017000 {
+               gpio-controller;
+               #gpio-cells = <2>;
+               reg = <0x7000 0x80>;
+               interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+               gpio-ranges = <&pinctrl 0 224 32>;
+       };
+
+       gpio0_iox1d1_pin: gpio0-iox1d1-pin {
+               pins = "GPIO0/IOX1DI";
+               output-high;
+       };
+
+       iox1_pins: iox1-pins {
+               groups = "iox1";
+               function = "iox1";
+       };
+       iox2_pins: iox2-pins {
+               groups = "iox2";
+               function = "iox2";
+       };
+
+       ....
+
+       clkreq_pins: clkreq-pins {
+               groups = "clkreq";
+               function = "clkreq";
+       };
+};
\ No newline at end of file
index ffd4345415f3288eff7920315115a54508cfe02e..ab4000eab07dfdbbeb76614a33d007c0a074a7d5 100644 (file)
@@ -19,6 +19,7 @@ PMIC's from Qualcomm.
                    "qcom,pm8998-gpio"
                    "qcom,pma8084-gpio"
                    "qcom,pmi8994-gpio"
+                   "qcom,pms405-gpio"
 
                    And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
                    if the device is on an spmi bus or an ssbi bus respectively
@@ -91,6 +92,7 @@ to specify in a pin configuration subnode:
                    gpio1-gpio26 for pm8998
                    gpio1-gpio22 for pma8084
                    gpio1-gpio10 for pmi8994
+                   gpio1-gpio11 for pms405
 
 - function:
        Usage: required
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt
new file mode 100644 (file)
index 0000000..2b8f777
--- /dev/null
@@ -0,0 +1,199 @@
+Qualcomm QCS404 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+QCS404 platform.
+
+- compatible:
+       Usage: required
+       Value type: <string>
+       Definition: must be "qcom,qcs404-pinctrl"
+
+- reg:
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: the base address and size of the north, south and east TLMM
+                   tiles.
+
+- reg-names:
+       Usage: required
+       Value type: <stringlist>
+       Defintiion: names for the cells of reg, must contain "north", "south"
+                   and "east".
+
+- interrupts:
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+       Usage: required
+       Value type: <none>
+       Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+       Usage: required
+       Value type: <u32>
+       Definition: must be 2. Specifying the pin number and flags, as defined
+                   in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+       Usage: required
+       Value type: <none>
+       Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+       Usage: required
+       Value type: <u32>
+       Definition: must be 2. Specifying the pin number and flags, as defined
+                   in <dt-bindings/gpio/gpio.h>
+
+- gpio-ranges:
+       Usage: required
+       Definition:  see ../gpio/gpio.txt
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+       Usage: required
+       Value type: <string-array>
+       Definition: List of gpio pins affected by the properties specified in
+                   this subnode.
+
+                   Valid pins are:
+                     gpio0-gpio119
+                       Supports mux, bias and drive-strength
+
+                     sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
+                     sdc2_data
+                       Supports bias and drive-strength
+
+                     ufs_reset
+                       Supports bias and drive-strength
+
+- function:
+       Usage: required
+       Value type: <string>
+       Definition: Specify the alternative function to be configured for the
+                   specified pins. Functions are only valid for gpio pins.
+                   Valid values are:
+
+                   gpio, hdmi_tx, hdmi_ddc, blsp_uart_tx_a2, blsp_spi2, m_voc,
+                   qdss_cti_trig_in_a0, blsp_uart_rx_a2, qdss_tracectl_a,
+                   blsp_uart2, aud_cdc, blsp_i2c_sda_a2, qdss_tracedata_a,
+                   blsp_i2c_scl_a2, qdss_tracectl_b, qdss_cti_trig_in_b0,
+                   blsp_uart1, blsp_spi_mosi_a1, blsp_spi_miso_a1,
+                   qdss_tracedata_b, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest,
+                   blsp_spi_clk_a1, rgb_data0, blsp_uart5, blsp_spi5,
+                   adsp_ext, rgb_data1, prng_rosc, rgb_data2, blsp_i2c5,
+                   gcc_gp1_clk_b, rgb_data3, gcc_gp2_clk_b, blsp_spi0,
+                   blsp_uart0, gcc_gp3_clk_b, blsp_i2c0, qdss_traceclk_b,
+                   pcie_clk, nfc_irq, blsp_spi4, nfc_dwl, audio_ts, rgb_data4,
+                   spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, rgb_data5,
+                   blsp_uart_rx_b2, blsp_i2c_sda_b2, blsp_i2c_scl_b2,
+                   pwm_led11, i2s_3_data0_a, ebi2_lcd, i2s_3_data1_a,
+                   i2s_3_data2_a, atest_char, pwm_led3, i2s_3_data3_a,
+                   pwm_led4, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, pwm_led6,
+                   pwm_led7, pwm_led8, pwm_led24, spkr_dac0, blsp_i2c4,
+                   pwm_led9, pwm_led10, spdifrx_opt, pwm_led12, pwm_led13,
+                   pwm_led14, wlan1_adc1, rgb_data_b0, pwm_led15,
+                   blsp_spi_mosi_b1, wlan1_adc0, rgb_data_b1, pwm_led16,
+                   blsp_spi_miso_b1, qdss_cti_trig_out_b0, wlan2_adc1,
+                   rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, wlan2_adc0,
+                   rgb_data_b3, pwm_led18, blsp_spi_clk_b1, rgb_data_b4,
+                   pwm_led19, ext_mclk1_b, qdss_traceclk_a, rgb_data_b5,
+                   pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0,
+                   rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, rgb_vsync,
+                   i2s_3_data0_b, ldo_en, hdmi_dtest, rgb_de, i2s_3_data1_b,
+                   hdmi_lbk9, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc,
+                   hdmi_lbk8, rgb_mdp, atest_char0, i2s_3_data3_b, hdmi_lbk7,
+                   rgb_data_b6, rgb_data_b7, hdmi_lbk6, rgmii_int, cri_trng1,
+                   rgmii_wol, cri_trng0, gcc_tlmm, rgmii_ck, rgmii_tx,
+                   hdmi_lbk5, hdmi_pixel, hdmi_rcv, hdmi_lbk4, rgmii_ctl,
+                   ext_lpass, rgmii_rx, cri_trng, hdmi_lbk3, hdmi_lbk2,
+                   qdss_cti_trig_out_b1, rgmii_mdio, hdmi_lbk1, rgmii_mdc,
+                   hdmi_lbk0, ir_in, wsa_en, rgb_data6, rgb_data7,
+                   atest_char2, ebi_ch0, blsp_uart3, blsp_spi3, sd_write,
+                   blsp_i2c3, gcc_gp1_clk_a, qdss_cti_trig_in_b1,
+                   gcc_gp2_clk_a, ext_mclk0, mclk_in1, i2s_1, dsd_clk_a,
+                   qdss_cti_trig_in_a1, rgmi_dll1, pwm_led22, pwm_led23,
+                   qdss_cti_trig_out_a0, rgmi_dll2, pwm_led1,
+                   qdss_cti_trig_out_a1, pwm_led2, i2s_2, pll_bist,
+                   ext_mclk1_a, mclk_in2, bimc_dte1, i2s_3_sck_a, i2s_3_ws_a
+
+- bias-disable:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins should be configued as pull up.
+
+- output-high:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins are configured in output mode, driven
+                   high.
+                   Not valid for sdc pins.
+
+- output-low:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins are configured in output mode, driven
+                   low.
+                   Not valid for sdc pins.
+
+- drive-strength:
+       Usage: optional
+       Value type: <u32>
+       Definition: Selects the drive strength for the specified pins, in mA.
+                   Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+       tlmm: pinctrl@1000000 {
+               compatible = "qcom,qcs404-pinctrl";
+               reg = <0x01000000 0x200000>,
+                     <0x01300000 0x200000>,
+                     <0x07b00000 0x200000>;
+               reg-names = "south", "north", "east";
+               interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-ranges = <&tlmm 0 0 120>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt
new file mode 100644 (file)
index 0000000..769ca83
--- /dev/null
@@ -0,0 +1,191 @@
+Qualcomm Technologies, Inc. SDM660 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+SDM660 platform.
+
+- compatible:
+       Usage: required
+       Value type: <string>
+       Definition: must be "qcom,sdm660-pinctrl" or
+                   "qcom,sdm630-pinctrl".
+
+- reg:
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: the base address and size of the north, center and south
+                   TLMM tiles.
+
+- reg-names:
+       Usage: required
+       Value type: <stringlist>
+       Definition: names for the cells of reg, must contain "north", "center"
+                   and "south".
+
+- interrupts:
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+       Usage: required
+       Value type: <none>
+       Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+       Usage: required
+       Value type: <u32>
+       Definition: must be 2. Specifying the pin number and flags, as defined
+                   in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+       Usage: required
+       Value type: <none>
+       Definition: identifies this node as a gpio controller
+
+- gpio-ranges:
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: Specifies the mapping between gpio controller and
+                   pin-controller pins.
+
+- #gpio-cells:
+       Usage: required
+       Value type: <u32>
+       Definition: must be 2. Specifying the pin number and flags, as defined
+                   in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+       Usage: required
+       Value type: <string-array>
+       Definition: List of gpio pins affected by the properties specified in
+                   this subnode.  Valid pins are:
+                   gpio0-gpio113,
+                       Supports mux, bias and drive-strength
+                   sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk,
+                       Supports bias and drive-strength
+
+- function:
+       Usage: required
+       Value type: <string>
+       Definition: Specify the alternative function to be configured for the
+                   specified pins. Functions are only valid for gpio pins.
+                   Valid values are:
+                   adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
+                   atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
+                   atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
+                   atest_usb11, atest_usb12, atest_usb13, atest_usb2,
+                   atest_usb20, atest_usb21, atest_usb22, atest_usb23,
+                   audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2,
+                   blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
+                   blsp_i2c8_a, blsp_i2c8_b, blsp_spi1, blsp_spi2, blsp_spi3,
+                   blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi4, blsp_spi5,
+                   blsp_spi6, blsp_spi7, blsp_spi8_a, blsp_spi8_b,
+                   blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, blsp_uart2,
+                   blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
+                   blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async,
+                   cci_i2c, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
+                   gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
+                   isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
+                   mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
+                   nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
+                   phase_flag1, phase_flag10, phase_flag11, phase_flag12,
+                   phase_flag13, phase_flag14, phase_flag15, phase_flag16,
+                   phase_flag17, phase_flag18, phase_flag19, phase_flag2,
+                   phase_flag20, phase_flag21, phase_flag22, phase_flag23,
+                   phase_flag24, phase_flag25, phase_flag26, phase_flag27,
+                   phase_flag28, phase_flag29, phase_flag3, phase_flag30,
+                   phase_flag31, phase_flag4, phase_flag5, phase_flag6,
+                   phase_flag7, phase_flag8, phase_flag9, pll_bypassnl,
+                   pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto,
+                   pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a,
+                   qdss_cti1_b, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10,
+                   qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
+                   qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
+                   qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request,
+                   qspi_clk, qspi_cs, qspi_data0, qspi_data1, qspi_data2,
+                   qspi_data3, qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data,
+                   sp_cmu, ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2,
+                   uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
+                   uim2_data, uim2_present, uim2_reset, uim_batt, vfr_1,
+                   vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
+                   wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1
+
+- bias-disable:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins should be configued as pull up.
+
+- output-high:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins are configured in output mode, driven
+                   high.
+                   Not valid for sdc pins.
+
+- output-low:
+       Usage: optional
+       Value type: <none>
+       Definition: The specified pins are configured in output mode, driven
+                   low.
+                   Not valid for sdc pins.
+
+- drive-strength:
+       Usage: optional
+       Value type: <u32>
+       Definition: Selects the drive strength for the specified pins, in mA.
+                   Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+       tlmm: pinctrl@3100000 {
+               compatible = "qcom,sdm660-pinctrl";
+               reg = <0x3100000 0x200000>,
+                     <0x3500000 0x200000>,
+                     <0x3900000 0x200000>;
+               reg-names = "south", "center", "north";
+               interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+               gpio-controller;
+               gpio-ranges = <&tlmm 0 0 114>;
+               #gpio-cells = <2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
index abd8fbcf1e62d480562a0fb9d1471020c0c29d75..3902efa18fd0f8994c98c4210d4c021d8665fdde 100644 (file)
@@ -14,8 +14,11 @@ Required Properties:
     - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
     - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
     - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
+    - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
     - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
     - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
+    - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
+    - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
     - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
     - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
     - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt
new file mode 100644 (file)
index 0000000..25e53ac
--- /dev/null
@@ -0,0 +1,153 @@
+Renesas RZ/N1 SoC Pinctrl node description.
+
+Pin controller node
+-------------------
+Required properties:
+- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
+  followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
+  strings must be one of:
+       "renesas,r9a06g032-pinctrl" for RZ/N1D
+       "renesas,r9a06g033-pinctrl" for RZ/N1S
+- reg: Address base and length of the memory area where the pin controller
+  hardware is mapped to.
+- clocks: phandle for the clock, see the description of clock-names below.
+- clock-names: Contains the name of the clock:
+    "bus", the bus clock, sometimes described as pclk, for register accesses.
+
+Example:
+       pinctrl: pin-controller@40067000 {
+           compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
+           reg = <0x40067000 0x1000>, <0x51000000 0x480>;
+           clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
+           clock-names = "bus";
+       };
+
+Sub-nodes
+---------
+
+The child nodes of the pin controller node describe a pin multiplexing
+function.
+
+- Pin multiplexing sub-nodes:
+  A pin multiplexing sub-node describes how to configure a set of
+  (or a single) pin in some desired alternate function mode.
+  A single sub-node may define several pin configurations.
+  Please refer to pinctrl-bindings.txt to get to know more on generic
+  pin properties usage.
+
+  The allowed generic formats for a pin multiplexing sub-node are the
+  following ones:
+
+  node-1 {
+      pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+      GENERIC_PINCONFIG;
+  };
+
+  node-2 {
+      sub-node-1 {
+          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+          GENERIC_PINCONFIG;
+      };
+
+      sub-node-2 {
+          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+          GENERIC_PINCONFIG;
+      };
+
+      ...
+
+      sub-node-n {
+          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+          GENERIC_PINCONFIG;
+      };
+  };
+
+  node-3 {
+      pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+      GENERIC_PINCONFIG;
+
+      sub-node-1 {
+          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+          GENERIC_PINCONFIG;
+      };
+
+      ...
+
+      sub-node-n {
+          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+          GENERIC_PINCONFIG;
+      };
+  };
+
+  Use the latter two formats when pins part of the same logical group need to
+  have different generic pin configuration flags applied. Note that the generic
+  pinconfig in node-3 does not apply to the sub-nodes.
+
+  Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
+  of the most external one.
+
+  Eg.
+
+  client-1 {
+      ...
+      pinctrl-0 = <&node-1>;
+      ...
+  };
+
+  client-2 {
+      ...
+      pinctrl-0 = <&node-2>;
+      ...
+  };
+
+  Required properties:
+    - pinmux:
+      integer array representing pin number and pin multiplexing configuration.
+      When a pin has to be configured in alternate function mode, use this
+      property to identify the pin by its global index, and provide its
+      alternate function configuration number along with it.
+      When multiple pins are required to be configured as part of the same
+      alternate function they shall be specified as members of the same
+      argument list of a single "pinmux" property.
+      Integers values in the "pinmux" argument list are assembled as:
+      (PIN | MUX_FUNC << 8)
+      where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is
+      one of the alternate function identifiers defined in:
+      <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
+      These identifiers collapse the IO Multiplex Configuration Level 1 and
+      Level 2 numbers that are detailed in the hardware reference manual into a
+      single number. The identifiers for Level 2 are simply offset by 10.
+      Additional identifiers are provided to specify the MDIO source peripheral.
+
+  Optional generic pinconf properties:
+    - bias-disable             - disable any pin bias
+    - bias-pull-up             - pull up the pin with 50 KOhm
+    - bias-pull-down           - pull down the pin with 50 KOhm
+    - bias-high-impedance      - high impedance mode
+    - drive-strength           - sink or source at most 4, 6, 8 or 12 mA
+
+  Example:
+  A serial communication interface with a TX output pin and an RX input pin.
+
+  &pinctrl {
+       pins_uart0: pins_uart0 {
+               pinmux = <
+                       RZN1_PINMUX(103, RZN1_FUNC_UART0_I)     /* UART0_TXD */
+                       RZN1_PINMUX(104, RZN1_FUNC_UART0_I)     /* UART0_RXD */
+               >;
+       };
+  };
+
+  Example 2:
+  Here we set the pull up on the RXD pin of the UART.
+
+  &pinctrl {
+       pins_uart0: pins_uart0 {
+               pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */
+
+               pins_uart6_rx {
+                       pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */
+                       bias-pull-up;
+               };
+       };
+  };
index 2e3eb51aa44be56954bcc136d2d309bec04fc326..8c2cd7e03c963ae7bb6d7cf3b4986df298012baa 100644 (file)
@@ -11519,15 +11519,12 @@ S:    Maintained
 F:     drivers/pinctrl/intel/
 
 PIN CONTROLLER - MEDIATEK
-M:     Sean Wang <sean.wang@mediatek.com>
+M:     Sean Wang <sean.wang@kernel.org>
 L:     linux-mediatek@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
 F:     Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 F:     Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
-F:     drivers/pinctrl/mediatek/mtk-eint.*
-F:     drivers/pinctrl/mediatek/pinctrl-mtk-common.*
-F:     drivers/pinctrl/mediatek/pinctrl-mt2701.c
-F:     drivers/pinctrl/mediatek/pinctrl-mt7622.c
+F:     drivers/pinctrl/mediatek/
 
 PIN CONTROLLER - QUALCOMM
 M:     Bjorn Andersson <bjorn.andersson@linaro.org>
index 4f52c3a8ec99bf0801ac1a2a3c7e01a9b9be1453..052dd5960cec071b39c53822f5d45131fda3a585 100644 (file)
@@ -267,17 +267,6 @@ config GPIO_ICH
 
          If unsure, say N.
 
-config GPIO_INGENIC
-       tristate "Ingenic JZ47xx SoCs GPIO support"
-       depends on OF
-       depends on MACH_INGENIC || COMPILE_TEST
-       select GPIOLIB_IRQCHIP
-       help
-         Say yes here to support the GPIO functionality present on the
-         JZ4740 and JZ4780 SoCs from Ingenic.
-
-         If unsure, say N.
-
 config GPIO_IOP
        tristate "Intel IOP GPIO"
        depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST
index c256aff66a6567e22ff8e80cfc73fffe224ac1d1..80d58c2de73070716ef67486df517a9a67c15900 100644 (file)
@@ -57,7 +57,6 @@ obj-$(CONFIG_GPIO_GRGPIO)     += gpio-grgpio.o
 obj-$(CONFIG_GPIO_HLWD)                += gpio-hlwd.o
 obj-$(CONFIG_HTC_EGPIO)                += gpio-htc-egpio.o
 obj-$(CONFIG_GPIO_ICH)         += gpio-ich.o
-obj-$(CONFIG_GPIO_INGENIC)     += gpio-ingenic.o
 obj-$(CONFIG_GPIO_IOP)         += gpio-iop.o
 obj-$(CONFIG_GPIO_IT87)                += gpio-it87.o
 obj-$(CONFIG_GPIO_JANZ_TTL)    += gpio-janz-ttl.o
diff --git a/drivers/gpio/gpio-ingenic.c b/drivers/gpio/gpio-ingenic.c
deleted file mode 100644 (file)
index e738e38..0000000
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * Ingenic JZ47xx GPIO driver
- *
- * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/gpio/driver.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/regmap.h>
-
-#define GPIO_PIN       0x00
-#define GPIO_MSK       0x20
-
-#define JZ4740_GPIO_DATA       0x10
-#define JZ4740_GPIO_SELECT     0x50
-#define JZ4740_GPIO_DIR                0x60
-#define JZ4740_GPIO_TRIG       0x70
-#define JZ4740_GPIO_FLAG       0x80
-
-#define JZ4770_GPIO_INT                0x10
-#define JZ4770_GPIO_PAT1       0x30
-#define JZ4770_GPIO_PAT0       0x40
-#define JZ4770_GPIO_FLAG       0x50
-
-#define REG_SET(x) ((x) + 0x4)
-#define REG_CLEAR(x) ((x) + 0x8)
-
-enum jz_version {
-       ID_JZ4740,
-       ID_JZ4770,
-       ID_JZ4780,
-};
-
-struct ingenic_gpio_chip {
-       struct regmap *map;
-       struct gpio_chip gc;
-       struct irq_chip irq_chip;
-       unsigned int irq, reg_base;
-       enum jz_version version;
-};
-
-static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
-{
-       unsigned int val;
-
-       regmap_read(jzgc->map, jzgc->reg_base + reg, &val);
-
-       return (u32) val;
-}
-
-static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
-               u8 reg, u8 offset, bool set)
-{
-       if (set)
-               reg = REG_SET(reg);
-       else
-               reg = REG_CLEAR(reg);
-
-       regmap_write(jzgc->map, jzgc->reg_base + reg, BIT(offset));
-}
-
-static inline bool gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset)
-{
-       unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
-
-       return !!(val & BIT(offset));
-}
-
-static void gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value)
-{
-       if (jzgc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
-       else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
-}
-
-static void irq_set_type(struct ingenic_gpio_chip *jzgc,
-               u8 offset, unsigned int type)
-{
-       u8 reg1, reg2;
-
-       if (jzgc->version >= ID_JZ4770) {
-               reg1 = JZ4770_GPIO_PAT1;
-               reg2 = JZ4770_GPIO_PAT0;
-       } else {
-               reg1 = JZ4740_GPIO_TRIG;
-               reg2 = JZ4740_GPIO_DIR;
-       }
-
-       switch (type) {
-       case IRQ_TYPE_EDGE_RISING:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, true);
-               break;
-       case IRQ_TYPE_EDGE_FALLING:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, true);
-               break;
-       case IRQ_TYPE_LEVEL_HIGH:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, false);
-               break;
-       case IRQ_TYPE_LEVEL_LOW:
-       default:
-               gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-               gpio_ingenic_set_bit(jzgc, reg1, offset, false);
-               break;
-       }
-}
-
-static void ingenic_gpio_irq_mask(struct irq_data *irqd)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-
-       gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
-}
-
-static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-
-       gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
-}
-
-static void ingenic_gpio_irq_enable(struct irq_data *irqd)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-       int irq = irqd->hwirq;
-
-       if (jzgc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
-       else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
-
-       ingenic_gpio_irq_unmask(irqd);
-}
-
-static void ingenic_gpio_irq_disable(struct irq_data *irqd)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-       int irq = irqd->hwirq;
-
-       ingenic_gpio_irq_mask(irqd);
-
-       if (jzgc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
-       else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
-}
-
-static void ingenic_gpio_irq_ack(struct irq_data *irqd)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-       int irq = irqd->hwirq;
-       bool high;
-
-       if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
-               /*
-                * Switch to an interrupt for the opposite edge to the one that
-                * triggered the interrupt being ACKed.
-                */
-               high = gpio_get_value(jzgc, irq);
-               if (high)
-                       irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
-               else
-                       irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
-       }
-
-       if (jzgc->version >= ID_JZ4770)
-               gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
-       else
-               gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
-}
-
-static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-
-       switch (type) {
-       case IRQ_TYPE_EDGE_BOTH:
-       case IRQ_TYPE_EDGE_RISING:
-       case IRQ_TYPE_EDGE_FALLING:
-               irq_set_handler_locked(irqd, handle_edge_irq);
-               break;
-       case IRQ_TYPE_LEVEL_HIGH:
-       case IRQ_TYPE_LEVEL_LOW:
-               irq_set_handler_locked(irqd, handle_level_irq);
-               break;
-       default:
-               irq_set_handler_locked(irqd, handle_bad_irq);
-       }
-
-       if (type == IRQ_TYPE_EDGE_BOTH) {
-               /*
-                * The hardware does not support interrupts on both edges. The
-                * best we can do is to set up a single-edge interrupt and then
-                * switch to the opposing edge when ACKing the interrupt.
-                */
-               bool high = gpio_get_value(jzgc, irqd->hwirq);
-
-               type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
-       }
-
-       irq_set_type(jzgc, irqd->hwirq, type);
-       return 0;
-}
-
-static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
-{
-       struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-
-       return irq_set_irq_wake(jzgc->irq, on);
-}
-
-static void ingenic_gpio_irq_handler(struct irq_desc *desc)
-{
-       struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-       struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
-       unsigned long flag, i;
-
-       chained_irq_enter(irq_chip, desc);
-
-       if (jzgc->version >= ID_JZ4770)
-               flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
-       else
-               flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
-
-       for_each_set_bit(i, &flag, 32)
-               generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
-       chained_irq_exit(irq_chip, desc);
-}
-
-static void ingenic_gpio_set(struct gpio_chip *gc,
-               unsigned int offset, int value)
-{
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-
-       gpio_set_value(jzgc, offset, value);
-}
-
-static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
-{
-       struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
-
-       return (int) gpio_get_value(jzgc, offset);
-}
-
-static int ingenic_gpio_direction_input(struct gpio_chip *gc,
-               unsigned int offset)
-{
-       return pinctrl_gpio_direction_input(gc->base + offset);
-}
-
-static int ingenic_gpio_direction_output(struct gpio_chip *gc,
-               unsigned int offset, int value)
-{
-       ingenic_gpio_set(gc, offset, value);
-       return pinctrl_gpio_direction_output(gc->base + offset);
-}
-
-static const struct of_device_id ingenic_gpio_of_match[] = {
-       { .compatible = "ingenic,jz4740-gpio", .data = (void *)ID_JZ4740 },
-       { .compatible = "ingenic,jz4770-gpio", .data = (void *)ID_JZ4770 },
-       { .compatible = "ingenic,jz4780-gpio", .data = (void *)ID_JZ4780 },
-       {},
-};
-MODULE_DEVICE_TABLE(of, ingenic_gpio_of_match);
-
-static int ingenic_gpio_probe(struct platform_device *pdev)
-{
-       struct device *dev = &pdev->dev;
-       struct ingenic_gpio_chip *jzgc;
-       u32 bank;
-       int err;
-
-       jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
-       if (!jzgc)
-               return -ENOMEM;
-
-       jzgc->map = dev_get_drvdata(dev->parent);
-       if (!jzgc->map) {
-               dev_err(dev, "Cannot get parent regmap\n");
-               return -ENXIO;
-       }
-
-       err = of_property_read_u32(dev->of_node, "reg", &bank);
-       if (err) {
-               dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
-               return err;
-       }
-
-       jzgc->reg_base = bank * 0x100;
-
-       jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
-       if (!jzgc->gc.label)
-               return -ENOMEM;
-
-       /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
-        * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
-        * <linux/gpio/consumer.h> INSTEAD.
-        */
-       jzgc->gc.base = bank * 32;
-
-       jzgc->gc.ngpio = 32;
-       jzgc->gc.parent = dev;
-       jzgc->gc.of_node = dev->of_node;
-       jzgc->gc.owner = THIS_MODULE;
-       jzgc->version = (enum jz_version)of_device_get_match_data(dev);
-
-       jzgc->gc.set = ingenic_gpio_set;
-       jzgc->gc.get = ingenic_gpio_get;
-       jzgc->gc.direction_input = ingenic_gpio_direction_input;
-       jzgc->gc.direction_output = ingenic_gpio_direction_output;
-
-       if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
-               jzgc->gc.request = gpiochip_generic_request;
-               jzgc->gc.free = gpiochip_generic_free;
-       }
-
-       err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
-       if (err)
-               return err;
-
-       jzgc->irq = irq_of_parse_and_map(dev->of_node, 0);
-       if (!jzgc->irq)
-               return -EINVAL;
-
-       jzgc->irq_chip.name = jzgc->gc.label;
-       jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
-       jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
-       jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
-       jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
-       jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
-       jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
-       jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
-       jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
-
-       err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
-                       handle_level_irq, IRQ_TYPE_NONE);
-       if (err)
-               return err;
-
-       gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
-                       jzgc->irq, ingenic_gpio_irq_handler);
-       return 0;
-}
-
-static int ingenic_gpio_remove(struct platform_device *pdev)
-{
-       return 0;
-}
-
-static struct platform_driver ingenic_gpio_driver = {
-       .driver = {
-               .name = "gpio-ingenic",
-               .of_match_table = of_match_ptr(ingenic_gpio_of_match),
-       },
-       .probe = ingenic_gpio_probe,
-       .remove = ingenic_gpio_remove,
-};
-
-static int __init ingenic_gpio_drv_register(void)
-{
-       return platform_driver_register(&ingenic_gpio_driver);
-}
-subsys_initcall(ingenic_gpio_drv_register);
-
-static void __exit ingenic_gpio_drv_unregister(void)
-{
-       platform_driver_unregister(&ingenic_gpio_driver);
-}
-module_exit(ingenic_gpio_drv_unregister);
-
-MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
-MODULE_DESCRIPTION("Ingenic JZ47xx GPIO driver");
-MODULE_LICENSE("GPL");
index 7fdac906097980f37e05cb23060369f4e3377a02..74551cbdb2e81cb408afdb8574e2fb2d820e3d11 100644 (file)
@@ -12,7 +12,7 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/bitops.h>
+#include <linux/bits.h>
 #include <linux/gpio/driver.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
index e86752be1f19ad39bfddcdb76620b4b37fc16639..4d8c00eac7420a8abfb5ceb4fd4769120f11dbe6 100644 (file)
@@ -195,6 +195,16 @@ config PINCTRL_RZA1
        help
          This selects pinctrl driver for Renesas RZ/A1 platforms.
 
+config PINCTRL_RZN1
+       bool "Renesas RZ/N1 pinctrl driver"
+       depends on OF
+       depends on ARCH_RZN1 || COMPILE_TEST
+       select GENERIC_PINCTRL_GROUPS
+       select GENERIC_PINMUX_FUNCTIONS
+       select GENERIC_PINCONF
+       help
+         This selects pinctrl driver for Renesas RZ/N1 devices.
+
 config PINCTRL_SINGLE
        tristate "One-register-per-pin type device tree based pinctrl driver"
        depends on OF
@@ -309,12 +319,14 @@ config PINCTRL_ZYNQ
 
 config PINCTRL_INGENIC
        bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
-       default y
+       default MACH_INGENIC
        depends on OF
-       depends on MACH_INGENIC || COMPILE_TEST
+       depends on MIPS || COMPILE_TEST
        select GENERIC_PINCONF
        select GENERIC_PINCTRL_GROUPS
        select GENERIC_PINMUX_FUNCTIONS
+       select GPIOLIB
+       select GPIOLIB_IRQCHIP
        select REGMAP_MMIO
 
 config PINCTRL_RK805
@@ -346,6 +358,7 @@ source "drivers/pinctrl/freescale/Kconfig"
 source "drivers/pinctrl/intel/Kconfig"
 source "drivers/pinctrl/mvebu/Kconfig"
 source "drivers/pinctrl/nomadik/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
 source "drivers/pinctrl/pxa/Kconfig"
 source "drivers/pinctrl/qcom/Kconfig"
 source "drivers/pinctrl/samsung/Kconfig"
index 46ef9bd52096fae55e694b52f420d0c7ec794b50..18a13c1e2c21f365988967b1edad7f816b7780a6 100644 (file)
@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32)   += pinctrl-pic32.o
 obj-$(CONFIG_PINCTRL_PISTACHIO)        += pinctrl-pistachio.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_RZA1)     += pinctrl-rza1.o
+obj-$(CONFIG_PINCTRL_RZN1)     += pinctrl-rzn1.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SIRF)     += sirf/
 obj-$(CONFIG_PINCTRL_SX150X)   += pinctrl-sx150x.o
@@ -51,6 +52,7 @@ obj-y                         += freescale/
 obj-$(CONFIG_X86)              += intel/
 obj-y                          += mvebu/
 obj-y                          += nomadik/
+obj-$(CONFIG_ARCH_NPCM7XX)     += nuvoton/
 obj-$(CONFIG_PINCTRL_PXA)      += pxa/
 obj-$(CONFIG_ARCH_QCOM)                += qcom/
 obj-$(CONFIG_PINCTRL_SAMSUNG)  += samsung/
index aefe3c33dffd85dbdeaba81fb46e32971a720314..eb87ab774269c5ea73e63c2c12af62f9499b51a3 100644 (file)
@@ -715,7 +715,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
 
                pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg);
 
-               if (unlikely(WARN_ON(!pmap)))
+               if (WARN_ON(!pmap))
                        return -EINVAL;
 
                val = pmap->val << pconf->bit;
index 0f38d51f47c64cf33f4918918056c4da1da5dfd3..c8575399d6f7ac67db7511e9824e30d466b1fa56 100644 (file)
@@ -73,6 +73,19 @@ config PINCTRL_CYGNUS_MUX
          configuration, with the exception that certain individual pins
          can be overridden to GPIO function
 
+config PINCTRL_NS
+       bool "Broadcom Northstar pins driver"
+       depends on OF && (ARCH_BCM_5301X || COMPILE_TEST)
+       select PINMUX
+       select GENERIC_PINCONF
+       default ARCH_BCM_5301X
+       help
+         Say yes here to enable the Broadcom NS SoC pins driver.
+
+         The Broadcom Northstar pins driver supports muxing multi-purpose pins
+         that can be used for various functions (e.g. SPI, I2C, UART) as well
+         as GPIOs.
+
 config PINCTRL_NSP_GPIO
        bool "Broadcom NSP GPIO (with PINCONF) driver"
        depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
index 80ceb9dae944247fdd4f9b97f930aa799c595e63..79d5e49fdd9a5a64198aa11106202a0b4f93c0d7 100644 (file)
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX)          += pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_BCM2835)          += pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)       += pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)       += pinctrl-cygnus-mux.o
+obj-$(CONFIG_PINCTRL_NS)               += pinctrl-ns.o
 obj-$(CONFIG_PINCTRL_NSP_GPIO)         += pinctrl-nsp-gpio.o
 obj-$(CONFIG_PINCTRL_NS2_MUX)          += pinctrl-ns2-mux.o
 obj-$(CONFIG_PINCTRL_NSP_MUX)          += pinctrl-nsp-mux.o
diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c
new file mode 100644 (file)
index 0000000..d7f8175
--- /dev/null
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Rafał Miłecki <rafal@milecki.pl>
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define FLAG_BCM4708           BIT(1)
+#define FLAG_BCM4709           BIT(2)
+#define FLAG_BCM53012          BIT(3)
+
+struct ns_pinctrl {
+       struct device *dev;
+       unsigned int chipset_flag;
+       struct pinctrl_dev *pctldev;
+       void __iomem *base;
+
+       struct pinctrl_desc pctldesc;
+       struct ns_pinctrl_group *groups;
+       unsigned int num_groups;
+       struct ns_pinctrl_function *functions;
+       unsigned int num_functions;
+};
+
+/*
+ * Pins
+ */
+
+static const struct pinctrl_pin_desc ns_pinctrl_pins[] = {
+       { 0, "spi_clk", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 1, "spi_ss", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 2, "spi_mosi", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 3, "spi_miso", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 4, "i2c_scl", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 5, "i2c_sda", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 6, "mdc", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
+       { 7, "mdio", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
+       { 8, "pwm0", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 9, "pwm1", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 10, "pwm2", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 11, "pwm3", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 12, "uart1_rx", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 13, "uart1_tx", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 14, "uart1_cts", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 15, "uart1_rts", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
+       { 16, "uart2_rx", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
+       { 17, "uart2_tx", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
+/* TODO { ??, "xtal_out", (void *)(FLAG_BCM4709) }, */
+       { 22, "sdio_pwr", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
+       { 23, "sdio_en_1p8v", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
+};
+
+/*
+ * Groups
+ */
+
+struct ns_pinctrl_group {
+       const char *name;
+       const unsigned int *pins;
+       const unsigned int num_pins;
+       unsigned int chipsets;
+};
+
+static const unsigned int spi_pins[] = { 0, 1, 2, 3 };
+static const unsigned int i2c_pins[] = { 4, 5 };
+static const unsigned int mdio_pins[] = { 6, 7 };
+static const unsigned int pwm0_pins[] = { 8 };
+static const unsigned int pwm1_pins[] = { 9 };
+static const unsigned int pwm2_pins[] = { 10 };
+static const unsigned int pwm3_pins[] = { 11 };
+static const unsigned int uart1_pins[] = { 12, 13, 14, 15 };
+static const unsigned int uart2_pins[] = { 16, 17 };
+static const unsigned int sdio_pwr_pins[] = { 22 };
+static const unsigned int sdio_1p8v_pins[] = { 23 };
+
+#define NS_GROUP(_name, _pins, _chipsets)              \
+{                                                      \
+       .name = _name,                                  \
+       .pins = _pins,                                  \
+       .num_pins = ARRAY_SIZE(_pins),                  \
+       .chipsets = _chipsets,                          \
+}
+
+static const struct ns_pinctrl_group ns_pinctrl_groups[] = {
+       NS_GROUP("spi_grp", spi_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("i2c_grp", i2c_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("mdio_grp", mdio_pins, FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("pwm0_grp", pwm0_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("pwm1_grp", pwm1_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("pwm2_grp", pwm2_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("pwm3_grp", pwm3_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("uart1_grp", uart1_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("uart2_grp", uart2_pins, FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("sdio_pwr_grp", sdio_pwr_pins, FLAG_BCM4709 | FLAG_BCM53012),
+       NS_GROUP("sdio_1p8v_grp", sdio_1p8v_pins, FLAG_BCM4709 | FLAG_BCM53012),
+};
+
+/*
+ * Functions
+ */
+
+struct ns_pinctrl_function {
+       const char *name;
+       const char * const *groups;
+       const unsigned int num_groups;
+       unsigned int chipsets;
+};
+
+static const char * const spi_groups[] = { "spi_grp" };
+static const char * const i2c_groups[] = { "i2c_grp" };
+static const char * const mdio_groups[] = { "mdio_grp" };
+static const char * const pwm_groups[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
+                                          "pwm3_grp" };
+static const char * const uart1_groups[] = { "uart1_grp" };
+static const char * const uart2_groups[] = { "uart2_grp" };
+static const char * const sdio_groups[] = { "sdio_pwr_grp", "sdio_1p8v_grp" };
+
+#define NS_FUNCTION(_name, _groups, _chipsets)         \
+{                                                      \
+       .name = _name,                                  \
+       .groups = _groups,                              \
+       .num_groups = ARRAY_SIZE(_groups),              \
+       .chipsets = _chipsets,                          \
+}
+
+static const struct ns_pinctrl_function ns_pinctrl_functions[] = {
+       NS_FUNCTION("spi", spi_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_FUNCTION("i2c", i2c_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_FUNCTION("mdio", mdio_groups, FLAG_BCM4709 | FLAG_BCM53012),
+       NS_FUNCTION("pwm", pwm_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_FUNCTION("uart1", uart1_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
+       NS_FUNCTION("uart2", uart2_groups, FLAG_BCM4709 | FLAG_BCM53012),
+       NS_FUNCTION("sdio", sdio_groups, FLAG_BCM4709 | FLAG_BCM53012),
+};
+
+/*
+ * Groups code
+ */
+
+static int ns_pinctrl_get_groups_count(struct pinctrl_dev *pctrl_dev)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+       return ns_pinctrl->num_groups;
+}
+
+static const char *ns_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev,
+                                            unsigned int selector)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+       return ns_pinctrl->groups[selector].name;
+}
+
+static int ns_pinctrl_get_group_pins(struct pinctrl_dev *pctrl_dev,
+                                    unsigned int selector,
+                                    const unsigned int **pins,
+                                    unsigned int *num_pins)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+       *pins = ns_pinctrl->groups[selector].pins;
+       *num_pins = ns_pinctrl->groups[selector].num_pins;
+
+       return 0;
+}
+
+static const struct pinctrl_ops ns_pinctrl_ops = {
+       .get_groups_count = ns_pinctrl_get_groups_count,
+       .get_group_name = ns_pinctrl_get_group_name,
+       .get_group_pins = ns_pinctrl_get_group_pins,
+       .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+       .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+/*
+ * Functions code
+ */
+
+static int ns_pinctrl_get_functions_count(struct pinctrl_dev *pctrl_dev)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+       return ns_pinctrl->num_functions;
+}
+
+static const char *ns_pinctrl_get_function_name(struct pinctrl_dev *pctrl_dev,
+                                               unsigned int selector)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+       return ns_pinctrl->functions[selector].name;
+}
+
+static int ns_pinctrl_get_function_groups(struct pinctrl_dev *pctrl_dev,
+                                         unsigned int selector,
+                                         const char * const **groups,
+                                         unsigned * const num_groups)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+       *groups = ns_pinctrl->functions[selector].groups;
+       *num_groups = ns_pinctrl->functions[selector].num_groups;
+
+       return 0;
+}
+
+static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
+                             unsigned int func_select,
+                             unsigned int grp_select)
+{
+       struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+       u32 unset = 0;
+       u32 tmp;
+       int i;
+
+       for (i = 0; i < ns_pinctrl->groups[grp_select].num_pins; i++) {
+               int pin_number = ns_pinctrl->groups[grp_select].pins[i];
+
+               unset |= BIT(pin_number);
+       }
+
+       tmp = readl(ns_pinctrl->base);
+       tmp &= ~unset;
+       writel(tmp, ns_pinctrl->base);
+
+       return 0;
+}
+
+static const struct pinmux_ops ns_pinctrl_pmxops = {
+       .get_functions_count = ns_pinctrl_get_functions_count,
+       .get_function_name = ns_pinctrl_get_function_name,
+       .get_function_groups = ns_pinctrl_get_function_groups,
+       .set_mux = ns_pinctrl_set_mux,
+};
+
+/*
+ * Controller code
+ */
+
+static struct pinctrl_desc ns_pinctrl_desc = {
+       .name = "pinctrl-ns",
+       .pctlops = &ns_pinctrl_ops,
+       .pmxops = &ns_pinctrl_pmxops,
+};
+
+static const struct of_device_id ns_pinctrl_of_match_table[] = {
+       { .compatible = "brcm,bcm4708-pinmux", .data = (void *)FLAG_BCM4708, },
+       { .compatible = "brcm,bcm4709-pinmux", .data = (void *)FLAG_BCM4709, },
+       { .compatible = "brcm,bcm53012-pinmux", .data = (void *)FLAG_BCM53012, },
+       { }
+};
+
+static int ns_pinctrl_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       const struct of_device_id *of_id;
+       struct ns_pinctrl *ns_pinctrl;
+       struct pinctrl_desc *pctldesc;
+       struct pinctrl_pin_desc *pin;
+       struct ns_pinctrl_group *group;
+       struct ns_pinctrl_function *function;
+       struct resource *res;
+       int i;
+
+       ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
+       if (!ns_pinctrl)
+               return -ENOMEM;
+       pctldesc = &ns_pinctrl->pctldesc;
+       platform_set_drvdata(pdev, ns_pinctrl);
+
+       /* Set basic properties */
+
+       ns_pinctrl->dev = dev;
+
+       of_id = of_match_device(ns_pinctrl_of_match_table, dev);
+       if (!of_id)
+               return -EINVAL;
+       ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
+
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                          "cru_gpio_control");
+       ns_pinctrl->base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(ns_pinctrl->base)) {
+               dev_err(dev, "Failed to map pinctrl regs\n");
+               return PTR_ERR(ns_pinctrl->base);
+       }
+
+       memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));
+
+       /* Set pinctrl properties */
+
+       pctldesc->pins = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_pins),
+                                     sizeof(struct pinctrl_pin_desc),
+                                     GFP_KERNEL);
+       if (!pctldesc->pins)
+               return -ENOMEM;
+       for (i = 0, pin = (struct pinctrl_pin_desc *)&pctldesc->pins[0];
+            i < ARRAY_SIZE(ns_pinctrl_pins); i++) {
+               const struct pinctrl_pin_desc *src = &ns_pinctrl_pins[i];
+               unsigned int chipsets = (uintptr_t)src->drv_data;
+
+               if (chipsets & ns_pinctrl->chipset_flag) {
+                       memcpy(pin++, src, sizeof(*src));
+                       pctldesc->npins++;
+               }
+       }
+
+       ns_pinctrl->groups = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_groups),
+                                         sizeof(struct ns_pinctrl_group),
+                                         GFP_KERNEL);
+       if (!ns_pinctrl->groups)
+               return -ENOMEM;
+       for (i = 0, group = &ns_pinctrl->groups[0];
+            i < ARRAY_SIZE(ns_pinctrl_groups); i++) {
+               const struct ns_pinctrl_group *src = &ns_pinctrl_groups[i];
+
+               if (src->chipsets & ns_pinctrl->chipset_flag) {
+                       memcpy(group++, src, sizeof(*src));
+                       ns_pinctrl->num_groups++;
+               }
+       }
+
+       ns_pinctrl->functions = devm_kcalloc(dev,
+                                            ARRAY_SIZE(ns_pinctrl_functions),
+                                            sizeof(struct ns_pinctrl_function),
+                                            GFP_KERNEL);
+       if (!ns_pinctrl->functions)
+               return -ENOMEM;
+       for (i = 0, function = &ns_pinctrl->functions[0];
+            i < ARRAY_SIZE(ns_pinctrl_functions); i++) {
+               const struct ns_pinctrl_function *src = &ns_pinctrl_functions[i];
+
+               if (src->chipsets & ns_pinctrl->chipset_flag) {
+                       memcpy(function++, src, sizeof(*src));
+                       ns_pinctrl->num_functions++;
+               }
+       }
+
+       /* Register */
+
+       ns_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, ns_pinctrl);
+       if (IS_ERR(ns_pinctrl->pctldev)) {
+               dev_err(dev, "Failed to register pinctrl\n");
+               return PTR_ERR(ns_pinctrl->pctldev);
+       }
+
+       return 0;
+}
+
+static struct platform_driver ns_pinctrl_driver = {
+       .probe = ns_pinctrl_probe,
+       .driver = {
+               .name = "ns-pinmux",
+               .of_match_table = ns_pinctrl_of_match_table,
+       },
+};
+
+module_platform_driver(ns_pinctrl_driver);
+
+MODULE_AUTHOR("Rafał Miłecki");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table);
index b5903fffb3d04be219514123646daea783368d8b..b17a03cf87bea7eaa58bfb1a762355ee619ea825 100644 (file)
@@ -64,16 +64,14 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
        ret = of_property_read_string(node, "function", &function_name);
        if (ret) {
                dev_err(pctrl->dev,
-                       "missing function property in node %s\n",
-                       node->name);
+                       "missing function property in node %pOFn\n", node);
                return -EINVAL;
        }
 
        ngroups = of_property_count_strings(node, "groups");
        if (ngroups < 0) {
                dev_err(pctrl->dev,
-                       "missing groups property in node %s\n",
-                       node->name);
+                       "missing groups property in node %pOFn\n", node);
                return -EINVAL;
        }
 
index c4f4d904e4a61e4c0d622a08fcb85e1f5e63b6a7..a5dda832024a01236eea8a570ef92b60abed942d 100644 (file)
@@ -550,7 +550,7 @@ static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev,
        seq_printf(s, " DRV=%umA", madera_pin_unmake_drv_str(priv, conf[1]));
 
        if (conf[0] & MADERA_GP1_IP_CFG_MASK)
-               seq_puts(s, "SCHMITT");
+               seq_puts(s, " SCHMITT");
 }
 
 
@@ -608,7 +608,7 @@ static int madera_mux_set_mux(struct pinctrl_dev *pctldev,
        unsigned int n_chip_groups = priv->chip->n_pin_groups;
        const char *func_name = madera_mux_funcs[selector].name;
        unsigned int reg;
-       int i, ret;
+       int i, ret = 0;
 
        dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n",
                __func__, selector, func_name, group,
@@ -801,7 +801,7 @@ static int madera_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin,
                        result = 1;
                break;
        default:
-               break;
+               return -ENOTSUPP;
        }
 
        *config = pinconf_to_config_packed(param, result);
@@ -905,7 +905,7 @@ static int madera_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin,
                        conf[1] &= ~MADERA_GP1_DIR;
                        break;
                default:
-                       break;
+                       return -ENOTSUPP;
                }
 
                ++configs;
@@ -971,10 +971,10 @@ static int madera_pin_conf_group_set(struct pinctrl_dev *pctldev,
 }
 
 static const struct pinconf_ops madera_pin_conf_ops = {
+       .is_generic = true,
        .pin_config_get = madera_pin_conf_get,
        .pin_config_set = madera_pin_conf_set,
        .pin_config_group_set = madera_pin_conf_group_set,
-
 };
 
 static struct pinctrl_desc madera_pin_desc = {
index a3dd777e3ce85b050dba4ed4495b6414006ac97b..c6ff4d5fa482e09f3aac5ad723e1510d364a099d 100644 (file)
@@ -627,7 +627,7 @@ static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev,
        while (selector < ngroups) {
                const char *gname = ops->get_group_name(pctldev, selector);
 
-               if (!strcmp(function, gname))
+               if (gname && !strcmp(function, gname))
                        return selector;
 
                selector++;
@@ -743,7 +743,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
        while (group_selector < ngroups) {
                const char *gname = pctlops->get_group_name(pctldev,
                                                            group_selector);
-               if (!strcmp(gname, pin_group)) {
+               if (gname && !strcmp(gname, pin_group)) {
                        dev_dbg(pctldev->dev,
                                "found group selector %u for %s\n",
                                group_selector,
index b04edc22dad7652ca2d9661b3cac31ed52224de8..4e8cf0e357c6eb638c958e9a20fbe610b49c299a 100644 (file)
@@ -69,8 +69,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
         */
        grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
        if (!grp) {
-               dev_err(ipctl->dev, "unable to find group for node %s\n",
-                       np->name);
+               dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
                return -EINVAL;
        }
 
@@ -434,7 +433,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
        int i;
        u32 config;
 
-       dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
+       dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
 
        if (info->flags & SHARE_MUX_CONF_REG)
                pin_size = FSL_PIN_SHARE_SIZE;
@@ -544,7 +543,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
        struct group_desc *grp;
        u32 i = 0;
 
-       dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name);
+       dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
 
        func = pinmux_generic_get_function(pctl, index);
        if (!func)
index deb7870b3d1a675df9d96453654887869d6a1e7b..7e29e3fecdb246568a78a205f978325c5f203cdf 100644 (file)
@@ -233,8 +233,8 @@ static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
         */
        grp = imx1_pinctrl_find_group_by_name(info, np->name);
        if (!grp) {
-               dev_err(info->dev, "unable to find group for node %s\n",
-                       np->name);
+               dev_err(info->dev, "unable to find group for node %pOFn\n",
+                       np);
                return -EINVAL;
        }
 
@@ -466,7 +466,7 @@ static int imx1_pinctrl_parse_groups(struct device_node *np,
        const __be32 *list;
        int i;
 
-       dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+       dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
 
        /* Initialise group */
        grp->name = np->name;
@@ -477,8 +477,8 @@ static int imx1_pinctrl_parse_groups(struct device_node *np,
        list = of_get_property(np, "fsl,pins", &size);
        /* we do not check return since it's safe node passed down */
        if (!size || size % 12) {
-               dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
-                               np->name);
+               dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n",
+                               np);
                return -EINVAL;
        }
 
@@ -513,7 +513,7 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
        static u32 grp_index;
        u32 i = 0;
 
-       dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+       dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
 
        func = &info->functions[index];
 
index a612e46ca51c07d6e07399d0217a8ae3395c90f1..641b3088876fb3037cfa56452f6088dbe3d456d6 100644 (file)
@@ -556,4 +556,3 @@ err:
        iounmap(d->base);
        return ret;
 }
-EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
index f38d596efa05f57c995d96094acb241cb48c67be..6d1a43c0c251b63c18fc1bb9e0957bbaea023d28 100644 (file)
@@ -6,18 +6,19 @@
  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
+#include <linux/acpi.h>
 #include <linux/bitops.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
 #include <linux/gpio/driver.h>
-#include <linux/acpi.h>
-#include <linux/platform_device.h>
-#include <linux/seq_file.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/seq_file.h>
+
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
@@ -682,7 +683,7 @@ static const struct pinctrl_pin_desc byt_ncore_pins[] = {
        PINCTRL_PIN(27, "GPIO_NCORE27"),
 };
 
-static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
+static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
        19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
        14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
        3, 6, 10, 13, 2, 5, 9, 7,
@@ -926,7 +927,7 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
        return 0;
 }
 
-static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
+static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
 {
        /* SCORE pin 92-93 */
        if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
@@ -1310,7 +1311,7 @@ static const struct pinctrl_desc byt_pinctrl_desc = {
        .owner          = THIS_MODULE,
 };
 
-static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
 {
        struct byt_gpio *vg = gpiochip_get_data(chip);
        void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
@@ -1324,7 +1325,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
        return !!(val & BYT_LEVEL);
 }
 
-static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 {
        struct byt_gpio *vg = gpiochip_get_data(chip);
        void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
@@ -1358,9 +1359,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
        raw_spin_unlock_irqrestore(&vg->lock, flags);
 
        if (!(value & BYT_OUTPUT_EN))
-               return GPIOF_DIR_OUT;
+               return 0;
        if (!(value & BYT_INPUT_EN))
-               return GPIOF_DIR_IN;
+               return 1;
 
        return -EINVAL;
 }
@@ -1495,7 +1496,7 @@ static void byt_irq_ack(struct irq_data *d)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct byt_gpio *vg = gpiochip_get_data(gc);
-       unsigned offset = irqd_to_hwirq(d);
+       unsigned int offset = irqd_to_hwirq(d);
        void __iomem *reg;
 
        reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
@@ -1519,7 +1520,7 @@ static void byt_irq_unmask(struct irq_data *d)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct byt_gpio *vg = gpiochip_get_data(gc);
-       unsigned offset = irqd_to_hwirq(d);
+       unsigned int offset = irqd_to_hwirq(d);
        unsigned long flags;
        void __iomem *reg;
        u32 value;
@@ -1775,13 +1776,11 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = {
        { "INT33FC", (kernel_ulong_t)byt_soc_data },
        { }
 };
-MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
 
 static int byt_pinctrl_probe(struct platform_device *pdev)
 {
        const struct byt_pinctrl_soc_data *soc_data = NULL;
        const struct byt_pinctrl_soc_data **soc_table;
-       const struct acpi_device_id *acpi_id;
        struct acpi_device *acpi_dev;
        struct byt_gpio *vg;
        int i, ret;
@@ -1790,11 +1789,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
        if (!acpi_dev)
                return -ENODEV;
 
-       acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
-       if (!acpi_id)
-               return -ENODEV;
-
-       soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
+       soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
 
        for (i = 0; soc_table[i]; i++) {
                if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
index 8b1c7b59ad3e34418c222004bf0342838c7acc01..68fefd4618bdf605b880451cab43d1e845a6e69c 100644 (file)
@@ -6,10 +6,10 @@
  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  */
 
-#include <linux/acpi.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -117,17 +117,17 @@ static const struct pinctrl_pin_desc bxt_north_pins[] = {
        PINCTRL_PIN(82, "TDO"),
 };
 
-static const unsigned bxt_north_pwm0_pins[] = { 34 };
-static const unsigned bxt_north_pwm1_pins[] = { 35 };
-static const unsigned bxt_north_pwm2_pins[] = { 36 };
-static const unsigned bxt_north_pwm3_pins[] = { 37 };
-static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
-static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
-static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
-static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
-static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
-static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
-static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
+static const unsigned int bxt_north_pwm0_pins[] = { 34 };
+static const unsigned int bxt_north_pwm1_pins[] = { 35 };
+static const unsigned int bxt_north_pwm2_pins[] = { 36 };
+static const unsigned int bxt_north_pwm3_pins[] = { 37 };
+static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
+static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
+static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
+static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
+static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
+static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
+static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
 
 static const struct intel_pingroup bxt_north_groups[] = {
        PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
@@ -260,12 +260,12 @@ static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
        PINCTRL_PIN(71, "GP_SSP_2_TXD"),
 };
 
-static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
-static const unsigned bxt_northwest_ssp1_pins[] = {
+static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
+static const unsigned int bxt_northwest_ssp1_pins[] = {
        59, 60, 61, 62, 63, 64, 65
 };
-static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
-static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
+static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
+static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
 
 static const struct intel_pingroup bxt_northwest_groups[] = {
        PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
@@ -347,17 +347,17 @@ static const struct pinctrl_pin_desc bxt_west_pins[] = {
        PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
 };
 
-static const unsigned bxt_west_i2c0_pins[] = { 0, 1 };
-static const unsigned bxt_west_i2c1_pins[] = { 2, 3 };
-static const unsigned bxt_west_i2c2_pins[] = { 4, 5 };
-static const unsigned bxt_west_i2c3_pins[] = { 6, 7 };
-static const unsigned bxt_west_i2c4_pins[] = { 8, 9 };
-static const unsigned bxt_west_i2c5_pins[] = { 10, 11 };
-static const unsigned bxt_west_i2c6_pins[] = { 12, 13 };
-static const unsigned bxt_west_i2c7_pins[] = { 14, 15 };
-static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 };
-static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 };
-static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 };
+static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 };
+static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 };
+static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 };
+static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 };
+static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 };
+static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 };
+static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 };
+static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 };
+static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 };
+static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 };
+static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 };
 
 static const struct intel_pingroup bxt_west_groups[] = {
        PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
@@ -443,13 +443,13 @@ static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
        PINCTRL_PIN(30, "SDCARD_LVL_WP"),
 };
 
-static const unsigned bxt_southwest_emmc0_pins[] = {
+static const unsigned int bxt_southwest_emmc0_pins[] = {
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
 };
-static const unsigned bxt_southwest_sdio_pins[] = {
+static const unsigned int bxt_southwest_sdio_pins[] = {
        10, 11, 12, 13, 14, 15, 27,
 };
-static const unsigned bxt_southwest_sdcard_pins[] = {
+static const unsigned int bxt_southwest_sdcard_pins[] = {
        16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
 };
 
@@ -611,13 +611,13 @@ static const struct pinctrl_pin_desc apl_north_pins[] = {
        PINCTRL_PIN(77, "SVID0_CLK"),
 };
 
-static const unsigned apl_north_pwm0_pins[] = { 34 };
-static const unsigned apl_north_pwm1_pins[] = { 35 };
-static const unsigned apl_north_pwm2_pins[] = { 36 };
-static const unsigned apl_north_pwm3_pins[] = { 37 };
-static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 };
-static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 };
-static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 };
+static const unsigned int apl_north_pwm0_pins[] = { 34 };
+static const unsigned int apl_north_pwm1_pins[] = { 35 };
+static const unsigned int apl_north_pwm2_pins[] = { 36 };
+static const unsigned int apl_north_pwm3_pins[] = { 37 };
+static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 };
+static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 };
+static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 };
 
 static const struct intel_pingroup apl_north_groups[] = {
        PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
@@ -743,10 +743,10 @@ static const struct pinctrl_pin_desc apl_northwest_pins[] = {
        PINCTRL_PIN(76, "GP_SSP_2_TXD"),
 };
 
-static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
-static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
-static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
-static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
+static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
+static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
+static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
+static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
 
 static const struct intel_pingroup apl_northwest_groups[] = {
        PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
@@ -833,15 +833,15 @@ static const struct pinctrl_pin_desc apl_west_pins[] = {
        PINCTRL_PIN(46, "SUSPWRDNACK"),
 };
 
-static const unsigned apl_west_i2c0_pins[] = { 0, 1 };
-static const unsigned apl_west_i2c1_pins[] = { 2, 3 };
-static const unsigned apl_west_i2c2_pins[] = { 4, 5 };
-static const unsigned apl_west_i2c3_pins[] = { 6, 7 };
-static const unsigned apl_west_i2c4_pins[] = { 8, 9 };
-static const unsigned apl_west_i2c5_pins[] = { 10, 11 };
-static const unsigned apl_west_i2c6_pins[] = { 12, 13 };
-static const unsigned apl_west_i2c7_pins[] = { 14, 15 };
-static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 };
+static const unsigned int apl_west_i2c0_pins[] = { 0, 1 };
+static const unsigned int apl_west_i2c1_pins[] = { 2, 3 };
+static const unsigned int apl_west_i2c2_pins[] = { 4, 5 };
+static const unsigned int apl_west_i2c3_pins[] = { 6, 7 };
+static const unsigned int apl_west_i2c4_pins[] = { 8, 9 };
+static const unsigned int apl_west_i2c5_pins[] = { 10, 11 };
+static const unsigned int apl_west_i2c6_pins[] = { 12, 13 };
+static const unsigned int apl_west_i2c7_pins[] = { 14, 15 };
+static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 };
 
 static const struct intel_pingroup apl_west_groups[] = {
        PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
@@ -939,16 +939,16 @@ static const struct pinctrl_pin_desc apl_southwest_pins[] = {
        PINCTRL_PIN(42, "LPC_FRAMEB"),
 };
 
-static const unsigned apl_southwest_emmc0_pins[] = {
+static const unsigned int apl_southwest_emmc0_pins[] = {
        4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
 };
-static const unsigned apl_southwest_sdio_pins[] = {
+static const unsigned int apl_southwest_sdio_pins[] = {
        14, 15, 16, 17, 18, 19, 30,
 };
-static const unsigned apl_southwest_sdcard_pins[] = {
+static const unsigned int apl_southwest_sdcard_pins[] = {
        20, 21, 22, 23, 24, 25, 26, 27, 28,
 };
-static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 };
+static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 };
 
 static const struct intel_pingroup apl_southwest_groups[] = {
        PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
@@ -1008,50 +1008,10 @@ static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
 
 static int bxt_pinctrl_probe(struct platform_device *pdev)
 {
-       const struct intel_pinctrl_soc_data *soc_data = NULL;
-       const struct intel_pinctrl_soc_data **soc_table;
-       struct acpi_device *adev;
-       int i;
-
-       adev = ACPI_COMPANION(&pdev->dev);
-       if (adev) {
-               const struct acpi_device_id *id;
-
-               id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
-               if (!id)
-                       return -ENODEV;
-
-               soc_table = (const struct intel_pinctrl_soc_data **)
-                       id->driver_data;
-
-               for (i = 0; soc_table[i]; i++) {
-                       if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
-                               soc_data = soc_table[i];
-                               break;
-                       }
-               }
-       } else {
-               const struct platform_device_id *pid;
-
-               pid = platform_get_device_id(pdev);
-               if (!pid)
-                       return -ENODEV;
-
-               soc_table = (const struct intel_pinctrl_soc_data **)
-                       pid->driver_data;
-               soc_data = soc_table[pdev->id];
-       }
-
-       if (!soc_data)
-               return -ENODEV;
-
-       return intel_pinctrl_probe(pdev, soc_data);
+       return intel_pinctrl_probe_by_uid(pdev);
 }
 
-static const struct dev_pm_ops bxt_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
 
 static struct platform_driver bxt_pinctrl_driver = {
        .probe = bxt_pinctrl_probe,
index e7f45d96b0cbd61e4cf7adfb050fbde547bcf752..fb121b3ed2f25bf0db144c722368add331536572 100644 (file)
@@ -7,10 +7,10 @@
  *          Mika Westerberg <mika.westerberg@linux.intel.com>
  */
 
-#include <linux/acpi.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -835,21 +835,10 @@ MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
 
 static int cnl_pinctrl_probe(struct platform_device *pdev)
 {
-       const struct intel_pinctrl_soc_data *soc_data;
-       const struct acpi_device_id *id;
-
-       id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
-       if (!id || !id->driver_data)
-               return -ENODEV;
-
-       soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
-       return intel_pinctrl_probe(pdev, soc_data);
+       return intel_pinctrl_probe_by_hid(pdev);
 }
 
-static const struct dev_pm_ops cnl_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
 
 static struct platform_driver cnl_pinctrl_driver = {
        .probe = cnl_pinctrl_probe,
index c788e37e338ed954f699e489810102cadcd4008c..7e068fc61ce108aefede7b01d49006377d471f79 100644 (file)
@@ -9,7 +9,7 @@
 #include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -335,10 +335,7 @@ static int cdf_pinctrl_probe(struct platform_device *pdev)
        return intel_pinctrl_probe(pdev, &cdf_soc_data);
 }
 
-static const struct dev_pm_ops cdf_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
 
 static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
        { "INTC3001" },
index 6d31ad7999879edf3e32f3371adff4d7830fe919..9b0f4b9ef482924aadcc126b788fc1494c7f6f7d 100644 (file)
  *   Alan Cox <alan@linux.intel.com>
  */
 
+#include <linux/acpi.h>
 #include <linux/dmi.h>
+#include <linux/gpio/driver.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/init.h>
+#include <linux/platform_device.h>
 #include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/gpio/driver.h>
-#include <linux/acpi.h>
+
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_device.h>
+
+#include "pinctrl-intel.h"
 
 #define CHV_INTSTAT                    0x300
 #define CHV_INTMASK                    0x380
@@ -73,7 +74,7 @@
  * @invert_oe: Invert OE for this pin
  */
 struct chv_alternate_function {
-       unsigned pin;
+       unsigned int pin;
        u8 mode;
        bool invert_oe;
 };
@@ -90,33 +91,21 @@ struct chv_alternate_function {
  */
 struct chv_pingroup {
        const char *name;
-       const unsigned *pins;
+       const unsigned int *pins;
        size_t npins;
        struct chv_alternate_function altfunc;
        const struct chv_alternate_function *overrides;
        size_t noverrides;
 };
 
-/**
- * struct chv_function - A CHV pinmux function
- * @name: Name of the function
- * @groups: An array of groups for this function
- * @ngroups: Number of groups in @groups
- */
-struct chv_function {
-       const char *name;
-       const char * const *groups;
-       size_t ngroups;
-};
-
 /**
  * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
  * @base: Start pin number
  * @npins: Number of pins in this range
  */
 struct chv_gpio_pinrange {
-       unsigned base;
-       unsigned npins;
+       unsigned int base;
+       unsigned int npins;
 };
 
 /**
@@ -131,6 +120,7 @@ struct chv_gpio_pinrange {
  * @gpio_ranges: An array of GPIO ranges in this community
  * @ngpio_ranges: Number of GPIO ranges
  * @nirqs: Total number of IRQs this community can generate
+ * @acpi_space_id: An address space ID for ACPI OpRegion handler
  */
 struct chv_community {
        const char *uid;
@@ -138,7 +128,7 @@ struct chv_community {
        size_t npins;
        const struct chv_pingroup *groups;
        size_t ngroups;
-       const struct chv_function *functions;
+       const struct intel_function *functions;
        size_t nfunctions;
        const struct chv_gpio_pinrange *gpio_ranges;
        size_t ngpio_ranges;
@@ -161,6 +151,8 @@ struct chv_pin_context {
  * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
  *             offset (in GPIO number space)
  * @community: Community this pinctrl instance represents
+ * @saved_intmask: Interrupt mask saved for system sleep
+ * @saved_pin_context: Pointer to a context of the pins saved for system sleep
  *
  * The first group in @groups is expected to contain all pins that can be
  * used as GPIOs.
@@ -184,7 +176,7 @@ struct chv_pinctrl {
                .invert_oe = (i),               \
        }
 
-#define PIN_GROUP(n, p, m, i)                  \
+#define PIN_GROUP_WITH_ALT(n, p, m, i)         \
        {                                       \
                .name = (n),                    \
                .pins = (p),                    \
@@ -204,13 +196,6 @@ struct chv_pinctrl {
                .noverrides = ARRAY_SIZE((o)),  \
        }
 
-#define FUNCTION(n, g)                         \
-       {                                       \
-               .name = (n),                    \
-               .groups = (g),                  \
-               .ngroups = ARRAY_SIZE((g)),     \
-       }
-
 #define GPIO_PINRANGE(start, end)              \
        {                                       \
                .base = (start),                \
@@ -282,7 +267,6 @@ static const struct pinctrl_pin_desc southwest_pins[] = {
        PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 };
 
-static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
@@ -298,7 +282,6 @@ static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
-static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 
 /* LPE I2S TXD pins need to have invert_oe set */
@@ -318,18 +301,18 @@ static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
 };
 
 static const struct chv_pingroup southwest_groups[] = {
-       PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
-       PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
-       PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
-       PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
-       PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
-       PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
-       PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
-       PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
-       PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
-       PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
-       PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
-       PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
+       PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false),
+       PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false),
+       PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false),
+       PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false),
+       PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true),
+       PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
 
        PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
                                southwest_lpe_altfuncs),
@@ -356,7 +339,7 @@ static const char * const southwest_spi3_groups[] = { "spi3_grp" };
  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
  * enabled only as GPIOs.
  */
-static const struct chv_function southwest_functions[] = {
+static const struct intel_function southwest_functions[] = {
        FUNCTION("uart0", southwest_uart0_groups),
        FUNCTION("uart1", southwest_uart1_groups),
        FUNCTION("uart2", southwest_uart2_groups),
@@ -610,13 +593,13 @@ static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 
 static const struct chv_pingroup southeast_groups[] = {
-       PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
-       PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
-       PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
-       PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
-       PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
-       PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
-       PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
+       PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false),
+       PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false),
+       PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
+       PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
+       PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
+       PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false),
+       PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false),
 };
 
 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
@@ -627,7 +610,7 @@ static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 
-static const struct chv_function southeast_functions[] = {
+static const struct intel_function southeast_functions[] = {
        FUNCTION("pwm0", southeast_pwm0_groups),
        FUNCTION("pwm1", southeast_pwm1_groups),
        FUNCTION("sdmmc1", southeast_sdmmc1_groups),
@@ -678,11 +661,11 @@ static const struct chv_community *chv_communities[] = {
  */
 static DEFINE_RAW_SPINLOCK(chv_lock);
 
-static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
-                               unsigned reg)
+static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
+                               unsigned int reg)
 {
-       unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
-       unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
+       unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
+       unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 
        offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
                 GPIO_REGS_SIZE * pad_no;
@@ -698,7 +681,7 @@ static void chv_writel(u32 value, void __iomem *reg)
 }
 
 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
-static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
+static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
 {
        void __iomem *reg;
 
@@ -714,15 +697,15 @@ static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 }
 
 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
-                                     unsigned group)
+                                     unsigned int group)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
        return pctrl->community->groups[group].name;
 }
 
-static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
-                             const unsigned **pins, unsigned *npins)
+static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
+                             const unsigned int **pins, unsigned int *npins)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -732,7 +715,7 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 }
 
 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
-                            unsigned offset)
+                            unsigned int offset)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        unsigned long flags;
@@ -779,7 +762,7 @@ static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 }
 
 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
-                                        unsigned function)
+                                        unsigned int function)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -787,9 +770,9 @@ static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 }
 
 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
-                                  unsigned function,
+                                  unsigned int function,
                                   const char * const **groups,
-                                  unsigned * const ngroups)
+                                  unsigned int * const ngroups)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -798,8 +781,8 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
        return 0;
 }
 
-static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
-                             unsigned group)
+static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
+                             unsigned int function, unsigned int group)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        const struct chv_pingroup *grp;
@@ -865,7 +848,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 
 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
                                   struct pinctrl_gpio_range *range,
-                                  unsigned offset)
+                                  unsigned int offset)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        unsigned long flags;
@@ -925,7 +908,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
                                  struct pinctrl_gpio_range *range,
-                                 unsigned offset)
+                                 unsigned int offset)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        unsigned long flags;
@@ -943,7 +926,7 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 
 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
                                  struct pinctrl_gpio_range *range,
-                                 unsigned offset, bool input)
+                                 unsigned int offset, bool input)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
@@ -974,7 +957,7 @@ static const struct pinmux_ops chv_pinmux_ops = {
        .gpio_set_direction = chv_gpio_set_direction,
 };
 
-static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
+static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
                          unsigned long *config)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -1054,7 +1037,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
        return 0;
 }
 
-static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
+static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
                               enum pin_config_param param, u32 arg)
 {
        void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
@@ -1141,8 +1124,8 @@ static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
        return 0;
 }
 
-static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
-                         unsigned long *configs, unsigned nconfigs)
+static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
+                         unsigned long *configs, unsigned int nconfigs)
 {
        struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        enum pin_config_param param;
@@ -1243,7 +1226,7 @@ static struct pinctrl_desc chv_pinctrl_desc = {
        .owner = THIS_MODULE,
 };
 
-static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
 {
        struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
        unsigned long flags;
@@ -1261,7 +1244,7 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
        return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
 }
 
-static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 {
        struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
        unsigned long flags;
@@ -1283,7 +1266,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
        raw_spin_unlock_irqrestore(&chv_lock, flags);
 }
 
-static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 {
        struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
        u32 ctrl0, direction;
@@ -1299,12 +1282,12 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
        return direction != CHV_PADCTRL0_GPIOCFG_GPO;
 }
 
-static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 {
        return pinctrl_gpio_direction_input(chip->base + offset);
 }
 
-static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
                                     int value)
 {
        chv_gpio_set(chip, offset, value);
@@ -1388,7 +1371,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
        if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
                struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
                struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
-               unsigned pin = irqd_to_hwirq(d);
+               unsigned int pin = irqd_to_hwirq(d);
                irq_flow_handler_t handler;
                unsigned long flags;
                u32 intsel, value;
@@ -1415,11 +1398,11 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
        return 0;
 }
 
-static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
+static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
-       unsigned pin = irqd_to_hwirq(d);
+       unsigned int pin = irqd_to_hwirq(d);
        unsigned long flags;
        u32 value;
 
index f321ab0d76e5bd6c0a44ad657d9ae5a70e90c1cc..88bc55281b8380da379b8e80fbbae881d4e2ed59 100644 (file)
@@ -9,7 +9,7 @@
 #include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -262,10 +262,7 @@ static int dnv_pinctrl_probe(struct platform_device *pdev)
        return intel_pinctrl_probe(pdev, &dnv_soc_data);
 }
 
-static const struct dev_pm_ops dnv_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
 
 static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
        { "INTC3000" },
index 5c4c96752fc1c16f71341e205a73424bd4a535e6..67600314454cea43f971455f461b9f7f98349bfa 100644 (file)
@@ -6,17 +6,17 @@
  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  */
 
-#include <linux/acpi.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
 
 #define GLK_PAD_OWN    0x020
-#define GLK_HOSTSW_OWN 0x0b0
 #define GLK_PADCFGLOCK 0x080
+#define GLK_HOSTSW_OWN 0x0b0
 #define GLK_GPI_IE     0x110
 
 #define GLK_COMMUNITY(s, e)                            \
@@ -58,16 +58,16 @@ static const struct pinctrl_pin_desc glk_northwest_pins[] = {
        PINCTRL_PIN(23, "GPIO_23"),
        PINCTRL_PIN(24, "GPIO_24"),
        PINCTRL_PIN(25, "GPIO_25"),
-       PINCTRL_PIN(26, "GPIO_26"),
-       PINCTRL_PIN(27, "GPIO_27"),
-       PINCTRL_PIN(28, "GPIO_28"),
-       PINCTRL_PIN(29, "GPIO_29"),
-       PINCTRL_PIN(30, "GPIO_30"),
-       PINCTRL_PIN(31, "GPIO_31"),
-       PINCTRL_PIN(32, "GPIO_32"),
-       PINCTRL_PIN(33, "GPIO_33"),
-       PINCTRL_PIN(34, "GPIO_34"),
-       PINCTRL_PIN(35, "GPIO_35"),
+       PINCTRL_PIN(26, "ISH_GPIO_0"),
+       PINCTRL_PIN(27, "ISH_GPIO_1"),
+       PINCTRL_PIN(28, "ISH_GPIO_2"),
+       PINCTRL_PIN(29, "ISH_GPIO_3"),
+       PINCTRL_PIN(30, "ISH_GPIO_4"),
+       PINCTRL_PIN(31, "ISH_GPIO_5"),
+       PINCTRL_PIN(32, "ISH_GPIO_6"),
+       PINCTRL_PIN(33, "ISH_GPIO_7"),
+       PINCTRL_PIN(34, "ISH_GPIO_8"),
+       PINCTRL_PIN(35, "ISH_GPIO_9"),
        PINCTRL_PIN(36, "GPIO_36"),
        PINCTRL_PIN(37, "GPIO_37"),
        PINCTRL_PIN(38, "GPIO_38"),
@@ -195,12 +195,12 @@ static const struct pinctrl_pin_desc glk_north_pins[] = {
        PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
        PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
        PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
-       PINCTRL_PIN(8, "LPSS_SPI_1_CLK"),
-       PINCTRL_PIN(9, "LPSS_SPI_1_FS0"),
-       PINCTRL_PIN(10, "LPSS_SPI_1_FS1"),
-       PINCTRL_PIN(11, "LPSS_SPI_1_FS2"),
-       PINCTRL_PIN(12, "LPSS_SPI_1_RXD"),
-       PINCTRL_PIN(13, "LPSS_SPI_1_TXD"),
+       PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
+       PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
+       PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
+       PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
+       PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
+       PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
        PINCTRL_PIN(14, "FST_SPI_CS0_B"),
        PINCTRL_PIN(15, "FST_SPI_CS1_B"),
        PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
@@ -215,8 +215,8 @@ static const struct pinctrl_pin_desc glk_north_pins[] = {
        PINCTRL_PIN(25, "PMU_SLP_S3_B"),
        PINCTRL_PIN(26, "PMU_SLP_S4_B"),
        PINCTRL_PIN(27, "SUSPWRDNACK"),
-       PINCTRL_PIN(28, "EMMC_PWR_EN_B"),
-       PINCTRL_PIN(29, "PMU_AC_PRESENT"),
+       PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
+       PINCTRL_PIN(29, "GPIO_105"),
        PINCTRL_PIN(30, "PMU_BATLOW_B"),
        PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
        PINCTRL_PIN(32, "PMU_SUSCLK"),
@@ -449,42 +449,15 @@ static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
 };
 
 static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
-       { "INT3453" },
+       { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
        { }
 };
 MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
 
-static int glk_pinctrl_probe(struct platform_device *pdev)
-{
-       const struct intel_pinctrl_soc_data *soc_data = NULL;
-       struct acpi_device *adev;
-       int i;
-
-       adev = ACPI_COMPANION(&pdev->dev);
-       if (!adev)
-               return -ENODEV;
-
-       for (i = 0; glk_pinctrl_soc_data[i]; i++) {
-               if (!strcmp(adev->pnp.unique_id,
-                           glk_pinctrl_soc_data[i]->uid)) {
-                       soc_data = glk_pinctrl_soc_data[i];
-                       break;
-               }
-       }
-
-       if (!soc_data)
-               return -ENODEV;
-
-       return intel_pinctrl_probe(pdev, soc_data);
-}
-
-static const struct dev_pm_ops glk_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
 
 static struct platform_driver glk_pinctrl_driver = {
-       .probe = glk_pinctrl_probe,
+       .probe = intel_pinctrl_probe_by_uid,
        .driver = {
                .name = "geminilake-pinctrl",
                .acpi_match_table = glk_pinctrl_acpi_match,
index 630b966ce081fd1a147a56559029998cc2297221..f33a5deafb97f68b5d6beeab04c9c45288d90e39 100644 (file)
@@ -10,7 +10,7 @@
 #include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -408,10 +408,7 @@ static int icl_pinctrl_probe(struct platform_device *pdev)
        return intel_pinctrl_probe(pdev, &icllp_soc_data);
 }
 
-static const struct dev_pm_ops icl_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
 
 static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
        { "INT3455" },
index 1ea3438ea67e925aa82b6e57e503efb72689fde3..8cda7b535b025ddde70b7d628cf8f2e07761306c 100644 (file)
@@ -7,11 +7,14 @@
  *          Mika Westerberg <mika.westerberg@linux.intel.com>
  */
 
+#include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/gpio/driver.h>
 #include <linux/log2.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
+
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
@@ -115,7 +118,7 @@ struct intel_pinctrl {
 #define padgroup_offset(g, p)  ((p) - (g)->base)
 
 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
-                                                  unsigned pin)
+                                                  unsigned int pin)
 {
        struct intel_community *community;
        int i;
@@ -133,7 +136,7 @@ static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 
 static const struct intel_padgroup *
 intel_community_get_padgroup(const struct intel_community *community,
-                            unsigned pin)
+                            unsigned int pin)
 {
        int i;
 
@@ -147,11 +150,11 @@ intel_community_get_padgroup(const struct intel_community *community,
        return NULL;
 }
 
-static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
-                                     unsigned reg)
+static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
+                                     unsigned int pin, unsigned int reg)
 {
        const struct intel_community *community;
-       unsigned padno;
+       unsigned int padno;
        size_t nregs;
 
        community = intel_get_community(pctrl, pin);
@@ -167,11 +170,11 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
        return community->pad_regs + reg + padno * nregs * 4;
 }
 
-static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
+static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 {
        const struct intel_community *community;
        const struct intel_padgroup *padgrp;
-       unsigned gpp, offset, gpp_offset;
+       unsigned int gpp, offset, gpp_offset;
        void __iomem *padown;
 
        community = intel_get_community(pctrl, pin);
@@ -192,11 +195,11 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
        return !(readl(padown) & PADOWN_MASK(gpp_offset));
 }
 
-static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
+static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 {
        const struct intel_community *community;
        const struct intel_padgroup *padgrp;
-       unsigned offset, gpp_offset;
+       unsigned int offset, gpp_offset;
        void __iomem *hostown;
 
        community = intel_get_community(pctrl, pin);
@@ -216,11 +219,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
        return !(readl(hostown) & BIT(gpp_offset));
 }
 
-static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
+static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 {
        struct intel_community *community;
        const struct intel_padgroup *padgrp;
-       unsigned offset, gpp_offset;
+       unsigned int offset, gpp_offset;
        u32 value;
 
        community = intel_get_community(pctrl, pin);
@@ -253,7 +256,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
        return false;
 }
 
-static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
+static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 {
        return intel_pad_owned_by_host(pctrl, pin) &&
                !intel_pad_locked(pctrl, pin);
@@ -267,15 +270,15 @@ static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 }
 
 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
-                                     unsigned group)
+                                     unsigned int group)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
        return pctrl->soc->groups[group].name;
 }
 
-static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
-                             const unsigned **pins, unsigned *npins)
+static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
+                             const unsigned int **pins, unsigned int *npins)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -285,7 +288,7 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 }
 
 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
-                              unsigned pin)
+                              unsigned int pin)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *padcfg;
@@ -344,7 +347,7 @@ static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 }
 
 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
-                                          unsigned function)
+                                          unsigned int function)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -352,9 +355,9 @@ static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 }
 
 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
-                                    unsigned function,
+                                    unsigned int function,
                                     const char * const **groups,
-                                    unsigned * const ngroups)
+                                    unsigned int * const ngroups)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
@@ -363,8 +366,8 @@ static int intel_get_function_groups(struct pinctrl_dev *pctldev,
        return 0;
 }
 
-static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
-                               unsigned group)
+static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
+                               unsigned int function, unsigned int group)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        const struct intel_pingroup *grp = &pctrl->soc->groups[group];
@@ -436,7 +439,7 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 
 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
                                     struct pinctrl_gpio_range *range,
-                                    unsigned pin)
+                                    unsigned int pin)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *padcfg0;
@@ -461,7 +464,7 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
                                    struct pinctrl_gpio_range *range,
-                                   unsigned pin, bool input)
+                                   unsigned int pin, bool input)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *padcfg0;
@@ -486,7 +489,7 @@ static const struct pinmux_ops intel_pinmux_ops = {
        .gpio_set_direction = intel_gpio_set_direction,
 };
 
-static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
+static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
                            unsigned long *config)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -575,11 +578,11 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
        return 0;
 }
 
-static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
+static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
                                 unsigned long config)
 {
-       unsigned param = pinconf_to_config_param(config);
-       unsigned arg = pinconf_to_config_argument(config);
+       unsigned int param = pinconf_to_config_param(config);
+       unsigned int arg = pinconf_to_config_argument(config);
        const struct intel_community *community;
        void __iomem *padcfg1;
        unsigned long flags;
@@ -653,8 +656,8 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
        return ret;
 }
 
-static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
-                                    unsigned debounce)
+static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
+                                    unsigned int pin, unsigned int debounce)
 {
        void __iomem *padcfg0, *padcfg2;
        unsigned long flags;
@@ -700,8 +703,8 @@ exit_unlock:
        return ret;
 }
 
-static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
-                         unsigned long *configs, unsigned nconfigs)
+static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
+                         unsigned long *configs, unsigned int nconfigs)
 {
        struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
        int i, ret;
@@ -751,14 +754,14 @@ static const struct pinctrl_desc intel_pinctrl_desc = {
  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
  * @pctrl: Pinctrl structure
  * @offset: GPIO offset from gpiolib
- * @commmunity: Community is filled here if not %NULL
+ * @community: Community is filled here if not %NULL
  * @padgrp: Pad group is filled here if not %NULL
  *
  * When coming through gpiolib irqchip, the GPIO offset is not
  * automatically translated to pinctrl pin number. This function can be
  * used to find out the corresponding pinctrl pin.
  */
-static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
+static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
                             const struct intel_community **community,
                             const struct intel_padgroup **padgrp)
 {
@@ -792,7 +795,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
        return -EINVAL;
 }
 
-static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 {
        struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
        void __iomem *reg;
@@ -814,7 +817,8 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
        return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 }
 
-static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
+                          int value)
 {
        struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
        unsigned long flags;
@@ -863,12 +867,12 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
        return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 }
 
-static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 {
        return pinctrl_gpio_direction_input(chip->base + offset);
 }
 
-static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
                                       int value)
 {
        intel_gpio_set(chip, offset, value);
@@ -897,7 +901,7 @@ static void intel_gpio_irq_ack(struct irq_data *d)
 
        pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
        if (pin >= 0) {
-               unsigned gpp, gpp_offset, is_offset;
+               unsigned int gpp, gpp_offset, is_offset;
 
                gpp = padgrp->reg_num;
                gpp_offset = padgroup_offset(padgrp, pin);
@@ -919,7 +923,7 @@ static void intel_gpio_irq_enable(struct irq_data *d)
 
        pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
        if (pin >= 0) {
-               unsigned gpp, gpp_offset, is_offset;
+               unsigned int gpp, gpp_offset, is_offset;
                unsigned long flags;
                u32 value;
 
@@ -948,7 +952,7 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 
        pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
        if (pin >= 0) {
-               unsigned gpp, gpp_offset;
+               unsigned int gpp, gpp_offset;
                unsigned long flags;
                void __iomem *reg;
                u32 value;
@@ -979,11 +983,11 @@ static void intel_gpio_irq_unmask(struct irq_data *d)
        intel_gpio_irq_mask_unmask(d, false);
 }
 
-static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
+static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
-       unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
+       unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
        unsigned long flags;
        void __iomem *reg;
        u32 value;
@@ -1040,7 +1044,7 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
-       unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
+       unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
 
        if (on)
                enable_irq_wake(pctrl->irq);
@@ -1135,7 +1139,7 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
 {
        const struct intel_community *community;
-       unsigned ngpio = 0;
+       unsigned int ngpio = 0;
        int i, j;
 
        for (i = 0; i < pctrl->ncommunities; i++) {
@@ -1211,8 +1215,8 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
                                       struct intel_community *community)
 {
        struct intel_padgroup *gpps;
-       unsigned npins = community->npins;
-       unsigned padown_num = 0;
+       unsigned int npins = community->npins;
+       unsigned int padown_num = 0;
        size_t ngpps, i;
 
        if (community->gpps)
@@ -1228,7 +1232,7 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
                if (community->gpps) {
                        gpps[i] = community->gpps[i];
                } else {
-                       unsigned gpp_size = community->gpp_size;
+                       unsigned int gpp_size = community->gpp_size;
 
                        gpps[i].reg_num = i;
                        gpps[i].base = community->pin_base + i * gpp_size;
@@ -1398,8 +1402,52 @@ int intel_pinctrl_probe(struct platform_device *pdev,
 }
 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
 
+int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
+{
+       const struct intel_pinctrl_soc_data *data;
+
+       data = device_get_match_data(&pdev->dev);
+       return intel_pinctrl_probe(pdev, data);
+}
+EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
+
+int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
+{
+       const struct intel_pinctrl_soc_data *data = NULL;
+       const struct intel_pinctrl_soc_data **table;
+       struct acpi_device *adev;
+       unsigned int i;
+
+       adev = ACPI_COMPANION(&pdev->dev);
+       if (adev) {
+               const void *match = device_get_match_data(&pdev->dev);
+
+               table = (const struct intel_pinctrl_soc_data **)match;
+               for (i = 0; table[i]; i++) {
+                       if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
+                               data = table[i];
+                               break;
+                       }
+               }
+       } else {
+               const struct platform_device_id *id;
+
+               id = platform_get_device_id(pdev);
+               if (!id)
+                       return -ENODEV;
+
+               table = (const struct intel_pinctrl_soc_data **)id->driver_data;
+               data = table[pdev->id];
+       }
+       if (!data)
+               return -ENODEV;
+
+       return intel_pinctrl_probe(pdev, data);
+}
+EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
+
 #ifdef CONFIG_PM_SLEEP
-static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
+static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
 {
        const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
 
@@ -1450,7 +1498,7 @@ int intel_pinctrl_suspend(struct device *dev)
        for (i = 0; i < pctrl->ncommunities; i++) {
                struct intel_community *community = &pctrl->communities[i];
                void __iomem *base;
-               unsigned gpp;
+               unsigned int gpp;
 
                base = community->regs + community->ie_offset;
                for (gpp = 0; gpp < community->ngpps; gpp++)
@@ -1468,7 +1516,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
        for (i = 0; i < pctrl->ncommunities; i++) {
                const struct intel_community *community;
                void __iomem *base;
-               unsigned gpp;
+               unsigned int gpp;
 
                community = &pctrl->communities[i];
                base = community->regs;
@@ -1532,7 +1580,7 @@ int intel_pinctrl_resume(struct device *dev)
        for (i = 0; i < pctrl->ncommunities; i++) {
                struct intel_community *community = &pctrl->communities[i];
                void __iomem *base;
-               unsigned gpp;
+               unsigned int gpp;
 
                base = community->regs + community->ie_offset;
                for (gpp = 0; gpp < community->ngpps; gpp++) {
index 1785abf157e4b3ed3ac3abcbf199a7b6d64c05b6..9fb4645f3c55821c09d3b33ed3df7e8a98abae86 100644 (file)
@@ -10,6 +10,8 @@
 #ifndef PINCTRL_INTEL_H
 #define PINCTRL_INTEL_H
 
+#include <linux/pm.h>
+
 struct pinctrl_pin_desc;
 struct platform_device;
 struct device;
@@ -25,10 +27,10 @@ struct device;
  */
 struct intel_pingroup {
        const char *name;
-       const unsigned *pins;
+       const unsigned int *pins;
        size_t npins;
        unsigned short mode;
-       const unsigned *modes;
+       const unsigned int *modes;
 };
 
 /**
@@ -56,11 +58,11 @@ struct intel_function {
  * to specify them.
  */
 struct intel_padgroup {
-       unsigned reg_num;
-       unsigned base;
-       unsigned size;
+       unsigned int reg_num;
+       unsigned int base;
+       unsigned int size;
        int gpio_base;
-       unsigned padown_num;
+       unsigned int padown_num;
 };
 
 /**
@@ -96,17 +98,17 @@ struct intel_padgroup {
  * pass custom @gpps and @ngpps instead.
  */
 struct intel_community {
-       unsigned barno;
-       unsigned padown_offset;
-       unsigned padcfglock_offset;
-       unsigned hostown_offset;
-       unsigned is_offset;
-       unsigned ie_offset;
-       unsigned pin_base;
-       unsigned gpp_size;
-       unsigned gpp_num_padown_regs;
+       unsigned int barno;
+       unsigned int padown_offset;
+       unsigned int padcfglock_offset;
+       unsigned int hostown_offset;
+       unsigned int is_offset;
+       unsigned int ie_offset;
+       unsigned int pin_base;
+       unsigned int gpp_size;
+       unsigned int gpp_num_padown_regs;
        size_t npins;
-       unsigned features;
+       unsigned int features;
        const struct intel_padgroup *gpps;
        size_t ngpps;
        /* Reserved for the core driver */
@@ -173,9 +175,17 @@ struct intel_pinctrl_soc_data {
 
 int intel_pinctrl_probe(struct platform_device *pdev,
                        const struct intel_pinctrl_soc_data *soc_data);
+int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
+int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
+
 #ifdef CONFIG_PM_SLEEP
 int intel_pinctrl_suspend(struct device *dev);
 int intel_pinctrl_resume(struct device *dev);
 #endif
 
+#define INTEL_PINCTRL_PM_OPS(_name)                                              \
+const struct dev_pm_ops _name = {                                                \
+       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, intel_pinctrl_resume) \
+}
+
 #endif /* PINCTRL_INTEL_H */
index 99894647edddc5ea1a9481f3112e970f34dd5f89..70ea9c51846079c998ff8244ec1e25ccab6d8eed 100644 (file)
@@ -9,7 +9,7 @@
 #include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -313,10 +313,7 @@ static int lbg_pinctrl_probe(struct platform_device *pdev)
        return intel_pinctrl_probe(pdev, &lbg_soc_data);
 }
 
-static const struct dev_pm_ops lbg_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
 
 static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
        { "INT3536" },
index 4fa69f988c7b780b95f4aaaf6cd64a617938507e..2e9988dac55f1d7980c5af2b9e7ede16857fec05 100644 (file)
@@ -476,6 +476,34 @@ static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin
        return family->regs + BUFCFG_OFFSET + bufno * 4;
 }
 
+static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
+{
+       void __iomem *bufcfg;
+
+       if (!mrfld_buf_available(mp, pin))
+               return -EBUSY;
+
+       bufcfg = mrfld_get_bufcfg(mp, pin);
+       *value = readl(bufcfg);
+
+       return 0;
+}
+
+static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
+                               u32 bits, u32 mask)
+{
+       void __iomem *bufcfg;
+       u32 value;
+
+       bufcfg = mrfld_get_bufcfg(mp, pin);
+       value = readl(bufcfg);
+
+       value &= ~mask;
+       value |= bits & mask;
+
+       writel(value, bufcfg);
+}
+
 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
 {
        struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
@@ -505,17 +533,15 @@ static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
                               unsigned int pin)
 {
        struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-       void __iomem *bufcfg;
        u32 value, mode;
+       int ret;
 
-       if (!mrfld_buf_available(mp, pin)) {
+       ret = mrfld_read_bufcfg(mp, pin, &value);
+       if (ret) {
                seq_puts(s, "not available");
                return;
        }
 
-       bufcfg = mrfld_get_bufcfg(mp, pin);
-       value = readl(bufcfg);
-
        mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
        if (!mode)
                seq_puts(s, "GPIO ");
@@ -559,21 +585,6 @@ static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
        return 0;
 }
 
-static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
-                               u32 bits, u32 mask)
-{
-       void __iomem *bufcfg;
-       u32 value;
-
-       bufcfg = mrfld_get_bufcfg(mp, pin);
-       value = readl(bufcfg);
-
-       value &= ~mask;
-       value |= bits & mask;
-
-       writel(value, bufcfg);
-}
-
 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
                                unsigned int function,
                                unsigned int group)
@@ -637,11 +648,12 @@ static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
        enum pin_config_param param = pinconf_to_config_param(*config);
        u32 value, term;
        u16 arg = 0;
+       int ret;
 
-       if (!mrfld_buf_available(mp, pin))
+       ret = mrfld_read_bufcfg(mp, pin, &value);
+       if (ret)
                return -ENOTSUPP;
 
-       value = readl(mrfld_get_bufcfg(mp, pin));
        term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
 
        switch (param) {
index 7984392104feeb420937f82dae794509e6afc4b6..38a7c811ff582c195909f417526d7610ca11c341 100644 (file)
@@ -7,10 +7,10 @@
  *          Mika Westerberg <mika.westerberg@linux.intel.com>
  */
 
-#include <linux/acpi.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
+
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-intel.h"
@@ -593,21 +593,10 @@ MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
 
 static int spt_pinctrl_probe(struct platform_device *pdev)
 {
-       const struct intel_pinctrl_soc_data *soc_data;
-       const struct acpi_device_id *id;
-
-       id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev);
-       if (!id || !id->driver_data)
-               return -ENODEV;
-
-       soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
-       return intel_pinctrl_probe(pdev, soc_data);
+       return intel_pinctrl_probe_by_hid(pdev);
 }
 
-static const struct dev_pm_ops spt_pinctrl_pm_ops = {
-       SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
-                                    intel_pinctrl_resume)
-};
+static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
 
 static struct platform_driver spt_pinctrl_driver = {
        .probe = spt_pinctrl_probe,
index 9905dc672f6bea8acbca58357b029dac219dbc83..9d142e1da56721933ea143549514b64fa2c36837 100644 (file)
@@ -3,7 +3,8 @@ menu "MediaTek pinctrl drivers"
 
 config EINT_MTK
        bool "MediaTek External Interrupt Support"
-       depends on PINCTRL_MTK || PINCTRL_MT7622 || COMPILE_TEST
+       depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST
+       select GPIOLIB
        select IRQ_DOMAIN
 
 config PINCTRL_MTK
@@ -15,6 +16,24 @@ config PINCTRL_MTK
        select EINT_MTK
        select OF_GPIO
 
+config PINCTRL_MTK_MOORE
+       bool "MediaTek Moore Core that implements generic binding"
+       depends on OF
+       select GENERIC_PINCONF
+       select GENERIC_PINCTRL_GROUPS
+       select GENERIC_PINMUX_FUNCTIONS
+       select GPIOLIB
+       select OF_GPIO
+
+config PINCTRL_MTK_PARIS
+       bool "MediaTek Paris Core that implements vendor binding"
+       depends on OF
+       select PINMUX
+       select GENERIC_PINCONF
+       select GPIOLIB
+       select EINT_MTK
+       select OF_GPIO
+
 # For ARMv7 SoCs
 config PINCTRL_MT2701
        bool "Mediatek MT2701 pin control"
@@ -23,6 +42,12 @@ config PINCTRL_MT2701
        default MACH_MT2701
        select PINCTRL_MTK
 
+config PINCTRL_MT7623
+       bool "Mediatek MT7623 pin control with generic binding"
+       depends on MACH_MT7623 || COMPILE_TEST
+       depends on PINCTRL_MTK_MOORE
+       default y
+
 config PINCTRL_MT8135
        bool "Mediatek MT8135 pin control"
        depends on MACH_MT8135 || COMPILE_TEST
@@ -45,15 +70,18 @@ config PINCTRL_MT2712
        default ARM64 && ARCH_MEDIATEK
        select PINCTRL_MTK
 
+config PINCTRL_MT6765
+       bool "Mediatek MT6765 pin control"
+       depends on OF
+       depends on ARM64 || COMPILE_TEST
+       default ARM64 && ARCH_MEDIATEK
+       select PINCTRL_MTK_PARIS
+
 config PINCTRL_MT7622
        bool "MediaTek MT7622 pin control"
-       depends on OF
        depends on ARM64 || COMPILE_TEST
-       select GENERIC_PINCONF
-       select GENERIC_PINCTRL_GROUPS
-       select GENERIC_PINMUX_FUNCTIONS
-       select GPIOLIB
-       select OF_GPIO
+       depends on PINCTRL_MTK_MOORE
+       default y
 
 config PINCTRL_MT8173
        bool "Mediatek MT8173 pin control"
@@ -62,6 +90,13 @@ config PINCTRL_MT8173
        default ARM64 && ARCH_MEDIATEK
        select PINCTRL_MTK
 
+config PINCTRL_MT8183
+       bool "Mediatek MT8183 pin control"
+       depends on OF
+       depends on ARM64 || COMPILE_TEST
+       default ARM64 && ARCH_MEDIATEK
+       select PINCTRL_MTK_PARIS
+
 # For PMIC
 config PINCTRL_MT6397
        bool "Mediatek MT6397 pin control"
index 3de7156df3454165b9fca68064772506a8e68602..70d800054f69426833bbb2e4ff71544b7c6ff3ed 100644 (file)
@@ -2,12 +2,17 @@
 # Core
 obj-$(CONFIG_EINT_MTK)         += mtk-eint.o
 obj-$(CONFIG_PINCTRL_MTK)      += pinctrl-mtk-common.o
+obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o
+obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o
 
 # SoC Drivers
 obj-$(CONFIG_PINCTRL_MT2701)   += pinctrl-mt2701.o
 obj-$(CONFIG_PINCTRL_MT2712)   += pinctrl-mt2712.o
 obj-$(CONFIG_PINCTRL_MT8135)   += pinctrl-mt8135.o
 obj-$(CONFIG_PINCTRL_MT8127)   += pinctrl-mt8127.o
+obj-$(CONFIG_PINCTRL_MT6765)   += pinctrl-mt6765.o
 obj-$(CONFIG_PINCTRL_MT7622)   += pinctrl-mt7622.o
+obj-$(CONFIG_PINCTRL_MT7623)   += pinctrl-mt7623.o
 obj-$(CONFIG_PINCTRL_MT8173)   += pinctrl-mt8173.o
+obj-$(CONFIG_PINCTRL_MT8183)   += pinctrl-mt8183.o
 obj-$(CONFIG_PINCTRL_MT6397)   += pinctrl-mt6397.o
index a613e546717a8d52d42d0b9e9872a9d565dc9e96..f464f8cd274b75c673e2a4f295798791e53e99b4 100644 (file)
@@ -11,7 +11,7 @@
 
 #include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/gpio.h>
+#include <linux/gpio/driver.h>
 #include <linux/io.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
index c286a9b940f2683809203700dc3588bcef8de114..48468d0fae686dff21cc8a8b2f0e8e55aabee352 100644 (file)
@@ -92,13 +92,13 @@ static inline int mtk_eint_do_resume(struct mtk_eint *eint)
        return -EOPNOTSUPP;
 }
 
-int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
+static inline int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
                          unsigned int debounce)
 {
        return -EOPNOTSUPP;
 }
 
-int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
+static inline int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
 {
        return -EOPNOTSUPP;
 }
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
new file mode 100644 (file)
index 0000000..3133ec0
--- /dev/null
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
+ * pinctrl-bindings.txt for MediaTek SoC.
+ *
+ * Copyright (C) 2017-2018 MediaTek Inc.
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#include <linux/gpio/driver.h>
+#include "pinctrl-moore.h"
+
+#define PINCTRL_PINCTRL_DEV            KBUILD_MODNAME
+
+/* Custom pinconf parameters */
+#define MTK_PIN_CONFIG_TDSEL   (PIN_CONFIG_END + 1)
+#define MTK_PIN_CONFIG_RDSEL   (PIN_CONFIG_END + 2)
+#define MTK_PIN_CONFIG_PU_ADV  (PIN_CONFIG_END + 3)
+#define MTK_PIN_CONFIG_PD_ADV  (PIN_CONFIG_END + 4)
+
+static const struct pinconf_generic_params mtk_custom_bindings[] = {
+       {"mediatek,tdsel",      MTK_PIN_CONFIG_TDSEL,           0},
+       {"mediatek,rdsel",      MTK_PIN_CONFIG_RDSEL,           0},
+       {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV,         1},
+       {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV,       1},
+};
+
+#ifdef CONFIG_DEBUG_FS
+static const struct pin_config_item mtk_conf_items[] = {
+       PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
+       PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
+       PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
+       PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
+};
+#endif
+
+static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
+                             unsigned int selector, unsigned int group)
+{
+       struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+       struct function_desc *func;
+       struct group_desc *grp;
+       int i;
+
+       func = pinmux_generic_get_function(pctldev, selector);
+       if (!func)
+               return -EINVAL;
+
+       grp = pinctrl_generic_get_group(pctldev, group);
+       if (!grp)
+               return -EINVAL;
+
+       dev_dbg(pctldev->dev, "enable function %s group %s\n",
+               func->name, grp->name);
+
+       for (i = 0; i < grp->num_pins; i++) {
+               const struct mtk_pin_desc *desc;
+               int *pin_modes = grp->data;
+               int pin = grp->pins[i];
+
+               desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+               mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+                                pin_modes[i]);
+       }
+
+       return 0;
+}
+
+static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+                                         struct pinctrl_gpio_range *range,
+                                         unsigned int pin)
+{
+       struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+       const struct mtk_pin_desc *desc;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+       return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+                               hw->soc->gpio_m);
+}
+
+static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+                                        struct pinctrl_gpio_range *range,
+                                        unsigned int pin, bool input)
+{
+       struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+       const struct mtk_pin_desc *desc;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+       /* hardware would take 0 as input direction */
+       return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
+}
+
+static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
+                          unsigned int pin, unsigned long *config)
+{
+       struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+       u32 param = pinconf_to_config_param(*config);
+       int val, val2, err, reg, ret = 1;
+       const struct mtk_pin_desc *desc;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+       switch (param) {
+       case PIN_CONFIG_BIAS_DISABLE:
+               if (hw->soc->bias_disable_get) {
+                       err = hw->soc->bias_disable_get(hw, desc, &ret);
+                       if (err)
+                               return err;
+               } else {
+                       return -ENOTSUPP;
+               }
+               break;
+       case PIN_CONFIG_BIAS_PULL_UP:
+               if (hw->soc->bias_get) {
+                       err = hw->soc->bias_get(hw, desc, 1, &ret);
+                       if (err)
+                               return err;
+               } else {
+                       return -ENOTSUPP;
+               }
+               break;
+       case PIN_CONFIG_BIAS_PULL_DOWN:
+               if (hw->soc->bias_get) {
+                       err = hw->soc->bias_get(hw, desc, 0, &ret);
+                       if (err)
+                               return err;
+               } else {
+                       return -ENOTSUPP;
+               }
+               break;
+       case PIN_CONFIG_SLEW_RATE:
+               err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
+               if (err)
+                       return err;
+
+               if (!val)
+                       return -EINVAL;
+
+               break;
+       case PIN_CONFIG_INPUT_ENABLE:
+       case PIN_CONFIG_OUTPUT_ENABLE:
+               err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
+               if (err)
+                       return err;
+
+               /* HW takes input mode as zero; output mode as non-zero */
+               if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
+                   (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
+                       return -EINVAL;
+
+               break;
+       case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+               err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
+               if (err)
+                       return err;
+
+               err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
+               if (err)
+                       return err;
+
+               if (val || !val2)
+                       return -EINVAL;
+
+               break;
+       case PIN_CONFIG_DRIVE_STRENGTH:
+               if (hw->soc->drive_get) {
+                       err = hw->soc->drive_get(hw, desc, &ret);
+                       if (err)
+                               return err;
+               } else {
+                       err = -ENOTSUPP;
+               }
+               break;
+       case MTK_PIN_CONFIG_TDSEL:
+       case MTK_PIN_CONFIG_RDSEL:
+               reg = (param == MTK_PIN_CONFIG_TDSEL) ?
+                      PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
+
+               err = mtk_hw_get_value(hw, desc, reg, &val);
+               if (err)
+                       return err;
+
+               ret = val;
+
+               break;
+       case MTK_PIN_CONFIG_PU_ADV:
+       case MTK_PIN_CONFIG_PD_ADV:
+               if (hw->soc->adv_pull_get) {
+                       bool pullup;
+
+                       pullup = param == MTK_PIN_CONFIG_PU_ADV;
+                       err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
+                       if (err)
+                               return err;
+               } else {
+                       return -ENOTSUPP;
+               }
+               break;
+       default:
+               return -ENOTSUPP;
+       }
+
+       *config = pinconf_to_config_packed(param, ret);
+
+       return 0;
+}
+
+static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+                          unsigned long *configs, unsigned int num_configs)
+{
+       struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
+       const struct mtk_pin_desc *desc;
+       u32 reg, param, arg;
+       int cfg, err = 0;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+
+       for (cfg = 0; cfg < num_configs; cfg++) {
+               param = pinconf_to_config_param(configs[cfg]);
+               arg = pinconf_to_config_argument(configs[cfg]);
+
+               switch (param) {
+               case PIN_CONFIG_BIAS_DISABLE:
+                       if (hw->soc->bias_disable_set) {
+                               err = hw->soc->bias_disable_set(hw, desc);
+                               if (err)
+                                       return err;
+                       } else {
+                               return -ENOTSUPP;
+                       }
+                       break;
+               case PIN_CONFIG_BIAS_PULL_UP:
+                       if (hw->soc->bias_set) {
+                               err = hw->soc->bias_set(hw, desc, 1);
+                               if (err)
+                                       return err;
+                       } else {
+                               return -ENOTSUPP;
+                       }
+                       break;
+               case PIN_CONFIG_BIAS_PULL_DOWN:
+                       if (hw->soc->bias_set) {
+                               err = hw->soc->bias_set(hw, desc, 0);
+                               if (err)
+                                       return err;
+                       } else {
+                               return -ENOTSUPP;
+                       }
+                       break;
+               case PIN_CONFIG_OUTPUT_ENABLE:
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
+                                              MTK_DISABLE);
+                       if (err)
+                               goto err;
+
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+                                              MTK_OUTPUT);
+                       if (err)
+                               goto err;
+                       break;
+               case PIN_CONFIG_INPUT_ENABLE:
+
+                       if (hw->soc->ies_present) {
+                               mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
+                                                MTK_ENABLE);
+                       }
+
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+                                              MTK_INPUT);
+                       if (err)
+                               goto err;
+                       break;
+               case PIN_CONFIG_SLEW_RATE:
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
+                                              arg);
+                       if (err)
+                               goto err;
+
+                       break;
+               case PIN_CONFIG_OUTPUT:
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+                                              MTK_OUTPUT);
+                       if (err)
+                               goto err;
+
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
+                                              arg);
+                       if (err)
+                               goto err;
+                       break;
+               case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                       /* arg = 1: Input mode & SMT enable ;
+                        * arg = 0: Output mode & SMT disable
+                        */
+                       arg = arg ? 2 : 1;
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+                                              arg & 1);
+                       if (err)
+                               goto err;
+
+                       err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
+                                              !!(arg & 2));
+                       if (err)
+                               goto err;
+                       break;
+               case PIN_CONFIG_DRIVE_STRENGTH:
+                       if (hw->soc->drive_set) {
+                               err = hw->soc->drive_set(hw, desc, arg);
+                       if (err)
+                               return err;
+                       } else {
+                               err = -ENOTSUPP;
+                       }
+                       break;
+               case MTK_PIN_CONFIG_TDSEL:
+               case MTK_PIN_CONFIG_RDSEL:
+                       reg = (param == MTK_PIN_CONFIG_TDSEL) ?
+                              PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
+
+                       err = mtk_hw_set_value(hw, desc, reg, arg);
+                       if (err)
+                               goto err;
+                       break;
+               case MTK_PIN_CONFIG_PU_ADV:
+               case MTK_PIN_CONFIG_PD_ADV:
+                       if (hw->soc->adv_pull_set) {
+                               bool pullup;
+
+                               pullup = param == MTK_PIN_CONFIG_PU_ADV;
+                               err = hw->soc->adv_pull_set(hw, desc, pullup,
+                                                           arg);
+                               if (err)
+                                       return err;
+                       } else {
+                               return -ENOTSUPP;
+                       }
+                       break;
+               default:
+                       err = -ENOTSUPP;
+               }
+       }
+err:
+       return err;
+}
+
+static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
+                                unsigned int group, unsigned long *config)
+{
+       const unsigned int *pins;
+       unsigned int i, npins, old = 0;
+       int ret;
+
+       ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < npins; i++) {
+               if (mtk_pinconf_get(pctldev, pins[i], config))
+                       return -ENOTSUPP;
+
+               /* configs do not match between two pins */
+               if (i && old != *config)
+                       return -ENOTSUPP;
+
+               old = *config;
+       }
+
+       return 0;
+}
+
+static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
+                                unsigned int group, unsigned long *configs,
+                                unsigned int num_configs)
+{
+       const unsigned int *pins;
+       unsigned int i, npins;
+       int ret;
+
+       ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < npins; i++) {
+               ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+static const struct pinctrl_ops mtk_pctlops = {
+       .get_groups_count = pinctrl_generic_get_group_count,
+       .get_group_name = pinctrl_generic_get_group_name,
+       .get_group_pins = pinctrl_generic_get_group_pins,
+       .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+       .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static const struct pinmux_ops mtk_pmxops = {
+       .get_functions_count = pinmux_generic_get_function_count,
+       .get_function_name = pinmux_generic_get_function_name,
+       .get_function_groups = pinmux_generic_get_function_groups,
+       .set_mux = mtk_pinmux_set_mux,
+       .gpio_request_enable = mtk_pinmux_gpio_request_enable,
+       .gpio_set_direction = mtk_pinmux_gpio_set_direction,
+       .strict = true,
+};
+
+static const struct pinconf_ops mtk_confops = {
+       .is_generic = true,
+       .pin_config_get = mtk_pinconf_get,
+       .pin_config_set = mtk_pinconf_set,
+       .pin_config_group_get = mtk_pinconf_group_get,
+       .pin_config_group_set = mtk_pinconf_group_set,
+       .pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
+static struct pinctrl_desc mtk_desc = {
+       .name = PINCTRL_PINCTRL_DEV,
+       .pctlops = &mtk_pctlops,
+       .pmxops = &mtk_pmxops,
+       .confops = &mtk_confops,
+       .owner = THIS_MODULE,
+};
+
+static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
+{
+       struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+       const struct mtk_pin_desc *desc;
+       int value, err;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+       err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
+       if (err)
+               return err;
+
+       return !!value;
+}
+
+static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
+{
+       struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+       const struct mtk_pin_desc *desc;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+
+       mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
+}
+
+static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
+{
+       return pinctrl_gpio_direction_input(chip->base + gpio);
+}
+
+static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
+                                    int value)
+{
+       mtk_gpio_set(chip, gpio, value);
+
+       return pinctrl_gpio_direction_output(chip->base + gpio);
+}
+
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+       struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+       const struct mtk_pin_desc *desc;
+
+       if (!hw->eint)
+               return -ENOTSUPP;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
+
+       if (desc->eint.eint_n == (u16)EINT_NA)
+               return -ENOTSUPP;
+
+       return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
+}
+
+static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+                              unsigned long config)
+{
+       struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+       const struct mtk_pin_desc *desc;
+       u32 debounce;
+
+       desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
+
+       if (!hw->eint ||
+           pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
+           desc->eint.eint_n == (u16)EINT_NA)
+               return -ENOTSUPP;
+
+       debounce = pinconf_to_config_argument(config);
+
+       return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
+}
+
+static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
+{
+       struct gpio_chip *chip = &hw->chip;
+       int ret;
+
+       chip->label             = PINCTRL_PINCTRL_DEV;
+       chip->parent            = hw->dev;
+       chip->request           = gpiochip_generic_request;
+       chip->free              = gpiochip_generic_free;
+       chip->direction_input   = mtk_gpio_direction_input;
+       chip->direction_output  = mtk_gpio_direction_output;
+       chip->get               = mtk_gpio_get;
+       chip->set               = mtk_gpio_set;
+       chip->to_irq            = mtk_gpio_to_irq,
+       chip->set_config        = mtk_gpio_set_config,
+       chip->base              = -1;
+       chip->ngpio             = hw->soc->npins;
+       chip->of_node           = np;
+       chip->of_gpio_n_cells   = 2;
+
+       ret = gpiochip_add_data(chip, hw);
+       if (ret < 0)
+               return ret;
+
+       /* Just for backward compatible for these old pinctrl nodes without
+        * "gpio-ranges" property. Otherwise, called directly from a
+        * DeviceTree-supported pinctrl driver is DEPRECATED.
+        * Please see Section 2.1 of
+        * Documentation/devicetree/bindings/gpio/gpio.txt on how to
+        * bind pinctrl and gpio drivers via the "gpio-ranges" property.
+        */
+       if (!of_find_property(np, "gpio-ranges", NULL)) {
+               ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
+                                            chip->ngpio);
+               if (ret < 0) {
+                       gpiochip_remove(chip);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+static int mtk_build_groups(struct mtk_pinctrl *hw)
+{
+       int err, i;
+
+       for (i = 0; i < hw->soc->ngrps; i++) {
+               const struct group_desc *group = hw->soc->grps + i;
+
+               err = pinctrl_generic_add_group(hw->pctrl, group->name,
+                                               group->pins, group->num_pins,
+                                               group->data);
+               if (err < 0) {
+                       dev_err(hw->dev, "Failed to register group %s\n",
+                               group->name);
+                       return err;
+               }
+       }
+
+       return 0;
+}
+
+static int mtk_build_functions(struct mtk_pinctrl *hw)
+{
+       int i, err;
+
+       for (i = 0; i < hw->soc->nfuncs ; i++) {
+               const struct function_desc *func = hw->soc->funcs + i;
+
+               err = pinmux_generic_add_function(hw->pctrl, func->name,
+                                                 func->group_names,
+                                                 func->num_group_names,
+                                                 func->data);
+               if (err < 0) {
+                       dev_err(hw->dev, "Failed to register function %s\n",
+                               func->name);
+                       return err;
+               }
+       }
+
+       return 0;
+}
+
+int mtk_moore_pinctrl_probe(struct platform_device *pdev,
+                           const struct mtk_pin_soc *soc)
+{
+       struct pinctrl_pin_desc *pins;
+       struct resource *res;
+       struct mtk_pinctrl *hw;
+       int err, i;
+
+       hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
+       if (!hw)
+               return -ENOMEM;
+
+       hw->soc = soc;
+       hw->dev = &pdev->dev;
+
+       if (!hw->soc->nbase_names) {
+               dev_err(&pdev->dev,
+                       "SoC should be assigned at least one register base\n");
+               return -EINVAL;
+       }
+
+       hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
+                                     sizeof(*hw->base), GFP_KERNEL);
+       if (!hw->base)
+               return -ENOMEM;
+
+       for (i = 0; i < hw->soc->nbase_names; i++) {
+               res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                                  hw->soc->base_names[i]);
+               if (!res) {
+                       dev_err(&pdev->dev, "missing IO resource\n");
+                       return -ENXIO;
+               }
+
+               hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
+               if (IS_ERR(hw->base[i]))
+                       return PTR_ERR(hw->base[i]);
+       }
+
+       hw->nbase = hw->soc->nbase_names;
+
+       /* Copy from internal struct mtk_pin_desc to register to the core */
+       pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
+                                 GFP_KERNEL);
+       if (!pins)
+               return -ENOMEM;
+
+       for (i = 0; i < hw->soc->npins; i++) {
+               pins[i].number = hw->soc->pins[i].number;
+               pins[i].name = hw->soc->pins[i].name;
+       }
+
+       /* Setup pins descriptions per SoC types */
+       mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
+       mtk_desc.npins = hw->soc->npins;
+       mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
+       mtk_desc.custom_params = mtk_custom_bindings;
+#ifdef CONFIG_DEBUG_FS
+       mtk_desc.custom_conf_items = mtk_conf_items;
+#endif
+
+       err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
+                                            &hw->pctrl);
+       if (err)
+               return err;
+
+       /* Setup groups descriptions per SoC types */
+       err = mtk_build_groups(hw);
+       if (err) {
+               dev_err(&pdev->dev, "Failed to build groups\n");
+               return err;
+       }
+
+       /* Setup functions descriptions per SoC types */
+       err = mtk_build_functions(hw);
+       if (err) {
+               dev_err(&pdev->dev, "Failed to build functions\n");
+               return err;
+       }
+
+       /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
+        * until all groups and functions are being added one.
+        */
+       err = pinctrl_enable(hw->pctrl);
+       if (err)
+               return err;
+
+       err = mtk_build_eint(hw, pdev);
+       if (err)
+               dev_warn(&pdev->dev,
+                        "Failed to add EINT, but pinctrl still can work\n");
+
+       /* Build gpiochip should be after pinctrl_enable is done */
+       err = mtk_build_gpiochip(hw, pdev->dev.of_node);
+       if (err) {
+               dev_err(&pdev->dev, "Failed to add gpio_chip\n");
+               return err;
+       }
+
+       platform_set_drvdata(pdev, hw);
+
+       return 0;
+}
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.h b/drivers/pinctrl/mediatek/pinctrl-moore.h
new file mode 100644 (file)
index 0000000..e1b4b82
--- /dev/null
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2018 MediaTek Inc.
+ *
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+#ifndef __PINCTRL_MOORE_H
+#define __PINCTRL_MOORE_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "mtk-eint.h"
+#include "pinctrl-mtk-common-v2.h"
+
+#define MTK_RANGE(_a)          { .range = (_a), .nranges = ARRAY_SIZE(_a), }
+
+#define MTK_PIN(_number, _name, _eint_m, _eint_n, _drv_n) {    \
+               .number = _number,                      \
+               .name = _name,                          \
+               .eint = {                               \
+                       .eint_m = _eint_m,              \
+                       .eint_n = _eint_n,              \
+               },                                      \
+               .drv_n = _drv_n,                        \
+               .funcs = NULL,                          \
+       }
+
+#define PINCTRL_PIN_GROUP(name, id)                    \
+       {                                               \
+               name,                                   \
+               id##_pins,                              \
+               ARRAY_SIZE(id##_pins),                  \
+               id##_funcs,                             \
+       }
+
+int mtk_moore_pinctrl_probe(struct platform_device *pdev,
+                           const struct mtk_pin_soc *soc);
+
+#endif /* __PINCTRL_MOORE_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
new file mode 100644 (file)
index 0000000..32451e8
--- /dev/null
@@ -0,0 +1,1108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: ZH Chen <zh.chen@mediatek.com>
+ *
+ */
+
+#include "pinctrl-mtk-mt6765.h"
+#include "pinctrl-paris.h"
+
+/* MT6765 have multiple bases to program pin configuration listed as the below:
+ * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
+ * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200,
+ * iocfg[6]:0x10002500, iocfg[7]:0x10002600.
+ * _i_base could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)    \
+       PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,      \
+                      _x_bits, 32, 0)
+
+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)   \
+       PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,      \
+                     _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt6765_pin_mode_range[] = {
+       PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_dir_range[] = {
+       PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_di_range[] = {
+       PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_do_range[] = {
+       PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_smt_range[] = {
+       PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
+       PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
+       PIN_FIELD_BASE(8, 8, 3, 0x0080, 0x10, 3, 1),
+       PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1),
+       PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 9, 1),
+       PINS_FIELD_BASE(13, 16, 6, 0x00b0, 0x10, 10, 1),
+       PINS_FIELD_BASE(17, 20, 6, 0x00b0, 0x10, 8, 1),
+       PINS_FIELD_BASE(21, 24, 6, 0x00b0, 0x10, 9, 1),
+       PINS_FIELD_BASE(25, 28, 6, 0x00b0, 0x10, 7, 1),
+       PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 0, 1),
+       PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 1, 1),
+       PINS_FIELD_BASE(31, 34, 6, 0x00b0, 0x10, 2, 1),
+       PINS_FIELD_BASE(35, 36, 6, 0x00b0, 0x10, 5, 1),
+       PIN_FIELD_BASE(37, 37, 6, 0x00b0, 0x10, 6, 1),
+       PIN_FIELD_BASE(38, 38, 6, 0x00b0, 0x10, 4, 1),
+       PINS_FIELD_BASE(39, 40, 6, 0x00b0, 0x10, 3, 1),
+       PINS_FIELD_BASE(41, 42, 7, 0x00c0, 0x10, 6, 1),
+       PIN_FIELD_BASE(43, 43, 7, 0x00c0, 0x10, 3, 1),
+       PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 4, 1),
+       PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 8, 1),
+       PINS_FIELD_BASE(46, 47, 7, 0x00c0, 0x10, 7, 1),
+       PIN_FIELD_BASE(48, 48, 7, 0x00c0, 0x10, 15, 1),
+       PIN_FIELD_BASE(49, 49, 7, 0x00c0, 0x10, 17, 1),
+       PIN_FIELD_BASE(50, 50, 7, 0x00c0, 0x10, 14, 1),
+       PIN_FIELD_BASE(51, 51, 7, 0x00c0, 0x10, 16, 1),
+       PINS_FIELD_BASE(52, 57, 7, 0x00c0, 0x10, 0, 1),
+       PINS_FIELD_BASE(58, 60, 7, 0x00c0, 0x10, 12, 1),
+       PINS_FIELD_BASE(61, 62, 3, 0x0080, 0x10, 5, 1),
+       PINS_FIELD_BASE(63, 64, 3, 0x0080, 0x10, 4, 1),
+       PINS_FIELD_BASE(65, 66, 3, 0x0080, 0x10, 7, 1),
+       PINS_FIELD_BASE(67, 68, 3, 0x0080, 0x10, 6, 1),
+       PINS_FIELD_BASE(69, 73, 3, 0x0080, 0x10, 1, 1),
+       PINS_FIELD_BASE(74, 78, 3, 0x0080, 0x10, 2, 1),
+       PINS_FIELD_BASE(79, 80, 3, 0x0080, 0x10, 0, 1),
+       PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 12, 1),
+       PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 11, 1),
+       PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 9, 1),
+       PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 10, 1),
+       PIN_FIELD_BASE(85, 85, 7, 0x00c0, 0x10, 12, 1),
+       PIN_FIELD_BASE(86, 86, 7, 0x00c0, 0x10, 13, 1),
+       PIN_FIELD_BASE(87, 87, 7, 0x00c0, 0x10, 2, 1),
+       PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 1, 1),
+       PIN_FIELD_BASE(89, 89, 2, 0x00b0, 0x10, 13, 1),
+       PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 8, 1),
+       PINS_FIELD_BASE(91, 92, 2, 0x00b0, 0x10, 8, 1),
+       PINS_FIELD_BASE(93, 94, 2, 0x00b0, 0x10, 7, 1),
+       PINS_FIELD_BASE(95, 96, 2, 0x00b0, 0x10, 14, 1),
+       PINS_FIELD_BASE(97, 98, 2, 0x00b0, 0x10, 2, 1),
+       PIN_FIELD_BASE(99, 99, 2, 0x00b0, 0x10, 0, 1),
+       PIN_FIELD_BASE(100, 100, 2, 0x00b0, 0x10, 1, 1),
+       PINS_FIELD_BASE(101, 102, 2, 0x00b0, 0x10, 3, 1),
+       PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 9, 1),
+       PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 11, 1),
+       PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 10, 1),
+       PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 12, 1),
+       PIN_FIELD_BASE(107, 107, 1, 0x0080, 0x10, 4, 1),
+       PIN_FIELD_BASE(108, 108, 1, 0x0080, 0x10, 3, 1),
+       PIN_FIELD_BASE(109, 109, 1, 0x0080, 0x10, 5, 1),
+       PIN_FIELD_BASE(110, 110, 1, 0x0080, 0x10, 0, 1),
+       PIN_FIELD_BASE(111, 111, 1, 0x0080, 0x10, 1, 1),
+       PIN_FIELD_BASE(112, 112, 1, 0x0080, 0x10, 2, 1),
+       PIN_FIELD_BASE(113, 113, 1, 0x0080, 0x10, 9, 1),
+       PIN_FIELD_BASE(114, 114, 1, 0x0080, 0x10, 10, 1),
+       PIN_FIELD_BASE(115, 115, 1, 0x0080, 0x10, 6, 1),
+       PIN_FIELD_BASE(116, 116, 1, 0x0080, 0x10, 7, 1),
+       PIN_FIELD_BASE(117, 117, 1, 0x0080, 0x10, 12, 1),
+       PIN_FIELD_BASE(118, 118, 1, 0x0080, 0x10, 13, 1),
+       PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 14, 1),
+       PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 11, 1),
+       PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 8, 1),
+       PIN_FIELD_BASE(122, 122, 4, 0x0080, 0x10, 2, 1),
+       PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 3, 1),
+       PIN_FIELD_BASE(124, 124, 4, 0x0080, 0x10, 1, 1),
+       PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 5, 1),
+       PIN_FIELD_BASE(126, 126, 4, 0x0080, 0x10, 7, 1),
+       PIN_FIELD_BASE(127, 127, 4, 0x0080, 0x10, 9, 1),
+       PIN_FIELD_BASE(128, 128, 4, 0x0080, 0x10, 4, 1),
+       PIN_FIELD_BASE(129, 129, 4, 0x0080, 0x10, 8, 1),
+       PIN_FIELD_BASE(130, 130, 4, 0x0080, 0x10, 10, 1),
+       PIN_FIELD_BASE(131, 131, 4, 0x0080, 0x10, 11, 1),
+       PIN_FIELD_BASE(132, 132, 4, 0x0080, 0x10, 6, 1),
+       PIN_FIELD_BASE(133, 133, 4, 0x0080, 0x10, 12, 1),
+       PIN_FIELD_BASE(134, 134, 5, 0x0060, 0x10, 11, 1),
+       PIN_FIELD_BASE(135, 135, 5, 0x0060, 0x10, 13, 1),
+       PIN_FIELD_BASE(136, 136, 5, 0x0060, 0x10, 1, 1),
+       PIN_FIELD_BASE(137, 137, 5, 0x0060, 0x10, 7, 1),
+       PIN_FIELD_BASE(138, 138, 5, 0x0060, 0x10, 4, 1),
+       PIN_FIELD_BASE(139, 139, 5, 0x0060, 0x10, 5, 1),
+       PIN_FIELD_BASE(140, 140, 5, 0x0060, 0x10, 0, 1),
+       PIN_FIELD_BASE(141, 141, 5, 0x0060, 0x10, 6, 1),
+       PIN_FIELD_BASE(142, 142, 5, 0x0060, 0x10, 2, 1),
+       PIN_FIELD_BASE(143, 143, 5, 0x0060, 0x10, 3, 1),
+       PINS_FIELD_BASE(144, 147, 5, 0x0060, 0x10, 10, 1),
+       PINS_FIELD_BASE(148, 149, 5, 0x0060, 0x10, 12, 1),
+       PINS_FIELD_BASE(150, 151, 7, 0x00c0, 0x10, 9, 1),
+       PINS_FIELD_BASE(152, 153, 7, 0x00c0, 0x10, 10, 1),
+       PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 11, 1),
+       PINS_FIELD_BASE(155, 158, 3, 0x0080, 0x10, 13, 1),
+       PIN_FIELD_BASE(159, 159, 7, 0x00c0, 0x10, 11, 1),
+       PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 8, 1),
+       PIN_FIELD_BASE(161, 161, 1, 0x0080, 0x10, 15, 1),
+       PIN_FIELD_BASE(162, 162, 1, 0x0080, 0x10, 16, 1),
+       PINS_FIELD_BASE(163, 170, 4, 0x0080, 0x10, 0, 1),
+       PINS_FIELD_BASE(171, 179, 7, 0x00c0, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_pd_range[] = {
+       PIN_FIELD_BASE(0, 0, 2, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(1, 1, 2, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(2, 2, 2, 0x0040, 0x10, 10, 1),
+       PIN_FIELD_BASE(3, 3, 2, 0x0040, 0x10, 11, 1),
+       PIN_FIELD_BASE(4, 4, 2, 0x0040, 0x10, 12, 1),
+       PIN_FIELD_BASE(5, 5, 2, 0x0040, 0x10, 13, 1),
+       PIN_FIELD_BASE(6, 6, 2, 0x0040, 0x10, 14, 1),
+       PIN_FIELD_BASE(7, 7, 2, 0x0040, 0x10, 15, 1),
+       PIN_FIELD_BASE(8, 8, 3, 0x0040, 0x10, 12, 1),
+       PIN_FIELD_BASE(9, 9, 2, 0x0040, 0x10, 16, 1),
+       PIN_FIELD_BASE(10, 10, 2, 0x0040, 0x10, 8, 1),
+       PIN_FIELD_BASE(11, 11, 2, 0x0040, 0x10, 9, 1),
+       PIN_FIELD_BASE(12, 12, 5, 0x0030, 0x10, 9, 1),
+       PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 14, 1),
+       PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 13, 1),
+       PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
+       PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 12, 1),
+       PIN_FIELD_BASE(17, 17, 6, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(18, 18, 6, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(19, 19, 6, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(20, 20, 6, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(21, 21, 6, 0x0040, 0x10, 10, 1),
+       PIN_FIELD_BASE(22, 22, 6, 0x0040, 0x10, 9, 1),
+       PIN_FIELD_BASE(23, 23, 6, 0x0040, 0x10, 11, 1),
+       PIN_FIELD_BASE(24, 24, 6, 0x0040, 0x10, 8, 1),
+       PIN_FIELD_BASE(25, 25, 6, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(26, 26, 6, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(27, 27, 6, 0x0040, 0x10, 3, 1),
+       PINS_FIELD_BASE(28, 40, 6, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(41, 41, 7, 0x0060, 0x10, 19, 1),
+       PIN_FIELD_BASE(42, 42, 7, 0x0060, 0x10, 9, 1),
+       PIN_FIELD_BASE(43, 43, 7, 0x0060, 0x10, 8, 1),
+       PIN_FIELD_BASE(44, 44, 7, 0x0060, 0x10, 10, 1),
+       PIN_FIELD_BASE(45, 45, 7, 0x0060, 0x10, 22, 1),
+       PIN_FIELD_BASE(46, 46, 7, 0x0060, 0x10, 21, 1),
+       PIN_FIELD_BASE(47, 47, 7, 0x0060, 0x10, 20, 1),
+       PIN_FIELD_BASE(48, 48, 7, 0x0070, 0x10, 3, 1),
+       PIN_FIELD_BASE(49, 49, 7, 0x0070, 0x10, 5, 1),
+       PIN_FIELD_BASE(50, 50, 7, 0x0070, 0x10, 2, 1),
+       PIN_FIELD_BASE(51, 51, 7, 0x0070, 0x10, 4, 1),
+       PIN_FIELD_BASE(52, 52, 7, 0x0060, 0x10, 1, 1),
+       PIN_FIELD_BASE(53, 53, 7, 0x0060, 0x10, 0, 1),
+       PIN_FIELD_BASE(54, 54, 7, 0x0060, 0x10, 5, 1),
+       PIN_FIELD_BASE(55, 55, 7, 0x0060, 0x10, 3, 1),
+       PIN_FIELD_BASE(56, 56, 7, 0x0060, 0x10, 4, 1),
+       PIN_FIELD_BASE(57, 57, 7, 0x0060, 0x10, 2, 1),
+       PIN_FIELD_BASE(58, 58, 7, 0x0070, 0x10, 0, 1),
+       PIN_FIELD_BASE(59, 59, 7, 0x0060, 0x10, 31, 1),
+       PIN_FIELD_BASE(60, 60, 7, 0x0060, 0x10, 30, 1),
+       PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 18, 1),
+       PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 14, 1),
+       PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 17, 1),
+       PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 13, 1),
+       PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 20, 1),
+       PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 16, 1),
+       PIN_FIELD_BASE(67, 67, 3, 0x0040, 0x10, 19, 1),
+       PIN_FIELD_BASE(68, 68, 3, 0x0040, 0x10, 15, 1),
+       PIN_FIELD_BASE(69, 69, 3, 0x0040, 0x10, 8, 1),
+       PIN_FIELD_BASE(70, 70, 3, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(71, 71, 3, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(72, 72, 3, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(73, 73, 3, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(74, 74, 3, 0x0040, 0x10, 3, 1),
+       PIN_FIELD_BASE(75, 75, 3, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(76, 76, 3, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(77, 77, 3, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(78, 78, 3, 0x0040, 0x10, 9, 1),
+       PIN_FIELD_BASE(79, 79, 3, 0x0040, 0x10, 11, 1),
+       PIN_FIELD_BASE(80, 80, 3, 0x0040, 0x10, 10, 1),
+       PIN_FIELD_BASE(81, 81, 3, 0x0040, 0x10, 25, 1),
+       PIN_FIELD_BASE(82, 82, 3, 0x0040, 0x10, 24, 1),
+       PIN_FIELD_BASE(83, 83, 3, 0x0040, 0x10, 22, 1),
+       PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 23, 1),
+       PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 1, 1),
+       PIN_FIELD_BASE(86, 86, 7, 0x0060, 0x10, 29, 1),
+       PIN_FIELD_BASE(87, 87, 7, 0x0060, 0x10, 7, 1),
+       PIN_FIELD_BASE(88, 88, 7, 0x0060, 0x10, 6, 1),
+       PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 21, 1),
+       PINS_FIELD_BASE(90, 94, 3, 0x0040, 0x10, 21, 1),
+       PIN_FIELD_BASE(95, 95, 2, 0x0040, 0x10, 22, 1),
+       PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 23, 1),
+       PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 3, 1),
+       PIN_FIELD_BASE(99, 99, 2, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(100, 100, 2, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(101, 101, 2, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(102, 102, 2, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(103, 103, 2, 0x0040, 0x10, 17, 1),
+       PIN_FIELD_BASE(104, 104, 2, 0x0040, 0x10, 19, 1),
+       PIN_FIELD_BASE(105, 105, 2, 0x0040, 0x10, 18, 1),
+       PIN_FIELD_BASE(106, 106, 2, 0x0040, 0x10, 20, 1),
+       PIN_FIELD_BASE(107, 107, 1, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(108, 108, 1, 0x0040, 0x10, 3, 1),
+       PIN_FIELD_BASE(109, 109, 1, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(110, 110, 1, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(111, 111, 1, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(112, 112, 1, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(113, 113, 1, 0x0040, 0x10, 9, 1),
+       PIN_FIELD_BASE(114, 114, 1, 0x0040, 0x10, 10, 1),
+       PIN_FIELD_BASE(115, 115, 1, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(116, 116, 1, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(117, 117, 1, 0x0040, 0x10, 12, 1),
+       PIN_FIELD_BASE(118, 118, 1, 0x0040, 0x10, 13, 1),
+       PIN_FIELD_BASE(119, 119, 1, 0x0040, 0x10, 14, 1),
+       PIN_FIELD_BASE(120, 120, 1, 0x0040, 0x10, 11, 1),
+       PINS_FIELD_BASE(121, 133, 1, 0x0040, 0x10, 8, 1),
+       PIN_FIELD_BASE(134, 134, 5, 0x0030, 0x10, 14, 1),
+       PIN_FIELD_BASE(135, 135, 5, 0x0030, 0x10, 19, 1),
+       PIN_FIELD_BASE(136, 136, 5, 0x0030, 0x10, 1, 1),
+       PIN_FIELD_BASE(137, 137, 5, 0x0030, 0x10, 7, 1),
+       PIN_FIELD_BASE(138, 138, 5, 0x0030, 0x10, 4, 1),
+       PIN_FIELD_BASE(139, 139, 5, 0x0030, 0x10, 5, 1),
+       PIN_FIELD_BASE(140, 140, 5, 0x0030, 0x10, 0, 1),
+       PIN_FIELD_BASE(141, 141, 5, 0x0030, 0x10, 6, 1),
+       PIN_FIELD_BASE(142, 142, 5, 0x0030, 0x10, 2, 1),
+       PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 3, 1),
+       PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 12, 1),
+       PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 11, 1),
+       PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 13, 1),
+       PIN_FIELD_BASE(147, 147, 5, 0x0030, 0x10, 10, 1),
+       PIN_FIELD_BASE(148, 148, 5, 0x0030, 0x10, 15, 1),
+       PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 16, 1),
+       PIN_FIELD_BASE(150, 150, 7, 0x0060, 0x10, 23, 1),
+       PIN_FIELD_BASE(151, 151, 7, 0x0060, 0x10, 24, 1),
+       PIN_FIELD_BASE(152, 152, 7, 0x0060, 0x10, 25, 1),
+       PIN_FIELD_BASE(153, 153, 7, 0x0060, 0x10, 26, 1),
+       PIN_FIELD_BASE(154, 154, 7, 0x0060, 0x10, 28, 1),
+       PIN_FIELD_BASE(155, 155, 3, 0x0040, 0x10, 28, 1),
+       PIN_FIELD_BASE(156, 156, 3, 0x0040, 0x10, 27, 1),
+       PIN_FIELD_BASE(157, 157, 3, 0x0040, 0x10, 29, 1),
+       PIN_FIELD_BASE(158, 158, 3, 0x0040, 0x10, 26, 1),
+       PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 27, 1),
+       PIN_FIELD_BASE(160, 160, 5, 0x0030, 0x10, 8, 1),
+       PIN_FIELD_BASE(161, 161, 1, 0x0040, 0x10, 15, 1),
+       PIN_FIELD_BASE(162, 162, 1, 0x0040, 0x10, 16, 1),
+       PIN_FIELD_BASE(163, 163, 4, 0x0020, 0x10, 0, 1),
+       PIN_FIELD_BASE(164, 164, 4, 0x0020, 0x10, 1, 1),
+       PIN_FIELD_BASE(165, 165, 4, 0x0020, 0x10, 2, 1),
+       PIN_FIELD_BASE(166, 166, 4, 0x0020, 0x10, 3, 1),
+       PIN_FIELD_BASE(167, 167, 4, 0x0020, 0x10, 4, 1),
+       PIN_FIELD_BASE(168, 168, 4, 0x0020, 0x10, 5, 1),
+       PIN_FIELD_BASE(169, 169, 4, 0x0020, 0x10, 6, 1),
+       PIN_FIELD_BASE(170, 170, 4, 0x0020, 0x10, 7, 1),
+       PIN_FIELD_BASE(171, 171, 7, 0x0060, 0x10, 17, 1),
+       PIN_FIELD_BASE(172, 172, 7, 0x0060, 0x10, 18, 1),
+       PIN_FIELD_BASE(173, 173, 7, 0x0060, 0x10, 11, 1),
+       PIN_FIELD_BASE(174, 174, 7, 0x0060, 0x10, 12, 1),
+       PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 13, 1),
+       PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 14, 1),
+       PIN_FIELD_BASE(177, 177, 7, 0x0060, 0x10, 15, 1),
+       PINS_FIELD_BASE(178, 179, 7, 0x0060, 0x10, 16, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_pu_range[] = {
+       PIN_FIELD_BASE(0, 0, 2, 0x0060, 0x10, 6, 1),
+       PIN_FIELD_BASE(1, 1, 2, 0x0060, 0x10, 7, 1),
+       PIN_FIELD_BASE(2, 2, 2, 0x0060, 0x10, 10, 1),
+       PIN_FIELD_BASE(3, 3, 2, 0x0060, 0x10, 11, 1),
+       PIN_FIELD_BASE(4, 4, 2, 0x0060, 0x10, 12, 1),
+       PIN_FIELD_BASE(5, 5, 2, 0x0060, 0x10, 13, 1),
+       PIN_FIELD_BASE(6, 6, 2, 0x0060, 0x10, 14, 1),
+       PIN_FIELD_BASE(7, 7, 2, 0x0060, 0x10, 15, 1),
+       PIN_FIELD_BASE(8, 8, 3, 0x0050, 0x10, 12, 1),
+       PIN_FIELD_BASE(9, 9, 2, 0x0060, 0x10, 16, 1),
+       PIN_FIELD_BASE(10, 10, 2, 0x0060, 0x10, 8, 1),
+       PIN_FIELD_BASE(11, 11, 2, 0x0060, 0x10, 9, 1),
+       PIN_FIELD_BASE(12, 12, 5, 0x0040, 0x10, 9, 1),
+       PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 14, 1),
+       PIN_FIELD_BASE(14, 14, 6, 0x0060, 0x10, 13, 1),
+       PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 15, 1),
+       PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 12, 1),
+       PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 7, 1),
+       PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 4, 1),
+       PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1),
+       PIN_FIELD_BASE(20, 20, 6, 0x0060, 0x10, 5, 1),
+       PIN_FIELD_BASE(21, 21, 6, 0x0060, 0x10, 10, 1),
+       PIN_FIELD_BASE(22, 22, 6, 0x0060, 0x10, 9, 1),
+       PIN_FIELD_BASE(23, 23, 6, 0x0060, 0x10, 11, 1),
+       PIN_FIELD_BASE(24, 24, 6, 0x0060, 0x10, 8, 1),
+       PIN_FIELD_BASE(25, 25, 6, 0x0060, 0x10, 2, 1),
+       PIN_FIELD_BASE(26, 26, 6, 0x0060, 0x10, 1, 1),
+       PIN_FIELD_BASE(27, 27, 6, 0x0060, 0x10, 3, 1),
+       PINS_FIELD_BASE(28, 40, 6, 0x0060, 0x10, 0, 1),
+       PIN_FIELD_BASE(41, 41, 7, 0x0080, 0x10, 19, 1),
+       PIN_FIELD_BASE(42, 42, 7, 0x0080, 0x10, 9, 1),
+       PIN_FIELD_BASE(43, 43, 7, 0x0080, 0x10, 8, 1),
+       PIN_FIELD_BASE(44, 44, 7, 0x0080, 0x10, 10, 1),
+       PIN_FIELD_BASE(45, 45, 7, 0x0080, 0x10, 22, 1),
+       PIN_FIELD_BASE(46, 46, 7, 0x0080, 0x10, 21, 1),
+       PIN_FIELD_BASE(47, 47, 7, 0x0080, 0x10, 20, 1),
+       PIN_FIELD_BASE(48, 48, 7, 0x0090, 0x10, 3, 1),
+       PIN_FIELD_BASE(49, 49, 7, 0x0090, 0x10, 5, 1),
+       PIN_FIELD_BASE(50, 50, 7, 0x0090, 0x10, 2, 1),
+       PIN_FIELD_BASE(51, 51, 7, 0x0090, 0x10, 4, 1),
+       PIN_FIELD_BASE(52, 52, 7, 0x0080, 0x10, 1, 1),
+       PIN_FIELD_BASE(53, 53, 7, 0x0080, 0x10, 0, 1),
+       PIN_FIELD_BASE(54, 54, 7, 0x0080, 0x10, 5, 1),
+       PIN_FIELD_BASE(55, 55, 7, 0x0080, 0x10, 3, 1),
+       PIN_FIELD_BASE(56, 56, 7, 0x0080, 0x10, 4, 1),
+       PIN_FIELD_BASE(57, 57, 7, 0x0080, 0x10, 2, 1),
+       PIN_FIELD_BASE(58, 58, 7, 0x0090, 0x10, 0, 1),
+       PIN_FIELD_BASE(59, 59, 7, 0x0080, 0x10, 31, 1),
+       PIN_FIELD_BASE(60, 60, 7, 0x0080, 0x10, 30, 1),
+       PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 18, 1),
+       PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 14, 1),
+       PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1),
+       PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 13, 1),
+       PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 20, 1),
+       PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 16, 1),
+       PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 19, 1),
+       PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 15, 1),
+       PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 8, 1),
+       PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 7, 1),
+       PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 6, 1),
+       PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 5, 1),
+       PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 4, 1),
+       PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1),
+       PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 2, 1),
+       PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 1, 1),
+       PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 0, 1),
+       PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 9, 1),
+       PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 11, 1),
+       PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 10, 1),
+       PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 25, 1),
+       PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 24, 1),
+       PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 22, 1),
+       PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 23, 1),
+       PIN_FIELD_BASE(85, 85, 7, 0x0090, 0x10, 1, 1),
+       PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 29, 1),
+       PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 7, 1),
+       PIN_FIELD_BASE(88, 88, 7, 0x0080, 0x10, 6, 1),
+       PIN_FIELD_BASE(89, 89, 2, 0x0060, 0x10, 21, 1),
+       PINS_FIELD_BASE(90, 94, 3, 0x0050, 0x10, 21, 1),
+       PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 22, 1),
+       PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 23, 1),
+       PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 2, 1),
+       PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 3, 1),
+       PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 0, 1),
+       PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 1, 1),
+       PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 4, 1),
+       PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 5, 1),
+       PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 17, 1),
+       PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 19, 1),
+       PIN_FIELD_BASE(105, 105, 2, 0x0060, 0x10, 18, 1),
+       PIN_FIELD_BASE(106, 106, 2, 0x0060, 0x10, 20, 1),
+       PIN_FIELD_BASE(107, 107, 1, 0x0050, 0x10, 4, 1),
+       PIN_FIELD_BASE(108, 108, 1, 0x0050, 0x10, 3, 1),
+       PIN_FIELD_BASE(109, 109, 1, 0x0050, 0x10, 5, 1),
+       PIN_FIELD_BASE(110, 110, 1, 0x0050, 0x10, 0, 1),
+       PIN_FIELD_BASE(111, 111, 1, 0x0050, 0x10, 1, 1),
+       PIN_FIELD_BASE(112, 112, 1, 0x0050, 0x10, 2, 1),
+       PIN_FIELD_BASE(113, 113, 1, 0x0050, 0x10, 9, 1),
+       PIN_FIELD_BASE(114, 114, 1, 0x0050, 0x10, 10, 1),
+       PIN_FIELD_BASE(115, 115, 1, 0x0050, 0x10, 6, 1),
+       PIN_FIELD_BASE(116, 116, 1, 0x0050, 0x10, 7, 1),
+       PIN_FIELD_BASE(117, 117, 1, 0x0050, 0x10, 12, 1),
+       PIN_FIELD_BASE(118, 118, 1, 0x0050, 0x10, 13, 1),
+       PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 14, 1),
+       PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 11, 1),
+       PINS_FIELD_BASE(121, 133, 1, 0x0050, 0x10, 8, 1),
+       PIN_FIELD_BASE(134, 134, 5, 0x0040, 0x10, 14, 1),
+       PIN_FIELD_BASE(135, 135, 5, 0x0040, 0x10, 19, 1),
+       PIN_FIELD_BASE(136, 136, 5, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(137, 137, 5, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(138, 138, 5, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(139, 139, 5, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(140, 140, 5, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(141, 141, 5, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(142, 142, 5, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 3, 1),
+       PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 12, 1),
+       PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 11, 1),
+       PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 13, 1),
+       PIN_FIELD_BASE(147, 147, 5, 0x0040, 0x10, 10, 1),
+       PIN_FIELD_BASE(148, 148, 5, 0x0040, 0x10, 15, 1),
+       PIN_FIELD_BASE(149, 149, 5, 0x0040, 0x10, 16, 1),
+       PIN_FIELD_BASE(150, 150, 7, 0x0080, 0x10, 23, 1),
+       PIN_FIELD_BASE(151, 151, 7, 0x0080, 0x10, 24, 1),
+       PIN_FIELD_BASE(152, 152, 7, 0x0080, 0x10, 25, 1),
+       PIN_FIELD_BASE(153, 153, 7, 0x0080, 0x10, 26, 1),
+       PIN_FIELD_BASE(154, 154, 7, 0x0080, 0x10, 28, 1),
+       PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 28, 1),
+       PIN_FIELD_BASE(156, 156, 3, 0x0050, 0x10, 27, 1),
+       PIN_FIELD_BASE(157, 157, 3, 0x0050, 0x10, 29, 1),
+       PIN_FIELD_BASE(158, 158, 3, 0x0050, 0x10, 26, 1),
+       PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 27, 1),
+       PIN_FIELD_BASE(160, 160, 5, 0x0040, 0x10, 8, 1),
+       PIN_FIELD_BASE(161, 161, 1, 0x0050, 0x10, 15, 1),
+       PIN_FIELD_BASE(162, 162, 1, 0x0050, 0x10, 16, 1),
+       PIN_FIELD_BASE(163, 163, 4, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(164, 164, 4, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(165, 165, 4, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(166, 166, 4, 0x0040, 0x10, 3, 1),
+       PIN_FIELD_BASE(167, 167, 4, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(168, 168, 4, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(169, 169, 4, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(170, 170, 4, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(171, 171, 7, 0x0080, 0x10, 17, 1),
+       PIN_FIELD_BASE(172, 172, 7, 0x0080, 0x10, 18, 1),
+       PIN_FIELD_BASE(173, 173, 7, 0x0080, 0x10, 11, 1),
+       PIN_FIELD_BASE(174, 174, 7, 0x0080, 0x10, 12, 1),
+       PIN_FIELD_BASE(175, 175, 7, 0x0080, 0x10, 13, 1),
+       PIN_FIELD_BASE(176, 176, 7, 0x0080, 0x10, 14, 1),
+       PIN_FIELD_BASE(177, 177, 7, 0x0080, 0x10, 15, 1),
+       PINS_FIELD_BASE(178, 179, 7, 0x0080, 0x10, 16, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_tdsel_range[] = {
+       PINS_FIELD_BASE(0, 3, 2, 0x00c0, 0x10, 16, 4),
+       PINS_FIELD_BASE(4, 7, 2, 0x00c0, 0x10, 20, 4),
+       PIN_FIELD_BASE(8, 8, 3, 0x0090, 0x10, 12, 4),
+       PINS_FIELD_BASE(9, 11, 2, 0x00c0, 0x10, 24, 4),
+       PIN_FIELD_BASE(12, 12, 5, 0x0080, 0x10, 4, 4),
+       PINS_FIELD_BASE(13, 16, 6, 0x00e0, 0x10, 8, 4),
+       PINS_FIELD_BASE(17, 20, 6, 0x00e0, 0x10, 0, 4),
+       PINS_FIELD_BASE(21, 24, 6, 0x00e0, 0x10, 4, 4),
+       PINS_FIELD_BASE(25, 28, 6, 0x00d0, 0x10, 28, 4),
+       PIN_FIELD_BASE(29, 29, 6, 0x00d0, 0x10, 0, 4),
+       PIN_FIELD_BASE(30, 30, 6, 0x00d0, 0x10, 4, 4),
+       PINS_FIELD_BASE(31, 34, 6, 0x00d0, 0x10, 8, 4),
+       PINS_FIELD_BASE(35, 36, 6, 0x00d0, 0x10, 20, 4),
+       PIN_FIELD_BASE(37, 37, 6, 0x00d0, 0x10, 24, 4),
+       PIN_FIELD_BASE(38, 38, 6, 0x00d0, 0x10, 16, 4),
+       PINS_FIELD_BASE(39, 40, 6, 0x00d0, 0x10, 12, 4),
+       PINS_FIELD_BASE(41, 42, 7, 0x00d0, 0x10, 24, 4),
+       PIN_FIELD_BASE(43, 43, 7, 0x00d0, 0x10, 12, 4),
+       PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 16, 4),
+       PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 0, 4),
+       PINS_FIELD_BASE(46, 47, 7, 0x00d0, 0x10, 28, 4),
+       PINS_FIELD_BASE(48, 49, 7, 0x00e0, 0x10, 28, 4),
+       PINS_FIELD_BASE(50, 51, 7, 0x00e0, 0x10, 24, 4),
+       PINS_FIELD_BASE(52, 57, 7, 0x00d0, 0x10, 0, 4),
+       PINS_FIELD_BASE(58, 60, 7, 0x00e0, 0x10, 16, 4),
+       PINS_FIELD_BASE(61, 62, 3, 0x0090, 0x10, 20, 4),
+       PINS_FIELD_BASE(63, 64, 3, 0x0090, 0x10, 16, 4),
+       PINS_FIELD_BASE(65, 66, 3, 0x0090, 0x10, 28, 4),
+       PINS_FIELD_BASE(67, 68, 3, 0x0090, 0x10, 24, 4),
+       PINS_FIELD_BASE(69, 73, 3, 0x0090, 0x10, 4, 4),
+       PINS_FIELD_BASE(74, 78, 3, 0x0090, 0x10, 8, 4),
+       PINS_FIELD_BASE(79, 80, 3, 0x0090, 0x10, 0, 4),
+       PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 8, 4),
+       PINS_FIELD_BASE(82, 83, 3, 0x00a0, 0x10, 4, 4),
+       PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 8, 4),
+       PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 16, 4),
+       PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 20, 4),
+       PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 8, 4),
+       PIN_FIELD_BASE(88, 88, 7, 0x00d0, 0x10, 4, 4),
+       PIN_FIELD_BASE(89, 89, 2, 0x00d0, 0x10, 12, 4),
+       PIN_FIELD_BASE(90, 90, 3, 0x00a0, 0x10, 0, 4),
+       PINS_FIELD_BASE(91, 92, 2, 0x00d0, 0x10, 0, 4),
+       PINS_FIELD_BASE(93, 94, 2, 0x00c0, 0x10, 28, 4),
+       PINS_FIELD_BASE(95, 96, 2, 0x00d0, 0x10, 16, 4),
+       PINS_FIELD_BASE(97, 98, 2, 0x00c0, 0x10, 8, 4),
+       PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 0, 4),
+       PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 4, 4),
+       PINS_FIELD_BASE(101, 102, 2, 0x00c0, 0x10, 12, 4),
+       PINS_FIELD_BASE(103, 104, 2, 0x00d0, 0x10, 4, 4),
+       PINS_FIELD_BASE(105, 106, 2, 0x00d0, 0x10, 8, 4),
+       PIN_FIELD_BASE(107, 107, 1, 0x0090, 0x10, 16, 4),
+       PIN_FIELD_BASE(108, 108, 1, 0x0090, 0x10, 12, 4),
+       PIN_FIELD_BASE(109, 109, 1, 0x0090, 0x10, 20, 4),
+       PIN_FIELD_BASE(110, 110, 1, 0x0090, 0x10, 0, 4),
+       PIN_FIELD_BASE(111, 111, 1, 0x0090, 0x10, 4, 4),
+       PIN_FIELD_BASE(112, 112, 1, 0x0090, 0x10, 8, 4),
+       PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 4, 4),
+       PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 8, 4),
+       PIN_FIELD_BASE(115, 115, 1, 0x0090, 0x10, 24, 4),
+       PIN_FIELD_BASE(116, 116, 1, 0x0090, 0x10, 28, 4),
+       PIN_FIELD_BASE(117, 117, 1, 0x00a0, 0x10, 16, 4),
+       PIN_FIELD_BASE(118, 118, 1, 0x00a0, 0x10, 20, 4),
+       PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 24, 4),
+       PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 12, 4),
+       PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 0, 4),
+       PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 8, 4),
+       PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 12, 4),
+       PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 4, 4),
+       PINS_FIELD_BASE(125, 130, 4, 0x0090, 0x10, 12, 4),
+       PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 16, 4),
+       PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 12, 4),
+       PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 20, 4),
+       PIN_FIELD_BASE(134, 134, 5, 0x0080, 0x10, 12, 4),
+       PIN_FIELD_BASE(135, 135, 5, 0x0080, 0x10, 20, 4),
+       PIN_FIELD_BASE(136, 136, 5, 0x0070, 0x10, 4, 4),
+       PIN_FIELD_BASE(137, 137, 5, 0x0070, 0x10, 28, 4),
+       PIN_FIELD_BASE(138, 138, 5, 0x0070, 0x10, 16, 4),
+       PIN_FIELD_BASE(139, 139, 5, 0x0070, 0x10, 20, 4),
+       PIN_FIELD_BASE(140, 140, 5, 0x0070, 0x10, 0, 4),
+       PIN_FIELD_BASE(141, 141, 5, 0x0070, 0x10, 24, 4),
+       PIN_FIELD_BASE(142, 142, 5, 0x0070, 0x10, 8, 4),
+       PIN_FIELD_BASE(143, 143, 5, 0x0070, 0x10, 12, 4),
+       PINS_FIELD_BASE(144, 147, 5, 0x0080, 0x10, 8, 4),
+       PINS_FIELD_BASE(148, 149, 5, 0x0080, 0x10, 16, 4),
+       PINS_FIELD_BASE(150, 151, 7, 0x00e0, 0x10, 4, 4),
+       PINS_FIELD_BASE(152, 153, 7, 0x00e0, 0x10, 8, 4),
+       PIN_FIELD_BASE(154, 154, 7, 0x00e0, 0x10, 12, 4),
+       PINS_FIELD_BASE(155, 158, 3, 0x00a0, 0x10, 12, 4),
+       PIN_FIELD_BASE(159, 159, 7, 0x00e0, 0x10, 12, 4),
+       PIN_FIELD_BASE(160, 160, 5, 0x0080, 0x10, 0, 4),
+       PINS_FIELD_BASE(161, 162, 1, 0x00a0, 0x10, 28, 4),
+       PINS_FIELD_BASE(163, 170, 4, 0x0090, 0x10, 0, 4),
+       PINS_FIELD_BASE(171, 179, 7, 0x00d0, 0x10, 20, 4),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_rdsel_range[] = {
+       PINS_FIELD_BASE(0, 3, 2, 0x0090, 0x10, 8, 2),
+       PINS_FIELD_BASE(4, 7, 2, 0x0090, 0x10, 10, 2),
+       PIN_FIELD_BASE(8, 8, 3, 0x0060, 0x10, 6, 2),
+       PINS_FIELD_BASE(9, 11, 2, 0x0090, 0x10, 12, 2),
+       PIN_FIELD_BASE(12, 12, 5, 0x0050, 0x10, 18, 2),
+       PINS_FIELD_BASE(13, 16, 6, 0x00a0, 0x10, 18, 2),
+       PINS_FIELD_BASE(17, 20, 6, 0x00a0, 0x10, 14, 2),
+       PINS_FIELD_BASE(21, 24, 6, 0x00a0, 0x10, 16, 2),
+       PINS_FIELD_BASE(25, 28, 6, 0x00a0, 0x10, 12, 2),
+       PIN_FIELD_BASE(29, 29, 6, 0x0090, 0x10, 0, 6),
+       PIN_FIELD_BASE(30, 30, 6, 0x0090, 0x10, 6, 6),
+       PINS_FIELD_BASE(31, 34, 6, 0x0090, 0x10, 12, 6),
+       PINS_FIELD_BASE(35, 36, 6, 0x00a0, 0x10, 0, 6),
+       PIN_FIELD_BASE(37, 37, 6, 0x00a0, 0x10, 6, 6),
+       PIN_FIELD_BASE(38, 38, 6, 0x0090, 0x10, 24, 6),
+       PINS_FIELD_BASE(39, 40, 6, 0x0090, 0x10, 18, 6),
+       PINS_FIELD_BASE(41, 42, 7, 0x00a0, 0x10, 12, 2),
+       PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 6, 2),
+       PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 8, 2),
+       PIN_FIELD_BASE(45, 45, 7, 0x00a0, 0x10, 16, 2),
+       PINS_FIELD_BASE(46, 47, 7, 0x00a0, 0x10, 14, 2),
+       PINS_FIELD_BASE(48, 49, 7, 0x00a0, 0x10, 30, 2),
+       PINS_FIELD_BASE(50, 51, 7, 0x00a0, 0x10, 28, 2),
+       PINS_FIELD_BASE(52, 57, 7, 0x00a0, 0x10, 0, 2),
+       PINS_FIELD_BASE(58, 60, 7, 0x00a0, 0x10, 24, 2),
+       PINS_FIELD_BASE(61, 62, 3, 0x0060, 0x10, 10, 2),
+       PINS_FIELD_BASE(63, 64, 3, 0x0060, 0x10, 8, 2),
+       PINS_FIELD_BASE(65, 66, 3, 0x0060, 0x10, 14, 2),
+       PINS_FIELD_BASE(67, 68, 3, 0x0060, 0x10, 12, 2),
+       PINS_FIELD_BASE(69, 73, 3, 0x0060, 0x10, 2, 2),
+       PINS_FIELD_BASE(74, 78, 3, 0x0060, 0x10, 4, 2),
+       PINS_FIELD_BASE(79, 80, 3, 0x0060, 0x10, 0, 2),
+       PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 20, 2),
+       PINS_FIELD_BASE(82, 83, 3, 0x0060, 0x10, 18, 2),
+       PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 20, 2),
+       PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 24, 2),
+       PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 26, 2),
+       PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 4, 2),
+       PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 2, 2),
+       PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 22, 2),
+       PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 16, 2),
+       PINS_FIELD_BASE(91, 92, 2, 0x0090, 0x10, 16, 2),
+       PINS_FIELD_BASE(93, 94, 2, 0x0090, 0x10, 14, 2),
+       PINS_FIELD_BASE(95, 96, 2, 0x0090, 0x10, 24, 2),
+       PINS_FIELD_BASE(97, 98, 2, 0x0090, 0x10, 4, 2),
+       PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 0, 2),
+       PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 2, 2),
+       PINS_FIELD_BASE(101, 102, 2, 0x0090, 0x10, 6, 2),
+       PINS_FIELD_BASE(103, 104, 2, 0x0090, 0x10, 18, 2),
+       PINS_FIELD_BASE(105, 106, 2, 0x0090, 0x10, 20, 2),
+       PIN_FIELD_BASE(107, 107, 1, 0x0060, 0x10, 8, 2),
+       PIN_FIELD_BASE(108, 108, 1, 0x0060, 0x10, 6, 2),
+       PIN_FIELD_BASE(109, 109, 1, 0x0060, 0x10, 10, 2),
+       PIN_FIELD_BASE(110, 110, 1, 0x0060, 0x10, 0, 2),
+       PIN_FIELD_BASE(111, 111, 1, 0x0060, 0x10, 2, 2),
+       PIN_FIELD_BASE(112, 112, 1, 0x0060, 0x10, 4, 2),
+       PIN_FIELD_BASE(113, 113, 1, 0x0060, 0x10, 18, 2),
+       PIN_FIELD_BASE(114, 114, 1, 0x0060, 0x10, 20, 2),
+       PIN_FIELD_BASE(115, 115, 1, 0x0060, 0x10, 12, 2),
+       PIN_FIELD_BASE(116, 116, 1, 0x0060, 0x10, 14, 2),
+       PIN_FIELD_BASE(117, 117, 1, 0x0060, 0x10, 24, 2),
+       PIN_FIELD_BASE(118, 118, 1, 0x0060, 0x10, 26, 2),
+       PIN_FIELD_BASE(119, 119, 1, 0x0060, 0x10, 28, 2),
+       PIN_FIELD_BASE(120, 120, 1, 0x0060, 0x10, 22, 2),
+       PIN_FIELD_BASE(121, 121, 1, 0x0060, 0x10, 16, 2),
+       PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 8, 6),
+       PIN_FIELD_BASE(123, 123, 4, 0x0070, 0x10, 14, 6),
+       PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 2, 6),
+       PINS_FIELD_BASE(125, 130, 4, 0x0070, 0x10, 14, 6),
+       PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 20, 6),
+       PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 14, 6),
+       PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 26, 6),
+       PIN_FIELD_BASE(134, 134, 5, 0x0050, 0x10, 22, 2),
+       PIN_FIELD_BASE(135, 135, 5, 0x0050, 0x10, 30, 2),
+       PIN_FIELD_BASE(136, 136, 5, 0x0050, 0x10, 2, 2),
+       PIN_FIELD_BASE(137, 137, 5, 0x0050, 0x10, 14, 2),
+       PIN_FIELD_BASE(138, 138, 5, 0x0050, 0x10, 8, 2),
+       PIN_FIELD_BASE(139, 139, 5, 0x0050, 0x10, 10, 2),
+       PIN_FIELD_BASE(140, 140, 5, 0x0050, 0x10, 0, 2),
+       PIN_FIELD_BASE(141, 141, 5, 0x0050, 0x10, 12, 2),
+       PIN_FIELD_BASE(142, 142, 5, 0x0050, 0x10, 4, 2),
+       PIN_FIELD_BASE(143, 143, 5, 0x0050, 0x10, 6, 2),
+       PINS_FIELD_BASE(144, 147, 5, 0x0050, 0x10, 20, 2),
+       PINS_FIELD_BASE(148, 149, 5, 0x0050, 0x10, 24, 2),
+       PINS_FIELD_BASE(150, 151, 7, 0x00a0, 0x10, 18, 2),
+       PINS_FIELD_BASE(152, 153, 7, 0x00a0, 0x10, 20, 2),
+       PIN_FIELD_BASE(154, 154, 7, 0x00a0, 0x10, 22, 2),
+       PINS_FIELD_BASE(155, 158, 3, 0x0060, 0x10, 22, 2),
+       PIN_FIELD_BASE(159, 159, 7, 0x00a0, 0x10, 22, 2),
+       PIN_FIELD_BASE(160, 160, 5, 0x0050, 0x10, 16, 2),
+       PINS_FIELD_BASE(161, 162, 1, 0x0060, 0x10, 30, 2),
+       PINS_FIELD_BASE(163, 170, 4, 0x0070, 0x10, 0, 2),
+       PINS_FIELD_BASE(171, 179, 7, 0x00a0, 0x10, 10, 2),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_drv_range[] = {
+       PINS_FIELD_BASE(0, 2, 2, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(3, 3, 2, 0x0000, 0x10, 15, 3),
+       PINS_FIELD_BASE(4, 6, 2, 0x0000, 0x10, 18, 3),
+       PIN_FIELD_BASE(7, 7, 2, 0x0000, 0x10, 21, 3),
+       PIN_FIELD_BASE(8, 8, 3, 0x0000, 0x10, 9, 3),
+       PINS_FIELD_BASE(9, 11, 2, 0x0000, 0x10, 24, 3),
+       PIN_FIELD_BASE(12, 12, 5, 0x0000, 0x10, 27, 3),
+       PINS_FIELD_BASE(13, 15, 6, 0x0010, 0x10, 3, 3),
+       PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 6, 3),
+       PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 23, 3),
+       PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 26, 3),
+       PINS_FIELD_BASE(19, 20, 6, 0x0000, 0x10, 23, 3),
+       PINS_FIELD_BASE(21, 23, 6, 0x0000, 0x10, 29, 3),
+       PIN_FIELD_BASE(24, 24, 6, 0x0010, 0x10, 0, 3),
+       PINS_FIELD_BASE(25, 27, 6, 0x0000, 0x10, 17, 3),
+       PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 20, 3),
+       PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 0, 3),
+       PIN_FIELD_BASE(30, 30, 6, 0x0000, 0x10, 3, 3),
+       PINS_FIELD_BASE(31, 34, 6, 0x0000, 0x10, 6, 3),
+       PINS_FIELD_BASE(35, 36, 6, 0x0000, 0x10, 13, 2),
+       PIN_FIELD_BASE(37, 37, 6, 0x0000, 0x10, 15, 2),
+       PIN_FIELD_BASE(38, 38, 6, 0x0000, 0x10, 11, 2),
+       PINS_FIELD_BASE(39, 40, 6, 0x0000, 0x10, 9, 2),
+       PINS_FIELD_BASE(41, 42, 7, 0x0000, 0x10, 21, 3),
+       PIN_FIELD_BASE(43, 43, 7, 0x0000, 0x10, 9, 3),
+       PIN_FIELD_BASE(44, 44, 7, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(45, 45, 7, 0x0000, 0x10, 27, 3),
+       PINS_FIELD_BASE(46, 47, 7, 0x0000, 0x10, 24, 3),
+       PINS_FIELD_BASE(48, 49, 7, 0x0010, 0x10, 18, 3),
+       PINS_FIELD_BASE(50, 51, 7, 0x0010, 0x10, 15, 3),
+       PINS_FIELD_BASE(52, 57, 7, 0x0000, 0x10, 0, 3),
+       PINS_FIELD_BASE(58, 60, 7, 0x0010, 0x10, 9, 3),
+       PINS_FIELD_BASE(61, 62, 3, 0x0000, 0x10, 15, 3),
+       PINS_FIELD_BASE(63, 64, 3, 0x0000, 0x10, 12, 3),
+       PINS_FIELD_BASE(65, 66, 3, 0x0000, 0x10, 21, 3),
+       PINS_FIELD_BASE(67, 68, 3, 0x0000, 0x10, 18, 3),
+       PINS_FIELD_BASE(69, 73, 3, 0x0000, 0x10, 3, 3),
+       PINS_FIELD_BASE(74, 78, 3, 0x0000, 0x10, 6, 3),
+       PINS_FIELD_BASE(79, 80, 3, 0x0000, 0x10, 0, 3),
+       PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 0, 3),
+       PINS_FIELD_BASE(82, 83, 3, 0x0000, 0x10, 27, 3),
+       PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 0, 3),
+       PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 9, 3),
+       PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 12, 3),
+       PIN_FIELD_BASE(87, 87, 7, 0x0000, 0x10, 6, 3),
+       PIN_FIELD_BASE(88, 88, 7, 0x0000, 0x10, 3, 3),
+       PIN_FIELD_BASE(89, 89, 2, 0x0010, 0x10, 15, 3),
+       PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 24, 3),
+       PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 6, 3),
+       PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3),
+       PIN_FIELD_BASE(93, 93, 2, 0x0000, 0x10, 27, 3),
+       PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 0, 3),
+       PINS_FIELD_BASE(95, 96, 2, 0x0010, 0x10, 18, 3),
+       PINS_FIELD_BASE(97, 98, 2, 0x0000, 0x10, 6, 3),
+       PIN_FIELD_BASE(99, 99, 2, 0x0000, 0x10, 0, 3),
+       PIN_FIELD_BASE(100, 100, 2, 0x0000, 0x10, 3, 3),
+       PINS_FIELD_BASE(101, 102, 2, 0x0000, 0x10, 9, 3),
+       PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 9, 3),
+       PINS_FIELD_BASE(105, 106, 2, 0x0010, 0x10, 12, 3),
+       PIN_FIELD_BASE(107, 107, 1, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(108, 108, 1, 0x0000, 0x10, 9, 3),
+       PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 15, 3),
+       PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 0, 3),
+       PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 3, 3),
+       PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 6, 3),
+       PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 27, 3),
+       PIN_FIELD_BASE(114, 114, 1, 0x0010, 0x10, 0, 3),
+       PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 18, 3),
+       PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 21, 3),
+       PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 6, 3),
+       PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 9, 3),
+       PIN_FIELD_BASE(119, 119, 1, 0x0010, 0x10, 12, 3),
+       PIN_FIELD_BASE(120, 120, 1, 0x0010, 0x10, 3, 3),
+       PIN_FIELD_BASE(121, 121, 1, 0x0000, 0x10, 24, 3),
+       PIN_FIELD_BASE(122, 122, 4, 0x0000, 0x10, 9, 3),
+       PIN_FIELD_BASE(123, 123, 4, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(124, 124, 4, 0x0000, 0x10, 6, 3),
+       PINS_FIELD_BASE(125, 130, 4, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 15, 3),
+       PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(133, 133, 4, 0x0000, 0x10, 18, 3),
+       PIN_FIELD_BASE(134, 134, 5, 0x0010, 0x10, 6, 3),
+       PIN_FIELD_BASE(135, 135, 5, 0x0010, 0x10, 12, 3),
+       PIN_FIELD_BASE(136, 136, 5, 0x0000, 0x10, 3, 3),
+       PIN_FIELD_BASE(137, 137, 5, 0x0000, 0x10, 21, 3),
+       PIN_FIELD_BASE(138, 138, 5, 0x0000, 0x10, 12, 3),
+       PIN_FIELD_BASE(139, 139, 5, 0x0000, 0x10, 15, 3),
+       PIN_FIELD_BASE(140, 140, 5, 0x0000, 0x10, 0, 3),
+       PIN_FIELD_BASE(141, 141, 5, 0x0000, 0x10, 18, 3),
+       PIN_FIELD_BASE(142, 142, 5, 0x0000, 0x10, 6, 3),
+       PIN_FIELD_BASE(143, 143, 5, 0x0000, 0x10, 9, 3),
+       PINS_FIELD_BASE(144, 146, 5, 0x0010, 0x10, 0, 3),
+       PIN_FIELD_BASE(147, 147, 5, 0x0010, 0x10, 3, 3),
+       PINS_FIELD_BASE(148, 149, 5, 0x0010, 0x10, 9, 3),
+       PINS_FIELD_BASE(150, 151, 7, 0x0010, 0x10, 0, 3),
+       PINS_FIELD_BASE(152, 153, 7, 0x0010, 0x10, 3, 3),
+       PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 6, 3),
+       PINS_FIELD_BASE(155, 157, 3, 0x0010, 0x10, 3, 3),
+       PIN_FIELD_BASE(158, 158, 3, 0x0010, 0x10, 6, 3),
+       PIN_FIELD_BASE(159, 159, 7, 0x0010, 0x10, 6, 3),
+       PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 24, 3),
+       PINS_FIELD_BASE(161, 162, 1, 0x0010, 0x10, 15, 3),
+       PINS_FIELD_BASE(163, 166, 4, 0x0000, 0x10, 0, 3),
+       PINS_FIELD_BASE(167, 170, 4, 0x0000, 0x10, 3, 3),
+       PINS_FIELD_BASE(171, 174, 7, 0x0000, 0x10, 18, 3),
+       PINS_FIELD_BASE(175, 179, 7, 0x0000, 0x10, 15, 3),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_pupd_range[] = {
+       PINS_FIELD_BASE(0, 28, 0, 0x0050, 0x10, 18, 1),
+       PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
+       PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
+       PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 5, 1),
+       PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 2, 1),
+       PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 4, 1),
+       PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 3, 1),
+       PIN_FIELD_BASE(35, 35, 6, 0x0050, 0x10, 10, 1),
+       PIN_FIELD_BASE(36, 36, 6, 0x0050, 0x10, 11, 1),
+       PIN_FIELD_BASE(37, 37, 6, 0x0050, 0x10, 9, 1),
+       PIN_FIELD_BASE(38, 38, 6, 0x0050, 0x10, 6, 1),
+       PIN_FIELD_BASE(39, 39, 6, 0x0050, 0x10, 8, 1),
+       PINS_FIELD_BASE(40, 90, 6, 0x0050, 0x10, 7, 1),
+       PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 3, 1),
+       PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 2, 1),
+       PIN_FIELD_BASE(93, 93, 2, 0x0050, 0x10, 0, 1),
+       PINS_FIELD_BASE(94, 121, 2, 0x0050, 0x10, 1, 1),
+       PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 1, 1),
+       PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 2, 1),
+       PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 0, 1),
+       PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 4, 1),
+       PIN_FIELD_BASE(126, 126, 4, 0x0030, 0x10, 6, 1),
+       PIN_FIELD_BASE(127, 127, 4, 0x0030, 0x10, 8, 1),
+       PIN_FIELD_BASE(128, 128, 4, 0x0030, 0x10, 3, 1),
+       PIN_FIELD_BASE(129, 129, 4, 0x0030, 0x10, 7, 1),
+       PIN_FIELD_BASE(130, 130, 4, 0x0030, 0x10, 9, 1),
+       PIN_FIELD_BASE(131, 131, 4, 0x0030, 0x10, 10, 1),
+       PIN_FIELD_BASE(132, 132, 4, 0x0030, 0x10, 5, 1),
+       PINS_FIELD_BASE(133, 179, 4, 0x0030, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_r0_range[] = {
+       PINS_FIELD_BASE(0, 28, 4, 0x0030, 0x10, 11, 1),
+       PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 0, 1),
+       PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 1, 1),
+       PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 5, 1),
+       PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 2, 1),
+       PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 4, 1),
+       PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 3, 1),
+       PIN_FIELD_BASE(35, 35, 6, 0x0070, 0x10, 10, 1),
+       PIN_FIELD_BASE(36, 36, 6, 0x0070, 0x10, 11, 1),
+       PIN_FIELD_BASE(37, 37, 6, 0x0070, 0x10, 9, 1),
+       PIN_FIELD_BASE(38, 38, 6, 0x0070, 0x10, 6, 1),
+       PIN_FIELD_BASE(39, 39, 6, 0x0070, 0x10, 8, 1),
+       PINS_FIELD_BASE(40, 90, 6, 0x0070, 0x10, 7, 1),
+       PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 3, 1),
+       PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 2, 1),
+       PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 0, 1),
+       PINS_FIELD_BASE(94, 121, 2, 0x0070, 0x10, 1, 1),
+       PIN_FIELD_BASE(122, 122, 4, 0x0050, 0x10, 1, 1),
+       PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1),
+       PIN_FIELD_BASE(124, 124, 4, 0x0050, 0x10, 0, 1),
+       PIN_FIELD_BASE(125, 125, 4, 0x0050, 0x10, 4, 1),
+       PIN_FIELD_BASE(126, 126, 4, 0x0050, 0x10, 6, 1),
+       PIN_FIELD_BASE(127, 127, 4, 0x0050, 0x10, 8, 1),
+       PIN_FIELD_BASE(128, 128, 4, 0x0050, 0x10, 3, 1),
+       PIN_FIELD_BASE(129, 129, 4, 0x0050, 0x10, 7, 1),
+       PIN_FIELD_BASE(130, 130, 4, 0x0050, 0x10, 9, 1),
+       PIN_FIELD_BASE(131, 131, 4, 0x0050, 0x10, 10, 1),
+       PIN_FIELD_BASE(132, 132, 4, 0x0050, 0x10, 5, 1),
+       PINS_FIELD_BASE(133, 179, 4, 0x0050, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_r1_range[] = {
+       PINS_FIELD_BASE(0, 28, 4, 0x0050, 0x10, 11, 1),
+       PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 0, 1),
+       PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
+       PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 5, 1),
+       PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 2, 1),
+       PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 4, 1),
+       PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 3, 1),
+       PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 10, 1),
+       PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 11, 1),
+       PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 9, 1),
+       PIN_FIELD_BASE(38, 38, 6, 0x0080, 0x10, 6, 1),
+       PIN_FIELD_BASE(39, 39, 6, 0x0080, 0x10, 8, 1),
+       PINS_FIELD_BASE(40, 90, 6, 0x0080, 0x10, 7, 1),
+       PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 3, 1),
+       PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1),
+       PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 0, 1),
+       PINS_FIELD_BASE(94, 121, 2, 0x0080, 0x10, 1, 1),
+       PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 1, 1),
+       PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 2, 1),
+       PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 0, 1),
+       PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 4, 1),
+       PIN_FIELD_BASE(126, 126, 4, 0x0060, 0x10, 6, 1),
+       PIN_FIELD_BASE(127, 127, 4, 0x0060, 0x10, 8, 1),
+       PIN_FIELD_BASE(128, 128, 4, 0x0060, 0x10, 3, 1),
+       PIN_FIELD_BASE(129, 129, 4, 0x0060, 0x10, 7, 1),
+       PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 9, 1),
+       PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 10, 1),
+       PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 5, 1),
+       PINS_FIELD_BASE(133, 179, 4, 0x0060, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt6765_pin_ies_range[] = {
+       PIN_FIELD_BASE(0, 0, 2, 0x0030, 0x10, 6, 1),
+       PIN_FIELD_BASE(1, 1, 2, 0x0030, 0x10, 7, 1),
+       PIN_FIELD_BASE(2, 2, 2, 0x0030, 0x10, 10, 1),
+       PIN_FIELD_BASE(3, 3, 2, 0x0030, 0x10, 11, 1),
+       PIN_FIELD_BASE(4, 4, 2, 0x0030, 0x10, 12, 1),
+       PIN_FIELD_BASE(5, 5, 2, 0x0030, 0x10, 13, 1),
+       PIN_FIELD_BASE(6, 6, 2, 0x0030, 0x10, 14, 1),
+       PIN_FIELD_BASE(7, 7, 2, 0x0030, 0x10, 15, 1),
+       PIN_FIELD_BASE(8, 8, 3, 0x0030, 0x10, 12, 1),
+       PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 16, 1),
+       PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 8, 1),
+       PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 9, 1),
+       PIN_FIELD_BASE(12, 12, 5, 0x0020, 0x10, 9, 1),
+       PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 26, 1),
+       PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 25, 1),
+       PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 27, 1),
+       PIN_FIELD_BASE(16, 16, 6, 0x0020, 0x10, 24, 1),
+       PIN_FIELD_BASE(17, 17, 6, 0x0020, 0x10, 19, 1),
+       PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 16, 1),
+       PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 18, 1),
+       PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 17, 1),
+       PIN_FIELD_BASE(21, 21, 6, 0x0020, 0x10, 22, 1),
+       PIN_FIELD_BASE(22, 22, 6, 0x0020, 0x10, 21, 1),
+       PIN_FIELD_BASE(23, 23, 6, 0x0020, 0x10, 23, 1),
+       PIN_FIELD_BASE(24, 24, 6, 0x0020, 0x10, 20, 1),
+       PIN_FIELD_BASE(25, 25, 6, 0x0020, 0x10, 14, 1),
+       PIN_FIELD_BASE(26, 26, 6, 0x0020, 0x10, 13, 1),
+       PIN_FIELD_BASE(27, 27, 6, 0x0020, 0x10, 15, 1),
+       PIN_FIELD_BASE(28, 28, 6, 0x0020, 0x10, 12, 1),
+       PIN_FIELD_BASE(29, 29, 6, 0x0020, 0x10, 0, 1),
+       PIN_FIELD_BASE(30, 30, 6, 0x0020, 0x10, 1, 1),
+       PIN_FIELD_BASE(31, 31, 6, 0x0020, 0x10, 5, 1),
+       PIN_FIELD_BASE(32, 32, 6, 0x0020, 0x10, 2, 1),
+       PIN_FIELD_BASE(33, 33, 6, 0x0020, 0x10, 4, 1),
+       PIN_FIELD_BASE(34, 34, 6, 0x0020, 0x10, 3, 1),
+       PIN_FIELD_BASE(35, 35, 6, 0x0020, 0x10, 10, 1),
+       PIN_FIELD_BASE(36, 36, 6, 0x0020, 0x10, 11, 1),
+       PIN_FIELD_BASE(37, 37, 6, 0x0020, 0x10, 9, 1),
+       PIN_FIELD_BASE(38, 38, 6, 0x0020, 0x10, 6, 1),
+       PIN_FIELD_BASE(39, 39, 6, 0x0020, 0x10, 8, 1),
+       PIN_FIELD_BASE(40, 40, 6, 0x0020, 0x10, 7, 1),
+       PIN_FIELD_BASE(41, 41, 7, 0x0040, 0x10, 19, 1),
+       PIN_FIELD_BASE(42, 42, 7, 0x0040, 0x10, 9, 1),
+       PIN_FIELD_BASE(43, 43, 7, 0x0040, 0x10, 8, 1),
+       PIN_FIELD_BASE(44, 44, 7, 0x0040, 0x10, 10, 1),
+       PIN_FIELD_BASE(45, 45, 7, 0x0040, 0x10, 22, 1),
+       PIN_FIELD_BASE(46, 46, 7, 0x0040, 0x10, 21, 1),
+       PIN_FIELD_BASE(47, 47, 7, 0x0040, 0x10, 20, 1),
+       PIN_FIELD_BASE(48, 48, 7, 0x0050, 0x10, 3, 1),
+       PIN_FIELD_BASE(49, 49, 7, 0x0050, 0x10, 5, 1),
+       PIN_FIELD_BASE(50, 50, 7, 0x0050, 0x10, 2, 1),
+       PIN_FIELD_BASE(51, 51, 7, 0x0050, 0x10, 4, 1),
+       PIN_FIELD_BASE(52, 52, 7, 0x0040, 0x10, 1, 1),
+       PIN_FIELD_BASE(53, 53, 7, 0x0040, 0x10, 0, 1),
+       PIN_FIELD_BASE(54, 54, 7, 0x0040, 0x10, 5, 1),
+       PIN_FIELD_BASE(55, 55, 7, 0x0040, 0x10, 3, 1),
+       PIN_FIELD_BASE(56, 56, 7, 0x0040, 0x10, 4, 1),
+       PIN_FIELD_BASE(57, 57, 7, 0x0040, 0x10, 2, 1),
+       PIN_FIELD_BASE(58, 58, 7, 0x0050, 0x10, 0, 1),
+       PIN_FIELD_BASE(59, 59, 7, 0x0040, 0x10, 31, 1),
+       PIN_FIELD_BASE(60, 60, 7, 0x0040, 0x10, 30, 1),
+       PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 18, 1),
+       PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 14, 1),
+       PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 17, 1),
+       PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 13, 1),
+       PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 20, 1),
+       PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 16, 1),
+       PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 19, 1),
+       PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 15, 1),
+       PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 8, 1),
+       PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 7, 1),
+       PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 6, 1),
+       PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 5, 1),
+       PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 4, 1),
+       PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1),
+       PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 2, 1),
+       PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 1, 1),
+       PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 0, 1),
+       PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 9, 1),
+       PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 11, 1),
+       PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 10, 1),
+       PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 25, 1),
+       PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 24, 1),
+       PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 22, 1),
+       PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 23, 1),
+       PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 1, 1),
+       PIN_FIELD_BASE(86, 86, 7, 0x0040, 0x10, 29, 1),
+       PIN_FIELD_BASE(87, 87, 7, 0x0040, 0x10, 7, 1),
+       PIN_FIELD_BASE(88, 88, 7, 0x0040, 0x10, 6, 1),
+       PIN_FIELD_BASE(89, 89, 2, 0x0030, 0x10, 25, 1),
+       PIN_FIELD_BASE(90, 90, 3, 0x0030, 0x10, 21, 1),
+       PIN_FIELD_BASE(91, 91, 2, 0x0030, 0x10, 20, 1),
+       PIN_FIELD_BASE(92, 92, 2, 0x0030, 0x10, 19, 1),
+       PIN_FIELD_BASE(93, 93, 2, 0x0030, 0x10, 17, 1),
+       PIN_FIELD_BASE(94, 94, 2, 0x0030, 0x10, 18, 1),
+       PIN_FIELD_BASE(95, 95, 2, 0x0030, 0x10, 26, 1),
+       PIN_FIELD_BASE(96, 96, 2, 0x0030, 0x10, 27, 1),
+       PIN_FIELD_BASE(97, 97, 2, 0x0030, 0x10, 2, 1),
+       PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 3, 1),
+       PIN_FIELD_BASE(99, 99, 2, 0x0030, 0x10, 0, 1),
+       PIN_FIELD_BASE(100, 100, 2, 0x0030, 0x10, 1, 1),
+       PIN_FIELD_BASE(101, 101, 2, 0x0030, 0x10, 4, 1),
+       PIN_FIELD_BASE(102, 102, 2, 0x0030, 0x10, 5, 1),
+       PIN_FIELD_BASE(103, 103, 2, 0x0030, 0x10, 21, 1),
+       PIN_FIELD_BASE(104, 104, 2, 0x0030, 0x10, 23, 1),
+       PIN_FIELD_BASE(105, 105, 2, 0x0030, 0x10, 22, 1),
+       PIN_FIELD_BASE(106, 106, 2, 0x0030, 0x10, 24, 1),
+       PIN_FIELD_BASE(107, 107, 1, 0x0030, 0x10, 4, 1),
+       PIN_FIELD_BASE(108, 108, 1, 0x0030, 0x10, 3, 1),
+       PIN_FIELD_BASE(109, 109, 1, 0x0030, 0x10, 5, 1),
+       PIN_FIELD_BASE(110, 110, 1, 0x0030, 0x10, 0, 1),
+       PIN_FIELD_BASE(111, 111, 1, 0x0030, 0x10, 1, 1),
+       PIN_FIELD_BASE(112, 112, 1, 0x0030, 0x10, 2, 1),
+       PIN_FIELD_BASE(113, 113, 1, 0x0030, 0x10, 9, 1),
+       PIN_FIELD_BASE(114, 114, 1, 0x0030, 0x10, 10, 1),
+       PIN_FIELD_BASE(115, 115, 1, 0x0030, 0x10, 6, 1),
+       PIN_FIELD_BASE(116, 116, 1, 0x0030, 0x10, 7, 1),
+       PIN_FIELD_BASE(117, 117, 1, 0x0030, 0x10, 12, 1),
+       PIN_FIELD_BASE(118, 118, 1, 0x0030, 0x10, 13, 1),
+       PIN_FIELD_BASE(119, 119, 1, 0x0030, 0x10, 14, 1),
+       PIN_FIELD_BASE(120, 120, 1, 0x0030, 0x10, 11, 1),
+       PIN_FIELD_BASE(121, 121, 1, 0x0030, 0x10, 8, 1),
+       PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 1),
+       PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 10, 1),
+       PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 8, 1),
+       PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 12, 1),
+       PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 14, 1),
+       PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 16, 1),
+       PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 11, 1),
+       PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 15, 1),
+       PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 17, 1),
+       PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 18, 1),
+       PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 13, 1),
+       PIN_FIELD_BASE(133, 133, 4, 0x0010, 0x10, 19, 1),
+       PIN_FIELD_BASE(134, 134, 5, 0x0020, 0x10, 14, 1),
+       PIN_FIELD_BASE(135, 135, 5, 0x0020, 0x10, 17, 1),
+       PIN_FIELD_BASE(136, 136, 5, 0x0020, 0x10, 1, 1),
+       PIN_FIELD_BASE(137, 137, 5, 0x0020, 0x10, 7, 1),
+       PIN_FIELD_BASE(138, 138, 5, 0x0020, 0x10, 4, 1),
+       PIN_FIELD_BASE(139, 139, 5, 0x0020, 0x10, 5, 1),
+       PIN_FIELD_BASE(140, 140, 5, 0x0020, 0x10, 0, 1),
+       PIN_FIELD_BASE(141, 141, 5, 0x0020, 0x10, 6, 1),
+       PIN_FIELD_BASE(142, 142, 5, 0x0020, 0x10, 2, 1),
+       PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 3, 1),
+       PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 12, 1),
+       PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 11, 1),
+       PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 13, 1),
+       PIN_FIELD_BASE(147, 147, 5, 0x0020, 0x10, 10, 1),
+       PIN_FIELD_BASE(148, 148, 5, 0x0020, 0x10, 15, 1),
+       PIN_FIELD_BASE(149, 149, 5, 0x0020, 0x10, 16, 1),
+       PIN_FIELD_BASE(150, 150, 7, 0x0040, 0x10, 23, 1),
+       PIN_FIELD_BASE(151, 151, 7, 0x0040, 0x10, 24, 1),
+       PIN_FIELD_BASE(152, 152, 7, 0x0040, 0x10, 25, 1),
+       PIN_FIELD_BASE(153, 153, 7, 0x0040, 0x10, 26, 1),
+       PIN_FIELD_BASE(154, 154, 7, 0x0040, 0x10, 28, 1),
+       PIN_FIELD_BASE(155, 155, 3, 0x0030, 0x10, 28, 1),
+       PIN_FIELD_BASE(156, 156, 3, 0x0030, 0x10, 27, 1),
+       PIN_FIELD_BASE(157, 157, 3, 0x0030, 0x10, 29, 1),
+       PIN_FIELD_BASE(158, 158, 3, 0x0030, 0x10, 26, 1),
+       PIN_FIELD_BASE(159, 159, 7, 0x0040, 0x10, 27, 1),
+       PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 8, 1),
+       PIN_FIELD_BASE(161, 161, 1, 0x0030, 0x10, 15, 1),
+       PIN_FIELD_BASE(162, 162, 1, 0x0030, 0x10, 16, 1),
+       PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 0, 1),
+       PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 1, 1),
+       PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 2, 1),
+       PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 1),
+       PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 4, 1),
+       PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 5, 1),
+       PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 6, 1),
+       PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 7, 1),
+       PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 17, 1),
+       PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 18, 1),
+       PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 11, 1),
+       PIN_FIELD_BASE(174, 174, 7, 0x0040, 0x10, 12, 1),
+       PIN_FIELD_BASE(175, 175, 7, 0x0040, 0x10, 13, 1),
+       PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 14, 1),
+       PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 15, 1),
+       PINS_FIELD_BASE(178, 179, 7, 0x0040, 0x10, 16, 1),
+};
+
+static const struct mtk_pin_reg_calc mt6765_reg_cals[PINCTRL_PIN_REG_MAX] = {
+       [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6765_pin_mode_range),
+       [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6765_pin_dir_range),
+       [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6765_pin_di_range),
+       [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6765_pin_do_range),
+       [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6765_pin_smt_range),
+       [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6765_pin_pd_range),
+       [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6765_pin_pu_range),
+       [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6765_pin_tdsel_range),
+       [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6765_pin_rdsel_range),
+       [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6765_pin_drv_range),
+       [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6765_pin_pupd_range),
+       [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6765_pin_r0_range),
+       [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6765_pin_r1_range),
+       [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6765_pin_ies_range),
+};
+
+static const char * const mt6765_pinctrl_register_base_names[] = {
+       "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5",
+       "iocfg6", "iocfg7",
+};
+
+static const struct mtk_eint_hw mt6765_eint_hw = {
+       .port_mask = 7,
+       .ports     = 6,
+       .ap_num    = 160,
+       .db_cnt    = 13,
+};
+
+static const struct mtk_pin_soc mt6765_data = {
+       .reg_cal = mt6765_reg_cals,
+       .pins = mtk_pins_mt6765,
+       .npins = ARRAY_SIZE(mtk_pins_mt6765),
+       .ngrps = ARRAY_SIZE(mtk_pins_mt6765),
+       .eint_hw = &mt6765_eint_hw,
+       .gpio_m = 0,
+       .ies_present = true,
+       .base_names = mt6765_pinctrl_register_base_names,
+       .nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names),
+       .bias_disable_set = mtk_pinconf_bias_disable_set,
+       .bias_disable_get = mtk_pinconf_bias_disable_get,
+       .bias_set = mtk_pinconf_bias_set,
+       .bias_get = mtk_pinconf_bias_get,
+       .drive_set = mtk_pinconf_drive_set_rev1,
+       .drive_get = mtk_pinconf_drive_get_rev1,
+       .adv_pull_get = mtk_pinconf_adv_pull_get,
+       .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt6765_pinctrl_of_match[] = {
+       { .compatible = "mediatek,mt6765-pinctrl", },
+       { }
+};
+
+static int mt6765_pinctrl_probe(struct platform_device *pdev)
+{
+       return mtk_paris_pinctrl_probe(pdev, &mt6765_data);
+}
+
+static struct platform_driver mt6765_pinctrl_driver = {
+       .driver = {
+               .name = "mt6765-pinctrl",
+               .of_match_table = mt6765_pinctrl_of_match,
+       },
+       .probe = mt6765_pinctrl_probe,
+};
+
+static int __init mt6765_pinctrl_init(void)
+{
+       return platform_driver_register(&mt6765_pinctrl_driver);
+}
+arch_initcall(mt6765_pinctrl_init);
index 6f931b85701b5f772f6dbd5ec24d2f02dd91fd4c..ce4a8a0cc19cb588c752dba5c3de2264331e8668 100644 (file)
+// SPDX-License-Identifier: GPL-2.0
 /*
- * MediaTek MT7622 Pinctrl Driver
+ * Copyright (C) 2017-2018 MediaTek Inc.
  *
- * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
+ * Author: Sean Wang <sean.wang@mediatek.com>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/gpio.h>
-#include <linux/gpio/driver.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/regmap.h>
-
-#include "../core.h"
-#include "../pinconf.h"
-#include "../pinmux.h"
-#include "mtk-eint.h"
-
-#define PINCTRL_PINCTRL_DEV            KBUILD_MODNAME
-#define MTK_RANGE(_a)          { .range = (_a), .nranges = ARRAY_SIZE(_a), }
-#define PINCTRL_PIN_GROUP(name, id)                    \
-       {                                               \
-               name,                                   \
-               id##_pins,                              \
-               ARRAY_SIZE(id##_pins),                  \
-               id##_funcs,                             \
-       }
-
-#define MTK_GPIO_MODE  1
-#define MTK_INPUT      0
-#define MTK_OUTPUT     1
-#define MTK_DISABLE    0
-#define MTK_ENABLE     1
-
-/* Custom pinconf parameters */
-#define MTK_PIN_CONFIG_TDSEL   (PIN_CONFIG_END + 1)
-#define MTK_PIN_CONFIG_RDSEL   (PIN_CONFIG_END + 2)
-
-/* List these attributes which could be modified for the pin */
-enum {
-       PINCTRL_PIN_REG_MODE,
-       PINCTRL_PIN_REG_DIR,
-       PINCTRL_PIN_REG_DI,
-       PINCTRL_PIN_REG_DO,
-       PINCTRL_PIN_REG_SR,
-       PINCTRL_PIN_REG_SMT,
-       PINCTRL_PIN_REG_PD,
-       PINCTRL_PIN_REG_PU,
-       PINCTRL_PIN_REG_E4,
-       PINCTRL_PIN_REG_E8,
-       PINCTRL_PIN_REG_TDSEL,
-       PINCTRL_PIN_REG_RDSEL,
-       PINCTRL_PIN_REG_MAX,
-};
-
-/* struct mtk_pin_field - the structure that holds the information of the field
- *                       used to describe the attribute for the pin
- * @offset:            the register offset relative to the base address
- * @mask:              the mask used to filter out the field from the register
- * @bitpos:            the start bit relative to the register
- * @next:              the indication that the field would be extended to the
-                       next register
  */
-struct mtk_pin_field {
-       u32 offset;
-       u32 mask;
-       u8  bitpos;
-       u8  next;
-};
 
-/* struct mtk_pin_field_calc - the structure that holds the range providing
- *                            the guide used to look up the relevant field
- * @s_pin:             the start pin within the range
- * @e_pin:             the end pin within the range
- * @s_addr:            the start address for the range
- * @x_addrs:           the address distance between two consecutive registers
- *                     within the range
- * @s_bit:             the start bit for the first register within the range
- * @x_bits:            the bit distance between two consecutive pins within
- *                     the range
- */
-struct mtk_pin_field_calc {
-       u16 s_pin;
-       u16 e_pin;
-       u32 s_addr;
-       u8  x_addrs;
-       u8  s_bit;
-       u8  x_bits;
-};
+#include "pinctrl-moore.h"
 
-/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
- *                          determine which register the pin would make use of
- *                          for certain pin attribute.
- * @range:                  the start address for the range
- * @nranges:                the number of items in the range
- */
-struct mtk_pin_reg_calc {
-       const struct mtk_pin_field_calc *range;
-       unsigned int nranges;
-};
-
-/* struct mtk_pin_soc - the structure that holds SoC-specific data */
-struct mtk_pin_soc {
-       const struct mtk_pin_reg_calc   *reg_cal;
-       const struct pinctrl_pin_desc   *pins;
-       unsigned int                    npins;
-       const struct group_desc         *grps;
-       unsigned int                    ngrps;
-       const struct function_desc      *funcs;
-       unsigned int                    nfuncs;
-       const struct mtk_eint_regs      *eint_regs;
-       const struct mtk_eint_hw        *eint_hw;
-};
-
-struct mtk_pinctrl {
-       struct pinctrl_dev              *pctrl;
-       void __iomem                    *base;
-       struct device                   *dev;
-       struct gpio_chip                chip;
-       const struct mtk_pin_soc        *soc;
-       struct mtk_eint                 *eint;
-};
+#define MT7622_PIN(_number, _name)                                     \
+       MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
 
 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
-       {0, 0, 0x320, 0x10, 16, 4},
-       {1, 4, 0x3a0, 0x10,  16, 4},
-       {5, 5, 0x320, 0x10,  0, 4},
-       {6, 6, 0x300, 0x10,  4, 4},
-       {7, 7, 0x300, 0x10,  4, 4},
-       {8, 9, 0x350, 0x10,  20, 4},
-       {10, 10, 0x300, 0x10, 8, 4},
-       {11, 11, 0x300, 0x10, 8, 4},
-       {12, 12, 0x300, 0x10, 8, 4},
-       {13, 13, 0x300, 0x10, 8, 4},
-       {14, 15, 0x320, 0x10, 4, 4},
-       {16, 17, 0x320, 0x10, 20, 4},
-       {18, 21, 0x310, 0x10, 16, 4},
-       {22, 22, 0x380, 0x10, 16, 4},
-       {23, 23, 0x300, 0x10, 24, 4},
-       {24, 24, 0x300, 0x10, 24, 4},
-       {25, 25, 0x300, 0x10, 12, 4},
-       {25, 25, 0x300, 0x10, 12, 4},
-       {26, 26, 0x300, 0x10, 12, 4},
-       {27, 27, 0x300, 0x10, 12, 4},
-       {28, 28, 0x300, 0x10, 12, 4},
-       {29, 29, 0x300, 0x10, 12, 4},
-       {30, 30, 0x300, 0x10, 12, 4},
-       {31, 31, 0x300, 0x10, 12, 4},
-       {32, 32, 0x300, 0x10, 12, 4},
-       {33, 33, 0x300, 0x10, 12, 4},
-       {34, 34, 0x300, 0x10, 12, 4},
-       {35, 35, 0x300, 0x10, 12, 4},
-       {36, 36, 0x300, 0x10, 12, 4},
-       {37, 37, 0x300, 0x10, 20, 4},
-       {38, 38, 0x300, 0x10, 20, 4},
-       {39, 39, 0x300, 0x10, 20, 4},
-       {40, 40, 0x300, 0x10, 20, 4},
-       {41, 41, 0x300, 0x10, 20, 4},
-       {42, 42, 0x300, 0x10, 20, 4},
-       {43, 43, 0x300, 0x10, 20, 4},
-       {44, 44, 0x300, 0x10, 20, 4},
-       {45, 46, 0x300, 0x10, 20, 4},
-       {47, 47, 0x300, 0x10, 20, 4},
-       {48, 48, 0x300, 0x10, 20, 4},
-       {49, 49, 0x300, 0x10, 20, 4},
-       {50, 50, 0x300, 0x10, 20, 4},
-       {51, 70, 0x330, 0x10, 4, 4},
-       {71, 71, 0x300, 0x10, 16, 4},
-       {72, 72, 0x300, 0x10, 16, 4},
-       {73, 76, 0x310, 0x10, 0, 4},
-       {77, 77, 0x320, 0x10, 28, 4},
-       {78, 78, 0x320, 0x10, 12, 4},
-       {79, 82, 0x3a0, 0x10, 0, 4},
-       {83, 83, 0x350, 0x10, 28, 4},
-       {84, 84, 0x330, 0x10, 0, 4},
-       {85, 90, 0x360, 0x10, 4, 4},
-       {91, 94, 0x390, 0x10, 16, 4},
-       {95, 97, 0x380, 0x10, 20, 4},
-       {98, 101, 0x390, 0x10, 0, 4},
-       {102, 102, 0x360, 0x10, 0, 4},
+       PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
+       PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
+       PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
+       PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
+       PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
+       PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
+       PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
+       PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
+       PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
+       PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
+       PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
+       PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
+       PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
+       PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
+       PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
+       PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
+       PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
+       PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
+       PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
+       PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
+       PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
+       PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
+       PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
+       PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
+       PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
+       PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
-       {0, 102, 0x0, 0x10, 0, 1},
+       PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
-       {0, 102, 0x200, 0x10, 0, 1},
+       PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
-       {0, 102, 0x100, 0x10, 0, 1},
+       PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
-       {0, 31, 0x910, 0x10, 0, 1},
-       {32, 50, 0xa10, 0x10, 0, 1},
-       {51, 70, 0x810, 0x10, 0, 1},
-       {71, 72, 0xb10, 0x10, 0, 1},
-       {73, 86, 0xb10, 0x10, 4, 1},
-       {87, 90, 0xc10, 0x10, 0, 1},
-       {91, 102, 0xb10, 0x10, 18, 1},
+       PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
+       PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
+       PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
+       PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
+       PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
+       PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
+       PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
-       {0, 31, 0x920, 0x10, 0, 1},
-       {32, 50, 0xa20, 0x10, 0, 1},
-       {51, 70, 0x820, 0x10, 0, 1},
-       {71, 72, 0xb20, 0x10, 0, 1},
-       {73, 86, 0xb20, 0x10, 4, 1},
-       {87, 90, 0xc20, 0x10, 0, 1},
-       {91, 102, 0xb20, 0x10, 18, 1},
+       PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
+       PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
+       PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
+       PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
+       PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
+       PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
+       PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
-       {0, 31, 0x930, 0x10, 0, 1},
-       {32, 50, 0xa30, 0x10, 0, 1},
-       {51, 70, 0x830, 0x10, 0, 1},
-       {71, 72, 0xb30, 0x10, 0, 1},
-       {73, 86, 0xb30, 0x10, 4, 1},
-       {87, 90, 0xc30, 0x10, 0, 1},
-       {91, 102, 0xb30, 0x10, 18, 1},
+       PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
+       PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
+       PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
+       PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
+       PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
+       PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
+       PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
-       {0, 31, 0x940, 0x10, 0, 1},
-       {32, 50, 0xa40, 0x10, 0, 1},
-       {51, 70, 0x840, 0x10, 0, 1},
-       {71, 72, 0xb40, 0x10, 0, 1},
-       {73, 86, 0xb40, 0x10, 4, 1},
-       {87, 90, 0xc40, 0x10, 0, 1},
-       {91, 102, 0xb40, 0x10, 18, 1},
+       PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
+       PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
+       PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
+       PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
+       PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
+       PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
+       PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
-       {0, 31, 0x960, 0x10, 0, 1},
-       {32, 50, 0xa60, 0x10, 0, 1},
-       {51, 70, 0x860, 0x10, 0, 1},
-       {71, 72, 0xb60, 0x10, 0, 1},
-       {73, 86, 0xb60, 0x10, 4, 1},
-       {87, 90, 0xc60, 0x10, 0, 1},
-       {91, 102, 0xb60, 0x10, 18, 1},
+       PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
+       PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
+       PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
+       PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
+       PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
+       PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
+       PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
-       {0, 31, 0x970, 0x10, 0, 1},
-       {32, 50, 0xa70, 0x10, 0, 1},
-       {51, 70, 0x870, 0x10, 0, 1},
-       {71, 72, 0xb70, 0x10, 0, 1},
-       {73, 86, 0xb70, 0x10, 4, 1},
-       {87, 90, 0xc70, 0x10, 0, 1},
-       {91, 102, 0xb70, 0x10, 18, 1},
+       PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
+       PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
+       PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
+       PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
+       PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
+       PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
+       PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
-       {0, 31, 0x980, 0x4, 0, 4},
-       {32, 50, 0xa80, 0x4, 0, 4},
-       {51, 70, 0x880, 0x4, 0, 4},
-       {71, 72, 0xb80, 0x4, 0, 4},
-       {73, 86, 0xb80, 0x4, 16, 4},
-       {87, 90, 0xc80, 0x4, 0, 4},
-       {91, 102, 0xb88, 0x4, 8, 4},
+       PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
+       PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
+       PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
+       PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
+       PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
+       PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
+       PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
-       {0, 31, 0x990, 0x4, 0, 6},
-       {32, 50, 0xa90, 0x4, 0, 6},
-       {51, 58, 0x890, 0x4, 0, 6},
-       {59, 60, 0x894, 0x4, 28, 6},
-       {61, 62, 0x894, 0x4, 16, 6},
-       {63, 66, 0x898, 0x4, 8, 6},
-       {67, 68, 0x89c, 0x4, 12, 6},
-       {69, 70, 0x89c, 0x4, 0, 6},
-       {71, 72, 0xb90, 0x4, 0, 6},
-       {73, 86, 0xb90, 0x4, 24, 6},
-       {87, 90, 0xc90, 0x4, 0, 6},
-       {91, 102, 0xb9c, 0x4, 12, 6},
+       PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
+       PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
+       PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
+       PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
+       PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
+       PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
+       PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
+       PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
+       PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
+       PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
+       PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
+       PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
 };
 
 static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
@@ -309,110 +152,110 @@ static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
        [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
 };
 
-static const struct pinctrl_pin_desc mt7622_pins[] = {
-       PINCTRL_PIN(0, "GPIO_A"),
-       PINCTRL_PIN(1, "I2S1_IN"),
-       PINCTRL_PIN(2, "I2S1_OUT"),
-       PINCTRL_PIN(3, "I2S_BCLK"),
-       PINCTRL_PIN(4, "I2S_WS"),
-       PINCTRL_PIN(5, "I2S_MCLK"),
-       PINCTRL_PIN(6, "TXD0"),
-       PINCTRL_PIN(7, "RXD0"),
-       PINCTRL_PIN(8, "SPI_WP"),
-       PINCTRL_PIN(9, "SPI_HOLD"),
-       PINCTRL_PIN(10, "SPI_CLK"),
-       PINCTRL_PIN(11, "SPI_MOSI"),
-       PINCTRL_PIN(12, "SPI_MISO"),
-       PINCTRL_PIN(13, "SPI_CS"),
-       PINCTRL_PIN(14, "I2C_SDA"),
-       PINCTRL_PIN(15, "I2C_SCL"),
-       PINCTRL_PIN(16, "I2S2_IN"),
-       PINCTRL_PIN(17, "I2S3_IN"),
-       PINCTRL_PIN(18, "I2S4_IN"),
-       PINCTRL_PIN(19, "I2S2_OUT"),
-       PINCTRL_PIN(20, "I2S3_OUT"),
-       PINCTRL_PIN(21, "I2S4_OUT"),
-       PINCTRL_PIN(22, "GPIO_B"),
-       PINCTRL_PIN(23, "MDC"),
-       PINCTRL_PIN(24, "MDIO"),
-       PINCTRL_PIN(25, "G2_TXD0"),
-       PINCTRL_PIN(26, "G2_TXD1"),
-       PINCTRL_PIN(27, "G2_TXD2"),
-       PINCTRL_PIN(28, "G2_TXD3"),
-       PINCTRL_PIN(29, "G2_TXEN"),
-       PINCTRL_PIN(30, "G2_TXC"),
-       PINCTRL_PIN(31, "G2_RXD0"),
-       PINCTRL_PIN(32, "G2_RXD1"),
-       PINCTRL_PIN(33, "G2_RXD2"),
-       PINCTRL_PIN(34, "G2_RXD3"),
-       PINCTRL_PIN(35, "G2_RXDV"),
-       PINCTRL_PIN(36, "G2_RXC"),
-       PINCTRL_PIN(37, "NCEB"),
-       PINCTRL_PIN(38, "NWEB"),
-       PINCTRL_PIN(39, "NREB"),
-       PINCTRL_PIN(40, "NDL4"),
-       PINCTRL_PIN(41, "NDL5"),
-       PINCTRL_PIN(42, "NDL6"),
-       PINCTRL_PIN(43, "NDL7"),
-       PINCTRL_PIN(44, "NRB"),
-       PINCTRL_PIN(45, "NCLE"),
-       PINCTRL_PIN(46, "NALE"),
-       PINCTRL_PIN(47, "NDL0"),
-       PINCTRL_PIN(48, "NDL1"),
-       PINCTRL_PIN(49, "NDL2"),
-       PINCTRL_PIN(50, "NDL3"),
-       PINCTRL_PIN(51, "MDI_TP_P0"),
-       PINCTRL_PIN(52, "MDI_TN_P0"),
-       PINCTRL_PIN(53, "MDI_RP_P0"),
-       PINCTRL_PIN(54, "MDI_RN_P0"),
-       PINCTRL_PIN(55, "MDI_TP_P1"),
-       PINCTRL_PIN(56, "MDI_TN_P1"),
-       PINCTRL_PIN(57, "MDI_RP_P1"),
-       PINCTRL_PIN(58, "MDI_RN_P1"),
-       PINCTRL_PIN(59, "MDI_RP_P2"),
-       PINCTRL_PIN(60, "MDI_RN_P2"),
-       PINCTRL_PIN(61, "MDI_TP_P2"),
-       PINCTRL_PIN(62, "MDI_TN_P2"),
-       PINCTRL_PIN(63, "MDI_TP_P3"),
-       PINCTRL_PIN(64, "MDI_TN_P3"),
-       PINCTRL_PIN(65, "MDI_RP_P3"),
-       PINCTRL_PIN(66, "MDI_RN_P3"),
-       PINCTRL_PIN(67, "MDI_RP_P4"),
-       PINCTRL_PIN(68, "MDI_RN_P4"),
-       PINCTRL_PIN(69, "MDI_TP_P4"),
-       PINCTRL_PIN(70, "MDI_TN_P4"),
-       PINCTRL_PIN(71, "PMIC_SCL"),
-       PINCTRL_PIN(72, "PMIC_SDA"),
-       PINCTRL_PIN(73, "SPIC1_CLK"),
-       PINCTRL_PIN(74, "SPIC1_MOSI"),
-       PINCTRL_PIN(75, "SPIC1_MISO"),
-       PINCTRL_PIN(76, "SPIC1_CS"),
-       PINCTRL_PIN(77, "GPIO_D"),
-       PINCTRL_PIN(78, "WATCHDOG"),
-       PINCTRL_PIN(79, "RTS3_N"),
-       PINCTRL_PIN(80, "CTS3_N"),
-       PINCTRL_PIN(81, "TXD3"),
-       PINCTRL_PIN(82, "RXD3"),
-       PINCTRL_PIN(83, "PERST0_N"),
-       PINCTRL_PIN(84, "PERST1_N"),
-       PINCTRL_PIN(85, "WLED_N"),
-       PINCTRL_PIN(86, "EPHY_LED0_N"),
-       PINCTRL_PIN(87, "AUXIN0"),
-       PINCTRL_PIN(88, "AUXIN1"),
-       PINCTRL_PIN(89, "AUXIN2"),
-       PINCTRL_PIN(90, "AUXIN3"),
-       PINCTRL_PIN(91, "TXD4"),
-       PINCTRL_PIN(92, "RXD4"),
-       PINCTRL_PIN(93, "RTS4_N"),
-       PINCTRL_PIN(94, "CTS4_N"),
-       PINCTRL_PIN(95, "PWM1"),
-       PINCTRL_PIN(96, "PWM2"),
-       PINCTRL_PIN(97, "PWM3"),
-       PINCTRL_PIN(98, "PWM4"),
-       PINCTRL_PIN(99, "PWM5"),
-       PINCTRL_PIN(100, "PWM6"),
-       PINCTRL_PIN(101, "PWM7"),
-       PINCTRL_PIN(102, "GPIO_E"),
+static const struct mtk_pin_desc mt7622_pins[] = {
+       MT7622_PIN(0, "GPIO_A"),
+       MT7622_PIN(1, "I2S1_IN"),
+       MT7622_PIN(2, "I2S1_OUT"),
+       MT7622_PIN(3, "I2S_BCLK"),
+       MT7622_PIN(4, "I2S_WS"),
+       MT7622_PIN(5, "I2S_MCLK"),
+       MT7622_PIN(6, "TXD0"),
+       MT7622_PIN(7, "RXD0"),
+       MT7622_PIN(8, "SPI_WP"),
+       MT7622_PIN(9, "SPI_HOLD"),
+       MT7622_PIN(10, "SPI_CLK"),
+       MT7622_PIN(11, "SPI_MOSI"),
+       MT7622_PIN(12, "SPI_MISO"),
+       MT7622_PIN(13, "SPI_CS"),
+       MT7622_PIN(14, "I2C_SDA"),
+       MT7622_PIN(15, "I2C_SCL"),
+       MT7622_PIN(16, "I2S2_IN"),
+       MT7622_PIN(17, "I2S3_IN"),
+       MT7622_PIN(18, "I2S4_IN"),
+       MT7622_PIN(19, "I2S2_OUT"),
+       MT7622_PIN(20, "I2S3_OUT"),
+       MT7622_PIN(21, "I2S4_OUT"),
+       MT7622_PIN(22, "GPIO_B"),
+       MT7622_PIN(23, "MDC"),
+       MT7622_PIN(24, "MDIO"),
+       MT7622_PIN(25, "G2_TXD0"),
+       MT7622_PIN(26, "G2_TXD1"),
+       MT7622_PIN(27, "G2_TXD2"),
+       MT7622_PIN(28, "G2_TXD3"),
+       MT7622_PIN(29, "G2_TXEN"),
+       MT7622_PIN(30, "G2_TXC"),
+       MT7622_PIN(31, "G2_RXD0"),
+       MT7622_PIN(32, "G2_RXD1"),
+       MT7622_PIN(33, "G2_RXD2"),
+       MT7622_PIN(34, "G2_RXD3"),
+       MT7622_PIN(35, "G2_RXDV"),
+       MT7622_PIN(36, "G2_RXC"),
+       MT7622_PIN(37, "NCEB"),
+       MT7622_PIN(38, "NWEB"),
+       MT7622_PIN(39, "NREB"),
+       MT7622_PIN(40, "NDL4"),
+       MT7622_PIN(41, "NDL5"),
+       MT7622_PIN(42, "NDL6"),
+       MT7622_PIN(43, "NDL7"),
+       MT7622_PIN(44, "NRB"),
+       MT7622_PIN(45, "NCLE"),
+       MT7622_PIN(46, "NALE"),
+       MT7622_PIN(47, "NDL0"),
+       MT7622_PIN(48, "NDL1"),
+       MT7622_PIN(49, "NDL2"),
+       MT7622_PIN(50, "NDL3"),
+       MT7622_PIN(51, "MDI_TP_P0"),
+       MT7622_PIN(52, "MDI_TN_P0"),
+       MT7622_PIN(53, "MDI_RP_P0"),
+       MT7622_PIN(54, "MDI_RN_P0"),
+       MT7622_PIN(55, "MDI_TP_P1"),
+       MT7622_PIN(56, "MDI_TN_P1"),
+       MT7622_PIN(57, "MDI_RP_P1"),
+       MT7622_PIN(58, "MDI_RN_P1"),
+       MT7622_PIN(59, "MDI_RP_P2"),
+       MT7622_PIN(60, "MDI_RN_P2"),
+       MT7622_PIN(61, "MDI_TP_P2"),
+       MT7622_PIN(62, "MDI_TN_P2"),
+       MT7622_PIN(63, "MDI_TP_P3"),
+       MT7622_PIN(64, "MDI_TN_P3"),
+       MT7622_PIN(65, "MDI_RP_P3"),
+       MT7622_PIN(66, "MDI_RN_P3"),
+       MT7622_PIN(67, "MDI_RP_P4"),
+       MT7622_PIN(68, "MDI_RN_P4"),
+       MT7622_PIN(69, "MDI_TP_P4"),
+       MT7622_PIN(70, "MDI_TN_P4"),
+       MT7622_PIN(71, "PMIC_SCL"),
+       MT7622_PIN(72, "PMIC_SDA"),
+       MT7622_PIN(73, "SPIC1_CLK"),
+       MT7622_PIN(74, "SPIC1_MOSI"),
+       MT7622_PIN(75, "SPIC1_MISO"),
+       MT7622_PIN(76, "SPIC1_CS"),
+       MT7622_PIN(77, "GPIO_D"),
+       MT7622_PIN(78, "WATCHDOG"),
+       MT7622_PIN(79, "RTS3_N"),
+       MT7622_PIN(80, "CTS3_N"),
+       MT7622_PIN(81, "TXD3"),
+       MT7622_PIN(82, "RXD3"),
+       MT7622_PIN(83, "PERST0_N"),
+       MT7622_PIN(84, "PERST1_N"),
+       MT7622_PIN(85, "WLED_N"),
+       MT7622_PIN(86, "EPHY_LED0_N"),
+       MT7622_PIN(87, "AUXIN0"),
+       MT7622_PIN(88, "AUXIN1"),
+       MT7622_PIN(89, "AUXIN2"),
+    &n