Merge tag 'gpio-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 5 Aug 2017 13:55:13 +0000 (06:55 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 5 Aug 2017 13:55:13 +0000 (06:55 -0700)
Pull GPIO fixes from Linus Walleij:

 - LP87565: set the proper output level for direction_output.

 - stm32: fix the kernel build by selecting the hierarchical irqdomain
   symbol properly - this happens to be done in the pin control
   framework but whatever, it had dependencies to GPIO so we need to
   apply it here.

 - Select the hierarchical IRQ domain also for Xgene.

 - Fix wakeups to work on MXC.

 - Fix up the device tree binding on Exar that went astray, also add the
   right bindings.

 - Fix the unwanted events for edges from the library.

 - Fix the unbalanced chanined IRQ on the Tegra.

* tag 'gpio-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
  gpio: tegra: fix unbalanced chained_irq_enter/exit
  gpiolib: skip unwanted events, don't convert them to opposite edge
  gpio: exar: Use correct property prefix and document bindings
  gpio: gpio-mxc: Fix: higher 16 GPIOs usable as wake source
  gpio: xgene-sb: select IRQ_DOMAIN_HIERARCHY
  pinctrl: stm32: select IRQ_DOMAIN_HIERARCHY instead of depends on
  gpio: lp87565: Set proper output level and direction for direction_output
  MAINTAINERS: Add entry for Whiskey Cove PMIC GPIO driver

281 files changed:
Documentation/admin-guide/pm/cpufreq.rst
Documentation/devicetree/bindings/ata/sata_rcar.txt
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
Documentation/power/runtime_pm.txt
MAINTAINERS
arch/arm/Kconfig
arch/arm/boot/dts/armada-388-gp.dts
arch/arm/boot/dts/da850-evm.dts
arch/arm/boot/dts/da850-lcdk.dts
arch/arm/boot/dts/dm8168-evm.dts
arch/arm/boot/dts/dm816x.dtsi
arch/arm/boot/dts/dra71-evm.dts
arch/arm/boot/dts/exynos4.dtsi
arch/arm/boot/dts/rk3288.dtsi
arch/arm/boot/dts/sun8i-a83t.dtsi
arch/arm/boot/dts/sunxi-h3-h5.dtsi
arch/arm/boot/dts/tango4-vantage-1172.dts
arch/arm/mach-davinci/board-da850-evm.c
arch/arm/mach-davinci/clock.c
arch/arm/mach-ep93xx/clock.c
arch/arm/mach-ixp4xx/include/mach/io.h
arch/arm/mach-mmp/devices.c
arch/arm/mach-mvebu/platsmp.c
arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-osk.c
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/prm3xxx.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-prima2/common.c
arch/arm/mach-pxa/Kconfig
arch/arm/mach-pxa/include/mach/mtd-xip.h
arch/arm/mach-rpc/include/mach/hardware.h
arch/arm/mach-sa1100/clock.c
arch/arm/mach-sa1100/include/mach/mtd-xip.h
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
arch/arm/mach-w90x900/clock.c
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
arch/arm64/boot/dts/renesas/salvator-common.dtsi
arch/arm64/boot/dts/renesas/ulcb.dtsi
arch/arm64/configs/defconfig
arch/arm64/include/asm/memory.h
arch/arm64/kernel/traps.c
arch/arm64/kvm/sys_regs.c
arch/arm64/mm/fault.c
arch/parisc/Kconfig
arch/parisc/include/asm/thread_info.h
arch/parisc/kernel/cache.c
arch/parisc/kernel/irq.c
arch/powerpc/boot/Makefile
arch/powerpc/include/asm/book3s/64/pgtable.h
arch/powerpc/kernel/exceptions-64s.S
arch/powerpc/kernel/idle_book3s.S
arch/powerpc/kernel/irq.c
arch/powerpc/kernel/ptrace.c
arch/powerpc/kernel/smp.c
arch/powerpc/platforms/83xx/mpc832x_rdb.c
arch/powerpc/platforms/powernv/pci-ioda.c
arch/sparc/configs/sparc32_defconfig
arch/sparc/configs/sparc64_defconfig
arch/sparc/include/asm/mmu_context_64.h
arch/sparc/kernel/tsb.S
arch/sparc/lib/U3memcpy.S
arch/sparc/mm/init_64.c
arch/sparc/power/hibernate.c
arch/x86/kernel/cpu/aperfmperf.c
arch/x86/kernel/hpet.c
arch/x86/kernel/kvm.c
arch/x86/kvm/svm.c
arch/x86/kvm/vmx.c
arch/x86/kvm/x86.c
drivers/acpi/acpi_apd.c
drivers/acpi/acpi_lpss.c
drivers/acpi/acpi_watchdog.c
drivers/ata/Kconfig
drivers/ata/libata-core.c
drivers/ata/libata-eh.c
drivers/ata/libata-scsi.c
drivers/ata/sata_rcar.c
drivers/bus/uniphier-system-bus.c
drivers/clk/clk-gemini.c
drivers/clk/keystone/sci-clk.c
drivers/clk/meson/clk-mpll.c
drivers/clk/meson/clkc.h
drivers/clk/meson/gxbb.c
drivers/clk/meson/meson8b.c
drivers/clk/samsung/clk-exynos5420.c
drivers/clk/sunxi-ng/ccu-sun5i.c
drivers/clk/x86/clk-pmc-atom.c
drivers/cpufreq/intel_pstate.c
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
drivers/gpu/drm/amd/amdgpu/si.c
drivers/iommu/amd_iommu.c
drivers/iommu/amd_iommu_init.c
drivers/iommu/arm-smmu.c
drivers/iommu/io-pgtable-arm-v7s.c
drivers/iommu/io-pgtable-arm.c
drivers/iommu/io-pgtable.h
drivers/iommu/mtk_iommu.c
drivers/iommu/mtk_iommu.h
drivers/isdn/i4l/isdn_common.c
drivers/isdn/i4l/isdn_net.c
drivers/mailbox/pcc.c
drivers/mmc/core/block.c
drivers/mmc/host/sdhci-of-at91.c
drivers/net/bonding/bond_main.c
drivers/net/ethernet/aurora/nb8800.c
drivers/net/ethernet/broadcom/genet/bcmgenet.c
drivers/net/ethernet/broadcom/genet/bcmgenet.h
drivers/net/ethernet/broadcom/genet/bcmmii.c
drivers/net/ethernet/cavium/thunder/thunder_bgx.c
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
drivers/net/ethernet/faraday/ftgmac100.c
drivers/net/ethernet/marvell/mv643xx_eth.c
drivers/net/ethernet/mediatek/mtk_eth_soc.c
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
drivers/net/ethernet/mellanox/mlx5/core/en.h
drivers/net/ethernet/mellanox/mlx5/core/en_clock.c
drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/eq.c
drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
drivers/net/ethernet/mellanox/mlx5/core/lag.c
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
drivers/net/ethernet/mellanox/mlx5/core/sriov.c
drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
drivers/net/ethernet/sun/sunhme.h
drivers/net/ethernet/toshiba/tc35815.c
drivers/net/hyperv/netvsc_drv.c
drivers/net/irda/mcs7780.c
drivers/net/phy/Kconfig
drivers/net/phy/phy.c
drivers/net/ppp/pptp.c
drivers/net/team/team.c
drivers/net/tun.c
drivers/net/virtio_net.c
drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
drivers/net/wireless/intel/iwlwifi/dvm/tx.c
drivers/net/wireless/intel/iwlwifi/iwl-devtrace.h
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
drivers/net/wireless/intel/iwlwifi/mvm/mvm.h
drivers/net/wireless/intel/iwlwifi/mvm/ops.c
drivers/net/wireless/intel/iwlwifi/mvm/sta.c
drivers/net/wireless/intel/iwlwifi/pcie/trans.c
drivers/net/wireless/intel/iwlwifi/pcie/tx.c
drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c
drivers/net/wireless/realtek/rtlwifi/wifi.h
drivers/of/property.c
drivers/parisc/pdc_stable.c
drivers/phy/broadcom/Kconfig
drivers/platform/x86/Kconfig
drivers/platform/x86/dell-wmi.c
drivers/platform/x86/wmi.c
drivers/sbus/char/display7seg.c
drivers/sbus/char/flash.c
drivers/sbus/char/uctrl.c
drivers/scsi/Kconfig
drivers/scsi/aic7xxx/Makefile
drivers/scsi/aic7xxx/aicasm/Makefile
drivers/scsi/cxgbi/libcxgbi.c
drivers/scsi/megaraid/megaraid_sas_fusion.c
drivers/scsi/qedi/Kconfig
drivers/scsi/qedi/qedi_iscsi.c
drivers/scsi/scsi_transport_fc.c
drivers/soc/zte/Kconfig
drivers/thunderbolt/icm.c
drivers/vfio/pci/vfio_pci.c
drivers/vfio/pci/vfio_pci_config.c
drivers/vhost/vhost.c
drivers/vhost/vhost.h
fs/nfs/nfs4client.c
fs/nfs/nfs4proc.c
fs/nfs/nfs4xdr.c
fs/ocfs2/acl.c
fs/userfaultfd.c
include/kvm/arm_pmu.h
include/linux/ceph/osd_client.h
include/linux/ceph/osdmap.h
include/linux/ceph/rados.h
include/linux/cpuset.h
include/linux/crush/crush.h
include/linux/ipv6.h
include/linux/kthread.h
include/linux/kvm_host.h
include/linux/libata.h
include/linux/mlx5/mlx5_ifc.h
include/linux/mm_types.h
include/linux/nfs_xdr.h
include/linux/pagemap.h
include/linux/phy.h
include/linux/vfio.h
include/linux/workqueue.h
include/net/sctp/sctp.h
include/net/udp.h
include/sound/soc.h
ipc/msg.c
ipc/sem.c
ipc/shm.c
kernel/bpf/syscall.c
kernel/bpf/verifier.c
kernel/cgroup/cgroup-internal.h
kernel/cgroup/cgroup.c
kernel/cgroup/cpuset.c
kernel/pid.c
kernel/time/timer.c
kernel/workqueue.c
lib/test_rhashtable.c
mm/hugetlb.c
mm/internal.h
mm/kasan/report.c
mm/madvise.c
mm/memory.c
mm/mprotect.c
mm/mremap.c
mm/page_alloc.c
mm/page_io.c
mm/rmap.c
mm/zsmalloc.c
net/ceph/crush/mapper.c
net/ceph/messenger.c
net/ceph/osd_client.c
net/ceph/osdmap.c
net/core/dev_ioctl.c
net/core/netpoll.c
net/dccp/feat.c
net/dccp/ipv4.c
net/dccp/ipv6.c
net/dsa/dsa2.c
net/ipv4/fib_semantics.c
net/ipv4/tcp_output.c
net/ipv4/udp.c
net/ipv6/exthdrs.c
net/ipv6/ip6_output.c
net/ipv6/udp.c
net/openvswitch/conntrack.c
net/packet/af_packet.c
net/socket.c
samples/bpf/tcbpf2_kern.c
samples/bpf/test_tunnel_bpf.sh
sound/pci/hda/patch_realtek.c
sound/soc/codecs/msm8916-wcd-analog.c
sound/soc/codecs/rt5663.c
sound/soc/codecs/rt5665.c
sound/soc/codecs/rt5665.h
sound/soc/codecs/sgtl5000.c
sound/soc/fsl/imx-ssi.c
sound/soc/generic/audio-graph-card.c
sound/soc/generic/audio-graph-scu-card.c
sound/soc/generic/simple-card-utils.c
sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c
sound/soc/intel/skylake/skl-messages.c
sound/soc/intel/skylake/skl.c
sound/soc/pxa/Kconfig
sound/soc/samsung/odroid.c
sound/soc/sh/hac.c
sound/soc/soc-core.c
sound/soc/soc-pcm.c
sound/soc/ux500/mop500.c
tools/lib/bpf/bpf.c
tools/testing/selftests/bpf/test_progs.c
tools/testing/selftests/bpf/test_verifier.c
virt/kvm/arm/mmu.c
virt/kvm/arm/pmu.c
virt/kvm/arm/vgic/vgic-init.c
virt/kvm/arm/vgic/vgic-its.c
virt/kvm/arm/vgic/vgic-mmio-v3.c
virt/kvm/kvm_main.c

index 463cf7e73db80b3bf3f8a36afe91bcf3d7f0d429..7af83a92d2d6103ea3fb0a3a0425e994b29f7f53 100644 (file)
@@ -237,6 +237,14 @@ are the following:
        This attribute is not present if the scaling driver in use does not
        support it.
 
+``cpuinfo_cur_freq``
+       Current frequency of the CPUs belonging to this policy as obtained from
+       the hardware (in KHz).
+
+       This is expected to be the frequency the hardware actually runs at.
+       If that frequency cannot be determined, this attribute should not
+       be present.
+
 ``cpuinfo_max_freq``
        Maximum possible operating frequency the CPUs belonging to this policy
        can run at (in kHz).
index 0764f9ab63dcde31f7efff01f74e56c5c6fa1c56..e20eac7a30874f0db82adefa0cdf3a77ac09aec2 100644 (file)
@@ -1,14 +1,22 @@
 * Renesas R-Car SATA
 
 Required properties:
-- compatible           : should contain one of the following:
+- compatible           : should contain one or more of the following:
                          - "renesas,sata-r8a7779" for R-Car H1
-                           ("renesas,rcar-sata" is deprecated)
                          - "renesas,sata-r8a7790-es1" for R-Car H2 ES1
                          - "renesas,sata-r8a7790" for R-Car H2 other than ES1
                          - "renesas,sata-r8a7791" for R-Car M2-W
                          - "renesas,sata-r8a7793" for R-Car M2-N
                          - "renesas,sata-r8a7795" for R-Car H3
+                         - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
+                         - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
+                         - "renesas,rcar-sata" is deprecated
+
+                         When compatible with the generic version nodes
+                         must list the SoC-specific version corresponding
+                         to the platform first followed by the generic
+                         version.
+
 - reg                  : address and length of the SATA registers;
 - interrupts           : must consist of one interrupt specifier.
 - clocks               : must contain a reference to the functional clock.
@@ -16,7 +24,7 @@ Required properties:
 Example:
 
 sata0: sata@ee300000 {
-       compatible = "renesas,sata-r8a7791";
+       compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
        reg = <0 0xee300000 0 0x2000>;
        interrupt-parent = <&gic>;
        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
index d3b6e1a4713a58d00692ab8bf2ae74f1956a40e3..5aa5926029ee7286c4cd2e41a446574c13102021 100644 (file)
@@ -40,7 +40,7 @@ Optional properties:
 Example for a Mali-T760:
 
 gpu@ffa30000 {
-       compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
+       compatible = "rockchip,rk3288-mali", "arm,mali-t760";
        reg = <0xffa30000 0x10000>;
        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
index 0fde3dcf077a302eb24ea6d8fd8df65c4b252d8e..625549d4c74a09642d72bce75387c15348406223 100644 (file)
@@ -435,7 +435,8 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
       PM status to 'suspended' and update its parent's counter of 'active'
       children as appropriate (it is only valid to use this function if
       'power.runtime_error' is set or 'power.disable_depth' is greater than
-      zero)
+      zero); it will fail and return an error code if the device has a child
+      which is active and the 'power.ignore_children' flag is unset
 
   bool pm_runtime_active(struct device *dev);
     - return true if the device's runtime PM status is 'active' or its
index a2249d3b94b1107735cb04a846587e9448b057c9..44cb004c765d5bc3e9b71844b08fca7f204cae61 100644 (file)
@@ -5090,12 +5090,20 @@ M:      Andrew Lunn <andrew@lunn.ch>
 M:     Florian Fainelli <f.fainelli@gmail.com>
 L:     netdev@vger.kernel.org
 S:     Maintained
-F:     include/linux/phy.h
-F:     include/linux/phy_fixed.h
-F:     drivers/net/phy/
+F:     Documentation/ABI/testing/sysfs-bus-mdio
+F:     Documentation/devicetree/bindings/net/mdio*
 F:     Documentation/networking/phy.txt
+F:     drivers/net/phy/
 F:     drivers/of/of_mdio.c
 F:     drivers/of/of_net.c
+F:     include/linux/*mdio*.h
+F:     include/linux/of_net.h
+F:     include/linux/phy.h
+F:     include/linux/phy_fixed.h
+F:     include/linux/platform_data/mdio-gpio.h
+F:     include/trace/events/mdio.h
+F:     include/uapi/linux/mdio.h
+F:     include/uapi/linux/mii.h
 
 EXT2 FILE SYSTEM
 M:     Jan Kara <jack@suse.com>
index a208bfe367b55574e2ca4a901de8b3a2862aee2e..61a0cb15067ea653eaa9631fe64276385e3de064 100644 (file)
@@ -380,7 +380,7 @@ config ARCH_EP93XX
        bool "EP93xx-based"
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARM_AMBA
-       select ARM_PATCH_PHYS_VIRT
+       imply ARM_PATCH_PHYS_VIRT
        select ARM_VIC
        select AUTO_ZRELADDR
        select CLKDEV_LOOKUP
index 895fa6cfa15a9ee1c56c5827f5f5fe2f8e512196..563901e0ec071f0c66a4590b17fe5c3f6cfcbd69 100644 (file)
@@ -75,7 +75,7 @@
                                        pinctrl-names = "default";
                                        pinctrl-0 = <&pca0_pins>;
                                        interrupt-parent = <&gpio0>;
-                                       interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                                       interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        interrupt-controller;
@@ -87,7 +87,7 @@
                                        compatible = "nxp,pca9555";
                                        pinctrl-names = "default";
                                        interrupt-parent = <&gpio0>;
-                                       interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                                       interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        interrupt-controller;
index a423e8ebfb3758057d41a4e9f77505df5dc1d783..67e72bc72e805be995b0d44fa68f74e29161b140 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
        status = "okay";
-
-       /* VPIF capture port */
-       port@0 {
-               vpif_input_ch0: endpoint@0 {
-                       reg = <0>;
-                       bus-width = <8>;
-               };
-
-               vpif_input_ch1: endpoint@1 {
-                       reg = <1>;
-                       bus-width = <8>;
-                       data-shift = <8>;
-               };
-       };
-
-       /* VPIF display port */
-       port@1 {
-               vpif_output_ch0: endpoint {
-                       bus-width = <8>;
-               };
-       };
 };
index b837fec70eec8cb7d241d14559c8fad9c0cbb909..a0f0916156e66d83949716c4b571184695fbef3b 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&vpif_capture_pins>;
        status = "okay";
-
-       /* VPIF capture port */
-       port {
-               vpif_ch0: endpoint {
-                         bus-width = <8>;
-               };
-       };
 };
index 1865976db5f9a3e11aad03cdd951d2f3af83c78d..c72a2132aa823b053c5ab9450a92faf266c85878 100644 (file)
                        DM816X_IOPAD(0x0d08, MUX_MODE0)                 /* USB1_DRVVBUS */
                >;
        };
+
+       nandflash_pins: nandflash_pins {
+               pinctrl-single,pins = <
+                       DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0)               /* PINCTRL207 GPMC_CS0*/
+                       DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0)              /* PINCTRL217 GPMC_ADV_ALE */
+                       DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0)    /* PINCTRL214 GPMC_OE_RE */
+                       DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0)              /* PINCTRL215 GPMC_BE0_CLE */
+                       DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0)               /* PINCTRL213 GPMC_WE */
+                       DM816X_IOPAD(0x0b6c, MUX_MODE0)                         /* PINCTRL220 GPMC_WAIT */
+                       DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0)              /* PINCTRL250 GPMC_CLK */
+                       DM816X_IOPAD(0x0ba4, MUX_MODE0)                         /* PINCTRL234 GPMC_D0 */
+                       DM816X_IOPAD(0x0ba8, MUX_MODE0)                         /* PINCTRL234 GPMC_D1 */
+                       DM816X_IOPAD(0x0bac, MUX_MODE0)                         /* PINCTRL234 GPMC_D2 */
+                       DM816X_IOPAD(0x0bb0, MUX_MODE0)                         /* PINCTRL234 GPMC_D3 */
+                       DM816X_IOPAD(0x0bb4, MUX_MODE0)                         /* PINCTRL234 GPMC_D4 */
+                       DM816X_IOPAD(0x0bb8, MUX_MODE0)                         /* PINCTRL234 GPMC_D5 */
+                       DM816X_IOPAD(0x0bbc, MUX_MODE0)                         /* PINCTRL234 GPMC_D6 */
+                       DM816X_IOPAD(0x0bc0, MUX_MODE0)                         /* PINCTRL234 GPMC_D7 */
+                       DM816X_IOPAD(0x0bc4, MUX_MODE0)                         /* PINCTRL234 GPMC_D8 */
+                       DM816X_IOPAD(0x0bc8, MUX_MODE0)                         /* PINCTRL234 GPMC_D9 */
+                       DM816X_IOPAD(0x0bcc, MUX_MODE0)                         /* PINCTRL234 GPMC_D10 */
+                       DM816X_IOPAD(0x0bd0, MUX_MODE0)                         /* PINCTRL234 GPMC_D11 */
+                       DM816X_IOPAD(0x0bd4, MUX_MODE0)                         /* PINCTRL234 GPMC_D12 */
+                       DM816X_IOPAD(0x0bd8, MUX_MODE0)                         /* PINCTRL234 GPMC_D13 */
+                       DM816X_IOPAD(0x0bdc, MUX_MODE0)                         /* PINCTRL234 GPMC_D14 */
+                       DM816X_IOPAD(0x0be0, MUX_MODE0)                         /* PINCTRL234 GPMC_D15 */
+               >;
+       };
 };
 
 &i2c1 {
 
 &gpmc {
        ranges = <0 0 0x04000000 0x01000000>;   /* CS0: 16MB for NAND */
+       pinctrl-names = "default";
+       pinctrl-0 = <&nandflash_pins>;
 
        nand@0,0 {
                compatible = "ti,omap2-nand";
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                #address-cells = <1>;
                #size-cells = <1>;
                ti,nand-ecc-opt = "bch8";
+               ti,elm-id = <&elm>;
                nand-bus-width = <16>;
                gpmc,device-width = <2>;
                gpmc,sync-clk-ps = <0>;
        vmmc-supply = <&vmmcsd_fixed>;
        bus-width = <4>;
        cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
-       wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 };
 
 /* At least dm8168-evm rev c won't support multipoint, later may */
index 59cbf958fcc3178c4b56aad647c340e40a63c098..566b2a8c8b96853da331571c233dc786d8adc187 100644 (file)
                };
 
                elm: elm@48080000 {
-                       compatible = "ti,816-elm";
+                       compatible = "ti,am3352-elm";
                        ti,hwmods = "elm";
                        reg = <0x48080000 0x2000>;
                        interrupts = <4>;
index 4d57a55473afd1f563667d948b49269e11028697..a6298eb56978710c24291fc05d17770fefccd188 100644 (file)
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-               ti,impedance-control = <0x1f>;
+               ti,min-output-impedance;
        };
 
        dp83867_1: ethernet-phy@3 {
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-               ti,impedance-control = <0x1f>;
+               ti,min-output-impedance;
        };
 };
 
index 497a9470c8881bca6e49800f90c0f5d20dd3d84a..5739389f5bb877ef7b29455a1bcd47328d7223ed 100644 (file)
@@ -59,6 +59,9 @@
                compatible = "samsung,exynos4210-audss-clock";
                reg = <0x03810000 0x0C>;
                #clock-cells = <1>;
+               clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                        <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
+               clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
        };
 
        i2s0: i2s@03830000 {
index 2484f11761ea24f3bfa44a81e7309442399367d9..858e1fed762a1df80f33bac4576b5d900e021bcf 100644 (file)
                };
        };
 
-       gpu: mali@ffa30000 {
-               compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
+       gpu: gpu@ffa30000 {
+               compatible = "rockchip,rk3288-mali", "arm,mali-t760";
                reg = <0xffa30000 0x10000>;
                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
index 8923ba625b76f156f27fde9c66f1f72ad044405a..19a8f4fcfab50ef5300360d980f1738d99345a94 100644 (file)
@@ -44,7 +44,9 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 / {
        interrupt-parent = <&gic>;
                        compatible = "allwinner,sun8i-a83t-dma";
                        reg = <0x01c02000 0x1000>;
                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 21>;
-                       resets = <&ccu 7>;
+                       clocks = <&ccu CLK_BUS_DMA>;
+                       resets = <&ccu RST_BUS_DMA>;
                        #dma-cells = <1>;
                };
 
                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                        reg = <0x01c20800 0x400>;
-                       clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+                       clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
                        clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        interrupt-controller;
                                     "allwinner,sun8i-h3-spdif";
                        reg = <0x01c21000 0x400>;
                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 44>, <&ccu 76>;
-                       resets = <&ccu 32>;
+                       clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+                       resets = <&ccu RST_BUS_SPDIF>;
                        clock-names = "apb", "spdif";
                        dmas = <&dma 2>;
                        dma-names = "tx";
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 53>;
-                       resets = <&ccu 40>;
+                       clocks = <&ccu CLK_BUS_UART0>;
+                       resets = <&ccu RST_BUS_UART0>;
                        status = "disabled";
                };
 
index 6f2162608006770896df2adcc258a4ed2a3b63a9..d38282b9e5d442cbf1709e38f8a64ee9bfacce1c 100644 (file)
                emac: ethernet@1c30000 {
                        compatible = "allwinner,sun8i-h3-emac";
                        syscon = <&syscon>;
-                       reg = <0x01c30000 0x104>;
+                       reg = <0x01c30000 0x10000>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
                        resets = <&ccu RST_BUS_EMAC>;
index 86d8df98802fdf66a651adb04de5c4be49af3fcc..13bcc460bcb2adf2ab17775bc0aa2c01bc694aed 100644 (file)
@@ -22,7 +22,7 @@
 };
 
 &eth0 {
-       phy-connection-type = "rgmii";
+       phy-connection-type = "rgmii-id";
        phy-handle = <&eth0_phy>;
        #address-cells = <1>;
        #size-cells = <0>;
index b5625d0092881bbbbb1022de2664c51f2a304844..e568c8c6f69cb67bf423db51f25d6315a15fbc96 100644 (file)
@@ -1166,7 +1166,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
 
 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
 
-static const struct vpif_input da850_ch0_inputs[] = {
+static struct vpif_input da850_ch0_inputs[] = {
        {
                .input = {
                        .index = 0,
@@ -1181,7 +1181,7 @@ static const struct vpif_input da850_ch0_inputs[] = {
        },
 };
 
-static const struct vpif_input da850_ch1_inputs[] = {
+static struct vpif_input da850_ch1_inputs[] = {
        {
                .input = {
                        .index = 0,
index f5dce9b4e617df833cd210bac2fe65ac4a93b788..f77a4f7660505fe949af782e50b99c08b12a5570 100644 (file)
@@ -218,6 +218,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 }
 EXPORT_SYMBOL(clk_set_parent);
 
+struct clk *clk_get_parent(struct clk *clk)
+{
+       if (!clk)
+               return NULL;
+
+       return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
 int clk_register(struct clk *clk)
 {
        if (clk == NULL || IS_ERR(clk))
index 39ef3b613912f8888013c30d591e4ad4f0cd8095..beec5f16443a29fb5a62f6deb8969ea33cff5b6d 100644 (file)
@@ -475,6 +475,26 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+       return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
 
 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
index 7a0c13bf42694b724e0fcb35439070eefde0a646..844e8ac593e270125980df3ecced92b6d6322f5e 100644 (file)
@@ -95,8 +95,10 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
 }
 
 static inline void __indirect_writesb(volatile void __iomem *bus_addr,
-                                     const u8 *vaddr, int count)
+                                     const void *p, int count)
 {
+       const u8 *vaddr = p;
+
        while (count--)
                writeb(*vaddr++, bus_addr);
 }
@@ -118,8 +120,10 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
 }
 
 static inline void __indirect_writesw(volatile void __iomem *bus_addr,
-                                     const u16 *vaddr, int count)
+                                     const void *p, int count)
 {
+       const u16 *vaddr = p;
+
        while (count--)
                writew(*vaddr++, bus_addr);
 }
@@ -137,8 +141,9 @@ static inline void __indirect_writel(u32 value, volatile void __iomem *p)
 }
 
 static inline void __indirect_writesl(volatile void __iomem *bus_addr,
-                                     const u32 *vaddr, int count)
+                                     const void *p, int count)
 {
+       const u32 *vaddr = p;
        while (count--)
                writel(*vaddr++, bus_addr);
 }
@@ -160,8 +165,10 @@ static inline u8 __indirect_readb(const volatile void __iomem *p)
 }
 
 static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
-                                    u8 *vaddr, u32 count)
+                                    void *p, u32 count)
 {
+       u8 *vaddr = p;
+
        while (count--)
                *vaddr++ = readb(bus_addr);
 }
@@ -183,8 +190,10 @@ static inline u16 __indirect_readw(const volatile void __iomem *p)
 }
 
 static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
-                                    u16 *vaddr, u32 count)
+                                    void *p, u32 count)
 {
+       u16 *vaddr = p;
+
        while (count--)
                *vaddr++ = readw(bus_addr);
 }
@@ -204,8 +213,10 @@ static inline u32 __indirect_readl(const volatile void __iomem *p)
 }
 
 static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
-                                    u32 *vaddr, u32 count)
+                                    void *p, u32 count)
 {
+       u32 *vaddr = p;
+
        while (count--)
                *vaddr++ = readl(bus_addr);
 }
@@ -523,8 +534,15 @@ static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
 #endif
 }
 
-#define        ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
-#define        ioport_unmap(addr)
+#define ioport_map(port, nr) ioport_map(port, nr)
+static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+       return ((void __iomem*)((port) + PIO_OFFSET));
+}
+#define        ioport_unmap(addr) ioport_unmap(addr)
+static inline void ioport_unmap(void __iomem *addr)
+{
+}
 #endif /* CONFIG_PCI */
 
 #endif /* __ASM_ARM_ARCH_IO_H */
index 3330ac7cfbefc78388b78ad06a47ab102a9d9a79..671c7a09ab3d65a43b1effae5fd3bffbcb9c22cb 100644 (file)
@@ -238,7 +238,7 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg)
 #endif
 
 #if IS_ENABLED(CONFIG_USB_SUPPORT)
-static u64 usb_dma_mask = ~(u32)0;
+static u64 __maybe_unused usb_dma_mask = ~(u32)0;
 
 #if IS_ENABLED(CONFIG_USB_MV_UDC)
 struct resource pxa168_u2o_resources[] = {
index e62273aacb43681f2bd8ab0c7e95d82d2c32020f..4ffbbd217e8286e18181fac98487a8860ead6372 100644 (file)
@@ -211,7 +211,7 @@ static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
                return PTR_ERR(base);
 
        writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
-       writel(virt_to_phys(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
+       writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
 
        iounmap(base);
 
index 6613a6ff5dbc9e35512ac94fd84904ddf2a63ee1..6cbc69c92913dbc4074a65e269bb5243e9193cdb 100644 (file)
@@ -510,6 +510,7 @@ static void __init ams_delta_init(void)
 static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
 {
        struct modem_private_data *priv = port->private_data;
+       int ret;
 
        if (IS_ERR(priv->regulator))
                return;
@@ -518,9 +519,16 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
                return;
 
        if (state == 0)
-               regulator_enable(priv->regulator);
+               ret = regulator_enable(priv->regulator);
        else if (old == 0)
-               regulator_disable(priv->regulator);
+               ret = regulator_disable(priv->regulator);
+       else
+               ret = 0;
+
+       if (ret)
+               dev_warn(port->dev,
+                        "ams_delta modem_pm: failed to %sable regulator: %d\n",
+                        state ? "dis" : "en", ret);
 }
 
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
index 4dfb995048103b8bff965b6119f3665e54887a40..95ac1929aede4d3f82cabcf627ccf548d369b6c6 100644 (file)
@@ -441,13 +441,11 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
        .chip_select            = 0,
 } };
 
-#ifdef CONFIG_PM
 static irqreturn_t
 osk_mistral_wake_interrupt(int irq, void *ignored)
 {
        return IRQ_HANDLED;
 }
-#endif
 
 static void __init osk_mistral_init(void)
 {
@@ -515,7 +513,6 @@ static void __init osk_mistral_init(void)
 
                gpio_direction_input(OMAP_MPUIO(2));
                irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
-#ifdef CONFIG_PM
                /* share the IRQ in case someone wants to use the
                 * button for more than wakeup from system sleep.
                 */
@@ -529,7 +526,6 @@ static void __init osk_mistral_init(void)
                                ret);
                } else
                        enable_irq_wake(irq);
-#endif
        } else
                printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
 
index dc9e34e670a26f280bdfe7947fa8709ee750465f..b1e661bb5521e4281a487c25cbfea12c0b29f91f 100644 (file)
@@ -28,7 +28,7 @@ static const struct of_device_id omap_dt_match_table[] __initconst = {
        { }
 };
 
-static void __init omap_generic_init(void)
+static void __init __maybe_unused omap_generic_init(void)
 {
        pdata_quirks_init(omap_dt_match_table);
 
index 1d739d1a0a657aec9ee73450154ff5b5197f8939..1cd20e4d56b06fe2afb4ce7d79bc310446e07762 100644 (file)
@@ -410,7 +410,7 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
 
-static void __init omap_hwmod_init_postsetup(void)
+static void __init __maybe_unused omap_hwmod_init_postsetup(void)
 {
        u8 postsetup_state;
 
index d44e0e2f11063134e9dd031c0a55b523dd76befa..841ba19d64a69b153a38ef594220d1a4054d7e59 100644 (file)
@@ -486,7 +486,6 @@ int __init omap3_pm_init(void)
        ret = request_irq(omap_prcm_event_to_irq("io"),
                _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
                omap3_pm_init);
-       enable_irq(omap_prcm_event_to_irq("io"));
 
        if (ret) {
                pr_err("pm: Failed to request pm_io irq\n");
index 382e236fbfd9a188a91aba9e731436dfca86dd02..64f6451499a795de85fd451903de1d9aef59ba7a 100644 (file)
@@ -692,7 +692,6 @@ static int omap3xxx_prm_late_init(void)
 {
        struct device_node *np;
        int irq_num;
-       int ret;
 
        if (!(prm_features & PRM_HAS_IO_WAKEUP))
                return 0;
@@ -712,12 +711,8 @@ static int omap3xxx_prm_late_init(void)
        }
 
        omap3xxx_prm_enable_io_wakeup();
-       ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
-       if (!ret)
-               irq_set_status_flags(omap_prcm_event_to_irq("io"),
-                                    IRQ_NOAUTOEN);
 
-       return ret;
+       return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
 }
 
 static void __exit omap3xxx_prm_exit(void)
index 87e86a4a9eadd7f6a544fb04e228a791268e6d73..3ab5df1ce900b26f91b8b582a36188bd281c6c3c 100644 (file)
@@ -336,6 +336,27 @@ static void omap44xx_prm_reconfigure_io_chain(void)
        return;
 }
 
+/**
+ * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
+ * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
+ * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
+ */
+static void __init omap44xx_prm_enable_io_wakeup(void)
+{
+       s32 inst = omap4_prmst_get_prm_dev_inst();
+
+       if (inst == PRM_INSTANCE_UNKNOWN)
+               return;
+
+       omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+                                   OMAP4430_GLOBAL_WUEN_MASK,
+                                   inst,
+                                   omap4_prcm_irq_setup.pm_ctrl);
+}
+
 /**
  * omap44xx_prm_read_reset_sources - return the last SoC reset source
  *
@@ -668,6 +689,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
        .pwrdm_has_voltdm       = omap4_check_vcvp,
 };
 
+static int omap44xx_prm_late_init(void);
+
 /*
  * XXX document
  */
@@ -675,6 +698,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
        .read_reset_sources = &omap44xx_prm_read_reset_sources,
        .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
        .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
+       .late_init = &omap44xx_prm_late_init,
        .assert_hardreset       = omap4_prminst_assert_hardreset,
        .deassert_hardreset     = omap4_prminst_deassert_hardreset,
        .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
@@ -711,6 +735,37 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
        return prm_register(&omap44xx_prm_ll_data);
 }
 
+static int omap44xx_prm_late_init(void)
+{
+       int irq_num;
+
+       if (!(prm_features & PRM_HAS_IO_WAKEUP))
+               return 0;
+
+       irq_num = of_irq_get(prm_init_data->np, 0);
+       /*
+        * Already have OMAP4 IRQ num. For all other platforms, we need
+        * IRQ numbers from DT
+        */
+       if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
+               if (irq_num == -EPROBE_DEFER)
+                       return irq_num;
+
+               /* Have nothing to do */
+               return 0;
+       }
+
+       /* Once OMAP4 DT is filled as well */
+       if (irq_num >= 0) {
+               omap4_prcm_irq_setup.irq = irq_num;
+               omap4_prcm_irq_setup.xlate_irq = NULL;
+       }
+
+       omap44xx_prm_enable_io_wakeup();
+
+       return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+}
+
 static void __exit omap44xx_prm_exit(void)
 {
        prm_unregister(&omap44xx_prm_ll_data);
index 8cadb302a7d2f54a3bbcddaf7296606293d69e4e..ffe05c27087e88340c40f3a302f87aae19e1d81e 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/of_platform.h>
 #include "common.h"
 
-static void __init sirfsoc_init_late(void)
+static void __init __maybe_unused sirfsoc_init_late(void)
 {
        sirfsoc_pm_init();
 }
index 76fbc115ec33f7bc620e462a01f80fd915e864c1..ce7d97babb0f9428803df53cae836e437ed08118 100644 (file)
@@ -566,6 +566,7 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
        bool "PXA based Toshiba e-series PDAs"
        select FB_W100
+       select FB
        select PXA25x
 
 config MACH_E330
index 990d2bf2fb45e6451226afe25a4699a14ff5f53a..9bf4ea6a6f7446b830a6bfadf5156ff9cf5aed0c 100644 (file)
 
 #include <mach/regs-ost.h>
 
-#define xip_irqpending()       (ICIP & ICMR)
+/* restored July 2017, this did not build since 2011! */
+
+#define ICIP                   io_p2v(0x40d00000)
+#define ICMR                   io_p2v(0x40d00004)
+#define xip_irqpending()       (readl(ICIP) & readl(ICMR))
 
 /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime()         (OSCR)
-#define xip_elapsed_since(x)   (signed)((OSCR - (x)) / 4)
+#define xip_currtime()         readl(OSCR)
+#define xip_elapsed_since(x)   (signed)((readl(OSCR) - (x)) / 4)
 
 /*
  * xip_cpu_idle() is used when waiting for a delay equal or larger than
index aa79fa47373ac8d3e605592cbe40e574cc9b3966..622d4e5df0293b48c697bb355a52a11613e7a629 100644 (file)
@@ -25,8 +25,8 @@
  *  *_SIZE  is the size of the region
  *  *_BASE  is the virtual address
  */
-#define RAM_SIZE               0x10000000
-#define RAM_START              0x10000000
+#define RPC_RAM_SIZE           0x10000000
+#define RPC_RAM_START          0x10000000
 
 #define EASI_SIZE              0x08000000      /* EASI I/O */
 #define EASI_START             0x08000000
index 0db46895c82a4729d40b6c94c62482cd00ae1c9b..7d52cd97d96e4091adbcff105f9a0dc8db86c83e 100644 (file)
@@ -35,6 +35,31 @@ struct clk clk_##_name = {                           \
 
 static DEFINE_SPINLOCK(clocks_lock);
 
+/* Dummy clk routine to build generic kernel parts that may be using them */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       return clk_get_rate(clk);
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+       return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
 static void clk_gpio27_enable(struct clk *clk)
 {
        /*
index b3d684098fbf545c033e56793935cee7da3e2bf0..cb76096a2e36b4ea4ccf02f983244a97919ff243 100644 (file)
@@ -20,7 +20,7 @@
 #define xip_irqpending()       (ICIP & ICMR)
 
 /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime()         (OSCR)
-#define xip_elapsed_since(x)   (signed)((OSCR - (x)) / 4)
+#define xip_currtime()         readl_relaxed(OSCR)
+#define xip_elapsed_since(x)   (signed)((readl_relaxed(OSCR) - (x)) / 4)
 
 #endif /* __ARCH_SA1100_MTD_XIP_H__ */
index 73e3adbc133096eca9cdf652d37ff110f5e35850..44438f344dc80f9c5073502fbe2019270d8df24a 100644 (file)
@@ -67,8 +67,12 @@ static int regulator_quirk_notify(struct notifier_block *nb,
 {
        struct device *dev = data;
        struct i2c_client *client;
+       static bool done;
        u32 mon;
 
+       if (done)
+               return 0;
+
        mon = ioread32(irqc + IRQC_MONITOR);
        dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
        if (mon & REGULATOR_IRQ_MASK)
@@ -99,7 +103,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
 remove:
        dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
 
-       bus_unregister_notifier(&i2c_bus_type, nb);
+       done = true;
        iounmap(irqc);
        return 0;
 }
index ac6fd1a2cb59fb43897d00581d18e53aa354ca80..3f93fac98d973dc9a952d40a98f33b9343545e8e 100644 (file)
@@ -93,3 +93,32 @@ void nuc900_subclk_enable(struct clk *clk, int enable)
 
        __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
 }
+
+/* dummy functions, should not be called */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+       WARN_ON(clk);
+       return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
index 9d00622ce8453820441e9c3c26980cab35c3dcd8..bd0f33b77f5728781f558414eebf1eb02055a78d 100644 (file)
                emac: ethernet@1c30000 {
                        compatible = "allwinner,sun50i-a64-emac";
                        syscon = <&syscon>;
-                       reg = <0x01c30000 0x100>;
+                       reg = <0x01c30000 0x10000>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
                        resets = <&ccu RST_BUS_EMAC>;
index 35b8c88c3220c84c76ce1b22c8440ad8fdcbaa10..738ed689ff692b0f16b9add648f9f32dd514d010 100644 (file)
                        };
 
                        pwm_AO_ab: pwm@550 {
-                               compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+                               compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
                                reg = <0x0 0x00550 0x0 0x10>;
                                #pwm-cells = <3>;
                                status = "disabled";
index 72c5a9f64ca8499fe83a11bdbb17c1c95c4206c6..94567eb178759c18162c276baa4ba481f903c064 100644 (file)
        status = "okay";
        pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
        pinctrl-names = "default";
-       clocks = <&clkc CLKID_FCLK_DIV4>;
-       clock-names = "clkin0";
+       clocks = <&xtal> , <&xtal>;
+       clock-names = "clkin0", "clkin1" ;
 };
 
 &pwm_ef {
index 890821d6e52b2d01a00e06d03ded2b49e091857a..266fbcf3e47f5640b565c09fae289003b7b9e679 100644 (file)
 
 #include <dt-bindings/input/input.h>
 
-#include "meson-gxl-s905x-p212.dtsi"
+#include "meson-gxl-s905x.dtsi"
 
 / {
        compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
        model = "Libre Technology CC";
 
+       aliases {
+               serial0 = &uart_AO;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
        cvbs-connector {
                compatible = "composite-video-connector";
 
                };
        };
 
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+       };
+
        hdmi-connector {
                compatible = "hdmi-connector";
                type = "a";
                        linux,default-trigger = "heartbeat";
                };
        };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+
+       vcc_3v3: regulator-vcc_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       vcc_card: regulator-vcc-card {
+               compatible = "regulator-gpio";
+
+               regulator-name = "VCC_CARD";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+               gpios-states = <0>;
+
+               states = <3300000 0>,
+                        <1800000 1>;
+       };
+
+       vddio_boot: regulator-vddio_boot {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_BOOT";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
 };
 
 &cvbs_vdac_port {
        };
 };
 
+&ethmac {
+       status = "okay";
+};
+
+&ir {
+       status = "okay";
+       pinctrl-0 = <&remote_input_ao_pins>;
+       pinctrl-names = "default";
+};
+
 &hdmi_tx {
        status = "okay";
        pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
        };
 };
 
-/*
- * The following devices exists but are exposed on the general
- * purpose GPIO header. End user may well decide to use those pins
- * for another purpose
- */
+/* SD card */
+&sd_emmc_b {
+       status = "okay";
+       pinctrl-0 = <&sdcard_pins>;
+       pinctrl-names = "default";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <100000000>;
+       disable-wp;
+
+       cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+       cd-inverted;
 
-&sd_emmc_a {
-       status = "disabled";
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vcc_card>;
 };
 
-&uart_A {
-       status = "disabled";
+/* eMMC */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_pins>;
+       pinctrl-names = "default";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       max-frequency = <50000000>;
+       non-removable;
+       disable-wp;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vddio_boot>;
 };
 
-&wifi32k {
-       status = "disabled";
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
 };
index dbcc3d4e2ed523e72bc8cd68dbf2c52503b7332f..51763d674050cb27c32b0909c62a62724d5d429d 100644 (file)
                                reg = <0x18800 0x100>, <0x18C00 0x20>;
                                gpiosb: gpio {
                                        #gpio-cells = <2>;
-                                       gpio-ranges = <&pinctrl_sb 0 0 29>;
+                                       gpio-ranges = <&pinctrl_sb 0 0 30>;
                                        gpio-controller;
                                        interrupts =
                                        <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
index 726528ce54e9650fe2b0ebfc085b0f0753e876d8..4c68605675a83db1639c0efed23788379c4d9e17 100644 (file)
                                interrupt-names = "mem", "ring0", "ring1",
                                "ring2", "ring3", "eip";
                                clocks = <&cpm_clk 1 26>;
+                               dma-coherent;
                        };
                };
 
index 95f8e5f607f608d2ec1bd258e1eec76f0d4b8528..923f354b02f00d199db276f60adffb013d688186 100644 (file)
@@ -64,7 +64,7 @@
                                compatible = "marvell,armada-8k-rtc";
                                reg = <0x284000 0x20>, <0x284080 0x24>;
                                reg-names = "rtc", "rtc-soc";
-                               interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
                        };
 
                        cps_ethernet: ethernet@0 {
                                interrupt-names = "mem", "ring0", "ring1",
                                                  "ring2", "ring3", "eip";
                                clocks = <&cps_clk 1 26>;
+                               dma-coherent;
                                /*
                                 * The cryptographic engine found on the cp110
                                 * master is enabled by default at the SoC
index aef35e0b685a3a8599f33d1b227f31d0e5f551ea..a451996f590a5173a3e9dbe56831a623e3c0639a 100644 (file)
 
        /* audio_clkout0/1/2/3 */
        #clock-cells = <1>;
-       clock-frequency = <11289600 12288000>;
+       clock-frequency = <12288000 11289600>;
 
        status = "okay";
 
index b5c6ee07d7f91d84d4b5b8e612fcc4f4304bc4c2..d1a3f3b7a0ab0b97aff29a898813a023a7d5bd3d 100644 (file)
 
        /* audio_clkout0/1/2/3 */
        #clock-cells = <1>;
-       clock-frequency = <11289600 12288000>;
+       clock-frequency = <12288000 11289600>;
 
        status = "okay";
 
index 6c7d147eed54de4cc19678ce8f318987406b0521..b4ca115b3be1c0a25121517e1e9e598d26c7c0b1 100644 (file)
@@ -476,6 +476,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_MSM_GCC_8916=y
 CONFIG_MSM_GCC_8994=y
 CONFIG_MSM_MMCC_8996=y
+CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_ARM_MHU=y
 CONFIG_PLATFORM_MHU=y
index 32f82723338a0e23bd880273aa9ae53e93a9979d..ef39dcb9ca6af1150152883cf338114536167b5f 100644 (file)
  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
  */
 #define VA_BITS                        (CONFIG_ARM64_VA_BITS)
-#define VA_START               (UL(0xffffffffffffffff) << VA_BITS)
-#define PAGE_OFFSET            (UL(0xffffffffffffffff) << (VA_BITS - 1))
+#define VA_START               (UL(0xffffffffffffffff) - \
+       (UL(1) << VA_BITS) + 1)
+#define PAGE_OFFSET            (UL(0xffffffffffffffff) - \
+       (UL(1) << (VA_BITS - 1)) + 1)
 #define KIMAGE_VADDR           (MODULES_END)
 #define MODULES_END            (MODULES_VADDR + MODULES_VSIZE)
 #define MODULES_VADDR          (VA_START + KASAN_SHADOW_SIZE)
index d48f470802136e17dfc7ec83be568b8e913e6cf4..8a62648848e5754a747649078206e782ef550172 100644 (file)
@@ -523,7 +523,7 @@ static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 {
        int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
 
-       pt_regs_write_reg(regs, rt, read_sysreg(cntfrq_el0));
+       pt_regs_write_reg(regs, rt, arch_timer_get_rate());
        regs->pc += 4;
 }
 
index 77862881ae860943b2f2553dbbd93c65b64102ab..2e070d3baf9f12db1363ed95d079b19b02ca0382 100644 (file)
@@ -764,7 +764,7 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
        if (p->is_write) {
                if (r->CRm & 0x2)
                        /* accessing PMOVSSET_EL0 */
-                       kvm_pmu_overflow_set(vcpu, p->regval & mask);
+                       vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
                else
                        /* accessing PMOVSCLR_EL0 */
                        vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
index c7861c9864e69e7b6dc7efc16083063bbab99e98..2509e4fe699225675f74876032e22b24b338a3b1 100644 (file)
@@ -163,26 +163,27 @@ int ptep_set_access_flags(struct vm_area_struct *vma,
        /* only preserve the access flags and write permission */
        pte_val(entry) &= PTE_AF | PTE_WRITE | PTE_DIRTY;
 
-       /*
-        * PTE_RDONLY is cleared by default in the asm below, so set it in
-        * back if necessary (read-only or clean PTE).
-        */
+       /* set PTE_RDONLY if actual read-only or clean PTE */
        if (!pte_write(entry) || !pte_sw_dirty(entry))
                pte_val(entry) |= PTE_RDONLY;
 
        /*
         * Setting the flags must be done atomically to avoid racing with the
-        * hardware update of the access/dirty state.
+        * hardware update of the access/dirty state. The PTE_RDONLY bit must
+        * be set to the most permissive (lowest value) of *ptep and entry
+        * (calculated as: a & b == ~(~a | ~b)).
         */
+       pte_val(entry) ^= PTE_RDONLY;
        asm volatile("//        ptep_set_access_flags\n"
        "       prfm    pstl1strm, %2\n"
        "1:     ldxr    %0, %2\n"
-       "       and     %0, %0, %3              // clear PTE_RDONLY\n"
+       "       eor     %0, %0, %3              // negate PTE_RDONLY in *ptep\n"
        "       orr     %0, %0, %4              // set flags\n"
+       "       eor     %0, %0, %3              // negate final PTE_RDONLY\n"
        "       stxr    %w1, %0, %2\n"
        "       cbnz    %w1, 1b\n"
        : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
-       : "L" (~PTE_RDONLY), "r" (pte_val(entry)));
+       : "L" (PTE_RDONLY), "r" (pte_val(entry)));
 
        flush_tlb_fix_spurious_fault(vma, address);
        return 1;
index 531da9eb8f4363ad95c65e16b3d7c9653ac973b8..dda1f558ef35c5fa9113c763c846924ee24f93dc 100644 (file)
@@ -47,6 +47,9 @@ config PARISC
          and later HP3000 series).  The PA-RISC Linux project home page is
          at <http://www.parisc-linux.org/>.
 
+config CPU_BIG_ENDIAN
+       def_bool y
+
 config MMU
        def_bool y
 
index 88fe0aad4390b10830ce1bc1be62925d4b2d4bbc..bc208136bbb26a837a978cdf77304f1c9dec0b2d 100644 (file)
@@ -34,7 +34,7 @@ struct thread_info {
 
 /* thread information allocation */
 
-#define THREAD_SIZE_ORDER      2 /* PA-RISC requires at least 16k stack */
+#define THREAD_SIZE_ORDER      3 /* PA-RISC requires at least 32k stack */
 /* Be sure to hunt all references to this down when you change the size of
  * the kernel stack */
 #define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
index 85a92db70afc99ab9151924823a3e277f1c0e8c5..19c0c141bc3f9f0edd509708f978a2d7ca16c230 100644 (file)
@@ -587,13 +587,12 @@ void flush_cache_range(struct vm_area_struct *vma,
        if (parisc_requires_coherency())
                flush_tlb_range(vma, start, end);
 
-       if ((end - start) >= parisc_cache_flush_threshold) {
+       if ((end - start) >= parisc_cache_flush_threshold
+           || vma->vm_mm->context != mfsp(3)) {
                flush_cache_all();
                return;
        }
 
-       BUG_ON(vma->vm_mm->context != mfsp(3));
-
        flush_user_dcache_range_asm(start, end);
        if (vma->vm_flags & VM_EXEC)
                flush_user_icache_range_asm(start, end);
index 5404e4086cb95d5e7a5b49e06e783f0cfdf89b8b..0ca254085a6626374ed488401618ca3af19872c7 100644 (file)
@@ -380,7 +380,7 @@ static inline int eirr_to_irq(unsigned long eirr)
 /*
  * IRQ STACK - used for irq handler
  */
-#define IRQ_STACK_SIZE      (4096 << 2) /* 16k irq stack size */
+#define IRQ_STACK_SIZE      (4096 << 3) /* 32k irq stack size */
 
 union irq_stack_union {
        unsigned long stack[IRQ_STACK_SIZE/sizeof(unsigned long)];
index a7814a7b15233261b0d9ba9d848543948dcd34d6..6f952fe1f0842232fab09eba6d89953d09946111 100644 (file)
@@ -25,12 +25,20 @@ compress-$(CONFIG_KERNEL_XZ)   := CONFIG_KERNEL_XZ
 BOOTCFLAGS    := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
                 -fno-strict-aliasing -Os -msoft-float -pipe \
                 -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
-                -isystem $(shell $(CROSS32CC) -print-file-name=include) \
                 -D$(compress-y)
 
+BOOTCC := $(CC)
 ifdef CONFIG_PPC64_BOOT_WRAPPER
 BOOTCFLAGS     += -m64
+else
+BOOTCFLAGS     += -m32
+ifdef CROSS32_COMPILE
+    BOOTCC := $(CROSS32_COMPILE)gcc
+endif
 endif
+
+BOOTCFLAGS     += -isystem $(shell $(BOOTCC) -print-file-name=include)
+
 ifdef CONFIG_CPU_BIG_ENDIAN
 BOOTCFLAGS     += -mbig-endian
 else
@@ -183,10 +191,10 @@ clean-files := $(zlib-) $(zlibheader-) $(zliblinuxheader-) \
                empty.c zImage.coff.lds zImage.ps3.lds zImage.lds
 
 quiet_cmd_bootcc = BOOTCC  $@
-      cmd_bootcc = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTCFLAGS) -c -o $@ $<
+      cmd_bootcc = $(BOOTCC) -Wp,-MD,$(depfile) $(BOOTCFLAGS) -c -o $@ $<
 
 quiet_cmd_bootas = BOOTAS  $@
-      cmd_bootas = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
+      cmd_bootas = $(BOOTCC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
 
 quiet_cmd_bootar = BOOTAR  $@
       cmd_bootar = $(CROSS32AR) -cr$(KBUILD_ARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
index d1da415e283cd270d8d2d089508558d369c7cf98..818a58fc3f4f967d3bc4524c32e64ba4529c4cca 100644 (file)
@@ -608,9 +608,17 @@ static inline pte_t pte_mkdevmap(pte_t pte)
        return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
 }
 
+/*
+ * This is potentially called with a pmd as the argument, in which case it's not
+ * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
+ * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
+ * use in page directory entries (ie. non-ptes).
+ */
 static inline int pte_devmap(pte_t pte)
 {
-       return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DEVMAP));
+       u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
+
+       return (pte_raw(pte) & mask) == mask;
 }
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
index 9029afd1fa2ab2ce231045659abf11ec9eaa32f6..f14f3c04ec7e0c7d366f60d161ff0ced6f1497ad 100644 (file)
@@ -1325,10 +1325,18 @@ EXC_VIRT_NONE(0x5800, 0x100)
        std     r10,PACA_EXGEN+EX_R13(r13);             \
        EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
 
+/*
+ * Branch to soft_nmi_interrupt using the emergency stack. The emergency
+ * stack is one that is usable by maskable interrupts so long as MSR_EE
+ * remains off. It is used for recovery when something has corrupted the
+ * normal kernel stack, for example. The "soft NMI" must not use the process
+ * stack because we want irq disabled sections to avoid touching the stack
+ * at all (other than PMU interrupts), so use the emergency stack for this,
+ * and run it entirely with interrupts hard disabled.
+ */
 EXC_COMMON_BEGIN(soft_nmi_common)
        mr      r10,r1
        ld      r1,PACAEMERGSP(r13)
-       ld      r1,PACA_NMI_EMERG_SP(r13)
        subi    r1,r1,INT_FRAME_SIZE
        EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
                        system_reset, soft_nmi_interrupt,
index 516ebef905c063b6bdb696f5f6048da37f7822cd..e6252c5a57a4a06f10bd13710ceecdcf72c3d26e 100644 (file)
@@ -460,11 +460,17 @@ pnv_restore_hyp_resource_arch300:
        /*
         * Workaround for POWER9, if we lost resources, the ERAT
         * might have been mixed up and needs flushing. We also need
-        * to reload MMCR0 (see comment above).
+        * to reload MMCR0 (see comment above). We also need to set
+        * then clear bit 60 in MMCRA to ensure the PMU starts running.
         */
        blt     cr3,1f
        PPC_INVALIDATE_ERAT
        ld      r1,PACAR1(r13)
+       mfspr   r4,SPRN_MMCRA
+       ori     r4,r4,(1 << (63-60))
+       mtspr   SPRN_MMCRA,r4
+       xori    r4,r4,(1 << (63-60))
+       mtspr   SPRN_MMCRA,r4
        ld      r4,_MMCR0(r1)
        mtspr   SPRN_MMCR0,r4
 1:
index 0bcec745a6724771c076e34132fb40e158b318f1..f291f7826abc65fe27bd9502ff45d922fa3f9e4e 100644 (file)
@@ -145,6 +145,19 @@ notrace unsigned int __check_irq_replay(void)
 
        /* Clear bit 0 which we wouldn't clear otherwise */
        local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
+       if (happened & PACA_IRQ_HARD_DIS) {
+               /*
+                * We may have missed a decrementer interrupt if hard disabled.
+                * Check the decrementer register in case we had a rollover
+                * while hard disabled.
+                */
+               if (!(happened & PACA_IRQ_DEC)) {
+                       if (decrementer_check_overflow()) {
+                               local_paca->irq_happened |= PACA_IRQ_DEC;
+                               happened |= PACA_IRQ_DEC;
+                       }
+               }
+       }
 
        /*
         * Force the delivery of pending soft-disabled interrupts on PS3.
@@ -170,7 +183,7 @@ notrace unsigned int __check_irq_replay(void)
         * in case we also had a rollover while hard disabled
         */
        local_paca->irq_happened &= ~PACA_IRQ_DEC;
-       if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow())
+       if (happened & PACA_IRQ_DEC)
                return 0x900;
 
        /* Finally check if an external interrupt happened */
index 925a4ef9055932174b4dc5a8f0424b330149132b..660ed39e9c9a59fc3b7087362787502a41ba50fd 100644 (file)
@@ -127,12 +127,19 @@ static void flush_tmregs_to_thread(struct task_struct *tsk)
         * If task is not current, it will have been flushed already to
         * it's thread_struct during __switch_to().
         *
-        * A reclaim flushes ALL the state.
+        * A reclaim flushes ALL the state or if not in TM save TM SPRs
+        * in the appropriate thread structures from live.
         */
 
-       if (tsk == current && MSR_TM_SUSPENDED(mfmsr()))
-               tm_reclaim_current(TM_CAUSE_SIGNAL);
+       if (tsk != current)
+               return;
 
+       if (MSR_TM_SUSPENDED(mfmsr())) {
+               tm_reclaim_current(TM_CAUSE_SIGNAL);
+       } else {
+               tm_enable();
+               tm_save_sprs(&(tsk->thread));
+       }
 }
 #else
 static inline void flush_tmregs_to_thread(struct task_struct *tsk) { }
index 997c88d54acf292b3e80beef1791ee2194ca9071..cf0e1245b8cc1c78948a4004be2d20c5b5ac0b78 100644 (file)
@@ -1003,21 +1003,13 @@ static struct sched_domain_topology_level powerpc_topology[] = {
        { NULL, },
 };
 
-static __init long smp_setup_cpu_workfn(void *data __always_unused)
-{
-       smp_ops->setup_cpu(boot_cpuid);
-       return 0;
-}
-
 void __init smp_cpus_done(unsigned int max_cpus)
 {
        /*
-        * We want the setup_cpu() here to be called on the boot CPU, but
-        * init might run on any CPU, so make sure it's invoked on the boot
-        * CPU.
+        * We are running pinned to the boot CPU, see rest_init().
         */
        if (smp_ops && smp_ops->setup_cpu)
-               work_on_cpu_safe(boot_cpuid, smp_setup_cpu_workfn, NULL);
+               smp_ops->setup_cpu(boot_cpuid);
 
        if (smp_ops && smp_ops->bringup_done)
                smp_ops->bringup_done();
index d7c9b186954d931c0957908dbd7a19e3f19d0610..763ffca9628d2e983299a2d44cb007cbbefd85c9 100644 (file)
@@ -89,7 +89,7 @@ static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
                        goto err;
 
                ret = of_irq_to_resource(np, 0, &res[1]);
-               if (!ret)
+               if (ret <= 0)
                        goto err;
 
                pdev = platform_device_alloc("mpc83xx_spi", i);
index 437613588df15ceab2a1ce5e88649b675c495de4..b900eb1d5e174c1cdafc0a7e9620caecac98bb69 100644 (file)
@@ -1852,6 +1852,14 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
                        /* 4GB offset bypasses 32-bit space */
                        set_dma_offset(&pdev->dev, (1ULL << 32));
                        set_dma_ops(&pdev->dev, &dma_direct_ops);
+               } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
+                       /*
+                        * Fail the request if a DMA mask between 32 and 64 bits
+                        * was requested but couldn't be fulfilled. Ideally we
+                        * would do this for 64-bits but historically we have
+                        * always fallen back to 32-bits.
+                        */
+                       return -ENOMEM;
                } else {
                        dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
                        set_dma_ops(&pdev->dev, &dma_iommu_ops);
index c74d3701ad6830fe88338c185be374f7a6730f07..207a43a2d8b337ee61d8d982341946018ded5c97 100644 (file)
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -23,7 +22,6 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_INET_AH=y
 CONFIG_INET_ESP=y
 CONFIG_INET_IPCOMP=y
-# CONFIG_INET_LRO is not set
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -69,7 +67,6 @@ CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=m
 CONFIG_PROC_KCORE=y
@@ -82,7 +79,6 @@ CONFIG_NLS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_SCHED_DEBUG is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_KGDB=y
 CONFIG_KGDB_TESTS=y
 CONFIG_CRYPTO_NULL=m
index b2e650d1764f63d430d6b96eac793621d26902da..ca8609d7292ffee5ffbf068eb2b11653bf59ff7c 100644 (file)
@@ -1,5 +1,4 @@
 CONFIG_64BIT=y
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -184,7 +183,6 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=m
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 CONFIG_USB_OHCI_HCD=y
@@ -210,8 +208,6 @@ CONFIG_LOCKUP_DETECTOR=y
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_SCHEDSTATS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_UPROBE_EVENTS=y
 CONFIG_KEYS=y
index 2cddcda4f85f7555dced053b1fc82fd991e19943..87841d687f8d5306663c54d050aa0ca4b2b08cd7 100644 (file)
@@ -27,9 +27,11 @@ void destroy_context(struct mm_struct *mm);
 void __tsb_context_switch(unsigned long pgd_pa,
                          struct tsb_config *tsb_base,
                          struct tsb_config *tsb_huge,
-                         unsigned long tsb_descr_pa);
+                         unsigned long tsb_descr_pa,
+                         unsigned long secondary_ctx);
 
-static inline void tsb_context_switch(struct mm_struct *mm)
+static inline void tsb_context_switch_ctx(struct mm_struct *mm,
+                                         unsigned long ctx)
 {
        __tsb_context_switch(__pa(mm->pgd),
                             &mm->context.tsb_block[MM_TSB_BASE],
@@ -40,9 +42,12 @@ static inline void tsb_context_switch(struct mm_struct *mm)
 #else
                             NULL
 #endif
-                            , __pa(&mm->context.tsb_descr[MM_TSB_BASE]));
+                            , __pa(&mm->context.tsb_descr[MM_TSB_BASE]),
+                            ctx);
 }
 
+#define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
+
 void tsb_grow(struct mm_struct *mm,
              unsigned long tsb_index,
              unsigned long mm_rss);
@@ -112,8 +117,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
         * cpu0 to update it's TSB because at that point the cpu_vm_mask
         * only had cpu1 set in it.
         */
-       load_secondary_context(mm);
-       tsb_context_switch(mm);
+       tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
 
        /* Any time a processor runs a context on an address space
         * for the first time, we must flush that context out of the
index 07c0df92496034efd1262dd2b40e56ffd5486c0c..db872dbfafe943fd92ca10b9995b003ed6a1aee7 100644 (file)
@@ -360,6 +360,7 @@ tsb_flush:
         * %o1: TSB base config pointer
         * %o2: TSB huge config pointer, or NULL if none
         * %o3: Hypervisor TSB descriptor physical address
+        * %o4: Secondary context to load, if non-zero
         *
         * We have to run this whole thing with interrupts
         * disabled so that the current cpu doesn't change
@@ -372,6 +373,17 @@ __tsb_context_switch:
        rdpr    %pstate, %g1
        wrpr    %g1, PSTATE_IE, %pstate
 
+       brz,pn  %o4, 1f
+        mov    SECONDARY_CONTEXT, %o5
+
+661:   stxa    %o4, [%o5] ASI_DMMU
+       .section .sun4v_1insn_patch, "ax"
+       .word   661b
+       stxa    %o4, [%o5] ASI_MMU
+       .previous
+       flush   %g6
+
+1:
        TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
 
        stx     %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
index 54f98706b03b2f53025adb99e086002a0629e9f0..5a8cb37f0a3b8e31d0a4194d831bb39559bb6a51 100644 (file)
@@ -145,13 +145,13 @@ ENDPROC(U3_retl_o2_plus_GS_plus_0x08)
 ENTRY(U3_retl_o2_and_7_plus_GS)
        and     %o2, 7, %o2
        retl
-        add    %o2, GLOBAL_SPARE, %o2
+        add    %o2, GLOBAL_SPARE, %o0
 ENDPROC(U3_retl_o2_and_7_plus_GS)
 ENTRY(U3_retl_o2_and_7_plus_GS_plus_8)
        add     GLOBAL_SPARE, 8, GLOBAL_SPARE
        and     %o2, 7, %o2
        retl
-        add    %o2, GLOBAL_SPARE, %o2
+        add    %o2, GLOBAL_SPARE, %o0
 ENDPROC(U3_retl_o2_and_7_plus_GS_plus_8)
 #endif
 
index 3c40ebd50f928cbbbfe69c65c35810a78b30c53d..fed73f14aa49befee59b93b0fcab02f65f7e10d2 100644 (file)
@@ -325,6 +325,29 @@ static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_inde
 }
 
 #ifdef CONFIG_HUGETLB_PAGE
+static void __init add_huge_page_size(unsigned long size)
+{
+       unsigned int order;
+
+       if (size_to_hstate(size))
+               return;
+
+       order = ilog2(size) - PAGE_SHIFT;
+       hugetlb_add_hstate(order);
+}
+
+static int __init hugetlbpage_init(void)
+{
+       add_huge_page_size(1UL << HPAGE_64K_SHIFT);
+       add_huge_page_size(1UL << HPAGE_SHIFT);
+       add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
+       add_huge_page_size(1UL << HPAGE_2GB_SHIFT);
+
+       return 0;
+}
+
+arch_initcall(hugetlbpage_init);
+
 static int __init setup_hugepagesz(char *string)
 {
        unsigned long long hugepage_size;
@@ -364,7 +387,7 @@ static int __init setup_hugepagesz(char *string)
                goto out;
        }
 
-       hugetlb_add_hstate(hugepage_shift - PAGE_SHIFT);
+       add_huge_page_size(hugepage_size);
        rc = 1;
 
 out:
index 17bd2e167e07edd934dfe9957c43712b21401c55..df707a8ad3117074805e138a3992a7e080d43e5a 100644 (file)
@@ -35,6 +35,5 @@ void restore_processor_state(void)
 {
        struct mm_struct *mm = current->active_mm;
 
-       load_secondary_context(mm);
-       tsb_context_switch(mm);
+       tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
 }
index d869c8671e364d55e343322b410fec9a3e5f66c6..7cf7c70b6ef2a20483361fb8333a85ace25bf1d7 100644 (file)
@@ -8,20 +8,25 @@
  * This file is licensed under GPLv2.
  */
 
-#include <linux/jiffies.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
 #include <linux/math64.h>
 #include <linux/percpu.h>
 #include <linux/smp.h>
 
 struct aperfmperf_sample {
        unsigned int    khz;
-       unsigned long   jiffies;
+       ktime_t time;
        u64     aperf;
        u64     mperf;
 };
 
 static DEFINE_PER_CPU(struct aperfmperf_sample, samples);
 
+#define APERFMPERF_CACHE_THRESHOLD_MS  10
+#define APERFMPERF_REFRESH_DELAY_MS    20
+#define APERFMPERF_STALE_THRESHOLD_MS  1000
+
 /*
  * aperfmperf_snapshot_khz()
  * On the current CPU, snapshot APERF, MPERF, and jiffies
@@ -33,9 +38,11 @@ static void aperfmperf_snapshot_khz(void *dummy)
        u64 aperf, aperf_delta;
        u64 mperf, mperf_delta;
        struct aperfmperf_sample *s = this_cpu_ptr(&samples);
+       ktime_t now = ktime_get();
+       s64 time_delta = ktime_ms_delta(now, s->time);
 
-       /* Don't bother re-computing within 10 ms */
-       if (time_before(jiffies, s->jiffies + HZ/100))
+       /* Don't bother re-computing within the cache threshold time. */
+       if (time_delta < APERFMPERF_CACHE_THRESHOLD_MS)
                return;
 
        rdmsrl(MSR_IA32_APERF, aperf);
@@ -51,22 +58,21 @@ static void aperfmperf_snapshot_khz(void *dummy)
        if (mperf_delta == 0)
                return;
 
-       /*
-        * if (cpu_khz * aperf_delta) fits into ULLONG_MAX, then
-        *      khz = (cpu_khz * aperf_delta) / mperf_delta
-        */
-       if (div64_u64(ULLONG_MAX, cpu_khz) > aperf_delta)
-               s->khz = div64_u64((cpu_khz * aperf_delta), mperf_delta);
-       else    /* khz = aperf_delta / (mperf_delta / cpu_khz) */
-               s->khz = div64_u64(aperf_delta,
-                       div64_u64(mperf_delta, cpu_khz));
-       s->jiffies = jiffies;
+       s->time = now;
        s->aperf = aperf;
        s->mperf = mperf;
+
+       /* If the previous iteration was too long ago, discard it. */
+       if (time_delta > APERFMPERF_STALE_THRESHOLD_MS)
+               s->khz = 0;
+       else
+               s->khz = div64_u64((cpu_khz * aperf_delta), mperf_delta);
 }
 
 unsigned int arch_freq_get_on_cpu(int cpu)
 {
+       unsigned int khz;
+
        if (!cpu_khz)
                return 0;
 
@@ -74,6 +80,12 @@ unsigned int arch_freq_get_on_cpu(int cpu)
                return 0;
 
        smp_call_function_single(cpu, aperfmperf_snapshot_khz, NULL, 1);
+       khz = per_cpu(samples.khz, cpu);
+       if (khz)
+               return khz;
+
+       msleep(APERFMPERF_REFRESH_DELAY_MS);
+       smp_call_function_single(cpu, aperfmperf_snapshot_khz, NULL, 1);
 
        return per_cpu(samples.khz, cpu);
 }
index 16f82a3aaec7c9c8d85e7c8b4f805da396981fce..8ce4212e2b8d0f139e543e05e7e284ee25ee856d 100644 (file)
@@ -345,21 +345,10 @@ static int hpet_shutdown(struct clock_event_device *evt, int timer)
        return 0;
 }
 
-static int hpet_resume(struct clock_event_device *evt, int timer)
-{
-       if (!timer) {
-               hpet_enable_legacy_int();
-       } else {
-               struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
-
-               irq_domain_deactivate_irq(irq_get_irq_data(hdev->irq));
-               irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
-               disable_hardirq(hdev->irq);
-               irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
-               enable_irq(hdev->irq);
-       }
+static int hpet_resume(struct clock_event_device *evt)
+{
+       hpet_enable_legacy_int();
        hpet_print_config();
-
        return 0;
 }
 
@@ -417,7 +406,7 @@ static int hpet_legacy_set_periodic(struct clock_event_device *evt)
 
 static int hpet_legacy_resume(struct clock_event_device *evt)
 {
-       return hpet_resume(evt, 0);
+       return hpet_resume(evt);
 }
 
 static int hpet_legacy_next_event(unsigned long delta,
@@ -510,8 +499,14 @@ static int hpet_msi_set_periodic(struct clock_event_device *evt)
 static int hpet_msi_resume(struct clock_event_device *evt)
 {
        struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
+       struct irq_data *data = irq_get_irq_data(hdev->irq);
+       struct msi_msg msg;
 
-       return hpet_resume(evt, hdev->num);
+       /* Restore the MSI msg and unmask the interrupt */
+       irq_chip_compose_msi_msg(data, &msg);
+       hpet_msi_write(hdev, &msg);
+       hpet_msi_unmask(data);
+       return 0;
 }
 
 static int hpet_msi_next_event(unsigned long delta,
index 71c17a5be983524ea277718b759ff1511a9a3214..d04e30e3c0ffd3f255f50e595c0ab0f919fddc70 100644 (file)
@@ -151,6 +151,8 @@ void kvm_async_pf_task_wait(u32 token)
                if (hlist_unhashed(&n.link))
                        break;
 
+               rcu_irq_exit();
+
                if (!n.halted) {
                        local_irq_enable();
                        schedule();
@@ -159,11 +161,11 @@ void kvm_async_pf_task_wait(u32 token)
                        /*
                         * We cannot reschedule. So halt.
                         */
-                       rcu_irq_exit();
                        native_safe_halt();
                        local_irq_disable();
-                       rcu_irq_enter();
                }
+
+               rcu_irq_enter();
        }
        if (!n.halted)
                finish_swait(&n.wq, &wait);
index 4d8141e533c369711df245d0a783683598ad4559..1107626938ccff4f26da130f8b570928ca7c8efb 100644 (file)
@@ -2430,6 +2430,16 @@ static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
        svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
        svm->vmcb->control.exit_code_hi = 0;
        svm->vmcb->control.exit_info_1 = error_code;
+
+       /*
+        * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
+        * The fix is to add the ancillary datum (CR2 or DR6) to structs
+        * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
+        * written only when inject_pending_event runs (DR6 would written here
+        * too).  This should be conditional on a new capability---if the
+        * capability is disabled, kvm_multiple_exception would write the
+        * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
+        */
        if (svm->vcpu.arch.exception.nested_apf)
                svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
        else
index 39a6222bf9687fcc47dea3ee564eaa92704026e9..9b21b12230354e334900e6536b7612285f75b7e3 100644 (file)
@@ -416,13 +416,10 @@ struct nested_vmx {
 
        /* The guest-physical address of the current VMCS L1 keeps for L2 */
        gpa_t current_vmptr;
-       /* The host-usable pointer to the above */
-       struct page *current_vmcs12_page;
-       struct vmcs12 *current_vmcs12;
        /*
         * Cache of the guest's VMCS, existing outside of guest memory.
         * Loaded from guest memory during VMPTRLD. Flushed to guest
-        * memory during VMXOFF, VMCLEAR, VMPTRLD.
+        * memory during VMCLEAR and VMPTRLD.
         */
        struct vmcs12 *cached_vmcs12;
        /*
@@ -927,6 +924,10 @@ static u32 vmx_segment_access_rights(struct kvm_segment *var);
 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 static int alloc_identity_pagetable(struct kvm *kvm);
+static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
+static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
+static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
+                                           u16 error_code);
 
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -2428,6 +2429,30 @@ static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
        vmx_set_interrupt_shadow(vcpu, 0);
 }
 
+static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
+                                              unsigned long exit_qual)
+{
+       struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+       unsigned int nr = vcpu->arch.exception.nr;
+       u32 intr_info = nr | INTR_INFO_VALID_MASK;
+
+       if (vcpu->arch.exception.has_error_code) {
+               vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
+               intr_info |= INTR_INFO_DELIVER_CODE_MASK;
+       }
+
+       if (kvm_exception_is_soft(nr))
+               intr_info |= INTR_TYPE_SOFT_EXCEPTION;
+       else
+               intr_info |= INTR_TYPE_HARD_EXCEPTION;
+
+       if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
+           vmx_get_nmi_mask(vcpu))
+               intr_info |= INTR_INFO_UNBLOCK_NMI;
+
+       nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
+}
+
 /*
  * KVM wants to inject page-faults which it got to the guest. This function
  * checks whether in a nested guest, we need to inject them to L1 or L2.
@@ -2437,23 +2462,38 @@ static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
        unsigned int nr = vcpu->arch.exception.nr;
 
-       if (!((vmcs12->exception_bitmap & (1u << nr)) ||
-               (nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
-               return 0;
+       if (nr == PF_VECTOR) {
+               if (vcpu->arch.exception.nested_apf) {
+                       nested_vmx_inject_exception_vmexit(vcpu,
+                                                          vcpu->arch.apf.nested_apf_token);
+                       return 1;
+               }
+               /*
+                * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
+                * The fix is to add the ancillary datum (CR2 or DR6) to structs
+                * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
+                * can be written only when inject_pending_event runs.  This should be
+                * conditional on a new capability---if the capability is disabled,
+                * kvm_multiple_exception would write the ancillary information to
+                * CR2 or DR6, for backwards ABI-compatibility.
+                */
+               if (nested_vmx_is_page_fault_vmexit(vmcs12,
+                                                   vcpu->arch.exception.error_code)) {
+                       nested_vmx_inject_exception_vmexit(vcpu, vcpu->arch.cr2);
+                       return 1;
+               }
+       } else {
+               unsigned long exit_qual = 0;
+               if (nr == DB_VECTOR)
+                       exit_qual = vcpu->arch.dr6;
 
-       if (vcpu->arch.exception.nested_apf) {
-               vmcs_write32(VM_EXIT_INTR_ERROR_CODE, vcpu->arch.exception.error_code);
-               nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
-                       PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
-                       INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
-                       vcpu->arch.apf.nested_apf_token);
-               return 1;
+               if (vmcs12->exception_bitmap & (1u << nr)) {
+                       nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
+                       return 1;
+               }
        }
 
-       nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
-                         vmcs_read32(VM_EXIT_INTR_INFO),
-                         vmcs_readl(EXIT_QUALIFICATION));
-       return 1;
+       return 0;
 }
 
 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
@@ -2667,7 +2707,7 @@ static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
         * reason is that if one of these bits is necessary, it will appear
         * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
         * fields of vmcs01 and vmcs02, will turn these bits off - and
-        * nested_vmx_exit_handled() will not pass related exits to L1.
+        * nested_vmx_exit_reflected() will not pass related exits to L1.
         * These rules have exceptions below.
         */
 
@@ -4955,6 +4995,28 @@ static bool vmx_get_enable_apicv(void)
        return enable_apicv;
 }
 
+static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
+{
+       struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+       gfn_t gfn;
+
+       /*
+        * Don't need to mark the APIC access page dirty; it is never
+        * written to by the CPU during APIC virtualization.
+        */
+
+       if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
+               gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
+               kvm_vcpu_mark_page_dirty(vcpu, gfn);
+       }
+
+       if (nested_cpu_has_posted_intr(vmcs12)) {
+               gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
+               kvm_vcpu_mark_page_dirty(vcpu, gfn);
+       }
+}
+
+
 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
 {
        struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -4962,18 +5024,15 @@ static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
        void *vapic_page;
        u16 status;
 
-       if (vmx->nested.pi_desc &&
-           vmx->nested.pi_pending) {
-               vmx->nested.pi_pending = false;
-               if (!pi_test_and_clear_on(vmx->nested.pi_desc))
-                       return;
-
-               max_irr = find_last_bit(
-                       (unsigned long *)vmx->nested.pi_desc->pir, 256);
+       if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
+               return;
 
-               if (max_irr == 256)
-                       return;
+       vmx->nested.pi_pending = false;
+       if (!pi_test_and_clear_on(vmx->nested.pi_desc))
+               return;
 
+       max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
+       if (max_irr != 256) {
                vapic_page = kmap(vmx->nested.virtual_apic_page);
                __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
                kunmap(vmx->nested.virtual_apic_page);
@@ -4985,6 +5044,8 @@ static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
                        vmcs_write16(GUEST_INTR_STATUS, status);
                }
        }
+
+       nested_mark_vmcs12_pages_dirty(vcpu);
 }
 
 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
@@ -7134,34 +7195,32 @@ static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
        return 1;
 }
 
+static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
+{
+       vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
+       vmcs_write64(VMCS_LINK_POINTER, -1ull);
+}
+
 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
 {
        if (vmx->nested.current_vmptr == -1ull)
                return;
 
-       /* current_vmptr and current_vmcs12 are always set/reset together */
-       if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
-               return;
-
        if (enable_shadow_vmcs) {
                /* copy to memory all shadowed fields in case
                   they were modified */
                copy_shadow_to_vmcs12(vmx);
                vmx->nested.sync_shadow_vmcs = false;
-               vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
-                               SECONDARY_EXEC_SHADOW_VMCS);
-               vmcs_write64(VMCS_LINK_POINTER, -1ull);
+               vmx_disable_shadow_vmcs(vmx);
        }
        vmx->nested.posted_intr_nv = -1;
 
        /* Flush VMCS12 to guest memory */
-       memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
-              VMCS12_SIZE);
+       kvm_vcpu_write_guest_page(&vmx->vcpu,
+                                 vmx->nested.current_vmptr >> PAGE_SHIFT,
+                                 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
 
-       kunmap(vmx->nested.current_vmcs12_page);
-       nested_release_page(vmx->nested.current_vmcs12_page);
        vmx->nested.current_vmptr = -1ull;
-       vmx->nested.current_vmcs12 = NULL;
 }
 
 /*
@@ -7175,12 +7234,14 @@ static void free_nested(struct vcpu_vmx *vmx)
 
        vmx->nested.vmxon = false;
        free_vpid(vmx->nested.vpid02);
-       nested_release_vmcs12(vmx);
+       vmx->nested.posted_intr_nv = -1;
+       vmx->nested.current_vmptr = -1ull;
        if (vmx->nested.msr_bitmap) {
                free_page((unsigned long)vmx->nested.msr_bitmap);
                vmx->nested.msr_bitmap = NULL;
        }
        if (enable_shadow_vmcs) {
+               vmx_disable_shadow_vmcs(vmx);
                vmcs_clear(vmx->vmcs01.shadow_vmcs);
                free_vmcs(vmx->vmcs01.shadow_vmcs);
                vmx->vmcs01.shadow_vmcs = NULL;
@@ -7579,14 +7640,14 @@ static int handle_vmptrld(struct kvm_vcpu *vcpu)
                }
 
                nested_release_vmcs12(vmx);
-               vmx->nested.current_vmcs12 = new_vmcs12;
-               vmx->nested.current_vmcs12_page = page;
                /*
                 * Load VMCS12 from guest memory since it is not already
                 * cached.
                 */
-               memcpy(vmx->nested.cached_vmcs12,
-                      vmx->nested.current_vmcs12, VMCS12_SIZE);
+               memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
+               kunmap(page);
+               nested_release_page_clean(page);
+
                set_current_vmptr(vmx, vmptr);
        }
 
@@ -8019,12 +8080,11 @@ static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
  * should handle it ourselves in L0 (and then continue L2). Only call this
  * when in is_guest_mode (L2).
  */
-static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
+static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
 {
        u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
        struct vcpu_vmx *vmx = to_vmx(vcpu);
        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-       u32 exit_reason = vmx->exit_reason;
 
        trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
                                vmcs_readl(EXIT_QUALIFICATION),
@@ -8033,6 +8093,18 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
                                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
                                KVM_ISA_VMX);
 
+       /*
+        * The host physical addresses of some pages of guest memory
+        * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
+        * may write to these pages via their host physical address while
+        * L2 is running, bypassing any address-translation-based dirty
+        * tracking (e.g. EPT write protection).
+        *
+        * Mark them dirty on every exit from L2 to prevent them from
+        * getting out of sync with dirty tracking.
+        */
+       nested_mark_vmcs12_pages_dirty(vcpu);
+
        if (vmx->nested.nested_run_pending)
                return false;
 
@@ -8169,6 +8241,29 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
        }
 }
 
+static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
+{
+       u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
+
+       /*
+        * At this point, the exit interruption info in exit_intr_info
+        * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
+        * we need to query the in-kernel LAPIC.
+        */
+       WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
+       if ((exit_intr_info &
+            (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
+           (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
+               struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+               vmcs12->vm_exit_intr_error_code =
+                       vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
+       }
+
+       nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
+                         vmcs_readl(EXIT_QUALIFICATION));
+       return 1;
+}
+
 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
 {
        *info1 = vmcs_readl(EXIT_QUALIFICATION);
@@ -8415,12 +8510,8 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
        if (vmx->emulation_required)
                return handle_invalid_guest_state(vcpu);
 
-       if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
-               nested_vmx_vmexit(vcpu, exit_reason,
-                                 vmcs_read32(VM_EXIT_INTR_INFO),
-                                 vmcs_readl(EXIT_QUALIFICATION));
-               return 1;
-       }
+       if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
+               return nested_vmx_reflect_vmexit(vcpu, exit_reason);
 
        if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
                dump_vmcs();
@@ -9223,7 +9314,6 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
 
        vmx->nested.posted_intr_nv = -1;
        vmx->nested.current_vmptr = -1ull;
-       vmx->nested.current_vmcs12 = NULL;
 
        vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
 
@@ -9509,12 +9599,15 @@ static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
 
        WARN_ON(!is_guest_mode(vcpu));
 
-       if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
-               nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
-                                 vmcs_read32(VM_EXIT_INTR_INFO),
-                                 vmcs_readl(EXIT_QUALIFICATION));
-       else
+       if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {
+               vmcs12->vm_exit_intr_error_code = fault->error_code;
+               nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
+                                 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
+                                 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
+                                 fault->address);
+       } else {
                kvm_inject_page_fault(vcpu, fault);
+       }
 }
 
 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
@@ -10094,12 +10187,6 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
         * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
         * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
         * !enable_ept, EB.PF is 1, so the "or" will always be 1.
-        *
-        * A problem with this approach (when !enable_ept) is that L1 may be
-        * injected with more page faults than it asked for. This could have
-        * caused problems, but in practice existing hypervisors don't care.
-        * To fix this, we will need to emulate the PFEC checking (on the L1
-        * page tables), using walk_addr(), when injecting PFs to L1.
         */
        vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
                enable_ept ? vmcs12->page_fault_error_code_mask : 0);
@@ -10847,13 +10934,8 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
 
        vmcs12->vm_exit_reason = exit_reason;
        vmcs12->exit_qualification = exit_qualification;
-
        vmcs12->vm_exit_intr_info = exit_intr_info;
-       if ((vmcs12->vm_exit_intr_info &
-            (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
-           (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
-               vmcs12->vm_exit_intr_error_code =
-                       vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
+
        vmcs12->idt_vectoring_info_field = 0;
        vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
        vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
@@ -11049,8 +11131,15 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
 
        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
 
-       if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
-           && nested_exit_intr_ack_set(vcpu)) {
+       /*
+        * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
+        * the VM-exit interrupt information (valid interrupt) is always set to
+        * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
+        * kvm_cpu_has_interrupt().  See the commit message for details.
+        */
+       if (nested_exit_intr_ack_set(vcpu) &&
+           exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
+           kvm_cpu_has_interrupt(vcpu)) {
                int irq = kvm_cpu_get_interrupt(vcpu);
                WARN_ON(irq < 0);
                vmcs12->vm_exit_intr_info = irq |
index 6c97c82814c45a2412da6e28b4393606da450bb3..d734aa8c5b4f7290e365badd00ea962fd0af9acd 100644 (file)
@@ -3159,15 +3159,18 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
                kvm_set_hflags(vcpu, hflags);
 
                vcpu->arch.smi_pending = events->smi.pending;
-               if (events->smi.smm_inside_nmi)
-                       vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
-               else
-                       vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
-               if (lapic_in_kernel(vcpu)) {
-                       if (events->smi.latched_init)
-                               set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
+
+               if (events->smi.smm) {
+                       if (events->smi.smm_inside_nmi)
+                               vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
                        else
-                               clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
+                               vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
+                       if (lapic_in_kernel(vcpu)) {
+                               if (events->smi.latched_init)
+                                       set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
+                               else
+                                       clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
+                       }
                }
        }
 
@@ -6215,6 +6218,7 @@ static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
 
        lapic_irq.shorthand = 0;
        lapic_irq.dest_mode = 0;
+       lapic_irq.level = 0;
        lapic_irq.dest_id = apicid;
        lapic_irq.msi_redir_hint = false;
 
index fc6c416f8724670aef2f29d4d81d373ed400dcd5..d5999eb41c00176e840d90b84241ab855c8881c4 100644 (file)
@@ -180,8 +180,8 @@ static const struct acpi_device_id acpi_apd_device_ids[] = {
        { "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
        { "BRCM900D", APD_ADDR(vulcan_spi_desc) },
        { "CAV900D",  APD_ADDR(vulcan_spi_desc) },
-       { "HISI0A21", APD_ADDR(hip07_i2c_desc) },
-       { "HISI0A22", APD_ADDR(hip08_i2c_desc) },
+       { "HISI02A1", APD_ADDR(hip07_i2c_desc) },
+       { "HISI02A2", APD_ADDR(hip08_i2c_desc) },
 #endif
        { }
 };
index e51a1e98e62f4f5ab5f2132184e9686ab1a1f3a9..f88caf5aab76217d73feb277b1918e399cc61beb 100644 (file)
@@ -85,6 +85,7 @@ static const struct lpss_device_desc lpss_dma_desc = {
 };
 
 struct lpss_private_data {
+       struct acpi_device *adev;
        void __iomem *mmio_base;
        resource_size_t mmio_size;
        unsigned int fixed_clk_rate;
@@ -155,6 +156,12 @@ static struct pwm_lookup byt_pwm_lookup[] = {
 
 static void byt_pwm_setup(struct lpss_private_data *pdata)
 {
+       struct acpi_device *adev = pdata->adev;
+
+       /* Only call pwm_add_table for the first PWM controller */
+       if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
+               return;
+
        if (!acpi_dev_present("INT33FD", NULL, -1))
                pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
 }
@@ -180,6 +187,12 @@ static struct pwm_lookup bsw_pwm_lookup[] = {
 
 static void bsw_pwm_setup(struct lpss_private_data *pdata)
 {
+       struct acpi_device *adev = pdata->adev;
+
+       /* Only call pwm_add_table for the first PWM controller */
+       if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
+               return;
+
        pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
 }
 
@@ -456,6 +469,7 @@ static int acpi_lpss_create_device(struct acpi_device *adev,
                goto err_out;
        }
 
+       pdata->adev = adev;
        pdata->dev_desc = dev_desc;
 
        if (dev_desc->setup)
index 8c4e0a18460a78df600067da69537e6256d6bc1c..bf22c29d25179e937523c026c8028f644f3379f6 100644 (file)
@@ -86,7 +86,12 @@ void __init acpi_watchdog_init(void)
 
                found = false;
                resource_list_for_each_entry(rentry, &resource_list) {
-                       if (resource_contains(rentry->res, &res)) {
+                       if (rentry->res->flags == res.flags &&
+                           resource_overlaps(rentry->res, &res)) {
+                               if (res.start < rentry->res->start)
+                                       rentry->res->start = res.start;
+                               if (res.end > rentry->res->end)
+                                       rentry->res->end = res.end;
                                found = true;
                                break;
                        }
index 948fc86980a1b75d1b9f99e9588bf894e024a88c..363fc5330c211456762e049d1569a04940c580ef 100644 (file)
@@ -215,7 +215,7 @@ config SATA_FSL
 
 config SATA_GEMINI
        tristate "Gemini SATA bridge support"
-       depends on PATA_FTIDE010
+       depends on ARCH_GEMINI || COMPILE_TEST
        default ARCH_GEMINI
        help
          This enabled support for the FTIDE010 to SATA bridge
@@ -613,7 +613,7 @@ config PATA_FTIDE010
        tristate "Faraday Technology FTIDE010 PATA support"
        depends on OF
        depends on ARM
-       default ARCH_GEMINI
+       depends on SATA_GEMINI
        help
          This option enables support for the Faraday FTIDE010
          PATA controller found in the Cortina Gemini SoCs.
index 8453f9a4682f855e910f59d1d78860f639d4bf59..fa7dd4394c02b642c00119bd00a4b59b18921a0d 100644 (file)
@@ -2083,7 +2083,7 @@ unsigned int ata_read_log_page(struct ata_device *dev, u8 log,
 retry:
        ata_tf_init(dev, &tf);
        if (dev->dma_mode && ata_id_has_read_log_dma_ext(dev->id) &&
-           !(dev->horkage & ATA_HORKAGE_NO_NCQ_LOG)) {
+           !(dev->horkage & ATA_HORKAGE_NO_DMA_LOG)) {
                tf.command = ATA_CMD_READ_LOG_DMA_EXT;
                tf.protocol = ATA_PROT_DMA;
                dma = true;
@@ -2102,8 +2102,8 @@ retry:
                                     buf, sectors * ATA_SECT_SIZE, 0);
 
        if (err_mask && dma) {
-               dev->horkage |= ATA_HORKAGE_NO_NCQ_LOG;
-               ata_dev_warn(dev, "READ LOG DMA EXT failed, trying unqueued\n");
+               dev->horkage |= ATA_HORKAGE_NO_DMA_LOG;
+               ata_dev_warn(dev, "READ LOG DMA EXT failed, trying PIO\n");
                goto retry;
        }
 
index b70bcf6d2914b6a82967fee346f5865b5c3b66b8..3dbd05532c09cdde995935539efa917e4f96dcd9 100644 (file)
@@ -1434,7 +1434,7 @@ void ata_eh_about_to_do(struct ata_link *link, struct ata_device *dev,
 
 /**
  *     ata_eh_done - EH action complete
-*      @ap: target ATA port
+ *     @link: ATA link for which EH actions are complete
  *     @dev: target ATA dev for per-dev action (can be NULL)
  *     @action: action just completed
  *
@@ -1576,7 +1576,7 @@ unsigned int atapi_eh_tur(struct ata_device *dev, u8 *r_sense_key)
 
 /**
  *     ata_eh_request_sense - perform REQUEST_SENSE_DATA_EXT
- *     @dev: device to perform REQUEST_SENSE_SENSE_DATA_EXT to
+ *     @qc: qc to perform REQUEST_SENSE_SENSE_DATA_EXT to
  *     @cmd: scsi command for which the sense code should be set
  *
  *     Perform REQUEST_SENSE_DATA_EXT after the device reported CHECK
@@ -4175,7 +4175,6 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
        struct ata_link *link;
        struct ata_device *dev;
        unsigned long flags;
-       int rc = 0;
 
        /* are we resuming? */
        spin_lock_irqsave(ap->lock, flags);
@@ -4202,7 +4201,7 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
        ata_acpi_set_state(ap, ap->pm_mesg);
 
        if (ap->ops->port_resume)
-               rc = ap->ops->port_resume(ap);
+               ap->ops->port_resume(ap);
 
        /* tell ACPI that we're resuming */
        ata_acpi_on_resume(ap);
index d462c5a3a7efd8b3c4933df845c0f3f1d8637bac..44ba292f2cd793f07e279ada3b2c83c44578f0cf 100644 (file)
@@ -3030,10 +3030,12 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
 static struct ata_device *ata_find_dev(struct ata_port *ap, int devno)
 {
        if (!sata_pmp_attached(ap)) {
-               if (likely(devno < ata_link_max_devices(&ap->link)))
+               if (likely(devno >= 0 &&
+                          devno < ata_link_max_devices(&ap->link)))
                        return &ap->link.device[devno];
        } else {
-               if (likely(devno < ap->nr_pmp_links))
+               if (likely(devno >= 0 &&
+                          devno < ap->nr_pmp_links))
                        return &ap->pmp_link[devno].device[0];
        }
 
index ee98447587366f240a580e56a49e0983f58727e2..537d11869069aae7d26e1e253ed3f4d587d25bbf 100644 (file)
@@ -858,6 +858,14 @@ static const struct of_device_id sata_rcar_match[] = {
                .compatible = "renesas,sata-r8a7795",
                .data = (void *)RCAR_GEN2_SATA
        },
+       {
+               .compatible = "renesas,rcar-gen2-sata",
+               .data = (void *)RCAR_GEN2_SATA
+       },
+       {
+               .compatible = "renesas,rcar-gen3-sata",
+               .data = (void *)RCAR_GEN2_SATA
+       },
        { },
 };
 MODULE_DEVICE_TABLE(of, sata_rcar_match);
index 1e6e0269edcc18ed9f7c8e4cc65e6ce6595c8683..f76be6bd6eb3dfd52bac8c847f3a93e5c3f7777c 100644 (file)
@@ -256,10 +256,23 @@ static int uniphier_system_bus_probe(struct platform_device *pdev)
 
        uniphier_system_bus_set_reg(priv);
 
+       platform_set_drvdata(pdev, priv);
+
        /* Now, the bus is configured.  Populate platform_devices below it */
        return of_platform_default_populate(dev->of_node, NULL, dev);
 }
 
+static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
+{
+       uniphier_system_bus_set_reg(dev_get_drvdata(dev));
+
+       return 0;
+}
+
+static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
+       SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
+};
+
 static const struct of_device_id uniphier_system_bus_match[] = {
        { .compatible = "socionext,uniphier-system-bus" },
        { /* sentinel */ }
@@ -271,6 +284,7 @@ static struct platform_driver uniphier_system_bus_driver = {
        .driver = {
                .name   = "uniphier-system-bus",
                .of_match_table = uniphier_system_bus_match,
+               .pm = &uniphier_system_bus_pm_ops,
        },
 };
 module_platform_driver(uniphier_system_bus_driver);
index c391a49aaaffb22fe1b02693368a447bbdc39dfd..b4cf2f699a21024b727aabcb5a265fb0d613e817 100644 (file)
@@ -237,6 +237,18 @@ static int gemini_reset(struct reset_controller_dev *rcdev,
                            BIT(GEMINI_RESET_CPU1) | BIT(id));
 }
 
+static int gemini_reset_assert(struct reset_controller_dev *rcdev,
+                              unsigned long id)
+{
+       return 0;
+}
+
+static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+       return 0;
+}
+
 static int gemini_reset_status(struct reset_controller_dev *rcdev,
                             unsigned long id)
 {
@@ -253,6 +265,8 @@ static int gemini_reset_status(struct reset_controller_dev *rcdev,
 
 static const struct reset_control_ops gemini_reset_ops = {
        .reset = gemini_reset,
+       .assert = gemini_reset_assert,
+       .deassert = gemini_reset_deassert,
        .status = gemini_reset_status,
 };
 
index 43b0f2f08df2f7536d2f09e4f37984dde090e474..9cdf9d5050aca80858d3dc9dfcea416d91912b97 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/bsearch.h>
 
 #define SCI_CLK_SSC_ENABLE             BIT(0)
 #define SCI_CLK_ALLOW_FREQ_CHANGE      BIT(1)
@@ -44,6 +45,7 @@ struct sci_clk_data {
  * @dev: Device pointer for the clock provider
  * @clk_data: Clock data
  * @clocks: Clocks array for this device
+ * @num_clocks: Total number of clocks for this provider
  */
 struct sci_clk_provider {
        const struct ti_sci_handle *sci;
@@ -51,6 +53,7 @@ struct sci_clk_provider {
        struct device *dev;
        const struct sci_clk_data *clk_data;
        struct clk_hw **clocks;
+       int num_clocks;
 };
 
 /**
@@ -58,7 +61,6 @@ struct sci_clk_provider {
  * @hw:                 Hardware clock cookie for common clock framework
  * @dev_id:     Device index
  * @clk_id:     Clock index
- * @node:       Clocks list link
  * @provider:   Master clock provider
  * @flags:      Flags for the clock
  */
@@ -66,7 +68,6 @@ struct sci_clk {
        struct clk_hw hw;
        u16 dev_id;
        u8 clk_id;
-       struct list_head node;
        struct sci_clk_provider *provider;
        u8 flags;
 };
@@ -367,6 +368,19 @@ err:
        return &sci_clk->hw;
 }
 
+static int _cmp_sci_clk(const void *a, const void *b)
+{
+       const struct sci_clk *ca = a;
+       const struct sci_clk *cb = *(struct sci_clk **)b;
+
+       if (ca->dev_id == cb->dev_id && ca->clk_id == cb->clk_id)
+               return 0;
+       if (ca->dev_id > cb->dev_id ||
+           (ca->dev_id == cb->dev_id && ca->clk_id > cb->clk_id))
+               return 1;
+       return -1;
+}
+
 /**
  * sci_clk_get - Xlate function for getting clock handles
  * @clkspec: device tree clock specifier
@@ -380,29 +394,22 @@ err:
 static struct clk_hw *sci_clk_get(struct of_phandle_args *clkspec, void *data)
 {
        struct sci_clk_provider *provider = data;
-       u16 dev_id;
-       u8 clk_id;
-       const struct sci_clk_data *clks = provider->clk_data;
-       struct clk_hw **clocks = provider->clocks;
+       struct sci_clk **clk;
+       struct sci_clk key;
 
        if (clkspec->args_count != 2)
                return ERR_PTR(-EINVAL);
 
-       dev_id = clkspec->args[0];
-       clk_id = clkspec->args[1];
+       key.dev_id = clkspec->args[0];
+       key.clk_id = clkspec->args[1];
 
-       while (clks->num_clks) {
-               if (clks->dev == dev_id) {
-                       if (clk_id >= clks->num_clks)
-                               return ERR_PTR(-EINVAL);
-
-                       return clocks[clk_id];
-               }
+       clk = bsearch(&key, provider->clocks, provider->num_clocks,
+                     sizeof(clk), _cmp_sci_clk);
 
-               clks++;
-       }
+       if (!clk)
+               return ERR_PTR(-ENODEV);
 
-       return ERR_PTR(-ENODEV);
+       return &(*clk)->hw;
 }
 
 static int ti_sci_init_clocks(struct sci_clk_provider *p)
@@ -410,18 +417,29 @@ static int ti_sci_init_clocks(struct sci_clk_provider *p)
        const struct sci_clk_data *data = p->clk_data;
        struct clk_hw *hw;
        int i;
+       int num_clks = 0;
 
        while (data->num_clks) {
-               p->clocks = devm_kcalloc(p->dev, data->num_clks,
-                                        sizeof(struct sci_clk),
-                                        GFP_KERNEL);
-               if (!p->clocks)
-                       return -ENOMEM;
+               num_clks += data->num_clks;
+               data++;
+       }
 
+       p->num_clocks = num_clks;
+
+       p->clocks = devm_kcalloc(p->dev, num_clks, sizeof(struct sci_clk),
+                                GFP_KERNEL);
+       if (!p->clocks)
+               return -ENOMEM;
+
+       num_clks = 0;
+
+       data = p->clk_data;
+
+       while (data->num_clks) {
                for (i = 0; i < data->num_clks; i++) {
                        hw = _sci_clk_build(p, data->dev, i);
                        if (!IS_ERR(hw)) {
-                               p->clocks[i] = hw;
+                               p->clocks[num_clks++] = hw;
                                continue;
                        }
 
index 39eab69fe51a8a76791029ae718c575f16843630..44a5a535ca6334ebe17acf74ca38fea45ab86708 100644 (file)
@@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw,
        reg = PARM_SET(p->width, p->shift, reg, 1);
        writel(reg, mpll->base + p->reg_off);
 
+       p = &mpll->ssen;
+       if (p->width != 0) {
+               reg = readl(mpll->base + p->reg_off);
+               reg = PARM_SET(p->width, p->shift, reg, 1);
+               writel(reg, mpll->base + p->reg_off);
+       }
+
        p = &mpll->n2;
        reg = readl(mpll->base + p->reg_off);
        reg = PARM_SET(p->width, p->shift, reg, n2);
index d6feafe8bd6cea9ff9d61b0416f7c5d7858a044a..1629da9b414195c5159ee96449f5e5a22dec39c6 100644 (file)
@@ -118,6 +118,7 @@ struct meson_clk_mpll {
        struct parm sdm_en;
        struct parm n2;
        struct parm en;
+       struct parm ssen;
        spinlock_t *lock;
 };
 
index a897ea45327c985b189e9c5e81ac40028a682d7d..a7ea5f3da89d5357c2332f8a7fe4afa609cb9997 100644 (file)
@@ -528,6 +528,11 @@ static struct meson_clk_mpll gxbb_mpll0 = {
                .shift   = 14,
                .width   = 1,
        },
+       .ssen = {
+               .reg_off = HHI_MPLL_CNTL,
+               .shift   = 25,
+               .width   = 1,
+       },
        .lock = &clk_lock,
        .hw.init = &(struct clk_init_data){
                .name = "mpll0",
index bb3f1de876b1a8cd6bd5f191c6f2ff0737751aa7..6ec512ad259805c34b57be3ee96eddef149599ee 100644 (file)
@@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = {
                .shift   = 14,
                .width   = 1,
        },
+       .ssen = {
+               .reg_off = HHI_MPLL_CNTL,
+               .shift   = 25,
+               .width   = 1,
+       },
        .lock = &clk_lock,
        .hw.init = &(struct clk_init_data){
                .name = "mpll0",
index 0748a0b333c54c4a4a4b888ddd9e83a25d4323f7..9a6476aa7d818b3ad3ec84c9e68abccf21f04daf 100644 (file)
@@ -1283,16 +1283,16 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
        PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
        PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
-       PLL_36XX_RATE(393216000U, 197, 3, 2, 25690),
-       PLL_36XX_RATE(361267200U, 301, 5, 2, 3671),
+       PLL_36XX_RATE(393216003U, 197, 3, 2, -25690),
+       PLL_36XX_RATE(361267218U, 301, 5, 2, 3671),
        PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
-       PLL_36XX_RATE(196608000U, 197, 3, 3, -25690),
-       PLL_36XX_RATE(180633600U, 301, 5, 3, 3671),
-       PLL_36XX_RATE(131072000U, 131, 3, 3, 4719),
+       PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),
+       PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
+       PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
        PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
-       PLL_36XX_RATE(65536000U, 131, 3, 4, 4719),
-       PLL_36XX_RATE(49152000U, 197, 3, 5, 25690),
-       PLL_36XX_RATE(32768000U, 131, 3, 5, 4719),
+       PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
+       PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
+       PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
 };
 
 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
index 5372bf8be5e6fb8b0a43185279d33cc1cc30bd3b..31d7ffda9aab0c826627c14e3f51808d4639a6b4 100644 (file)
@@ -184,7 +184,7 @@ static struct ccu_mux cpu_clk = {
                .hw.init        = CLK_HW_INIT_PARENTS("cpu",
                                                      cpu_parents,
                                                      &ccu_mux_ops,
-                                                     CLK_IS_CRITICAL),
+                                                     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
        }
 };
 
index f99abc1106f0cb725ff7c63e9bc84b75596a4e75..08ef69945ffbf425efa001d48c6c9b5b0f4333eb 100644 (file)
@@ -186,6 +186,13 @@ static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
        pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
        spin_lock_init(&pclk->lock);
 
+       /*
+        * If the clock was already enabled by the firmware mark it as critical
+        * to avoid it being gated by the clock framework if no driver owns it.
+        */
+       if (plt_clk_is_enabled(&pclk->hw))
+               init.flags |= CLK_IS_CRITICAL;
+
        ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
        if (ret) {
                pclk = ERR_PTR(ret);
index 6cd50352563894bea24866d2d36d6b815d0abc20..0566455f233ed3cd663506321f08f7ae546862be 100644 (file)
@@ -1922,13 +1922,6 @@ static int intel_pstate_init_cpu(unsigned int cpunum)
        return 0;
 }
 
-static unsigned int intel_pstate_get(unsigned int cpu_num)
-{
-       struct cpudata *cpu = all_cpu_data[cpu_num];
-
-       return cpu ? get_avg_frequency(cpu) : 0;
-}
-
 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
 {
        struct cpudata *cpu = all_cpu_data[cpu_num];
@@ -2169,7 +2162,6 @@ static struct cpufreq_driver intel_pstate = {
        .setpolicy      = intel_pstate_set_policy,
        .suspend        = intel_pstate_hwp_save_state,
        .resume         = intel_pstate_resume,
-       .get            = intel_pstate_get,
        .init           = intel_pstate_cpu_init,
        .exit           = intel_pstate_cpu_exit,
        .stop_cpu       = intel_pstate_stop_cpu,
index 38f739fb727bd2da4c81ad198ae18e46bee8e040..6558a3ed57a7f6a1127f81aa0e1b5a861aa21b8d 100644 (file)
@@ -359,7 +359,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
        head = bo->mn_list.next;
 
        bo->mn = NULL;
-       list_del(&bo->mn_list);
+       list_del_init(&bo->mn_list);
 
        if (list_empty(head)) {
                struct amdgpu_mn_node *node;
index 18fd01f3e4b245d7d9f4cf24a97daa20beeaee66..003a131bad474db5d28584735c0e399b1def20d6 100644 (file)
@@ -1,24 +1,25 @@
-
 /*
-***************************************************************************************************
-*
-*  Trade secret of Advanced Micro Devices, Inc.
-*  Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished)
-*
-*  All rights reserved.  This notice is intended as a precaution against inadvertent publication and
-*  does not imply publication or any waiver of confidentiality.  The year included in the foregoing
-*  notice is the year of creation of the work.
-*
-***************************************************************************************************
-*/
-/**
-***************************************************************************************************
-* @brief gfx9 Clearstate Definitions
-***************************************************************************************************
-*
-*   Do not edit! This is a machine-generated file!
-*
-*/
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
 
 static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
 {
index f45fb0f022b3c6480b08afa545f4e3f4f9381610..4267fa417997aeaf6336297f25a05c31c7ae4eb8 100644 (file)
@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
                amdgpu_program_register_sequence(adev,
                                                 pitcairn_mgcg_cgcg_init,
                                                 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+               break;
        case CHIP_VERDE:
                amdgpu_program_register_sequence(adev,
                                                 verde_golden_registers,
@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
                amdgpu_program_register_sequence(adev,
                                                 oland_mgcg_cgcg_init,
                                                 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+               break;
        case CHIP_HAINAN:
                amdgpu_program_register_sequence(adev,
                                                 hainan_golden_registers,
index 688e77576e5a50b3f2f137eec72cd721d6bf96fa..354cbd6392cdf261ba657548ed2c208a09ddf50f 100644 (file)
@@ -4452,6 +4452,7 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
                /* Setting */
                irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
                irte->hi.fields.vector = vcpu_pi_info->vector;
+               irte->lo.fields_vapic.ga_log_intr = 1;
                irte->lo.fields_vapic.guest_mode = 1;
                irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
 
index 5cc597b383c7208d69e83d8ec0646e936817d1b4..372303700566f4f984e6656bd937e2d99bf07cc6 100644 (file)
@@ -2440,11 +2440,11 @@ static int __init state_next(void)
                break;
        case IOMMU_ACPI_FINISHED:
                early_enable_iommus();
-               register_syscore_ops(&amd_iommu_syscore_ops);
                x86_platform.iommu_shutdown = disable_iommus;
                init_state = IOMMU_ENABLED;
                break;
        case IOMMU_ENABLED:
+               register_syscore_ops(&amd_iommu_syscore_ops);
                ret = amd_iommu_init_pci();
                init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
                enable_iommus_v2();
index bc89b4d6c043dacee88463ba22edc8883f60385e..b97188acc4f1006185a5f8cb4fb3ee0e5cf735cf 100644 (file)
@@ -400,6 +400,8 @@ struct arm_smmu_device {
 
        u32                             cavium_id_base; /* Specific to Cavium */
 
+       spinlock_t                      global_sync_lock;
+
        /* IOMMU core code handle */
        struct iommu_device             iommu;
 };
@@ -436,7 +438,7 @@ struct arm_smmu_domain {
        struct arm_smmu_cfg             cfg;
        enum arm_smmu_domain_stage      stage;
        struct mutex                    init_mutex; /* Protects smmu pointer */
-       spinlock_t                      cb_lock; /* Serialises ATS1* ops */
+       spinlock_t                      cb_lock; /* Serialises ATS1* ops and TLB syncs */
        struct iommu_domain             domain;
 };
 
@@ -602,9 +604,12 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu,
 static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu)
 {
        void __iomem *base = ARM_SMMU_GR0(smmu);
+       unsigned long flags;
 
+       spin_lock_irqsave(&smmu->global_sync_lock, flags);
        __arm_smmu_tlb_sync(smmu, base + ARM_SMMU_GR0_sTLBGSYNC,
                            base + ARM_SMMU_GR0_sTLBGSTATUS);
+       spin_unlock_irqrestore(&smmu->global_sync_lock, flags);
 }
 
 static void arm_smmu_tlb_sync_context(void *cookie)
@@ -612,9 +617,12 @@ static void arm_smmu_tlb_sync_context(void *cookie)
        struct arm_smmu_domain *smmu_domain = cookie;
        struct arm_smmu_device *smmu = smmu_domain->smmu;
        void __iomem *base = ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx);
+       unsigned long flags;
 
+       spin_lock_irqsave(&smmu_domain->cb_lock, flags);
        __arm_smmu_tlb_sync(smmu, base + ARM_SMMU_CB_TLBSYNC,
                            base + ARM_SMMU_CB_TLBSTATUS);
+       spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
 }
 
 static void arm_smmu_tlb_sync_vmid(void *cookie)
@@ -1511,7 +1519,6 @@ static int arm_smmu_add_device(struct device *dev)
 
        if (using_legacy_binding) {
                ret = arm_smmu_register_legacy_master(dev, &smmu);
-               fwspec = dev->iommu_fwspec;
                if (ret)
                        goto out_free;
        } else if (fwspec && fwspec->ops == &arm_smmu_ops) {
@@ -1550,15 +1557,15 @@ static int arm_smmu_add_device(struct device *dev)
 
        ret = arm_smmu_master_alloc_smes(dev);
        if (ret)
-               goto out_free;
+               goto out_cfg_free;
 
        iommu_device_link(&smmu->iommu, dev);
 
        return 0;
 
+out_cfg_free:
+       kfree(cfg);
 out_free:
-       if (fwspec)
-               kfree(fwspec->iommu_priv);
        iommu_fwspec_free(dev);
        return ret;
 }
@@ -1925,6 +1932,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
 
        smmu->num_mapping_groups = size;
        mutex_init(&smmu->stream_map_mutex);
+       spin_lock_init(&smmu->global_sync_lock);
 
        if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) {
                smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L;
index af330f513653d2849682b2d4536dd86dcb6a43d7..d665d0dc16e8f787813a6106d15bd83afacc4f34 100644 (file)
@@ -479,6 +479,9 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
        if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
                return 0;
 
+       if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
+               return -ERANGE;
+
        ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
        /*
         * Synchronise all PTE updates for the new mapping before there's
@@ -659,6 +662,9 @@ static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
        struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
        size_t unmapped;
 
+       if (WARN_ON(upper_32_bits(iova)))
+               return 0;
+
        unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd);
        if (unmapped)
                io_pgtable_tlb_sync(&data->iop);
index b182039862c50debf8c55df4aad825cee468eed6..e8018a308868e33a4ea722c0b9686118078dc0db 100644 (file)
@@ -452,6 +452,10 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
        if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
                return 0;
 
+       if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
+                   paddr >= (1ULL << data->iop.cfg.oas)))
+               return -ERANGE;
+
        prot = arm_lpae_prot_to_pte(data, iommu_prot);
        ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
        /*
@@ -610,6 +614,9 @@ static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
        arm_lpae_iopte *ptep = data->pgd;
        int lvl = ARM_LPAE_START_LVL(data);
 
+       if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
+               return 0;
+
        unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep);
        if (unmapped)
                io_pgtable_tlb_sync(&data->iop);
index 524263a7ae6f54c290d9fc017633e0ac074054df..a3e667077b14e12ccca5df742922fe47d4e64005 100644 (file)
@@ -158,14 +158,12 @@ void free_io_pgtable_ops(struct io_pgtable_ops *ops);
  * @fmt:    The page table format.
  * @cookie: An opaque token provided by the IOMMU driver and passed back to
  *          any callback routines.
- * @tlb_sync_pending: Private flag for optimising out redundant syncs.
  * @cfg:    A copy of the page table configuration.
  * @ops:    The page table operations in use for this set of page tables.
  */
 struct io_pgtable {
        enum io_pgtable_fmt     fmt;
        void                    *cookie;
-       bool                    tlb_sync_pending;
        struct io_pgtable_cfg   cfg;
        struct io_pgtable_ops   ops;
 };
@@ -175,22 +173,17 @@ struct io_pgtable {
 static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop)
 {
        iop->cfg.tlb->tlb_flush_all(iop->cookie);
-       iop->tlb_sync_pending = true;
 }
 
 static inline void io_pgtable_tlb_add_flush(struct io_pgtable *iop,
                unsigned long iova, size_t size, size_t granule, bool leaf)
 {
        iop->cfg.tlb->tlb_add_flush(iova, size, granule, leaf, iop->cookie);
-       iop->tlb_sync_pending = true;
 }
 
 static inline void io_pgtable_tlb_sync(struct io_pgtable *iop)
 {
-       if (iop->tlb_sync_pending) {
-               iop->cfg.tlb->tlb_sync(iop->cookie);
-               iop->tlb_sync_pending = false;
-       }
+       iop->cfg.tlb->tlb_sync(iop->cookie);
 }
 
 /**
index 5d14cd15198db5cb6361d060abf208260c086ebe..91c6d367ab3593b99a6c9cfb9be01855e8372af2 100644 (file)
@@ -129,6 +129,7 @@ static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
        writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
        writel_relaxed(iova + size - 1, data->base + REG_MMU_INVLD_END_A);
        writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
+       data->tlb_flush_active = true;
 }
 
 static void mtk_iommu_tlb_sync(void *cookie)
@@ -137,6 +138,10 @@ static void mtk_iommu_tlb_sync(void *cookie)
        int ret;
        u32 tmp;
 
+       /* Avoid timing out if there's nothing to wait for */
+       if (!data->tlb_flush_active)
+               return;
+
        ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, tmp,
                                        tmp != 0, 10, 100000);
        if (ret) {
@@ -146,6 +151,7 @@ static void mtk_iommu_tlb_sync(void *cookie)
        }
        /* Clear the CPE status */
        writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
+       data->tlb_flush_active = false;
 }
 
 static const struct iommu_gather_ops mtk_iommu_gather_ops = {
index 2a28eadeea0ec3cf2ad363f7076f8555245520a2..c06cc91b5d9a1e63ec0984927b6c7722b5242f82 100644 (file)
@@ -47,6 +47,7 @@ struct mtk_iommu_data {
        struct iommu_group              *m4u_group;
        struct mtk_smi_iommu            smi_imu;      /* SMI larb iommu info */
        bool                            enable_4GB;
+       bool                            tlb_flush_active;
 
        struct iommu_device             iommu;
 };
index 89b09c51ab7cff64d20e24ff43fff8bd720d1ef3..38a5bb764c7b55cb8b742639e49756e413b4ab26 100644 (file)
@@ -1376,6 +1376,7 @@ isdn_ioctl(struct file *file, uint cmd, ulong arg)
                        if (arg) {
                                if (copy_from_user(bname, argp, sizeof(bname) - 1))
                                        return -EFAULT;
+                               bname[sizeof(bname)-1] = 0;
                        } else
                                return -EINVAL;
                        ret = mutex_lock_interruptible(&dev->mtx);
index c151c6daa67ee8aa2ae600b4462f146d85776335..f63a110b7bcb2d2257869484bd9b894d94b9b5d2 100644 (file)
@@ -2611,10 +2611,9 @@ isdn_net_newslave(char *parm)
        char newname[10];
 
        if (p) {
-               /* Slave-Name MUST not be empty */
-               if (!strlen(p + 1))
+               /* Slave-Name MUST not be empty or overflow 'newname' */
+               if (strscpy(newname, p + 1, sizeof(newname)) <= 0)
                        return NULL;
-               strcpy(newname, p + 1);
                *p = 0;
                /* Master must already exist */
                if (!(n = isdn_net_findif(parm)))
index ac91fd0d62c6e4e22c57ab354ceb56adfdaee48e..cbca5e51b9759c57813b8579a2d38318bab39e02 100644 (file)
@@ -92,7 +92,7 @@ static struct mbox_controller pcc_mbox_ctrl = {};
  */
 static struct mbox_chan *get_pcc_channel(int id)
 {
-       if (id < 0 || id > pcc_mbox_ctrl.num_chans)
+       if (id < 0 || id >= pcc_mbox_ctrl.num_chans)
                return ERR_PTR(-ENOENT);
 
        return &pcc_mbox_channels[id];
index 8ac59dc80f23e51b8449c884611396376000e5a4..e5938c791330c9be1203c2698bc511e4f98aaea4 100644 (file)
@@ -2170,6 +2170,7 @@ static void mmc_blk_remove_req(struct mmc_blk_data *md)
                 * from being accepted.
                 */
                card = md->queue.card;
+               queue_flag_set(QUEUE_FLAG_BYPASS, md->queue.queue);
                blk_set_queue_dying(md->queue.queue);
                mmc_cleanup_queue(&md->queue);
                if (md->disk->flags & GENHD_FL_UP) {
index 7611fd679f1ad83d7dee4052aebb6e9f6d3168cf..1485530c35921744a5fac79f53e2f35c05e1b51d 100644 (file)
@@ -31,6 +31,7 @@
 
 #define SDMMC_MC1R     0x204
 #define                SDMMC_MC1R_DDR          BIT(3)
+#define                SDMMC_MC1R_FCD          BIT(7)
 #define SDMMC_CACR     0x230
 #define                SDMMC_CACR_CAPWREN      BIT(0)
 #define                SDMMC_CACR_KEY          (0x46 << 8)
@@ -43,6 +44,15 @@ struct sdhci_at91_priv {
        struct clk *mainck;
 };
 
+static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
+{
+       u8 mc1r;
+
+       mc1r = readb(host->ioaddr + SDMMC_MC1R);
+       mc1r |= SDMMC_MC1R_FCD;
+       writeb(mc1r, host->ioaddr + SDMMC_MC1R);
+}
+
 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
 {
        u16 clk;
@@ -110,10 +120,18 @@ void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
        sdhci_set_uhs_signaling(host, timing);
 }
 
+static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
+{
+       sdhci_reset(host, mask);
+
+       if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
+               sdhci_at91_set_force_card_detect(host);
+}
+
 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
        .set_clock              = sdhci_at91_set_clock,
        .set_bus_width          = sdhci_set_bus_width,
-       .reset                  = sdhci_reset,
+       .reset                  = sdhci_at91_reset,
        .set_uhs_signaling      = sdhci_at91_set_uhs_signaling,
        .set_power              = sdhci_at91_set_power,
 };
@@ -324,6 +342,21 @@ static int sdhci_at91_probe(struct platform_device *pdev)
                host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
        }
 
+       /*
+        * If the device attached to the MMC bus is not removable, it is safer
+        * to set the Force Card Detect bit. People often don't connect the
+        * card detect signal and use this pin for another purpose. If the card
+        * detect pin is not muxed to SDHCI controller, a default value is
+        * used. This value can be different from a SoC revision to another
+        * one. Problems come when this default value is not card present. To
+        * avoid this case, if the device is non removable then the card
+        * detection procedure using the SDMCC_CD signal is bypassed.
+        * This bit is reset when a software reset for all command is performed
+        * so we need to implement our own reset function to set back this bit.
+        */
+       if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
+               sdhci_at91_set_force_card_detect(host);
+
        pm_runtime_put_autosuspend(&pdev->dev);
 
        return 0;
index 181839d6fbea44a8b6962f94703e4293645cc21c..9bee6c1c70cca33941ae8db8002d69e760693bac 100644 (file)
@@ -2050,6 +2050,7 @@ static int bond_miimon_inspect(struct bonding *bond)
                                continue;
 
                        bond_propose_link_state(slave, BOND_LINK_FAIL);
+                       commit++;
                        slave->delay = bond->params.downdelay;
                        if (slave->delay) {
                                netdev_info(bond->dev, "link status down for %sinterface %s, disabling it in %d ms\n",
@@ -2088,6 +2089,7 @@ static int bond_miimon_inspect(struct bonding *bond)
                                continue;
 
                        bond_propose_link_state(slave, BOND_LINK_BACK);
+                       commit++;
                        slave->delay = bond->params.updelay;
 
                        if (slave->delay) {
index 041cfb7952f81d71278279454a394c9754e0fb97..e94159507847b33962f99d63561301b924fd2dd1 100644 (file)
@@ -609,7 +609,7 @@ static void nb8800_mac_config(struct net_device *dev)
                mac_mode |= HALF_DUPLEX;
 
        if (gigabit) {
-               if (priv->phy_mode == PHY_INTERFACE_MODE_RGMII)
+               if (phy_interface_is_rgmii(dev->phydev))
                        mac_mode |= RGMII_MODE;
 
                mac_mode |= GMAC_MODE;
@@ -1268,11 +1268,10 @@ static int nb8800_tangox_init(struct net_device *dev)
                break;
 
        case PHY_INTERFACE_MODE_RGMII:
-               pad_mode = PAD_MODE_RGMII;
-               break;
-
+       case PHY_INTERFACE_MODE_RGMII_ID:
+       case PHY_INTERFACE_MODE_RGMII_RXID:
        case PHY_INTERFACE_MODE_RGMII_TXID:
-               pad_mode = PAD_MODE_RGMII | PAD_MODE_GTX_CLK_DELAY;
+               pad_mode = PAD_MODE_RGMII;
                break;
 
        default:
index 7b0b399aaedd44778b96a38fe0fc5c7659494da5..a981c4ee9d72deab705231088043e8690853d563 100644 (file)
@@ -3669,7 +3669,7 @@ static int bcmgenet_resume(struct device *d)
 
        phy_init_hw(priv->phydev);
        /* Speed settings must be restored */
-       bcmgenet_mii_config(priv->dev);
+       bcmgenet_mii_config(priv->dev, false);
 
        /* disable ethernet MAC while updating its registers */
        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
index b9344de669f84d2d1fa8e983c704b97ba09c7195..3a34fdba5301185e9939dc2feff52bef4f3ea68f 100644 (file)
@@ -698,7 +698,7 @@ GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
 
 /* MDIO routines */
 int bcmgenet_mii_init(struct net_device *dev);
-int bcmgenet_mii_config(struct net_device *dev);
+int bcmgenet_mii_config(struct net_device *dev, bool init);
 int bcmgenet_mii_probe(struct net_device *dev);
 void bcmgenet_mii_exit(struct net_device *dev);
 void bcmgenet_mii_reset(struct net_device *dev);
index 071fcbd14e6a4e17534950107d5081662eba5c3c..30cb97b4a1d7a27f4be917e4d718f86d596734a5 100644 (file)
@@ -238,7 +238,7 @@ static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
                                          bcmgenet_fixed_phy_link_update);
 }
 
-int bcmgenet_mii_config(struct net_device *dev)
+int bcmgenet_mii_config(struct net_device *dev, bool init)
 {
        struct bcmgenet_priv *priv = netdev_priv(dev);
        struct phy_device *phydev = priv->phydev;
@@ -327,7 +327,8 @@ int bcmgenet_mii_config(struct net_device *dev)
                bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
        }
 
-       dev_info_once(kdev, "configuring instance for %s\n", phy_name);
+       if (init)
+               dev_info(kdev, "configuring instance for %s\n", phy_name);
 
        return 0;
 }
@@ -375,7 +376,7 @@ int bcmgenet_mii_probe(struct net_device *dev)
         * PHY speed which is needed for bcmgenet_mii_config() to configure
         * things appropriately.
         */
-       ret = bcmgenet_mii_config(dev);
+       ret = bcmgenet_mii_config(dev, true);
        if (ret) {
                phy_disconnect(priv->phydev);
                return ret;
index 79112563a25ae08db35bfb2de214c2b3e84a15a6..5e5c4d7796b8882168eba6fe858ac4bfff2aaf53 100644 (file)
@@ -292,11 +292,30 @@ static void bgx_sgmii_change_link_state(struct lmac *lmac)
        u64 cmr_cfg;
        u64 port_cfg = 0;
        u64 misc_ctl = 0;
+       bool tx_en, rx_en;
 
        cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
-       cmr_cfg &= ~CMR_EN;
+       tx_en = cmr_cfg & CMR_PKT_TX_EN;
+       rx_en = cmr_cfg & CMR_PKT_RX_EN;
+       cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
        bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
 
+       /* Wait for BGX RX to be idle */
+       if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
+                        GMI_PORT_CFG_RX_IDLE, false)) {
+               dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
+                       bgx->bgx_id, lmac->lmacid);
+               return;
+       }
+
+       /* Wait for BGX TX to be idle */
+       if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
+                        GMI_PORT_CFG_TX_IDLE, false)) {
+               dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
+                       bgx->bgx_id, lmac->lmacid);
+               return;
+       }
+
        port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
        misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
 
@@ -347,10 +366,8 @@ static void bgx_sgmii_change_link_state(struct lmac *lmac)
        bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
        bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
 
-       port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
-
-       /* Re-enable lmac */
-       cmr_cfg |= CMR_EN;
+       /* Restore CMR config settings */
+       cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
        bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
 
        if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
index 6b7fe6fdd13b9b27b4a1573e8c7b3869b17bcc19..23acdc5ab896306f3f1e6d2fbc7d8afb58273888 100644 (file)
 #define  GMI_PORT_CFG_DUPLEX                   BIT_ULL(2)
 #define  GMI_PORT_CFG_SLOT_TIME                        BIT_ULL(3)
 #define  GMI_PORT_CFG_SPEED_MSB                        BIT_ULL(8)
+#define  GMI_PORT_CFG_RX_IDLE                  BIT_ULL(12)
+#define  GMI_PORT_CFG_TX_IDLE                  BIT_ULL(13)
 #define BGX_GMP_GMI_RXX_JABBER         0x38038
 #define BGX_GMP_GMI_TXX_THRESH         0x38210
 #define BGX_GMP_GMI_TXX_APPEND         0x38218
index 95bf5e89cfd17b30d3543b33cb069f8aaee69d31..34dae51effd45a19c9a2b8b607dafeaec3aa0456 100644 (file)
@@ -125,7 +125,7 @@ static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
        iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
        iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
                  priv->base + FTGMAC100_OFFSET_MACCR);
-       for (i = 0; i < 50; i++) {
+       for (i = 0; i < 200; i++) {
                unsigned int maccr;
 
                maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
@@ -392,7 +392,7 @@ static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
        struct net_device *netdev = priv->netdev;
        struct sk_buff *skb;
        dma_addr_t map;
-       int err;
+       int err = 0;
 
        skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
        if (unlikely(!skb)) {
@@ -428,7 +428,7 @@ static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
        else
                rxdes->rxdes0 = 0;
 
-       return 0;
+       return err;
 }
 
 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
@@ -1682,6 +1682,7 @@ static int ftgmac100_setup_mdio(struct net_device *netdev)
        priv->mii_bus->name = "ftgmac100_mdio";
        snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
                 pdev->name, pdev->id);
+       priv->mii_bus->parent = priv->dev;
        priv->mii_bus->priv = priv->netdev;
        priv->mii_bus->read = ftgmac100_mdiobus_read;
        priv->mii_bus->write = ftgmac100_mdiobus_write;
index 5794d98d946f35c132f010b58368a15b5534070d..9c94ea9b2b802306c0286472c2255571e8e3ed36 100644 (file)
@@ -2734,7 +2734,7 @@ static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
        ppd.shared = pdev;
 
        memset(&res, 0, sizeof(res));
-       if (!of_irq_to_resource(pnp, 0, &res)) {
+       if (of_irq_to_resource(pnp, 0, &res) <= 0) {
                dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
                return -EINVAL;
        }
index b3d0c2e6347a636aa23a6f637233d27d7b55f646..e588a0cdb074040fe83ba8caaec9cd30c4189689 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/if_vlan.h>
 #include <linux/reset.h>
 #include <linux/tcp.h>
+#include <linux/interrupt.h>
 
 #include "mtk_eth_soc.h"
 
@@ -947,6 +948,10 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
                      RX_DMA_FPORT_MASK;
                mac--;
 
+               if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
+                            !eth->netdev[mac]))
+                       goto release_desc;
+
                netdev = eth->netdev[mac];
 
                if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
index f5a2c605749ff2dad1db091bb93d3b6957fa4058..31cbe5e86a01300bacd92db829d9ddc186e5db7a 100644 (file)
@@ -786,6 +786,10 @@ static void cb_timeout_handler(struct work_struct *work)
        mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 }
 
+static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
+static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
+                             struct mlx5_cmd_msg *msg);
+
 static void cmd_work_handler(struct work_struct *work)
 {
        struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
@@ -796,17 +800,28 @@ static void cmd_work_handler(struct work_struct *work)
        struct semaphore *sem;
        unsigned long flags;
        bool poll_cmd = ent->polling;
+       int alloc_ret;
 
 
        sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
        down(sem);
        if (!ent->page_queue) {
-               ent->idx = alloc_ent(cmd);
-               if (ent->idx < 0) {
+               alloc_ret = alloc_ent(cmd);
+               if (alloc_ret < 0) {
                        mlx5_core_err(dev, "failed to allocate command entry\n");
+                       if (ent->callback) {
+                               ent->callback(-EAGAIN, ent->context);
+                               mlx5_free_cmd_msg(dev, ent->out);
+                               free_msg(dev, ent->in);
+                               free_cmd(ent);
+                       } else {
+                               ent->ret = -EAGAIN;
+                               complete(&ent->done);
+                       }
                        up(sem);
                        return;
                }
+               ent->idx = alloc_ret;
        } else {
                ent->idx = cmd->max_reg_cmds;
                spin_lock_irqsave(&cmd->alloc_lock, flags);
@@ -967,7 +982,7 @@ static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 
        err = wait_func(dev, ent);
        if (err == -ETIMEDOUT)
-               goto out_free;
+               goto out;
 
        ds = ent->ts2 - ent->ts1;
        op = MLX5_GET(mbox_in, in->first.data, opcode);
@@ -1430,6 +1445,7 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
                                        mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
                                                      ent->idx);
                                        free_ent(cmd, ent->idx);
+                                       free_cmd(ent);
                                }
                                continue;
                        }
@@ -1488,7 +1504,8 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
                                free_msg(dev, ent->in);
 
                                err = err ? err : ent->status;
-                               free_cmd(ent);
+                               if (!forced)
+                                       free_cmd(ent);
                                callback(err, context);
                        } else {
                                complete(&ent->done);
index e1b7ddfecd011436c1520edc93eb30e8e15221d4..0039b4725405fcf0a961fa53eab250adc2d51f3c 100644 (file)
@@ -266,6 +266,14 @@ struct mlx5e_dcbx {
 };
 #endif
 
+#define MAX_PIN_NUM    8
+struct mlx5e_pps {
+       u8                         pin_caps[MAX_PIN_NUM];
+       struct work_struct         out_work;
+       u64                        start[MAX_PIN_NUM];
+       u8                         enabled;
+};
+
 struct mlx5e_tstamp {
        rwlock_t                   lock;
        struct cyclecounter        cycles;
@@ -277,7 +285,7 @@ struct mlx5e_tstamp {
        struct mlx5_core_dev      *mdev;
        struct ptp_clock          *ptp;
        struct ptp_clock_info      ptp_info;
-       u8                        *pps_pin_caps;
+       struct mlx5e_pps           pps_info;
 };
 
 enum {
index 66f432385dbbd5ea6ce3ceb256abb7ce6dada7b0..84dd63e740414e75d5aa5ac1ebf871c801718bda 100644 (file)
@@ -53,6 +53,15 @@ enum {
        MLX5E_EVENT_MODE_ONCE_TILL_ARM  = 0x2,
 };
 
+enum {
+       MLX5E_MTPPS_FS_ENABLE                   = BIT(0x0),
+       MLX5E_MTPPS_FS_PATTERN                  = BIT(0x2),
+       MLX5E_MTPPS_FS_PIN_MODE                 = BIT(0x3),
+       MLX5E_MTPPS_FS_TIME_STAMP               = BIT(0x4),
+       MLX5E_MTPPS_FS_OUT_PULSE_DURATION       = BIT(0x5),
+       MLX5E_MTPPS_FS_ENH_OUT_PER_ADJ          = BIT(0x7),
+};
+
 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *tstamp, u64 timestamp,
                        struct skb_shared_hwtstamps *hwts)
 {
@@ -73,17 +82,46 @@ static u64 mlx5e_read_internal_timer(const struct cyclecounter *cc)
        return mlx5_read_internal_timer(tstamp->mdev) & cc->mask;
 }
 
+static void mlx5e_pps_out(struct work_struct *work)
+{
+       struct mlx5e_pps *pps_info = container_of(work, struct mlx5e_pps,
+                                                 out_work);
+       struct mlx5e_tstamp *tstamp = container_of(pps_info, struct mlx5e_tstamp,
+                                                  pps_info);
+       u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
+       unsigned long flags;
+       int i;
+
+       for (i = 0; i < tstamp->ptp_info.n_pins; i++) {
+               u64 tstart;
+
+               write_lock_irqsave(&tstamp->lock, flags);
+               tstart = tstamp->pps_info.start[i];
+               tstamp->pps_info.start[i] = 0;
+               write_unlock_irqrestore(&tstamp->lock, flags);
+               if (!tstart)
+                       continue;
+
+               MLX5_SET(mtpps_reg, in, pin, i);
+               MLX5_SET64(mtpps_reg, in, time_stamp, tstart);
+               MLX5_SET(mtpps_reg, in, field_select, MLX5E_MTPPS_FS_TIME_STAMP);
+               mlx5_set_mtpps(tstamp->mdev, in, sizeof(in));
+       }
+}
+
 static void mlx5e_timestamp_overflow(struct work_struct *work)
 {
        struct delayed_work *dwork = to_delayed_work(work);
        struct mlx5e_tstamp *tstamp = container_of(dwork, struct mlx5e_tstamp,
                                                   overflow_work);
+       struct mlx5e_priv *priv = container_of(tstamp, struct mlx5e_priv, tstamp);
        unsigned long flags;
 
        write_lock_irqsave(&tstamp->lock, flags);
        timecounter_read(&tstamp->clock);
        write_unlock_irqrestore(&tstamp->lock, flags);
-       schedule_delayed_work(&tstamp->overflow_work, tstamp->overflow_period);
+       queue_delayed_work(priv->wq, &tstamp->overflow_work,
+                          msecs_to_jiffies(tstamp->overflow_period * 1000));
 }
 
 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
@@ -213,18 +251,6 @@ static int mlx5e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
        int neg_adj = 0;
        struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
                                                  ptp_info);
-       struct mlx5e_priv *priv =
-               container_of(tstamp, struct mlx5e_priv, tstamp);
-
-       if (MLX5_CAP_GEN(priv->mdev, pps_modify)) {
-               u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
-
-               /* For future use need to add a loop for finding all 1PPS out pins */
-               MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_OUT);
-               MLX5_SET(mtpps_reg, in, out_periodic_adjustment, delta & 0xFFFF);
-
-               mlx5_set_mtpps(priv->mdev, in, sizeof(in));
-       }
 
        if (delta < 0) {
                neg_adj = 1;
@@ -253,12 +279,13 @@ static int mlx5e_extts_configure(struct ptp_clock_info *ptp,
        struct mlx5e_priv *priv =
                container_of(tstamp, struct mlx5e_priv, tstamp);
        u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
+       u32 field_select = 0;
+       u8 pin_mode = 0;
        u8 pattern = 0;
        int pin = -1;
        int err = 0;
 
-       if (!MLX5_CAP_GEN(priv->mdev, pps) ||
-           !MLX5_CAP_GEN(priv->mdev, pps_modify))
+       if (!MLX5_PPS_CAP(priv->mdev))
                return -EOPNOTSUPP;
 
        if (rq->extts.index >= tstamp->ptp_info.n_pins)
@@ -268,15 +295,21 @@ static int mlx5e_extts_configure(struct ptp_clock_info *ptp,
                pin = ptp_find_pin(tstamp->ptp, PTP_PF_EXTTS, rq->extts.index);
                if (pin < 0)
                        return -EBUSY;
+               pin_mode = MLX5E_PIN_MODE_IN;
+               pattern = !!(rq->extts.flags & PTP_FALLING_EDGE);
+               field_select = MLX5E_MTPPS_FS_PIN_MODE |
+                              MLX5E_MTPPS_FS_PATTERN |
+                              MLX5E_MTPPS_FS_ENABLE;
+       } else {
+               pin = rq->extts.index;
+               field_select = MLX5E_MTPPS_FS_ENABLE;
        }
 
-       if (rq->extts.flags & PTP_FALLING_EDGE)
-               pattern = 1;
-
        MLX5_SET(mtpps_reg, in, pin, pin);
-       MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_IN);
+       MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
        MLX5_SET(mtpps_reg, in, pattern, pattern);
        MLX5_SET(mtpps_reg, in, enable, on);
+       MLX5_SET(mtpps_reg, in, field_select, field_select);
 
        err = mlx5_set_mtpps(priv->mdev, in, sizeof(in));
        if (err)
@@ -295,14 +328,18 @@ static int mlx5e_perout_configure(struct ptp_clock_info *ptp,
        struct mlx5e_priv *priv =
                container_of(tstamp, struct mlx5e_priv, tstamp);
        u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
-       u64 nsec_now, nsec_delta, time_stamp;
+       u64 nsec_now, nsec_delta, time_stamp = 0;
        u64 cycles_now, cycles_delta;
        struct timespec64 ts;
        unsigned long flags;
+       u32 field_select = 0;
+       u8 pin_mode = 0;
+       u8 pattern = 0;
        int pin = -1;
+       int err = 0;
        s64 ns;
 
-       if (!MLX5_CAP_GEN(priv->mdev, pps_modify))
+       if (!MLX5_PPS_CAP(priv->mdev))
                return -EOPNOTSUPP;
 
        if (rq->perout.index >= tstamp->ptp_info.n_pins)
@@ -313,32 +350,60 @@ static int mlx5e_perout_configure(struct ptp_clock_info *ptp,
                                   rq->perout.index);
                if (pin < 0)
                        return -EBUSY;
-       }
 
-       ts.tv_sec = rq->perout.period.sec;
-       ts.tv_nsec = rq->perout.period.nsec;
-       ns = timespec64_to_ns(&ts);
-       if (on)
+               pin_mode = MLX5E_PIN_MODE_OUT;
+               pattern = MLX5E_OUT_PATTERN_PERIODIC;
+               ts.tv_sec = rq->perout.period.sec;
+               ts.tv_nsec = rq->perout.period.nsec;
+               ns = timespec64_to_ns(&ts);
+
                if ((ns >> 1) != 500000000LL)
                        return -EINVAL;
-       ts.tv_sec = rq->perout.start.sec;
-       ts.tv_nsec = rq->perout.start.nsec;
-       ns = timespec64_to_ns(&ts);
-       cycles_now = mlx5_read_internal_timer(tstamp->mdev);
-       write_lock_irqsave(&tstamp->lock, flags);
-       nsec_now = timecounter_cyc2time(&tstamp->clock, cycles_now);
-       nsec_delta = ns - nsec_now;
-       cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift,
-                                tstamp->cycles.mult);
-       write_unlock_irqrestore(&tstamp->lock, flags);
-       time_stamp = cycles_now + cycles_delta;
+
+               ts.tv_sec = rq->perout.start.sec;
+               ts.tv_nsec = rq->perout.start.nsec;
+               ns = timespec64_to_ns(&ts);
+               cycles_now = mlx5_read_internal_timer(tstamp->mdev);
+               write_lock_irqsave(&tstamp->lock, flags);
+               nsec_now = timecounter_cyc2time(&tstamp->clock, cycles_now);
+               nsec_delta = ns - nsec_now;
+               cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift,
+                                        tstamp->cycles.mult);
+               write_unlock_irqrestore(&tstamp->lock, flags);
+               time_stamp = cycles_now + cycles_delta;
+               field_select = MLX5E_MTPPS_FS_PIN_MODE |
+                              MLX5E_MTPPS_FS_PATTERN |
+                              MLX5E_MTPPS_FS_ENABLE |
+                              MLX5E_MTPPS_FS_TIME_STAMP;
+       } else {
+               pin = rq->perout.index;
+               field_select = MLX5E_MTPPS_FS_ENABLE;
+       }
+
        MLX5_SET(mtpps_reg, in, pin, pin);
-       MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_OUT);
-       MLX5_SET(mtpps_reg, in, pattern, MLX5E_OUT_PATTERN_PERIODIC);
+       MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
+       MLX5_SET(mtpps_reg, in, pattern, pattern);
        MLX5_SET(mtpps_reg, in, enable, on);
        MLX5_SET64(mtpps_reg, in, time_stamp, time_stamp);
+       MLX5_SET(mtpps_reg, in, field_select, field_select);
+
+       err = mlx5_set_mtpps(priv->mdev, in, sizeof(in));
+       if (err)
+               return err;
 
-       return mlx5_set_mtpps(priv->mdev, in, sizeof(in));
+       return mlx5_set_mtppse(priv->mdev, pin, 0,
+                              MLX5E_EVENT_MODE_REPETETIVE & on);
+}
+
+static int mlx5e_pps_configure(struct ptp_clock_info *ptp,
+                              struct ptp_clock_request *rq,
+                              int on)
+{
+       struct mlx5e_tstamp *tstamp =
+               container_of(ptp, struct mlx5e_tstamp, ptp_info);
+
+       tstamp->pps_info.enabled = !!on;
+       return 0;
 }
 
 static int mlx5e_ptp_enable(struct ptp_clock_info *ptp,
@@ -350,6 +415,8 @@ static int mlx5e_ptp_enable(struct ptp_clock_info *ptp,
                return mlx5e_extts_configure(ptp, rq, on);
        case PTP_CLK_REQ_PEROUT:
                return mlx5e_perout_configure(ptp, rq, on);
+       case PTP_CLK_REQ_PPS:
+               return mlx5e_pps_configure(ptp, rq, on);
        default:
                return -EOPNOTSUPP;
        }
@@ -395,6 +462,7 @@ static int mlx5e_init_pin_config(struct mlx5e_tstamp *tstamp)
                return -ENOMEM;
        tstamp->ptp_info.enable = mlx5e_ptp_enable;
        tstamp->ptp_info.verify = mlx5e_ptp_verify;
+       tstamp->ptp_info.pps = 1;
 
        for (i = 0; i < tstamp->ptp_info.n_pins; i++) {
                snprintf(tstamp->ptp_info.pin_config[i].name,
@@ -422,22 +490,56 @@ static void mlx5e_get_pps_caps(struct mlx5e_priv *priv,
        tstamp->ptp_info.n_per_out = MLX5_GET(mtpps_reg, out,
                                              cap_max_num_of_pps_out_pins);
 
-       tstamp->pps_pin_caps[0] = MLX5_GET(mtpps_reg, out, cap_pin_0_mode);
-       tstamp->pps_pin_caps[1] = MLX5_GET(mtpps_reg, out, cap_pin_1_mode);
-       tstamp->pps_pin_caps[2] = MLX5_GET(mtpps_reg, out, cap_pin_2_mode);
-       tstamp->pps_pin_caps[3] = MLX5_GET(mtpps_reg, out, cap_pin_3_mode);
-       tstamp->pps_pin_caps[4] = MLX5_GET(mtpps_reg, out, cap_pin_4_mode);
-       tstamp->pps_pin_caps[5] = MLX5_GET(mtpps_reg, out, cap_pin_5_mode);
-       tstamp->pps_pin_caps[6] = MLX5_GET(mtpps_reg, out, cap_pin_6_mode);
-       tstamp->pps_pin_caps[7] = MLX5_GET(mtpps_reg, out, cap_pin_7_mode);
+       tstamp->pps_info.pin_caps[0] = MLX5_GET(mtpps_reg, out, cap_pin_0_mode);
+       tstamp->pps_info.pin_caps[1] = MLX5_GET(mtpps_reg, out, cap_pin_1_mode);
+       tstamp->pps_info.pin_caps[2] = MLX5_GET(mtpps_reg, out, cap_pin_2_mode);
+       tstamp->pps_info.pin_caps[3] = MLX5_GET(mtpps_reg, out, cap_pin_3_mode);
+       tstamp->pps_info.pin_caps[4] = MLX5_GET(mtpps_reg, out, cap_pin_4_mode);
+       tstamp->pps_info.pin_caps[5] = MLX5_GET(mtpps_reg, out, cap_pin_5_mode);
+       tstamp->pps_info.pin_caps[6] = MLX5_GET(mtpps_reg, out, cap_pin_6_mode);
+       tstamp->pps_info.pin_caps[7] = MLX5_GET(mtpps_reg, out, cap_pin_7_mode);
 }
 
 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
                             struct ptp_clock_event *event)
 {
+       struct net_device *netdev = priv->netdev;
        struct mlx5e_tstamp *tstamp = &priv->tstamp;
+       struct timespec64 ts;
+       u64 nsec_now, nsec_delta;
+       u64 cycles_now, cycles_delta;
+       int pin = event->index;
+       s64 ns;
+       unsigned long flags;
 
-       ptp_clock_event(tstamp->ptp, event);
+       switch (tstamp->ptp_info.pin_config[pin].func) {
+       case PTP_PF_EXTTS:
+               if (tstamp->pps_info.enabled) {
+                       event->type = PTP_CLOCK_PPSUSR;
+                       event->pps_times.ts_real = ns_to_timespec64(event->timestamp);
+               } else {
+                       event->type = PTP_CLOCK_EXTTS;
+               }
+               ptp_clock_event(tstamp->ptp, event);
+               break;
+       case PTP_PF_PEROUT:
+               mlx5e_ptp_gettime(&tstamp->ptp_info, &ts);
+               cycles_now = mlx5_read_internal_timer(tstamp->mdev);
+               ts.tv_sec += 1;
+               ts.tv_nsec = 0;
+               ns = timespec64_to_ns(&ts);
+               write_lock_irqsave(&tstamp->lock, flags);
+               nsec_now = timecounter_cyc2time(&tstamp->clock, cycles_now);
+               nsec_delta = ns - nsec_now;
+               cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift,
+                                        tstamp->cycles.mult);
+               tstamp->pps_info.start[pin] = cycles_now + cycles_delta;
+               queue_work(priv->wq, &tstamp->pps_info.out_work);
+               write_unlock_irqrestore(&tstamp->lock, flags);
+               break;
+       default:
+               netdev_err(netdev, "%s: Unhandled event\n", __func__);
+       }
 }
 
 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
@@ -473,9 +575,10 @@ void mlx5e_timestamp_init(struct mlx5e_priv *priv)
        do_div(ns, NSEC_PER_SEC / 2 / HZ);
        tstamp->overflow_period = ns;
 
+       INIT_WORK(&tstamp->pps_info.out_work, mlx5e_pps_out);
        INIT_DELAYED_WORK(&tstamp->overflow_work, mlx5e_timestamp_overflow);
        if (tstamp->overflow_period)
-               schedule_delayed_work(&tstamp->overflow_work, 0);
+               queue_delayed_work(priv->wq, &tstamp->overflow_work, 0);
        else
                mlx5_core_warn(priv->mdev, "invalid overflow period, overflow_work is not scheduled\n");
 
@@ -484,16 +587,10 @@ void mlx5e_timestamp_init(struct mlx5e_priv *priv)
        snprintf(tstamp->ptp_info.name, 16, "mlx5 ptp");
 
        /* Initialize 1PPS data structures */
-#define MAX_PIN_NUM    8
-       tstamp->pps_pin_caps = kzalloc(sizeof(u8) * MAX_PIN_NUM, GFP_KERNEL);
-       if (tstamp->pps_pin_caps) {
-               if (MLX5_CAP_GEN(priv->mdev, pps))
-                       mlx5e_get_pps_caps(priv, tstamp);
-               if (tstamp->ptp_info.n_pins)
-                       mlx5e_init_pin_config(tstamp);
-       } else {
-               mlx5_core_warn(priv->mdev, "1PPS initialization failed\n");
-       }
+       if (MLX5_PPS_CAP(priv->mdev))
+               mlx5e_get_pps_caps(priv, tstamp);
+       if (tstamp->ptp_info.n_pins)
+               mlx5e_init_pin_config(tstamp);
 
        tstamp->ptp = ptp_clock_register(&tstamp->ptp_info,
                                         &priv->mdev->pdev->dev);
@@ -516,8 +613,7 @@ void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv)
                priv->tstamp.ptp = NULL;
        }
 
-       kfree(tstamp->pps_pin_caps);
-       kfree(tstamp->ptp_info.pin_config);
-
+       cancel_work_sync(&tstamp->pps_info.out_work);
        cancel_delayed_work_sync(&tstamp->overflow_work);
+       kfree(tstamp->ptp_info.pin_config);
 }
index bdd82c9b399262428247471798e7fd4dbf03ca92..eafc59280adae527374e321b3cfcd8549ac140d8 100644 (file)
@@ -276,7 +276,7 @@ static void add_rule_to_list(struct mlx5e_priv *priv,
 
 static bool outer_header_zero(u32 *match_criteria)
 {
-       int size = MLX5_ST_SZ_BYTES(fte_match_param);
+       int size = MLX5_FLD_SZ_BYTES(fte_match_param, outer_headers);
        char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
                                             outer_headers);
 
@@ -320,7 +320,7 @@ add_ethtool_flow_rule(struct mlx5e_priv *priv,
 
        spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria));
        flow_act.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
-       rule = mlx5_add_flow_rules(ft, spec, &flow_act, dst, 1);
+       rule = mlx5_add_flow_rules(ft, spec, &flow_act, dst, dst ? 1 : 0);
        if (IS_ERR(rule)) {
                err = PTR_ERR(rule);
                netdev_err(priv->netdev, "%s: failed to add ethtool steering rule: %d\n",
index 1eac5003084fb9d131392ab7e87ec82d7c4d20b7..57f31fa478ceee5b83a3b4041cfef12457acbd03 100644 (file)
@@ -377,7 +377,6 @@ static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
                break;
        case MLX5_DEV_EVENT_PPS:
                eqe = (struct mlx5_eqe *)param;
-               ptp_event.type = PTP_CLOCK_EXTTS;
                ptp_event.index = eqe->data.pps.pin;
                ptp_event.timestamp =
                        timecounter_cyc2time(&priv->tstamp.clock,
index af51a5d2b912721222fa2434e7919231ccaacdcb..52b9a64cd3a20be3eb8a8e5beb1990d583d2db93 100644 (file)
@@ -698,7 +698,7 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
        else
                mlx5_core_dbg(dev, "port_module_event is not set\n");
 
-       if (MLX5_CAP_GEN(dev, pps))
+       if (MLX5_PPS_CAP(dev))
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
 
        if (MLX5_CAP_GEN(dev, fpga))
index 89bfda419efe96efc1778ec832ff0eac56588cc5..8b18cc9ec026f99d68d23626bde3d695fa1aa895 100644 (file)
@@ -1668,7 +1668,8 @@ void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
        int i;
 
        if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
-           MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
+           MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH ||
+           esw->mode == SRIOV_NONE)
                return;
 
        esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
index 1ee5bce8590118a2075bfd4ce2cc52d0da8c1f27..85298051a3e4fcf74767196dcc6660114222b4cf 100644 (file)
@@ -178,8 +178,6 @@ out:
 
 static void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp)
 {
-       mlx5_fs_remove_rx_underlay_qpn(mdev, qp->qpn);
-
        mlx5_core_destroy_qp(mdev, qp);
 }
 
@@ -194,8 +192,6 @@ static int mlx5i_init_tx(struct mlx5e_priv *priv)
                return err;
        }
 
-       mlx5_fs_add_rx_underlay_qpn(priv->mdev, ipriv->qp.qpn);
-
        err = mlx5e_create_tis(priv->mdev, 0 /* tc */, ipriv->qp.qpn, &priv->tisn[0]);
        if (err) {
                mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err);
@@ -253,6 +249,7 @@ static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv)
 
 static int mlx5i_init_rx(struct mlx5e_priv *priv)
 {
+       struct mlx5i_priv *ipriv  = priv->ppriv;
        int err;
 
        err = mlx5e_create_indirect_rqt(priv);
@@ -271,12 +268,18 @@ static int mlx5i_init_rx(struct mlx5e_priv *priv)
        if (err)
                goto err_destroy_indirect_tirs;
 
-       err = mlx5i_create_flow_steering(priv);
+       err = mlx5_fs_add_rx_underlay_qpn(priv->mdev, ipriv->qp.qpn);
        if (err)
                goto err_destroy_direct_tirs;
 
+       err = mlx5i_create_flow_steering(priv);
+       if (err)
+               goto err_remove_rx_underlay_qpn;
+
        return 0;
 
+err_remove_rx_underlay_qpn:
+       mlx5_fs_remove_rx_underlay_qpn(priv->mdev, ipriv->qp.qpn);
 err_destroy_direct_tirs:
        mlx5e_destroy_direct_tirs(priv);
 err_destroy_indirect_tirs:
@@ -290,6 +293,9 @@ err_destroy_indirect_rqts:
 
 static void mlx5i_cleanup_rx(struct mlx5e_priv *priv)
 {
+       struct mlx5i_priv *ipriv  = priv->ppriv;
+
+       mlx5_fs_remove_rx_underlay_qpn(priv->mdev, ipriv->qp.qpn);
        mlx5i_destroy_flow_steering(priv);
        mlx5e_destroy_direct_tirs(priv);
        mlx5e_destroy_indirect_tirs(priv);
index a3a836bdcfd29c18e2ba46822a559c8e6982d7fb..f26f97fe46666ff7a3f2ce6c496cb8936ee5cbb3 100644 (file)
@@ -162,22 +162,17 @@ static bool mlx5_lag_is_bonded(struct mlx5_lag *ldev)
 static void mlx5_infer_tx_affinity_mapping(struct lag_tracker *tracker,
                                           u8 *port1, u8 *port2)
 {
-       if (tracker->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) {
-               if (tracker->netdev_state[0].tx_enabled) {
-                       *port1 = 1;
-                       *port2 = 1;
-               } else {
-                       *port1 = 2;
-                       *port2 = 2;
-               }
-       } else {
-               *port1 = 1;
-               *port2 = 2;
-               if (!tracker->netdev_state[0].link_up)
-                       *port1 = 2;
-               else if (!tracker->netdev_state[1].link_up)
-                       *port2 = 1;
+       *port1 = 1;
+       *port2 = 2;
+       if (!tracker->netdev_state[0].tx_enabled ||
+           !tracker->netdev_state[0].link_up) {
+               *port1 = 2;
+               return;
        }
+
+       if (!tracker->netdev_state[1].tx_enabled ||
+           !tracker->netdev_state[1].link_up)
+               *port2 = 1;
 }
 
 static void mlx5_activate_lag(struct mlx5_lag *ldev,
index 6a3d6bef7dd4a4a99d6e8427a0a35a78c0b56d20..6a263e8d883a6bae2791a011026e03bc0cd1dead 100644 (file)
@@ -154,6 +154,11 @@ int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
 
+#define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) &&               \
+                           MLX5_CAP_GEN((mdev), pps_modify) &&         \
+                           MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) &&  \
+                           MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
+
 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw);
 
 void mlx5e_init(void);
index bcdf7779c48d79ffb85f3505e122210d16e9b46d..bf99d40e30b4e07a234ea68366d226267d365d7b 100644 (file)
@@ -88,7 +88,11 @@ static void mlx5_device_disable_sriov(struct mlx5_core_dev *dev)
        int vf;
 
        if (!sriov->enabled_vfs)
+#ifdef CONFIG_MLX5_CORE_EN
+               goto disable_sriov_resources;
+#else
                return;
+#endif
 
        for (vf = 0; vf < sriov->num_vfs; vf++) {
                if (!sriov->vfs_ctx[vf].enabled)
@@ -103,6 +107,7 @@ static void mlx5_device_disable_sriov(struct mlx5_core_dev *dev)
        }
 
 #ifdef CONFIG_MLX5_CORE_EN
+disable_sriov_resources:
        mlx5_eswitch_disable_sriov(dev->priv.eswitch);
 #endif
 
index 383fef5a8e24203e20137671c0924f7cc7cbfbf3..4b2e0fd7d51e0a6635cdea75055eec9365d21588 100644 (file)
@@ -1512,6 +1512,10 @@ mlxsw_sp_nexthop_group_mac_update(struct mlxsw_sp *mlxsw_sp,
 static int mlxsw_sp_fib_entry_update(struct mlxsw_sp *mlxsw_sp,
                                     struct mlxsw_sp_fib_entry *fib_entry);
 
+static bool
+mlxsw_sp_fib_node_entry_is_first(const struct mlxsw_sp_fib_node *fib_node,
+                                const struct mlxsw_sp_fib_entry *fib_entry);
+
 static int
 mlxsw_sp_nexthop_fib_entries_update(struct mlxsw_sp *mlxsw_sp,
                                    struct mlxsw_sp_nexthop_group *nh_grp)
@@ -1520,6 +1524,9 @@ mlxsw_sp_nexthop_fib_entries_update(struct mlxsw_sp *mlxsw_sp,
        int err;
 
        list_for_each_entry(fib_entry, &nh_grp->fib_list, nexthop_group_node) {
+               if (!mlxsw_sp_fib_node_entry_is_first(fib_entry->fib_node,
+                                                     fib_entry))
+                       continue;
                err = mlxsw_sp_fib_entry_update(mlxsw_sp, fib_entry);
                if (err)
                        return err;
index 22cf6353ba0418ab5c64ad1fbb343c797d82f18d..7ecf549c7f1cd594f86f165c02743f415f7ada85 100644 (file)
@@ -205,7 +205,7 @@ static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
 {
        int i;
 
-       for (i = 0; i < 23; i++)
+       for (i = 0; i < NUM_DWMAC1000_DMA_REGS; i++)
                if ((i < 12) || (i > 17))
                        reg_space[DMA_BUS_MODE / 4 + i] =
                                readl(ioaddr + DMA_BUS_MODE + i * 4);
index eef2f222ce9a87f91a1d02fa6a6c7354486d4231..6502b9aa3bf587d0095816052066ce301a765634 100644 (file)
@@ -70,7 +70,7 @@ static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
 {
        int i;
 
-       for (i = 0; i < 9; i++)
+       for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++)
                reg_space[DMA_BUS_MODE / 4 + i] =
                        readl(ioaddr + DMA_BUS_MODE + i * 4);
 
index 9091df86723a3988075cbda535d5d6ba21826b7b..adc54006f8843a5bb2081de064291068e66fcf28 100644 (file)
 #define DMA_STATUS_TI  0x00000001      /* Transmit Interrupt */
 #define DMA_CONTROL_FTF                0x00100000      /* Flush transmit FIFO */
 
+#define NUM_DWMAC100_DMA_REGS  9
+#define NUM_DWMAC1000_DMA_REGS 23
+
 void dwmac_enable_dma_transmission(void __iomem *ioaddr);
 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan);
 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan);
index babb39c646ff2f64c96880b437cbca5fc5668453..af30b4857c3b9352d4b9745ebdb07779b7621afc 100644 (file)
@@ -33,6 +33,8 @@
 #define MAC100_ETHTOOL_NAME    "st_mac100"
 #define GMAC_ETHTOOL_NAME      "st_gmac"
 
+#define ETHTOOL_DMA_OFFSET     55
+
 struct stmmac_stats {
        char stat_string[ETH_GSTRING_LEN];
        int sizeof_stat;
@@ -442,6 +444,9 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
 
        priv->hw->mac->dump_regs(priv->hw, reg_space);
        priv->hw->dma->dump_regs(priv->ioaddr, reg_space);
+       /* Copy DMA registers to where ethtool expects them */
+       memcpy(&reg_space[ETHTOOL_DMA_OFFSET], &reg_space[DMA_BUS_MODE / 4],
+              NUM_DWMAC1000_DMA_REGS * 4);
 }
 
 static void
index 3af540adb3c58e83b4265c77fa436d7d44da06c7..fca1bca7f69d1c4c1307c1cc7e2a11f80d6ec866 100644 (file)
@@ -13,9 +13,9 @@
 /* Happy Meal global registers. */
 #define GREG_SWRESET   0x000UL /* Software Reset  */
 #define GREG_CFG       0x004UL /* Config Register */
-#define GREG_STAT      0x108UL /* Status          */
-#define GREG_IMASK     0x10cUL /* Interrupt Mask  */
-#define GREG_REG_SIZE  0x110UL
+#define GREG_STAT      0x100UL /* Status          */
+#define GREG_IMASK     0x104UL /* Interrupt Mask  */
+#define GREG_REG_SIZE  0x108UL
 
 /* Global reset register. */
 #define GREG_RESET_ETX         0x01
index d9db8a06afd26ef901aa0e5cf559559657ea3179..cce9c9ed46aa9a8462080c5949bdb6621e247f0d 100644 (file)
@@ -1338,7 +1338,7 @@ static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
 {
        static int count;
-       printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
+       printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):",
               dev->name, status);
        if (status & Int_IntPCI)
                printk(" IntPCI");
index 63c98bbbc596dbe11cc74ba71c384da02c5d763b..0d78727f1a14dd9c4ae301f053769437cbe4eb3b 100644 (file)
@@ -315,14 +315,34 @@ static u32 init_page_array(void *hdr, u32 len, struct sk_buff *skb,
        return slots_used;
 }
 
-/* Estimate number of page buffers neede to transmit
- * Need at most 2 for RNDIS header plus skb body and fragments.
- */
-static unsigned int netvsc_get_slots(const struct sk_buff *skb)
+static int count_skb_frag_slots(struct sk_buff *skb)
+{
+       int i, frags = skb_shinfo(skb)->nr_frags;
+       int pages = 0;
+
+       for (i = 0; i < frags; i++) {
+               skb_frag_t *frag = skb_shinfo(skb)->frags + i;
+               unsigned long size = skb_frag_size(frag);
+               unsigned long offset = frag->page_offset;
+
+               /* Skip unused frames from start of page */
+               offset &= ~PAGE_MASK;
+               pages += PFN_UP(offset + size);
+       }
+       return pages;
+}
+
+static int netvsc_get_slots(struct sk_buff *skb)
 {
-       return PFN_UP(offset_in_page(skb->data) + skb_headlen(skb))
-               + skb_shinfo(skb)->nr_frags
-               + 2;
+       char *data = skb->data;
+       unsigned int offset = offset_in_page(data);
+       unsigned int len = skb_headlen(skb);
+       int slots;
+       int frag_slots;
+
+       slots = DIV_ROUND_UP(offset + len, PAGE_SIZE);
+       frag_slots = count_skb_frag_slots(skb);
+       return slots + frag_slots;
 }
 
 static u32 net_checksum_info(struct sk_buff *skb)
@@ -360,18 +380,21 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net)
        struct hv_page_buffer page_buf[MAX_PAGE_BUFFER_COUNT];
        struct hv_page_buffer *pb = page_buf;
 
-       /* We can only transmit MAX_PAGE_BUFFER_COUNT number
+       /* We will atmost need two pages to describe the rndis
+        * header. We can only transmit MAX_PAGE_BUFFER_COUNT number
         * of pages in a single packet. If skb is scattered around
         * more pages we try linearizing it.
         */
-       num_data_pgs = netvsc_get_slots(skb);
+
+       num_data_pgs = netvsc_get_slots(skb) + 2;
+
        if (unlikely(num_data_pgs > MAX_PAGE_BUFFER_COUNT)) {
                ++net_device_ctx->eth_stats.tx_scattered;
 
                if (skb_linearize(skb))
                        goto no_memory;
 
-               num_data_pgs = netvsc_get_slots(skb);
+               num_data_pgs = netvsc_get_slots(skb) + 2;
                if (num_data_pgs > MAX_PAGE_BUFFER_COUNT) {
                        ++net_device_ctx->eth_stats.tx_too_big;
                        goto drop;
index 6f6ed75b63c97e7eaa2e49e7fcb385ca965f1ca5..765de3bedb8817d018b4f6143b3195c581cc3834 100644 (file)
@@ -141,9 +141,19 @@ static int mcs_set_reg(struct mcs_cb *mcs, __u16 reg, __u16 val)
 static int mcs_get_reg(struct mcs_cb *mcs, __u16 reg, __u16 * val)
 {
        struct usb_device *dev = mcs->usbdev;
-       int ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), MCS_RDREQ,
-                                 MCS_RD_RTYPE, 0, reg, val, 2,
-                                 msecs_to_jiffies(MCS_CTRL_TIMEOUT));
+       void *dmabuf;
+       int ret;
+
+       dmabuf = kmalloc(sizeof(__u16), GFP_KERNEL);
+       if (!dmabuf)
+               return -ENOMEM;
+
+       ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), MCS_RDREQ,
+                             MCS_RD_RTYPE, 0, reg, dmabuf, 2,
+                             msecs_to_jiffies(MCS_CTRL_TIMEOUT));
+
+       memcpy(val, dmabuf, sizeof(__u16));
+       kfree(dmabuf);
 
        return ret;
 }
index 2dda72004a7d5ba0ede8fb34c853bce2266ace4a..928fd892f167546e329f913ec10ea56e454cea0d 100644 (file)
@@ -7,7 +7,16 @@ menuconfig MDIO_DEVICE
        help
           MDIO devices and driver infrastructure code.
 
-if MDIO_DEVICE
+config MDIO_BUS
+       tristate
+       default m if PHYLIB=m
+       default MDIO_DEVICE
+       help
+         This internal symbol is used for link time dependencies and it
+         reflects whether the mdio_bus/mdio_device code is built as a
+         loadable module or built-in.
+
+if MDIO_BUS
 
 config MDIO_BCM_IPROC
        tristate "Broadcom iProc MDIO bus controller"
@@ -28,7 +37,6 @@ config MDIO_BCM_UNIMAC
 
 config MDIO_BITBANG
        tristate "Bitbanged MDIO buses"
-       depends on !(MDIO_DEVICE=y && PHYLIB=m)
        help
          This module implements the MDIO bus protocol in software,
          for use by low level drivers that export the ability to
@@ -127,7 +135,6 @@ config MDIO_THUNDER
        tristate "ThunderX SOCs MDIO buses"
        depends on 64BIT
        depends on PCI
-       depends on !(MDIO_DEVICE=y && PHYLIB=m)
        select MDIO_CAVIUM
        help
          This driver supports the MDIO interfaces found on Cavium
index d0626bf5c540911b0d15bdbab1b960145b6d124c..5068c582d502c6944a01a2ee87062d7ffb409034 100644 (file)
@@ -749,6 +749,9 @@ void phy_stop_machine(struct phy_device *phydev)
        if (phydev->state > PHY_UP && phydev->state != PHY_HALTED)
                phydev->