drm/i915: Rename GFX_TLB_INVALIDATE_ALWAYS

The documentation calls this GFX_MODE bit "Flush TLB invalidate Mode".
However, that is not a good name for an enable bit as it doesn't make it
clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS
as enabling that bit actually prevents the TLB from being invalidated at
every flush. This leads to great confusion when reading code and
proposed patches. To get around this try to bake in what is enabled by
setting the bit and call it GFX_TLB_INVALIDATE_EXPLICIT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Gupta, Sourab" <sourab.gupta@intel.com>
Acked-by: "Gupta, Sourab" <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f5b18d9d8850e886eeb44ca68b0bd17af4c3f30..15c27479edbc4097d994305f3cce42fbef0a67ee 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -841,7 +841,7 @@ enum punit_power_well {
 #define GFX_MODE_GEN7  0x0229c
 #define RING_MODE_GEN7(ring)   ((ring)->mmio_base+0x29c)
 #define   GFX_RUN_LIST_ENABLE          (1<<15)
-#define   GFX_TLB_INVALIDATE_ALWAYS    (1<<13)
+#define   GFX_TLB_INVALIDATE_EXPLICIT  (1<<13)
 #define   GFX_SURFACE_FAULT_ENABLE     (1<<12)
 #define   GFX_REPLAY_MODE              (1<<11)
 #define   GFX_PSMI_GRANULARITY         (1<<10)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6bc68bdcf433cf06a68d52d95b063f9a42795194..64a0ecf970b9444ffb58ca9e97ccfd26bf9add2c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -589,11 +589,11 @@ static int init_render_ring(struct intel_ring_buffer *ring)
        /* Required for the hardware to program scanline values for waiting */
        if (INTEL_INFO(dev)->gen == 6)
                I915_WRITE(GFX_MODE,
-                          _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
+                          _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 
        if (IS_GEN7(dev))
                I915_WRITE(GFX_MODE_GEN7,
-                          _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
+                          _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
                           _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 
        if (INTEL_INFO(dev)->gen >= 5) {
@@ -616,7 +616,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
                 * TODO: consider explicitly setting the bit for GEN5
                 */
                ring->itlb_before_ctx_switch =
-                       !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
+                       !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_EXPLICIT);
        }
 
        if (INTEL_INFO(dev)->gen >= 6)