ARM: dts: Add Arria10 Ethernet EDAC devicetree entry
authorThor Thayer <tthayer@opensource.altera.com>
Wed, 22 Jun 2016 13:58:59 +0000 (08:58 -0500)
committerBorislav Petkov <bp@suse.de>
Mon, 27 Jun 2016 17:46:19 +0000 (19:46 +0200)
Add the device tree entries needed to support the Altera Ethernet FIFO
buffer EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1466603939-7526-9-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
arch/arm/boot/dts/socfpga_arria10.dtsi

index 17e81dc9213e795455052e05fc426faf9f559719..5820b70c95b3076c1b8d7c7d07f936440eb27033 100644 (file)
                                compatible = "altr,socfpga-a10-ocram-ecc";
                                reg = <0xff8c3000 0x400>;
                        };
                                compatible = "altr,socfpga-a10-ocram-ecc";
                                reg = <0xff8c3000 0x400>;
                        };
+
+                       emac0-rx-ecc@ff8c0800 {
+                               compatible = "altr,socfpga-eth-mac-ecc";
+                               reg = <0xff8c0800 0x400>;
+                               altr,ecc-parent = <&gmac0>;
+                               interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+                                            <36 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       emac0-tx-ecc@ff8c0c00 {
+                               compatible = "altr,socfpga-eth-mac-ecc";
+                               reg = <0xff8c0c00 0x400>;
+                               altr,ecc-parent = <&gmac0>;
+                               interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+                                            <37 IRQ_TYPE_LEVEL_HIGH>;
+                       };
                };
 
                rst: rstmgr@ffd05000 {
                };
 
                rst: rstmgr@ffd05000 {