ARM: dts: Move omap5 mmio-sram out of l3 interconnect

We need mmio-sram early for omap4_sram_init() for IO barrier init, and
will be moving l3 interconnect to probe with simple-pm-bus that probes
at module_init() time. So let's move mmio-sram out of l3 to prepare for
that.

Otherwise we will get the following after probing the interconnects with
simple-pm-bus:

omap4_sram_init:Unable to get sram pool needed to handle errata I688

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index f4132dfae814d5efc6802066665326c713adb1de..42b525510b52207d48c21bd87b032137eabecca7 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -106,6 +106,15 @@
                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       /*
+        * Needed early by omap4_sram_init() for barrier, do not move to l3
+        * interconnect as simple-pm-bus probes at module_init() time.
+        */
+       ocmcram: sram@40300000 {
+               compatible = "mmio-sram";
+               reg = <0 0x40300000 0 0x20000>; /* 128k */
+       };
+
        gic: interrupt-controller@48211000 {
                compatible = "arm,cortex-a15-gic";
                interrupt-controller;
@@ -172,11 +181,6 @@
                l4_abe: interconnect@40100000 {
                };
 
-               ocmcram: sram@40300000 {
-                       compatible = "mmio-sram";
-                       reg = <0x40300000 0x20000>; /* 128k */
-               };
-
                target-module@50000000 {
                        compatible = "ti,sysc-omap2", "ti,sysc";
                        reg = <0x50000000 4>,