drm/i915/skl: drop workarounds for A0 and B0 revisions

Pre-production hardware is not supported.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/7929af62a68504c84038a8db1625bd96ebaa9e6f.1474034059.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0568fb53b7cd746e35e40ea56592b8975e0cd8ce..57da2b7510df4e6598d6af372f7f799074f3bb5c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = dig_port->base.base.dev;
 
-       /* WaDisableHBR2:skl */
-       if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
-               return false;
-
        if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
            (INTEL_INFO(dev)->gen >= 9))
                return true;

diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index c438b02184cb06a0902ad3dd9ba4ae43622f0e2d..0048b520baf7c7bf210c2287b3d5c5f0139ceb52 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
         * Intel platforms that support HBR2 also support TPS3. TPS3 support is
         * also mandatory for downstream devices that support HBR2. However, not
         * all sinks follow the spec.
-        *
-        * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
-        * supported in source but still not enabled.
         */
        source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
        sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6fd39efb789475e1ec7cb50e594d9e6ddcc2e409..acc1dbdd024ebc77387226a4c2fbff59fc85ef0d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
        /* Enable MIA caching. GuC clock gating is disabled. */
        I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
-       /* WaDisableMinuteIaClockGating:skl,bxt */
-       if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-           IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+       /* WaDisableMinuteIaClockGating:bxt */
+       if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
                                              ~GUC_ENABLE_MIA_CLOCK_GATING));
        }

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 39417b77bff2da19d85ed6d24190cd0e57543f58..47f7afa538a1055d6d838f0bdb63e326fa2bd195 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
        struct drm_i915_private *dev_priv = engine->i915;
 
        engine->disable_lite_restore_wa =
-               (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
-                IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
+               IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
                (engine->id == VCS || engine->id == VCS2);
 
        engine->ctx_desc_template = GEN8_CTX_VALID;
@@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
 {
        uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-       /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-       if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
-           IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
+       /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+       if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
                wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
                wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
                wa_ctx_emit(batch, index,

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7a74750076c57cb21b91461cbefe386e372ca783..2faf64f9f256e6758f5e7436b6d2ab23eede892d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
        WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
                          GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
-       /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
-       if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
-           IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+       /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
+       if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
                WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
                                  GEN9_DG_MIRROR_FIX_ENABLE);
 
-       /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-       if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
-           IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
+       /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+       if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
                WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
                                  GEN9_RHWO_OPTIMIZATION_DISABLE);
                /*
@@ -1023,15 +1021,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
                           GEN8_LQSC_RO_PERF_DIS);
 
        /* WaEnableGapsTsvCreditFix:skl */
-       if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
-               I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-                                          GEN9_GAPS_TSV_CREDIT_DISABLE));
-       }
-
-       /* WaDisablePowerCompilerClockGating:skl */
-       if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
-               WA_SET_BIT_MASKED(HIZ_CHICKEN,
-                                 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
+       I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+                                  GEN9_GAPS_TSV_CREDIT_DISABLE));
 
        /* WaBarrierPerformanceFixDisable:skl */
        if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))