KVM: vmx/pmu: Add PMU_CAP_LBR_FMT check when guest LBR is enabled

Usespace could set the bits [0, 5] of the IA32_PERF_CAPABILITIES
MSR which tells about the record format stored in the LBR records.

The LBR will be enabled on the guest if host perf supports LBR
(checked via x86_perf_get_lbr()) and the vcpu model is compatible
with the host one.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20210201051039.255478-4-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index d0f31fcccd2ba886045971d6b46c3f575ae8ab1b..da3db1a37b34f1c430a0689045b3a8d3a4650e91 100644 (file)
--- a/arch/x86/kvm/vmx/capabilities.h
+++ b/arch/x86/kvm/vmx/capabilities.h
@@ -19,6 +19,7 @@ extern int __read_mostly pt_mode;
 #define PT_MODE_HOST_GUEST     1
 
 #define PMU_CAP_FW_WRITES      (1ULL << 13)
+#define PMU_CAP_LBR_FMT                0x3f
 
 struct nested_vmx_msrs {
        /*

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 7403d46998d673d8c8b826fb51964c60c1f8cf44..d21104e6f9ec34515bc368c157f81be8537edbe7 100644 (file)
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -173,6 +173,16 @@ static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)
        return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);
 }
 
+bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu)
+{
+       /*
+        * As a first step, a guest could only enable LBR feature if its
+        * cpu model is the same as the host because the LBR registers
+        * would be pass-through to the guest and they're model specific.
+        */
+       return boot_cpu_data.x86_model == guest_cpuid_model(vcpu);
+}
+
 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
 {
        struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
@@ -321,6 +331,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 {
        struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+       struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
+
        struct x86_pmu_capability x86_pmu;
        struct kvm_cpuid_entry2 *entry;
        union cpuid10_eax eax;
@@ -387,12 +399,18 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
                INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);
 
        nested_vmx_pmu_entry_exit_ctls_update(vcpu);
+
+       if (intel_pmu_lbr_is_compatible(vcpu))
+               x86_perf_get_lbr(&lbr_desc->records);
+       else
+               lbr_desc->records.nr = 0;
 }
 
 static void intel_pmu_init(struct kvm_vcpu *vcpu)
 {
        int i;
        struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+       struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
 
        for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
                pmu->gp_counters[i].type = KVM_PMC_GP;
@@ -409,6 +427,7 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu)
        }
 
        vcpu->arch.perf_capabilities = vmx_get_perf_capabilities();
+       lbr_desc->records.nr = 0;
 }
 
 static void intel_pmu_reset(struct kvm_vcpu *vcpu)

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index c4b15f9f69b08a0349a7875c9266fa3d3df688c4..9a978a49721b5d1ec82e99bc935a44fd5f7291c0 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2211,6 +2211,18 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                if ((data >> 32) != 0)
                        return 1;
                goto find_uret_msr;
+       case MSR_IA32_PERF_CAPABILITIES:
+               if (data && !vcpu_to_pmu(vcpu)->version)
+                       return 1;
+               if (data & PMU_CAP_LBR_FMT) {
+                       if ((data & PMU_CAP_LBR_FMT) !=
+                           (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
+                               return 1;
+                       if (!intel_pmu_lbr_is_compatible(vcpu))
+                               return 1;
+               }
+               ret = kvm_set_msr_common(vcpu, msr_info);
+               break;
 
        default:
        find_uret_msr:

diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 94bf7fd4e6eaf262ff109661083da45569f6d489..df61b0d09eb749a55171c72be378c41b7077bce6 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -93,6 +93,16 @@ union vmx_exit_reason {
        u32 full;
 };
 
+#define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
+#define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
+
+bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
+
+struct lbr_desc {
+       /* Basic info about guest LBR records. */
+       struct x86_pmu_lbr records;
+};
+
 /*
  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
@@ -302,6 +312,7 @@ struct vcpu_vmx {
        u64 ept_pointer;
 
        struct pt_desc pt_desc;
+       struct lbr_desc lbr_desc;
 
        /* Save desired MSR intercept (read: pass-through) state */
 #define MAX_POSSIBLE_PASSTHROUGH_MSRS  13