Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 cpu handling changes from Ingo Molnar:
 "Bigger changes:

   - Intel CPU hardware-enablement: new vector instructions support
     (AVX-512), by Fenghua Yu.

   - Support the clflushopt instruction and use it in appropriate
     places.  clflushopt is similar to clflush but with more relaxed
     ordering, by Ross Zwisler.

   - MSR accessor cleanups, by Borislav Petkov.

   - 'forcepae' boot flag for those who have way too much time to spend
     on way too old Pentium-M systems and want to live way too
     dangerously, by Chris Bainbridge"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, cpu: Add forcepae parameter for booting PAE kernels on PAE-disabled Pentium M
  Rename TAINT_UNSAFE_SMP to TAINT_CPU_OUT_OF_SPEC
  x86, intel: Make MSR_IA32_MISC_ENABLE bit constants systematic
  x86, Intel: Convert to the new bit access MSR accessors
  x86, AMD: Convert to the new bit access MSR accessors
  x86: Add another set of MSR accessor functions
  x86: Use clflushopt in drm_clflush_virt_range
  x86: Use clflushopt in drm_clflush_page
  x86: Use clflushopt in clflush_cache_range
  x86: Add support for the clflushopt instruction
  x86, AVX-512: Enable AVX-512 States Context Switch
  x86, AVX-512: AVX-512 Feature Detection

diff --combined arch/x86/mm/pageattr.c
index ba957c9b677ce177c19b47702acb2e2bdb70ba49,b1c46723b19b74d529f894d87a90c54e0fbf8a78..cf125b301b692304da63fa72534a8d285ca0da3f
--- 1/arch/x86/mm/pageattr.c
--- 2/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@@ -126,8 -126,8 +126,8 @@@ within(unsigned long addr, unsigned lon
   * @vaddr:    virtual start address
   * @size:     number of bytes to flush
   *
-  * clflush is an unordered instruction which needs fencing with mfence
-  * to avoid ordering issues.
+  * clflushopt is an unordered instruction which needs fencing with mfence or
+  * sfence to avoid ordering issues.
   */
  void clflush_cache_range(void *vaddr, unsigned int size)
  {
@@@ -136,11 -136,11 +136,11 @@@
        mb();
  
        for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
-               clflush(vaddr);
+               clflushopt(vaddr);
        /*
         * Flush any possible final partial cacheline:
         */
-       clflush(vend);
+       clflushopt(vend);
  
        mb();
  }
@@@ -1377,10 -1377,10 +1377,10 @@@ static int change_page_attr_set_clr(uns
        cache = cache_attr(mask_set);
  
        /*
 -       * On success we use clflush, when the CPU supports it to
 -       * avoid the wbindv. If the CPU does not support it and in the
 +       * On success we use CLFLUSH, when the CPU supports it to
 +       * avoid the WBINVD. If the CPU does not support it and in the
         * error case we fall back to cpa_flush_all (which uses
 -       * wbindv):
 +       * WBINVD):
         */
        if (!ret && cpu_has_clflush) {
                if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {