Merge tag 'pci-v4.14-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 16 Sep 2017 03:25:06 +0000 (20:25 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 16 Sep 2017 03:25:06 +0000 (20:25 -0700)
Pull PCI fix from Bjorn Helgaas:
 "Revert an attempt to fix a race while enabling upstream bridges
  because it broke iwlwifi firmware loading"

* tag 'pci-v4.14-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  Revert "PCI: Avoid race while enabling upstream bridges"

220 files changed:
Documentation/devicetree/bindings/i2c/i2c-altera.txt [new file with mode: 0644]
Documentation/devicetree/bindings/i2c/i2c-stm32.txt
Documentation/filesystems/orangefs.txt
MAINTAINERS
Makefile
arch/mips/kvm/mips.c
arch/nios2/boot/dts/3c120_devboard.dts
arch/nios2/kernel/time.c
arch/powerpc/kernel/align.c
arch/powerpc/kvm/book3s_hv.c
arch/powerpc/kvm/book3s_hv_rm_xive.c
arch/powerpc/kvm/book3s_hv_rmhandlers.S
arch/powerpc/kvm/book3s_xive.c
arch/powerpc/kvm/book3s_xive_template.c
arch/x86/include/asm/kvm_host.h
arch/x86/kernel/kvm.c
arch/x86/kvm/cpuid.h
arch/x86/kvm/lapic.c
arch/x86/kvm/svm.c
arch/x86/kvm/vmx.c
arch/x86/kvm/x86.c
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/include/vi_structs.h
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
drivers/gpu/drm/ttm/ttm_bo.c
drivers/gpu/drm/ttm/ttm_bo_util.c
drivers/i2c/busses/Kconfig
drivers/i2c/busses/Makefile
drivers/i2c/busses/i2c-altera.c [new file with mode: 0644]
drivers/i2c/busses/i2c-stm32.h [new file with mode: 0644]
drivers/i2c/busses/i2c-stm32f4.c
drivers/i2c/busses/i2c-stm32f7.c [new file with mode: 0644]
firmware/.gitignore [deleted file]
firmware/3com/typhoon.bin.ihex [deleted file]
firmware/Makefile [deleted file]
firmware/README.AddingFirmware [deleted file]
firmware/WHENCE [deleted file]
firmware/acenic/tg1.bin.ihex [deleted file]
firmware/acenic/tg2.bin.ihex [deleted file]
firmware/adaptec/starfire_rx.bin.ihex [deleted file]
firmware/adaptec/starfire_tx.bin.ihex [deleted file]
firmware/advansys/3550.bin.ihex [deleted file]
firmware/advansys/38C0800.bin.ihex [deleted file]
firmware/advansys/38C1600.bin.ihex [deleted file]
firmware/advansys/mcode.bin.ihex [deleted file]
firmware/atmsar11.HEX [deleted file]
firmware/av7110/Boot.S [deleted file]
firmware/av7110/bootcode.bin.ihex [deleted file]
firmware/bnx2/bnx2-mips-06-6.2.1.fw.ihex [deleted file]
firmware/bnx2/bnx2-mips-09-6.2.1a.fw.ihex [deleted file]
firmware/bnx2/bnx2-rv2p-06-6.0.15.fw.ihex [deleted file]
firmware/bnx2/bnx2-rv2p-09-6.0.17.fw.ihex [deleted file]
firmware/bnx2/bnx2-rv2p-09ax-6.0.17.fw.ihex [deleted file]
firmware/bnx2x/bnx2x-e1-6.2.9.0.fw.ihex [deleted file]
firmware/bnx2x/bnx2x-e1h-6.2.9.0.fw.ihex [deleted file]
firmware/bnx2x/bnx2x-e2-6.2.9.0.fw.ihex [deleted file]
firmware/cis/.gitignore [deleted file]
firmware/cis/3CCFEM556.cis.ihex [deleted file]
firmware/cis/3CXEM556.cis.ihex [deleted file]
firmware/cis/COMpad2.cis.ihex [deleted file]
firmware/cis/COMpad4.cis.ihex [deleted file]
firmware/cis/DP83903.cis.ihex [deleted file]
firmware/cis/LA-PCM.cis.ihex [deleted file]
firmware/cis/MT5634ZLX.cis.ihex [deleted file]
firmware/cis/NE2K.cis.ihex [deleted file]
firmware/cis/PCMLM28.cis.ihex [deleted file]
firmware/cis/PE-200.cis.ihex [deleted file]
firmware/cis/PE520.cis.ihex [deleted file]
firmware/cis/RS-COM-2P.cis.ihex [deleted file]
firmware/cis/SW_555_SER.cis.ihex [deleted file]
firmware/cis/SW_7xx_SER.cis.ihex [deleted file]
firmware/cis/SW_8xx_SER.cis.ihex [deleted file]
firmware/cis/tamarack.cis.ihex [deleted file]
firmware/cpia2/stv0672_vp4.bin.ihex [deleted file]
firmware/cxgb3/ael2005_opt_edc.bin.ihex [deleted file]
firmware/cxgb3/ael2005_twx_edc.bin.ihex [deleted file]
firmware/cxgb3/ael2020_twx_edc.bin.ihex [deleted file]
firmware/cxgb3/t3b_psram-1.1.0.bin.ihex [deleted file]
firmware/cxgb3/t3c_psram-1.1.0.bin.ihex [deleted file]
firmware/dsp56k/bootstrap.asm [deleted file]
firmware/dsp56k/bootstrap.bin.ihex [deleted file]
firmware/e100/d101m_ucode.bin.ihex [deleted file]
firmware/e100/d101s_ucode.bin.ihex [deleted file]
firmware/e100/d102e_ucode.bin.ihex [deleted file]
firmware/edgeport/boot.H16 [deleted file]
firmware/edgeport/boot2.H16 [deleted file]
firmware/edgeport/down.H16 [deleted file]
firmware/edgeport/down2.H16 [deleted file]
firmware/edgeport/down3.bin.ihex [deleted file]
firmware/emi26/bitstream.HEX [deleted file]
firmware/emi26/firmware.HEX [deleted file]
firmware/emi26/loader.HEX [deleted file]
firmware/emi62/bitstream.HEX [deleted file]
firmware/emi62/loader.HEX [deleted file]
firmware/emi62/midi.HEX [deleted file]
firmware/emi62/spdif.HEX [deleted file]
firmware/ess/maestro3_assp_kernel.fw.ihex [deleted file]
firmware/ess/maestro3_assp_minisrc.fw.ihex [deleted file]
firmware/ihex2fw.c [deleted file]
firmware/kaweth/new_code.bin.ihex [deleted file]
firmware/kaweth/new_code_fix.bin.ihex [deleted file]
firmware/kaweth/trigger_code.bin.ihex [deleted file]
firmware/kaweth/trigger_code_fix.bin.ihex [deleted file]
firmware/keyspan/mpr.HEX [deleted file]
firmware/keyspan/usa18x.HEX [deleted file]
firmware/keyspan/usa19.HEX [deleted file]
firmware/keyspan/usa19qi.HEX [deleted file]
firmware/keyspan/usa19qw.HEX [deleted file]
firmware/keyspan/usa19w.HEX [deleted file]
firmware/keyspan/usa28.HEX [deleted file]
firmware/keyspan/usa28x.HEX [deleted file]
firmware/keyspan/usa28xa.HEX [deleted file]
firmware/keyspan/usa28xb.HEX [deleted file]
firmware/keyspan/usa49w.HEX [deleted file]
firmware/keyspan/usa49wlc.HEX [deleted file]
firmware/keyspan_pda/keyspan_pda.HEX [deleted file]
firmware/keyspan_pda/keyspan_pda.S [deleted file]
firmware/keyspan_pda/xircom_pgs.HEX [deleted file]
firmware/keyspan_pda/xircom_pgs.S [deleted file]
firmware/korg/k1212.dsp.ihex [deleted file]
firmware/matrox/g200_warp.H16 [deleted file]
firmware/matrox/g400_warp.H16 [deleted file]
firmware/mts_cdma.fw.ihex [deleted file]
firmware/mts_edge.fw.ihex [deleted file]
firmware/mts_gsm.fw.ihex [deleted file]
firmware/myricom/lanai.bin.ihex [deleted file]
firmware/ositech/Xilinx7OD.bin.ihex [deleted file]
firmware/qlogic/1040.bin.ihex [deleted file]
firmware/qlogic/12160.bin.ihex [deleted file]
firmware/qlogic/1280.bin.ihex [deleted file]
firmware/qlogic/isp1000.bin.ihex [deleted file]
firmware/qlogic/sd7220.fw.ihex [deleted file]
firmware/r128/r128_cce.bin.ihex [deleted file]
firmware/radeon/R100_cp.bin.ihex [deleted file]
firmware/radeon/R200_cp.bin.ihex [deleted file]
firmware/radeon/R300_cp.bin.ihex [deleted file]
firmware/radeon/R420_cp.bin.ihex [deleted file]
firmware/radeon/R520_cp.bin.ihex [deleted file]
firmware/radeon/R600_me.bin.ihex [deleted file]
firmware/radeon/R600_pfp.bin.ihex [deleted file]
firmware/radeon/RS600_cp.bin.ihex [deleted file]
firmware/radeon/RS690_cp.bin.ihex [deleted file]
firmware/radeon/RS780_me.bin.ihex [deleted file]
firmware/radeon/RS780_pfp.bin.ihex [deleted file]
firmware/radeon/RV610_me.bin.ihex [deleted file]
firmware/radeon/RV610_pfp.bin.ihex [deleted file]
firmware/radeon/RV620_me.bin.ihex [deleted file]
firmware/radeon/RV620_pfp.bin.ihex [deleted file]
firmware/radeon/RV630_me.bin.ihex [deleted file]
firmware/radeon/RV630_pfp.bin.ihex [deleted file]
firmware/radeon/RV635_me.bin.ihex [deleted file]
firmware/radeon/RV635_pfp.bin.ihex [deleted file]
firmware/radeon/RV670_me.bin.ihex [deleted file]
firmware/radeon/RV670_pfp.bin.ihex [deleted file]
firmware/radeon/RV710_me.bin.ihex [deleted file]
firmware/radeon/RV710_pfp.bin.ihex [deleted file]
firmware/radeon/RV730_me.bin.ihex [deleted file]
firmware/radeon/RV730_pfp.bin.ihex [deleted file]
firmware/radeon/RV770_me.bin.ihex [deleted file]
firmware/radeon/RV770_pfp.bin.ihex [deleted file]
firmware/sb16/alaw_main.csp.ihex [deleted file]
firmware/sb16/ima_adpcm_capture.csp.ihex [deleted file]
firmware/sb16/ima_adpcm_init.csp.ihex [deleted file]
firmware/sb16/ima_adpcm_playback.csp.ihex [deleted file]
firmware/sb16/mulaw_main.csp.ihex [deleted file]
firmware/sun/cassini.bin.ihex [deleted file]
firmware/tehuti/bdx.bin.ihex [deleted file]
firmware/ti_3410.fw.ihex [deleted file]
firmware/ti_5052.fw.ihex [deleted file]
firmware/tigon/tg3.bin.ihex [deleted file]
firmware/tigon/tg3_tso.bin.ihex [deleted file]
firmware/tigon/tg3_tso5.bin.ihex [deleted file]
firmware/ttusb-budget/dspbootcode.bin.ihex [deleted file]
firmware/vicam/firmware.H16 [deleted file]
firmware/whiteheat.HEX [deleted file]
firmware/whiteheat_loader.HEX [deleted file]
firmware/whiteheat_loader_debug.HEX [deleted file]
firmware/yam/1200.bin.ihex [deleted file]
firmware/yam/9600.bin.ihex [deleted file]
firmware/yamaha/ds1_ctrl.fw.ihex [deleted file]
firmware/yamaha/ds1_dsp.fw.ihex [deleted file]
firmware/yamaha/ds1e_ctrl.fw.ihex [deleted file]
firmware/yamaha/yss225_registers.bin.ihex [deleted file]
fs/orangefs/acl.c
fs/orangefs/devorangefs-req.c
fs/orangefs/file.c
fs/orangefs/orangefs-bufmap.c
fs/orangefs/orangefs-debugfs.c
fs/orangefs/orangefs-mod.c
fs/orangefs/super.c
fs/orangefs/xattr.c
include/linux/swait.h
include/trace/events/kvm.h
scripts/Makefile.fwinst [deleted file]
virt/kvm/async_pf.c
virt/kvm/eventfd.c
virt/kvm/kvm_main.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt
new file mode 100644 (file)
index 0000000..767664f
--- /dev/null
@@ -0,0 +1,39 @@
+* Altera I2C Controller
+* This is Altera's synthesizable logic block I2C Controller for use
+* in Altera's FPGAs.
+
+Required properties :
+ - compatible : should be "altr,softip-i2c-v1.0"
+ - reg        : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number.
+ - clocks     : phandle to input clock.
+ - #address-cells = <1>;
+ - #size-cells = <0>;
+
+Recommended properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+
+Optional properties :
+ - fifo-size : Size of the RX and TX FIFOs in bytes.
+ - Child nodes conforming to i2c bus binding
+
+Example :
+
+       i2c@100080000 {
+               compatible = "altr,softip-i2c-v1.0";
+               reg = <0x00000001 0x00080000 0x00000040>;
+               interrupt-parent = <&intc>;
+               interrupts = <0 43 4>;
+               clocks = <&clk_0>;
+               clock-frequency = <100000>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               fifo-size = <4>;
+
+               eeprom@51 {
+                       compatible = "atmel,24c32";
+                       reg = <0x51>;
+                       pagesize = <32>;
+               };
+       };
+
index 78eaf7b718eddc764385357449cffa835c3c0d97..3b54899666342b8e5a114bc0842e193871139d5e 100644 (file)
@@ -1,7 +1,9 @@
 * I2C controller embedded in STMicroelectronics STM32 I2C platform
 
 Required properties :
-- compatible : Must be "st,stm32f4-i2c"
+- compatible : Must be one of the following
+  - "st,stm32f4-i2c"
+  - "st,stm32f7-i2c"
 - reg : Offset and length of the register set for the device
 - interrupts : Must contain the interrupt id for I2C event and then the
   interrupt id for I2C error.
@@ -14,8 +16,16 @@ Required properties :
 
 Optional properties :
 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
-  the default 100 kHz frequency will be used. As only Normal and Fast modes
-  are supported, possible values are 100000 and 400000.
+  the default 100 kHz frequency will be used.
+  For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
+  100000 and 400000.
+  For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
+  possible values are 100000, 400000 and 1000000.
+- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
+  (default: 25)
+- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
+  (default: 10)
+  I2C Timings are derived from these 2 values
 
 Example :
 
@@ -31,3 +41,16 @@ Example :
                pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
                pinctrl-names = "default";
        };
+
+       i2c@40005400 {
+               compatible = "st,stm32f7-i2c";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x40005400 0x400>;
+               interrupts = <31>,
+                            <32>;
+               resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+               clocks = <&rcc 1 CLK_I2C1>;
+               pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+               pinctrl-names = "default";
+       };
index 1dfdec7909464650acd7786db4368e03223c0765..e2818b60a5c21739d65588cdcac350af0809e794 100644 (file)
@@ -45,14 +45,11 @@ upstream version of the kernel client.
 BUILDING THE USERSPACE FILESYSTEM ON A SINGLE SERVER
 ====================================================
 
-When Orangefs is upstream, "--with-kernel" shouldn't be needed, but
-until then the path to where the kernel with the Orangefs kernel client
-patch was built is needed to ensure that pvfs2-client-core (the bridge
-between kernel space and user space) will build properly. You can omit
---prefix if you don't care that things are sprinkled around in
-/usr/local.
+You can omit --prefix if you don't care that things are sprinkled around in
+/usr/local. As of version 2.9.6, Orangefs uses Berkeley DB by default, we
+will probably be changing the default to lmdb soon.
 
-./configure --prefix=/opt/ofs --with-kernel=/path/to/orangefs/kernel
+./configure --prefix=/opt/ofs --with-db-backend=lmdb
 
 make
 
@@ -82,9 +79,6 @@ prove things are working with:
 
 /opt/osf/bin/pvfs2-ls /mymountpoint
 
-You might not want to enforce selinux, it doesn't seem to matter by
-linux 3.11...
-
 If stuff seems to be working, turn on the client core:
 /opt/osf/sbin/pvfs2-client -p /opt/osf/sbin/pvfs2-client-core
 
index 209306019483c88ece7c990b9d3fe85f77837535..4b914dd27bae6c9f353a69cc2b3e4fc9e3a30cb8 100644 (file)
@@ -644,6 +644,11 @@ ALPS PS/2 TOUCHPAD DRIVER
 R:     Pali Roh├ír <pali.rohar@gmail.com>
 F:     drivers/input/mouse/alps.*
 
+ALTERA I2C CONTROLLER DRIVER
+M:     Thor Thayer <thor.thayer@linux.intel.com>
+S:     Maintained
+F:     drivers/i2c/busses/i2c-altera.c
+
 ALTERA MAILBOX DRIVER
 M:     Ley Foon Tan <lftan@altera.com>
 L:     nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
index 6585339586a679f0a2c82d2ca311a36269fb99b0..7e2ca4971a39e4f91b3e80cb73b169c691fdc25b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -562,7 +562,7 @@ scripts: scripts_basic include/config/auto.conf include/config/tristate.conf \
 
 # Objects we will link into vmlinux / subdirs we need to visit
 init-y         := init/
-drivers-y      := drivers/ sound/ firmware/
+drivers-y      := drivers/ sound/
 net-y          := net/
 libs-y         := lib/
 core-y         := usr/
@@ -1128,16 +1128,6 @@ headerdep:
        $(Q)find $(srctree)/include/ -name '*.h' | xargs --max-args 1 \
        $(srctree)/scripts/headerdep.pl -I$(srctree)/include
 
-# ---------------------------------------------------------------------------
-# Firmware install
-INSTALL_FW_PATH=$(INSTALL_MOD_PATH)/lib/firmware
-export INSTALL_FW_PATH
-
-PHONY += firmware_install
-firmware_install:
-       @mkdir -p $(objtree)/firmware
-       $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_install
-
 # ---------------------------------------------------------------------------
 # Kernel headers
 
@@ -1216,7 +1206,6 @@ modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin
        $(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.order) > $(objtree)/modules.order
        @$(kecho) '  Building modules, stage 2.';
        $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
-       $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modbuild
 
 modules.builtin: $(vmlinux-dirs:%=%/modules.builtin)
        $(Q)$(AWK) '!x[$$0]++' $^ > $(objtree)/modules.builtin
@@ -1252,7 +1241,6 @@ _modinst_:
 # boot script depmod is the master version.
 PHONY += _modinst_post
 _modinst_post: _modinst_
-       $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modinst
        $(call cmd,depmod)
 
 ifeq ($(CONFIG_MODULE_SIG), y)
@@ -1375,8 +1363,6 @@ help:
        @echo  '* vmlinux         - Build the bare kernel'
        @echo  '* modules         - Build all modules'
        @echo  '  modules_install - Install all modules to INSTALL_MOD_PATH (default: /)'
-       @echo  '  firmware_install- Install all firmware to INSTALL_FW_PATH'
-       @echo  '                    (default: $$(INSTALL_MOD_PATH)/lib/firmware)'
        @echo  '  dir/            - Build all files in dir and below'
        @echo  '  dir/file.[ois]  - Build specified target only'
        @echo  '  dir/file.ll     - Build the LLVM assembly file'
index bce2a6431430366ee626ddc4f6282665caeb7f06..d535edc01434117a8809fc21fb152226e0b46521 100644 (file)
@@ -514,7 +514,7 @@ int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 
        dvcpu->arch.wait = 0;
 
-       if (swait_active(&dvcpu->wq))
+       if (swq_has_sleeper(&dvcpu->wq))
                swake_up(&dvcpu->wq);
 
        return 0;
@@ -1179,7 +1179,7 @@ static void kvm_mips_comparecount_func(unsigned long data)
        kvm_mips_callbacks->queue_timer_int(vcpu);
 
        vcpu->arch.wait = 0;
-       if (swait_active(&vcpu->wq))
+       if (swq_has_sleeper(&vcpu->wq))
                swake_up(&vcpu->wq);
 }
 
index 31c51f9a2f0973c9d9ee38637ff00b988eb280a2..36ccdf05837dec19988d0be5206257d09a92ecd6 100644 (file)
        };
 
        chosen {
-               bootargs = "debug console=ttyJ0,115200";
+               bootargs = "debug earlycon console=ttyJ0,115200";
+               stdout-path = &jtag_uart;
        };
 };
index 645129aaa9a016b5e91b2ebc6e42e241ee00f72d..20e86209ef2e03646b49dd1f00324dae0ecedf72 100644 (file)
@@ -107,7 +107,10 @@ static struct nios2_clocksource nios2_cs = {
 
 cycles_t get_cycles(void)
 {
-       return nios2_timer_read(&nios2_cs.cs);
+       /* Only read timer if it has been initialized */
+       if (nios2_cs.timer.base)
+               return nios2_timer_read(&nios2_cs.cs);
+       return 0;
 }
 EXPORT_SYMBOL(get_cycles);
 
index 26b9994d27eef9c806b5c1f683f10325aff85d1c..43ef2515648098f985ff5f7d10a66b2f6d724391 100644 (file)
@@ -341,7 +341,7 @@ int fix_alignment(struct pt_regs *regs)
 
        type = op.type & INSTR_TYPE_MASK;
        if (!OP_IS_LOAD_STORE(type)) {
-               if (type != CACHEOP + DCBZ)
+               if (op.type != CACHEOP + DCBZ)
                        return -EINVAL;
                PPC_WARN_ALIGNMENT(dcbz, regs);
                r = emulate_dcbz(op.ea, regs);
index 18e974a34fced58328ecb062fee539279f3df7cd..73bf1ebfa78fcc7ef74dd51713d800ea12e9e745 100644 (file)
@@ -181,7 +181,7 @@ static void kvmppc_fast_vcpu_kick_hv(struct kvm_vcpu *vcpu)
        struct swait_queue_head *wqp;
 
        wqp = kvm_arch_vcpu_wq(vcpu);
-       if (swait_active(wqp)) {
+       if (swq_has_sleeper(wqp)) {
                swake_up(wqp);
                ++vcpu->stat.halt_wakeup;
        }
@@ -4212,11 +4212,13 @@ static int kvmhv_configure_mmu(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg)
        if ((cfg->process_table & PRTS_MASK) > 24)
                return -EINVAL;
 
+       mutex_lock(&kvm->lock);
        kvm->arch.process_table = cfg->process_table;
        kvmppc_setup_partition_table(kvm);
 
        lpcr = (cfg->flags & KVM_PPC_MMUV3_GTSE) ? LPCR_GTSE : 0;
        kvmppc_update_lpcr(kvm, lpcr, LPCR_GTSE);
+       mutex_unlock(&kvm->lock);
 
        return 0;
 }
index abf5f01b6eb1f04b05d0643ddc46bb8ded237d8f..5b81a807d742c8b11018ead176b60590064f5d7f 100644 (file)
@@ -38,7 +38,6 @@ static inline void __iomem *get_tima_phys(void)
 #define __x_tima               get_tima_phys()
 #define __x_eoi_page(xd)       ((void __iomem *)((xd)->eoi_page))
 #define __x_trig_page(xd)      ((void __iomem *)((xd)->trig_page))
-#define __x_readb      __raw_rm_readb
 #define __x_writeb     __raw_rm_writeb
 #define __x_readw      __raw_rm_readw
 #define __x_readq      __raw_rm_readq
index 663a4a861e7f3600903c61df65240fe32e58e5d3..17936f82d3c787c38327f41186f634d043d843a9 100644 (file)
@@ -771,6 +771,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 BEGIN_FTR_SECTION
+       /*
+        * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
+        */
        bl      kvmppc_restore_tm
 END_FTR_SECTION_IFSET(CPU_FTR_TM)
 #endif
@@ -1630,6 +1633,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 BEGIN_FTR_SECTION
+       /*
+        * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
+        */
        bl      kvmppc_save_tm
 END_FTR_SECTION_IFSET(CPU_FTR_TM)
 #endif
@@ -1749,7 +1755,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
        /*
         * Are we running hash or radix ?
         */
-       beq     cr2,3f
+       ld      r5, VCPU_KVM(r9)
+       lbz     r0, KVM_RADIX(r5)
+       cmpwi   cr2, r0, 0
+       beq     cr2, 3f
 
        /* Radix: Handle the case where the guest used an illegal PID */
        LOAD_REG_ADDR(r4, mmu_base_pid)
@@ -2466,6 +2475,9 @@ _GLOBAL(kvmppc_h_cede)            /* r3 = vcpu pointer, r11 = msr, r13 = paca */
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 BEGIN_FTR_SECTION
+       /*
+        * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
+        */
        ld      r9, HSTATE_KVM_VCPU(r13)
        bl      kvmppc_save_tm
 END_FTR_SECTION_IFSET(CPU_FTR_TM)
@@ -2578,6 +2590,9 @@ kvm_end_cede:
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 BEGIN_FTR_SECTION
+       /*
+        * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
+        */
        bl      kvmppc_restore_tm
 END_FTR_SECTION_IFSET(CPU_FTR_TM)
 #endif
index 08b200a0bbcec8c47a3128f4685ffcbfad261552..13304622ab1c78682fa18f06120f5eb0970f57fb 100644 (file)
@@ -48,7 +48,6 @@
 #define __x_tima               xive_tima
 #define __x_eoi_page(xd)       ((void __iomem *)((xd)->eoi_mmio))
 #define __x_trig_page(xd)      ((void __iomem *)((xd)->trig_mmio))
-#define __x_readb      __raw_readb
 #define __x_writeb     __raw_writeb
 #define __x_readw      __raw_readw
 #define __x_readq      __raw_readq
index d1ed2c41b5d246dde6d53c34530bc30dc63656b9..c7a5deadd1cc782ddd45667c9fc29f96166e85e7 100644 (file)
@@ -28,7 +28,8 @@ static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc)
         * bit.
         */
        if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
-               u8 pipr = __x_readb(__x_tima + TM_QW1_OS + TM_PIPR);
+               __be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
+               u8 pipr = be64_to_cpu(qw1) & 0xff;
                if (pipr >= xc->hw_cppr)
                        return;
        }
@@ -336,7 +337,6 @@ X_STATIC unsigned long GLUE(X_PFX,h_ipoll)(struct kvm_vcpu *vcpu, unsigned long
        struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
        u8 pending = xc->pending;
        u32 hirq;
-       u8 pipr;
 
        pr_devel("H_IPOLL(server=%ld)\n", server);
 
@@ -353,7 +353,8 @@ X_STATIC unsigned long GLUE(X_PFX,h_ipoll)(struct kvm_vcpu *vcpu, unsigned long
                pending = 0xff;
        } else {
                /* Grab pending interrupt if any */
-               pipr = __x_readb(__x_tima + TM_QW1_OS + TM_PIPR);
+               __be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
+               u8 pipr = be64_to_cpu(qw1) & 0xff;
                if (pipr < 8)
                        pending |= 1 << pipr;
        }
index 8844eee290b268b11a8404b1d3305551c6b98203..c73e493adf0748108c31389ca62437267ea877e2 100644 (file)
@@ -951,7 +951,6 @@ struct kvm_x86_ops {
        void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
        unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
        void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
-       u32 (*get_pkru)(struct kvm_vcpu *vcpu);
 
        void (*tlb_flush)(struct kvm_vcpu *vcpu);
 
@@ -973,7 +972,7 @@ struct kvm_x86_ops {
        void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
        void (*enable_irq_window)(struct kvm_vcpu *vcpu);
        void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
-       bool (*get_enable_apicv)(void);
+       bool (*get_enable_apicv)(struct kvm_vcpu *vcpu);
        void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
        void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
        void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr);
index 874827b0d7ca2e3a0f79d40ee7c2b9e84e9bb583..aa60a08b65b1090392b542ec7dc642e9827b7606 100644 (file)
@@ -180,7 +180,7 @@ static void apf_task_wake_one(struct kvm_task_sleep_node *n)
        hlist_del_init(&n->link);
        if (n->halted)
                smp_send_reschedule(n->cpu);
-       else if (swait_active(&n->wq))
+       else if (swq_has_sleeper(&n->wq))
                swake_up(&n->wq);
 }
 
index 1ea3c0e1e3a9a3df6d6061e1e367abf632c50b79..0bc5c1315708e6aad8b409d377be41e2291efb40 100644 (file)
@@ -59,7 +59,6 @@ static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned x86_feature)
 {
        unsigned x86_leaf = x86_feature / 32;
 
-       BUILD_BUG_ON(!__builtin_constant_p(x86_leaf));
        BUILD_BUG_ON(x86_leaf >= ARRAY_SIZE(reverse_cpuid));
        BUILD_BUG_ON(reverse_cpuid[x86_leaf].function == 0);
 
index aaf10b6f5380d6d41531b25365b433eac9d42c48..69c5612be786fbc7909b6f81a8d0a29f2cd324a6 100644 (file)
@@ -1324,6 +1324,10 @@ static void apic_timer_expired(struct kvm_lapic *apic)
        atomic_inc(&apic->lapic_timer.pending);
        kvm_set_pending_timer(vcpu);
 
+       /*
+        * For x86, the atomic_inc() is serialized, thus
+        * using swait_active() is safe.
+        */
        if (swait_active(q))
                swake_up(q);
 
index 2c1cfe68a9af1e11761f1938deea2d6d1fe51ab5..0e68f0b3cbf72064f36bfedcb997305fde124911 100644 (file)
@@ -1200,7 +1200,6 @@ static void avic_init_vmcb(struct vcpu_svm *svm)
        vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
        vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
        vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
-       svm->vcpu.arch.apicv_active = true;
 }
 
 static void init_vmcb(struct vcpu_svm *svm)
@@ -1316,7 +1315,7 @@ static void init_vmcb(struct vcpu_svm *svm)
                set_intercept(svm, INTERCEPT_PAUSE);
        }
 
-       if (avic)
+       if (kvm_vcpu_apicv_active(&svm->vcpu))
                avic_init_vmcb(svm);
 
        /*
@@ -1600,6 +1599,23 @@ static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
                avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
 }
 
+static int avic_init_vcpu(struct vcpu_svm *svm)
+{
+       int ret;
+
+       if (!kvm_vcpu_apicv_active(&svm->vcpu))
+               return 0;
+
+       ret = avic_init_backing_page(&svm->vcpu);
+       if (ret)
+               return ret;
+
+       INIT_LIST_HEAD(&svm->ir_list);
+       spin_lock_init(&svm->ir_list_lock);
+
+       return ret;
+}
+
 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 {
        struct vcpu_svm *svm;
@@ -1636,14 +1652,9 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
        if (!hsave_page)
                goto free_page3;
 
-       if (avic) {
-               err = avic_init_backing_page(&svm->vcpu);
-               if (err)
-                       goto free_page4;
-
-               INIT_LIST_HEAD(&svm->ir_list);
-               spin_lock_init(&svm->ir_list_lock);
-       }
+       err = avic_init_vcpu(svm);
+       if (err)
+               goto free_page4;
 
        /* We initialize this flag to true to make sure that the is_running
         * bit would be set the first time the vcpu is loaded.
@@ -4395,9 +4406,9 @@ static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
        return;
 }
 
-static bool svm_get_enable_apicv(void)
+static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
 {
-       return avic;
+       return avic && irqchip_split(vcpu->kvm);
 }
 
 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
@@ -4414,7 +4425,7 @@ static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
        struct vcpu_svm *svm = to_svm(vcpu);
        struct vmcb *vmcb = svm->vmcb;
 
-       if (!avic)
+       if (!kvm_vcpu_apicv_active(&svm->vcpu))
                return;
 
        vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
@@ -5302,6 +5313,7 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu,
                 */
                if (info->rep_prefix != REPE_PREFIX)
                        goto out;
+               break;
        case SVM_EXIT_IOIO: {
                u64 exit_info;
                u32 bytes;
index 699704d4bc9e7716e04da7298ec7f4491b436af1..06c0c6d0541e9bf95eabbcaa8d20c8ec45f19496 100644 (file)
@@ -5012,7 +5012,7 @@ static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_activ
        }
 }
 
-static bool vmx_get_enable_apicv(void)
+static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
 {
        return enable_apicv;
 }
@@ -8344,12 +8344,14 @@ static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
        struct vcpu_vmx *vmx = to_vmx(vcpu);
        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 
-       trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
-                               vmcs_readl(EXIT_QUALIFICATION),
-                               vmx->idt_vectoring_info,
-                               intr_info,
-                               vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
-                               KVM_ISA_VMX);
+       if (vmx->nested.nested_run_pending)
+               return false;
+
+       if (unlikely(vmx->fail)) {
+               pr_info_ratelimited("%s failed vm entry %x\n", __func__,
+                                   vmcs_read32(VM_INSTRUCTION_ERROR));
+               return true;
+       }
 
        /*
         * The host physical addresses of some pages of guest memory
@@ -8363,14 +8365,12 @@ static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
         */
        nested_mark_vmcs12_pages_dirty(vcpu);
 
-       if (vmx->nested.nested_run_pending)
-               return false;
-
-       if (unlikely(vmx->fail)) {
-               pr_info_ratelimited("%s failed vm entry %x\n", __func__,
-                                   vmcs_read32(VM_INSTRUCTION_ERROR));
-               return true;
-       }
+       trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
+                               vmcs_readl(EXIT_QUALIFICATION),
+                               vmx->idt_vectoring_info,
+                               intr_info,
+                               vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
+                               KVM_ISA_VMX);
 
        switch (exit_reason) {
        case EXIT_REASON_EXCEPTION_NMI:
@@ -9424,12 +9424,6 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
                                  | (1 << VCPU_EXREG_CR3));
        vcpu->arch.regs_dirty = 0;
 
-       vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
-
-       vmx->loaded_vmcs->launched = 1;
-
-       vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
-
        /*
         * eager fpu is enabled if PKEY is supported and CR4 is switched
         * back on host, so it is safe to read guest PKRU from current
@@ -9451,6 +9445,14 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
                kvm_make_request(KVM_REQ_EVENT, vcpu);
 
        vmx->nested.nested_run_pending = 0;
+       vmx->idt_vectoring_info = 0;
+
+       vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
+       if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
+               return;
+
+       vmx->loaded_vmcs->launched = 1;
+       vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
 
        vmx_complete_atomic_exit(vmx);
        vmx_recover_nmi_blocking(vmx);
@@ -10525,6 +10527,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
        if (exec_control & CPU_BASED_TPR_SHADOW) {
                vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
                vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
+       } else {
+#ifdef CONFIG_X86_64
+               exec_control |= CPU_BASED_CR8_LOAD_EXITING |
+                               CPU_BASED_CR8_STORE_EXITING;
+#endif
        }
 
        /*
@@ -11388,46 +11395,30 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
 {
        struct vcpu_vmx *vmx = to_vmx(vcpu);
        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-       u32 vm_inst_error = 0;
 
        /* trying to cancel vmlaunch/vmresume is a bug */
        WARN_ON_ONCE(vmx->nested.nested_run_pending);
 
+       /*
+        * The only expected VM-instruction error is "VM entry with
+        * invalid control field(s)." Anything else indicates a
+        * problem with L0.
+        */
+       WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
+                                  VMXERR_ENTRY_INVALID_CONTROL_FIELD));
+
        leave_guest_mode(vcpu);
-       prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
-                      exit_qualification);
 
-       if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
-                                vmcs12->vm_exit_msr_store_count))
-               nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
+       if (likely(!vmx->fail)) {
+               prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
+                              exit_qualification);
 
-       if (unlikely(vmx->fail))
-               vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
+               if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
+                                        vmcs12->vm_exit_msr_store_count))
+                       nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
+       }
 
        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
-
-       /*
-        * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
-        * the VM-exit interrupt information (valid interrupt) is always set to
-        * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
-        * kvm_cpu_has_interrupt().  See the commit message for details.
-        */
-       if (nested_exit_intr_ack_set(vcpu) &&
-           exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
-           kvm_cpu_has_interrupt(vcpu)) {
-               int irq = kvm_cpu_get_interrupt(vcpu);
-               WARN_ON(irq < 0);
-               vmcs12->vm_exit_intr_info = irq |
-                       INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
-       }
-
-       trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
-                                      vmcs12->exit_qualification,
-                                      vmcs12->idt_vectoring_info_field,
-                                      vmcs12->vm_exit_intr_info,
-                                      vmcs12->vm_exit_intr_error_code,
-                                      KVM_ISA_VMX);
-
        vm_entry_controls_reset_shadow(vmx);
        vm_exit_controls_reset_shadow(vmx);
        vmx_segment_cache_clear(vmx);
@@ -11436,8 +11427,6 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
        if (VMCS02_POOL_SIZE == 0)
                nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
 
-       load_vmcs12_host_state(vcpu, vmcs12);
-
        /* Update any VMCS fields that might have changed while L2 ran */
        vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
        vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
@@ -11486,21 +11475,57 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
         */
        kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
 
-       /*
-        * Exiting from L2 to L1, we're now back to L1 which thinks it just
-        * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
-        * success or failure flag accordingly.
-        */
-       if (unlikely(vmx->fail)) {
-               vmx->fail = 0;
-               nested_vmx_failValid(vcpu, vm_inst_error);
-       } else
-               nested_vmx_succeed(vcpu);
        if (enable_shadow_vmcs)
                vmx->nested.sync_shadow_vmcs = true;
 
        /* in case we halted in L2 */
        vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
+
+       if (likely(!vmx->fail)) {
+               /*
+                * TODO: SDM says that with acknowledge interrupt on
+                * exit, bit 31 of the VM-exit interrupt information
+                * (valid interrupt) is always set to 1 on
+                * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
+                * need kvm_cpu_has_interrupt().  See the commit
+                * message for details.
+                */
+               if (nested_exit_intr_ack_set(vcpu) &&
+                   exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
+                   kvm_cpu_has_interrupt(vcpu)) {
+                       int irq = kvm_cpu_get_interrupt(vcpu);
+                       WARN_ON(irq < 0);
+                       vmcs12->vm_exit_intr_info = irq |
+                               INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
+               }
+
+               trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
+                                              vmcs12->exit_qualification,
+                                              vmcs12->idt_vectoring_info_field,
+                                              vmcs12->vm_exit_intr_info,
+                                              vmcs12->vm_exit_intr_error_code,
+                                              KVM_ISA_VMX);
+
+               load_vmcs12_host_state(vcpu, vmcs12);
+
+               return;
+       }
+       
+       /*
+        * After an early L2 VM-entry failure, we're now back
+        * in L1 which thinks it just finished a VMLAUNCH or
+        * VMRESUME instruction, so we need to set the failure
+        * flag and the VM-instruction error field of the VMCS
+        * accordingly.
+        */
+       nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
+       /*
+        * The emulated instruction was already skipped in
+        * nested_vmx_run, but the updated RIP was never
+        * written back to the vmcs01.
+        */
+       skip_emulated_instruction(vcpu);
+       vmx->fail = 0;
 }
 
 /*
@@ -11829,7 +11854,7 @@ static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
        struct kvm_lapic_irq irq;
        struct kvm_vcpu *vcpu;
        struct vcpu_data vcpu_info;
-       int idx, ret = -EINVAL;
+       int idx, ret = 0;
 
        if (!kvm_arch_has_assigned_device(kvm) ||
                !irq_remapping_cap(IRQ_POSTING_CAP) ||
@@ -11838,7 +11863,12 @@ static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
 
        idx = srcu_read_lock(&kvm->irq_srcu);
        irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
-       BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
+       if (guest_irq >= irq_rt->nr_rt_entries ||
+           hlist_empty(&irq_rt->map[guest_irq])) {
+               pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
+                            guest_irq, irq_rt->nr_rt_entries);
+               goto out;
+       }
 
        hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
                if (e->type != KVM_IRQ_ROUTING_MSI)
index 6069af86da3b95884861f1e3a9f7d209ad729b3c..cd17b7d9a1076c1d28904bc4cd1ea06af5e0f2c0 100644 (file)
@@ -7231,10 +7231,19 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 
        if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
+               if (kvm_run->immediate_exit) {
+                       r = -EINTR;
+                       goto out;
+               }
                kvm_vcpu_block(vcpu);
                kvm_apic_accept_events(vcpu);
                kvm_clear_request(KVM_REQ_UNHALT, vcpu);
                r = -EAGAIN;
+               if (signal_pending(current)) {
+                       r = -EINTR;
+                       vcpu->run->exit_reason = KVM_EXIT_INTR;
+                       ++vcpu->stat.signal_exits;
+               }
                goto out;
        }
 
@@ -7971,7 +7980,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
        BUG_ON(vcpu->kvm == NULL);
        kvm = vcpu->kvm;
 
-       vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
+       vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
        vcpu->arch.pv.pv_unhalted = false;
        vcpu->arch.emulate_ctxt.ops = &emulate_ops;
        if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
@@ -8452,6 +8461,9 @@ static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
        if (vcpu->arch.pv.pv_unhalted)
                return true;
 
+       if (vcpu->arch.exception.pending)
+               return true;
+
        if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
            (vcpu->arch.nmi_pending &&
             kvm_x86_ops->nmi_allowed(vcpu)))
@@ -8619,6 +8631,13 @@ static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
                                      sizeof(val));
 }
 
+static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
+{
+
+       return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
+                                     sizeof(u32));
+}
+
 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
                                     struct kvm_async_pf *work)
 {
@@ -8646,6 +8665,7 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
                                 struct kvm_async_pf *work)
 {
        struct x86_exception fault;
+       u32 val;
 
        if (work->wakeup_all)
                work->arch.token = ~0; /* broadcast wakeup */
@@ -8653,15 +8673,26 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
                kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
        trace_kvm_async_pf_ready(work->arch.token, work->gva);
 
-       if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
-           !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
-               fault.vector = PF_VECTOR;
-               fault.error_code_valid = true;
-               fault.error_code = 0;
-               fault.nested_page_fault = false;
-               fault.address = work->arch.token;
-               fault.async_page_fault = true;
-               kvm_inject_page_fault(vcpu, &fault);
+       if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
+           !apf_get_user(vcpu, &val)) {
+               if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
+                   vcpu->arch.exception.pending &&
+                   vcpu->arch.exception.nr == PF_VECTOR &&
+                   !apf_put_user(vcpu, 0)) {
+                       vcpu->arch.exception.injected = false;
+                       vcpu->arch.exception.pending = false;
+                       vcpu->arch.exception.nr = 0;
+                       vcpu->arch.exception.has_error_code = false;
+                       vcpu->arch.exception.error_code = 0;
+               } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
+                       fault.vector = PF_VECTOR;
+                       fault.error_code_valid = true;
+                       fault.error_code = 0;
+                       fault.nested_page_fault = false;
+                       fault.address = work->arch.token;
+                       fault.async_page_fault = true;
+                       kvm_inject_page_fault(vcpu, &fault);
+               }
        }
        vcpu->arch.apf.halted = false;
        vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
index 12e71bbfd2228ebeaccd9188142c276653edb938..103635ab784c989945dc1dbcba616b0fe011c8da 100644 (file)
@@ -76,7 +76,7 @@
 extern int amdgpu_modeset;
 extern int amdgpu_vram_limit;
 extern int amdgpu_vis_vram_limit;
-extern unsigned amdgpu_gart_size;
+extern int amdgpu_gart_size;
 extern int amdgpu_gtt_size;
 extern int amdgpu_moverate;
 extern int amdgpu_benchmarking;
index fb6e5dbd5a03558d4ad06049b7fe581f18a801ec..309f2419c6d8aaed250f1fd2235cc45c3cdef1d7 100644 (file)
@@ -155,7 +155,6 @@ static const struct kfd2kgd_calls kfd2kgd = {
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 {
        return (struct kfd2kgd_calls *)&kfd2kgd;
-       return (struct kfd2kgd_calls *)&kfd2kgd;
 }
 
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
index 269b835571eb07f31093574fb86f662e93eb4c2d..60d8bedb694db733a707405a0b50da4fe0c0265c 100644 (file)
@@ -1079,6 +1079,9 @@ static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
                                             GFP_KERNEL);
        p->num_post_dep_syncobjs = 0;
 
+       if (!p->post_dep_syncobjs)
+               return -ENOMEM;
+
        for (i = 0; i < num_deps; ++i) {
                p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
                if (!p->post_dep_syncobjs[i])
@@ -1150,7 +1153,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
        cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
        job->uf_sequence = cs->out.handle;
        amdgpu_job_free_resources(job);
-       amdgpu_cs_parser_fini(p, 0, true);
 
        trace_amdgpu_cs_ioctl(job);
        amd_sched_entity_push_job(&job->base);
@@ -1208,10 +1210,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                goto out;
 
        r = amdgpu_cs_submit(&parser, cs);
-       if (r)
-               goto out;
 
-       return 0;
 out:
        amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
        return r;
index 1a459ac63df453b2cab796b8ed28fd4afff59522..e630d918fefc0993e540ac4ecb1734eeaaf3aec6 100644 (file)
@@ -1062,11 +1062,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
                amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
        }
 
-       if (amdgpu_gart_size < 32) {
+       if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
                /* gart size must be greater or equal to 32M */
                dev_warn(adev->dev, "gart size (%d) too small\n",
                         amdgpu_gart_size);
-               amdgpu_gart_size = 32;
+               amdgpu_gart_size = -1;
        }
 
        if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
@@ -2622,12 +2622,6 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
                        goto err;
                }
 
-               r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem);
-               if (r) {
-                       DRM_ERROR("%p bind failed\n", bo->shadow);
-                       goto err;
-               }
-
                r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
                                                 NULL, fence, true);
                if (r) {
index e39ec981b11c85d11ca6250caf2c4ab7de35fd97..0f16986ec5bc44356c19e9a7988a57e4b35f05bb 100644 (file)
@@ -76,7 +76,7 @@
 
 int amdgpu_vram_limit = 0;
 int amdgpu_vis_vram_limit = 0;
-unsigned amdgpu_gart_size = 256;
+int amdgpu_gart_size = -1; /* auto */
 int amdgpu_gtt_size = -1; /* auto */
 int amdgpu_moverate = -1; /* auto */
 int amdgpu_benchmarking = 0;
@@ -128,7 +128,7 @@ module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
-MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc.)");
+MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
index 94c1e2e8e34ca659717af06aa944c8e2675ba2a7..f4370081f6e60bafc3003e100e2eb41911d59951 100644 (file)
  * Common GART table functions.
  */
 
-/**
- * amdgpu_gart_set_defaults - set the default gart_size
- *
- * @adev: amdgpu_device pointer
- *
- * Set the default gart_size based on parameters and available VRAM.
- */
-void amdgpu_gart_set_defaults(struct amdgpu_device *adev)
-{
-       adev->mc.gart_size = (uint64_t)amdgpu_gart_size << 20;
-}
-
 /**
  * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
  *
index d4cce69362003241455a6d60bc57c3d648700fac..afbe803b1a13a93bce4d342d4c7f6bccce03c3aa 100644 (file)
@@ -56,7 +56,6 @@ struct amdgpu_gart {
        const struct amdgpu_gart_funcs *gart_funcs;
 };
 
-void amdgpu_gart_set_defaults(struct amdgpu_device *adev);
 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
index 9e05e257729f2e20dd91c4e81f6299e0800cc0e7..0d15eb7d31d7d0471b9253155c211bf5d3a641bc 100644 (file)
@@ -108,10 +108,10 @@ bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem)
  *
  * Allocate the address space for a node.
  */
-int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
-                        struct ttm_buffer_object *tbo,
-                        const struct ttm_place *place,
-                        struct ttm_mem_reg *mem)
+static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
+                               struct ttm_buffer_object *tbo,
+                               const struct ttm_place *place,
+                               struct ttm_mem_reg *mem)
 {
        struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
        struct amdgpu_gtt_mgr *mgr = man->priv;
@@ -143,12 +143,8 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
                                        fpfn, lpfn, mode);
        spin_unlock(&mgr->lock);
 
-       if (!r) {
+       if (!r)
                mem->start = node->start;
-               if (&tbo->mem == mem)
-                       tbo->offset = (tbo->mem.start << PAGE_SHIFT) +
-                           tbo->bdev->man[tbo->mem.mem_type].gpu_offset;
-       }
 
        return r;
 }
index 4bdd851f56d081310614f27dce5093255ecf7dfd..538e5f27d1205809ec293dee0aae8da5b5711e8b 100644 (file)
@@ -221,8 +221,9 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 
        spin_lock_init(&adev->irq.lock);
 
-       /* Disable vblank irqs aggressively for power-saving */
-       adev->ddev->vblank_disable_immediate = true;
+       if (!adev->enable_virtual_display)
+               /* Disable vblank irqs aggressively for power-saving */
+               adev->ddev->vblank_disable_immediate = true;
 
        r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
        if (r) {
index e7e899190befb9f74edd45a82eeefbed7529fde5..9e495da0bb03c8b4946aa84f1966a951c5639300 100644 (file)
@@ -91,7 +91,10 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 
        if (domain & AMDGPU_GEM_DOMAIN_GTT) {
                places[c].fpfn = 0;
-               places[c].lpfn = 0;
+               if (flags & AMDGPU_GEM_CREATE_SHADOW)
+                       places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT;
+               else
+                       places[c].lpfn = 0;
                places[c].flags = TTM_PL_FLAG_TT;
                if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
                        places[c].flags |= TTM_PL_FLAG_WC |
@@ -446,17 +449,16 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
        if (bo->shadow)
                return 0;
 
-       bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
-       memset(&placements, 0,
-              (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
-
-       amdgpu_ttm_placement_init(adev, &placement,
-                                 placements, AMDGPU_GEM_DOMAIN_GTT,
-                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC);
+       memset(&placements, 0, sizeof(placements));
+       amdgpu_ttm_placement_init(adev, &placement, placements,
+                                 AMDGPU_GEM_DOMAIN_GTT,
+                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+                                 AMDGPU_GEM_CREATE_SHADOW);
 
        r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
                                        AMDGPU_GEM_DOMAIN_GTT,
-                                       AMDGPU_GEM_CREATE_CPU_GTT_USWC,
+                                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+                                       AMDGPU_GEM_CREATE_SHADOW,
                                        NULL, &placement,
                                        bo->tbo.resv,
                                        0,
@@ -484,30 +486,28 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 {
        struct ttm_placement placement = {0};
        struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
+       uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
        int r;
 
-       memset(&placements, 0,
-              (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
+       memset(&placements, 0, sizeof(placements));
+       amdgpu_ttm_placement_init(adev, &placement, placements,
+                                 domain, parent_flags);
 
-       amdgpu_ttm_placement_init(adev, &placement,
-                                 placements, domain, flags);
-
-       r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
-                                       domain, flags, sg, &placement,
-                                       resv, init_value, bo_ptr);
+       r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, domain,
+                                       parent_flags, sg, &placement, resv,
+                                       init_value, bo_ptr);
        if (r)
                return r;
 
-       if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) {
-               if (!resv) {
-                       r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL);
-                       WARN_ON(r != 0);
-               }
+       if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
+               if (!resv)
+                       WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
+                                                       NULL));
 
                r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 
                if (!resv)
-                       ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock);
+                       reservation_object_unlock((*bo_ptr)->tbo.resv);
 
                if (r)
                        amdgpu_bo_unref(bo_ptr);
index 6c5646b48d1a5fce145df441ce66098ea62e95d8..5ce65280b3960fabc9a774184ba20d39481c3d98 100644 (file)
@@ -170,6 +170,16 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                     unsigned irq_type)
 {
        int r;
+       int sched_hw_submission = amdgpu_sched_hw_submission;
+
+       /* Set the hw submission limit higher for KIQ because
+        * it's used for a number of gfx/compute tasks by both
+        * KFD and KGD which may have outstanding fences and
+        * it doesn't really use the gpu scheduler anyway;
+        * KIQ tasks get submitted directly to the ring.
+        */
+       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+               sched_hw_submission = max(sched_hw_submission, 256);
 
        if (ring->adev == NULL) {
                if (adev->num_rings >= AMDGPU_MAX_RINGS)
@@ -178,8 +188,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                ring->adev = adev;
                ring->idx = adev->num_rings++;
                adev->rings[ring->idx] = ring;
-               r = amdgpu_fence_driver_init_ring(ring,
-                       amdgpu_sched_hw_submission);
+               r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
                if (r)
                        return r;
        }
@@ -218,8 +227,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                return r;
        }
 
-       ring->ring_size = roundup_pow_of_two(max_dw * 4 *
-                                            amdgpu_sched_hw_submission);
+       ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
 
        ring->buf_mask = (ring->ring_size / 4) - 1;
        ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
index 8b2c294f6f7999371a045aa985dd409ef12dd2d5..7ef6c28a34d991a2bba6f20224284072330c22d1 100644 (file)
@@ -761,35 +761,11 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
        sg_free_table(ttm->sg);
 }
 
-static int amdgpu_ttm_do_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
-{
-       struct amdgpu_ttm_tt *gtt = (void *)ttm;
-       uint64_t flags;
-       int r;
-
-       spin_lock(&gtt->adev->gtt_list_lock);
-       flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, mem);
-       gtt->offset = (u64)mem->start << PAGE_SHIFT;
-       r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
-               ttm->pages, gtt->ttm.dma_address, flags);
-
-       if (r) {
-               DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
-                         ttm->num_pages, gtt->offset);
-               goto error_gart_bind;
-       }
-
-       list_add_tail(&gtt->list, &gtt->adev->gtt_list);
-error_gart_bind:
-       spin_unlock(&gtt->adev->gtt_list_lock);
-       return r;
-
-}
-
 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
                                   struct ttm_mem_reg *bo_mem)
 {
        struct amdgpu_ttm_tt *gtt = (void*)ttm;
+       uint64_t flags;
        int r = 0;
 
        if (gtt->userptr) {
@@ -809,9 +785,24 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
            bo_mem->mem_type == AMDGPU_PL_OA)
                return -EINVAL;
 
-       if (amdgpu_gtt_mgr_is_allocated(bo_mem))
-           r = amdgpu_ttm_do_bind(ttm, bo_mem);
+       if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
+               return 0;
 
+       spin_lock(&gtt->adev->gtt_list_lock);
+       flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
+       gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
+       r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
+               ttm->pages, gtt->ttm.dma_address, flags);
+
+       if (r) {
+               DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
+                         ttm->num_pages, gtt->offset);
+               goto error_gart_bind;
+       }
+
+       list_add_tail(&gtt->list, &gtt->adev->gtt_list);
+error_gart_bind:
+       spin_unlock(&gtt->adev->gtt_list_lock);
        return r;
 }
 
@@ -824,20 +815,39 @@ bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 
 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 {
+       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
        struct ttm_tt *ttm = bo->ttm;
+       struct ttm_mem_reg tmp;
+
+       struct ttm_placement placement;
+       struct ttm_place placements;
        int r;
 
        if (!ttm || amdgpu_ttm_is_bound(ttm))
                return 0;
 
-       r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
-                                NULL, bo_mem);
-       if (r) {
-               DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
+       tmp = bo->mem;
+       tmp.mm_node = NULL;
+       placement.num_placement = 1;
+       placement.placement = &placements;
+       placement.num_busy_placement = 1;
+       placement.busy_placement = &placements;
+       placements.fpfn = 0;
+       placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
+       placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
+
+       r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
+       if (unlikely(r))
                return r;
-       }
 
-       return amdgpu_ttm_do_bind(ttm, bo_mem);
+       r = ttm_bo_move_ttm(bo, true, false, &tmp);
+       if (unlikely(r))
+               ttm_bo_mem_put(bo, &tmp);
+       else
+               bo->offset = (bo->mem.start << PAGE_SHIFT) +
+                       bo->bdev->man[bo->mem.mem_type].gpu_offset;
+
+       return r;
 }
 
 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
index f22a4758719da1121bd9368b857cb14fa42bb958..43093bffa2cfa8f2d3a81592acb138908089f53b 100644 (file)
@@ -62,10 +62,6 @@ extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
 extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
 
 bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem);
-int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
-                        struct ttm_buffer_object *tbo,
-                        const struct ttm_place *place,
-                        struct ttm_mem_reg *mem);
 uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
 
 uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
index b9a5a77eedaf00c339ef15faac6e1c4302053f2f..bd20ff018512271b79d9dac6c40b21693ea54f6b 100644 (file)
@@ -165,14 +165,6 @@ static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
        unsigned i;
        int r;
 
-       if (parent->bo->shadow) {
-               struct amdgpu_bo *shadow = parent->bo->shadow;
-
-               r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
-               if (r)
-                       return r;
-       }
-
        if (use_cpu_for_update) {
                r = amdgpu_bo_kmap(parent->bo, NULL);
                if (r)
@@ -1277,7 +1269,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
        /* In the case of a mixed PT the PDE must point to it*/
        if (p->adev->asic_type < CHIP_VEGA10 ||
            nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
-           p->func == amdgpu_vm_do_copy_ptes ||
+           p->src ||
            !(flags & AMDGPU_PTE_VALID)) {
 
                dst = amdgpu_bo_gpu_offset(entry->bo);
@@ -1294,9 +1286,23 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
        entry->addr = (dst | flags);
 
        if (use_cpu_update) {
+               /* In case a huge page is replaced with a system
+                * memory mapping, p->pages_addr != NULL and
+                * amdgpu_vm_cpu_set_ptes would try to translate dst
+                * through amdgpu_vm_map_gart. But dst is already a
+                * GPU address (of the page table). Disable
+                * amdgpu_vm_map_gart temporarily.
+                */
+               dma_addr_t *tmp;
+
+               tmp = p->pages_addr;
+               p->pages_addr = NULL;
+
                pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
                pde = pd_addr + (entry - parent->entries) * 8;
                amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
+
+               p->pages_addr = tmp;
        } else {
                if (parent->bo->shadow) {
                        pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
@@ -1610,7 +1616,6 @@ error_free:
  *
  * @adev: amdgpu_device pointer
  * @exclusive: fence we need to sync to
- * @gtt_flags: flags as they are used for GTT
  * @pages_addr: DMA addresses to use for mapping
  * @vm: requested vm
  * @mapping: mapped range and flags to use for the update
@@ -1624,7 +1629,6 @@ error_free:
  */
 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
                                      struct dma_fence *exclusive,
-                                     uint64_t gtt_flags,
                                      dma_addr_t *pages_addr,
                                      struct amdgpu_vm *vm,
                                      struct amdgpu_bo_va_mapping *mapping,
@@ -1679,11 +1683,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
                }
 
                if (pages_addr) {
-                       if (flags == gtt_flags)
-                               src = adev->gart.table_addr +
-                                       (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
-                       else
-                               max_entries = min(max_entries, 16ull * 1024ull);
+                       max_entries = min(max_entries, 16ull * 1024ull);
                        addr = 0;
                } else if (flags & AMDGPU_PTE_VALID) {
                        addr += adev->vm_manager.vram_base_offset;
@@ -1728,10 +1728,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        struct amdgpu_vm *vm = bo_va->base.vm;
        struct amdgpu_bo_va_mapping *mapping;
        dma_addr_t *pages_addr = NULL;
-       uint64_t gtt_flags, flags;
        struct ttm_mem_reg *mem;
        struct drm_mm_node *nodes;
        struct dma_fence *exclusive;
+       uint64_t flags;
        int r;
 
        if (clear || !bo_va->base.bo) {
@@ -1751,15 +1751,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
                exclusive = reservation_object_get_excl(bo->tbo.resv);
        }
 
-       if (bo) {
+       if (bo)
                flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-               gtt_flags = (amdgpu_ttm_is_bound(bo->tbo.ttm) &&
-                       adev == amdgpu_ttm_adev(bo->tbo.bdev)) ?
-                       flags : 0;
-       } else {
+       else
                flags = 0x0;
-               gtt_flags = ~0x0;
-       }
 
        spin_lock(&vm->status_lock);
        if (!list_empty(&bo_va->base.vm_status))
@@ -1767,8 +1762,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        spin_unlock(&vm->status_lock);
 
        list_for_each_entry(mapping, &bo_va->invalids, list) {
-               r = amdgpu_vm_bo_split_mapping(adev, exclusive,
-                                              gtt_flags, pages_addr, vm,
+               r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
                                               mapping, flags, nodes,
                                               &bo_va->last_pt_update);
                if (r)
index 832e592fcd0725b0f32406aec57d2fc466fe1179..fc260c13b1da4938443a972aecea21c2250d7e40 100644 (file)
@@ -4579,9 +4579,9 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
        mqd->compute_misc_reserved = 0x00000003;
        if (!(adev->flags & AMD_IS_APU)) {
                mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
-                                            + offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
+                                            + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
                mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
-                                            + offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
+                                            + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
        }
        eop_base_addr = ring->eop_gpu_addr >> 8;
        mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
@@ -4768,8 +4768,8 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
                mutex_unlock(&adev->srbm_mutex);
        } else {
                memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
-               ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
-               ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
                mutex_lock(&adev->srbm_mutex);
                vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
                gfx_v8_0_mqd_init(ring);
@@ -4792,8 +4792,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
 
        if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
                memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
-               ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
-               ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
                mutex_lock(&adev->srbm_mutex);
                vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
                gfx_v8_0_mqd_init(ring);
index 4f2788b61a08bd4db43d52d14ec9ab6e771b0e37..6c8040e616c4ed69f4f1addbf8282f2aea3ec81b 100644 (file)
@@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 
 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 {
-       uint32_t tmp, field;
+       uint32_t tmp;
 
        /* Setup L2 cache */
        tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
@@ -143,9 +143,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
        WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
 
-       field = adev->vm_manager.fragment_size;
        tmp = mmVM_L2_CNTL3_DEFAULT;
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
+       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
        WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 
index 12b0c4cd7a5af801b32dd29067cbba3ee88b2e08..5be9c83dfcf7d6b9ff169e5cb7b5fcde192b49cc 100644 (file)
@@ -332,7 +332,24 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
        adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
        adev->mc.visible_vram_size = adev->mc.aper_size;
 
-       amdgpu_gart_set_defaults(adev);
+       /* set the gart size */
+       if (amdgpu_gart_size == -1) {
+               switch (adev->asic_type) {
+               case CHIP_HAINAN:    /* no MM engines */
+               default:
+                       adev->mc.gart_size = 256ULL << 20;
+                       break;
+               case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
+               case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
+               case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
+               case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
+                       adev->mc.gart_size = 1024ULL << 20;
+                       break;
+               }
+       } else {
+               adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+       }
+
        gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 
        return 0;
index e42c1ad3af5e06c33a59939bc9abab48b2d9c406..eace9e7182c8a832d2b29984463f78fe05ca002c 100644 (file)
@@ -386,7 +386,27 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
        if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
                adev->mc.visible_vram_size = adev->mc.real_vram_size;
 
-       amdgpu_gart_set_defaults(adev);
+       /* set the gart size */
+       if (amdgpu_gart_size == -1) {
+               switch (adev->asic_type) {
+               case CHIP_TOPAZ:     /* no MM engines */
+               default:
+                       adev->mc.gart_size = 256ULL << 20;
+                       break;
+#ifdef CONFIG_DRM_AMDGPU_CIK
+               case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
+               case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
+               case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
+               case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
+               case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
+                       adev->mc.gart_size = 1024ULL << 20;
+                       break;
+#endif
+               }
+       } else {
+               adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+       }
+
        gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 
        return 0;
index 7ca2dae8237a0952da81414d5e14b53fa06e566e..3b3326daf32b9b09b25914a58d023b391ca8e52a 100644 (file)
@@ -562,7 +562,26 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
        if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
                adev->mc.visible_vram_size = adev->mc.real_vram_size;
 
-       amdgpu_gart_set_defaults(adev);
+       /* set the gart size */
+       if (amdgpu_gart_size == -1) {
+               switch (adev->asic_type) {
+               case CHIP_POLARIS11: /* all engines support GPUVM */
+               case CHIP_POLARIS10: /* all engines support GPUVM */
+               case CHIP_POLARIS12: /* all engines support GPUVM */
+               default:
+                       adev->mc.gart_size = 256ULL << 20;
+                       break;
+               case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
+               case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
+               case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
+               case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
+                       adev->mc.gart_size = 1024ULL << 20;
+                       break;
+               }
+       } else {
+               adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+       }
+
        gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 
        return 0;
index 2769c2b3b56e8f5ff8e8bbfa0f2cefe86569fe1f..d04d0b123212035a15f02c964a93271f4a8c64a1 100644 (file)
@@ -499,7 +499,21 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
        if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
                adev->mc.visible_vram_size = adev->mc.real_vram_size;
 
-       amdgpu_gart_set_defaults(adev);
+       /* set the gart size */
+       if (amdgpu_gart_size == -1) {
+               switch (adev->asic_type) {
+               case CHIP_VEGA10:  /* all engines support GPUVM */
+               default:
+                       adev->mc.gart_size = 256ULL << 20;
+                       break;
+               case CHIP_RAVEN:   /* DCE SG support */
+                       adev->mc.gart_size = 1024ULL << 20;
+                       break;
+               }
+       } else {
+               adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+       }
+
        gmc_v9_0_vram_gtt_location(adev, &adev->mc);
 
        return 0;
index 4395a4f12149c37db23404fa89077d783aa88c06..74cb647da30e08c28260937a2df7d02f13aeae9c 100644 (file)
@@ -138,7 +138,7 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 
 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 {
-       uint32_t tmp, field;
+       uint32_t tmp;
 
        /* Setup L2 cache */
        tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
@@ -157,9 +157,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
        WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 
-       field = adev->vm_manager.fragment_size;
        tmp = mmVM_L2_CNTL3_DEFAULT;
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
+       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
        WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 
index ca93b5160ba6cfb34b5cc4cc4f409bda66ba0a35..3e606a761d0e6466be9e40002e4fab09f2ca4a5c 100644 (file)
@@ -419,8 +419,8 @@ struct vi_mqd_allocation {
        struct vi_mqd mqd;
        uint32_t wptr_poll_mem;
        uint32_t rptr_report_mem;
-       uint32_t dyamic_cu_mask;
-       uint32_t dyamic_rb_mask;
+       uint32_t dynamic_cu_mask;
+       uint32_t dynamic_rb_mask;
 };
 
 struct cz_mqd {
index 9d71a259d97d46fc8008e288f71605f3cb5e23ff..f8f02e70b8bc06974b52dda715755de77aaaeae6 100644 (file)
@@ -1558,7 +1558,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
 */
 
 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
-               uint32_t gfx_clock, PllSetting_t *current_gfxclk_level)
+               uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
+               uint32_t *acg_freq)
 {
        struct phm_ppt_v2_information *table_info =
                        (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1609,6 +1610,8 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
                        cpu_to_le16(dividers.usPll_ss_slew_frac);
        current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
 
+       *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
+
        return 0;
 }
 
@@ -1689,7 +1692,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
        for (i = 0; i < dpm_table->count; i++) {
                result = vega10_populate_single_gfx_level(hwmgr,
                                dpm_table->dpm_levels[i].value,
-                               &(pp_table->GfxclkLevel[i]));
+                               &(pp_table->GfxclkLevel[i]),
+                               &(pp_table->AcgFreqTable[i]));
                if (result)
                        return result;
        }
@@ -1698,7 +1702,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
        while (i < NUM_GFXCLK_DPM_LEVELS) {
                result = vega10_populate_single_gfx_level(hwmgr,
                                dpm_table->dpm_levels[j].value,
-                               &(pp_table->GfxclkLevel[i]));
+                               &(pp_table->GfxclkLevel[i]),
+                               &(pp_table->AcgFreqTable[i]));
                if (result)
                        return result;
                i++;
index f6d6c61f796a463abfd8dfb2be0129c6c2579740..2818c98ff5ca907e317ec03c05e91fc4635554b4 100644 (file)
@@ -315,10 +315,12 @@ typedef struct {
   uint8_t      AcgEnable[NUM_GFXCLK_DPM_LEVELS];
   GbVdroopTable_t AcgBtcGbVdroopTable;
   QuadraticInt_t  AcgAvfsGb;
-  uint32_t     Reserved[4];
+
+  /* ACG Frequency Table, in Mhz */
+  uint32_t     AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];
 
   /* Padding - ignore */
-  uint32_t     MmHubPadding[7]; /* SMU internal use */
+  uint32_t     MmHubPadding[3]; /* SMU internal use */
 
 } PPTable_t;
 
index 76347ff6d6554b447e8e066c7ac81ef85562d4bc..c49a6f22002f77c9205d6e1973ee405e236f6008 100644 (file)
@@ -380,7 +380,8 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
                entry->num_register_entries = 0;
        }
 
-       if (fw_type == UCODE_ID_RLC_G)
+       if ((fw_type == UCODE_ID_RLC_G)
+               || (fw_type == UCODE_ID_CP_MEC))
                entry->flags = 1;
        else
                entry->flags = 0;
index 38cea6fb25a8b9221d64b43da04c4268a2c986b8..97c94f9683fa047392ba62f128586e0b7e4492bc 100644 (file)
@@ -205,17 +205,32 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
                           struct amd_sched_entity *entity)
 {
        struct amd_sched_rq *rq = entity->rq;
+       int r;
 
        if (!amd_sched_entity_is_initialized(sched, entity))
                return;
-
        /**
         * The client will not queue more IBs during this fini, consume existing
-        * queued IBs
+        * queued IBs or discard them on SIGKILL
        */
-       wait_event(sched->job_scheduled, amd_sched_entity_is_idle(entity));
-
+       if ((current->flags & PF_SIGNALED) && current->exit_code == SIGKILL)
+               r = -ERESTARTSYS;
+       else
+               r = wait_event_killable(sched->job_scheduled,
+                                       amd_sched_entity_is_idle(entity));
        amd_sched_rq_remove_entity(rq, entity);
+       if (r) {
+               struct amd_sched_job *job;
+
+               /* Park the kernel for a moment to make sure it isn't processing
+                * our enity.
+                */
+               kthread_park(sched->thread);
+               kthread_unpark(sched->thread);
+               while (kfifo_out(&entity->job_queue, &job, sizeof(job)))
+                       sched->ops->free_job(job);
+
+       }
        kfifo_free(&entity->job_queue);
 }
 
index cba11f13d994fbb9b51ee99d8beac08cac26d8fe..180ce629641618adb2ec001ce0c25a563502da0e 100644 (file)
@@ -109,8 +109,8 @@ static ssize_t ttm_bo_global_show(struct kobject *kobj,
        struct ttm_bo_global *glob =
                container_of(kobj, struct ttm_bo_global, kobj);
 
-       return snprintf(buffer, PAGE_SIZE, "%lu\n",
-                       (unsigned long) atomic_read(&glob->bo_count));
+       return snprintf(buffer, PAGE_SIZE, "%d\n",
+                               atomic_read(&glob->bo_count));
 }
 
 static struct attribute *ttm_bo_global_attrs[] = {
index d0459b392e5eb07324b2ad9e9f77f4a7a6f278cb..c934ad5b39036c6de16265e8c2e9cbf61873d6fe 100644 (file)
@@ -469,6 +469,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
         * TODO: Explicit member copy would probably be better here.
         */
 
+       atomic_inc(&bo->glob->bo_count);
        INIT_LIST_HEAD(&fbo->ddestroy);
        INIT_LIST_HEAD(&fbo->lru);
        INIT_LIST_HEAD(&fbo->swap);
index edc0cfb6fc1ad550750eaf4f0058ca884828f4fb..c06dce2c1da745fab9727715f5ffaa01a40d4d04 100644 (file)
@@ -336,6 +336,16 @@ config I2C_POWERMAC
 
 comment "I2C system bus drivers (mostly embedded / system-on-chip)"
 
+config I2C_ALTERA
+       tristate "Altera Soft IP I2C"
+       depends on (ARCH_SOCFPGA || NIOS2) && OF
+       help
+         If you say yes to this option, support will be included for the
+         Altera Soft IP I2C interfaces on SoCFPGA and Nios2 architectures.
+
+         This driver can also be built as a module.  If so, the module
+         will be called i2c-altera.
+
 config I2C_ASPEED
        tristate "Aspeed I2C Controller"
        depends on ARCH_ASPEED || COMPILE_TEST
@@ -935,6 +945,16 @@ config I2C_STM32F4
          This driver can also be built as module. If so, the module
          will be called i2c-stm32f4.
 
+config I2C_STM32F7
+       tristate "STMicroelectronics STM32F7 I2C support"
+       depends on ARCH_STM32 || COMPILE_TEST
+       help
+         Enable this option to add support for STM32 I2C controller embedded
+         in STM32F7 SoCs.
+
+         This driver can also be built as module. If so, the module
+         will be called i2c-stm32f7.
+
 config I2C_STU300
        tristate "ST Microelectronics DDC I2C interface"
        depends on MACH_U300
index 562daf738048610c57585514f3c2646a5a5f3619..47f3ac9a695ad21066fc5ab47df40a564913e024 100644 (file)
@@ -30,6 +30,7 @@ obj-$(CONFIG_I2C_HYDRA)               += i2c-hydra.o
 obj-$(CONFIG_I2C_POWERMAC)     += i2c-powermac.o
 
 # Embedded system I2C/SMBus host controller drivers
+obj-$(CONFIG_I2C_ALTERA)       += i2c-altera.o
 obj-$(CONFIG_I2C_ASPEED)       += i2c-aspeed.o
 obj-$(CONFIG_I2C_AT91)         += i2c-at91.o
 obj-$(CONFIG_I2C_AU1550)       += i2c-au1550.o
@@ -93,6 +94,7 @@ obj-$(CONFIG_I2C_SIRF)                += i2c-sirf.o
 obj-$(CONFIG_I2C_SPRD)         += i2c-sprd.o
 obj-$(CONFIG_I2C_ST)           += i2c-st.o
 obj-$(CONFIG_I2C_STM32F4)      += i2c-stm32f4.o
+obj-$(CONFIG_I2C_STM32F7)      += i2c-stm32f7.o
 obj-$(CONFIG_I2C_STU300)       += i2c-stu300.o
 obj-$(CONFIG_I2C_SUN6I_P2WI)   += i2c-sun6i-p2wi.o
 obj-$(CONFIG_I2C_TEGRA)                += i2c-tegra.o
diff --git a/drivers/i2c/busses/i2c-altera.c b/drivers/i2c/busses/i2c-altera.c
new file mode 100644 (file)
index 0000000..f5e1941
--- /dev/null
@@ -0,0 +1,511 @@
+/*
+ *  Copyright Intel Corporation (C) 2017.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Based on the i2c-axxia.c driver.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#define ALTR_I2C_TFR_CMD       0x00    /* Transfer Command register */
+#define     ALTR_I2C_TFR_CMD_STA       BIT(9)  /* send START before byte */
+#define     ALTR_I2C_TFR_CMD_STO       BIT(8)  /* send STOP after byte */
+#define     ALTR_I2C_TFR_CMD_RW_D      BIT(0)  /* Direction of transfer */
+#define ALTR_I2C_RX_DATA       0x04    /* RX data FIFO register */
+#define ALTR_I2C_CTRL          0x08    /* Control register */
+#define     ALTR_I2C_CTRL_RXT_SHFT     4       /* RX FIFO Threshold */
+#define     ALTR_I2C_CTRL_TCT_SHFT     2       /* TFER CMD FIFO Threshold */
+#define     ALTR_I2C_CTRL_BSPEED       BIT(1)  /* Bus Speed (1=Fast) */
+#define     ALTR_I2C_CTRL_EN   BIT(0)  /* Enable Core (1=Enable) */
+#define ALTR_I2C_ISER          0x0C    /* Interrupt Status Enable register */
+#define     ALTR_I2C_ISER_RXOF_EN      BIT(4)  /* Enable RX OVERFLOW IRQ */
+#define     ALTR_I2C_ISER_ARB_EN       BIT(3)  /* Enable ARB LOST IRQ */
+#define     ALTR_I2C_ISER_NACK_EN      BIT(2)  /* Enable NACK DET IRQ */
+#define     ALTR_I2C_ISER_RXRDY_EN     BIT(1)  /* Enable RX Ready IRQ */
+#define     ALTR_I2C_ISER_TXRDY_EN     BIT(0)  /* Enable TX Ready IRQ */
+#define ALTR_I2C_ISR           0x10    /* Interrupt Status register */
+#define     ALTR_I2C_ISR_RXOF          BIT(4)  /* RX OVERFLOW IRQ */
+#define     ALTR_I2C_ISR_ARB           BIT(3)  /* ARB LOST IRQ */
+#define     ALTR_I2C_ISR_NACK          BIT(2)  /* NACK DET IRQ */
+#define     ALTR_I2C_ISR_RXRDY         BIT(1)  /* RX Ready IRQ */
+#define     ALTR_I2C_ISR_TXRDY         BIT(0)  /* TX Ready IRQ */
+#define ALTR_I2C_STATUS                0x14    /* Status register */
+#define     ALTR_I2C_STAT_CORE         BIT(0)  /* Core Status (0=idle) */
+#define ALTR_I2C_TC_FIFO_LVL   0x18    /* Transfer FIFO LVL register */
+#define ALTR_I2C_RX_FIFO_LVL   0x1C    /* Receive FIFO LVL register */
+#define ALTR_I2C_SCL_LOW       0x20    /* SCL low count register */
+#define ALTR_I2C_SCL_HIGH      0x24    /* SCL high count register */
+#define ALTR_I2C_SDA_HOLD      0x28    /* SDA hold count register */
+
+#define ALTR_I2C_ALL_IRQ       (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
+                                ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
+                                ALTR_I2C_ISR_TXRDY)
+
+#define ALTR_I2C_THRESHOLD     0       /* IRQ Threshold at 1 element */
+#define ALTR_I2C_DFLT_FIFO_SZ  4
+#define ALTR_I2C_TIMEOUT       100000  /* 100ms */
+#define ALTR_I2C_XFER_TIMEOUT  (msecs_to_jiffies(250))
+
+/**
+ * altr_i2c_dev - I2C device context
+ * @base: pointer to register struct
+ * @msg: pointer to current message
+ * @msg_len: number of bytes transferred in msg
+ * @msg_err: error code for completed message
+ * @msg_complete: xfer completion object
+ * @dev: device reference
+ * @adapter: core i2c abstraction
+ * @i2c_clk: clock reference for i2c input clock
+ * @bus_clk_rate: current i2c bus clock rate
+ * @buf: ptr to msg buffer for easier use.
+ * @fifo_size: size of the FIFO passed in.
+ * @isr_mask: cached copy of local ISR enables.
+ * @isr_status: cached copy of local ISR status.
+ * @lock: spinlock for IRQ synchronization.
+ */
+struct altr_i2c_dev {
+       void __iomem *base;
+       struct i2c_msg *msg;
+       size_t msg_len;
+       int msg_err;
+       struct completion msg_complete;
+       struct device *dev;
+       struct i2c_adapter adapter;
+       struct clk *i2c_clk;
+       u32 bus_clk_rate;
+       u8 *buf;
+       u32 fifo_size;
+       u32 isr_mask;
+       u32 isr_status;
+       spinlock_t lock;        /* IRQ synchronization */
+};
+
+static void
+altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
+{
+       unsigned long flags;
+       u32 int_en;
+
+       spin_lock_irqsave(&idev->lock, flags);
+
+       int_en = readl(idev->base + ALTR_I2C_ISER);
+       if (enable)
+               idev->isr_mask = int_en | mask;
+       else
+               idev->isr_mask = int_en & ~mask;
+
+       writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
+
+       spin_unlock_irqrestore(&idev->lock, flags);
+}
+
+static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
+{
+       u32 int_en = readl(idev->base + ALTR_I2C_ISR);
+
+       writel(int_en | mask, idev->base + ALTR_I2C_ISR);
+}
+
+static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
+{
+       u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
+
+       writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
+}
+
+static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
+{
+       u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
+
+       writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
+}
+
+static void altr_i2c_reset(struct altr_i2c_dev *idev)
+{
+       altr_i2c_core_disable(idev);
+       altr_i2c_core_enable(idev);
+}
+
+static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
+{
+       writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
+}
+
+static void altr_i2c_init(struct altr_i2c_dev *idev)
+{
+       u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
+       u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
+       u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
+                 (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
+       u32 t_high, t_low;
+
+       if (idev->bus_clk_rate <= 100000) {
+               tmp &= ~ALTR_I2C_CTRL_BSPEED;
+               /* Standard mode SCL 50/50 */
+               t_high = divisor * 1 / 2;
+               t_low = divisor * 1 / 2;
+       } else {
+               tmp |= ALTR_I2C_CTRL_BSPEED;
+               /* Fast mode SCL 33/66 */
+               t_high = divisor * 1 / 3;
+               t_low = divisor * 2 / 3;
+       }
+       writel(tmp, idev->base + ALTR_I2C_CTRL);
+
+       dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
+               idev->bus_clk_rate, clk_mhz, divisor);
+
+       /* Reset controller */
+       altr_i2c_reset(idev);
+
+       /* SCL High Time */
+       writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
+       /* SCL Low Time */
+       writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
+       /* SDA Hold Time, 300ns */
+       writel(div_u64(300 * clk_mhz, 1000), idev->base + ALTR_I2C_SDA_HOLD);
+
+       /* Mask all master interrupt bits */
+       altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
+}
+
+/**
+ * altr_i2c_transfer - On the last byte to be transmitted, send
+ * a Stop bit on the last byte.
+ */
+static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
+{
+       /* On the last byte to be transmitted, send STOP */
+       if (idev->msg_len == 1)
+               data |= ALTR_I2C_TFR_CMD_STO;
+       if (idev->msg_len > 0)
+               writel(data, idev->base + ALTR_I2C_TFR_CMD);
+}
+
+/**
+ * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
+ * transfer. Send a Stop bit on the last byte.
+ */
+static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
+{
+       size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
+       int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
+
+       while (bytes_to_transfer-- > 0) {
+               *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
+               idev->msg_len--;
+               altr_i2c_transfer(idev, 0);
+       }
+}
+
+/**
+ * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
+ * @return: Number of bytes left to transfer.
+ */
+static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
+{
+       size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
+                                                      ALTR_I2C_TC_FIFO_LVL);
+       int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
+       int ret = idev->msg_len - bytes_to_transfer;
+
+       while (bytes_to_transfer-- > 0) {
+               altr_i2c_transfer(idev, *idev->buf++);
+               idev->msg_len--;
+       }
+
+       return ret;
+}
+
+static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
+{
+       struct altr_i2c_dev *idev = _dev;
+       irqreturn_t ret = IRQ_HANDLED;
+
+       /* Read IRQ status but only interested in Enabled IRQs. */
+       idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
+       if (idev->isr_status)
+               ret = IRQ_WAKE_THREAD;
+
+       return ret;
+}
+
+static irqreturn_t altr_i2c_isr(int irq, void *_dev)
+{
+       int ret;
+       bool read, finish = false;
+       struct altr_i2c_dev *idev = _dev;
+       u32 status = idev->isr_status;
+
+       if (!idev->msg) {
+               dev_warn(idev->dev, "unexpected interrupt\n");
+               altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
+               return IRQ_HANDLED;
+       }
+       read = (idev->msg->flags & I2C_M_RD) != 0;
+
+       /* handle Lost Arbitration */
+       if (unlikely(status & ALTR_I2C_ISR_ARB)) {
+               altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
+               idev->msg_err = -EAGAIN;
+               finish = true;
+       } else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
+               dev_dbg(idev->dev, "Could not get ACK\n");
+               idev->msg_err = -ENXIO;
+               altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
+               altr_i2c_stop(idev);
+               finish = true;
+       } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
+               /* handle RX FIFO Overflow */
+               altr_i2c_empty_rx_fifo(idev);
+               altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
+               altr_i2c_stop(idev);
+               dev_err(idev->dev, "RX FIFO Overflow\n");
+               finish = true;
+       } else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
+               /* RX FIFO needs service? */
+               altr_i2c_empty_rx_fifo(idev);
+               altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
+               if (!idev->msg_len)
+                       finish = true;
+       } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
+               /* TX FIFO needs service? */
+               altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
+               if (idev->msg_len > 0)
+                       altr_i2c_fill_tx_fifo(idev);
+               else
+                       finish = true;
+       } else {
+               dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
+               altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
+       }
+
+       if (finish) {
+               /* Wait for the Core to finish */
+               ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
+                                               status,
+                                               !(status & ALTR_I2C_STAT_CORE),
+                                               1, ALTR_I2C_TIMEOUT);
+               if (ret)
+                       dev_err(idev->dev, "message timeout\n");
+               altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
+               altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
+               complete(&idev->msg_complete);
+               dev_dbg(idev->dev, "Message Complete\n");
+       }
+
+       return IRQ_HANDLED;
+}
+
+static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
+{
+       u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
+       unsigned long time_left;
+       u32 value;
+       u8 addr = i2c_8bit_addr_from_msg(msg);
+
+       idev->msg = msg;
+       idev->msg_len = msg->len;
+       idev->buf = msg->buf;
+       idev->msg_err = 0;
+       reinit_completion(&idev->msg_complete);
+       altr_i2c_core_enable(idev);
+
+       /* Make sure RX FIFO is empty */
+       do {
+               readl(idev->base + ALTR_I2C_RX_DATA);
+       } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
+
+       writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
+
+       if ((msg->flags & I2C_M_RD) != 0) {
+               imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
+               altr_i2c_int_enable(idev, imask, true);
+               /* write the first byte to start the RX */
+               altr_i2c_transfer(idev, 0);
+       } else {
+               imask |= ALTR_I2C_ISR_TXRDY;
+               altr_i2c_int_enable(idev, imask, true);
+               altr_i2c_fill_tx_fifo(idev);
+       }
+
+       time_left = wait_for_completion_timeout(&idev->msg_complete,
+                                               ALTR_I2C_XFER_TIMEOUT);
+       altr_i2c_int_enable(idev, imask, false);
+
+       value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
+       if (value)
+               dev_err(idev->dev, "Core Status not IDLE...\n");
+
+       if (time_left == 0) {
+               idev->msg_err = -ETIMEDOUT;
+               dev_dbg(idev->dev, "Transaction timed out.\n");
+       }
+
+       altr_i2c_core_disable(idev);
+
+       return idev->msg_err;
+}
+
+static int
+altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+{
+       struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
+       int i, ret;
+
+       for (i = 0; i < num; i++) {
+               ret = altr_i2c_xfer_msg(idev, msgs++);
+               if (ret)
+                       return ret;
+       }
+       return num;
+}
+
+static u32 altr_i2c_func(struct i2c_adapter *adap)
+{
+       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm altr_i2c_algo = {
+       .master_xfer = altr_i2c_xfer,
+       .functionality = altr_i2c_func,
+};
+
+static int altr_i2c_probe(struct platform_device *pdev)
+{
+       struct altr_i2c_dev *idev = NULL;
+       struct resource *res;
+       int irq, ret;
+       u32 val;
+
+       idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
+       if (!idev)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       idev->base = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(idev->base))
+               return PTR_ERR(idev->base);
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(&pdev->dev, "missing interrupt resource\n");
+               return irq;
+       }
+
+       idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
+       if (IS_ERR(idev->i2c_clk)) {
+               dev_err(&pdev->dev, "missing clock\n");
+               return PTR_ERR(idev->i2c_clk);
+       }
+
+       idev->dev = &pdev->dev;
+       init_completion(&idev->msg_complete);
+       spin_lock_init(&idev->lock);
+
+       val = device_property_read_u32(idev->dev, "fifo-size",
+                                      &idev->fifo_size);
+       if (val) {
+               dev_err(&pdev->dev, "FIFO size set to default of %d\n",
+                       ALTR_I2C_DFLT_FIFO_SZ);
+               idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
+       }
+
+       val = device_property_read_u32(idev->dev, "clock-frequency",
+                                      &idev->bus_clk_rate);
+       if (val) {
+               dev_err(&pdev->dev, "Default to 100kHz\n");
+               idev->bus_clk_rate = 100000;    /* default clock rate */
+       }
+
+       if (idev->bus_clk_rate > 400000) {
+               dev_err(&pdev->dev, "invalid clock-frequency %d\n",
+                       idev->bus_clk_rate);
+               return -EINVAL;
+       }
+
+       ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
+                                       altr_i2c_isr, IRQF_ONESHOT,
+                                       pdev->name, idev);
+       if (ret) {
+               dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
+               return ret;
+       }
+
+       ret = clk_prepare_enable(idev->i2c_clk);
+       if (ret) {
+               dev_err(&pdev->dev, "failed to enable clock\n");
+               return ret;
+       }
+
+       altr_i2c_init(idev);
+
+       i2c_set_adapdata(&idev->adapter, idev);
+       strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
+       idev->adapter.owner = THIS_MODULE;
+       idev->adapter.algo = &altr_i2c_algo;
+       idev->adapter.dev.parent = &pdev->dev;
+       idev->adapter.dev.of_node = pdev->dev.of_node;
+
+       platform_set_drvdata(pdev, idev);
+
+       ret = i2c_add_adapter(&idev->adapter);
+       if (ret) {
+               clk_disable_unprepare(idev->i2c_clk);
+               return ret;
+       }
+       dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
+
+       return 0;
+}
+
+static int altr_i2c_remove(struct platform_device *pdev)
+{
+       struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
+
+       clk_disable_unprepare(idev->i2c_clk);
+       i2c_del_adapter(&idev->adapter);
+
+       return 0;
+}
+
+/* Match table for of_platform binding */
+static const struct of_device_id altr_i2c_of_match[] = {
+       { .compatible = "altr,softip-i2c-v1.0" },
+       {},
+};
+MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
+
+static struct platform_driver altr_i2c_driver = {
+       .probe = altr_i2c_probe,
+       .remove = altr_i2c_remove,
+       .driver = {
+               .name = "altera-i2c",
+               .of_match_table = altr_i2c_of_match,
+       },
+};
+
+module_platform_driver(altr_i2c_driver);
+
+MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
+MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-stm32.h b/drivers/i2c/busses/i2c-stm32.h
new file mode 100644 (file)
index 0000000..dab5176
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * i2c-stm32.h
+ *
+ * Copyright (C) M'boumba Cedric Madianga 2017
+ * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#ifndef _I2C_STM32_H
+#define _I2C_STM32_H
+
+enum stm32_i2c_speed {
+       STM32_I2C_SPEED_STANDARD, /* 100 kHz */
+       STM32_I2C_SPEED_FAST, /* 400 kHz */
+       STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
+       STM32_I2C_SPEED_END,
+};
+
+#endif /* _I2C_STM32_H */
index aceb6f7885641f254ee09f23af32db627089c0d7..4ec108496f15cdf5dcedd3bad1b368cac5482bd8 100644 (file)
@@ -27,6 +27,8 @@
 #include <linux/platform_device.h>
 #include <linux/reset.h>
 
+#include "i2c-stm32.h"
+
 /* STM32F4 I2C offset registers */
 #define STM32F4_I2C_CR1                        0x00
 #define STM32F4_I2C_CR2                        0x04
 #define STM32F4_I2C_MAX_FREQ           46U
 #define HZ_TO_MHZ                      1000000
 
-enum stm32f4_i2c_speed {
-       STM32F4_I2C_SPEED_STANDARD, /* 100 kHz */
-       STM32F4_I2C_SPEED_FAST, /* 400 kHz */
-       STM32F4_I2C_SPEED_END,
-};
-
 /**
  * struct stm32f4_i2c_msg - client specific data
  * @addr: 8-bit slave addr, including r/w bit
@@ -159,7 +155,7 @@ static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
        i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
        freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
 
-       if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) {
+       if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
                /*
                 * To reach 100 kHz, the parent clk frequency should be between
                 * a minimum value of 2 MHz and a maximum value of 46 MHz due
@@ -216,7 +212,7 @@ static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
         * is not higher than 46 MHz . As a result trise is at most 4 bits wide
         * and so fits into the TRISE bits [5:0].
         */
-       if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD)
+       if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD)
                trise = freq + 1;
        else
                trise = freq * 3 / 10 + 1;
@@ -230,7 +226,7 @@ static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
        u32 val;
        u32 ccr = 0;
 
-       if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) {
+       if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
                /*
                 * In standard mode:
                 * t_scl_high = t_scl_low = CCR * I2C parent clk period
@@ -808,10 +804,10 @@ static int stm32f4_i2c_probe(struct platform_device *pdev)
        udelay(2);
        reset_control_deassert(rst);
 
-       i2c_dev->speed = STM32F4_I2C_SPEED_STANDARD;
+       i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
        ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
        if (!ret && clk_rate >= 400000)
-               i2c_dev->speed = STM32F4_I2C_SPEED_FAST;
+               i2c_dev->speed = STM32_I2C_SPEED_FAST;
 
        i2c_dev->dev = &pdev->dev;
 
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
new file mode 100644 (file)
index 0000000..47c67b0
--- /dev/null
@@ -0,0 +1,972 @@
+/*
+ * Driver for STMicroelectronics STM32F7 I2C controller
+ *
+ * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
+ * reference manual.
+ * Please see below a link to the documentation:
+ * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
+ *
+ * Copyright (C) M'boumba Cedric Madianga 2017
+ * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
+ *
+ * This driver is based on i2c-stm32f4.c
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include "i2c-stm32.h"
+
+/* STM32F7 I2C registers */
+#define STM32F7_I2C_CR1                                0x00
+#define STM32F7_I2C_CR2                                0x04
+#define STM32F7_I2C_TIMINGR                    0x10
+#define STM32F7_I2C_ISR                                0x18
+#define STM32F7_I2C_ICR                                0x1C
+#define STM32F7_I2C_RXDR                       0x24
+#define STM32F7_I2C_TXDR                       0x28
+
+/* STM32F7 I2C control 1 */
+#define STM32F7_I2C_CR1_ANFOFF                 BIT(12)
+#define STM32F7_I2C_CR1_ERRIE                  BIT(7)
+#define STM32F7_I2C_CR1_TCIE                   BIT(6)
+#define STM32F7_I2C_CR1_STOPIE                 BIT(5)
+#define STM32F7_I2C_CR1_NACKIE                 BIT(4)
+#define STM32F7_I2C_CR1_ADDRIE                 BIT(3)
+#define STM32F7_I2C_CR1_RXIE                   BIT(2)
+#define STM32F7_I2C_CR1_TXIE                   BIT(1)
+#define STM32F7_I2C_CR1_PE                     BIT(0)
+#define STM32F7_I2C_ALL_IRQ_MASK               (STM32F7_I2C_CR1_ERRIE \
+                                               | STM32F7_I2C_CR1_TCIE \
+                                               | STM32F7_I2C_CR1_STOPIE \
+                                               | STM32F7_I2C_CR1_NACKIE \
+                                               | STM32F7_I2C_CR1_RXIE \
+                                               | STM32F7_I2C_CR1_TXIE)
+
+/* STM32F7 I2C control 2 */
+#define STM32F7_I2C_CR2_RELOAD                 BIT(24)
+#define STM32F7_I2C_CR2_NBYTES_MASK            GENMASK(23, 16)
+#define STM32F7_I2C_CR2_NBYTES(n)              (((n) & 0xff) << 16)
+#define STM32F7_I2C_CR2_NACK                   BIT(15)
+#define STM32F7_I2C_CR2_STOP                   BIT(14)
+#define STM32F7_I2C_CR2_START                  BIT(13)
+#define STM32F7_I2C_CR2_RD_WRN                 BIT(10)
+#define STM32F7_I2C_CR2_SADD7_MASK             GENMASK(7, 1)
+#define STM32F7_I2C_CR2_SADD7(n)               (((n) & 0x7f) << 1)
+
+/* STM32F7 I2C Interrupt Status */
+#define STM32F7_I2C_ISR_BUSY                   BIT(15)
+#define STM32F7_I2C_ISR_ARLO                   BIT(9)
+#define STM32F7_I2C_ISR_BERR                   BIT(8)
+#define STM32F7_I2C_ISR_TCR                    BIT(7)
+#define STM32F7_I2C_ISR_TC                     BIT(6)
+#define STM32F7_I2C_ISR_STOPF                  BIT(5)
+#define STM32F7_I2C_ISR_NACKF                  BIT(4)
+#define STM32F7_I2C_ISR_RXNE                   BIT(2)
+#define STM32F7_I2C_ISR_TXIS                   BIT(1)
+
+/* STM32F7 I2C Interrupt Clear */
+#define STM32F7_I2C_ICR_ARLOCF                 BIT(9)
+#define STM32F7_I2C_ICR_BERRCF                 BIT(8)
+#define STM32F7_I2C_ICR_STOPCF                 BIT(5)
+#define STM32F7_I2C_ICR_NACKCF                 BIT(4)
+
+/* STM32F7 I2C Timing */
+#define STM32F7_I2C_TIMINGR_PRESC(n)           (((n) & 0xf) << 28)
+#define STM32F7_I2C_TIMINGR_SCLDEL(n)          (((n) & 0xf) << 20)
+#define STM32F7_I2C_TIMINGR_SDADEL(n)          (((n) & 0xf) << 16)
+#define STM32F7_I2C_TIMINGR_SCLH(n)            (((n) & 0xff) << 8)
+#define STM32F7_I2C_TIMINGR_SCLL(n)            ((n) & 0xff)
+
+#define STM32F7_I2C_MAX_LEN                    0xff
+
+#define STM32F7_I2C_DNF_DEFAULT                        0
+#define STM32F7_I2C_DNF_MAX                    16
+
+#define STM32F7_I2C_ANALOG_FILTER_ENABLE       1
+#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN    50      /* ns */
+#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX    260     /* ns */
+
+#define STM32F7_I2C_RISE_TIME_DEFAULT          25      /* ns */
+#define STM32F7_I2C_FALL_TIME_DEFAULT          10      /* ns */
+
+#define STM32F7_PRESC_MAX                      BIT(4)
+#define STM32F7_SCLDEL_MAX                     BIT(4)
+#define STM32F7_SDADEL_MAX                     BIT(4)
+#define STM32F7_SCLH_MAX                       BIT(8)
+#define STM32F7_SCLL_MAX                       BIT(8)
+
+/**
+ * struct stm32f7_i2c_spec - private i2c specification timing
+ * @rate: I2C bus speed (Hz)
+ * @rate_min: 80% of I2C bus speed (Hz)
+ * @rate_max: 100% of I2C bus speed (Hz)
+ * @fall_max: Max fall time of both SDA and SCL signals (ns)
+ * @rise_max: Max rise time of both SDA and SCL signals (ns)
+ * @hddat_min: Min data hold time (ns)
+ * @vddat_max: Max data valid time (ns)
+ * @sudat_min: Min data setup time (ns)
+ * @l_min: Min low period of the SCL clock (ns)
+ * @h_min: Min high period of the SCL clock (ns)
+ */
+struct stm32f7_i2c_spec {
+       u32 rate;
+       u32 rate_min;
+       u32 rate_max;
+       u32 fall_max;
+       u32 rise_max;
+       u32 hddat_min;
+       u32 vddat_max;
+       u32 sudat_min;
+       u32 l_min;
+       u32 h_min;
+};
+
+/**
+ * struct stm32f7_i2c_setup - private I2C timing setup parameters
+ * @speed: I2C speed mode (standard, Fast Plus)
+ * @speed_freq: I2C speed frequency  (Hz)
+ * @clock_src: I2C clock source frequency (Hz)
+ * @rise_time: Rise time (ns)
+ * @fall_time: Fall time (ns)
+ * @dnf: Digital filter coefficient (0-16)
+ * @analog_filter: Analog filter delay (On/Off)
+ */
+struct stm32f7_i2c_setup {
+       enum stm32_i2c_speed speed;
+       u32 speed_freq;
+       u32 clock_src;
+       u32 rise_time;
+       u32 fall_time;
+       u8 dnf;
+       bool analog_filter;
+};
+
+/**
+ * struct stm32f7_i2c_timings - private I2C output parameters
+ * @prec: Prescaler value
+ * @scldel: Data setup time
+ * @sdadel: Data hold time
+ * @sclh: SCL high period (master mode)
+ * @sclh: SCL low period (master mode)
+ */
+struct stm32f7_i2c_timings {
+       struct list_head node;
+       u8 presc;
+       u8 scldel;
+       u8 sdadel;
+       u8 sclh;
+       u8 scll;
+};
+
+/**
+ * struct stm32f7_i2c_msg - client specific data
+ * @addr: 8-bit slave addr, including r/w bit
+ * @count: number of bytes to be transferred
+ * @buf: data buffer
+ * @result: result of the transfer
+ * @stop: last I2C msg to be sent, i.e. STOP to be generated
+ */
+struct stm32f7_i2c_msg {
+       u8 addr;
+       u32 count;
+       u8 *buf;
+       int result;
+       bool stop;
+};
+
+/**
+ * struct stm32f7_i2c_dev - private data of the controller
+ * @adap: I2C adapter for this controller
+ * @dev: device for this controller
+ * @base: virtual memory area
+ * @complete: completion of I2C message
+ * @clk: hw i2c clock
+ * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
+ * @msg: Pointer to data to be written
+ * @msg_num: number of I2C messages to be executed
+ * @msg_id: message identifiant
+ * @f7_msg: customized i2c msg for driver usage
+ * @setup: I2C timing input setup
+ * @timing: I2C computed timings
+ */
+struct stm32f7_i2c_dev {
+       struct i2c_adapter adap;
+       struct device *dev;
+       void __iomem *base;
+       struct completion complete;
+       struct clk *clk;
+       int speed;
+       struct i2c_msg *msg;
+       unsigned int msg_num;
+       unsigned int msg_id;
+       struct stm32f7_i2c_msg f7_msg;
+       struct stm32f7_i2c_setup *setup;
+       struct stm32f7_i2c_timings timing;
+};
+
+/**
+ * All these values are coming from I2C Specification, Version 6.0, 4th of
+ * April 2014.
+ *
+ * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
+ * and Fast-mode Plus I2C-bus devices
+ */
+static struct stm32f7_i2c_spec i2c_specs[] = {
+       [STM32_I2C_SPEED_STANDARD] = {
+               .rate = 100000,
+               .rate_min = 80000,
+               .rate_max = 100000,
+               .fall_max = 300,
+               .rise_max = 1000,
+               .hddat_min = 0,
+               .vddat_max = 3450,
+               .sudat_min = 250,
+               .l_min = 4700,
+               .h_min = 4000,
+       },
+       [STM32_I2C_SPEED_FAST] = {
+               .rate = 400000,
+               .rate_min = 320000,
+               .rate_max = 400000,
+               .fall_max = 300,
+               .rise_max = 300,
+               .hddat_min = 0,
+               .vddat_max = 900,
+               .sudat_min = 100,
+               .l_min = 1300,
+               .h_min = 600,
+       },
+       [STM32_I2C_SPEED_FAST_PLUS] = {
+               .rate = 1000000,
+               .rate_min = 800000,
+               .rate_max = 1000000,
+               .fall_max = 100,
+               .rise_max = 120,
+               .hddat_min = 0,
+               .vddat_max = 450,
+               .sudat_min = 50,
+               .l_min = 500,
+               .h_min = 260,
+       },
+};
+
+struct stm32f7_i2c_setup stm32f7_setup = {
+       .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
+       .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
+       .dnf = STM32F7_I2C_DNF_DEFAULT,
+       .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
+};
+
+static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
+{
+       writel_relaxed(readl_relaxed(reg) | mask, reg);
+}
+
+static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
+{
+       writel_relaxed(readl_relaxed(reg) & ~mask, reg);
+}
+
+static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
+                                     struct stm32f7_i2c_setup *setup,
+                                     struct stm32f7_i2c_timings *output)
+{
+       u32 p_prev = STM32F7_PRESC_MAX;
+       u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
+                                      setup->clock_src);
+       u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
+                                      setup->speed_freq);
+       u32 clk_error_prev = i2cbus;
+       u32 tsync;
+       u32 af_delay_min, af_delay_max;
+       u32 dnf_delay;
+       u32 clk_min, clk_max;
+       int sdadel_min, sdadel_max;
+       int scldel_min;
+       struct stm32f7_i2c_timings *v, *_v, *s;
+       struct list_head solutions;
+       u16 p, l, a, h;
+       int ret = 0;
+
+       if (setup->speed >= STM32_I2C_SPEED_END) {
+               dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
+                       setup->speed, STM32_I2C_SPEED_END - 1);
+               return -EINVAL;
+       }
+
+       if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
+           (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
+               dev_err(i2c_dev->dev,
+                       "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
+                       setup->rise_time, i2c_specs[setup->speed].rise_max,
+                       setup->fall_time, i2c_specs[setup->speed].fall_max);
+               return -EINVAL;
+       }
+
+       if (setup->dnf > STM32F7_I2C_DNF_MAX) {
+               dev_err(i2c_dev->dev,
+                       "DNF out of bound %d/%d\n",
+                       setup->dnf, STM32F7_I2C_DNF_MAX);
+               return -EINVAL;
+       }
+
+       if (setup->speed_freq > i2c_specs[setup->speed].rate) {
+               dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
+                       setup->speed_freq, i2c_specs[setup->speed].rate);
+               return -EINVAL;
+       }
+
+       /*  Analog and Digital Filters */
+       af_delay_min =
+               (setup->analog_filter ?
+                STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
+       af_delay_max =
+               (setup->analog_filter ?
+                STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
+       dnf_delay = setup->dnf * i2cclk;
+
+       sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
+               af_delay_min - (setup->dnf + 3) * i2cclk;
+
+       sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
+               af_delay_max - (setup->dnf + 4) * i2cclk;
+
+       scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
+
+       if (sdadel_min < 0)
+               sdadel_min = 0;
+       if (sdadel_max < 0)
+               sdadel_max = 0;
+
+       dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
+               sdadel_min, sdadel_max, scldel_min);
+
+       INIT_LIST_HEAD(&solutions);
+       /* Compute possible values for PRESC, SCLDEL and SDADEL */
+       for (p = 0; p < STM32F7_PRESC_MAX; p++) {
+               for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
+                       u32 scldel = (l + 1) * (p + 1) * i2cclk;
+
+                       if (scldel < scldel_min)
+                               continue;
+
+                       for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
+                               u32 sdadel = (a * (p + 1) + 1) * i2cclk;
+
+                               if (((sdadel >= sdadel_min) &&
+                                    (sdadel <= sdadel_max)) &&
+                                   (p != p_prev)) {
+                                       v = kmalloc(sizeof(*v), GFP_KERNEL);
+                                       if (!v) {
+                                               ret = -ENOMEM;
+                                               goto exit;
+                                       }
+
+                                       v->presc = p;
+                                       v->scldel = l;
+                                       v->sdadel = a;
+                                       p_prev = p;
+
+                                       list_add_tail(&v->node,
+                                                     &solutions);
+                               }
+                       }
+               }
+       }
+
+       if (list_empty(&solutions)) {
+               dev_err(i2c_dev->dev, "no Prescaler solution\n");
+               ret = -EPERM;
+               goto exit;
+       }
+
+       tsync = af_delay_min + dnf_delay + (2 * i2cclk);
+       s = NULL;
+       clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
+       clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
+
+       /*
+        * Among Prescaler possibilities discovered above figures out SCL Low
+        * and High Period. Provided:
+        * - SCL Low Period has to be higher than SCL Clock Low Period
+        *   defined by I2C Specification. I2C Clock has to be lower than
+        *   (SCL Low Period - Analog/Digital filters) / 4.
+        * - SCL High Period has to be lower than SCL Clock High Period
+        *   defined by I2C Specification
+        * - I2C Clock has to be lower than SCL High Period
+        */
+       list_for_each_entry(v, &solutions, node) {
+               u32 prescaler = (v->presc + 1) * i2cclk;
+
+               for (l = 0; l < STM32F7_SCLL_MAX; l++) {
+                       u32 tscl_l = (l + 1) * prescaler + tsync;
+
+                       if ((tscl_l < i2c_specs[setup->speed].l_min) ||
+                           (i2cclk >=
+                            ((tscl_l - af_delay_min - dnf_delay) / 4))) {
+                               continue;
+                       }
+
+                       for (h = 0; h < STM32F7_SCLH_MAX; h++) {
+                               u32 tscl_h = (h + 1) * prescaler + tsync;
+                               u32 tscl = tscl_l + tscl_h +
+                                       setup->rise_time + setup->fall_time;
+
+                               if ((tscl >= clk_min) && (tscl <= clk_max) &&
+                                   (tscl_h >= i2c_specs[setup->speed].h_min) &&
+                                   (i2cclk < tscl_h)) {
+                                       int clk_error = tscl - i2cbus;
+
+                                       if (clk_error < 0)
+                                               clk_error = -clk_error;
+
+                                       if (clk_error < clk_error_prev) {
+                                               clk_error_prev = clk_error;
+                                               v->scll = l;
+                                               v->sclh = h;
+                                               s = v;
+                                       }
+                               }
+                       }
+               }
+       }
+
+       if (!s) {
+               dev_err(i2c_dev->dev, "no solution at all\n");
+               ret = -EPERM;
+               goto exit;
+       }
+
+       output->presc = s->presc;
+       output->scldel = s->scldel;
+       output->sdadel = s->sdadel;
+       output->scll = s->scll;
+       output->sclh = s->sclh;
+
+       dev_dbg(i2c_dev->dev,
+               "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
+               output->presc,
+               output->scldel, output->sdadel,
+               output->scll, output->sclh);
+
+exit:
+       /* Release list and memory */
+       list_for_each_entry_safe(v, _v, &solutions, node) {
+               list_del(&v->node);
+               kfree(v);
+       }
+
+       return ret;
+}
+
+static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
+                                   struct stm32f7_i2c_setup *setup)
+{
+       int ret = 0;
+
+       setup->speed = i2c_dev->speed;
+       setup->speed_freq = i2c_specs[setup->speed].rate;
+       setup->clock_src = clk_get_rate(i2c_dev->clk);
+
+       if (!setup->clock_src) {
+               dev_err(i2c_dev->dev, "clock rate is 0\n");
+               return -EINVAL;
+       }
+
+       do {
+               ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
+                                                &i2c_dev->timing);
+               if (ret) {
+                       dev_err(i2c_dev->dev,
+                               "failed to compute I2C timings.\n");
+                       if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
+                               i2c_dev->speed--;
+                               setup->speed = i2c_dev->speed;
+                               setup->speed_freq =
+                                       i2c_specs[setup->speed].rate;
+                               dev_warn(i2c_dev->dev,
+                                        "downgrade I2C Speed Freq to (%i)\n",
+                                        i2c_specs[setup->speed].rate);
+                       } else {
+                               break;
+                       }
+               }
+       } while (ret);
+
+       if (ret) {
+               dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
+               return ret;
+       }
+
+       dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
+               setup->speed, setup->speed_freq, setup->clock_src);
+       dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
+               setup->rise_time, setup->fall_time);
+       dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
+               (setup->analog_filter ? "On" : "Off"), setup->dnf);
+
+       return 0;
+}
+
+static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
+{
+       struct stm32f7_i2c_timings *t = &i2c_dev->timing;
+       u32 timing = 0;
+
+       /* Timing settings */
+       timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
+       timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
+       timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
+       timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
+       timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
+       writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
+
+       /* Enable I2C */
+       if (i2c_dev->setup->analog_filter)
+               stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
+                                    STM32F7_I2C_CR1_ANFOFF);
+       else
+               stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
+                                    STM32F7_I2C_CR1_ANFOFF);
+       stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
+                            STM32F7_I2C_CR1_PE);
+}
+
+static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
+{
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       void __iomem *base = i2c_dev->base;
+
+       if (f7_msg->count) {
+               writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
+               f7_msg->count--;
+       }
+}
+
+static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
+{
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       void __iomem *base = i2c_dev->base;
+
+       if (f7_msg->count) {
+               *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
+               f7_msg->count--;
+       }
+}
+
+static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
+{
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       u32 cr2;
+
+       cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
+
+       cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
+       if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
+               cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
+       } else {
+               cr2 &= ~STM32F7_I2C_CR2_RELOAD;
+               cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
+       }
+
+       writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
+}
+
+static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
+{
+       u32 status;
+       int ret;
+
+       ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
+                                        status,
+                                        !(status & STM32F7_I2C_ISR_BUSY),
+                                        10, 1000);
+       if (ret) {
+               dev_dbg(i2c_dev->dev, "bus busy\n");
+               ret = -EBUSY;
+       }
+
+       return ret;
+}
+
+static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
+                                struct i2c_msg *msg)
+{
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       void __iomem *base = i2c_dev->base;
+       u32 cr1, cr2;
+
+       f7_msg->addr = msg->addr;
+       f7_msg->buf = msg->buf;
+       f7_msg->count = msg->len;
+       f7_msg->result = 0;
+       f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
+
+       reinit_completion(&i2c_dev->complete);
+
+       cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
+       cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
+
+       /* Set transfer direction */
+       cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
+       if (msg->flags & I2C_M_RD)
+               cr2 |= STM32F7_I2C_CR2_RD_WRN;
+
+       /* Set slave address */
+       cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
+       cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
+
+       /* Set nb bytes to transfer and reload if needed */
+       cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
+       if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
+               cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
+               cr2 |= STM32F7_I2C_CR2_RELOAD;
+       } else {
+               cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
+       }
+
+       /* Enable NACK, STOP, error and transfer complete interrupts */
+       cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
+               STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
+
+       /* Clear TX/RX interrupt */
+       cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
+
+       /* Enable RX/TX interrupt according to msg direction */
+       if (msg->flags & I2C_M_RD)
+               cr1 |= STM32F7_I2C_CR1_RXIE;
+       else
+               cr1 |= STM32F7_I2C_CR1_TXIE;
+
+       /* Configure Start/Repeated Start */
+       cr2 |= STM32F7_I2C_CR2_START;
+
+       /* Write configurations registers */
+       writel_relaxed(cr1, base + STM32F7_I2C_CR1);
+       writel_relaxed(cr2, base + STM32F7_I2C_CR2);
+}
+
+static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
+{
+       stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
+}
+
+static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
+{
+       struct stm32f7_i2c_dev *i2c_dev = data;
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       void __iomem *base = i2c_dev->base;
+       u32 status, mask;
+
+       status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
+
+       /* Tx empty */
+       if (status & STM32F7_I2C_ISR_TXIS)
+               stm32f7_i2c_write_tx_data(i2c_dev);
+
+       /* RX not empty */
+       if (status & STM32F7_I2C_ISR_RXNE)
+               stm32f7_i2c_read_rx_data(i2c_dev);
+
+       /* NACK received */
+       if (status & STM32F7_I2C_ISR_NACKF) {
+               dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
+               writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
+               f7_msg->result = -ENXIO;
+       }
+
+       /* STOP detection flag */
+       if (status & STM32F7_I2C_ISR_STOPF) {
+               /* Disable interrupts */
+               stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
+
+               /* Clear STOP flag */
+               writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
+
+               complete(&i2c_dev->complete);
+       }
+
+       /* Transfer complete */
+       if (status & STM32F7_I2C_ISR_TC) {
+               if (f7_msg->stop) {
+                       mask = STM32F7_I2C_CR2_STOP;
+                       stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
+               } else {
+                       i2c_dev->msg_id++;
+                       i2c_dev->msg++;
+                       stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
+               }
+       }
+
+       /*
+        * Transfer Complete Reload: 255 data bytes have been transferred
+        * We have to prepare the I2C controller to transfer the remaining
+        * data.
+        */
+       if (status & STM32F7_I2C_ISR_TCR)
+               stm32f7_i2c_reload(i2c_dev);
+
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
+{
+       struct stm32f7_i2c_dev *i2c_dev = data;
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       void __iomem *base = i2c_dev->base;
+       struct device *dev = i2c_dev->dev;
+       u32 status;
+
+       status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
+
+       /* Bus error */
+       if (status & STM32F7_I2C_ISR_BERR) {
+               dev_err(dev, "<%s>: Bus error\n", __func__);
+               writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
+               f7_msg->result = -EIO;
+       }
+
+       /* Arbitration loss */
+       if (status & STM32F7_I2C_ISR_ARLO) {
+               dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
+               writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
+               f7_msg->result = -EAGAIN;
+       }
+
+       stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
+
+       complete(&i2c_dev->complete);
+
+       return IRQ_HANDLED;
+}
+
+static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
+                           struct i2c_msg msgs[], int num)
+{
+       struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
+       struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
+       unsigned long time_left;
+       int ret;
+
+       i2c_dev->msg = msgs;
+       i2c_dev->msg_num = num;
+       i2c_dev->msg_id = 0;
+
+       ret = clk_enable(i2c_dev->clk);
+       if (ret) {
+               dev_err(i2c_dev->dev, "Failed to enable clock\n");
+               return ret;
+       }
+
+       ret = stm32f7_i2c_wait_free_bus(i2c_dev);
+       if (ret)
+               goto clk_free;
+
+       stm32f7_i2c_xfer_msg(i2c_dev, msgs);
+
+       time_left = wait_for_completion_timeout(&i2c_dev->complete,
+                                               i2c_dev->adap.timeout);
+       ret = f7_msg->result;
+
+       if (!time_left) {
+               dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
+                       i2c_dev->msg->addr);
+               ret = -ETIMEDOUT;
+       }
+
+clk_free:
+       clk_disable(i2c_dev->clk);
+
+       return (ret < 0) ? ret : num;
+}
+
+static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
+{
+       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static struct i2c_algorithm stm32f7_i2c_algo = {
+       .master_xfer = stm32f7_i2c_xfer,
+       .functionality = stm32f7_i2c_func,
+};
+
+static int stm32f7_i2c_probe(struct platform_device *pdev)
+{
+       struct device_node *np = pdev->dev.of_node;
+       struct stm32f7_i2c_dev *i2c_dev;
+       const struct stm32f7_i2c_setup *setup;
+       struct resource *res;
+       u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
+       struct i2c_adapter *adap;
+       struct reset_control *rst;
+       int ret;
+
+       i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
+       if (!i2c_dev)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(i2c_dev->base))
+               return PTR_ERR(i2c_dev->base);
+
+       irq_event = irq_of_parse_and_map(np, 0);
+       if (!irq_event) {
+               dev_err(&pdev->dev, "IRQ event missing or invalid\n");
+               return -EINVAL;
+       }
+
+       irq_error = irq_of_parse_and_map(np, 1);
+       if (!irq_error) {
+               dev_err(&pdev->dev, "IRQ error missing or invalid\n");
+               return -EINVAL;
+       }
+
+       i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
+       if (IS_ERR(i2c_dev->clk)) {
+               dev_err(&pdev->dev, "Error: Missing controller clock\n");
+               return PTR_ERR(i2c_dev->clk);
+       }
+       ret = clk_prepare_enable(i2c_dev->clk);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
+               return ret;
+       }
+
+       i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
+       ret = device_property_read_u32(&pdev->dev, "clock-frequency",
+                                      &clk_rate);
+       if (!ret && clk_rate >= 1000000)
+               i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
+       else if (!ret && clk_rate >= 400000)
+               i2c_dev->speed = STM32_I2C_SPEED_FAST;
+       else if (!ret && clk_rate >= 100000)
+               i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
+
+       rst = devm_reset_control_get(&pdev->dev, NULL);
+       if (IS_ERR(rst)) {
+               dev_err(&pdev->dev, "Error: Missing controller reset\n");
+               ret = PTR_ERR(rst);
+               goto clk_free;
+       }
+       reset_control_assert(rst);
+       udelay(2);
+       reset_control_deassert(rst);
+
+       i2c_dev->dev = &pdev->dev;
+
+       ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0,
+                              pdev->name, i2c_dev);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to request irq event %i\n",
+                       irq_event);
+               goto clk_free;
+       }
+
+       ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
+                              pdev->name, i2c_dev);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to request irq error %i\n",
+                       irq_error);
+               goto clk_free;
+       }
+
+       setup = of_device_get_match_data(&pdev->dev);
+       i2c_dev->setup->rise_time = setup->rise_time;
+       i2c_dev->setup->fall_time = setup->fall_time;
+       i2c_dev->setup->dnf = setup->dnf;
+       i2c_dev->setup->analog_filter = setup->analog_filter;
+
+       ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
+                                      &rise_time);
+       if (!ret)
+               i2c_dev->setup->rise_time = rise_time;
+
+       ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
+                                      &fall_time);
+       if (!ret)
+               i2c_dev->setup->fall_time = fall_time;
+
+       ret = stm32f7_i2c_setup_timing(i2c_dev, i2c_dev->setup);
+       if (ret)
+               goto clk_free;
+
+       stm32f7_i2c_hw_config(i2c_dev);
+
+       adap = &i2c_dev->adap;
+       i2c_set_adapdata(adap, i2c_dev);
+       snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
+                &res->start);
+       adap->owner = THIS_MODULE;
+       adap->timeout = 2 * HZ;
+       adap->retries = 3;
+       adap->algo = &stm32f7_i2c_algo;
+       adap->dev.parent = &pdev->dev;
+       adap->dev.of_node = pdev->dev.of_node;
+
+       init_completion(&i2c_dev->complete);
+
+       ret = i2c_add_adapter(adap);
+       if (ret)
+               goto clk_free;
+
+       platform_set_drvdata(pdev, i2c_dev);
+
+       clk_disable(i2c_dev->clk);
+
+       dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
+
+       return 0;
+
+clk_free:
+       clk_disable_unprepare(i2c_dev->clk);
+
+       return ret;
+}
+
+static int stm32f7_i2c_remove(struct platform_device *pdev)
+{
+       struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
+       i2c_del_adapter(&i2c_dev->adap);
+
+       clk_unprepare(i2c_dev->clk);
+
+       return 0;
+}
+
+static const struct of_device_id stm32f7_i2c_match[] = {
+       { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
+       {},
+};
+MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
+
+static struct platform_driver stm32f7_i2c_driver = {
+       .driver = {
+               .name = "stm32f7-i2c",
+               .of_match_table = stm32f7_i2c_match,
+       },
+       .probe = stm32f7_i2c_probe,
+       .remove = stm32f7_i2c_remove,
+};
+
+module_platform_driver(stm32f7_i2c_driver);
+
+MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
+MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
+MODULE_LICENSE("GPL v2");
diff --git a/firmware/.gitignore b/firmware/.gitignore
deleted file mode 100644 (file)
index d9c6901..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-*.gen.S
-*.fw
-*.bin
-*.csp
-*.dsp
-ihex2fw
diff --git a/firmware/3com/typhoon.bin.ihex b/firmware/3com/typhoon.bin.ihex
deleted file mode 100644 (file)
index d7a83be..0000000
+++ /dev/null
@@ -1,2819 +0,0 @@
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-:10AD4000C0469361D36AC046D361136BC046136299
-:10AD5000536BC0465362012201300B28E0D3074BEE
-:10AD6000002A02D19A688A4203D10021996090BCDE
-:10AD700070470020C043FAE7680E0080E81B00809F
-:10AD80000B2817DA0C4901235B068A691343012259
-:10AD900012058B6113610001401833239B01C01819
-:10ADA000036BC0464363530188699843886110610F
-:10ADB000012070470020FCE7680E008090B4084A2C
-:10ADC000D0690021074FD369834202D9FC1A2018A9
-:10ADD00000E0C01A0918181CB942F4D990BC704799
-:10ADE00000201440A861000090B5071C0024002F2B
-:10ADF00004D3FFF7E3FF0134BC42FAD990BC08BC8E
-:04AE000018470000EF
-:00000001FF
-/* ver 03.001.008 */
-/*
- * Copyright 1999-2004 3Com Corporation.  All Rights Reserved.
- *
- * Redistribution and use in source and binary forms of the 3c990img.h
- * microcode software are permitted provided that the following conditions
- * are met:
- * 1. Redistribution of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistribution in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of 3Com may not be used to endorse or promote products
- *    derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY 3COM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * USER ACKNOWLEDGES AND AGREES THAT PURCHASE OR USE OF THE 3c990img.h
- * MICROCODE SOFTWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY
- * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS
- * (PATENT, COPYRIGHT, TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT)
- * EMBODIED IN ANY OTHER 3COM HARDWARE OR SOFTWARE EITHER SOLELY OR IN
- * COMBINATION WITH THE 3c990img.h MICROCODE SOFTWARE
- */
diff --git a/firmware/Makefile b/firmware/Makefile
deleted file mode 100644 (file)
index fa3e81c..0000000
+++ /dev/null
@@ -1,238 +0,0 @@
-#
-# kbuild file for firmware/
-#
-
-# Create $(fwabs) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a
-# leading /, it's relative to $(srctree).
-fwdir := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE_DIR))
-fwabs := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir))
-
-fw-external-y := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE))
-
-# There are three cases to care about:
-# 1. Building kernel with CONFIG_FIRMWARE_IN_KERNEL=y -- $(fw-shipped-y) should
-#    include the firmware files to include, according to .config
-# 2. 'make modules_install', which will install firmware for modules, and 
-#    _also_ for the in-kernel drivers when CONFIG_FIRMWARE_IN_KERNEL=n
-# 3. 'make firmware_install', which installs all firmware, unconditionally.
-
-# For the former two cases we want $(fw-shipped-y) and $(fw-shipped-m) to be
-# accurate. In the latter case it doesn't matter -- it'll use $(fw-shipped-all).
-# But be aware that the config file might not be included at all.
-
-ifdef CONFIG_ACENIC_OMIT_TIGON_I
-acenic-objs := acenic/tg2.bin
-fw-shipped- += acenic/tg1.bin
-else
-acenic-objs := acenic/tg1.bin acenic/tg2.bin
-endif
-fw-shipped-$(CONFIG_ACENIC) += $(acenic-objs)
-fw-shipped-$(CONFIG_ADAPTEC_STARFIRE) += adaptec/starfire_rx.bin \
-                                        adaptec/starfire_tx.bin
-fw-shipped-$(CONFIG_ATARI_DSP56K) += dsp56k/bootstrap.bin
-fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw
-fw-shipped-$(CONFIG_BNX2X) += bnx2x/bnx2x-e1-6.2.9.0.fw \
-                             bnx2x/bnx2x-e1h-6.2.9.0.fw \
-                             bnx2x/bnx2x-e2-6.2.9.0.fw
-fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-6.2.1a.fw \
-                            bnx2/bnx2-rv2p-09-6.0.17.fw \
-                            bnx2/bnx2-rv2p-09ax-6.0.17.fw \
-                            bnx2/bnx2-mips-06-6.2.1.fw \
-                            bnx2/bnx2-rv2p-06-6.0.15.fw
-fw-shipped-$(CONFIG_CASSINI) += sun/cassini.bin
-fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \
-                                  cxgb3/t3c_psram-1.1.0.bin \
-                                  cxgb3/ael2005_opt_edc.bin \
-                                  cxgb3/ael2005_twx_edc.bin \
-                                  cxgb3/ael2020_twx_edc.bin
-fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw
-fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin
-fw-shipped-$(CONFIG_DRM_RADEON) += radeon/R100_cp.bin radeon/R200_cp.bin \
-                                  radeon/R300_cp.bin radeon/R420_cp.bin \
-                                  radeon/RS690_cp.bin radeon/RS600_cp.bin \
-                                  radeon/R520_cp.bin \
-                                  radeon/R600_pfp.bin radeon/R600_me.bin \
-                                  radeon/RV610_pfp.bin radeon/RV610_me.bin \
-                                  radeon/RV630_pfp.bin radeon/RV630_me.bin \
-                                  radeon/RV620_pfp.bin radeon/RV620_me.bin \
-                                  radeon/RV635_pfp.bin radeon/RV635_me.bin \
-                                  radeon/RV670_pfp.bin radeon/RV670_me.bin \
-                                  radeon/RS780_pfp.bin radeon/RS780_me.bin \
-                                  radeon/RV770_pfp.bin radeon/RV770_me.bin \
-                                  radeon/RV730_pfp.bin radeon/RV730_me.bin \
-                                  radeon/RV710_pfp.bin radeon/RV710_me.bin
-fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
-fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
-fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
-                            e100/d102e_ucode.bin
-fw-shipped-$(CONFIG_MYRI_SBUS) += myricom/lanai.bin
-fw-shipped-$(CONFIG_PCMCIA_PCNET) += cis/LA-PCM.cis cis/PCMLM28.cis \
-                                    cis/DP83903.cis cis/NE2K.cis \
-                                    cis/tamarack.cis cis/PE-200.cis \
-                                    cis/PE520.cis
-fw-shipped-$(CONFIG_PCMCIA_3C589) += cis/3CXEM556.cis
-fw-shipped-$(CONFIG_PCMCIA_3C574) += cis/3CCFEM556.cis
-fw-shipped-$(CONFIG_SERIAL_8250_CS) += cis/MT5634ZLX.cis cis/RS-COM-2P.cis \
-                                      cis/COMpad2.cis cis/COMpad4.cis \
-                                      cis/SW_555_SER.cis cis/SW_7xx_SER.cis \
-                                      cis/SW_8xx_SER.cis
-fw-shipped-$(CONFIG_PCMCIA_SMC91C92) += ositech/Xilinx7OD.bin
-fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \
-                                     advansys/3550.bin advansys/38C0800.bin
-fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \
-                                        qlogic/12160.bin
-fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin
-fw-shipped-$(CONFIG_INFINIBAND_QIB) += qlogic/sd7220.fw
-fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp
-fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \
-                                    ess/maestro3_assp_minisrc.fw
-fw-shipped-$(CONFIG_SND_SB16_CSP) += sb16/mulaw_main.csp sb16/alaw_main.csp \
-                                    sb16/ima_adpcm_init.csp \
-                                    sb16/ima_adpcm_playback.csp \
-                                    sb16/ima_adpcm_capture.csp
-fw-shipped-$(CONFIG_SND_YMFPCI) += yamaha/ds1_ctrl.fw yamaha/ds1_dsp.fw \
-                                  yamaha/ds1e_ctrl.fw
-fw-shipped-$(CONFIG_SND_WAVEFRONT) += yamaha/yss225_registers.bin
-fw-shipped-$(CONFIG_TEHUTI) += tehuti/bdx.bin
-fw-shipped-$(CONFIG_TIGON3) += tigon/tg3.bin tigon/tg3_tso.bin \
-                              tigon/tg3_tso5.bin
-fw-shipped-$(CONFIG_TYPHOON) += 3com/typhoon.bin
-fw-shipped-$(CONFIG_USB_EMI26) += emi26/loader.fw emi26/firmware.fw \
-                                 emi26/bitstream.fw
-fw-shipped-$(CONFIG_USB_EMI62) += emi62/loader.fw emi62/bitstream.fw \
-                                 emi62/spdif.fw emi62/midi.fw
-fw-shipped-$(CONFIG_USB_KAWETH) += kaweth/new_code.bin kaweth/trigger_code.bin \
-                                  kaweth/new_code_fix.bin \
-                                  kaweth/trigger_code_fix.bin
-ifdef CONFIG_FIRMWARE_IN_KERNEL
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_MPR) += keyspan/mpr.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA18X) += keyspan/usa18x.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19) += keyspan/usa19.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19QI) += keyspan/usa19qi.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19QW) += keyspan/usa19qw.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19W) += keyspan/usa19w.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28) += keyspan/usa28.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28XA) += keyspan/usa28xa.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28XB) += keyspan/usa28xb.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28X) += keyspan/usa28x.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA49W) += keyspan/usa49w.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA49WLC) += keyspan/usa49wlc.fw
-else
-fw-shipped- += keyspan/mpr.fw keyspan/usa18x.fw keyspan/usa19.fw       \
-       keyspan/usa19qi.fw keyspan/usa19qw.fw keyspan/usa19w.fw         \
-       keyspan/usa28.fw keyspan/usa28xa.fw keyspan/usa28xb.fw          \
-       keyspan/usa28x.fw keyspan/usa49w.fw keyspan/usa49wlc.fw
-endif
-fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw \
-                                     mts_cdma.fw mts_gsm.fw mts_edge.fw
-fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT) += edgeport/boot.fw edgeport/boot2.fw \
-                                           edgeport/down.fw edgeport/down2.fw
-fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += edgeport/down3.bin
-fw-shipped-$(CONFIG_USB_SERIAL_WHITEHEAT) += whiteheat_loader.fw whiteheat.fw \
-                                          # whiteheat_loader_debug.fw
-fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw
-fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
-fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
-fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
-fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
-
-fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
-
-quiet_cmd_ihex  = IHEX    $@
-      cmd_ihex  = $(OBJCOPY) -Iihex -Obinary $< $@
-
-quiet_cmd_ihex2fw  = IHEX2FW $@
-      cmd_ihex2fw  = $(objtree)/$(obj)/ihex2fw $< $@
-
-quiet_cmd_h16tofw  = H16TOFW $@
-      cmd_h16tofw  = $(objtree)/$(obj)/ihex2fw -w $< $@
-
-quiet_cmd_fwbin = MK_FW   $@
-      cmd_fwbin = FWNAME="$(patsubst firmware/%.gen.S,%,$@)";               \
-                 FWSTR="$(subst /,_,$(subst .,_,$(subst -,_,$(patsubst      \
-                               firmware/%.gen.S,%,$@))))";                  \
-                 ASM_WORD=$(if $(CONFIG_64BIT),.quad,.long);                \
-                 ASM_ALIGN=$(if $(CONFIG_64BIT),3,2);                       \
-                 PROGBITS=$(if $(CONFIG_ARM),%,@)progbits;                  \
-                 echo "/* Generated by firmware/Makefile */"           > $@;\
-                 echo "    .section .rodata"                           >>$@;\
-                 echo "    .p2align $${ASM_ALIGN}"                     >>$@;\
-                 echo "_fw_$${FWSTR}_bin:"                             >>$@;\
-                 echo "    .incbin \"$(2)\""                           >>$@;\
-                 echo "_fw_end:"                                       >>$@;\
-                 echo "   .section .rodata.str,\"aMS\",$${PROGBITS},1" >>$@;\
-                 echo "    .p2align $${ASM_ALIGN}"                     >>$@;\
-                 echo "_fw_$${FWSTR}_name:"                            >>$@;\
-                 echo "    .string \"$$FWNAME\""                       >>$@;\
-                 echo "    .section .builtin_fw,\"a\",$${PROGBITS}"    >>$@;\
-                 echo "    .p2align $${ASM_ALIGN}"                     >>$@;\
-                 echo "    $${ASM_WORD} _fw_$${FWSTR}_name"            >>$@;\
-                 echo "    $${ASM_WORD} _fw_$${FWSTR}_bin"             >>$@;\
-                 echo "    $${ASM_WORD} _fw_end - _fw_$${FWSTR}_bin"   >>$@;
-
-# One of these files will change, or come into existence, whenever
-# the configuration changes between 32-bit and 64-bit. The .S files
-# need to change when that happens.
-wordsize_deps := $(wildcard include/config/64bit.h include/config/32bit.h \
-               include/config/ppc32.h include/config/ppc64.h \
-               include/config/superh32.h include/config/superh64.h \
-               include/config/x86_32.h include/config/x86_64.h \
-               firmware/Makefile)
-
-$(patsubst %,$(obj)/%.gen.S, $(fw-shipped-y)): %: $(wordsize_deps)
-       $(call cmd,fwbin,$(patsubst %.gen.S,%,$@))
-$(patsubst %,$(obj)/%.gen.S, $(fw-external-y)): %: $(wordsize_deps) \
-               include/config/extra/firmware/dir.h
-       $(call cmd,fwbin,$(fwabs)/$(patsubst $(obj)/%.gen.S,%,$@))
-
-# The .o files depend on the binaries directly; the .S files don't.
-$(patsubst %,$(obj)/%.gen.o, $(fw-shipped-y)): %.gen.o: %
-$(patsubst %,$(obj)/%.gen.o, $(fw-external-y)): $(obj)/%.gen.o: $(fwdir)/%
-
-# .ihex is used just as a simple way to hold binary files in a source tree
-# where binaries are frowned upon. They are directly converted with objcopy.
-$(obj)/%: $(obj)/%.ihex
-       $(call cmd,ihex)
-
-# Don't depend on ihex2fw if we're installing and it already exists.
-# Putting it after | in the dependencies doesn't seem sufficient when
-# we're installing after a cross-compile, because ihex2fw has dependencies
-# on stuff like /usr/lib/gcc/ppc64-redhat-linux/4.3.0/include/stddef.h and 
-# thus wants to be rebuilt. Which it can't be, if the prebuilt kernel tree
-# is exported read-only for someone to run 'make install'.
-ifeq ($(INSTALL):$(wildcard $(obj)/ihex2fw),install:$(obj)/ihex2fw)
-ihex2fw_dep :=
-else
-ihex2fw_dep := $(obj)/ihex2fw
-endif
-
-# .HEX is also Intel HEX, but where the offset and length in each record
-# is actually meaningful, because the firmware has to be loaded in a certain
-# order rather than as a single binary blob. Thus, we convert them into our
-# more compact binary representation of ihex records (<linux/ihex.h>)
-$(obj)/%.fw: $(obj)/%.HEX $(ihex2fw_dep)
-       $(call cmd,ihex2fw)
-
-# .H16 is our own modified form of Intel HEX, with 16-bit length for records.
-$(obj)/%.fw: $(obj)/%.H16 $(ihex2fw_dep)
-       $(call cmd,h16tofw)
-
-obj-y                           += $(patsubst %,%.gen.o, $(fw-external-y))
-obj-$(CONFIG_FIRMWARE_IN_KERNEL) += $(patsubst %,%.gen.o, $(fw-shipped-y))
-
-ifeq ($(KBUILD_SRC),)
-# Makefile.build only creates subdirectories for O= builds, but external
-# firmware might live outside the kernel source tree
-_dummy := $(foreach d,$(addprefix $(obj)/,$(dir $(fw-external-y))), $(shell [ -d $(d) ] || mkdir -p $(d)))
-endif
-
-# Remove .S files and binaries created from ihex
-# (during 'make clean' .config isn't included so they're all in $(fw-shipped-))
-targets := $(fw-shipped-) $(patsubst $(obj)/%,%, \
-                               $(shell find $(obj) -name \*.gen.S 2>/dev/null))
-
-# Without this, built-in.o won't be created when it's empty, and the
-# final vmlinux link will fail.
-obj- := dummy
-
-hostprogs-y := ihex2fw
diff --git a/firmware/README.AddingFirmware b/firmware/README.AddingFirmware
deleted file mode 100644 (file)
index bcb5f46..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-
-       DO NOT ADD FIRMWARE TO THIS DIRECTORY.
-       ======================================
-
-This directory is only here to contain firmware images extracted from old
-device drivers which predate the common use of request_firmware().
-
-As we update those drivers to use request_firmware() and keep a clean
-separation between code and firmware, we put the extracted firmware
-here.
-
-This directory is _NOT_ for adding arbitrary new firmware images. The
-place to add those is the separate linux-firmware repository:
-
-    git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
-
-That repository contains all these firmware images which have been
-extracted from older drivers, as well various new firmware images which
-we were never permitted to include in a GPL'd work, but which we _have_
-been permitted to redistribute under separate cover.
-
-To submit firmware to that repository, please send either a git binary
-diff or preferably a git pull request to:
-      linux-firmware@kernel.org
-and also cc: to related mailing lists.
-
-Your commit should include an update to the WHENCE file clearly
-identifying the licence under which the firmware is available, and
-that it is redistributable. If the licence is long and involved, it's
-permitted to include it in a separate file and refer to it from the
-WHENCE file.
-And if it were possible, a changelog of the firmware itself.
-
-Ideally, your commit should contain a Signed-Off-By: from someone
-authoritative on the licensing of the firmware in question (i.e. from
-within the company that owns the code).
-
-
-WARNING:
-=======
-
-Don't send any "CONFIDENTIALITY STATEMENT" in your e-mail, patch or
-request. Otherwise your firmware _will never be accepted_.
-
-Maintainers are really busy, so don't expect a prompt reply.
diff --git a/firmware/WHENCE b/firmware/WHENCE
deleted file mode 100644 (file)
index de6f22e..0000000
+++ /dev/null
@@ -1,854 +0,0 @@
-             **********
-             * WHENCE *
-             **********
-
-This file attempts to document the origin and licensing information,
-if known, for each piece of firmware distributed for use with the Linux
-kernel.
-
---------------------------------------------------------------------------
-
-Driver: ambassador -- Madge Ambassador (Collage PCI 155 Server) ATM NIC.
-
-File: firmware/atmsar11.fw
-
-Licence: Allegedly GPLv2+, but no source visible. Marked:
-
-  Madge Ambassador ATM Adapter microcode.
-  Copyright (C) 1995-1999  Madge Networks Ltd.
-
-  This microcode data is placed under the terms of the GNU General
-  Public License. The GPL is contained in /usr/doc/copyright/GPL on a
-  Debian system and in the file COPYING in the Linux kernel source.
-
-  We would prefer you not to distribute modified versions without
-  consultation and not to ask for assembly/other microcode source.
-
---------------------------------------------------------------------------
-
-Driver: korg1212 -- Korg 1212 IO audio device
-
-File: korg/k1212.dsp
-
-Licence: Unknown
-
-Found in alsa-firmware package in hex form; no licensing information.
-
---------------------------------------------------------------------------
-
-Driver: maestro3 -- ESS Allegro Maestro3 audio device
-
-File: ess/maestro3_assp_kernel.fw
-File: ess/maestro3_assp_minisrc.fw
-
-Licence: Unknown
-
-Found in alsa-firmware package in hex form with a comment claiming to
-be GPLv2+, but without source -- and with another comment saying "ESS
-drops binary dsp code images on our heads, but we don't get to see
-specs on the dsp."
-
---------------------------------------------------------------------------
-
-Driver: ymfpci -- Yamaha YMF724/740/744/754 audio devices
-
-File: yamaha/ds1_ctrl.fw
-File: yamaha/ds1_dsp.fw
-File: yamaha/ds1e_ctrl.fw
-
-Licence: Unknown
-
-Found alsa-firmware package in hex form, with the following comment:
-   Copyright (c) 1997-1999 Yamaha Corporation. All Rights Reserved.
-
---------------------------------------------------------------------------
-
-Driver: SCSI_ADVANSYS - AdvanSys SCSI
-
-File: advansys/mcode.bin
-File: advansys/3550.bin
-File: advansys/38C0800.bin
-File: advansys/38C1600.bin
-
-Licence: BSD, no source available.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: SCSI_QLOGIC_1280 - Qlogic QLA 1240/1x80/1x160 SCSI support
-
-File: qlogic/1040.bin
-File: qlogic/1280.bin
-File: qlogic/12160.bin
-
-Licence: Allegedly GPLv2+, but no source visible. Marked:
-
-                   QLOGIC LINUX SOFTWARE
-  QLogic ISP1280/ device driver for Linux 2.2.x and 2.4.x
-  Copyright (C) 2001 Qlogic Corporation (www.qlogic.com)
-
---------------------------------------------------------------------------
-
-Driver: kaweth -- USB KLSI KL5USB101-based Ethernet device
-
-File: kaweth/new_code.bin
-File: kaweth/new_code_fix.bin
-File: kaweth/trigger_code.bin
-File: kaweth/trigger_code_fix.bin
-
-Licence: Unknown
-
-Found in hex form in the kernel source.
-
---------------------------------------------------------------------------
-
-Driver: ttusb-budget -- Technotrend/Hauppauge Nova-USB devices
-
-File: ttusb-budget/dspbootcode.bin
-
-Licence: Unknown
-
-Found in hex form in the kernel source.
-
---------------------------------------------------------------------------
-
-Driver: keyspan -- USB Keyspan USA-xxx serial device
-
-File: keyspan/mpr.fw
-File: keyspan/usa18x.fw
-File: keyspan/usa19.fw
-File: keyspan/usa19qi.fw
-File: keyspan/usa19qw.fw
-File: keyspan/usa19w.fw
-File: keyspan/usa28.fw
-File: keyspan/usa28xa.fw
-File: keyspan/usa28xb.fw
-File: keyspan/usa28x.fw
-File: keyspan/usa49w.fw
-File: keyspan/usa49wlc.fw
-
-Converted from Intel HEX files, used in our binary representation of ihex.
-
-Original licence information:
-
-               Copyright (C) 1999-2001
-               Keyspan, A division of InnoSys Incorporated ("Keyspan")
-
-       as an unpublished work. This notice does not imply unrestricted or
-       public access to the source code from which this firmware image is
-       derived.  Except as noted below this firmware image may not be
-       reproduced, used, sold or transferred to any third party without
-       Keyspan's prior written consent.  All Rights Reserved.
-
-       Permission is hereby granted for the distribution of this firmware
-       image as part of a Linux or other Open Source operating system kernel
-       in text or binary form as required.
-
-       This firmware may not be modified and may only be used with
-       Keyspan hardware.  Distribution and/or Modification of the
-       keyspan.c driver which includes this firmware, in whole or in
-       part, requires the inclusion of this statement."
-
---------------------------------------------------------------------------
-
-Driver: keyspan_pda -- USB Keyspan PDA single-port serial device
-
-File: keyspan_pda/keyspan_pda.fw
-Source: keyspan_pda/keyspan_pda.S
-
-File: keyspan_pda/xircom_pgs.fw
-Source: keyspan_pda/xircom_pgs.S
-
-Licence: GPLv2+
-
-Compiled from original 8051 source into Intel HEX, used in our binary ihex form.
-
---------------------------------------------------------------------------
-
-Driver: emi26 -- EMI 2|6 USB Audio interface
-
-File: emi26/bitstream.fw
-Info: VERSION=1.1.1.131 DATE=2001dec06
-
-File: emi26/firmware.fw
-Info: VERSION=1.0.2.916 DATE=12.02.2002
-
-File: emi26/loader.fw
-
-Converted from Intel HEX files, used in our binary representation of ihex.
-
-Original licence information:
-/*
- * This firmware is for the Emagic EMI 2|6 Audio Interface
- *
- * The firmware contained herein is Copyright (c) 1999-2002 Emagic
- * as an unpublished work. This notice does not imply unrestricted
- * or public access to this firmware which is a trade secret of Emagic,
- * and which may not be reproduced, used, sold or transferred to
- * any third party without Emagic's written consent. All Rights Reserved.
- *
- * Permission is hereby granted for the distribution of this firmware
- * image as part of a Linux or other Open Source operating system kernel
- * in text or binary form as required.
- *
- * This firmware may not be modified and may only be used with the
- * Emagic EMI 2|6 Audio Interface. Distribution and/or Modification of
- * any driver which includes this firmware, in whole or in part,
- * requires the inclusion of this statement.
- */
-
---------------------------------------------------------------------------
-
-Driver: emi62 -- EMI 6|2m USB Audio interface
-
-File: emi62/bitstream.fw
-Info: VERSION=1.0.0.191 DATE= 2002oct28
-
-File: emi62/loader.fw
-Source: EMILOAD.HEX
-Info: VERSION=1.0.2.002 DATE=10.01.2002
-
-File: emi62/midi.fw
-Source: EMI62MFW.HEX
-Info: VERSION=1.04.062 DATE=16.10.2002
-
-File: emi62/spdif.fw
-Source: EMI62SFW.HEX
-Info: VERSION=1.04.062 DATE=16.10.2002
-
-Converted from Intel HEX files, used in our binary representation of ihex.
-
-Original licence information: None
-
---------------------------------------------------------------------------
-
-Driver: ti_usb_3410_5052 -- USB TI 3410/5052 serial device
-
-File: ti_3410.fw
-Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort
-
-File: ti_5052.fw
-Info: firmware 9/18/04
-
-Licence: Allegedly GPLv2+, but no source visible. Marked:
-        Copyright (C) 2004 Texas Instruments
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: ti_usb_3410_5052 -- Multi-Tech USB cell modems
-
-File: mts_cdma.fw
-File: mts_gsm.fw
-File: mts_edge.fw
-
-Licence: "all firmware components are redistributable in binary form"
-         per support@multitech.com
-        Copyright (C) 2005 Multi-Tech Systems, Inc.
-
-Found in hex form in ftp://ftp.multitech.com/wireless/wireless_linux.zip
-
---------------------------------------------------------------------------
-
-Driver: whiteheat -- USB ConnectTech WhiteHEAT serial device
-
-File: whiteheat.fw
-Version: 4.06
-
-File: whiteheat_loader.fw
-File: whiteheat_loader_debug.fw
-
-Licence: Allegedly GPLv2, but no source visible. Marked:
-        Copyright (C) 2000-2002  ConnectTech Inc
-
-Debug loader claims the following behaviour:
-       Port 1 LED flashes when the vend_ax program is running
-       Port 2 LED flashes when any SETUP command arrives
-       Port 3 LED flashes when any valid VENDOR request occurs
-       Port 4 LED flashes when the EXTERNAL RAM DOWNLOAD request occurs
-
-Converted from Intel HEX files, used in our binary representation of ihex.
-
---------------------------------------------------------------------------
-
-Driver: CPiA2 -- cameras based on Vision's CPiA2
-
-File: cpia2/stv0672_vp4.bin
-
-Licence: Allegedly GPLv2+, but no source visible. Marked:
-       Copyright (C) 2001 STMicroelectronics, Inc.
-       Contact:  steve.miller@st.com
-       Description: This file contains patch data for the CPiA2 (stv0672) VP4.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: DABUSB -- Digital Audio Broadcasting (DAB) Receiver for USB and Linux
-
-File: dabusb/firmware.fw
-File: dabusb/bitstream.bin
-
-Licence: Distributable
-
- * Copyright (C) 1999 BayCom GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that redistributions of source
- * code retain the above copyright notice and this comment without
- * modification.
-
---------------------------------------------------------------------------
-
-Driver: USB_VICAM -- USB 3com HomeConnect (aka vicam)
-
-File: vicam/firmware.fw
-
-Licence: Unknown
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: USB_SERIAL_EDGEPORT - USB Inside Out Edgeport Serial Driver
-
-File: edgeport/boot.fw
-File: edgeport/boot2.fw
-File: edgeport/down.fw
-File: edgeport/down2.fw
-
-Licence: Allegedly GPLv2+, but no source visible. Marked:
-//**************************************************************
-//* Edgeport/4 Binary Image
-//* Generated by HEX2C v1.06
-//* Copyright (C) 1998 Inside Out Networks, All rights reserved.
-//**************************************************************
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: USB_SERIAL_EDGEPORT_TI - USB Inside Out Edgeport Serial Driver
-(TI Devices)
-
-File: edgeport/down3.bin
-
-Licence:
-//**************************************************************
-//* Edgeport Binary Image (for TI based products)
-//* Generated by TIBin2C v2.00 (watchport)
-//* Copyright (C) 2001 Inside Out Networks, All rights reserved.
-//**************************************************************
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: ATARI_DSP56K - Atari DSP56k support
-
-File: dsp56k/bootstrap.bin
-Source: dsp56k/bootstrap.asm
-
-Licence: GPLv2 or later
-
-DSP56001 assembler, possibly buildable with a56 from 
-http://www.zdomain.com/a56.html
-
---------------------------------------------------------------------------
-
-Driver: SND_SB16_CSP - Sound Blaster 16/AWE CSP support
-
-File: sb16/mulaw_main.csp
-File: sb16/alaw_main.csp
-File: sb16/ima_adpcm_init.csp
-File: sb16/ima_adpcm_playback.csp
-File: sb16/ima_adpcm_capture.csp
-
-Licence: Allegedly GPLv2+, but no source visible. Marked:
-/*
- *  Copyright (c) 1994 Creative Technology Ltd.
- *  Microcode files for SB16 Advanced Signal Processor
- */
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: CASSINI - Sun Cassini
-
-File: sun/cassini.bin
-
-Licence: Unknown
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: cxgb3 - Chelsio Terminator 3 1G/10G Ethernet adapter
-
-File: cxgb3/t3b_psram-1.1.0.bin.ihex
-File: cxgb3/t3c_psram-1.1.0.bin.ihex
-file: cxgb3/t3fw-7.4.0.bin.ihex
-
-License: GPLv2 or OpenIB.org BSD license, no source visible
-
---------------------------------------------------------------------------
-
-Driver: cxgb3 - Chelsio Terminator 3 1G/10G Ethernet adapter
-
-File: cxgb3/ael2005_opt_edc.bin.ihex
-File: cxgb3/ael2005_twx_edc.bin.ihex
-File: cxgb3/ael2020_twx_edc.bin.ihex
-
-Licence:
- *     Copyright (c) 2007-2009 NetLogic Microsystems, Inc.
- *
- *     Permission is hereby granted for the distribution of this firmware
- *     data in hexadecimal or equivalent format, provided this copyright
- *     notice is accompanying it.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: e100 -- Intel PRO/100 Ethernet NIC
-
-File: e100/d101m_ucode.bin
-File: e100/d101s_ucode.bin
-File: e100/d102e_ucode.bin
-
-Licence: Unknown
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: acenic -- Alteon AceNIC Gigabit Ethernet card
-
-File: acenic/tg1.bin
-File: acenic/tg2.bin
-
-Licence: Unknown
-
-Found in hex form in kernel source, but source allegedly available at
-http://alteon.shareable.org/
-
---------------------------------------------------------------------------
-
-Driver: tigon3 -- Broadcom Tigon3 based gigabit Ethernet cards
-
-File: tigon/tg3.bin
-File: tigon/tg3_tso.bin
-File: tigon/tg3_tso5.bin
-
-Licence:
- * Firmware is:
- *     Derived from proprietary unpublished source code,
- *     Copyright (C) 2000-2003 Broadcom Corporation.
- *
- *     Permission is hereby granted for the distribution of this firmware
- *     data in hexadecimal or equivalent format, provided this copyright
- *     notice is accompanying it.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: ADAPTEC_STARFIRE - Adaptec Starfire/DuraLAN support
-
-File: adaptec/starfire_rx.bin
-File: adaptec/starfire_tx.bin
-
-Licence: Allegedly GPLv2, but no source visible.
-
-Found in hex form in kernel source, with the following notice:
-
- BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE IT IS LICENSED "AS IS" AND
- THERE IS NO WARRANTY FOR THE PROGRAM, INCLUDING BUT NOT LIMITED TO THE
- IMPLIED WARRANTIES OF MERCHANTIBILITY OR FITNESS FOR A PARTICULAR PURPOSE
- (TO THE EXTENT PERMITTED BY APPLICABLE LAW). USE OF THE PROGRAM IS AT YOUR
- OWN RISK. IN NO EVENT WILL ADAPTEC OR ITS LICENSORS BE LIABLE TO YOU FOR
- DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
- ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM.
-
---------------------------------------------------------------------------
-
-Driver: TEHUTI - Tehuti Networks 10G Ethernet
-
-File: tehuti/bdx.bin
-
-Licence:
-
- Copyright (C) 2007 Tehuti Networks Ltd.
-
- Permission is hereby granted for the distribution of this firmware data
- in hexadecimal or equivalent format, provided this copyright notice is
- accompanying it.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: TYPHOON - 3cr990 series Typhoon
-
-File: 3com/typhoon.bin
-
-Licence:
-/*
- * Copyright 1999-2004 3Com Corporation.  All Rights Reserved.
- *
- * Redistribution and use in source and binary forms of the 3c990img.h
- * microcode software are permitted provided that the following conditions
- * are met:
- * 1. Redistribution of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistribution in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of 3Com may not be used to endorse or promote products
- *    derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY 3COM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * USER ACKNOWLEDGES AND AGREES THAT PURCHASE OR USE OF THE 3c990img.h
- * MICROCODE SOFTWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY
- * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS
- * (PATENT, COPYRIGHT, TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT)
- * EMBODIED IN ANY OTHER 3COM HARDWARE OR SOFTWARE EITHER SOLELY OR IN
- * COMBINATION WITH THE 3c990img.h MICROCODE SOFTWARE
- */
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: YAM - YAM driver for AX.25
-
-File: yam/1200.bin
-File: yam/9600.bin
-
-Licence:
- * (C) F6FBB 1998
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: PCMCIA_PCNET - NE2000 compatible PCMCIA adapter
-
-File: cis/LA-PCM.cis
-      cis/PCMLM28.cis
-      cis/DP83903.cis
-      cis/NE2K.cis
-      cis/tamarack.cis
-      cis/PE-200.cis
-      cis/PE520.cis
-
-Licence: GPL
-
-Originally developed by the pcmcia-cs project
-
---------------------------------------------------------------------------
-
-Driver: PCMCIA_3C589 - 3Com PCMCIA adapter
-
-File: cis/3CXEM556.cis
-
-Licence: GPL
-
-Originally developed by the pcmcia-cs project
-
---------------------------------------------------------------------------
-
-Driver: PCMCIA_3C574 - 3Com PCMCIA adapter
-
-File: cis/3CCFEM556.cis
-
-Licence: GPL
-
-Originally developed by the pcmcia-cs project
-
---------------------------------------------------------------------------
-
-Driver: SERIAL_8250_CS - Serial PCMCIA adapter
-
-File: cis/MT5634ZLX.cis
-      cis/RS-COM-2P.cis
-      cis/COMpad2.cis
-      cis/COMpad4.cis
-      cis/SW_555_SER.cis
-      cis/SW_7xx_SER.cis
-      cis/SW_8xx_SER.cis
-
-Licence: GPL
-
-Originally developed by the pcmcia-cs project
-
---------------------------------------------------------------------------
-
-Driver: PCMCIA_SMC91C92 - SMC 91Cxx PCMCIA
-
-File: ositech/Xilinx7OD.bin
-
-Licence: Allegedly GPL, but no source visible. Marked:
-    This file contains the firmware of Seven of Diamonds from OSITECH.
-    (Special thanks to Kevin MacPherson of OSITECH)
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: SCSI_QLOGICPTI - PTI Qlogic, ISP Driver
-
-File: qlogic/isp1000.bin
-
-Licence: Unknown
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: MYRI_SBUS - MyriCOM Gigabit Ethernet
-
-File: myricom/lanai.bin
-
-Licence: Unknown
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: bnx2x: Broadcom Everest
-
-File: bnx2x/bnx2x-e1-6.2.9.0.fw
-File: bnx2x/bnx2x-e1h-6.2.9.0.fw
-File: bnx2x/bnx2x-e2-6.2.9.0.fw
-
-License:
-  Copyright (c) 2007-2011 Broadcom Corporation
-
-  This file contains firmware data derived from proprietary unpublished
-  source code, Copyright (c) 2007-2011 Broadcom Corporation.
-
-  Permission is hereby granted for the distribution of this firmware data
-  in hexadecimal or equivalent format, provided this copyright notice is
-  accompanying it.
-
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: BNX2 - Broadcom NetXtremeII
-
-File: bnx2/bnx2-mips-06-6.2.1.fw
-File: bnx2/bnx2-rv2p-06-6.0.15.fw
-File: bnx2/bnx2-mips-09-6.2.1a.fw
-File: bnx2/bnx2-rv2p-09-6.0.17.fw
-File: bnx2/bnx2-rv2p-09ax-6.0.17.fw
-
-Licence:
-
- This file contains firmware data derived from proprietary unpublished
- source code, Copyright (c) 2004 - 2010 Broadcom Corporation.
-
- Permission is hereby granted for the distribution of this firmware data
- in hexadecimal or equivalent format, provided this copyright notice is
- accompanying it.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: DVB AV7110 -- AV7110 cards
-
-File: av7110/bootcode.bin
-
-Licence: GPLv2 or later
-
-ARM assembly source code available at https://linuxtv.org/downloads/firmware/Boot.S
-
---------------------------------------------------------------------------
-
-Driver: wavefront - ISA WaveFront sound card
-
-File: yamaha/yss225_registers.bin
-
-Licence: Allegedly GPLv2+, but no source visible.
-
-Found in hex form in kernel source, with the following comment:
-   Copyright (c) 1998-2002 by Paul Davis <pbd@op.net>
-
---------------------------------------------------------------------------
-
-Driver: mga - Matrox G200/G400/G550
-
-File: matrox/g200_warp.fw
-File: matrox/g400_warp.fw
-
-Licence:
-
-Copyright 1999 Matrox Graphics Inc.
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-the rights to use, copy, modify, merge, publish, distribute, sublicense,
-and/or sell copies of the Software, and to permit persons to whom the
-Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
-OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: r128 - ATI Rage 128
-
-File: r128/r128_cce.bin
-
-Licence:
-
-Copyright 2000 Advanced Micro Devices, Inc.
-
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
-
-Found in decimal form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: radeon - ATI Radeon
-
-File: radeon/R100_cp.bin
-File: radeon/R200_cp.bin
-File: radeon/R300_cp.bin
-File: radeon/R420_cp.bin
-File: radeon/RS600_cp.bin
-File: radeon/RS690_cp.bin
-File: radeon/R520_cp.bin
-File: radeon/R600_pfp.bin
-File: radeon/R600_me.bin
-File: radeon/RV610_pfp.bin
-File: radeon/RV610_me.bin
-File: radeon/RV630_pfp.bin
-File: radeon/RV630_me.bin
-File: radeon/RV620_pfp.bin
-File: radeon/RV620_me.bin
-File: radeon/RV635_pfp.bin
-File: radeon/RV635_me.bin
-File: radeon/RV670_pfp.bin
-File: radeon/RV670_me.bin
-File: radeon/RS780_pfp.bin
-File: radeon/RS780_me.bin
-File: radeon/RV770_pfp.bin
-File: radeon/RV770_me.bin
-File: radeon/RV730_pfp.bin
-File: radeon/RV730_me.bin
-File: radeon/RV710_pfp.bin
-File: radeon/RV710_me.bin
-
-Licence:
-
- * Copyright 2007-2009 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
-
-Driver: ib_qib - QLogic Infiniband
-
-File: qlogic/sd7220.fw
-
-Licence:
-
- * Copyright (c) 2007, 2008 QLogic Corporation. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- *     Redistribution and use in source and binary forms, with or
- *     without modification, are permitted provided that the following
- *     conditions are met:
- *
- *      - Redistributions of source code must retain the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer.
- *
- *      - Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials
- *        provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
-
-Found in hex form in kernel source.
-
---------------------------------------------------------------------------
diff --git a/firmware/acenic/tg1.bin.ihex b/firmware/acenic/tg1.bin.ihex
deleted file mode 100644 (file)
index bef2659..0000000
+++ /dev/null
@@ -1,4573 +0,0 @@
-:100000000C040B0000004000000040001000000342
-:10001000000000000000000D0000000D3C1D00016C
-:100020008FBD5C5403A0F0213C100000261040005E
-:100030000C00100C000000000000000D27BDFFD8D0
-:100040003C1CC0003C1B0013377BD8000000D021B3
-:100050003C17001336F7541802E02021340583E8DA
-:10006000AFBF00240C002488AFB000200C0023E8B0
-:10007000000000003C040001248451A42405000178
-:1000800002E03021000038213C10000126107E5093
-:10009000AFB000100C002403AFBB00143C02000FF3
-:1000A0003442FFFF020210240362102B10400009AB
-:1000B000240500033C040001248451B002003021D7
-:1000C000036038213C020010AFA200100C00240392
-:1000D000AFA00014000020213405C0003C01000145
-:1000E00000370821A02083B03C010001003708211F
-:1000F000A02083B23C01000100370821A02083B377
-:100100003C01000100370821AC2083B4A2E004D8F0
-:10011000000418C02484000100771021AC40727CD8
-:1001200000771021AC40728002E31021A445727C5C
-:100130002C8200201440FFF7000418C0000020218A
-:100140003405C000000418C0248400010077102189
-:10015000AC40737C00771021AC40738002E3102127
-:10016000A445737C2C8200805440FFF7000418C023
-:10017000AF800054AF80011C8F82004434420040A5
-:10018000AF8200448F82004434420020AF8200449A
-:100190008F420218304200021040000900000000A7
-:1001A0008F4202203C030002346300040043102508
-:1001B000AEE204C48F42021C0800107434420004F2
-:1001C0008F4202203C0300023463000600431025E6
-:1001D000AEE204C48F42021C34420006AEE204CCFC
-:1001E0008F420218304200101040000A0000000048
-:1001F0008F42021C34420004AEE204C88F42022047
-:100200003C03000A34630004004310250800108AF0
-:10021000AEE204C08F4202203C03000A34630006B1
-:1002200000431025AEE204C08F42021C3442000697
-:10023000AEE204C88F4202183042020010400003B0
-:100240002402000108001091A2E27248A2E0724864
-:1002500024020001AF8200A0AF8200B08F8300545F
-:100260008F82005408001099246300648F82005428
-:10027000006210232C4200651440FFFC00000000C7
-:10028000AF8000448F4202088F43020CAEE20010A0
-:10029000AEE300148EE400108EE5001426E2003078
-:1002A000AEE2002824020490AEE20018AF84009071
-:1002B000AF8500948EE20028AF8200B496E2001A67
-:1002C000AF82009C8F8200B08EE304CC00431025E7
-:1002D000AF8200B08F8200B0304200041440FFFDB6
-:1002E000000000008EE204508EE30454AEE304FCF0
-:1002F0008EE204FC2442E0002C4220011440000D58
-:1003000026E400308EE204508EE304543C040001E5
-:10031000248451BC3C050001AFA00010AFA0001424
-:100320008EE704FC34A5F0000C00240300603021AB
-:1003300026E400300C0024882405040027440080B3
-:100340000C0024882405008026E4777C0C00248897
-:10035000240504008F42025C26E40094AEE20060B3
-:100360008F4202602745020024060008AEE20068C2
-:10037000240200060C00249AAEE200643C023B9A80
-:100380003442CA000000202124030002AEE30074BE
-:10039000AEE30070AEE2006C240203E8AEE20104BA
-:1003A00024020001AEE30100AEE2010C3C030001B7
-:1003B0000064182190635C2002E410212484000171
-:1003C000A043009C2C82000F1440FFF800000000A6
-:1003D0008F82004002E418212484000100021702E9
-:1003E00024420030A062009C02E41021A040009C46
-:1003F00096E2046A30420003144000090000000045
-:1004000096E2047A30420003504001313C03080078
-:1004100096E2046A304200031040002A3C020700C2
-:1004200096E2047A30420003104000263C020700A6
-:1004300096E3047A96E2046A146200223C02070002
-:100440008EE204C024030001A2E34E2034420E00D9
-:10045000AEE204C08F420218304201001040000595
-:10046000000000003C0200012442E1680800111D68
-:10047000000211003C0200012442D35C0002110082
-:10048000000211823C030800004310253C010001DA
-:10049000AC2212383C0200012442F6800002110016
-:1004A000000211823C030800004310253C010001BA
-:1004B000AC2212788EE2000034424000080012386C
-:1004C000AEE2000034423000AFA200188EE206080F
-:1004D0008F43022824420001304900FF512300E2EB
-:1004E000AFA000108EE20608000210C000571021D5
-:1004F0008FA300188FA4001CAC43060CAC4406105C
-:100500008F8701202762380024E800200102102B89
-:1005100050400001276830008F820128110200043A
-:10052000000000008F820124150200070000102146
-:100530008EE201A40000302124420001AEE201A4B9
-:10054000080011A08EE201A48EE40608000420C079
-:10055000008018218EE404308EE5043400A32821A5
-:1005600000A3302B0082202100862021ACE4000073
-:10057000ACE500048EE3060824020008A4E2000EA5
-:100580002402000DACE20018ACE9001C000318C006
-:100590002463060C02E31021ACE200088EE204C4DE
-:1005A000ACE20010AF88012092E24E2014400037E8
-:1005B000240600018EE24E30000210C02442503862
-:1005C00002E220218C830000240200071462001F35
-:1005D000000000008EE34E308EE24E341062001BAD
-:1005E000240300408C82000424420001AC820004F9
-:1005F0008EE24E348EE54E30244200011043000757
-:10060000000000008EE24E342442000110A20005DA
-:10061000000000000800118A0000000014A000057E
-:10062000000000008F82012824420020AF820128B0
-:100630008F8201288C8200042C420011504000134C
-:10064000AC800000080011A0000000008EE24E30D7
-:100650002403004024420001504300030000102105
-:100660008EE24E3024420001AEE24E308EE24E3039
-:10067000000210C02442503802E220212402000768
-:10068000AC82000024020001AC82000454C0000CC3
-:10069000AEE906083C040001248451C8AFA0001054
-:1006A000AFA000148EE606088F4702283C0500091B
-:1006B0000C00240334A5F000080012230000000001
-:1006C0008F830120276238002466002000C2102B8F
-:1006D00050400001276630008F82012810C20004BC
-:1006E000000000008F82012414C2000700000000F7
-:1006F0008EE201A40000302124420001AEE201A4F8
-:10070000080012078EE201A48EE20608AC62001C0B
-:100710008EE404A08EE504A42462001CAC620008F0
-:1007200024020008A462000E24020011AC6200182A
-:10073000AC640000AC6500048EE204C4AC6200103E
-:10074000AF86012092E24E201440003724060001BB
-:100750008EE24E30000210C02442503802E22021C6
-:100760008C830000240200121462001F00000000AD
-:100770008EE34E308EE24E341062001B24030040A4
-:100780