Merge drm/drm-next into drm-intel-next-queued
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 10 Jul 2019 13:51:35 +0000 (06:51 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 10 Jul 2019 13:51:35 +0000 (06:51 -0700)
Catch-up with 5.2. Specially to remove a drm-tip merge
fixup around intel_workarounds.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
1  2 
drivers/gpu/drm/i915/display/intel_sdvo.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/i915_reg.h

index 651bf26bd1a3da6191b397945fb55a91c1720c2a,ceda03e5a3d4e0e50de7850fa155f13c7b464d34..3fe8eaef6bd89ab8ef8253526ff32e92f3a799b5
@@@ -274,145 -274,130 +274,145 @@@ static bool intel_sdvo_read_byte(struc
        return false;
  }
  
 -#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 +#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
 +
  /** Mapping of command numbers to names, for debug output */
 -static const struct _sdvo_cmd_name {
 +static const struct {
        u8 cmd;
        const char *name;
  } __attribute__ ((packed)) sdvo_cmd_names[] = {
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 +      SDVO_CMD_NAME_ENTRY(RESET),
 +      SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
 +      SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
 +      SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
 +      SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
 +      SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
 +      SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
 +      SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
 +      SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
 +      SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
 +      SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
 +      SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
 +      SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
 +      SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
 +      SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
 +      SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
 +      SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
 +      SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
 +      SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
 +      SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
 +      SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
 +      SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
 +      SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
 +      SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
 +      SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
 +      SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
 +      SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
 +      SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
 +      SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
 +      SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
 +      SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
 +      SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
 +      SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
 +      SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
 +      SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
 +      SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
 +      SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
 +      SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
 +      SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
 +      SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
 +      SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 +      SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
  
        /* Add the op code for SDVO enhancements */
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
 +      SDVO_CMD_NAME_ENTRY(GET_HPOS),
 +      SDVO_CMD_NAME_ENTRY(SET_HPOS),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
 +      SDVO_CMD_NAME_ENTRY(GET_VPOS),
 +      SDVO_CMD_NAME_ENTRY(SET_VPOS),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
 +      SDVO_CMD_NAME_ENTRY(GET_SATURATION),
 +      SDVO_CMD_NAME_ENTRY(SET_SATURATION),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
 +      SDVO_CMD_NAME_ENTRY(GET_HUE),
 +      SDVO_CMD_NAME_ENTRY(SET_HUE),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
 +      SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
 +      SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
 +      SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
 +      SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
 +      SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
 +      SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
 +      SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
 +      SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
 +      SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
 +      SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
 +      SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
 +      SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
 +      SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
 +      SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
 +      SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
 +      SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
 +      SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
 +      SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
 +      SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
 +      SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
 +      SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
 +      SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
 +      SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
  
        /* HDMI op code */
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 -      SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 +      SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
 +      SDVO_CMD_NAME_ENTRY(GET_ENCODE),
 +      SDVO_CMD_NAME_ENTRY(SET_ENCODE),
 +      SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
 +      SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
 +      SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
 +      SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
 +      SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
 +      SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
 +      SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
 +      SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
 +      SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
 +      SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
 +      SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
 +      SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
 +      SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
 +      SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
 +      SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
 +      SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
 +      SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
  };
  
 +#undef SDVO_CMD_NAME_ENTRY
 +
 +static const char *sdvo_cmd_name(u8 cmd)
 +{
 +      int i;
 +
 +      for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
 +              if (cmd == sdvo_cmd_names[i].cmd)
 +                      return sdvo_cmd_names[i].name;
 +      }
 +
 +      return NULL;
 +}
 +
  #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
  
  static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
                                   const void *args, int args_len)
  {
 +      const char *cmd_name;
        int i, pos = 0;
  #define BUF_LEN 256
        char buffer[BUF_LEN];
        for (; i < 8; i++) {
                BUF_PRINT("   ");
        }
 -      for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
 -              if (cmd == sdvo_cmd_names[i].cmd) {
 -                      BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
 -                      break;
 -              }
 -      }
 -      if (i == ARRAY_SIZE(sdvo_cmd_names)) {
 +
 +      cmd_name = sdvo_cmd_name(cmd);
 +      if (cmd_name)
 +              BUF_PRINT("(%s)", cmd_name);
 +      else
                BUF_PRINT("(%02X)", cmd);
 -      }
        BUG_ON(pos >= BUF_LEN - 1);
  #undef BUF_PRINT
  #undef BUF_LEN
  }
  
  static const char * const cmd_status_names[] = {
 -      "Power on",
 -      "Success",
 -      "Not supported",
 -      "Invalid arg",
 -      "Pending",
 -      "Target not specified",
 -      "Scaling not supported"
 +      [SDVO_CMD_STATUS_POWER_ON] = "Power on",
 +      [SDVO_CMD_STATUS_SUCCESS] = "Success",
 +      [SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
 +      [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
 +      [SDVO_CMD_STATUS_PENDING] = "Pending",
 +      [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
 +      [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
  };
  
 +static const char *sdvo_cmd_status(u8 status)
 +{
 +      if (status < ARRAY_SIZE(cmd_status_names))
 +              return cmd_status_names[status];
 +      else
 +              return NULL;
 +}
 +
  static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
                                   const void *args, int args_len,
                                   bool unlocked)
@@@ -536,7 -516,6 +536,7 @@@ static bool intel_sdvo_write_cmd(struc
  static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
                                     void *response, int response_len)
  {
 +      const char *cmd_status;
        u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
        u8 status;
        int i, pos = 0;
  #define BUF_PRINT(args...) \
        pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
  
 -      if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 -              BUF_PRINT("(%s)", cmd_status_names[status]);
 +      cmd_status = sdvo_cmd_status(status);
 +      if (cmd_status)
 +              BUF_PRINT("(%s)", cmd_status);
        else
                BUF_PRINT("(??? %d)", status);
  
@@@ -2419,9 -2397,10 +2419,10 @@@ static const struct drm_connector_func
  };
  
  static int intel_sdvo_atomic_check(struct drm_connector *conn,
-                                  struct drm_connector_state *new_conn_state)
+                                  struct drm_atomic_state *state)
  {
-       struct drm_atomic_state *state = new_conn_state->state;
+       struct drm_connector_state *new_conn_state =
+               drm_atomic_get_new_connector_state(state, conn);
        struct drm_connector_state *old_conn_state =
                drm_atomic_get_old_connector_state(state, conn);
        struct intel_sdvo_connector_state *old_state =
            (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
             memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
                struct drm_crtc_state *crtc_state =
-                       drm_atomic_get_new_crtc_state(new_conn_state->state,
+                       drm_atomic_get_new_crtc_state(state,
                                                      new_conn_state->crtc);
  
                crtc_state->connectors_changed = true;
        }
  
-       return intel_digital_connector_atomic_check(conn, new_conn_state);
+       return intel_digital_connector_atomic_check(conn, state);
  }
  
  static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
index 0342b7d761b8ba8033989e15cc608250549df309,15e90fd2cfdc2e9882cfeff9f2e2e1e4a1ff1a7e..f6fd6905ee6fb4758f93287dcfb3e436a915adea
@@@ -6,7 -6,6 +6,7 @@@
  
  #include "i915_drv.h"
  #include "intel_context.h"
 +#include "intel_gt.h"
  #include "intel_workarounds.h"
  
  /**
@@@ -39,7 -38,7 +39,7 @@@
   *    costly and simplifies things. We can revisit this in the future.
   *
   * Layout
-  * ''''''
+  * ~~~~~~
   *
   * Keep things in this file ordered by WA type, as per the above (context, GT,
   * display, register whitelist, batchbuffer). Then, inside each type, keep the
@@@ -531,6 -530,12 +531,12 @@@ static void icl_ctx_workarounds_init(st
  {
        struct drm_i915_private *i915 = engine->i915;
  
+       /* WaDisableBankHangMode:icl */
+       wa_write(wal,
+                GEN8_L3CNTLREG,
+                intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
+                GEN8_ERRDETBCTRL);
        /* WaDisableBankHangMode:icl */
        wa_write(wal,
                 GEN8_L3CNTLREG,
@@@ -985,9 -990,9 +991,9 @@@ wa_list_apply(struct intel_uncore *unco
        spin_unlock_irqrestore(&uncore->lock, flags);
  }
  
 -void intel_gt_apply_workarounds(struct drm_i915_private *i915)
 +void intel_gt_apply_workarounds(struct intel_gt *gt)
  {
 -      wa_list_apply(&i915->uncore, &i915->gt_wa_list);
 +      wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
  }
  
  static bool wa_list_verify(struct intel_uncore *uncore,
        return ok;
  }
  
 -bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
 -                               const char *from)
 +bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
  {
 -      return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
 +      return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
  }
  
  static void
@@@ -1092,25 -1098,10 +1098,25 @@@ static void glk_whitelist_build(struct 
  
  static void cfl_whitelist_build(struct intel_engine_cs *engine)
  {
 +      struct i915_wa_list *w = &engine->whitelist;
 +
        if (engine->class != RENDER_CLASS)
                return;
  
 -      gen9_whitelist_build(&engine->whitelist);
 +      gen9_whitelist_build(w);
 +
 +      /*
 +       * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
 +       *
 +       * This covers 4 register which are next to one another :
 +       *   - PS_INVOCATION_COUNT
 +       *   - PS_INVOCATION_COUNT_UDW
 +       *   - PS_DEPTH_COUNT
 +       *   - PS_DEPTH_COUNT_UDW
 +       */
 +      whitelist_reg_ext(w, PS_INVOCATION_COUNT,
 +                        RING_FORCE_TO_NONPRIV_RD |
 +                        RING_FORCE_TO_NONPRIV_RANGE_4);
  }
  
  static void cnl_whitelist_build(struct intel_engine_cs *engine)
@@@ -1138,19 -1129,6 +1144,19 @@@ static void icl_whitelist_build(struct 
  
                /* WaEnableStateCacheRedirectToCS:icl */
                whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
 +
 +              /*
 +               * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
 +               *
 +               * This covers 4 register which are next to one another :
 +               *   - PS_INVOCATION_COUNT
 +               *   - PS_INVOCATION_COUNT_UDW
 +               *   - PS_DEPTH_COUNT
 +               *   - PS_DEPTH_COUNT_UDW
 +               */
 +              whitelist_reg_ext(w, PS_INVOCATION_COUNT,
 +                                RING_FORCE_TO_NONPRIV_RD |
 +                                RING_FORCE_TO_NONPRIV_RANGE_4);
                break;
  
        case VIDEO_DECODE_CLASS:
@@@ -1280,12 -1258,8 +1286,12 @@@ rcs_engine_wa_init(struct intel_engine_
                if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
                        wa_write_or(wal,
                                    GEN7_SARCHKMD,
 -                                  GEN7_DISABLE_DEMAND_PREFETCH |
 -                                  GEN7_DISABLE_SAMPLER_PREFETCH);
 +                                  GEN7_DISABLE_DEMAND_PREFETCH);
 +
 +              /* Wa_1606682166:icl */
 +              wa_write_or(wal,
 +                          GEN7_SARCHKMD,
 +                          GEN7_DISABLE_SAMPLER_PREFETCH);
        }
  
        if (IS_GEN_RANGE(i915, 9, 11)) {
@@@ -1354,7 -1328,7 +1360,7 @@@ engine_init_workarounds(struct intel_en
        if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
                return;
  
 -      if (engine->id == RCS0)
 +      if (engine->class == RENDER_CLASS)
                rcs_engine_wa_init(engine, wal);
        else
                xcs_engine_wa_init(engine, wal);
@@@ -1364,7 -1338,7 +1370,7 @@@ void intel_engine_init_workarounds(stru
  {
        struct i915_wa_list *wal = &engine->wa_list;
  
 -      if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
 +      if (INTEL_GEN(engine->i915) < 8)
                return;
  
        wa_init_start(wal, engine->name);
@@@ -1452,7 -1426,7 +1458,7 @@@ static int engine_wa_list_verify(struc
        if (!wal->count)
                return 0;
  
 -      vma = create_scratch(&ce->engine->i915->ggtt.vm, wal->count);
 +      vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
        if (IS_ERR(vma))
                return PTR_ERR(vma);
  
index 089b186097278448c223a0f313ae0cb0401c445c,d6483b5dc8e593532ba96fed9ee0b8d39f16fe90..5898f59e3dd7aa35799bdc51ec981e1e913855ab
@@@ -35,7 -35,7 +35,7 @@@
   * macros. Do **not** mass change existing definitions just to update the style.
   *
   * Layout
-  * ''''''
+  * ~~~~~~
   *
   * Keep helper macros near the top. For example, _PIPE() and friends.
   *
@@@ -79,7 -79,7 +79,7 @@@
   * style. Use lower case in hexadecimal values.
   *
   * Naming
-  * ''''''
+  * ~~~~~~
   *
   * Try to name registers according to the specs. If the register name changes in
   * the specs from platform to another, stick to the original name.
@@@ -97,7 -97,7 +97,7 @@@
   * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
   *
   * Examples
-  * ''''''''
+  * ~~~~~~~~
   *
   * (Note that the values in the example are indented using spaces instead of
   * TABs to avoid misalignment in generated documentation. Use TABs in the
@@@ -1793,10 -1793,8 +1793,10 @@@ enum i915_power_well_id 
   */
  #define _ICL_COMBOPHY_A                       0x162000
  #define _ICL_COMBOPHY_B                       0x6C000
 +#define _EHL_COMBOPHY_C                       0x160000
  #define _ICL_COMBOPHY(port)           _PICK(port, _ICL_COMBOPHY_A, \
 -                                            _ICL_COMBOPHY_B)
 +                                            _ICL_COMBOPHY_B, \
 +                                            _EHL_COMBOPHY_C)
  
  /* CNL/ICL Port CL_DW registers */
  #define _ICL_PORT_CL_DW(dw, port)     (_ICL_COMBOPHY(port) + \
  #define ICL_PORT_PCS_DW1_GRP(port)    _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
  #define ICL_PORT_PCS_DW1_LN0(port)    _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
  #define   COMMON_KEEPER_EN            (1 << 26)
 +#define   LATENCY_OPTIM_MASK          (0x3 << 2)
 +#define   LATENCY_OPTIM_VAL(x)                ((x) << 2)
  
  /* CNL/ICL Port TX registers */
  #define _CNL_PORT_TX_AE_GRP_OFFSET            0x162340
  #define   N_SCALAR(x)                 ((x) << 24)
  #define   N_SCALAR_MASK                       (0x7F << 24)
  
 +#define _ICL_DPHY_CHKN_REG                    0x194
 +#define ICL_DPHY_CHKN(port)                   _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
 +#define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP    REG_BIT(7)
 +
  #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
        _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
  
@@@ -6292,7 -6284,6 +6292,7 @@@ enum 
  #define _DSPATILEOFF                          0x701A4 /* 965+ only */
  #define _DSPAOFFSET                           0x701A4 /* HSW */
  #define _DSPASURFLIVE                         0x701AC
 +#define _DSPAGAMC                             0x701E0
  
  #define DSPCNTR(plane)                _MMIO_PIPE2(plane, _DSPACNTR)
  #define DSPADDR(plane)                _MMIO_PIPE2(plane, _DSPAADDR)
  #define DSPLINOFF(plane)      DSPADDR(plane)
  #define DSPOFFSET(plane)      _MMIO_PIPE2(plane, _DSPAOFFSET)
  #define DSPSURFLIVE(plane)    _MMIO_PIPE2(plane, _DSPASURFLIVE)
 +#define DSPGAMC(plane, i)     _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
  
  /* CHV pipe B blender and primary plane */
  #define _CHV_BLEND_A          0x60a00
  #define _DVSAKEYMAXVAL                0x721a0
  #define _DVSATILEOFF          0x721a4
  #define _DVSASURFLIVE         0x721ac
 +#define _DVSAGAMC_G4X         0x721e0 /* g4x */
  #define _DVSASCALE            0x72204
  #define   DVS_SCALE_ENABLE    (1 << 31)
  #define   DVS_FILTER_MASK     (3 << 29)
  #define   DVS_FILTER_SOFTENING        (2 << 29)
  #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
  #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
 -#define _DVSAGAMC             0x72300
 +#define _DVSAGAMC_ILK         0x72300 /* ilk/snb */
 +#define _DVSAGAMCMAX_ILK      0x72340 /* ilk/snb */
  
  #define _DVSBCNTR             0x73180
  #define _DVSBLINOFF           0x73184
  #define _DVSBKEYMAXVAL                0x731a0
  #define _DVSBTILEOFF          0x731a4
  #define _DVSBSURFLIVE         0x731ac
 +#define _DVSBGAMC_G4X         0x731e0 /* g4x */
  #define _DVSBSCALE            0x73204
 -#define _DVSBGAMC             0x73300
 +#define _DVSBGAMC_ILK         0x73300 /* ilk/snb */
 +#define _DVSBGAMCMAX_ILK      0x73340 /* ilk/snb */
  
  #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
  #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
  #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
  #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
  #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
 +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
 +#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
 +#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
  
  #define _SPRA_CTL             0x70280
  #define   SPRITE_ENABLE                       (1 << 31)
  #define   SPRITE_YUV_ORDER_VYUY               (3 << 16)
  #define   SPRITE_ROTATE_180           (1 << 15)
  #define   SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
 -#define   SPRITE_INT_GAMMA_ENABLE     (1 << 13)
 +#define   SPRITE_INT_GAMMA_DISABLE    (1 << 13)
  #define   SPRITE_TILED                        (1 << 10)
  #define   SPRITE_DEST_KEY             (1 << 2)
  #define _SPRA_LINOFF          0x70284
  #define   SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
  #define   SPRITE_VERTICAL_OFFSET_ENABLE       (1 << 27)
  #define _SPRA_GAMC            0x70400
 +#define _SPRA_GAMC16          0x70440
 +#define _SPRA_GAMC17          0x7044c
  
  #define _SPRB_CTL             0x71280
  #define _SPRB_LINOFF          0x71284
  #define _SPRB_SURFLIVE                0x712ac
  #define _SPRB_SCALE           0x71304
  #define _SPRB_GAMC            0x71400
 +#define _SPRB_GAMC16          0x71440
 +#define _SPRB_GAMC17          0x7144c
  
  #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
  #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
  #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
  #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
  #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
 -#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
 +#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
 +#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
 +#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
  #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
  
  #define _SPACNTR              (VLV_DISPLAY_BASE + 0x72180)
  #define _SPACLRC1             (VLV_DISPLAY_BASE + 0x721d4)
  #define   SP_SH_SIN(x)                        (((x) & 0x7ff) << 16) /* s4.7 */
  #define   SP_SH_COS(x)                        (x) /* u3.7 */
 -#define _SPAGAMC              (VLV_DISPLAY_BASE + 0x721f4)
 +#define _SPAGAMC              (VLV_DISPLAY_BASE + 0x721e0)
  
  #define _SPBCNTR              (VLV_DISPLAY_BASE + 0x72280)
  #define _SPBLINOFF            (VLV_DISPLAY_BASE + 0x72284)
  #define _SPBCONSTALPHA                (VLV_DISPLAY_BASE + 0x722a8)
  #define _SPBCLRC0             (VLV_DISPLAY_BASE + 0x722d0)
  #define _SPBCLRC1             (VLV_DISPLAY_BASE + 0x722d4)
 -#define _SPBGAMC              (VLV_DISPLAY_BASE + 0x722f4)
 +#define _SPBGAMC              (VLV_DISPLAY_BASE + 0x722e0)
  
 +#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
 +      _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
  #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
 -      _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
 +      _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
  
  #define SPCNTR(pipe, plane_id)                _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
  #define SPLINOFF(pipe, plane_id)      _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
  #define SPCONSTALPHA(pipe, plane_id)  _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
  #define SPCLRC0(pipe, plane_id)               _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
  #define SPCLRC1(pipe, plane_id)               _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
 -#define SPGAMC(pipe, plane_id)                _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
 +#define SPGAMC(pipe, plane_id, i)     _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
  
  /*
   * CHV pipe B sprite CSC
@@@ -11170,7 -11145,6 +11170,7 @@@ enum skl_power_gate 
  #define _ICL_PHY_MISC_B               0x64C04
  #define ICL_PHY_MISC(port)    _MMIO_PORT(port, _ICL_PHY_MISC_A, \
                                                 _ICL_PHY_MISC_B)
 +#define  ICL_PHY_MISC_MUX_DDID                        (1 << 28)
  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN     (1 << 23)
  
  /* Icelake Display Stream Compression Registers */