Merge branch 'for-linus' into test
authorJens Axboe <axboe@kernel.dk>
Wed, 7 Feb 2018 22:54:25 +0000 (15:54 -0700)
committerJens Axboe <axboe@kernel.dk>
Wed, 7 Feb 2018 22:54:25 +0000 (15:54 -0700)
* for-linus:
  block, bfq: add requeue-request hook
  bcache: fix for data collapse after re-attaching an attached device
  bcache: return attach error when no cache set exist
  bcache: set writeback_rate_update_seconds in range [1, 60] seconds
  bcache: fix for allocator and register thread race
  bcache: set error_limit correctly
  bcache: properly set task state in bch_writeback_thread()
  bcache: fix high CPU occupancy during journal
  bcache: add journal statistic
  block: Add should_fail_bio() for bpf error injection
  blk-wbt: account flush requests correctly

484 files changed:
Documentation/ABI/testing/sysfs-driver-samsung-laptop
Documentation/admin-guide/thunderbolt.rst
Documentation/bpf/bpf_devel_QA.txt
Documentation/devicetree/bindings/thermal/armada-thermal.txt
Documentation/devicetree/bindings/thermal/rcar-thermal.txt
Documentation/devicetree/bindings/vendor-prefixes.txt
Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt [deleted file]
Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt [moved from Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt with 55% similarity]
Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt
Documentation/devicetree/bindings/watchdog/realtek,rtd119x.txt [new file with mode: 0644]
Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
Documentation/devicetree/bindings/watchdog/sprd-wdt.txt [new file with mode: 0644]
Documentation/mips/AU1xxx_IDE.README
Documentation/networking/ip-sysctl.txt
Documentation/process/index.rst
Documentation/process/kernel-docs.rst
Documentation/process/maintainer-pgp-guide.rst [new file with mode: 0644]
Documentation/sysctl/user.txt
Documentation/watchdog/watchdog-parameters.txt
MAINTAINERS
Makefile
arch/Kconfig
arch/arm/include/asm/bitops.h
arch/arm64/Kconfig
arch/arm64/include/asm/kasan.h
arch/arm64/include/asm/memory.h
arch/arm64/kernel/entry.S
arch/arm64/kernel/perf_event.c
arch/arm64/mm/kasan_init.c
arch/ia64/kernel/perfmon.c
arch/m68k/include/asm/bitops.h
arch/mips/Kconfig
arch/mips/Makefile
arch/mips/bcm47xx/Platform
arch/mips/boot/compressed/Makefile
arch/mips/boot/dts/ingenic/Makefile
arch/mips/boot/dts/ingenic/gcw0.dts [new file with mode: 0644]
arch/mips/boot/dts/ingenic/jz4770.dtsi [new file with mode: 0644]
arch/mips/configs/bigsur_defconfig
arch/mips/configs/gcw0_defconfig [new file with mode: 0644]
arch/mips/configs/generic/board-ranchu.config [new file with mode: 0644]
arch/mips/configs/ip27_defconfig
arch/mips/configs/ip32_defconfig
arch/mips/configs/malta_defconfig
arch/mips/configs/malta_kvm_defconfig
arch/mips/configs/malta_kvm_guest_defconfig
arch/mips/configs/malta_qemu_32r6_defconfig
arch/mips/configs/maltaaprp_defconfig
arch/mips/configs/maltasmvp_defconfig
arch/mips/configs/maltasmvp_eva_defconfig
arch/mips/configs/maltaup_defconfig
arch/mips/configs/maltaup_xpa_defconfig
arch/mips/configs/nlm_xlp_defconfig
arch/mips/configs/nlm_xlr_defconfig
arch/mips/configs/pnx8335_stb225_defconfig
arch/mips/configs/sb1250_swarm_defconfig
arch/mips/generic/Kconfig
arch/mips/generic/Makefile
arch/mips/generic/board-ranchu.c [new file with mode: 0644]
arch/mips/generic/irq.c
arch/mips/include/asm/bootinfo.h
arch/mips/include/asm/checksum.h
arch/mips/include/asm/mach-loongson64/boot_param.h
arch/mips/include/asm/machine.h
arch/mips/include/asm/mipsregs.h
arch/mips/include/asm/msa.h
arch/mips/jz4740/Kconfig
arch/mips/jz4740/prom.c
arch/mips/jz4740/setup.c
arch/mips/jz4740/time.c
arch/mips/kernel/branch.c
arch/mips/kernel/cps-vec.S
arch/mips/kernel/ftrace.c
arch/mips/kernel/setup.c
arch/mips/kernel/smp-cps.c
arch/mips/kernel/watch.c
arch/mips/loongson64/Kconfig
arch/mips/loongson64/common/mem.c
arch/mips/loongson64/loongson-3/numa.c
arch/mips/math-emu/cp1emu.c
arch/mips/math-emu/dp_add.c
arch/mips/math-emu/dp_div.c
arch/mips/math-emu/dp_fmax.c
arch/mips/math-emu/dp_fmin.c
arch/mips/math-emu/dp_maddf.c
arch/mips/math-emu/dp_mul.c
arch/mips/math-emu/dp_sqrt.c
arch/mips/math-emu/dp_sub.c
arch/mips/math-emu/ieee754dp.h
arch/mips/math-emu/sp_add.c
arch/mips/math-emu/sp_div.c
arch/mips/math-emu/sp_fdp.c
arch/mips/math-emu/sp_fmax.c
arch/mips/math-emu/sp_fmin.c
arch/mips/math-emu/sp_maddf.c
arch/mips/math-emu/sp_mul.c
arch/mips/math-emu/sp_sqrt.c
arch/mips/math-emu/sp_sub.c
arch/mips/math-emu/sp_tlong.c
arch/mips/mm/dma-default.c
arch/mips/mm/sc-mips.c
arch/mips/txx9/rbtx4939/setup.c
arch/powerpc/Kconfig
arch/powerpc/include/asm/membarrier.h [new file with mode: 0644]
arch/powerpc/mm/mmu_context.c
arch/riscv/Kconfig
arch/riscv/include/asm/Kbuild
arch/riscv/include/asm/csr.h
arch/riscv/include/asm/ftrace.h [new file with mode: 0644]
arch/riscv/include/asm/mmu_context.h
arch/riscv/include/asm/tlbflush.h
arch/riscv/include/asm/unistd.h
arch/riscv/kernel/Makefile
arch/riscv/kernel/entry.S
arch/riscv/kernel/ftrace.c [new file with mode: 0644]
arch/riscv/kernel/head.S
arch/riscv/kernel/mcount.S [new file with mode: 0644]
arch/riscv/kernel/setup.c
arch/riscv/kernel/vdso.c
arch/riscv/mm/fault.c
arch/riscv/mm/init.c
arch/score/kernel/setup.c
arch/unicore32/include/asm/bitops.h
arch/x86/Kconfig
arch/x86/entry/entry_32.S
arch/x86/entry/entry_64.S
arch/x86/events/perf_event.h
arch/x86/include/asm/intel-family.h
arch/x86/include/asm/intel_pmc_ipc.h
arch/x86/include/asm/kasan.h
arch/x86/include/asm/pmc_core.h [deleted file]
arch/x86/include/asm/sync_core.h [new file with mode: 0644]
arch/x86/mm/tlb.c
drivers/acpi/acpi_lpit.c
drivers/clk/ingenic/Makefile
drivers/clk/ingenic/cgu.c
drivers/clk/ingenic/cgu.h
drivers/clk/ingenic/jz4770-cgu.c [new file with mode: 0644]
drivers/clk/ingenic/jz4780-cgu.c
drivers/media/dvb-core/dvb_vb2.c
drivers/mfd/ab8500-debugfs.c
drivers/net/ethernet/amd/xgbe/xgbe-drv.c
drivers/net/ethernet/emulex/benet/be.h
drivers/net/ethernet/emulex/benet/be_ethtool.c
drivers/net/ethernet/emulex/benet/be_hw.h
drivers/net/ethernet/emulex/benet/be_main.c
drivers/net/ethernet/ibm/ibmvnic.c
drivers/net/ethernet/netronome/nfp/bpf/main.h
drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c
drivers/net/ethernet/netronome/nfp/nfp_net.h
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_resource.c
drivers/net/netdevsim/bpf.c
drivers/net/phy/mdio_bus.c
drivers/perf/arm_dsu_pmu.c
drivers/platform/Kconfig
drivers/platform/Makefile
drivers/platform/mellanox/Kconfig [new file with mode: 0644]
drivers/platform/mellanox/Makefile [new file with mode: 0644]
drivers/platform/mellanox/mlxreg-hotplug.c [new file with mode: 0644]
drivers/platform/x86/Kconfig
drivers/platform/x86/Makefile
drivers/platform/x86/acer-wireless.c [new file with mode: 0644]
drivers/platform/x86/alienware-wmi.c
drivers/platform/x86/apple-gmux.c
drivers/platform/x86/asus-nb-wmi.c
drivers/platform/x86/dell-laptop.c
drivers/platform/x86/dell-smbios.c
drivers/platform/x86/dell-wmi.c
drivers/platform/x86/gpd-pocket-fan.c [new file with mode: 0644]
drivers/platform/x86/ideapad-laptop.c
drivers/platform/x86/intel-hid.c
drivers/platform/x86/intel-vbtn.c
drivers/platform/x86/intel_chtdc_ti_pwrbtn.c [new file with mode: 0644]
drivers/platform/x86/intel_int0002_vgpio.c
drivers/platform/x86/intel_pmc_core.c
drivers/platform/x86/intel_pmc_core.h
drivers/platform/x86/intel_pmc_ipc.c
drivers/platform/x86/intel_telemetry_debugfs.c
drivers/platform/x86/mlx-platform.c
drivers/platform/x86/mlxcpld-hotplug.c [deleted file]
drivers/platform/x86/pmc_atom.c
drivers/platform/x86/samsung-laptop.c
drivers/platform/x86/silead_dmi.c
drivers/platform/x86/thinkpad_acpi.c
drivers/pps/generators/pps_gen_parport.c
drivers/rapidio/devices/tsi721_dma.c
drivers/rapidio/rio.c
drivers/regulator/core.c
drivers/thermal/Kconfig
drivers/thermal/armada_thermal.c
drivers/thermal/hisi_thermal.c
drivers/thermal/imx_thermal.c
drivers/thermal/int340x_thermal/int3400_thermal.c
drivers/thermal/mtk_thermal.c
drivers/thermal/of-thermal.c
drivers/thermal/power_allocator.c
drivers/thermal/tegra/soctherm.c
drivers/thermal/thermal_hwmon.c
drivers/thermal/x86_pkg_temp_thermal.c
drivers/video/console/dummycon.c
drivers/video/fbdev/Kconfig
drivers/video/fbdev/atmel_lcdfb.c
drivers/video/fbdev/aty/radeon_base.c
drivers/video/fbdev/au1200fb.h
drivers/video/fbdev/auo_k190x.c
drivers/video/fbdev/mmp/core.c
drivers/video/fbdev/mxsfb.c
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
drivers/video/fbdev/omap2/omapfb/dss/dss.c
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c
drivers/video/fbdev/pxa3xx-gcu.c
drivers/video/fbdev/smscufx.c
drivers/video/fbdev/udlfb.c
drivers/video/fbdev/vfb.c
drivers/video/fbdev/vga16fb.c
drivers/video/fbdev/vt8500lcdfb.c
drivers/video/fbdev/wm8505fb.c
drivers/watchdog/Kconfig
drivers/watchdog/Makefile
drivers/watchdog/advantechwdt.c
drivers/watchdog/alim1535_wdt.c
drivers/watchdog/aspeed_wdt.c
drivers/watchdog/at32ap700x_wdt.c [deleted file]
drivers/watchdog/da9062_wdt.c
drivers/watchdog/davinci_wdt.c
drivers/watchdog/dw_wdt.c
drivers/watchdog/eurotechwdt.c
drivers/watchdog/f71808e_wdt.c
drivers/watchdog/ftwdt010_wdt.c [new file with mode: 0644]
drivers/watchdog/gemini_wdt.c [deleted file]
drivers/watchdog/gpio_wdt.c
drivers/watchdog/hpwdt.c
drivers/watchdog/i6300esb.c
drivers/watchdog/ib700wdt.c
drivers/watchdog/imx2_wdt.c
drivers/watchdog/jz4740_wdt.c
drivers/watchdog/mei_wdt.c
drivers/watchdog/mpc8xxx_wdt.c
drivers/watchdog/mt7621_wdt.c
drivers/watchdog/orion_wdt.c
drivers/watchdog/pcwd_pci.c
drivers/watchdog/pcwd_usb.c
drivers/watchdog/rtd119x_wdt.c [new file with mode: 0644]
drivers/watchdog/sp5100_tco.c
drivers/watchdog/sp5100_tco.h
drivers/watchdog/sprd_wdt.c [new file with mode: 0644]
drivers/watchdog/stm32_iwdg.c
drivers/watchdog/sunxi_wdt.c
drivers/watchdog/watchdog_core.c
drivers/watchdog/watchdog_dev.c
drivers/watchdog/wdt_pci.c
drivers/watchdog/xen_wdt.c
fs/affs/dir.c
fs/binfmt_elf.c
fs/exofs/dir.c
fs/ext2/dir.c
fs/ext2/super.c
fs/ext4/dir.c
fs/ext4/inline.c
fs/fat/namei_vfat.c
fs/hfsplus/dir.c
fs/hfsplus/hfsplus_fs.h
fs/hfsplus/inode.c
fs/hfsplus/super.c
fs/inode.c
fs/nfs/inode.c
fs/nilfs2/segbuf.c
fs/nilfs2/segbuf.h
fs/nilfs2/segment.c
fs/nilfs2/segment.h
fs/nilfs2/sufile.c
fs/nilfs2/sufile.h
fs/nilfs2/super.c
fs/nilfs2/sysfs.c
fs/nilfs2/the_nilfs.h
fs/ocfs2/dir.c
fs/pipe.c
fs/proc/array.c
fs/proc/base.c
fs/proc/consoles.c
fs/proc/fd.c
fs/proc/generic.c
fs/proc/inode.c
fs/proc/internal.h
fs/proc/kcore.c
fs/proc/proc_net.c
fs/proc/self.c
fs/proc/thread_self.c
fs/proc/vmcore.c
fs/udf/udftime.c
fs/ufs/dir.c
include/asm-generic/audit_dir_write.h
include/asm-generic/bitops/find.h
include/asm-generic/qrwlock_types.h
include/dt-bindings/clock/jz4770-cgu.h [new file with mode: 0644]
include/linux/bitmap.h
include/linux/build_bug.h
include/linux/compiler-clang.h
include/linux/cpumask.h
include/linux/cpuset.h
include/linux/crash_dump.h
include/linux/fb.h
include/linux/genl_magic_func.h
include/linux/ioport.h
include/linux/iversion.h
include/linux/jump_label.h
include/linux/kallsyms.h
include/linux/kasan.h
include/linux/lockref.h
include/linux/memblock.h
include/linux/module.h
include/linux/mutex.h
include/linux/netdevice.h
include/linux/pipe_fs_i.h
include/linux/platform_data/mlxcpld-hotplug.h [deleted file]
include/linux/platform_data/mlxreg.h [new file with mode: 0644]
include/linux/sched.h
include/linux/sched/mm.h
include/linux/seq_file.h
include/linux/sync_core.h [new file with mode: 0644]
include/linux/sysctl.h
include/linux/uuid.h
include/media/dvb_vb2.h
include/net/erspan.h
include/sound/soc.h
include/uapi/asm-generic/siginfo.h
include/uapi/linux/input-event-codes.h
include/uapi/linux/membarrier.h
include/uapi/linux/uuid.h
include/video/udlfb.h
init/Kconfig
ipc/mqueue.c
ipc/msg.c
ipc/sem.c
ipc/shm.c
ipc/util.c
kernel/async.c
kernel/bpf/core.c
kernel/cgroup/cpuset.c
kernel/compat.c
kernel/configs/tiny.config
kernel/fork.c
kernel/futex.c
kernel/irq/spurious.c
kernel/kcov.c
kernel/module.c
kernel/pid.c
kernel/ptrace.c
kernel/relay.c
kernel/resource.c
kernel/sched/core.c
kernel/sched/fair.c
kernel/sched/membarrier.c
kernel/sched/rt.c
kernel/sched/sched.h
kernel/sched/stats.h
kernel/sched/topology.c
kernel/sysctl.c
kernel/taskstats.c
kernel/time/hrtimer.c
lib/Kconfig.debug
lib/Kconfig.kasan
lib/Makefile
lib/bitmap.c
lib/cpumask.c
lib/find_bit.c
lib/find_bit_benchmark.c [moved from lib/test_find_bit.c with 69% similarity]
lib/stackdepot.c
lib/test_bitmap.c
lib/test_kasan.c
lib/test_sort.c
lib/ubsan.c
lib/ubsan.h
mm/bootmem.c
mm/kasan/kasan.c
mm/kasan/kasan.h
mm/kasan/report.c
mm/ksm.c
mm/maccess.c
mm/memblock.c
mm/memcontrol.c
mm/memory.c
mm/mempool.c
mm/mlock.c
mm/nommu.c
mm/pagewalk.c
mm/process_vm_access.c
mm/slab.c
mm/slub.c
mm/swap.c
mm/userfaultfd.c
mm/vmscan.c
mm/z3fold.c
mm/zbud.c
mm/zpool.c
net/bluetooth/hci_debugfs.c
net/bpf/test_run.c
net/core/ethtool.c
net/ipv4/ip_gre.c
net/ipv6/ip6_gre.c
net/ipv6/mcast.c
net/rds/ib.c
net/sched/cls_u32.c
net/sctp/ipv6.c
net/sctp/protocol.c
samples/bpf/Makefile
samples/bpf/bpf_load.c
samples/bpf/bpf_load.h
samples/bpf/tcbpf2_kern.c
samples/bpf/test_tunnel_bpf.sh
samples/bpf/xdp1_user.c
samples/bpf/xdp_redirect_cpu_user.c
samples/bpf/xdp_redirect_map_user.c
samples/bpf/xdp_redirect_user.c
samples/bpf/xdp_router_ipv4_user.c
samples/bpf/xdp_rxq_info_user.c
samples/bpf/xdp_tx_iptunnel_user.c
scripts/Makefile.kasan
scripts/Makefile.lib
scripts/Makefile.ubsan
scripts/checkpatch.pl
scripts/mod/modpost.c
security/integrity/ima/ima_main.c
security/yama/yama_lsm.c
sound/soc/atmel/sam9g20_wm8731.c
sound/soc/atmel/sam9x5_wm8731.c
sound/soc/codecs/ak4613.c
sound/soc/codecs/dmic.c
sound/soc/codecs/max98373.c
sound/soc/codecs/max98373.h
sound/soc/codecs/sgtl5000.c
sound/soc/codecs/twl4030.c
sound/soc/codecs/twl6040.c
sound/soc/intel/Kconfig
sound/soc/intel/boards/Kconfig
sound/soc/intel/boards/kbl_rt5663_max98927.c
sound/soc/intel/skylake/Makefile
sound/soc/intel/skylake/skl-i2s.h
sound/soc/intel/skylake/skl-messages.c
sound/soc/intel/skylake/skl-nhlt.c
sound/soc/intel/skylake/skl-ssp-clk.c [new file with mode: 0644]
sound/soc/intel/skylake/skl-ssp-clk.h
sound/soc/intel/skylake/skl.h
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
sound/soc/mediatek/mt8173/mt8173-rt5650.c
sound/soc/rockchip/rk3399_gru_sound.c
sound/soc/soc-compress.c
sound/soc/soc-core.c
sound/soc/soc-dapm.c
sound/soc/soc-pcm.c
sound/soc/stm/Kconfig
sound/soc/sunxi/sun8i-codec.c
tools/arch/powerpc/include/uapi/asm/kvm.h
tools/arch/s390/include/uapi/asm/kvm.h
tools/arch/x86/include/asm/cpufeatures.h
tools/arch/x86/include/asm/disabled-features.h
tools/arch/x86/include/asm/required-features.h
tools/include/asm-generic/bitops/find.h
tools/include/uapi/linux/if_link.h [new file with mode: 0644]
tools/include/uapi/linux/kvm.h
tools/include/uapi/linux/netlink.h [new file with mode: 0644]
tools/include/uapi/linux/sched.h
tools/include/uapi/sound/asound.h
tools/lib/bpf/Build
tools/lib/bpf/Makefile
tools/lib/bpf/bpf.c
tools/lib/bpf/bpf.h
tools/lib/bpf/libbpf.c
tools/lib/bpf/libbpf.h
tools/lib/bpf/nlattr.c [new file with mode: 0644]
tools/lib/bpf/nlattr.h [new file with mode: 0644]
tools/lib/find_bit.c
tools/lib/subcmd/pager.c
tools/perf/.gitignore
tools/perf/builtin-record.c
tools/perf/builtin-trace.c
tools/perf/perf.h
tools/perf/util/evsel.c
tools/testing/selftests/bpf/.gitignore
tools/testing/selftests/bpf/Makefile
tools/testing/selftests/bpf/test_verifier.c
tools/testing/selftests/membarrier/membarrier_test.c

index 63c1ad0212fc8624432f1691240443b9015b5d3f..34d3a3359cf4587fb182eaf146d6b1648d6a7188 100644 (file)
@@ -3,7 +3,7 @@ Date:           January 1, 2010
 KernelVersion: 2.6.33
 Contact:       Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 Description:   Some Samsung laptops have different "performance levels"
-               that are can be modified by a function key, and by this
+               that can be modified by a function key, and by this
                sysfs file.  These values don't always make a whole lot
                of sense, but some users like to modify them to keep
                their fans quiet at all costs.  Reading from this file
index 9b55952039a692d8119ce62502af9a4dd071b8e6..9948ec36a204f9927821f529f57353b046efee38 100644 (file)
@@ -3,13 +3,13 @@
 =============
 The interface presented here is not meant for end users. Instead there
 should be a userspace tool that handles all the low-level details, keeps
-database of the authorized devices and prompts user for new connections.
+a database of the authorized devices and prompts users for new connections.
 
 More details about the sysfs interface for Thunderbolt devices can be
 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
 
 Those users who just want to connect any device without any sort of
-manual work, can add following line to
+manual work can add following line to
 ``/etc/udev/rules.d/99-local.rules``::
 
   ACTION=="add", SUBSYSTEM=="thunderbolt", ATTR{authorized}=="0", ATTR{authorized}="1"
@@ -20,7 +20,7 @@ vulnerable to DMA attacks.
 
 Security levels and how to use them
 -----------------------------------
-Starting from Intel Falcon Ridge Thunderbolt controller there are 4
+Starting with Intel Falcon Ridge Thunderbolt controller there are 4
 security levels available. The reason for these is the fact that the
 connected devices can be DMA masters and thus read contents of the host
 memory without CPU and OS knowing about it. There are ways to prevent
@@ -37,14 +37,14 @@ The security levels are as follows:
   user
     User is asked whether the device is allowed to be connected.
     Based on the device identification information available through
-    ``/sys/bus/thunderbolt/devices``. user then can do the decision.
+    ``/sys/bus/thunderbolt/devices``, the user then can make the decision.
     In BIOS settings this is typically called *Unique ID*.
 
   secure
     User is asked whether the device is allowed to be connected. In
     addition to UUID the device (if it supports secure connect) is sent
     a challenge that should match the expected one based on a random key
-    written to ``key`` sysfs attribute. In BIOS settings this is
+    written to the ``key`` sysfs attribute. In BIOS settings this is
     typically called *One time saved key*.
 
   dponly
@@ -78,7 +78,7 @@ When a device is plugged in it will appear in sysfs as follows::
   /sys/bus/thunderbolt/devices/0-1/unique_id   - e0376f00-0300-0100-ffff-ffffffffffff
 
 The ``authorized`` attribute reads 0 which means no PCIe tunnels are
-created yet. The user can authorize the device by simply::
+created yet. The user can authorize the device by simply entering::
 
   # echo 1 > /sys/bus/thunderbolt/devices/0-1/authorized
 
@@ -86,7 +86,7 @@ This will create the PCIe tunnels and the device is now connected.
 
 If the device supports secure connect, and the domain security level is
 set to ``secure``, it has an additional attribute ``key`` which can hold
-a random 32 byte value used for authorization and challenging the device in
+a random 32-byte value used for authorization and challenging the device in
 future connects::
 
   /sys/bus/thunderbolt/devices/0-3/authorized  - 0
@@ -99,12 +99,12 @@ future connects::
 
 Notice the key is empty by default.
 
-If the user does not want to use secure connect it can just ``echo 1``
+If the user does not want to use secure connect they can just ``echo 1``
 to the ``authorized`` attribute and the PCIe tunnels will be created in
-the same way than in ``user`` security level.
+the same way as in the ``user`` security level.
 
 If the user wants to use secure connect, the first time the device is
-plugged a key needs to be created and send to the device::
+plugged a key needs to be created and sent to the device::
 
   # key=$(openssl rand -hex 32)
   # echo $key > /sys/bus/thunderbolt/devices/0-3/key
@@ -121,27 +121,27 @@ device using the same key::
 
 If the challenge the device returns back matches the one we expect based
 on the key, the device is connected and the PCIe tunnels are created.
-However, if the challenge failed no tunnels are created and error is
+However, if the challenge fails no tunnels are created and error is
 returned to the user.
 
-If the user still wants to connect the device it can either approve
-the device without a key or write new key and write 1 to the
+If the user still wants to connect the device they can either approve
+the device without a key or write new key and write 1 to the
 ``authorized`` file to get the new key stored on the device NVM.
 
 Upgrading NVM on Thunderbolt device or host
 -------------------------------------------
-Since most of the functionality is handled in firmware running on a
+Since most of the functionality is handled in firmware running on a
 host controller or a device, it is important that the firmware can be
 upgraded to the latest where possible bugs in it have been fixed.
 Typically OEMs provide this firmware from their support site.
 
-There is also a central site which has links where to download firmwares
+There is also a central site which has links where to download firmware
 for some machines:
 
   `Thunderbolt Updates <https://thunderbolttechnology.net/updates>`_
 
-Before you upgrade firmware on a device or host, please make sure it is
-the suitable. Failing to do that may render the device (or host) in a
+Before you upgrade firmware on a device or host, please make sure it is a
+suitable upgrade. Failing to do that may render the device (or host) in a
 state where it cannot be used properly anymore without special tools!
 
 Host NVM upgrade on Apple Macs is not supported.
@@ -151,7 +151,7 @@ Thunderbolt device so that the host controller appears. It does not
 matter which device is connected (unless you are upgrading NVM on a
 device - then you need to connect that particular device).
 
-Note OEM-specific method to power the controller up ("force power") may
+Note an OEM-specific method to power the controller up ("force power") may
 be available for your system in which case there is no need to plug in a
 Thunderbolt device.
 
@@ -171,7 +171,7 @@ it comes back the driver notices it and initiates a full power cycle.
 After a while the host controller appears again and this time it should
 be fully functional.
 
-We can verify that the new NVM firmware is active by running following
+We can verify that the new NVM firmware is active by running the following
 commands::
 
   # cat /sys/bus/thunderbolt/devices/0-0/nvm_authenticate
@@ -179,38 +179,38 @@ commands::
   # cat /sys/bus/thunderbolt/devices/0-0/nvm_version
   18.0
 
-If ``nvm_authenticate`` contains anything else than 0x0 it is the error
+If ``nvm_authenticate`` contains anything other than 0x0 it is the error
 code from the last authentication cycle, which means the authentication
 of the NVM image failed.
 
 Note names of the NVMem devices ``nvm_activeN`` and ``nvm_non_activeN``
-depends on the order they are registered in the NVMem subsystem. N in
+depend on the order they are registered in the NVMem subsystem. N in
 the name is the identifier added by the NVMem subsystem.
 
 Upgrading NVM when host controller is in safe mode
 --------------------------------------------------
 If the existing NVM is not properly authenticated (or is missing) the
-host controller goes into safe mode which means that only available
-functionality is flashing new NVM image. When in this mode the reading
+host controller goes into safe mode which means that the only available
+functionality is flashing a new NVM image. When in this mode, reading
 ``nvm_version`` fails with ``ENODATA`` and the device identification
 information is missing.
 
 To recover from this mode, one needs to flash a valid NVM image to the
-host host controller in the same way it is done in the previous chapter.
+host controller in the same way it is done in the previous chapter.
 
 Networking over Thunderbolt cable
 ---------------------------------
-Thunderbolt technology allows software communication across two hosts
+Thunderbolt technology allows software communication between two hosts
 connected by a Thunderbolt cable.
 
-It is possible to tunnel any kind of traffic over Thunderbolt link but
+It is possible to tunnel any kind of traffic over Thunderbolt link but
 currently we only support Apple ThunderboltIP protocol.
 
-If the other host is running Windows or macOS only thing you need to
-do is to connect Thunderbolt cable between the two hosts, the
-``thunderbolt-net`` is loaded automatically. If the other host is also
-Linux you should load ``thunderbolt-net`` manually on one host (it does
-not matter which one)::
+If the other host is running Windows or macOS, the only thing you need to
+do is to connect a Thunderbolt cable between the two hosts; the
+``thunderbolt-net`` driver is loaded automatically. If the other host is
+also Linux you should load ``thunderbolt-net`` manually on one host (it
+does not matter which one)::
 
   # modprobe thunderbolt-net
 
@@ -220,12 +220,12 @@ is built-in to the kernel image, there is no need to do anything.
 The driver will create one virtual ethernet interface per Thunderbolt
 port which are named like ``thunderbolt0`` and so on. From this point
 you can either use standard userspace tools like ``ifconfig`` to
-configure the interface or let your GUI to handle it automatically.
+configure the interface or let your GUI handle it automatically.
 
 Forcing power
 -------------
 Many OEMs include a method that can be used to force the power of a
-thunderbolt controller to an "On" state even if nothing is connected.
+Thunderbolt controller to an "On" state even if nothing is connected.
 If supported by your machine this will be exposed by the WMI bus with
 a sysfs attribute called "force_power".
 
index cefef855dea4513e5a35bb2da0fb9fd00f2b8209..84cbb302f2b56e1fe9b4ecc46dfb2f94b1ff392d 100644 (file)
@@ -516,4 +516,35 @@ A: LLVM has a -mcpu selector for the BPF back end in order to allow the
    By the way, the BPF kernel selftests run with -mcpu=probe for better
    test coverage.
 
+Q: In some cases clang flag "-target bpf" is used but in other cases the
+   default clang target, which matches the underlying architecture, is used.
+   What is the difference and when I should use which?
+
+A: Although LLVM IR generation and optimization try to stay architecture
+   independent, "-target <arch>" still has some impact on generated code:
+
+     - BPF program may recursively include header file(s) with file scope
+       inline assembly codes. The default target can handle this well,
+       while bpf target may fail if bpf backend assembler does not
+       understand these assembly codes, which is true in most cases.
+
+     - When compiled without -g, additional elf sections, e.g.,
+       .eh_frame and .rela.eh_frame, may be present in the object file
+       with default target, but not with bpf target.
+
+     - The default target may turn a C switch statement into a switch table
+       lookup and jump operation. Since the switch table is placed
+       in the global readonly section, the bpf program will fail to load.
+       The bpf target does not support switch table optimization.
+       The clang option "-fno-jump-tables" can be used to disable
+       switch table generation.
+
+   You should use default target when:
+
+     - Your program includes a header file, e.g., ptrace.h, which eventually
+       pulls in some header files containing file scope host assembly codes.
+     - You can add "-fno-jump-tables" to work around the switch table issue.
+
+   Otherwise, you can use bpf target.
+
 Happy BPF hacking!
index 24aacf8948c51626a22d844ddd95f752da4206f3..e0d013a2e66da64999935d94f832f4d49e88ba90 100644 (file)
@@ -2,22 +2,35 @@
 
 Required properties:
 
-- compatible:  Should be set to one of the following:
-               marvell,armada370-thermal
-               marvell,armada375-thermal
-               marvell,armada380-thermal
-               marvell,armadaxp-thermal
+- compatible: Should be set to one of the following:
+    * marvell,armada370-thermal
+    * marvell,armada375-thermal
+    * marvell,armada380-thermal
+    * marvell,armadaxp-thermal
+    * marvell,armada-ap806-thermal
+    * marvell,armada-cp110-thermal
 
-- reg:         Device's register space.
-               Two entries are expected, see the examples below.
-               The first one is required for the sensor register;
-               the second one is required for the control register
-               to be used for sensor initialization (a.k.a. calibration).
+- reg: Device's register space.
+  Two entries are expected, see the examples below. The first one points
+  to the status register (4B). The second one points to the control
+  registers (8B).
+  Note: The compatibles marvell,armada370-thermal,
+  marvell,armada380-thermal, and marvell,armadaxp-thermal must point to
+  "control MSB/control 1", with size of 4 (deprecated binding), or point
+  to "control LSB/control 0" with size of 8 (current binding). All other
+  compatibles must point to "control LSB/control 0" with size of 8.
 
-Example:
+Examples:
 
+       /* Legacy bindings */
        thermal@d0018300 {
                compatible = "marvell,armada370-thermal";
-                reg = <0xd0018300 0x4
+               reg = <0xd0018300 0x4
                       0xd0018304 0x4>;
        };
+
+       ap_thermal: thermal@6f8084 {
+               compatible = "marvell,armada-ap806-thermal";
+               reg = <0x6f808C 0x4>,
+                     <0x6f8084 0x8>;
+       };
index a8e52c8ccfcca623040a38ebd8f27063c3f96c72..349e635f2d87e0a8421bcaaea1ef18e12b73dff2 100644 (file)
@@ -6,6 +6,7 @@ Required properties:
                           "renesas,rcar-thermal" (without thermal-zone) as fallback.
                          Examples with soctypes are:
                            - "renesas,thermal-r8a73a4" (R-Mobile APE6)
+                           - "renesas,thermal-r8a7743" (RZ/G1M)
                            - "renesas,thermal-r8a7779" (R-Car H1)
                            - "renesas,thermal-r8a7790" (R-Car H2)
                            - "renesas,thermal-r8a7791" (R-Car M2-W)
index b1fa64a1d4d0f6a9a20945cb7be0dc9e7e936fd8..ae850d6c0ad3779f2e9fa0f1ba60f49b5b864e8a 100644 (file)
@@ -125,6 +125,7 @@ focaltech   FocalTech Systems Co.,Ltd
 friendlyarm    Guangzhou FriendlyARM Computer Tech Co., Ltd
 fsl    Freescale Semiconductor
 fujitsu        Fujitsu Ltd.
+gcw Game Consoles Worldwide
 ge     General Electric Company
 geekbuying     GeekBuying
 gef    GE Fanuc Intelligent Platforms Embedded Systems, Inc.
diff --git a/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt b/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
deleted file mode 100644 (file)
index bc4b865..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
-Cortina Systems Gemini SoC Watchdog
-
-Required properties:
-- compatible : must be "cortina,gemini-watchdog"
-- reg : shall contain base register location and length
-- interrupts : shall contain the interrupt for the watchdog
-
-Optional properties:
-- timeout-sec : the default watchdog timeout in seconds.
-
-Example:
-
-watchdog@41000000 {
-       compatible = "cortina,gemini-watchdog";
-       reg = <0x41000000 0x1000>;
-       interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
-};
similarity index 55%
rename from Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt
rename to Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt
index bc4b865d178b4f386ef9fdb9bb4f81e14816d214..9ecdb502e605949f79b88fa7ab03ff90e98b590a 100644 (file)
@@ -1,7 +1,12 @@
-Cortina Systems Gemini SoC Watchdog
+Faraday Technology FTWDT010 watchdog
+
+This is an IP part from Faraday Technology found in the Gemini
+SoCs and others.
 
 Required properties:
-- compatible : must be "cortina,gemini-watchdog"
+- compatible : must be one of
+  "faraday,ftwdt010"
+  "cortina,gemini-watchdog", "faraday,ftwdt010"
 - reg : shall contain base register location and length
 - interrupts : shall contain the interrupt for the watchdog
 
@@ -11,7 +16,7 @@ Optional properties:
 Example:
 
 watchdog@41000000 {
-       compatible = "cortina,gemini-watchdog";
+       compatible = "faraday,ftwdt010";
        reg = <0x41000000 0x1000>;
        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 };
index 3c7a1cd13b1011f37753f67905561843ce984370..cb44918f01a8b61b9ebf7444d372cf74c4a6a075 100644 (file)
@@ -1,7 +1,7 @@
-Ingenic Watchdog Timer (WDT) Controller for JZ4740
+Ingenic Watchdog Timer (WDT) Controller for JZ4740 & JZ4780
 
 Required properties:
-compatible: "ingenic,jz4740-watchdog"
+compatible: "ingenic,jz4740-watchdog" or "ingenic,jz4780-watchdog"
 reg: Register address and length for watchdog registers
 
 Example:
diff --git a/Documentation/devicetree/bindings/watchdog/realtek,rtd119x.txt b/Documentation/devicetree/bindings/watchdog/realtek,rtd119x.txt
new file mode 100644 (file)
index 0000000..0565305
--- /dev/null
@@ -0,0 +1,17 @@
+Realtek RTD1295 Watchdog
+========================
+
+Required properties:
+
+- compatible :  Should be "realtek,rtd1295-watchdog"
+- reg        :  Specifies the physical base address and size of registers
+- clocks     :  Specifies one clock input
+
+
+Example:
+
+       watchdog@98007680 {
+               compatible = "realtek,rtd1295-watchdog";
+               reg = <0x98007680 0x100>;
+               clocks = <&osc27M>;
+       };
index bf6d1ca58af7d1989deda93d037b57a23ffd426d..74b2f03c151553f5ce78fd89373f07b09549b2c8 100644 (file)
@@ -4,10 +4,11 @@ Required properties:
 - compatible : Should be "renesas,<soctype>-wdt", and
               "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback.
               Examples with soctypes are:
+                - "renesas,r7s72100-wdt" (RZ/A1)
                 - "renesas,r8a7795-wdt" (R-Car H3)
                 - "renesas,r8a7796-wdt" (R-Car M3-W)
+                - "renesas,r8a77970-wdt" (R-Car V3M)
                 - "renesas,r8a77995-wdt" (R-Car D3)
-                - "renesas,r7s72100-wdt" (RZ/A1)
 
   When compatible with the generic version, nodes must list the SoC-specific
   version corresponding to the platform first, followed by the generic
diff --git a/Documentation/devicetree/bindings/watchdog/sprd-wdt.txt b/Documentation/devicetree/bindings/watchdog/sprd-wdt.txt
new file mode 100644 (file)
index 0000000..aeaf3e0
--- /dev/null
@@ -0,0 +1,19 @@
+Spreadtrum SoCs Watchdog timer
+
+Required properties:
+- compatible : Should be "sprd,sp9860-wdt".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : Exactly one interrupt specifier.
+- timeout-sec : Contain the default watchdog timeout in seconds.
+- clock-names : Contain the input clock names.
+- clocks : Phandles to input clocks.
+
+Example:
+       watchdog: watchdog@40310000 {
+               compatible = "sprd,sp9860-wdt";
+               reg = <0 0x40310000 0 0x1000>;
+               interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+               timeout-sec = <12>;
+               clock-names = "enable", "rtc_enable";
+               clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>;
+       };
index 52844a58cc8a73cc4d619c384e2d0016aa002b59..ff675a1b142223af49c7f2fad5dbbe82d7c7dafa 100644 (file)
@@ -56,8 +56,6 @@ Following extra configs variables are introduced:
 
   CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA    - enable the PIO+DBDMA mode
   CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA  - enable the MWDMA mode
-  CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON - set Burstable FIFO in DBDMA
-                                           controller
 
 
 SUPPORTED IDE MODES
@@ -82,11 +80,9 @@ CONFIG_IDE_GENERIC=y
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_BLK_DEV_GENERIC=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDE_AU1XXX=y
 CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
 CONFIG_BLK_DEV_IDEDMA=y
-CONFIG_IDEDMA_AUTO=y
 
 Also define 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to enable
 the burst support on DBDMA controller.
@@ -94,16 +90,13 @@ the burst support on DBDMA controller.
 If the used system need the USB support enable the following kernel configs for
 high IDE to USB throughput.
 
-CONFIG_BLK_DEV_IDEDISK=y
 CONFIG_IDE_GENERIC=y
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_BLK_DEV_GENERIC=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDE_AU1XXX=y
 CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
 CONFIG_BLK_DEV_IDEDMA=y
-CONFIG_IDEDMA_AUTO=y
 
 Also undefine 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to
 disable the burst support on DBDMA controller.
index 3f2c40d8e6aa895452d6cf15977b080f4d79360e..a553d4e4a0fb4c6f5ef675629edb2aa1b0a6f71a 100644 (file)
@@ -508,7 +508,7 @@ tcp_rmem - vector of 3 INTEGERs: min, default, max
        min: Minimal size of receive buffer used by TCP sockets.
        It is guaranteed to each TCP socket, even under moderate memory
        pressure.
-       Default: 1 page
+       Default: 4K
 
        default: initial size of receive buffer used by TCP sockets.
        This value overrides net.core.rmem_default used by other protocols.
@@ -667,7 +667,7 @@ tcp_window_scaling - BOOLEAN
 tcp_wmem - vector of 3 INTEGERs: min, default, max
        min: Amount of memory reserved for send buffers for TCP sockets.
        Each TCP socket has rights to use it due to fact of its birth.
-       Default: 1 page
+       Default: 4K
 
        default: initial size of send buffer used by TCP sockets.  This
        value overrides net.core.wmem_default used by other protocols.
index a430f6eee7569570b8e81c5399c6a14dc3b4480c..1c9fe657ed01b049e3e8a963177cbd85f63c180c 100644 (file)
@@ -24,6 +24,7 @@ Below are the essential guides that every developer should read.
    development-process
    submitting-patches
    coding-style
+   maintainer-pgp-guide
    email-clients
    kernel-enforcement-statement
    kernel-driver-statement
index b8cac85a40011c7d857672115dcaf5f33989d096..3fb28de556e41dca7c17de616dedae788721b5f6 100644 (file)
@@ -58,7 +58,7 @@ On-line docs
     * Title: **Linux Kernel Mailing List Glossary**
 
       :Author: various
-      :URL: http://kernelnewbies.org/glossary/
+      :URL: https://kernelnewbies.org/KernelGlossary
       :Date: rolling version
       :Keywords: glossary, terms, linux-kernel.
       :Description: From the introduction: "This glossary is intended as
diff --git a/Documentation/process/maintainer-pgp-guide.rst b/Documentation/process/maintainer-pgp-guide.rst
new file mode 100644 (file)
index 0000000..b453561
--- /dev/null
@@ -0,0 +1,929 @@
+.. _pgpguide:
+
+===========================
+Kernel Maintainer PGP guide
+===========================
+
+:Author: Konstantin Ryabitsev <konstantin@linuxfoundation.org>
+
+This document is aimed at Linux kernel developers, and especially at
+subsystem maintainers. It contains a subset of information discussed in
+the more general "`Protecting Code Integrity`_" guide published by the
+Linux Foundation. Please read that document for more in-depth discussion
+on some of the topics mentioned in this guide.
+
+.. _`Protecting Code Integrity`: https://github.com/lfit/itpol/blob/master/protecting-code-integrity.md
+
+The role of PGP in Linux Kernel development
+===========================================
+
+PGP helps ensure the integrity of the code that is produced by the Linux
+kernel development community and, to a lesser degree, establish trusted
+communication channels between developers via PGP-signed email exchange.
+
+The Linux kernel source code is available in two main formats:
+
+- Distributed source repositories (git)
+- Periodic release snapshots (tarballs)
+
+Both git repositories and tarballs carry PGP signatures of the kernel
+developers who create official kernel releases. These signatures offer a
+cryptographic guarantee that downloadable versions made available via
+kernel.org or any other mirrors are identical to what these developers
+have on their workstations. To this end:
+
+- git repositories provide PGP signatures on all tags
+- tarballs provide detached PGP signatures with all downloads
+
+.. _devs_not_infra:
+
+Trusting the developers, not infrastructure
+-------------------------------------------
+
+Ever since the 2011 compromise of core kernel.org systems, the main
+operating principle of the Kernel Archives project has been to assume
+that any part of the infrastructure can be compromised at any time. For
+this reason, the administrators have taken deliberate steps to emphasize
+that trust must always be placed with developers and never with the code
+hosting infrastructure, regardless of how good the security practices
+for the latter may be.
+
+The above guiding principle is the reason why this guide is needed. We
+want to make sure that by placing trust into developers we do not simply
+shift the blame for potential future security incidents to someone else.
+The goal is to provide a set of guidelines developers can use to create
+a secure working environment and safeguard the PGP keys used to
+establish the integrity of the Linux kernel itself.
+
+.. _pgp_tools:
+
+PGP tools
+=========
+
+Use GnuPG v2
+------------
+
+Your distro should already have GnuPG installed by default, you just
+need to verify that you are using version 2.x and not the legacy 1.4
+release -- many distributions still package both, with the default
+``gpg`` command invoking GnuPG v.1. To check, run::
+
+    $ gpg --version | head -n1
+
+If you see ``gpg (GnuPG) 1.4.x``, then you are using GnuPG v.1. Try the
+``gpg2`` command (if you don't have it, you may need to install the
+gnupg2 package)::
+
+    $ gpg2 --version | head -n1
+
+If you see ``gpg (GnuPG) 2.x.x``, then you are good to go. This guide
+will assume you have the version 2.2 of GnuPG (or later). If you are
+using version 2.0 of GnuPG, then some of the commands in this guide will
+not work, and you should consider installing the latest 2.2 version of
+GnuPG. Versions of gnupg-2.1.11 and later should be compatible for the
+purposes of this guide as well.
+
+If you have both ``gpg`` and ``gpg2`` commands, you should make sure you
+are always using GnuPG v2, not the legacy version. You can enforce this
+by setting the appropriate alias::
+
+    $ alias gpg=gpg2
+
+You can put that in your ``.bashrc`` to make sure it's always the case.
+
+Configure gpg-agent options
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The GnuPG agent is a helper tool that will start automatically whenever
+you use the ``gpg`` command and run in the background with the purpose
+of caching the private key passphrase. There are two options you should
+know in order to tweak when the passphrase should be expired from cache:
+
+- ``default-cache-ttl`` (seconds): If you use the same key again before
+  the time-to-live expires, the countdown will reset for another period.
+  The default is 600 (10 minutes).
+- ``max-cache-ttl`` (seconds): Regardless of how recently you've used
+  the key since initial passphrase entry, if the maximum time-to-live
+  countdown expires, you'll have to enter the passphrase again. The
+  default is 30 minutes.
+
+If you find either of these defaults too short (or too long), you can
+edit your ``~/.gnupg/gpg-agent.conf`` file to set your own values::
+
+    # set to 30 minutes for regular ttl, and 2 hours for max ttl
+    default-cache-ttl 1800
+    max-cache-ttl 7200
+
+.. note::
+
+    It is no longer necessary to start gpg-agent manually at the
+    beginning of your shell session. You may want to check your rc files
+    to remove anything you had in place for older versions of GnuPG, as
+    it may not be doing the right thing any more.
+
+Set up a refresh cronjob
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+You will need to regularly refresh your keyring in order to get the
+latest changes on other people's public keys, which is best done with a
+daily cronjob::
+
+    @daily /usr/bin/gpg2 --refresh >/dev/null 2>&1
+
+Check the full path to your ``gpg`` or ``gpg2`` command and use the
+``gpg2`` command if regular ``gpg`` for you is the legacy GnuPG v.1.
+
+.. _master_key:
+
+Protect your master PGP key
+===========================
+
+This guide assumes that you already have a PGP key that you use for Linux
+kernel development purposes. If you do not yet have one, please see the
+"`Protecting Code Integrity`_" document mentioned earlier for guidance
+on how to create a new one.
+
+You should also make a new key if your current one is weaker than 2048 bits
+(RSA).
+
+Master key vs. Subkeys
+----------------------
+
+Subkeys are fully independent PGP keypairs that are tied to the "master"
+key using certifying key signatures (certificates). It is important to
+understand the following:
+
+1. There are no technical differences between the "master key" and "subkeys."
+2. At creation time, we assign functional limitations to each key by
+   giving it specific capabilities.
+3. A PGP key can have 4 capabilities:
+
+   - **[S]** key can be used for signing
+   - **[E]** key can be used for encryption
+   - **[A]** key can be used for authentication
+   - **[C]** key can be used for certifying other keys
+
+4. A single key may have multiple capabilities.
+5. A subkey is fully independent from the master key. A message
+   encrypted to a subkey cannot be decrypted with the master key. If you
+   lose your private subkey, it cannot be recreated from the master key
+   in any way.
+
+The key carrying the **[C]** (certify) capability is considered the
+"master" key because it is the only key that can be used to indicate
+relationship with other keys. Only the **[C]** key can be used to:
+
+- add or revoke other keys (subkeys) with S/E/A capabilities
+- add, change or revoke identities (uids) associated with the key
+- add or change the expiration date on itself or any subkey
+- sign other people's keys for web of trust purposes
+
+By default, GnuPG creates the following when generating new keys:
+
+- A master key carrying both Certify and Sign capabilities (**[SC]**)
+- A separate subkey with the Encryption capability (**[E]**)
+
+If you used the default parameters when generating your key, then that
+is what you will have. You can verify by running ``gpg --list-secret-keys``,
+for example::
+
+    sec   rsa2048 2018-01-23 [SC] [expires: 2020-01-23]
+          000000000000000000000000AAAABBBBCCCCDDDD
+    uid           [ultimate] Alice Dev <adev@kernel.org>
+    ssb   rsa2048 2018-01-23 [E] [expires: 2020-01-23]
+
+Any key carrying the **[C]** capability is your master key, regardless
+of any other capabilities it may have assigned to it.
+
+The long line under the ``sec`` entry is your key fingerprint --
+whenever you see ``[fpr]`` in the examples below, that 40-character
+string is what it refers to.
+
+Ensure your passphrase is strong
+--------------------------------
+
+GnuPG uses passphrases to encrypt your private keys before storing them on
+disk. This way, even if your ``.gnupg`` directory is leaked or stolen in
+its entirety, the attackers cannot use your private keys without first
+obtaining the passphrase to decrypt them.
+
+It is absolutely essential that your private keys are protected by a
+strong passphrase. To set it or change it, use::
+
+    $ gpg --change-passphrase [fpr]
+
+Create a separate Signing subkey
+--------------------------------
+
+Our goal is to protect your master key by moving it to offline media, so
+if you only have a combined **[SC]** key, then you should create a separate
+signing subkey::
+
+    $ gpg --quick-add-key [fpr] ed25519 sign
+
+Remember to tell the keyservers about this change, so others can pull down
+your new subkey::
+
+    $ gpg --send-key [fpr]
+
+.. note:: ECC support in GnuPG
+
+    GnuPG 2.1 and later has full support for Elliptic Curve
+    Cryptography, with ability to combine ECC subkeys with traditional
+    RSA master keys. The main upside of ECC cryptography is that it is
+    much faster computationally and creates much smaller signatures when
+    compared byte for byte with 2048+ bit RSA keys. Unless you plan on
+    using a smartcard device that does not support ECC operations, we
+    recommend that you create an ECC signing subkey for your kernel
+    work.
+
+    If for some reason you prefer to stay with RSA subkeys, just replace
+    "ed25519" with "rsa2048" in the above command.
+
+
+Back up your master key for disaster recovery
+---------------------------------------------
+
+The more signatures you have on your PGP key from other developers, the
+more reasons you have to create a backup version that lives on something
+other than digital media, for disaster recovery reasons.
+
+The best way to create a printable hardcopy of your private key is by
+using the ``paperkey`` software written for this very purpose. See ``man
+paperkey`` for more details on the output format and its benefits over
+other solutions. Paperkey should already be packaged for most
+distributions.
+
+Run the following command to create a hardcopy backup of your private
+key::
+
+    $ gpg --export-secret-key [fpr] | paperkey -o /tmp/key-backup.txt
+
+Print out that file (or pipe the output straight to lpr), then take a
+pen and write your passphrase on the margin of the paper. **This is
+strongly recommended** because the key printout is still encrypted with
+that passphrase, and if you ever change it you will not remember what it
+used to be when you had created the backup -- *guaranteed*.
+
+Put the resulting printout and the hand-written passphrase into an envelope
+and store in a secure and well-protected place, preferably away from your
+home, such as your bank vault.
+
+.. note::
+
+    Your printer is probably no longer a simple dumb device connected to
+    your parallel port, but since the output is still encrypted with
+    your passphrase, printing out even to "cloud-integrated" modern
+    printers should remain a relatively safe operation. One option is to
+    change the passphrase on your master key immediately after you are
+    done with paperkey.
+
+Back up your whole GnuPG directory
+----------------------------------
+
+.. warning::
+
+    **!!!Do not skip this step!!!**
+
+It is important to have a readily available backup of your PGP keys
+should you need to recover them. This is different from the
+disaster-level preparedness we did with ``paperkey``. You will also rely
+on these external copies whenever you need to use your Certify key --
+such as when making changes to your own key or signing other people's
+keys after conferences and summits.
+
+Start by getting a small USB "thumb" drive (preferably two!) that you
+will use for backup purposes. You will need to encrypt them using LUKS
+-- refer to your distro's documentation on how to accomplish this.
+
+For the encryption passphrase, you can use the same one as on your
+master key.
+
+Once the encryption process is over, re-insert the USB drive and make
+sure it gets properly mounted. Copy your entire ``.gnupg`` directory
+over to the encrypted storage::
+
+    $ cp -a ~/.gnupg /media/disk/foo/gnupg-backup
+
+You should now test to make sure everything still works::
+
+    $ gpg --homedir=/media/disk/foo/gnupg-backup --list-key [fpr]
+
+If you don't get any errors, then you should be good to go. Unmount the
+USB drive, distinctly label it so you don't blow it away next time you
+need to use a random USB drive, and put in a safe place -- but not too
+far away, because you'll need to use it every now and again for things
+like editing identities, adding or revoking subkeys, or signing other
+people's keys.
+
+Remove the master key from  your homedir
+----------------------------------------
+
+The files in our home directory are not as well protected as we like to
+think.  They can be leaked or stolen via many different means:
+
+- by accident when making quick homedir copies to set up a new workstation
+- by systems administrator negligence or malice
+- via poorly secured backups
+- via malware in desktop apps (browsers, pdf viewers, etc)
+- via coercion when crossing international borders
+
+Protecting your key with a good passphrase greatly helps reduce the risk
+of any of the above, but passphrases can be discovered via keyloggers,
+shoulder-surfing, or any number of other means. For this reason, the
+recommended setup is to remove your master key from your home directory
+and store it on offline storage.
+
+.. warning::
+
+    Please see the previous section and make sure you have backed up
+    your GnuPG directory in its entirety. What we are about to do will
+    render your key useless if you do not have a usable backup!
+
+First, identify the keygrip of your master key::
+
+    $ gpg --with-keygrip --list-key [fpr]
+
+The output will be something like this::
+
+    pub   rsa2048 2018-01-24 [SC] [expires: 2020-01-24]
+          000000000000000000000000AAAABBBBCCCCDDDD
+          Keygrip = 1111000000000000000000000000000000000000
+    uid           [ultimate] Alice Dev <adev@kernel.org>
+    sub   rsa2048 2018-01-24 [E] [expires: 2020-01-24]
+          Keygrip = 2222000000000000000000000000000000000000
+    sub   ed25519 2018-01-24 [S]
+          Keygrip = 3333000000000000000000000000000000000000
+
+Find the keygrip entry that is beneath the ``pub`` line (right under the
+master key fingerprint). This will correspond directly to a file in your
+``~/.gnupg`` directory::
+
+    $ cd ~/.gnupg/private-keys-v1.d
+    $ ls
+    1111000000000000000000000000000000000000.key
+    2222000000000000000000000000000000000000.key
+    3333000000000000000000000000000000000000.key
+
+All you have to do is simply remove the .key file that corresponds to
+the master keygrip::
+
+    $ cd ~/.gnupg/private-keys-v1.d
+    $ rm 1111000000000000000000000000000000000000.key
+
+Now, if you issue the ``--list-secret-keys`` command, it will show that
+the master key is missing (the ``#`` indicates it is not available)::
+
+    $ gpg --list-secret-keys
+    sec#  rsa2048 2018-01-24 [SC] [expires: 2020-01-24]
+          000000000000000000000000AAAABBBBCCCCDDDD
+    uid           [ultimate] Alice Dev <adev@kernel.org>
+    ssb   rsa2048 2018-01-24 [E] [expires: 2020-01-24]
+    ssb   ed25519 2018-01-24 [S]
+
+You should also remove any ``secring.gpg`` files in the ``~/.gnupg``
+directory, which are left over from earlier versions of GnuPG.
+
+If you don't have the "private-keys-v1.d" directory
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+If you do not have a ``~/.gnupg/private-keys-v1.d`` directory, then your
+secret keys are still stored in the legacy ``secring.gpg`` file used by
+GnuPG v1. Making any changes to your key, such as changing the
+passphrase or adding a subkey, should automatically convert the old
+``secring.gpg`` format to use ``private-keys-v1.d`` instead.
+
+Once you get that done, make sure to delete the obsolete ``secring.gpg``
+file, which still contains your private keys.
+
+.. _smartcards:
+
+Move the subkeys to a dedicated crypto device
+=============================================
+
+Even though the master key is now safe from being leaked or stolen, the
+subkeys are still in your home directory. Anyone who manages to get
+their hands on those will be able to decrypt your communication or fake
+your signatures (if they know the passphrase). Furthermore, each time a
+GnuPG operation is performed, the keys are loaded into system memory and
+can be stolen from there by sufficiently advanced malware (think
+Meltdown and Spectre).
+
+The best way to completely protect your keys is to move them to a
+specialized hardware device that is capable of smartcard operations.
+
+The benefits of smartcards
+--------------------------
+
+A smartcard contains a cryptographic chip that is capable of storing
+private keys and performing crypto operations directly on the card
+itself. Because the key contents never leave the smartcard, the
+operating system of the computer into which you plug in the hardware
+device is not able to retrieve the private keys themselves. This is very
+different from the encrypted USB storage device we used earlier for
+backup purposes -- while that USB device is plugged in and mounted, the
+operating system is able to access the private key contents.
+
+Using external encrypted USB media is not a substitute to having a
+smartcard-capable device.
+
+Available smartcard devices
+---------------------------
+
+Unless all your laptops and workstations have smartcard readers, the
+easiest is to get a specialized USB device that implements smartcard
+functionality.  There are several options available:
+
+- `Nitrokey Start`_: Open hardware and Free Software, based on FSI
+  Japan's `Gnuk`_. Offers support for ECC keys, but fewest security
+  features (such as resistance to tampering or some side-channel
+  attacks).
+- `Nitrokey Pro`_: Similar to the Nitrokey Start, but more
+  tamper-resistant and offers more security features, but no ECC
+  support.
+- `Yubikey 4`_: proprietary hardware and software, but cheaper than
+  Nitrokey Pro and comes available in the USB-C form that is more useful
+  with newer laptops. Offers additional security features such as FIDO
+  U2F, but no ECC.
+
+`LWN has a good review`_ of some of the above models, as well as several
+others. If you want to use ECC keys, your best bet among commercially
+available devices is the Nitrokey Start.
+
+.. _`Nitrokey Start`: https://shop.nitrokey.com/shop/product/nitrokey-start-6
+.. _`Nitrokey Pro`: https://shop.nitrokey.com/shop/product/nitrokey-pro-3
+.. _`Yubikey 4`: https://www.yubico.com/product/yubikey-4-series/
+.. _Gnuk: http://www.fsij.org/doc-gnuk/
+.. _`LWN has a good review`: https://lwn.net/Articles/736231/
+
+Configure your smartcard device
+-------------------------------
+
+Your smartcard device should Just Work (TM) the moment you plug it into
+any modern Linux workstation. You can verify it by running::
+
+    $ gpg --card-status
+
+If you see full smartcard details, then you are good to go.
+Unfortunately, troubleshooting all possible reasons why things may not
+be working for you is way beyond the scope of this guide. If you are
+having trouble getting the card to work with GnuPG, please seek help via
+usual support channels.
+
+To configure your smartcard, you will need to use the GnuPG menu system, as
+there are no convenient command-line switches::
+
+    $ gpg --card-edit
+    [...omitted...]
+    gpg/card> admin
+    Admin commands are allowed
+    gpg/card> passwd
+
+You should set the user PIN (1), Admin PIN (3), and the Reset Code (4).
+Please make sure to record and store these in a safe place -- especially
+the Admin PIN and the Reset Code (which allows you to completely wipe
+the smartcard).  You so rarely need to use the Admin PIN, that you will
+inevitably forget what it is if you do not record it.
+
+Getting back to the main card menu, you can also set other values (such
+as name, sex, login data, etc), but it's not necessary and will
+additionally leak information about your smartcard should you lose it.
+
+.. note::
+
+    Despite having the name "PIN", neither the user PIN nor the admin
+    PIN on the card need to be numbers.
+
+Move the subkeys to your smartcard
+----------------------------------
+
+Exit the card menu (using "q") and save all changes. Next, let's move
+your subkeys onto the smartcard. You will need both your PGP key
+passphrase and the admin PIN of the card for most operations::
+
+    $ gpg --edit-key [fpr]
+
+    Secret subkeys are available.
+
+    pub  rsa2048/AAAABBBBCCCCDDDD
+         created: 2018-01-23  expires: 2020-01-23  usage: SC
+         trust: ultimate      validity: ultimate
+    ssb  rsa2048/1111222233334444
+         created: 2018-01-23  expires: never       usage: E
+    ssb  ed25519/5555666677778888
+         created: 2017-12-07  expires: never       usage: S
+    [ultimate] (1). Alice Dev <adev@kernel.org>
+
+    gpg>
+
+Using ``--edit-key`` puts us into the menu mode again, and you will
+notice that the key listing is a little different. From here on, all
+commands are done from inside this menu mode, as indicated by ``gpg>``.
+
+First, let's select the key we'll be putting onto the card -- you do
+this by typing ``key 1`` (it's the first one in the listing, the **[E]**
+subkey)::
+
+    gpg> key 1
+
+In the output, you should now see ``ssb*`` on the **[E]** key. The ``*``
+indicates which key is currently "selected." It works as a *toggle*,
+meaning that if you type ``key 1`` again, the ``*`` will disappear and
+the key will not be selected any more.
+
+Now, let's move that key onto the smartcard::
+
+    gpg> keytocard
+    Please select where to store the key:
+       (2) Encryption key
+    Your selection? 2
+
+Since it's our **[E]** key, it makes sense to put it into the Encryption
+slot.  When you submit your selection, you will be prompted first for
+your PGP key passphrase, and then for the admin PIN. If the command
+returns without an error, your key has been moved.
+
+**Important**: Now type ``key 1`` again to unselect the first key, and
+``key 2`` to select the **[S]** key::
+
+    gpg> key 1
+    gpg> key 2
+    gpg> keytocard
+    Please select where to store the key:
+       (1) Signature key
+       (3) Authentication key
+    Your selection? 1
+
+You can use the **[S]** key both for Signature and Authentication, but
+we want to make sure it's in the Signature slot, so choose (1). Once
+again, if your command returns without an error, then the operation was
+successful::
+
+    gpg> q
+    Save changes? (y/N) y
+
+Saving the changes will delete the keys you moved to the card from your
+home directory (but it's okay, because we have them in our backups
+should we need to do this again for a replacement smartcard).
+
+Verifying that the keys were moved
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+If you perform ``--list-secret-keys`` now, you will see a subtle
+difference in the output::
+
+    $ gpg --list-secret-keys
+    sec#  rsa2048 2018-01-24 [SC] [expires: 2020-01-24]
+          000000000000000000000000AAAABBBBCCCCDDDD
+    uid           [ultimate] Alice Dev <adev@kernel.org>
+    ssb>  rsa2048 2018-01-24 [E] [expires: 2020-01-24]
+    ssb>  ed25519 2018-01-24 [S]
+
+The ``>`` in the ``ssb>`` output indicates that the subkey is only
+available on the smartcard. If you go back into your secret keys
+directory and look at the contents there, you will notice that the
+``.key`` files there have been replaced with stubs::
+
+    $ cd ~/.gnupg/private-keys-v1.d
+    $ strings *.key | grep 'private-key'
+
+The output should contain ``shadowed-private-key`` to indicate that
+these files are only stubs and the actual content is on the smartcard.
+
+Verifying that the smartcard is functioning
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To verify that the smartcard is working as intended, you can create a
+signature::
+
+    $ echo "Hello world" | gpg --clearsign > /tmp/test.asc
+    $ gpg --verify /tmp/test.asc
+
+This should ask for your smartcard PIN on your first command, and then
+show "Good signature" after you run ``gpg --verify``.
+
+Congratulations, you have successfully made it extremely difficult to
+steal your digital developer identity!
+
+Other common GnuPG operations
+-----------------------------
+
+Here is a quick reference for some common operations you'll need to do
+with your PGP key.
+
+Mounting your master key offline storage
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+You will need your master key for any of the operations below, so you
+will first need to mount your backup offline storage and tell GnuPG to
+use it::
+
+    $ export GNUPGHOME=/media/disk/foo/gnupg-backup
+    $ gpg --list-secret-keys
+
+You want to make sure that you see ``sec`` and not ``sec#`` in the
+output (the ``#`` means the key is not available and you're still using
+your regular home directory location).
+
+Extending key expiration date
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The master key has the default expiration date of 2 years from the date
+of creation. This is done both for security reasons and to make obsolete
+keys eventually disappear from keyservers.
+
+To extend the expiration on your key by a year from current date, just
+run::
+
+    $ gpg --quick-set-expire [fpr] 1y
+
+You can also use a specific date if that is easier to remember (e.g.
+your birthday, January 1st, or Canada Day)::
+
+    $ gpg --quick-set-expire [fpr] 2020-07-01
+
+Remember to send the updated key back to keyservers::
+
+    $ gpg --send-key [fpr]
+
+Updating your work directory after any changes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+After you make any changes to your key using the offline storage, you will
+want to import these changes back into your regular working directory::
+
+    $ gpg --export | gpg --homedir ~/.gnupg --import
+    $ unset GNUPGHOME
+
+
+Using PGP with Git
+==================
+
+One of the core features of Git is its decentralized nature -- once a
+repository is cloned to your system, you have full history of the
+project, including all of its tags, commits and branches. However, with
+hundreds of cloned repositories floating around, how does anyone verify
+that their copy of linux.git has not been tampered with by a malicious
+third party?
+
+Or what happens if a backdoor is discovered in the code and the "Author"
+line in the commit says it was done by you, while you're pretty sure you
+had `nothing to do with it`_?
+
+To address both of these issues, Git introduced PGP integration. Signed
+tags prove the repository integrity by assuring that its contents are
+exactly the same as on the workstation of the developer who created the
+tag, while signed commits make it nearly impossible for someone to
+impersonate you without having access to your PGP keys.
+
+.. _`nothing to do with it`: https://github.com/jayphelps/git-blame-someone-else
+
+Configure git to use your PGP key
+---------------------------------
+
+If you only have one secret key in your keyring, then you don't really
+need to do anything extra, as it becomes your default key.  However, if
+you happen to have multiple secret keys, you can tell git which key
+should be used (``[fpr]`` is the fingerprint of your key)::
+
+    $ git config --global user.signingKey [fpr]
+
+**IMPORTANT**: If you have a distinct ``gpg2`` command, then you should
+tell git to always use it instead of the legacy ``gpg`` from version 1::
+
+    $ git config --global gpg.program gpg2
+
+How to work with signed tags
+----------------------------
+
+To create a signed tag, simply pass the ``-s`` switch to the tag
+command::
+
+    $ git tag -s [tagname]
+
+Our recommendation is to always sign git tags, as this allows other
+developers to ensure that the git repository they are pulling from has
+not been maliciously altered.
+
+How to verify signed tags
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To verify a signed tag, simply use the ``verify-tag`` command::
+
+    $ git verify-tag [tagname]
+
+If you are pulling a tag from another fork of the project repository,
+git should automatically verify the signature at the tip you're pulling
+and show you the results during the merge operation::
+
+    $ git pull [url] tags/sometag
+
+The merge message will contain something like this::
+
+    Merge tag 'sometag' of [url]
+
+    [Tag message]
+
+    # gpg: Signature made [...]
+    # gpg: Good signature from [...]
+
+If you are verifying someone else's git tag, then you will need to
+import their PGP key. Please refer to the
+":ref:`verify_identities`" section below.
+
+Configure git to always sign annotated tags
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Chances are, if you're creating an annotated tag, you'll want to sign
+it. To force git to always sign annotated tags, you can set a global
+configuration option::
+
+    $ git config --global tag.forceSignAnnotated true
+
+How to work with signed commits
+-------------------------------
+
+It is easy to create signed commits, but it is much more difficult to
+use them in Linux kernel development, since it relies on patches sent to
+the mailing list, and this workflow does not preserve PGP commit
+signatures. Furthermore, when rebasing your repository to match
+upstream, even your own PGP commit signatures will end up discarded. For
+this reason, most kernel developers don't bother signing their commits
+and will ignore signed commits in any external repositories that they
+rely upon in their work.
+
+However, if you have your working git tree publicly available at some
+git hosting service (kernel.org, infradead.org, ozlabs.org, or others),
+then the recommendation is that you sign all your git commits even if
+upstream developers do not directly benefit from this practice.
+
+We recommend this for the following reasons:
+
+1. Should there ever be a need to perform code forensics or track code
+   provenance, even externally maintained trees carrying PGP commit
+   signatures will be valuable for such purposes.
+2. If you ever need to re-clone your local repository (for example,
+   after a disk failure), this lets you easily verify the repository
+   integrity before resuming your work.
+3. If someone needs to cherry-pick your commits, this allows them to
+   quickly verify their integrity before applying them.
+
+Creating signed commits
+~~~~~~~~~~~~~~~~~~~~~~~
+
+To create a signed commit, you just need to pass the ``-S`` flag to the
+``git commit`` command (it's capital ``-S`` due to collision with
+another flag)::
+
+    $ git commit -S
+
+Configure git to always sign commits
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+You can tell git to always sign commits::
+
+    git config --global commit.gpgSign true
+
+.. note::
+
+    Make sure you configure ``gpg-agent`` before you turn this on.
+
+.. _verify_identities:
+
+How to verify kernel developer identities
+=========================================
+
+Signing tags and commits is easy, but how does one go about verifying
+that the key used to sign something belongs to the actual kernel
+developer and not to a malicious imposter?
+
+Configure auto-key-retrieval using WKD and DANE
+-----------------------------------------------
+
+If you are not already someone with an extensive collection of other
+developers' public keys, then you can jumpstart your keyring by relying
+on key auto-discovery and auto-retrieval. GnuPG can piggyback on other
+delegated trust technologies, namely DNSSEC and TLS, to get you going if
+the prospect of starting your own Web of Trust from scratch is too
+daunting.
+
+Add the following to your ``~/.gnupg/gpg.conf``::
+
+    auto-key-locate wkd,dane,local
+    auto-key-retrieve
+
+DNS-Based Authentication of Named Entities ("DANE") is a method for
+publishing public keys in DNS and securing them using DNSSEC signed
+zones. Web Key Directory ("WKD") is the alternative method that uses
+https lookups for the same purpose. When using either DANE or WKD for
+looking up public keys, GnuPG will validate DNSSEC or TLS certificates,
+respectively, before adding auto-retrieved public keys to your local
+keyring.
+
+Kernel.org publishes the WKD for all developers who have kernel.org
+accounts. Once you have the above changes in your ``gpg.conf``, you can
+auto-retrieve the keys for Linus Torvalds and Greg Kroah-Hartman (if you
+don't already have them)::
+
+    $ gpg --locate-keys torvalds@kernel.org gregkh@kernel.org
+
+If you have a kernel.org account, then you should `add the kernel.org
+UID to your key`_ to make WKD more useful to other kernel developers.
+
+.. _`add the kernel.org UID to your key`: https://korg.wiki.kernel.org/userdoc/mail#adding_a_kernelorg_uid_to_your_pgp_key
+
+Web of Trust (WOT) vs. Trust on First Use (TOFU)
+------------------------------------------------
+
+PGP incorporates a trust delegation mechanism known as the "Web of
+Trust." At its core, this is an attempt to replace the need for
+centralized Certification Authorities of the HTTPS/TLS world. Instead of
+various software makers dictating who should be your trusted certifying
+entity, PGP leaves this responsibility to each user.
+
+Unfortunately, very few people understand how the Web of Trust works.
+While it remains an important aspect of the OpenPGP specification,
+recent versions of GnuPG (2.2 and above) have implemented an alternative
+mechanism called "Trust on First Use" (TOFU). You can think of TOFU as
+"the SSH-like approach to trust." With SSH, the first time you connect
+to a remote system, its key fingerprint is recorded and remembered. If
+the key changes in the future, the SSH client will alert you and refuse
+to connect, forcing you to make a decision on whether you choose to
+trust the changed key or not. Similarly, the first time you import
+someone's PGP key, it is assumed to be valid. If at any point in the
+future GnuPG comes across another key with the same identity, both the
+previously imported key and the new key will be marked as invalid and
+you will need to manually figure out which one to keep.
+
+We recommend that you use the combined TOFU+PGP trust model (which is
+the new default in GnuPG v2). To set it, add (or modify) the
+``trust-model`` setting in ``~/.gnupg/gpg.conf``::
+
+    trust-model tofu+pgp
+
+How to use keyservers (more) safely
+-----------------------------------
+
+If you get a "No public key" error when trying to validate someone's
+tag, then you should attempt to lookup that key using a keyserver. It is
+important to keep in mind that there is absolutely no guarantee that the
+key you retrieve from PGP keyservers belongs to the actual person --
+that much is by design. You are supposed to use the Web of Trust to
+establish key validity.
+
+How to properly maintain the Web of Trust is beyond the scope of this
+document, simply because doing it properly requires both effort and
+dedication that tends to be beyond the caring threshold of most human
+beings. Here are some shortcuts that will help you reduce the risk of
+importing a malicious key.
+
+First, let's say you've tried to run ``git verify-tag`` but it returned
+an error saying the key is not found::
+
+    $ git verify-tag sunxi-fixes-for-4.15-2
+    gpg: Signature made Sun 07 Jan 2018 10:51:55 PM EST
+    gpg:                using RSA key DA73759BF8619E484E5A3B47389A54219C0F2430
+    gpg:                issuer "wens@...org"
+    gpg: Can't check signature: No public key
+
+Let's query the keyserver for more info about that key fingerprint (the
+fingerprint probably belongs to a subkey, so we can't use it directly
+without finding out the ID of the master key it is associated with)::
+
+    $ gpg --search DA73759BF8619E484E5A3B47389A54219C0F2430
+    gpg: data source: hkp://keys.gnupg.net
+    (1) Chen-Yu Tsai <wens@...org>
+          4096 bit RSA key C94035C21B4F2AEB, created: 2017-03-14, expires: 2019-03-15
+    Keys 1-1 of 1 for "DA73759BF8619E484E5A3B47389A54219C0F2430".  Enter number(s), N)ext, or Q)uit > q
+
+Locate the ID of the master key in the output, in our example
+``C94035C21B4F2AEB``. Now display the key of Linus Torvalds that you
+have on your keyring::
+
+    $ gpg --list-key torvalds@kernel.org
+    pub   rsa2048 2011-09-20 [SC]
+          ABAF11C65A2970B130ABE3C479BE3E4300411886
+    uid           [ unknown] Linus Torvalds <torvalds@kernel.org>
+    sub   rsa2048 2011-09-20 [E]
+
+Next, open the `PGP pathfinder`_. In the "From" field, paste the key
+fingerprint of Linus Torvalds from the output above. In the "To" field,
+paste they key-id you found via ``gpg --search`` of the unknown key, and
+check the results:
+
+- `Finding paths to Linus`_
+
+If you get a few decent trust paths, then it's a pretty good indication
+that it is a valid key. You can add it to your keyring from the
+keyserver now::
+
+    $ gpg --recv-key C94035C21B4F2AEB
+
+This process is not perfect, and you are obviously trusting the
+administrators of the PGP Pathfinder service to not be malicious (in
+fact, this goes against :ref:`devs_not_infra`). However, if you
+do not carefully maintain your own web of trust, then it is a marked
+improvement over blindly trusting keyservers.
+
+.. _`PGP pathfinder`: https://pgp.cs.uu.nl/
+.. _`Finding paths to Linus`: https://pgp.cs.uu.nl/paths/79BE3E4300411886/to/C94035C21B4F2AEB.html
index 1291c498f78fdd91b5eeebf01d6f43de33737413..a5882865836e3d87c990012486da810b32326a67 100644 (file)
@@ -3,7 +3,7 @@ Documentation for /proc/sys/user/*      kernel version 4.9.0
 
 ==============================================================
 
-This file contains the documetation for the sysctl files in
+This file contains the documentation for the sysctl files in
 /proc/sys/user.
 
 The files in this directory can be used to override the default
index 6f9d7b4189170f25143d852d9cf2699af211f997..beea975980f63236c7ca507aeb7fd7a2c610ef81 100644 (file)
@@ -40,11 +40,6 @@ margin: Watchdog margin in seconds (default=60)
 nowayout: Disable watchdog shutdown on close
        (default=kernel config parameter)
 -------------------------------------------------
-at32ap700x_wdt:
-timeout: Timeout value. Limited to be 1 or 2 seconds. (default=2)
-nowayout: Watchdog cannot be stopped once started
-       (default=kernel config parameter)
--------------------------------------------------
 at91rm9200_wdt:
 wdt_time: Watchdog time in seconds. (default=5)
 nowayout: Watchdog cannot be stopped once started
@@ -162,11 +157,6 @@ testmode: Watchdog test mode (1 = no reboot), default=0
 nowayout: Watchdog cannot be stopped once started
        (default=kernel config parameter)
 -------------------------------------------------
-ixp2000_wdt:
-heartbeat: Watchdog heartbeat in seconds (default 60s)
-nowayout: Watchdog cannot be stopped once started
-       (default=kernel config parameter)
--------------------------------------------------
 ixp4xx_wdt:
 heartbeat: Watchdog heartbeat in seconds (default 60s)
 nowayout: Watchdog cannot be stopped once started
@@ -381,19 +371,6 @@ timeout: Watchdog timeout in seconds. 1 <= timeout <= 255, default=60.
 nowayout: Watchdog cannot be stopped once started
        (default=kernel config parameter)
 -------------------------------------------------
-w83697hf_wdt:
-wdt_io: w83697hf/hg WDT io port (default 0x2e, 0 = autodetect)
-timeout: Watchdog timeout in seconds. 1<= timeout <=255 (default=60)
-nowayout: Watchdog cannot be stopped once started
-       (default=kernel config parameter)
-early_disable: Watchdog gets disabled at boot time (default=1)
--------------------------------------------------
-w83697ug_wdt:
-wdt_io: w83697ug/uf WDT io port (default 0x2e)
-timeout: Watchdog timeout in seconds. 1<= timeout <=255 (default=60)
-nowayout: Watchdog cannot be stopped once started
-       (default=kernel config parameter)
--------------------------------------------------
 w83877f_wdt:
 timeout: Watchdog timeout in seconds. (1<=timeout<=3600, default=30)
 nowayout: Watchdog cannot be stopped once started
index 836f6c7bbf2d50c67bb56e5a1a882f01d9d98a41..cf42583385870061ab93bc91a1f9b51fc97b7c3f 100644 (file)
@@ -903,7 +903,6 @@ L:  devel@driverdev.osuosl.org
 S:     Supported
 F:     drivers/staging/android/ion
 F:     drivers/staging/android/uapi/ion.h
-F:     drivers/staging/android/uapi/ion_test.h
 
 AOA (Apple Onboard Audio) ALSA DRIVER
 M:     Johannes Berg <johannes@sipsolutions.net>
@@ -1308,7 +1307,6 @@ M:        Russell King <linux@armlinux.org.uk>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
 T:     git git://git.armlinux.org.uk/~rmk/linux-arm.git clkdev
-F:     arch/arm/include/asm/clkdev.h
 F:     drivers/clk/clkdev.c
 
 ARM/COMPULAB CM-X270/EM-X270 and CM-X300 MACHINE SUPPORT
@@ -1360,7 +1358,7 @@ F:        Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
 F:     Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
 F:     Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
 F:     arch/arm/mach-gemini/
-F:     drivers/net/ethernet/cortina/gemini/*
+F:     drivers/net/ethernet/cortina/
 F:     drivers/pinctrl/pinctrl-gemini.c
 F:     drivers/rtc/rtc-ftrtc010.c
 
@@ -1737,9 +1735,7 @@ L:        linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:     linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers)
 S:     Maintained
 F:     arch/arm/mach-oxnas/
-F:     arch/arm/boot/dts/ox8*.dtsi
-F:     arch/arm/boot/dts/wd-mbwe.dts
-F:     arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts
+F:     arch/arm/boot/dts/ox8*.dts*
 N:     oxnas
 
 ARM/PALM TREO SUPPORT
@@ -1747,8 +1743,7 @@ M:        Tomas Cech <sleep_walker@suse.com>
 L:     linux-arm-kernel@lists.infradead.org
 W:     http://hackndev.com
 S:     Maintained
-F:     arch/arm/mach-pxa/include/mach/palmtreo.h
-F:     arch/arm/mach-pxa/palmtreo.c
+F:     arch/arm/mach-pxa/palmtreo.*
 
 ARM/PALMTX,PALMT5,PALMLD,PALMTE2,PALMTC SUPPORT
 M:     Marek Vasut <marek.vasut@gmail.com>
@@ -1757,12 +1752,10 @@ W:      http://hackndev.com
 S:     Maintained
 F:     arch/arm/mach-pxa/include/mach/palmtx.h
 F:     arch/arm/mach-pxa/palmtx.c
-F:     arch/arm/mach-pxa/include/mach/palmt5.h
-F:     arch/arm/mach-pxa/palmt5.c
+F:     arch/arm/mach-pxa/palmt5.*
 F:     arch/arm/mach-pxa/include/mach/palmld.h
 F:     arch/arm/mach-pxa/palmld.c
-F:     arch/arm/mach-pxa/include/mach/palmte2.h
-F:     arch/arm/mach-pxa/palmte2.c
+F:     arch/arm/mach-pxa/palmte2.*
 F:     arch/arm/mach-pxa/include/mach/palmtc.h
 F:     arch/arm/mach-pxa/palmtc.c
 
@@ -1771,8 +1764,7 @@ M:        Sergey Lapin <slapin@ossfans.org>
 L:     linux-arm-kernel@lists.infradead.org
 W:     http://hackndev.com
 S:     Maintained
-F:     arch/arm/mach-pxa/include/mach/palmz72.h
-F:     arch/arm/mach-pxa/palmz72.c
+F:     arch/arm/mach-pxa/palmz72.*
 
 ARM/PLEB SUPPORT
 M:     Peter Chubb <pleb@gelato.unsw.edu.au>
@@ -1801,7 +1793,6 @@ F:        drivers/clk/qcom/
 F:     drivers/dma/qcom/
 F:     drivers/soc/qcom/
 F:     drivers/spi/spi-qup.c
-F:     drivers/tty/serial/msm_serial.h
 F:     drivers/tty/serial/msm_serial.c
 F:     drivers/*/pm8???-*
 F:     drivers/mfd/ssbi.c
@@ -3567,7 +3558,7 @@ F:        drivers/media/platform/coda/
 
 COMMON CLK FRAMEWORK
 M:     Michael Turquette <mturquette@baylibre.com>
-M:     Stephen Boyd <sboyd@codeaurora.org>
+M:     Stephen Boyd <sboyd@kernel.org>
 L:     linux-clk@vger.kernel.org
 Q:     http://patchwork.kernel.org/project/linux-clk/list/
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
@@ -6001,6 +5992,12 @@ L:       linux-input@vger.kernel.org
 S:     Maintained
 F:     drivers/input/touchscreen/goodix.c
 
+GPD POCKET FAN DRIVER
+M:     Hans de Goede <hdegoede@redhat.com>
+L:     platform-driver-x86@vger.kernel.org
+S:     Maintained
+F:     drivers/platform/x86/gpd-pocket-fan.c
+
 GPIO ACPI SUPPORT
 M:     Mika Westerberg <mika.westerberg@linux.intel.com>
 M:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
@@ -8939,12 +8936,13 @@ W:      http://www.mellanox.com
 Q:     http://patchwork.ozlabs.org/project/netdev/list/
 F:     drivers/net/ethernet/mellanox/mlxfw/
 
-MELLANOX MLX CPLD HOTPLUG DRIVER
+MELLANOX HARDWARE PLATFORM SUPPORT
+M:     Andy Shevchenko <andy@infradead.org>
+M:     Darren Hart <dvhart@infradead.org>
 M:     Vadim Pasternak <vadimp@mellanox.com>
 L:     platform-driver-x86@vger.kernel.org
 S:     Supported
-F:     drivers/platform/x86/mlxcpld-hotplug.c
-F:     include/linux/platform_data/mlxcpld-hotplug.h
+F:     drivers/platform/mellanox/
 
 MELLANOX MLX4 core VPI driver
 M:     Tariq Toukan <tariqt@mellanox.com>
@@ -9018,6 +9016,7 @@ L:        linux-kernel@vger.kernel.org
 S:     Supported
 F:     kernel/sched/membarrier.c
 F:     include/uapi/linux/membarrier.h
+F:     arch/powerpc/include/asm/membarrier.h
 
 MEMORY MANAGEMENT
 L:     linux-mm@kvack.org
@@ -9189,6 +9188,7 @@ S:        Supported
 F:     Documentation/devicetree/bindings/mips/
 F:     Documentation/mips/
 F:     arch/mips/
+F:     drivers/platform/mips/
 
 MIPS BOSTON DEVELOPMENT BOARD
 M:     Paul Burton <paul.burton@mips.com>
@@ -9216,6 +9216,25 @@ F:       arch/mips/include/asm/mach-loongson32/
 F:     drivers/*/*loongson1*
 F:     drivers/*/*/*loongson1*
 
+MIPS/LOONGSON2 ARCHITECTURE
+M:     Jiaxun Yang <jiaxun.yang@flygoat.com>
+L:     linux-mips@linux-mips.org
+S:     Maintained
+F:     arch/mips/loongson64/*{2e/2f}*
+F:     arch/mips/include/asm/mach-loongson64/
+F:     drivers/*/*loongson2*
+F:     drivers/*/*/*loongson2*
+
+MIPS/LOONGSON3 ARCHITECTURE
+M:     Huacai Chen <chenhc@lemote.com>
+L:     linux-mips@linux-mips.org
+S:     Maintained
+F:     arch/mips/loongson64/
+F:     arch/mips/include/asm/mach-loongson64/
+F:     drivers/platform/mips/cpu_hwmon.c
+F:     drivers/*/*loongson3*
+F:     drivers/*/*/*loongson3*
+
 MIPS RINT INSTRUCTION EMULATION
 M:     Aleksandar Markovic <aleksandar.markovic@mips.com>
 L:     linux-mips@linux-mips.org
@@ -9261,7 +9280,6 @@ F:        drivers/media/dvb-frontends/mn88473*
 
 MODULE SUPPORT
 M:     Jessica Yu <jeyu@kernel.org>
-M:     Rusty Russell <rusty@rustcorp.com.au>
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/jeyu/linux.git modules-next
 S:     Maintained
 F:     include/linux/module.h
@@ -10276,7 +10294,7 @@ F:      include/uapi/linux/openvswitch.h
 OPERATING PERFORMANCE POINTS (OPP)
 M:     Viresh Kumar <vireshk@kernel.org>
 M:     Nishanth Menon <nm@ti.com>
-M:     Stephen Boyd <sboyd@codeaurora.org>
+M:     Stephen Boyd <sboyd@kernel.org>
 L:     linux-pm@vger.kernel.org
 S:     Maintained
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git
@@ -10411,7 +10429,6 @@ F:      Documentation/parport*.txt
 PARAVIRT_OPS INTERFACE
 M:     Juergen Gross <jgross@suse.com>
 M:     Alok Kataria <akataria@vmware.com>
-M:     Rusty Russell <rusty@rustcorp.com.au>
 L:     virtualization@lists.linux-foundation.org
 S:     Supported
 F:     Documentation/virtual/paravirt_ops.txt
@@ -11587,6 +11604,13 @@ S:     Maintained
 F:     Documentation/blockdev/ramdisk.txt
 F:     drivers/block/brd.c
 
+RANCHU VIRTUAL BOARD FOR MIPS
+M:     Miodrag Dinic <miodrag.dinic@mips.com>
+L:     linux-mips@linux-mips.org
+S:     Supported
+F:     arch/mips/generic/board-ranchu.c
+F:     arch/mips/configs/generic/board-ranchu.config
+
 RANDOM NUMBER DRIVER
 M:     "Theodore Ts'o" <tytso@mit.edu>
 S:     Maintained
@@ -13012,7 +13036,7 @@ F:      Documentation/networking/spider_net.txt
 F:     drivers/net/ethernet/toshiba/spider_net*
 
 SPMI SUBSYSTEM
-R:     Stephen Boyd <sboyd@codeaurora.org>
+R:     Stephen Boyd <sboyd@kernel.org>
 L:     linux-arm-msm@vger.kernel.org
 F:     Documentation/devicetree/bindings/spmi/
 F:     drivers/spmi/
@@ -13319,7 +13343,6 @@ F:      include/linux/platform_data/dma-dw.h
 F:     drivers/dma/dw/
 
 SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER
-M:     Jie Deng <jiedeng@synopsys.com>
 M:     Jose Abreu <Jose.Abreu@synopsys.com>
 L:     netdev@vger.kernel.org
 S:     Supported
@@ -13898,7 +13921,7 @@ F:      include/linux/usb/tilegx.h
 TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
 M:     John Stultz <john.stultz@linaro.org>
 M:     Thomas Gleixner <tglx@linutronix.de>
-R:     Stephen Boyd <sboyd@codeaurora.org>
+R:     Stephen Boyd <sboyd@kernel.org>
 L:     linux-kernel@vger.kernel.org
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
 S:     Supported
@@ -14966,8 +14989,8 @@ S:      Maintained
 F:     drivers/input/tablet/wacom_serial4.c
 
 WATCHDOG DEVICE DRIVERS
-M:     Wim Van Sebroeck <wim@iguana.be>
-R:     Guenter Roeck <linux@roeck-us.net>
+M:     Wim Van Sebroeck <wim@linux-watchdog.org>
+M:     Guenter Roeck <linux@roeck-us.net>
 L:     linux-watchdog@vger.kernel.org
 W:     http://www.linux-watchdog.org/
 T:     git git://www.linux-watchdog.org/linux-watchdog.git
@@ -15134,7 +15157,7 @@ X86 PLATFORM DRIVERS
 M:     Darren Hart <dvhart@infradead.org>
 M:     Andy Shevchenko <andy@infradead.org>
 L:     platform-driver-x86@vger.kernel.org
-T:     git git://git.infradead.org/users/dvhart/linux-platform-drivers-x86.git
+T:     git git://git.infradead.org/linux-platform-drivers-x86.git
 S:     Maintained
 F:     drivers/platform/x86/
 F:     drivers/platform/olpc/
index 11aff0f9e105f19f45f6f4861c22c25fe65b86d6..d192dd826ccea13f5fda798a570e65e687d3e0e2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -434,7 +434,8 @@ export MAKE LEX YACC AWK GENKSYMS INSTALLKERNEL PERL PYTHON UTS_MACHINE
 export HOSTCXX HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS LDFLAGS
-export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE CFLAGS_KASAN CFLAGS_UBSAN
+export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE
+export CFLAGS_KASAN CFLAGS_KASAN_NOSANITIZE CFLAGS_UBSAN
 export KBUILD_AFLAGS AFLAGS_KERNEL AFLAGS_MODULE
 export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_LDFLAGS_MODULE
 export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL
@@ -679,6 +680,10 @@ endif
 # This selects the stack protector compiler flag. Testing it is delayed
 # until after .config has been reprocessed, in the prepare-compiler-check
 # target.
+ifdef CONFIG_CC_STACKPROTECTOR_AUTO
+  stackp-flag := $(call cc-option,-fstack-protector-strong,$(call cc-option,-fstack-protector))
+  stackp-name := AUTO
+else
 ifdef CONFIG_CC_STACKPROTECTOR_REGULAR
   stackp-flag := -fstack-protector
   stackp-name := REGULAR
@@ -687,16 +692,40 @@ ifdef CONFIG_CC_STACKPROTECTOR_STRONG
   stackp-flag := -fstack-protector-strong
   stackp-name := STRONG
 else
+  # If either there is no stack protector for this architecture or
+  # CONFIG_CC_STACKPROTECTOR_NONE is selected, we're done, and $(stackp-name)
+  # is empty, skipping all remaining stack protector tests.
+  #
   # Force off for distro compilers that enable stack protector by default.
-  stackp-flag := $(call cc-option, -fno-stack-protector)
+  KBUILD_CFLAGS += $(call cc-option, -fno-stack-protector)
+endif
 endif
 endif
 # Find arch-specific stack protector compiler sanity-checking script.
-ifdef CONFIG_CC_STACKPROTECTOR
+ifdef stackp-name
+ifneq ($(stackp-flag),)
   stackp-path := $(srctree)/scripts/gcc-$(SRCARCH)_$(BITS)-has-stack-protector.sh
   stackp-check := $(wildcard $(stackp-path))
+  # If the wildcard test matches a test script, run it to check functionality.
+  ifdef stackp-check
+    ifneq ($(shell $(CONFIG_SHELL) $(stackp-check) $(CC) $(KBUILD_CPPFLAGS) $(biarch)),y)
+      stackp-broken := y
+    endif
+  endif
+  ifndef stackp-broken
+    # If the stack protector is functional, enable code that depends on it.
+    KBUILD_CPPFLAGS += -DCONFIG_CC_STACKPROTECTOR
+    # Either we've already detected the flag (for AUTO) or we'll fail the
+    # build in the prepare-compiler-check rule (for specific flag).
+    KBUILD_CFLAGS += $(stackp-flag)
+  else
+    # We have to make sure stack protector is unconditionally disabled if
+    # the compiler is broken (in case we're going to continue the build in
+    # AUTO mode).
+    KBUILD_CFLAGS += $(call cc-option, -fno-stack-protector)
+  endif
+endif
 endif
-KBUILD_CFLAGS += $(stackp-flag)
 
 ifeq ($(cc-name),clang)
 KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
@@ -1091,14 +1120,25 @@ PHONY += prepare-compiler-check
 prepare-compiler-check: FORCE
 # Make sure compiler supports requested stack protector flag.
 ifdef stackp-name
+  # Warn about CONFIG_CC_STACKPROTECTOR_AUTO having found no option.
+  ifeq ($(stackp-flag),)
+       @echo CONFIG_CC_STACKPROTECTOR_$(stackp-name): \
+                 Compiler does not support any known stack-protector >&2
+  else
+  # Fail if specifically requested stack protector is missing.
   ifeq ($(call cc-option, $(stackp-flag)),)
        @echo Cannot use CONFIG_CC_STACKPROTECTOR_$(stackp-name): \
                  $(stackp-flag) not supported by compiler >&2 && exit 1
   endif
+  endif
 endif
-# Make sure compiler does not have buggy stack-protector support.
-ifdef stackp-check
-  ifneq ($(shell $(CONFIG_SHELL) $(stackp-check) $(CC) $(KBUILD_CPPFLAGS) $(biarch)),y)
+# Make sure compiler does not have buggy stack-protector support. If a
+# specific stack-protector was requested, fail the build, otherwise warn.
+ifdef stackp-broken
+  ifeq ($(stackp-name),AUTO)
+       @echo CONFIG_CC_STACKPROTECTOR_$(stackp-name): \
+                  $(stackp-flag) available but compiler is broken: disabling >&2
+  else
        @echo Cannot use CONFIG_CC_STACKPROTECTOR_$(stackp-name): \
                   $(stackp-flag) available but compiler is broken >&2 && exit 1
   endif
index 467dfa35bf969b568cf974da432e563785d4a502..76c0b54443b1fd7563414622988032d9f63fc11f 100644 (file)
@@ -538,16 +538,10 @@ config HAVE_CC_STACKPROTECTOR
          - its compiler supports the -fstack-protector option
          - it has implemented a stack canary (e.g. __stack_chk_guard)
 
-config CC_STACKPROTECTOR
-       def_bool n
-       help
-         Set when a stack-protector mode is enabled, so that the build
-         can enable kernel-side support for the GCC feature.
-
 choice
        prompt "Stack Protector buffer overflow detection"
        depends on HAVE_CC_STACKPROTECTOR
-       default CC_STACKPROTECTOR_NONE
+       default CC_STACKPROTECTOR_AUTO
        help
          This option turns on the "stack-protector" GCC feature. This
          feature puts, at the beginning of functions, a canary value on
@@ -564,7 +558,6 @@ config CC_STACKPROTECTOR_NONE
 
 config CC_STACKPROTECTOR_REGULAR
        bool "Regular"
-       select CC_STACKPROTECTOR
        help
          Functions will have the stack-protector canary logic added if they
          have an 8-byte or larger character array on the stack.
@@ -578,7 +571,6 @@ config CC_STACKPROTECTOR_REGULAR
 
 config CC_STACKPROTECTOR_STRONG
        bool "Strong"
-       select CC_STACKPROTECTOR
        help
          Functions will have the stack-protector canary logic added in any
          of the following conditions:
@@ -596,6 +588,12 @@ config CC_STACKPROTECTOR_STRONG
          about 20% of all kernel functions, which increases the kernel code
          size by about 2%.
 
+config CC_STACKPROTECTOR_AUTO
+       bool "Automatic"
+       help
+         If the compiler supports it, the best available stack-protector
+         option will be chosen.
+
 endchoice
 
 config THIN_ARCHIVES
index ce5ee762ed66c6cbc94fd5ab0755ad588f6a0090..4cab9bb823fbbb4511225a695927a9387bce7eec 100644 (file)
@@ -338,6 +338,7 @@ static inline int find_next_bit_le(const void *p, int size, int offset)
 
 #endif
 
+#include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/le.h>
 
 /*
index 53612879fe567022a74ad989b48e664f7ac99013..7381eeb7ef8e40197ccdd4de2c61386ea8409110 100644 (file)
@@ -16,6 +16,7 @@ config ARM64
        select ARCH_HAS_GCOV_PROFILE_ALL
        select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
        select ARCH_HAS_KCOV
+       select ARCH_HAS_MEMBARRIER_SYNC_CORE
        select ARCH_HAS_SET_MEMORY
        select ARCH_HAS_SG_CHAIN
        select ARCH_HAS_STRICT_KERNEL_RWX
index e266f80e45b78142e03e454cda2d72eca8b16c34..8758bb008436d4e3fb6a5b119c55fa07d0186bbb 100644 (file)
@@ -12,7 +12,8 @@
 
 /*
  * KASAN_SHADOW_START: beginning of the kernel virtual addresses.
- * KASAN_SHADOW_END: KASAN_SHADOW_START + 1/8 of kernel virtual addresses.
+ * KASAN_SHADOW_END: KASAN_SHADOW_START + 1/N of kernel virtual addresses,
+ * where N = (1 << KASAN_SHADOW_SCALE_SHIFT).
  */
 #define KASAN_SHADOW_START      (VA_START)
 #define KASAN_SHADOW_END        (KASAN_SHADOW_START + KASAN_SHADOW_SIZE)
 /*
  * This value is used to map an address to the corresponding shadow
  * address by the following formula:
- *     shadow_addr = (address >> 3) + KASAN_SHADOW_OFFSET;
+ *     shadow_addr = (address >> KASAN_SHADOW_SCALE_SHIFT) + KASAN_SHADOW_OFFSET
  *
- * (1 << 61) shadow addresses - [KASAN_SHADOW_OFFSET,KASAN_SHADOW_END]
- * cover all 64-bits of virtual addresses. So KASAN_SHADOW_OFFSET
- * should satisfy the following equation:
- *      KASAN_SHADOW_OFFSET = KASAN_SHADOW_END - (1ULL << 61)
+ * (1 << (64 - KASAN_SHADOW_SCALE_SHIFT)) shadow addresses that lie in range
+ * [KASAN_SHADOW_OFFSET, KASAN_SHADOW_END) cover all 64-bits of virtual
+ * addresses. So KASAN_SHADOW_OFFSET should satisfy the following equation:
+ *      KASAN_SHADOW_OFFSET = KASAN_SHADOW_END -
+ *                             (1ULL << (64 - KASAN_SHADOW_SCALE_SHIFT))
  */
-#define KASAN_SHADOW_OFFSET     (KASAN_SHADOW_END - (1ULL << (64 - 3)))
+#define KASAN_SHADOW_OFFSET     (KASAN_SHADOW_END - (1ULL << \
+                                       (64 - KASAN_SHADOW_SCALE_SHIFT)))
 
 void kasan_init(void);
 void kasan_copy_shadow(pgd_t *pgdir);
index d4bae7d6e0d8b9786f3961d7dfe9627f9c5a57d8..50fa96a497926178a010075701eea807a1b7e99d 100644 (file)
@@ -85,7 +85,8 @@
  * stack size when KASAN is in use.
  */
 #ifdef CONFIG_KASAN
-#define KASAN_SHADOW_SIZE      (UL(1) << (VA_BITS - 3))
+#define KASAN_SHADOW_SCALE_SHIFT 3
+#define KASAN_SHADOW_SIZE      (UL(1) << (VA_BITS - KASAN_SHADOW_SCALE_SHIFT))
 #define KASAN_THREAD_SHIFT     1
 #else
 #define KASAN_SHADOW_SIZE      (0)
index b34e717d75970cba4f646d204265d5c0d84e89c0..cccd2788e63195199b67bf1006d7f5ea9a056702 100644 (file)
@@ -324,6 +324,10 @@ alternative_else_nop_endif
        ldp     x28, x29, [sp, #16 * 14]
        ldr     lr, [sp, #S_LR]
        add     sp, sp, #S_FRAME_SIZE           // restore sp
+       /*
+        * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on eret context synchronization
+        * when returning from IPI handler, and when returning to user-space.
+        */
 
        .if     \el == 0
 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
index 3affca3dd96a3ee8c3c7bbb14085b08a7b657a79..75b220ba73a3234b7815062537e9367d36e6a040 100644 (file)
@@ -925,9 +925,8 @@ static void __armv8pmu_probe_pmu(void *info)
        pmceid[0] = read_sysreg(pmceid0_el0);
        pmceid[1] = read_sysreg(pmceid1_el0);
 
-       bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
-                            ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
-                            ARRAY_SIZE(pmceid));
+       bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
+                            pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 }
 
 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
index acba49fb5aac0f1e464383bda2b1af3ad56675d1..6e02e6fb4c7b9e12da9796b2e8a2be68ca143ae0 100644 (file)
@@ -135,7 +135,8 @@ static void __init kasan_pgd_populate(unsigned long addr, unsigned long end,
 /* The early shadow maps everything to a single page of zeroes */
 asmlinkage void __init kasan_early_init(void)
 {
-       BUILD_BUG_ON(KASAN_SHADOW_OFFSET != KASAN_SHADOW_END - (1UL << 61));
+       BUILD_BUG_ON(KASAN_SHADOW_OFFSET !=
+               KASAN_SHADOW_END - (1UL << (64 - KASAN_SHADOW_SCALE_SHIFT)));
        BUILD_BUG_ON(!IS_ALIGNED(KASAN_SHADOW_START, PGDIR_SIZE));
        BUILD_BUG_ON(!IS_ALIGNED(KASAN_SHADOW_END, PGDIR_SIZE));
        kasan_pgd_populate(KASAN_SHADOW_START, KASAN_SHADOW_END, NUMA_NO_NODE,
index c44f002e8f6bb9a936b59e59d5cffa56b68003ff..8586024940963bb9e1bf2be5d50d31e3fcc75755 100644 (file)
@@ -2610,17 +2610,10 @@ pfm_get_task(pfm_context_t *ctx, pid_t pid, struct task_struct **task)
        if (pid < 2) return -EPERM;
 
        if (pid != task_pid_vnr(current)) {
-
-               read_lock(&tasklist_lock);
-
-               p = find_task_by_vpid(pid);
-
                /* make sure task cannot go away while we operate on it */
-               if (p) get_task_struct(p);
-
-               read_unlock(&tasklist_lock);
-
-               if (p == NULL) return -ESRCH;
+               p = find_get_task_by_vpid(pid);
+               if (!p)
+                       return -ESRCH;
        }
 
        ret = pfm_task_incompatible(ctx, p);
index dda58cfe8c22a3ec65ba074c4c0baab3c957340b..93b47b1f6fb420a1d7d52bd096f611b6668eceb0 100644 (file)
@@ -311,7 +311,6 @@ static inline int bfchg_mem_test_and_change_bit(int nr,
  *     functions.
  */
 #if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
-#include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/ffz.h>
 #else
 
@@ -441,6 +440,8 @@ static inline unsigned long ffz(unsigned long word)
 
 #endif
 
+#include <asm-generic/bitops/find.h>
+
 #ifdef __KERNEL__
 
 #if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
index ab98569994f0f61cf61d62b6b8c2757f9533c5e3..449397c60b56eae1fdaef29423588c97ee8f0d09 100644 (file)
@@ -7,8 +7,6 @@ config MIPS
        select ARCH_DISCARD_MEMBLOCK
        select ARCH_HAS_ELF_RANDOMIZE
        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
-       select ARCH_MIGHT_HAVE_PC_PARPORT
-       select ARCH_MIGHT_HAVE_PC_SERIO
        select ARCH_SUPPORTS_UPROBES
        select ARCH_USE_BUILTIN_BSWAP
        select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
@@ -119,12 +117,12 @@ config MIPS_GENERIC
        select SYS_SUPPORTS_MULTITHREADING
        select SYS_SUPPORTS_RELOCATABLE
        select SYS_SUPPORTS_SMARTMIPS
-       select USB_EHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
-       select USB_EHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
-       select USB_OHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
-       select USB_OHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
-       select USB_UHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
-       select USB_UHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
+       select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
+       select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+       select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
+       select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+       select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
+       select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
        select USE_OF
        help
          Select this to build a kernel which aims to support multiple boards,
@@ -253,6 +251,7 @@ config BCM47XX
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_MIPS16
+       select SYS_SUPPORTS_ZBOOT
        select SYS_HAS_EARLY_PRINTK
        select USE_GENERIC_EARLY_PRINTK_8250
        select GPIOLIB
@@ -341,6 +340,8 @@ config MACH_DECSTATION
 
 config MACH_JAZZ
        bool "Jazz family of machines"
+       select ARCH_MIGHT_HAVE_PC_PARPORT
+       select ARCH_MIGHT_HAVE_PC_SERIO
        select FW_ARC
        select FW_ARC32
        select ARCH_MAY_HAVE_PC_FDC
@@ -476,6 +477,8 @@ config MACH_PISTACHIO
 config MIPS_MALTA
        bool "MIPS Malta board"
        select ARCH_MAY_HAVE_PC_FDC
+       select ARCH_MIGHT_HAVE_PC_PARPORT
+       select ARCH_MIGHT_HAVE_PC_SERIO
        select BOOT_ELF32
        select BOOT_RAW
        select BUILTIN_DTB
@@ -613,6 +616,7 @@ config SGI_IP22
        bool "SGI IP22 (Indy/Indigo2)"
        select FW_ARC
        select FW_ARC32
+       select ARCH_MIGHT_HAVE_PC_SERIO
        select BOOT_ELF32
        select CEVT_R4K
        select CSRC_R4K
@@ -675,6 +679,7 @@ config SGI_IP28
        bool "SGI IP28 (Indigo2 R10k)"
        select FW_ARC
        select FW_ARC64
+       select ARCH_MIGHT_HAVE_PC_SERIO
        select BOOT_ELF64
        select CEVT_R4K
        select CSRC_R4K
@@ -824,6 +829,8 @@ config SNI_RM
        select FW_ARC32 if CPU_LITTLE_ENDIAN
        select FW_SNIPROM if CPU_BIG_ENDIAN
        select ARCH_MAY_HAVE_PC_FDC
+       select ARCH_MIGHT_HAVE_PC_PARPORT
+       select ARCH_MIGHT_HAVE_PC_SERIO
        select BOOT_ELF32
        select CEVT_R4K
        select CSRC_R4K
index 9f6a26d72f9fe66c405b27d62414feaf71e8d2cb..d1ca839c3981e5c7db6d42affe939f2fc0d8dbb0 100644 (file)
@@ -216,6 +216,12 @@ cflags-$(toolchain-msa)                    += -DTOOLCHAIN_SUPPORTS_MSA
 endif
 toolchain-virt                         := $(call cc-option-yn,$(mips-cflags) -mvirt)
 cflags-$(toolchain-virt)               += -DTOOLCHAIN_SUPPORTS_VIRT
+# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
+# only warns
+xpa-cflags-y                           := $(mips-cflags)
+xpa-cflags-$(micromips-ase)            += -mmicromips -Wa$(comma)-fatal-warnings
+toolchain-xpa                          := $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
+cflags-$(toolchain-xpa)                        += -DTOOLCHAIN_SUPPORTS_XPA
 
 #
 # Firmware support
@@ -228,7 +234,7 @@ libs-y                              += arch/mips/fw/lib/
 #
 # Kernel compression
 #
-ifdef SYS_SUPPORTS_ZBOOT
+ifdef CONFIG_SYS_SUPPORTS_ZBOOT
 COMPRESSION_FNAME              = vmlinuz
 else
 COMPRESSION_FNAME              = vmlinux
index 874b7ca4cd11de1d81d3a39d16bf986a7006d0c2..70783b75fd9df8553fe1d97e648ccd0cd566fd4f 100644 (file)
@@ -5,3 +5,4 @@ platform-$(CONFIG_BCM47XX)      += bcm47xx/
 cflags-$(CONFIG_BCM47XX)       +=                                      \
                -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
 load-$(CONFIG_BCM47XX)         := 0xffffffff80001000
+zload-$(CONFIG_BCM47XX)                += 0xffffffff80400000
index c675eece389a41c036c4ff2e1aeaf89509368a1f..adce180f3ee4264cabfdf85e7032f7c661b6a4c0 100644 (file)
@@ -133,4 +133,8 @@ vmlinuz.srec: vmlinuz
 uzImage.bin: vmlinuz.bin FORCE
        $(call if_changed,uimage,none)
 
-clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec}
+clean-files += $(objtree)/vmlinuz
+clean-files += $(objtree)/vmlinuz.32
+clean-files += $(objtree)/vmlinuz.ecoff
+clean-files += $(objtree)/vmlinuz.bin
+clean-files += $(objtree)/vmlinuz.srec
index 6a31759839b415d008b35e5159b2a81335de92c9..5b1361a89e021c749c7328dbf91a5673dfc0615d 100644 (file)
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_JZ4740_QI_LB60)   += qi_lb60.dtb
+dtb-$(CONFIG_JZ4770_GCW0)      += gcw0.dtb
 dtb-$(CONFIG_JZ4780_CI20)      += ci20.dtb
 
 obj-y                          += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
new file mode 100644 (file)
index 0000000..35f0291
--- /dev/null
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "jz4770.dtsi"
+
+/ {
+       compatible = "gcw,zero", "ingenic,jz4770";
+       model = "GCW Zero";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+       };
+
+       chosen {
+               stdout-path = "serial2:57600n8";
+       };
+
+       board {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               otg_phy: otg-phy {
+                       compatible = "usb-nop-xceiv";
+                       clocks = <&cgu JZ4770_CLK_OTG_PHY>;
+                       clock-names = "main_clk";
+               };
+       };
+};
+
+&ext {
+       clock-frequency = <12000000>;
+};
+
+&uart2 {
+       status = "okay";
+};
+
+&cgu {
+       /* Put high-speed peripherals under PLL1, such that we can change the
+        * PLL0 frequency on demand without having to suspend peripherals.
+        * We use a rate of 432 MHz, which is the least common multiple of
+        * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
+        */
+       assigned-clocks =
+               <&cgu JZ4770_CLK_PLL1>,
+               <&cgu JZ4770_CLK_UHC>;
+       assigned-clock-parents =
+               <0>,
+               <&cgu JZ4770_CLK_PLL1>;
+       assigned-clock-rates =
+               <432000000>;
+};
+
+&uhc {
+       /* The WiFi module is connected to the UHC. */
+       status = "okay";
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
new file mode 100644 (file)
index 0000000..7c2804f
--- /dev/null
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/clock/jz4770-cgu.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "ingenic,jz4770";
+
+       cpuintc: interrupt-controller {
+               #address-cells = <0>;
+               #interrupt-cells = <1>;
+               interrupt-controller;
+               compatible = "mti,cpu-interrupt-controller";
+       };
+
+       intc: interrupt-controller@10001000 {
+               compatible = "ingenic,jz4770-intc";
+               reg = <0x10001000 0x40>;
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+
+               interrupt-parent = <&cpuintc>;
+               interrupts = <2>;
+       };
+
+       ext: ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+       };
+
+       osc32k: osc32k {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+       };
+
+       cgu: jz4770-cgu@10000000 {
+               compatible = "ingenic,jz4770-cgu";
+               reg = <0x10000000 0x100>;
+
+               clocks = <&ext>, <&osc32k>;
+               clock-names = "ext", "osc32k";
+
+               #clock-cells = <1>;
+       };
+
+       pinctrl: pin-controller@10010000 {
+               compatible = "ingenic,jz4770-pinctrl";
+               reg = <0x10010000 0x600>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               gpa: gpio@0 {
+                       compatible = "ingenic,jz4770-gpio";
+                       reg = <0>;
+
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 0 32>;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <17>;
+               };
+
+               gpb: gpio@1 {
+                       compatible = "ingenic,jz4770-gpio";
+                       reg = <1>;
+
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 32 32>;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <16>;
+               };
+
+               gpc: gpio@2 {
+                       compatible = "ingenic,jz4770-gpio";
+                       reg = <2>;
+
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 64 32>;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <15>;
+               };
+
+               gpd: gpio@3 {
+                       compatible = "ingenic,jz4770-gpio";
+                       reg = <3>;
+
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 96 32>;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <14>;
+               };
+
+               gpe: gpio@4 {
+                       compatible = "ingenic,jz4770-gpio";
+                       reg = <4>;
+
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 128 32>;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <13>;
+               };
+
+               gpf: gpio@5 {
+                       compatible = "ingenic,jz4770-gpio";
+                       reg = <5>;
+
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 160 32>;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <12>;
+               };
+       };
+
+       uart0: serial@10030000 {
+               compatible = "ingenic,jz4770-uart";
+               reg = <0x10030000 0x100>;
+
+               clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
+               clock-names = "baud", "module";
+
+               interrupt-parent = <&intc>;
+               interrupts = <5>;
+
+               status = "disabled";
+       };
+
+       uart1: serial@10031000 {
+               compatible = "ingenic,jz4770-uart";
+               reg = <0x10031000 0x100>;
+
+               clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
+               clock-names = "baud", "module";
+
+               interrupt-parent = <&intc>;
+               interrupts = <4>;
+
+               status = "disabled";
+       };
+
+       uart2: serial@10032000 {
+               compatible = "ingenic,jz4770-uart";
+               reg = <0x10032000 0x100>;
+
+               clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
+               clock-names = "baud", "module";
+
+               interrupt-parent = <&intc>;
+               interrupts = <3>;
+
+               status = "disabled";
+       };
+
+       uart3: serial@10033000 {
+               compatible = "ingenic,jz4770-uart";
+               reg = <0x10033000 0x100>;
+
+               clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
+               clock-names = "baud", "module";
+
+               interrupt-parent = <&intc>;
+               interrupts = <2>;
+
+               status = "disabled";
+       };
+
+       uhc: uhc@13430000 {
+               compatible = "generic-ohci";
+               reg = <0x13430000 0x1000>;
+
+               clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
+               assigned-clocks = <&cgu JZ4770_CLK_UHC>;
+               assigned-clock-rates = <48000000>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <20>;
+
+               status = "disabled";
+       };
+};
index a55009edbb29a664ddbb3b53cadb80256ae7b351..5e73fe755be6cf151b73c9a73381675345ca3481 100644 (file)
@@ -153,7 +153,6 @@ CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
 # CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_VT is not set
 CONFIG_SERIAL_NONSTANDARD=y
diff --git a/arch/mips/configs/gcw0_defconfig b/arch/mips/configs/gcw0_defconfig
new file mode 100644 (file)
index 0000000..99ac1fa
--- /dev/null
@@ -0,0 +1,27 @@
+CONFIG_MACH_INGENIC=y
+CONFIG_JZ4770_GCW0=y
+CONFIG_HIGHMEM=y
+# CONFIG_BOUNCE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_SECCOMP is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EMBEDDED=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_INGENIC=y
+CONFIG_USB=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_TMPFS=y
diff --git a/arch/mips/configs/generic/board-ranchu.config b/arch/mips/configs/generic/board-ranchu.config
new file mode 100644 (file)
index 0000000..fee9ad4
--- /dev/null
@@ -0,0 +1,30 @@
+CONFIG_VIRT_BOARD_RANCHU=y
+
+CONFIG_BATTERY_GOLDFISH=y
+CONFIG_FB=y
+CONFIG_FB_GOLDFISH=y
+CONFIG_GOLDFISH=y
+CONFIG_STAGING=y
+CONFIG_GOLDFISH_AUDIO=y
+CONFIG_GOLDFISH_PIC=y
+CONFIG_GOLDFISH_PIPE=y
+CONFIG_GOLDFISH_TTY=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GOLDFISH=y
+
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_GOLDFISH_EVENTS=y
+
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
index a0d593248668ff7c6cf40536d4114fbdbb9bd63f..91a9c13e2c820ea26dc42f3769e767a95ba5b58b 100644 (file)
@@ -252,7 +252,6 @@ CONFIG_RT2800PCI=m
 CONFIG_WL12XX=m
 CONFIG_WL1251=m
 # CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_LIBPS2=m
 CONFIG_SERIO_RAW=m
 CONFIG_SERIO_ALTERA_PS2=m
index 1e26e58b9dc36c37d00c6c3c35d3dba3ee11f47d..ebff297328aed97d6fd8333203a16ddec0b2a94a 100644 (file)
@@ -75,7 +75,6 @@ CONFIG_DE2104X=m
 CONFIG_TULIP=m
 CONFIG_TULIP_MMIO=y
 CONFIG_INPUT_EVDEV=m
-# CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_MACEPS2=y
 CONFIG_SERIO_RAW=y
 # CONFIG_CONSOLE_TRANSLATIONS is not set
index 396408404487e1a248bd331b228bc1d4199dc111..df8a9a15ca83a71ed80a792c7655334601902335 100644 (file)
@@ -312,9 +312,8 @@ CONFIG_HOSTAP_PCI=m
 CONFIG_IPW2100=m
 CONFIG_IPW2100_MONITOR=y
 CONFIG_LIBERTAS=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
index 5691673a332772dedd4af5c80af14c2102e79d88..14df9ef15d408d7b6d9bd2868736c6b9852f4401 100644 (file)
@@ -324,9 +324,7 @@ CONFIG_HOSTAP_PCI=m
 CONFIG_IPW2100=m
 CONFIG_IPW2100_MONITOR=y
 CONFIG_LIBERTAS=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
+CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
index e9cadb37d684f74321c508abf61e0df2b4951353..25092e344574b8267822311596b8f1306204af19 100644 (file)
@@ -326,9 +326,7 @@ CONFIG_HOSTAP_PCI=m
 CONFIG_IPW2100=m
 CONFIG_IPW2100_MONITOR=y
 CONFIG_LIBERTAS=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
+CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
index 77145ecaa23bd35deb7b90b49fa220b846cc7e4e..210bf609f7858308548a6f437f69bef772462cc9 100644 (file)
@@ -126,6 +126,7 @@ CONFIG_PCNET32=y
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_VT is not set
 CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
index cc2687cfdc135dcd104086e8d98b436313c0e801..e5934aa98397189740359f5ecfe06d23a9e62890 100644 (file)
@@ -126,6 +126,7 @@ CONFIG_PCNET32=y
 # CONFIG_NET_VENDOR_TOSHIBA is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_VT is not set
 CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
index d8c8f5fb89180f956221cc3f913e7867d703b88a..cb2ca11c17893e2048b0060d6a6fa25993a4d24d 100644 (file)
@@ -127,6 +127,7 @@ CONFIG_PCNET32=y
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_VT is not set
 CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
index 04827bc9f87f97dd5aad599cc10fa9eb4fd22720..be29fcec69fcc70e325627bfa60f07e90f307c84 100644 (file)
@@ -130,6 +130,7 @@ CONFIG_PCNET32=y
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_VT is not set
 CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
index 7ea7c0ba26664ea5501749efb07423c413d4a524..40462d4c90a0159d563516664011c2bafa51f912 100644 (file)
@@ -125,6 +125,7 @@ CONFIG_PCNET32=y
 # CONFIG_NET_VENDOR_TOSHIBA is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_VT is not set
 CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
index 2942610e408216d99a9491e8811757866064321a..4e50176cb3df53e65c06fc00355b359ed0216a20 100644 (file)
@@ -321,9 +321,8 @@ CONFIG_HOSTAP_PCI=m
 CONFIG_IPW2100=m
 CONFIG_IPW2100_MONITOR=y
 CONFIG_LIBERTAS=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
index 7357248b3d7aa75df627dfb05f25a87ad64b5c58..e8e1dd8e0e99cd525dff3e5b2f9bd8de413461a4 100644 (file)
@@ -399,7 +399,6 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_SERPORT=m
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
index 1e18fd7de209bc9be10006589cf03b11870b0c99..c4477a4d40c119b5ad053cdca84de40a9996fc32 100644 (file)
@@ -332,7 +332,6 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_SERPORT=m
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
index 81b5eb89446c76d02b29f9ea929893f0e98cebc8..e73cdb08fc6ea86a9ec8d27aeadfff700de92f4a 100644 (file)
@@ -49,7 +49,6 @@ CONFIG_INPUT_EVDEV=m
 CONFIG_INPUT_EVBUG=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
 # CONFIG_VT_CONSOLE is not set
 CONFIG_SERIAL_PNX8XXX=y
 CONFIG_SERIAL_PNX8XXX_CONSOLE=y
index c724bdd6a7e615b5a966e2f948519f033f4f4985..1edd8430ad61ed0790f68c7737fb42ee1481fd40 100644 (file)
@@ -65,7 +65,6 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SB1250_MAC=y
 # CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_VT is not set
 # CONFIG_HW_RANDOM is not set
index 52e0286a161203d5904089c301bb2120a28cd77d..2ff3b17bfab18d829d74a1cb8c0e3fb790789d1b 100644 (file)
@@ -49,4 +49,14 @@ config FIT_IMAGE_FDT_XILFPGA
          Enable this to include the FDT for the MIPSfpga platform
          from Imagination Technologies in the FIT kernel image.
 
+config VIRT_BOARD_RANCHU
+       bool "Support Ranchu platform for Android emulator"
+       help
+         This enables support for the platform used by Android emulator.
+
+         Ranchu platform consists of a set of virtual devices. This platform
+         enables emulation of variety of virtual configurations while using
+         Android emulator. Android emulator is based on Qemu, and contains
+         the support for the same set of virtual devices.
+
 endif
index 874967363dbb20a0c61d6f21b3cbc4d211c7a77d..5c31e0c4697dd69a88cde68eee45c89c331ec0db 100644 (file)
@@ -15,3 +15,4 @@ obj-y += proc.o
 obj-$(CONFIG_YAMON_DT_SHIM)            += yamon-dt.o
 obj-$(CONFIG_LEGACY_BOARD_SEAD3)       += board-sead3.o
 obj-$(CONFIG_KEXEC)                    += kexec.o
+obj-$(CONFIG_VIRT_BOARD_RANCHU)                += board-ranchu.o
diff --git a/arch/mips/generic/board-ranchu.c b/arch/mips/generic/board-ranchu.c
new file mode 100644 (file)
index 0000000..59a8c18
--- /dev/null
@@ -0,0 +1,93 @@
+/*
+ * Support code for virtual Ranchu board for MIPS.
+ *
+ * Author: Miodrag Dinic <miodrag.dinic@mips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/of_address.h>
+#include <linux/types.h>
+
+#include <asm/machine.h>
+#include <asm/mipsregs.h>
+#include <asm/time.h>
+
+#define GOLDFISH_TIMER_LOW             0x00
+#define GOLDFISH_TIMER_HIGH            0x04
+
+static __init u64 read_rtc_time(void __iomem *base)
+{
+       u32 time_low;
+       u32 time_high;
+
+       /*
+        * Reading the low address latches the high value
+        * as well so there is no fear that we may read
+        * inaccurate high value.
+        */
+       time_low = readl(base + GOLDFISH_TIMER_LOW);
+       time_high = readl(base + GOLDFISH_TIMER_HIGH);
+
+       return ((u64)time_high << 32) | time_low;
+}
+
+static __init unsigned int ranchu_measure_hpt_freq(void)
+{
+       u64 rtc_start, rtc_current, rtc_delta;
+       unsigned int start, count;
+       struct device_node *np;
+       void __iomem *rtc_base;
+
+       np = of_find_compatible_node(NULL, NULL, "google,goldfish-rtc");
+       if (!np)
+               panic("%s(): Failed to find 'google,goldfish-rtc' dt node!",
+                     __func__);
+
+       rtc_base = of_iomap(np, 0);
+       if (!rtc_base)
+               panic("%s(): Failed to ioremap Goldfish RTC base!", __func__);
+
+       /*
+        * Poll the nanosecond resolution RTC for one
+        * second to calibrate the CPU frequency.
+        */
+       rtc_start = read_rtc_time(rtc_base);
+       start = read_c0_count();
+
+       do {
+               rtc_current = read_rtc_time(rtc_base);
+               rtc_delta = rtc_current - rtc_start;
+       } while (rtc_delta < NSEC_PER_SEC);
+
+       count = read_c0_count() - start;
+
+       /*
+        * Make sure the frequency will be a round number.
+        * Without this correction, the returned value may vary
+        * between subsequent emulation executions.
+        *
+        * TODO: Set this value using device tree.
+        */
+       count += 5000;
+       count -= count % 10000;
+
+       iounmap(rtc_base);
+
+       return count;
+}
+
+static const struct of_device_id ranchu_of_match[] __initconst = {
+       {
+               .compatible = "mti,ranchu",
+       },
+       {}
+};
+
+MIPS_MACHINE(ranchu) = {
+       .matches = ranchu_of_match,
+       .measure_hpt_freq = ranchu_measure_hpt_freq,
+};
index 394f8161e4628680e82a79bf81c63160e0752bf8..cb7fdaeef426c88bc4a90a8d980b73a39b5bf824 100644 (file)
@@ -22,10 +22,10 @@ int get_c0_fdc_int(void)
 {
        int mips_cpu_fdc_irq;
 
-       if (cpu_has_veic)
-               panic("Unimplemented!");
-       else if (mips_gic_present())
+       if (mips_gic_present())
                mips_cpu_fdc_irq = gic_get_c0_fdc_int();
+       else if (cpu_has_veic)
+               panic("Unimplemented!");
        else if (cp0_fdc_irq >= 0)
                mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
        else
@@ -38,10 +38,10 @@ int get_c0_perfcount_int(void)
 {
        int mips_cpu_perf_irq;
 
-       if (cpu_has_veic)
-               panic("Unimplemented!");
-       else if (mips_gic_present())
+       if (mips_gic_present())
                mips_cpu_perf_irq = gic_get_c0_perfcount_int();
+       else if (cpu_has_veic)
+               panic("Unimplemented!");
        else if (cp0_perfcount_irq >= 0)
                mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
        else
@@ -54,10 +54,10 @@ unsigned int get_c0_compare_int(void)
 {
        int mips_cpu_timer_irq;
 
-       if (cpu_has_veic)
-               panic("Unimplemented!");
-       else if (mips_gic_present())
+       if (mips_gic_present())
                mips_cpu_timer_irq = gic_get_c0_compare_int();
+       else if (cpu_has_veic)
+               panic("Unimplemented!");
        else
                mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 
index e26a093bb17a2e34e2079f1e5cda21a66052e843..a301a8f4bc6683b502165f5236fe6bd3dbdd7980 100644 (file)
@@ -79,6 +79,8 @@ enum loongson_machine_type {
  */
 #define  MACH_INGENIC_JZ4730   0       /* JZ4730 SOC           */
 #define  MACH_INGENIC_JZ4740   1       /* JZ4740 SOC           */
+#define  MACH_INGENIC_JZ4770   2       /* JZ4770 SOC           */
+#define  MACH_INGENIC_JZ4780   3       /* JZ4780 SOC           */
 
 extern char *system_type;
 const char *get_system_type(void);
index 77cad232a1c61cde88587230374ba153dd6bc975..e8161e4dfde7039a80cb3875bba7b9415520c67b 100644 (file)
@@ -110,7 +110,7 @@ __wsum csum_partial_copy_nocheck(const void *src, void *dst,
  */
 static inline __sum16 csum_fold(__wsum csum)
 {
-       u32 sum = (__force u32)csum;;
+       u32 sum = (__force u32)csum;
 
        sum += (sum << 16);
        csum = (sum < csum);
index 4f69f08717f6efc08bd3db360e8d2e32834ef04e..8c286bedff3e15339ba292f6fed55c7c44df5a81 100644 (file)
@@ -4,7 +4,7 @@
 
 #define SYSTEM_RAM_LOW         1
 #define SYSTEM_RAM_HIGH                2
-#define MEM_RESERVED           3
+#define SYSTEM_RAM_RESERVED    3
 #define PCI_IO                 4
 #define PCI_MEM                        5
 #define LOONGSON_CFG_REG       6
index e0d9b373d415195f95d34c628e94c621a1306462..f83879dadd1e3693023f17c6a707fbd91d2e3a98 100644 (file)
@@ -52,7 +52,7 @@ mips_machine_is_compatible(const struct mips_machine *mach, const void *fdt)
        if (!mach->matches)
                return NULL;
 
-       for (match = mach->matches; match->compatible; match++) {
+       for (match = mach->matches; match->compatible[0]; match++) {
                if (fdt_node_check_compatible(fdt, 0, match->compatible) == 0)
                        return match;
        }
index 6b1f1ad0542c9aa559d203c3d6082c5944c50942..858752dac3373475234063ba8940013bc5f97cae 100644 (file)
@@ -1180,6 +1180,89 @@ static inline int mm_insn_16bit(u16 insn)
 #define _ASM_INSN_IF_MIPS(_enc)
 #endif
 
+/*
+ * parse_r var, r - Helper assembler macro for parsing register names.
+ *
+ * This converts the register name in $n form provided in \r to the
+ * corresponding register number, which is assigned to the variable \var. It is
+ * needed to allow explicit encoding of instructions in inline assembly where
+ * registers are chosen by the compiler in $n form, allowing us to avoid using
+ * fixed register numbers.
+ *
+ * It also allows newer instructions (not implemented by the assembler) to be
+ * transparently implemented using assembler macros, instead of needing separate
+ * cases depending on toolchain support.
+ *
+ * Simple usage example:
+ * __asm__ __volatile__("parse_r __rt, %0\n\t"
+ *                     ".insn\n\t"
+ *                     "# di    %0\n\t"
+ *                     ".word   (0x41606000 | (__rt << 16))"
+ *                     : "=r" (status);
+ */
+
+/* Match an individual register number and assign to \var */
+#define _IFC_REG(n)                            \
+       ".ifc   \\r, $" #n "\n\t"               \
+       "\\var  = " #n "\n\t"                   \
+       ".endif\n\t"
+
+__asm__(".macro        parse_r var r\n\t"
+       "\\var  = -1\n\t"
+       _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
+       _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
+       _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
+       _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
+       _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
+       _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
+       _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
+       _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
+       ".iflt  \\var\n\t"
+       ".error \"Unable to parse register name \\r\"\n\t"
+       ".endif\n\t"
+       ".endm");
+
+#undef _IFC_REG
+
+/*
+ * C macros for generating assembler macros for common instruction formats.
+ *
+ * The names of the operands can be chosen by the caller, and the encoding of
+ * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
+ * the ENC encodings.
+ */
+
+/* Instructions with no operands */
+#define _ASM_MACRO_0(OP, ENC)                                          \
+       __asm__(".macro " #OP "\n\t"                                    \
+               ENC                                                     \
+               ".endm")
+
+/* Instructions with 2 register operands */
+#define _ASM_MACRO_2R(OP, R1, R2, ENC)                                 \
+       __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t"                   \
+               "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+               "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
+               ENC                                                     \
+               ".endm")
+
+/* Instructions with 3 register operands */
+#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)                             \
+       __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t"          \
+               "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+               "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
+               "parse_r __" #R3 ", \\" #R3 "\n\t"                      \
+               ENC                                                     \
+               ".endm")
+
+/* Instructions with 2 register operands and 1 optional select operand */
+#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)                                \
+       __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"    \
+               "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+               "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
+               ENC                                                     \
+               ".endm")
+
 /*
  * TLB Invalidate Flush
  */
@@ -1245,14 +1328,14 @@ do {                                                            \
  * Macros to access the system control coprocessor
  */
 
-#define __read_32bit_c0_register(source, sel)                          \
+#define ___read_32bit_c0_register(source, sel, vol)                    \
 ({ unsigned int __res;                                                 \
        if (sel == 0)                                                   \
-               __asm__ __volatile__(                                   \
+               __asm__ vol(                                            \
                        "mfc0\t%0, " #source "\n\t"                     \
                        : "=r" (__res));                                \
        else                                                            \
-               __asm__ __volatile__(                                   \
+               __asm__ vol(                                            \
                        ".set\tmips32\n\t"                              \
                        "mfc0\t%0, " #source ", " #sel "\n\t"           \
                        ".set\tmips0\n\t"                               \
@@ -1260,18 +1343,18 @@ do {                                                            \
        __res;                                                          \
 })
 
-#define __read_64bit_c0_register(source, sel)                          \
+#define ___read_64bit_c0_register(source, sel, vol)                    \
 ({ unsigned long long __res;                                           \
        if (sizeof(unsigned long) == 4)                                 \
-               __res = __read_64bit_c0_split(source, sel);             \
+               __res = __read_64bit_c0_split(source, sel, vol);        \
        else if (sel == 0)                                              \
-               __asm__ __volatile__(                                   \
+               __asm__ vol(                                            \
                        ".set\tmips3\n\t"                               \
                        "dmfc0\t%0, " #source "\n\t"                    \
                        ".set\tmips0"                                   \
                        : "=r" (__res));                                \
        else                                                            \
-               __asm__ __volatile__(                                   \
+               __asm__ vol(                                            \
                        ".set\tmips64\n\t"                              \
                        "dmfc0\t%0, " #source ", " #sel "\n\t"          \
                        ".set\tmips0"                                   \
@@ -1279,6 +1362,18 @@ do {                                                             \
        __res;                                                          \
 })
 
+#define __read_32bit_c0_register(source, sel)                          \
+       ___read_32bit_c0_register(source, sel, __volatile__)
+
+#define __read_const_32bit_c0_register(source, sel)                    \
+       ___read_32bit_c0_register(source, sel,)
+
+#define __read_64bit_c0_register(source, sel)                          \
+       ___read_64bit_c0_register(source, sel, __volatile__)
+
+#define __read_const_64bit_c0_register(source, sel)                    \
+       ___read_64bit_c0_register(source, sel,)
+
 #define __write_32bit_c0_register(register, sel, value)                        \
 do {                                                                   \
        if (sel == 0)                                                   \
@@ -1316,6 +1411,11 @@ do {                                                                     \
        (unsigned long) __read_32bit_c0_register(reg, sel) :            \
        (unsigned long) __read_64bit_c0_register(reg, sel))
 
+#define __read_const_ulong_c0_register(reg, sel)                       \
+       ((sizeof(unsigned long) == 4) ?                                 \
+       (unsigned long) __read_const_32bit_c0_register(reg, sel) :      \
+       (unsigned long) __read_const_64bit_c0_register(reg, sel))
+
 #define __write_ulong_c0_register(reg, sel, val)                       \
 do {                                                                   \
        if (sizeof(unsigned long) == 4)                                 \
@@ -1346,14 +1446,14 @@ do {                                                                    \
  * These versions are only needed for systems with more than 38 bits of
  * physical address space running the 32-bit kernel.  That's none atm :-)
  */
-#define __read_64bit_c0_split(source, sel)                             \
+#define __read_64bit_c0_split(source, sel, vol)                                \
 ({                                                                     \
        unsigned long long __val;                                       \
        unsigned long __flags;                                          \
                                                                        \
        local_irq_save(__flags);                                        \
        if (sel == 0)                                                   \
-               __asm__ __volatile__(                                   \
+               __asm__ vol(                                            \
                        ".set\tmips64\n\t"                              \
                        "dmfc0\t%L0, " #source "\n\t"                   \
                        "dsra\t%M0, %L0, 32\n\t"                        \
@@ -1361,7 +1461,7 @@ do {                                                                      \
                        ".set\tmips0"                                   \
                        : "=r" (__val));                                \
        else                                                            \
-               __asm__ __volatile__(                                   \
+               __asm__ vol(                                            \
                        ".set\tmips64\n\t"                              \
                        "dmfc0\t%L0, " #source ", " #sel "\n\t"         \
                        "dsra\t%M0, %L0, 32\n\t"                        \
@@ -1404,37 +1504,43 @@ do {                                                                    \
        local_irq_restore(__flags);                                     \
 } while (0)
 
-#define __readx_32bit_c0_register(source)                              \
+#ifndef TOOLCHAIN_SUPPORTS_XPA
+_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
+       _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
+       _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
+       _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
+       _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
+#define _ASM_SET_XPA ""
+#else  /* !TOOLCHAIN_SUPPORTS_XPA */
+#define _ASM_SET_XPA ".set\txpa\n\t"
+#endif
+
+#define __readx_32bit_c0_register(source, sel)                         \
 ({                                                                     \
        unsigned int __res;                                             \
                                                                        \
        __asm__ __volatile__(                                           \
        "       .set    push                                    \n"     \
-       "       .set    noat                                    \n"     \
        "       .set    mips32r2                                \n"     \
-       "       # mfhc0 $1, %1                                  \n"     \
-       _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11))             \
-       _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16))             \
-       "       move    %0, $1                                  \n"     \
+       _ASM_SET_XPA                                                    \
+       "       mfhc0   %0, " #source ", %1                     \n"     \
        "       .set    pop                                     \n"     \
        : "=r" (__res)                                                  \
-       : "i" (source));                                                \
+       : "i" (sel));                                                   \
        __res;                                                          \
 })
 
-#define __writex_32bit_c0_register(register, value)                    \
+#define __writex_32bit_c0_register(register, sel, value)               \
 do {                                                                   \
        __asm__ __volatile__(                                           \
        "       .set    push                                    \n"     \
-       "       .set    noat                                    \n"     \
        "       .set    mips32r2                                \n"     \
-       "       move    $1, %0                                  \n"     \
-       "       # mthc0 $1, %1                                  \n"     \
-       _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11))             \
-       _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16))             \
+       _ASM_SET_XPA                                                    \
+       "       mthc0   %z0, " #register ", %1                  \n"     \
        "       .set    pop                                     \n"     \
        :                                                               \
-       : "r" (value), "i" (register));                                 \
+       : "Jr" (value), "i" (sel));                                     \
 } while (0)
 
 #define read_c0_index()                __read_32bit_c0_register($0, 0)
@@ -1446,14 +1552,14 @@ do {                                                                    \
 #define read_c0_entrylo0()     __read_ulong_c0_register($2, 0)
 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
 
-#define readx_c0_entrylo0()    __readx_32bit_c0_register(2)
-#define writex_c0_entrylo0(val)        __writex_32bit_c0_register(2, val)
+#define readx_c0_entrylo0()    __readx_32bit_c0_register($2, 0)
+#define writex_c0_entrylo0(val)        __writex_32bit_c0_register($2, 0, val)
 
 #define read_c0_entrylo1()     __read_ulong_c0_register($3, 0)
 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
 
-#define readx_c0_entrylo1()    __readx_32bit_c0_register(3)
-#define writex_c0_entrylo1(val)        __writex_32bit_c0_register(3, val)
+#define readx_c0_entrylo1()    __readx_32bit_c0_register($3, 0)
+#define writex_c0_entrylo1(val)        __writex_32bit_c0_register($3, 0, val)
 
 #define read_c0_conf()         __read_32bit_c0_register($3, 0)
 #define write_c0_conf(val)     __write_32bit_c0_register($3, 0, val)
@@ -1541,7 +1647,7 @@ do {                                                                      \
 #define read_c0_epc()          __read_ulong_c0_register($14, 0)
 #define write_c0_epc(val)      __write_ulong_c0_register($14, 0, val)
 
-#define read_c0_prid()         __read_32bit_c0_register($15, 0)
+#define read_c0_prid()         __read_const_32bit_c0_register($15, 0)
 
 #define read_c0_cmgcrbase()    __read_ulong_c0_register($15, 3)
 
@@ -1830,18 +1936,44 @@ do {                                                                    \
  * Macros to access the guest system control coprocessor
  */
 
-#ifdef TOOLCHAIN_SUPPORTS_VIRT
+#ifndef TOOLCHAIN_SUPPORTS_VIRT
+_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
+       _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
+       _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
+       _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
+       _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
+       _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
+       _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
+       _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
+       _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
+_ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
+                      _ASM_INSN32_IF_MM(0x0000017c));
+_ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
+                      _ASM_INSN32_IF_MM(0x0000117c));
+_ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
+                      _ASM_INSN32_IF_MM(0x0000217c));
+_ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
+                      _ASM_INSN32_IF_MM(0x0000317c));
+_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
+                      _ASM_INSN32_IF_MM(0x0000517c));
+#define _ASM_SET_VIRT ""
+#else  /* !TOOLCHAIN_SUPPORTS_VIRT */
+#define _ASM_SET_VIRT ".set\tvirt\n\t"
+#endif
 
 #define __read_32bit_gc0_register(source, sel)                         \
 ({ int __res;                                                          \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
                ".set\tmips32r2\n\t"                                    \
-               ".set\tvirt\n\t"                                        \
-               "mfgc0\t%0, $%1, %2\n\t"                                \
+               _ASM_SET_VIRT                                           \
+               "mfgc0\t%0, " #source ", %1\n\t"                        \
                ".set\tpop"                                             \
                : "=r" (__res)                                          \
-               : "i" (source), "i" (sel));                             \
+               : "i" (sel));                                           \
        __res;                                                          \
 })
 
@@ -1850,11 +1982,11 @@ do {                                                                    \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
                ".set\tmips64r2\n\t"                                    \
-               ".set\tvirt\n\t"                                        \
-               "dmfgc0\t%0, $%1, %2\n\t"                       \
+               _ASM_SET_VIRT                                           \
+               "dmfgc0\t%0, " #source ", %1\n\t"                       \
                ".set\tpop"                                             \
                : "=r" (__res)                                          \
-               : "i" (source), "i" (sel));                             \
+               : "i" (sel));                                           \
        __res;                                                          \
 })
 
@@ -1863,11 +1995,11 @@ do {                                                                    \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
                ".set\tmips32r2\n\t"                                    \
-               ".set\tvirt\n\t"                                        \
-               "mtgc0\t%z0, $%1, %2\n\t"                               \
+               _ASM_SET_VIRT                                           \
+               "mtgc0\t%z0, " #register ", %1\n\t"                     \
                ".set\tpop"                                             \
                : : "Jr" ((unsigned int)(value)),                       \
-                   "i" (register), "i" (sel));                         \
+                   "i" (sel));                                         \
 } while (0)
 
 #define __write_64bit_gc0_register(register, sel, value)               \
@@ -1875,75 +2007,13 @@ do {                                                                    \
        __asm__ __volatile__(                                           \
                ".set\tpush\n\t"                                        \
                ".set\tmips64r2\n\t"                                    \
-               ".set\tvirt\n\t"                                        \
-               "dmtgc0\t%z0, $%1, %2\n\t"                              \
+               _ASM_SET_VIRT                                           \
+               "dmtgc0\t%z0, " #register ", %1\n\t"                    \
                ".set\tpop"                                             \
                : : "Jr" (value),                                       \
-                   "i" (register), "i" (sel));                         \
+                   "i" (sel));                                         \
 } while (0)
 
-#else  /* TOOLCHAIN_SUPPORTS_VIRT */
-
-#define __read_32bit_gc0_register(source, sel)                         \
-({ int __res;                                                          \
-       __asm__ __volatile__(                                           \
-               ".set\tpush\n\t"                                        \
-               ".set\tnoat\n\t"                                        \
-               "# mfgc0\t$1, $%1, %2\n\t"                              \
-               _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2)           \
-               _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11)     \
-               "move\t%0, $1\n\t"                                      \
-               ".set\tpop"                                             \
-               : "=r" (__res)                                          \
-               : "i" (source), "i" (sel));                             \
-       __res;                                                          \
-})
-
-#define __read_64bit_gc0_register(source, sel)                         \
-({ unsigned long long __res;                                           \
-       __asm__ __volatile__(                                           \
-               ".set\tpush\n\t"                                        \
-               ".set\tnoat\n\t"                                        \
-               "# dmfgc0\t$1, $%1, %2\n\t"                             \
-               _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2)           \
-               _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11)     \
-               "move\t%0, $1\n\t"                                      \
-               ".set\tpop"                                             \
-               : "=r" (__res)                                          \
-               : "i" (source), "i" (sel));                             \
-       __res;                                                          \
-})
-
-#define __write_32bit_gc0_register(register, sel, value)               \
-do {                                                                   \
-       __asm__ __volatile__(                                           \
-               ".set\tpush\n\t"                                        \
-               ".set\tnoat\n\t"                                        \
-               "move\t$1, %z0\n\t"                                     \
-               "# mtgc0\t$1, $%1, %2\n\t"                              \
-               _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2)           \
-               _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11)     \
-               ".set\tpop"                                             \
-               : : "Jr" ((unsigned int)(value)),                       \
-                   "i" (register), "i" (sel));                         \
-} while (0)
-
-#define __write_64bit_gc0_register(register, sel, value)               \
-do {                                                                   \
-       __asm__ __volatile__(                                           \
-               ".set\tpush\n\t"                                        \
-               ".set\tnoat\n\t"                                        \
-               "move\t$1, %z0\n\t"                                     \
-               "# dmtgc0\t$1, $%1, %2\n\t"                             \
-               _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2)           \
-               _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11)     \
-               ".set\tpop"                                             \
-               : : "Jr" (value),                                       \
-                   "i" (register), "i" (sel));                         \
-} while (0)
-
-#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
-
 #define __read_ulong_gc0_register(reg, sel)                            \
        ((sizeof(unsigned long) == 4) ?                                 \
        (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
@@ -1957,207 +2027,207 @@ do {                                                                  \
                __write_64bit_gc0_register(reg, sel, val);              \
 } while (0)
 
-#define read_gc0_index()               __read_32bit_gc0_register(0, 0)
-#define write_gc0_index(val)           __write_32bit_gc0_register(0, 0, val)
+#define read_gc0_index()               __read_32bit_gc0_register($0, 0)
+#define write_gc0_index(val)           __write_32bit_gc0_register($0, 0, val)
 
-#define read_gc0_entrylo0()            __read_ulong_gc0_register(2, 0)
-#define write_gc0_entrylo0(val)                __write_ulong_gc0_register(2, 0, val)
+#define read_gc0_entrylo0()            __read_ulong_gc0_register($2, 0)
+#define write_gc0_entrylo0(val)                __write_ulong_gc0_register($2, 0, val)
 
-#define read_gc0_entrylo1()            __read_ulong_gc0_register(3, 0)
-#define write_gc0_entrylo1(val)                __write_ulong_gc0_register(3, 0, val)
+#define read_gc0_entrylo1()            __read_ulong_gc0_register($3, 0)
+#define write_gc0_entrylo1(val)                __write_ulong_gc0_register($3, 0, val)
 
-#define read_gc0_context()             __read_ulong_gc0_register(4, 0)
-#define write_gc0_context(val)         __write_ulong_gc0_register(4, 0, val)
+#define read_gc0_context()             __read_ulong_gc0_register($4, 0)
+#define write_gc0_context(val)         __write_ulong_gc0_register($4, 0, val)
 
-#define read_gc0_contextconfig()       __read_32bit_gc0_register(4, 1)
-#define write_gc0_contextconfig(val)   __write_32bit_gc0_register(4, 1, val)
+#define read_gc0_contextconfig()       __read_32bit_gc0_register($4, 1)
+#define write_gc0_contextconfig(val)   __write_32bit_gc0_register($4, 1, val)
 
-#define read_gc0_userlocal()           __read_ulong_gc0_register(4, 2)
-#define write_gc0_userlocal(val)       __write_ulong_gc0_register(4, 2, val)
+#define read_gc0_userlocal()           __read_ulong_gc0_register($4, 2)
+#define write_gc0_userlocal(val)       __write_ulong_gc0_register($4, 2, val)
 
-#define read_gc0_xcontextconfig()      __read_ulong_gc0_register(4, 3)
-#define write_gc0_xcontextconfig(val)  __write_ulong_gc0_register(4, 3, val)
+#define read_gc0_xcontextconfig()      __read_ulong_gc0_register($4, 3)
+#define write_gc0_xcontextconfig(val)  __write_ulong_gc0_register($4, 3, val)
 
-#define read_gc0_pagemask()            __read_32bit_gc0_register(5, 0)
-#define write_gc0_pagemask(val)                __write_32bit_gc0_register(5, 0, val)
+#define read_gc0_pagemask()            __read_32bit_gc0_register($5, 0)
+#define write_gc0_pagemask(val)                __write_32bit_gc0_register($5, 0, val)
 
-#define read_gc0_pagegrain()           __read_32bit_gc0_register(5, 1)
-#define write_gc0_pagegrain(val)       __write_32bit_gc0_register(5, 1, val)
+#define read_gc0_pagegrain()           __read_32bit_gc0_register($5, 1)
+#define write_gc0_pagegrain(val)       __write_32bit_gc0_register($5, 1, val)
 
-#define read_gc0_segctl0()             __read_ulong_gc0_register(5, 2)
-#define write_gc0_segctl0(val)         __write_ulong_gc0_register(5, 2, val)
+#define read_gc0_segctl0()             __read_ulong_gc0_register($5, 2)
+#define write_gc0_segctl0(val)         __write_ulong_gc0_register($5, 2, val)
 
-#define read_gc0_segctl1()             __read_ulong_gc0_register(5, 3)
-#define write_gc0_segctl1(val)         __write_ulong_gc0_register(5, 3, val)
+#define read_gc0_segctl1()             __read_ulong_gc0_register($5, 3)
+#define write_gc0_segctl1(val)         __write_ulong_gc0_register($5, 3, val)
 
-#define read_gc0_segctl2()             __read_ulong_gc0_register(5, 4)
-#define write_gc0_segctl2(val)         __write_ulong_gc0_register(5, 4, val)
+#define read_gc0_segctl2()             __read_ulong_gc0_register($5, 4)
+#define write_gc0_segctl2(val)         __write_ulong_gc0_register($5, 4, val)
 
-#define read_gc0_pwbase()              __read_ulong_gc0_register(5, 5)
-#define write_gc0_pwbase(val)          __write_ulong_gc0_register(5, 5, val)
+#define read_gc0_pwbase()              __read_ulong_gc0_register($5, 5)
+#define write_gc0_pwbase(val)          __write_ulong_gc0_register($5, 5, val)
 
-#define read_gc0_pwfield()             __read_ulong_gc0_register(5, 6)
-#define write_gc0_pwfield(val)         __write_ulong_gc0_register(5, 6, val)
+#define read_gc0_pwfield()             __read_ulong_gc0_register($5, 6)
+#define write_gc0_pwfield(val)         __write_ulong_gc0_register($5, 6, val)
 
-#define read_gc0_pwsize()              __read_ulong_gc0_register(5, 7)
-#define write_gc0_pwsize(val)          __write_ulong_gc0_register(5, 7, val)
+#define read_gc0_pwsize()              __read_ulong_gc0_register($5, 7)
+#define write_gc0_pwsize(val)          __write_ulong_gc0_register($5, 7, val)
 
-#define read_gc0_wired()               __read_32bit_gc0_register(6, 0)
-#define write_gc0_wired(val)           __write_32bit_gc0_register(6, 0, val)
+#define read_gc0_wired()               __read_32bit_gc0_register($6, 0)
+#define write_gc0_wired(val)           __write_32bit_gc0_register($6, 0, val)
 
-#define read_gc0_pwctl()               __read_32bit_gc0_register(6, 6)
-#define write_gc0_pwctl(val)           __write_32bit_gc0_register(6, 6, val)
-
-#define read_gc0_hwrena()              __read_32bit_gc0_register(7, 0)
-#define write_gc0_hwrena(val)          __write_32bit_gc0_register(7, 0, val)
-
-#define read_gc0_badvaddr()            __read_ulong_gc0_register(8, 0)
-#define write_gc0_badvaddr(val)                __write_ulong_gc0_register(8, 0, val)
-
-#define read_gc0_badinstr()            __read_32bit_gc0_register(8, 1)
-#define write_gc0_badinstr(val)                __write_32bit_gc0_register(8, 1, val)
-
-#define read_gc0_badinstrp()           __read_32bit_gc0_register(8, 2)
-#define write_gc0_badinstrp(val)       __write_32bit_gc0_register(8, 2, val)
-
-#define read_gc0_count()               __read_32bit_gc0_register(9, 0)
-
-#define read_gc0_entryhi()             __read_ulong_gc0_register(10, 0)
-#define write_gc0_entryhi(val)         __write_ulong_gc0_register(10, 0, val)
-
-#define read_gc0_compare()             __read_32bit_gc0_register(11, 0)
-#define write_gc0_compare(val)         __write_32bit_gc0_register(11, 0, val)
-
-#define read_gc0_status()              __read_32bit_gc0_register(12, 0)
-#define write_gc0_status(val)          __write_32bit_gc0_register(12, 0, val)
-
-#define read_gc0_intctl()              __read_32bit_gc0_register(12, 1)
-#define write_gc0_intctl(val)          __write_32bit_gc0_register(12, 1, val)
-
-#define read_gc0_cause()               __read_32bit_gc0_register(13, 0)
-#define write_gc0_cause(val)           __write_32bit_gc0_register(13, 0, val)
-
-#define read_gc0_epc()                 __read_ulong_gc0_register(14, 0)
-#define write_gc0_epc(val)             __write_ulong_gc0_register(14, 0, val)
-
-#define read_gc0_prid()                        __read_32bit_gc0_register(15, 0)
-
-#define read_gc0_ebase()               __read_32bit_gc0_register(15, 1)
-#define write_gc0_ebase(val)           __write_32bit_gc0_register(15, 1, val)
-
-#define read_gc0_ebase_64()            __read_64bit_gc0_register(15, 1)
-#define write_gc0_ebase_64(val)                __write_64bit_gc0_register(15, 1, val)
-
-#define read_gc0_config()              __read_32bit_gc0_register(16, 0)
-#define read_gc0_config1()             __read_32bit_gc0_register(16, 1)
-#define read_gc0_config2()             __read_32bit_gc0_register(16, 2)
-#define read_gc0_config3()             __read_32bit_gc0_register(16, 3)
-#define read_gc0_config4()             __read_32bit_gc0_register(16, 4)
-#define read_gc0_config5()             __read_32bit_gc0_register(16, 5)
-#define read_gc0_config6()             __read_32bit_gc0_register(16, 6)
-#define read_gc0_config7()             __read_32bit_gc0_register(16, 7)
-#define write_gc0_config(val)          __write_32bit_gc0_register(16, 0, val)
-#define write_gc0_config1(val)         __write_32bit_gc0_register(16, 1, val)
-#define write_gc0_config2(val)         __write_32bit_gc0_register(16, 2, val)
-#define write_gc0_config3(val)         __write_32bit_gc0_register(16, 3, val)
-#define write_gc0_config4(val)         __write_32bit_gc0_register(16, 4, val)
-#define write_gc0_config5(val)         __write_32bit_gc0_register(16, 5, val)
-#define write_gc0_config6(val)         __write_32bit_gc0_register(16, 6, val)
-#define write_gc0_config7(val)         __write_32bit_gc0_register(16, 7, val)
-
-#define read_gc0_lladdr()              __read_ulong_gc0_register(17, 0)
-#define write_gc0_lladdr(val)          __write_ulong_gc0_register(17, 0, val)
-
-#define read_gc0_watchlo0()            __read_ulong_gc0_register(18, 0)
-#define read_gc0_watchlo1()            __read_ulong_gc0_register(18, 1)
-#define read_gc0_watchlo2()            __read_ulong_gc0_register(18, 2)
-#define read_gc0_watchlo3()            __read_ulong_gc0_register(18, 3)
-#define read_gc0_watchlo4()            __read_ulong_gc0_register(18, 4)
-#define read_gc0_watchlo5()            __read_ulong_gc0_register(18, 5)
-#define read_gc0_watchlo6()            __read_ulong_gc0_register(18, 6)
-#define read_gc0_watchlo7()            __read_ulong_gc0_register(18, 7)
-#define write_gc0_watchlo0(val)                __write_ulong_gc0_register(18, 0, val)
-#define write_gc0_watchlo1(val)                __write_ulong_gc0_register(18, 1, val)
-#define write_gc0_watchlo2(val)                __write_ulong_gc0_register(18, 2, val)
-#define write_gc0_watchlo3(val)                __write_ulong_gc0_register(18, 3, val)
-#define write_gc0_watchlo4(val)                __write_ulong_gc0_register(18, 4, val)
-#define write_gc0_watchlo5(val)                __write_ulong_gc0_register(18, 5, val)
-#define write_gc0_watchlo6(val)                __write_ulong_gc0_register(18, 6, val)
-#define write_gc0_watchlo7(val)                __write_ulong_gc0_register(18, 7, val)
-
-#define read_gc0_watchhi0()            __read_32bit_gc0_register(19, 0)
-#define read_gc0_watchhi1()            __read_32bit_gc0_register(19, 1)
-#define read_gc0_watchhi2()            __read_32bit_gc0_register(19, 2)
-#define read_gc0_watchhi3()            __read_32bit_gc0_register(19, 3)
-#define read_gc0_watchhi4()            __read_32bit_gc0_register(19, 4)
-#define read_gc0_watchhi5()            __read_32bit_gc0_register(19, 5)
-#define read_gc0_watchhi6()            __read_32bit_gc0_register(19, 6)
-#define read_gc0_watchhi7()            __read_32bit_gc0_register(19, 7)
-#define write_gc0_watchhi0(val)                __write_32bit_gc0_register(19, 0, val)
-#define write_gc0_watchhi1(val)                __write_32bit_gc0_register(19, 1, val)
-#define write_gc0_watchhi2(val)                __write_32bit_gc0_register(19, 2, val)
-#define write_gc0_watchhi3(val)                __write_32bit_gc0_register(19, 3, val)
-#define write_gc0_watchhi4(val)                __write_32bit_gc0_register(19, 4, val)
-#define write_gc0_watchhi5(val)                __write_32bit_gc0_register(19, 5, val)
-#define write_gc0_watchhi6(val)                __write_32bit_gc0_register(19, 6, val)
-#define write_gc0_watchhi7(val)                __write_32bit_gc0_register(19, 7, val)
-
-#define read_gc0_xcontext()            __read_ulong_gc0_register(20, 0)
-#define write_gc0_xcontext(val)                __write_ulong_gc0_register(20, 0, val)
-
-#define read_gc0_perfctrl0()           __read_32bit_gc0_register(25, 0)
-#define write_gc0_perfctrl0(val)       __write_32bit_gc0_register(25, 0, val)
-#define read_gc0_perfcntr0()           __read_32bit_gc0_register(25, 1)
-#define write_gc0_perfcntr0(val)       __write_32bit_gc0_register(25, 1, val)
-#define read_gc0_perfcntr0_64()                __read_64bit_gc0_register(25, 1)
-#define write_gc0_perfcntr0_64(val)    __write_64bit_gc0_register(25, 1, val)
-#define read_gc0_perfctrl1()           __read_32bit_gc0_register(25, 2)
-#define write_gc0_perfctrl1(val)       __write_32bit_gc0_register(25, 2, val)
-#define read_gc0_perfcntr1()           __read_32bit_gc0_register(25, 3)
-#define write_gc0_perfcntr1(val)       __write_32bit_gc0_register(25, 3, val)
-#define read_gc0_perfcntr1_64()                __read_64bit_gc0_register(25, 3)
-#define write_gc0_perfcntr1_64(val)    __write_64bit_gc0_register(25, 3, val)
-#define read_gc0_perfctrl2()           __read_32bit_gc0_register(25, 4)
-#define write_gc0_perfctrl2(val)       __write_32bit_gc0_register(25, 4, val)
-#define read_gc0_perfcntr2()           __read_32bit_gc0_register(25, 5)
-#define write_gc0_perfcntr2(val)       __write_32bit_gc0_register(25, 5, val)
-#define read_gc0_perfcntr2_64()                __read_64bit_gc0_register(25, 5)
-#define write_gc0_perfcntr2_64(val)    __write_64bit_gc0_register(25, 5, val)
-#define read_gc0_perfctrl3()           __read_32bit_gc0_register(25, 6)
-#define write_gc0_perfctrl3(val)       __write_32bit_gc0_register(25, 6, val)
-#define read_gc0_perfcntr3()           __read_32bit_gc0_register(25, 7)
-#define write_gc0_perfcntr3(val)       __write_32bit_gc0_register(25, 7, val)
-#define read_gc0_perfcntr3_64()                __read_64bit_gc0_register(25, 7)
-#define write_gc0_perfcntr3_64(val)    __write_64bit_gc0_register(25, 7, val)
-
-#define read_gc0_errorepc()            __read_ulong_gc0_register(30, 0)
-#define write_gc0_errorepc(val)                __write_ulong_gc0_register(30, 0, val)
-
-#define read_gc0_kscratch1()           __read_ulong_gc0_register(31, 2)
-#define read_gc0_kscratch2()           __read_ulong_gc0_register(31, 3)
-#define read_gc0_kscratch3()           __read_ulong_gc0_register(31, 4)
-#define read_gc0_kscratch4()           __read_ulong_gc0_register(31, 5)
-#define read_gc0_kscratch5()           __read_ulong_gc0_register(31, 6)
-#define read_gc0_kscratch6()           __read_ulong_gc0_register(31, 7)
-#define write_gc0_kscratch1(val)       __write_ulong_gc0_register(31, 2, val)
-#define write_gc0_kscratch2(val)       __write_ulong_gc0_register(31, 3, val)
-#define write_gc0_kscratch3(val)       __write_ulong_gc0_register(31, 4, val)
-#define write_gc0_kscratch4(val)       __write_ulong_gc0_register(31, 5, val)
-#define write_gc0_kscratch5(val)       __write_ulong_gc0_register(31, 6, val)
-#define write_gc0_kscratch6(val)       __write_ulong_gc0_register(31, 7, val)
+#define read_gc0_pwctl()               __read_32bit_gc0_register($6, 6)
+#define write_gc0_pwctl(val)           __write_32bit_gc0_register($6, 6, val)
+
+#define read_gc0_hwrena()              __read_32bit_gc0_register($7, 0)
+#define write_gc0_hwrena(val)          __write_32bit_gc0_register($7, 0, val)
+
+#define read_gc0_badvaddr()            __read_ulong_gc0_register($8, 0)
+#define write_gc0_badvaddr(val)                __write_ulong_gc0_register($8, 0, val)
+
+#define read_gc0_badinstr()            __read_32bit_gc0_register($8, 1)
+#define write_gc0_badinstr(val)                __write_32bit_gc0_register($8, 1, val)
+
+#define read_gc0_badinstrp()           __read_32bit_gc0_register($8, 2)
+#define write_gc0_badinstrp(val)       __write_32bit_gc0_register($8, 2, val)
+
+#define read_gc0_count()               __read_32bit_gc0_register($9, 0)
+
+#define read_gc0_entryhi()             __read_ulong_gc0_register($10, 0)
+#define write_gc0_entryhi(val)         __write_ulong_gc0_register($10, 0, val)
+
+#define read_gc0_compare()             __read_32bit_gc0_register($11, 0)
+#define write_gc0_compare(val)         __write_32bit_gc0_register($11, 0, val)
+
+#define read_gc0_status()              __read_32bit_gc0_register($12, 0)
+#define write_gc0_status(val)          __write_32bit_gc0_register($12, 0, val)
+
+#define read_gc0_intctl()              __read_32bit_gc0_register($12, 1)
+#define write_gc0_intctl(val)          __write_32bit_gc0_register($12, 1, val)
+
+#define read_gc0_cause()               __read_32bit_gc0_register($13, 0)
+#define write_gc0_cause(val)           __write_32bit_gc0_register($13, 0, val)
+
+#define read_gc0_epc()                 __read_ulong_gc0_register($14, 0)
+#define write_gc0_epc(val)             __write_ulong_gc0_register($14, 0, val)
+
+#define read_gc0_prid()                        __read_32bit_gc0_register($15, 0)
+
+#define read_gc0_ebase()               __read_32bit_gc0_register($15, 1)
+#define write_gc0_ebase(val)           __write_32bit_gc0_register($15, 1, val)
+
+#define read_gc0_ebase_64()            __read_64bit_gc0_register($15, 1)
+#define write_gc0_ebase_64(val)                __write_64bit_gc0_register($15, 1, val)
+
+#define read_gc0_config()              __read_32bit_gc0_register($16, 0)
+#define read_gc0_config1()             __read_32bit_gc0_register($16, 1)
+#define read_gc0_config2()             __read_32bit_gc0_register($16, 2)
+#define read_gc0_config3()             __read_32bit_gc0_register($16, 3)
+#define read_gc0_config4()             __read_32bit_gc0_register($16, 4)
+#define read_gc0_config5()             __read_32bit_gc0_register($16, 5)
+#define read_gc0_config6()             __read_32bit_gc0_register($16, 6)
+#define read_gc0_config7()             __read_32bit_gc0_register($16, 7)
+#define write_gc0_config(val)          __write_32bit_gc0_register($16, 0, val)
+#define write_gc0_config1(val)         __write_32bit_gc0_register($16, 1, val)
+#define write_gc0_config2(val)         __write_32bit_gc0_register($16, 2, val)
+#define write_gc0_config3(val)         __write_32bit_gc0_register($16, 3, val)
+#define write_gc0_config4(val)         __write_32bit_gc0_register($16, 4, val)
+#define write_gc0_config5(val)         __write_32bit_gc0_register($16, 5, val)
+#define write_gc0_config6(val)         __write_32bit_gc0_register($16, 6, val)
+#define write_gc0_config7(val)         __write_32bit_gc0_register($16, 7, val)
+
+#define read_gc0_lladdr()              __read_ulong_gc0_register($17, 0)
+#define write_gc0_lladdr(val)          __write_ulong_gc0_register($17, 0, val)
+
+#define read_gc0_watchlo0()            __read_ulong_gc0_register($18, 0)
+#define read_gc0_watchlo1()            __read_ulong_gc0_register($18, 1)
+#define read_gc0_watchlo2()            __read_ulong_gc0_register($18, 2)
+#define read_gc0_watchlo3()            __read_ulong_gc0_register($18, 3)
+#define read_gc0_watchlo4()            __read_ulong_gc0_register($18, 4)
+#define read_gc0_watchlo5()            __read_ulong_gc0_register($18, 5)
+#define read_gc0_watchlo6()            __read_ulong_gc0_register($18, 6)
+#define read_gc0_watchlo7()            __read_ulong_gc0_register($18, 7)
+#define write_gc0_watchlo0(val)                __write_ulong_gc0_register($18, 0, val)
+#define write_gc0_watchlo1(val)                __write_ulong_gc0_register($18, 1, val)
+#define write_gc0_watchlo2(val)                __write_ulong_gc0_register($18, 2, val)
+#define write_gc0_watchlo3(val)                __write_ulong_gc0_register($18, 3, val)
+#define write_gc0_watchlo4(val)                __write_ulong_gc0_register($18, 4, val)
+#define write_gc0_watchlo5(val)                __write_ulong_gc0_register($18, 5, val)
+#define write_gc0_watchlo6(val)                __write_ulong_gc0_register($18, 6, val)
+#define write_gc0_watchlo7(val)                __write_ulong_gc0_register($18, 7, val)
+
+#define read_gc0_watchhi0()            __read_32bit_gc0_register($19, 0)
+#define read_gc0_watchhi1()            __read_32bit_gc0_register($19, 1)
+#define read_gc0_watchhi2()            __read_32bit_gc0_register($19, 2)
+#define read_gc0_watchhi3()            __read_32bit_gc0_register($19, 3)
+#define read_gc0_watchhi4()            __read_32bit_gc0_register($19, 4)
+#define read_gc0_watchhi5()            __read_32bit_gc0_register($19, 5)
+#define read_gc0_watchhi6()            __read_32bit_gc0_register($19, 6)
+#define read_gc0_watchhi7()            __read_32bit_gc0_register($19, 7)
+#define write_gc0_watchhi0(val)                __write_32bit_gc0_register($19, 0, val)
+#define write_gc0_watchhi1(val)                __write_32bit_gc0_register($19, 1, val)
+#define write_gc0_watchhi2(val)                __write_32bit_gc0_register($19, 2, val)
+#define write_gc0_watchhi3(val)                __write_32bit_gc0_register($19, 3, val)
+#define write_gc0_watchhi4(val)                __write_32bit_gc0_register($19, 4, val)
+#define write_gc0_watchhi5(val)                __write_32bit_gc0_register($19, 5, val)
+#define write_gc0_watchhi6(val)                __write_32bit_gc0_register($19, 6, val)
+#define write_gc0_watchhi7(val)                __write_32bit_gc0_register($19, 7, val)
+
+#define read_gc0_xcontext()            __read_ulong_gc0_register($20, 0)
+#define write_gc0_xcontext(val)                __write_ulong_gc0_register($20, 0, val)
+
+#define read_gc0_perfctrl0()           __read_32bit_gc0_register($25, 0)
+#define write_gc0_perfctrl0(val)       __write_32bit_gc0_register($25, 0, val)
+#define read_gc0_perfcntr0()           __read_32bit_gc0_register($25, 1)
+#define write_gc0_perfcntr0(val)       __write_32bit_gc0_register($25, 1, val)
+#define read_gc0_perfcntr0_64()                __read_64bit_gc0_register($25, 1)
+#define write_gc0_perfcntr0_64(val)    __write_64bit_gc0_register($25, 1, val)
+#define read_gc0_perfctrl1()           __read_32bit_gc0_register($25, 2)
+#define write_gc0_perfctrl1(val)       __write_32bit_gc0_register($25, 2, val)
+#define read_gc0_perfcntr1()           __read_32bit_gc0_register($25, 3)
+#define write_gc0_perfcntr1(val)       __write_32bit_gc0_register($25, 3, val)
+#define read_gc0_perfcntr1_64()                __read_64bit_gc0_register($25, 3)
+#define write_gc0_perfcntr1_64(val)    __write_64bit_gc0_register($25, 3, val)
+#define read_gc0_perfctrl2()           __read_32bit_gc0_register($25, 4)
+#define write_gc0_perfctrl2(val)       __write_32bit_gc0_register($25, 4, val)
+#define read_gc0_perfcntr2()           __read_32bit_gc0_register($25, 5)
+#define write_gc0_perfcntr2(val)       __write_32bit_gc0_register($25, 5, val)
+#define read_gc0_perfcntr2_64()                __read_64bit_gc0_register($25, 5)
+#define write_gc0_perfcntr2_64(val)    __write_64bit_gc0_register($25, 5, val)
+#define read_gc0_perfctrl3()           __read_32bit_gc0_register($25, 6)
+#define write_gc0_perfctrl3(val)       __write_32bit_gc0_register($25, 6, val)
+#define read_gc0_perfcntr3()           __read_32bit_gc0_register($25, 7)
+#define write_gc0_perfcntr3(val)       __write_32bit_gc0_register($25, 7, val)
+#define read_gc0_perfcntr3_64()                __read_64bit_gc0_register($25, 7)
+#define write_gc0_perfcntr3_64(val)    __write_64bit_gc0_register($25, 7, val)
+
+#define read_gc0_errorepc()            __read_ulong_gc0_register($30, 0)
+#define write_gc0_errorepc(val)                __write_ulong_gc0_register($30, 0, val)
+
+#define read_gc0_kscratch1()           __read_ulong_gc0_register($31, 2)
+#define read_gc0_kscratch2()           __read_ulong_gc0_register($31, 3)
+#define read_gc0_kscratch3()           __read_ulong_gc0_register($31, 4)
+#define read_gc0_kscratch4()           __read_ulong_gc0_register($31, 5)
+#define read_gc0_kscratch5()           __read_ulong_gc0_register($31, 6)
+#define read_gc0_kscratch6()           __read_ulong_gc0_register($31, 7)
+#define write_gc0_kscratch1(val)       __write_ulong_gc0_register($31, 2, val)
+#define write_gc0_kscratch2(val)       __write_ulong_gc0_register($31, 3, val)
+#define write_gc0_kscratch3(val)       __write_ulong_gc0_register($31, 4, val)
+#define write_gc0_kscratch4(val)       __write_ulong_gc0_register($31, 5, val)
+#define write_gc0_kscratch5(val)       __write_ulong_gc0_register($31, 6, val)
+#define write_gc0_kscratch6(val)       __write_ulong_gc0_register($31, 7, val)
 
 /* Cavium OCTEON (cnMIPS) */
-#define read_gc0_cvmcount()            __read_ulong_gc0_register(9, 6)
-#define write_gc0_cvmcount(val)                __write_ulong_gc0_register(9, 6, val)
+#define read_gc0_cvmcount()            __read_ulong_gc0_register($9, 6)
+#define write_gc0_cvmcount(val)                __write_ulong_gc0_register($9, 6, val)
 
-#define read_gc0_cvmctl()              __read_64bit_gc0_register(9, 7)
-#define write_gc0_cvmctl(val)          __write_64bit_gc0_register(9, 7, val)
+#define read_gc0_cvmctl()              __read_64bit_gc0_register($9, 7)
+#define write_gc0_cvmctl(val)          __write_64bit_gc0_register($9, 7, val)
 
-#define read_gc0_cvmmemctl()           __read_64bit_gc0_register(11, 7)
-#define write_gc0_cvmmemctl(val)       __write_64bit_gc0_register(11, 7, val)
+#define read_gc0_cvmmemctl()           __read_64bit_gc0_register($11, 7)
+#define write_gc0_cvmmemctl(val)       __write_64bit_gc0_register($11, 7, val)
 
-#define read_gc0_cvmmemctl2()          __read_64bit_gc0_register(16, 6)
-#define write_gc0_cvmmemctl2(val)      __write_64bit_gc0_register(16, 6, val)
+#define read_gc0_cvmmemctl2()          __read_64bit_gc0_register($16, 6)
+#define write_gc0_cvmmemctl2(val)      __write_64bit_gc0_register($16, 6, val)
 
 /*
  * Macros to access the floating point coprocessor control registers
@@ -2581,8 +2651,6 @@ static inline void tlb_write_random(void)
                ".set reorder");
 }
 
-#ifdef TOOLCHAIN_SUPPORTS_VIRT
-
 /*
  * Guest TLB operations.
  *
@@ -2593,7 +2661,7 @@ static inline void guest_tlb_probe(void)
        __asm__ __volatile__(
                ".set push\n\t"
                ".set noreorder\n\t"
-               ".set virt\n\t"
+               _ASM_SET_VIRT
                "tlbgp\n\t"
                ".set pop");
 }
@@ -2603,7 +2671,7 @@ static inline void guest_tlb_read(void)
        __asm__ __volatile__(
                ".set push\n\t"
                ".set noreorder\n\t"
-               ".set virt\n\t"
+               _ASM_SET_VIRT
                "tlbgr\n\t"
                ".set pop");
 }
@@ -2613,7 +2681,7 @@ static inline void guest_tlb_write_indexed(void)
        __asm__ __volatile__(
                ".set push\n\t"
                ".set noreorder\n\t"
-               ".set virt\n\t"
+               _ASM_SET_VIRT
                "tlbgwi\n\t"
                ".set pop");
 }
@@ -2623,7 +2691,7 @@ static inline void guest_tlb_write_random(void)
        __asm__ __volatile__(
                ".set push\n\t"
                ".set noreorder\n\t"
-               ".set virt\n\t"
+               _ASM_SET_VIRT
                "tlbgwr\n\t"
                ".set pop");
 }
@@ -2636,63 +2704,11 @@ static inline void guest_tlbinvf(void)
        __asm__ __volatile__(
                ".set push\n\t"
                ".set noreorder\n\t"
-               ".set virt\n\t"
+               _ASM_SET_VIRT
                "tlbginvf\n\t"
                ".set pop");
 }
 
-#else  /* TOOLCHAIN_SUPPORTS_VIRT */
-
-/*
- * Guest TLB operations.
- *
- * It is responsibility of the caller to take care of any TLB hazards.
- */
-static inline void guest_tlb_probe(void)
-{
-       __asm__ __volatile__(
-               "# tlbgp\n\t"
-               _ASM_INSN_IF_MIPS(0x42000010)
-               _ASM_INSN32_IF_MM(0x0000017c));
-}
-
-static inline void guest_tlb_read(void)
-{
-       __asm__ __volatile__(
-               "# tlbgr\n\t"
-               _ASM_INSN_IF_MIPS(0x42000009)
-               _ASM_INSN32_IF_MM(0x0000117c));
-}
-
-static inline void guest_tlb_write_indexed(void)
-{
-       __asm__ __volatile__(
-               "# tlbgwi\n\t"
-               _ASM_INSN_IF_MIPS(0x4200000a)
-               _ASM_INSN32_IF_MM(0x0000217c));
-}
-
-static inline void guest_tlb_write_random(void)
-{
-       __asm__ __volatile__(
-               "# tlbgwr\n\t"
-               _ASM_INSN_IF_MIPS(0x4200000e)
-               _ASM_INSN32_IF_MM(0x0000317c));
-}
-
-/*
- * Guest TLB Invalidate Flush
- */
-static inline void guest_tlbinvf(void)
-{
-       __asm__ __volatile__(
-               "# tlbginvf\n\t"
-               _ASM_INSN_IF_MIPS(0x4200000c)
-               _ASM_INSN32_IF_MM(0x0000517c));
-}
-
-#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
-
 /*
  * Manipulate bits in a register.
  */
index b1845102f8f9d28f7ae424f9b10904a7eef9b13f..b4f9577ed96a66656d5a940a8e7656811573c2c5 100644 (file)
@@ -160,7 +160,23 @@ static inline void init_msa_upper(void)
        _init_msa_upper();
 }
 
-#ifdef TOOLCHAIN_SUPPORTS_MSA
+#ifndef TOOLCHAIN_SUPPORTS_MSA
+/*
+ * Define assembler macros using .word for the c[ft]cmsa instructions in order
+ * to allow compilation with toolchains that do not support MSA. Once all
+ * toolchains in use support MSA these can be removed.
+ */
+_ASM_MACRO_2R(cfcmsa, rd, cs,
+       _ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6)
+       _ASM_INSN32_IF_MM(0x587e0016 | __cs << 11 | __rd << 6));
+_ASM_MACRO_2R(ctcmsa, cd, rs,
+       _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)
+       _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6));
+#define _ASM_SET_MSA ""
+#else /* TOOLCHAIN_SUPPORTS_MSA */
+#define _ASM_SET_MSA ".set\tfp=64\n\t"                         \
+                    ".set\tmsa\n\t"
+#endif
 
 #define __BUILD_MSA_CTL_REG(name, cs)                          \
 static inline unsigned int read_msa_##name(void)               \
@@ -168,8 +184,7 @@ static inline unsigned int read_msa_##name(void)            \
        unsigned int reg;                                       \
        __asm__ __volatile__(                                   \
        "       .set    push\n"                                 \
-       "       .set    fp=64\n"                                \
-       "       .set    msa\n"                                  \
+       _ASM_SET_MSA                                            \
        "       cfcmsa  %0, $" #cs "\n"                         \
        "       .set    pop\n"                                  \
        : "=r"(reg));                                           \
@@ -180,52 +195,12 @@ static inline void write_msa_##name(unsigned int val)             \
 {                                                              \
        __asm__ __volatile__(                                   \
        "       .set    push\n"                                 \
-       "       .set    fp=64\n"                                \
-       "       .set    msa\n"                                  \
+       _ASM_SET_MSA                                            \
        "       ctcmsa  $" #cs ", %0\n"                         \
        "       .set    pop\n"                                  \
        : : "r"(val));                                          \
 }
 
-#else /* !TOOLCHAIN_SUPPORTS_MSA */
-
-/*
- * Define functions using .word for the c[ft]cmsa instructions in order to
- * allow compilation with toolchains that do not support MSA. Once all
- * toolchains in use support MSA these can be removed.
- */
-
-#define __BUILD_MSA_CTL_REG(name, cs)                          \
-static inline unsigned int read_msa_##name(void)               \
-{                                                              \
-       unsigned int reg;                                       \
-       __asm__ __volatile__(                                   \
-       "       .set    push\n"                                 \
-       "       .set    noat\n"                                 \
-       "       # cfcmsa $1, $%1\n"                             \
-       _ASM_INSN_IF_MIPS(0x787e0059 | %1 << 11)                \
-       _ASM_INSN32_IF_MM(0x587e0056 | %1 << 11)                \
-       "       move    %0, $1\n"                               \
-       "       .set    pop\n"                                  \
-       : "=r"(reg) : "i"(cs));                                 \
-       return reg;                                             \
-}                                                              \
-                                                               \
-static inline void write_msa_##name(unsigned int val)          \
-{                                                              \
-       __asm__ __volatile__(                                   \
-       "       .set    push\n"                                 \
-       "       .set    noat\n"                                 \
-       "       move    $1, %0\n"                               \
-       "       # ctcmsa $%1, $1\n"                             \
-       _ASM_INSN_IF_MIPS(0x783e0819 | %1 << 6)                 \
-       _ASM_INSN32_IF_MM(0x583e0816 | %1 << 6)                 \
-       "       .set    pop\n"                                  \
-       : : "r"(val), "i"(cs));                                 \
-}
-
-#endif /* !TOOLCHAIN_SUPPORTS_MSA */
-
 __BUILD_MSA_CTL_REG(ir, 0)
 __BUILD_MSA_CTL_REG(csr, 1)
 __BUILD_MSA_CTL_REG(access, 2)
index 643af2012e143cf30e6f3d9bec4fc42c3f0780fb..4dd0c446ecec71d37678e273ea2bc9618f680a80 100644 (file)
@@ -8,6 +8,10 @@ config JZ4740_QI_LB60
        bool "Qi Hardware Ben NanoNote"
        select MACH_JZ4740
 
+config JZ4770_GCW0
+       bool "Game Consoles Worldwide GCW Zero"
+       select MACH_JZ4770
+
 config JZ4780_CI20
        bool "MIPS Creator CI20"
        select MACH_JZ4780
@@ -18,6 +22,12 @@ config MACH_JZ4740
        bool
        select SYS_HAS_CPU_MIPS32_R1
 
+config MACH_JZ4770
+       bool
+       select MIPS_CPU_SCACHE
+       select SYS_HAS_CPU_MIPS32_R2
+       select SYS_SUPPORTS_HIGHMEM
+
 config MACH_JZ4780
        bool
        select MIPS_CPU_SCACHE
index 47e857194ce66aaa5e1b8428c14871d630745fac..eb9f2f97bedb66132037ea9231261671c3ac865f 100644 (file)
 #include <linux/serial_reg.h>
 
 #include <asm/bootinfo.h>
+#include <asm/fw/fw.h>
 #include <asm/mach-jz4740/base.h>
 
-static __init void jz4740_init_cmdline(int argc, char *argv[])
-{
-       unsigned int count = COMMAND_LINE_SIZE - 1;
-       int i;
-       char *dst = &(arcs_cmdline[0]);
-       char *src;
-
-       for (i = 1; i < argc && count; ++i) {
-               src = argv[i];
-               while (*src && count) {
-                       *dst++ = *src++;
-                       --count;
-               }
-               *dst++ = ' ';
-       }
-       if (i > 1)
-               --dst;
-
-       *dst = 0;
-}
-
 void __init prom_init(void)
 {
-       jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
-       mips_machtype = MACH_INGENIC_JZ4740;
+       fw_init_cmdline();
 }
 
 void __init prom_free_prom_memory(void)
index 6d0152321819b823200b8082bed7e757078f47fd..afb40f8bce961200cdf1d1eaa694129acaec9a7d 100644 (file)
@@ -53,6 +53,16 @@ static void __init jz4740_detect_mem(void)
        add_memory_region(0, size, BOOT_MEM_RAM);
 }
 
+static unsigned long __init get_board_mach_type(const void *fdt)
+{
+       if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4780"))
+               return MACH_INGENIC_JZ4780;
+       if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770"))
+               return MACH_INGENIC_JZ4770;
+
+       return MACH_INGENIC_JZ4740;
+}
+
 void __init plat_mem_setup(void)
 {
        int offset;
@@ -63,6 +73,8 @@ void __init plat_mem_setup(void)
        offset = fdt_path_offset(__dtb_start, "/memory");
        if (offset < 0)
                jz4740_detect_mem();
+
+       mips_machtype = get_board_mach_type(__dtb_start);
 }
 
 void __init device_tree_init(void)
@@ -75,10 +87,14 @@ void __init device_tree_init(void)
 
 const char *get_system_type(void)
 {
-       if (IS_ENABLED(CONFIG_MACH_JZ4780))
+       switch (mips_machtype) {
+       case MACH_INGENIC_JZ4780:
                return "JZ4780";
-
-       return "JZ4740";
+       case MACH_INGENIC_JZ4770:
+               return "JZ4770";
+       default:
+               return "JZ4740";
+       }
 }
 
 void __init arch_init_irq(void)
index bb1ad5119da4e90f35b1bdfba16fdcbf118bb61c..2ca9160f642a23ba8b62d1149b8ef0dab5964514 100644 (file)
@@ -113,7 +113,7 @@ static struct clock_event_device jz4740_clockevent = {
 #ifdef CONFIG_MACH_JZ4740
        .irq = JZ4740_IRQ_TCU0,
 #endif
-#ifdef CONFIG_MACH_JZ4780
+#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
        .irq = JZ4780_IRQ_TCU2,
 #endif
 };
index b79ed9af98860f09e7b9691bd1ccd9b0ec95546b..e48f6c0a9e4a39522f5925cb9716065232cc2de0 100644 (file)
@@ -399,7 +399,7 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs)
  *
  * @regs:      Pointer to pt_regs
  * @insn:      branch instruction to decode
- * @returns:   -EFAULT on error and forces SIGILL, and on success
+ * Return:     -EFAULT on error and forces SIGILL, and on success
  *             returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
  *             evaluating the branch.
  *
index e68e6e04063a7e0d9f30c50ebac3b082ac7b8b88..1025f937ab0e5a312d963f07b96d563519221931 100644 (file)
@@ -388,15 +388,16 @@ LEAF(mips_cps_boot_vpes)
 
 #elif defined(CONFIG_MIPS_MT)
 
-       .set    push
-       .set    MIPS_ISA_LEVEL_RAW
-       .set    mt
-
        /* If the core doesn't support MT then return */
        has_mt  t0, 5f
 
        /* Enter VPE configuration state */
+       .set    push
+       .set    MIPS_ISA_LEVEL_RAW
+       .set    mt
        dvpe
+       .set    pop
+
        PTR_LA  t1, 1f
        jr.hb   t1
         nop
@@ -422,6 +423,10 @@ LEAF(mips_cps_boot_vpes)
        mtc0    t0, CP0_VPECONTROL
        ehb
 
+       .set    push
+       .set    MIPS_ISA_LEVEL_RAW
+       .set    mt
+
        /* Skip the VPE if its TC is not halted */
        mftc0   t0, CP0_TCHALT
        beqz    t0, 2f
@@ -495,6 +500,8 @@ LEAF(mips_cps_boot_vpes)
        ehb
        evpe
 
+       .set    pop
+
        /* Check whether this VPE is meant to be running */
        li      t0, 1
        sll     t0, t0, a1
@@ -509,7 +516,7 @@ LEAF(mips_cps_boot_vpes)
 1:     jr.hb   t0
         nop
 
-2:     .set    pop
+2:
 
 #endif /* CONFIG_MIPS_MT_SMP */
 
index 99285be0e0884c9f6d5d6b9506b7b2b221b4b918..7f3dfdbc3657e6705b6a797c6e1dfa565fa3bff9 100644 (file)
@@ -361,7 +361,7 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra,
         * If fails when getting the stack address of the non-leaf function's
         * ra, stop function graph tracer and return
         */
-       if (parent_ra_addr == 0)
+       if (parent_ra_addr == NULL)
                goto out;
 #endif
        /* *parent_ra_addr = return_hooker; */
index 702c678de1166bd7cbef012cb2c00d556f85666c..85bc601e9a0d43ffd89669eac4b359de99566083 100644 (file)
@@ -826,25 +826,6 @@ static void __init arch_mem_init(char **cmdline_p)
        struct memblock_region *reg;
        extern void plat_mem_setup(void);
 
-       /* call board setup routine */
-       plat_mem_setup();
-
-       /*
-        * Make sure all kernel memory is in the maps.  The "UP" and
-        * "DOWN" are opposite for initdata since if it crosses over
-        * into another memory section you don't want that to be
-        * freed when the initdata is freed.
-        */
-       arch_mem_addpart(PFN_DOWN(__pa_symbol(&_text)) << PAGE_SHIFT,
-                        PFN_UP(__pa_symbol(&_edata)) << PAGE_SHIFT,
-                        BOOT_MEM_RAM);
-       arch_mem_addpart(PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT,
-                        PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT,
-                        BOOT_MEM_INIT_RAM);
-
-       pr_info("Determined physical RAM map:\n");
-       print_memory_map();
-
 #if defined(CONFIG_CMDLINE_BOOL) && defined(CONFIG_CMDLINE_OVERRIDE)
        strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
 #else
@@ -872,6 +853,26 @@ static void __init arch_mem_init(char **cmdline_p)
        }
 #endif
 #endif
+
+       /* call board setup routine */
+       plat_mem_setup();
+
+       /*
+        * Make sure all kernel memory is in the maps.  The "UP" and
+        * "DOWN" are opposite for initda