ASoC: max98927: Modified chip default register values
authorRyan Lee <ryans.lee@maximintegrated.com>
Mon, 28 Aug 2017 23:30:58 +0000 (16:30 -0700)
committerMark Brown <broonie@kernel.org>
Thu, 31 Aug 2017 11:45:07 +0000 (12:45 +0100)
Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/max98927.c

index f74cdb065bf2808f1e04385537db161a5e737385..5b853604120a1cce14e3d69f0f3ce5da33e80dd1 100644 (file)
@@ -44,9 +44,9 @@ static struct reg_default max98927_reg[] = {
        {MAX98927_R0011_CLK_MON,  0x00},
        {MAX98927_R0012_WDOG_CTRL,  0x00},
        {MAX98927_R0013_WDOG_RST,  0x00},
        {MAX98927_R0011_CLK_MON,  0x00},
        {MAX98927_R0012_WDOG_CTRL,  0x00},
        {MAX98927_R0013_WDOG_RST,  0x00},
-       {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH,  0x00},
-       {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH,  0x00},
-       {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS,  0x00},
+       {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH,  0x75},
+       {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH,  0x8c},
+       {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS,  0x08},
        {MAX98927_R0017_PIN_CFG,  0x55},
        {MAX98927_R0018_PCM_RX_EN_A,  0x00},
        {MAX98927_R0019_PCM_RX_EN_B,  0x00},
        {MAX98927_R0017_PIN_CFG,  0x55},
        {MAX98927_R0018_PCM_RX_EN_A,  0x00},
        {MAX98927_R0019_PCM_RX_EN_B,  0x00},
@@ -82,14 +82,14 @@ static struct reg_default max98927_reg[] = {
        {MAX98927_R003A_AMP_EN,  0x00},
        {MAX98927_R003B_SPK_SRC_SEL,  0x00},
        {MAX98927_R003C_SPK_GAIN,  0x00},
        {MAX98927_R003A_AMP_EN,  0x00},
        {MAX98927_R003B_SPK_SRC_SEL,  0x00},
        {MAX98927_R003C_SPK_GAIN,  0x00},
-       {MAX98927_R003D_SSM_CFG,  0x01},
+       {MAX98927_R003D_SSM_CFG,  0x04},
        {MAX98927_R003E_MEAS_EN,  0x00},
        {MAX98927_R003F_MEAS_DSP_CFG,  0x04},
        {MAX98927_R0040_BOOST_CTRL0,  0x00},
        {MAX98927_R0041_BOOST_CTRL3,  0x00},
        {MAX98927_R0042_BOOST_CTRL1,  0x00},
        {MAX98927_R0043_MEAS_ADC_CFG,  0x00},
        {MAX98927_R003E_MEAS_EN,  0x00},
        {MAX98927_R003F_MEAS_DSP_CFG,  0x04},
        {MAX98927_R0040_BOOST_CTRL0,  0x00},
        {MAX98927_R0041_BOOST_CTRL3,  0x00},
        {MAX98927_R0042_BOOST_CTRL1,  0x00},
        {MAX98927_R0043_MEAS_ADC_CFG,  0x00},
-       {MAX98927_R0044_MEAS_ADC_BASE_MSB,  0x00},
+       {MAX98927_R0044_MEAS_ADC_BASE_MSB,  0x01},
        {MAX98927_R0045_MEAS_ADC_BASE_LSB,  0x00},
        {MAX98927_R0046_ADC_CH0_DIVIDE,  0x00},
        {MAX98927_R0047_ADC_CH1_DIVIDE,  0x00},
        {MAX98927_R0045_MEAS_ADC_BASE_LSB,  0x00},
        {MAX98927_R0046_ADC_CH0_DIVIDE,  0x00},
        {MAX98927_R0047_ADC_CH1_DIVIDE,  0x00},