Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
authorSaeed Mahameed <saeedm@mellanox.com>
Mon, 23 Jul 2018 21:58:46 +0000 (14:58 -0700)
committerSaeed Mahameed <saeedm@mellanox.com>
Mon, 23 Jul 2018 21:58:46 +0000 (14:58 -0700)
mlx5 core infrastructure updates and fixes.

From Eran:
 - Add MPEGC (Management PCIe General Configuration) registers and btis
 - Fix tristate and description for MLX5 module

rom Feras:
 - Add hardware structures for the firmware tracer

From Jainbo:
 - Core support for double vlan push/pop steering action

From Max:
 - Add XRQ commands definitions

From Noa:
 - Add missing SET_DRIVER_VERSION command translation

From Roi:
 - Use ERR_CAST() instead of coding it

From Tariq:
 - Better return types for CQE API

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
17 files changed:
drivers/infiniband/hw/mlx5/Kconfig
drivers/infiniband/hw/mlx5/cmd.c
drivers/infiniband/hw/mlx5/cmd.h
drivers/net/ethernet/mellanox/mlx5/core/Kconfig
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
drivers/net/ethernet/mellanox/mlx5/core/debugfs.c
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
drivers/net/ethernet/mellanox/mlx5/core/main.c
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
drivers/net/ethernet/mellanox/mlx5/core/mr.c
include/linux/mlx5/device.h
include/linux/mlx5/driver.h
include/linux/mlx5/fs.h
include/linux/mlx5/mlx5_ifc.h

index fb4d77be019b77797b5bf281dfdd63a447fd065f..0440966bc6ec31df4163d64f8530bcff1b8e0b2c 100644 (file)
@@ -1,5 +1,5 @@
 config MLX5_INFINIBAND
-       tristate "Mellanox Connect-IB HCA support"
+       tristate "Mellanox 5th generation network adapters (ConnectX series) support"
        depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE
        depends on INFINIBAND_USER_ACCESS || INFINIBAND_USER_ACCESS=n
        ---help---
index 188512bf46e63210e478a0527bc225c075dcf28a..ccc0b5d06a7df7bd4917ac17b95faab051621959 100644 (file)
 
 #include "cmd.h"
 
+int mlx5_cmd_dump_fill_mkey(struct mlx5_core_dev *dev, u32 *mkey)
+{
+       u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0};
+       u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]   = {0};
+       int err;
+
+       MLX5_SET(query_special_contexts_in, in, opcode,
+                MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
+       err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
+       if (!err)
+               *mkey = MLX5_GET(query_special_contexts_out, out,
+                                dump_fill_mkey);
+       return err;
+}
+
 int mlx5_cmd_null_mkey(struct mlx5_core_dev *dev, u32 *null_mkey)
 {
        u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {};
index e7206c8a8011b273581d290f9d751a84ec8a94e6..98ea4648c655a62f6240803893efcdcb7fe20ac5 100644 (file)
@@ -37,6 +37,7 @@
 #include <linux/kernel.h>
 #include <linux/mlx5/driver.h>
 
+int mlx5_cmd_dump_fill_mkey(struct mlx5_core_dev *dev, u32 *mkey);
 int mlx5_cmd_null_mkey(struct mlx5_core_dev *dev, u32 *null_mkey);
 int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point,
                               void *out, int out_size);
index 2545296a0c087888701048dfd36b957cb91c6993..7a84dd07ced2524178eeffb1b45dec7f1b98a604 100644 (file)
@@ -3,7 +3,7 @@
 #
 
 config MLX5_CORE
-       tristate "Mellanox Technologies ConnectX-4 and Connect-IB core driver"
+       tristate "Mellanox 5th generation network adapters (ConnectX series) core driver"
        depends on MAY_USE_DEVLINK
        depends on PCI
        imply PTP_1588_CLOCK
@@ -27,7 +27,7 @@ config MLX5_FPGA
           sandbox-specific client drivers.
 
 config MLX5_CORE_EN
-       bool "Mellanox Technologies ConnectX-4 Ethernet support"
+       bool "Mellanox 5th generation network adapters (ConnectX series) Ethernet support"
        depends on NETDEVICES && ETHERNET && INET && PCI && MLX5_CORE
        depends on IPV6=y || IPV6=n || MLX5_CORE=m
        select PAGE_POOL
@@ -69,7 +69,7 @@ config MLX5_CORE_EN_DCB
          If unsure, set to Y
 
 config MLX5_CORE_IPOIB
-       bool "Mellanox Technologies ConnectX-4 IPoIB offloads support"
+       bool "Mellanox 5th generation network adapters (connectX series) IPoIB offloads support"
        depends on MLX5_CORE_EN
        default n
        ---help---
index 384c1fa490811ee651919c139b9cd9e724d4ff81..f498c7730c5b105cb23f41611ec84f7992dba830 100644 (file)
@@ -278,6 +278,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
        case MLX5_CMD_OP_DESTROY_PSV:
        case MLX5_CMD_OP_DESTROY_SRQ:
        case MLX5_CMD_OP_DESTROY_XRC_SRQ:
+       case MLX5_CMD_OP_DESTROY_XRQ:
        case MLX5_CMD_OP_DESTROY_DCT:
        case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
        case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
@@ -310,6 +311,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
        case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
        case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
        case MLX5_CMD_OP_FPGA_DESTROY_QP:
+       case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
                return MLX5_CMD_STAT_OK;
 
        case MLX5_CMD_OP_QUERY_HCA_CAP:
@@ -346,6 +348,9 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
        case MLX5_CMD_OP_CREATE_XRC_SRQ:
        case MLX5_CMD_OP_QUERY_XRC_SRQ:
        case MLX5_CMD_OP_ARM_XRC_SRQ:
+       case MLX5_CMD_OP_CREATE_XRQ:
+       case MLX5_CMD_OP_QUERY_XRQ:
+       case MLX5_CMD_OP_ARM_XRQ:
        case MLX5_CMD_OP_CREATE_DCT:
        case MLX5_CMD_OP_DRAIN_DCT:
        case MLX5_CMD_OP_QUERY_DCT:
@@ -427,6 +432,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
        case MLX5_CMD_OP_FPGA_MODIFY_QP:
        case MLX5_CMD_OP_FPGA_QUERY_QP:
        case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
+       case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
                *status = MLX5_DRIVER_STATUS_ABORTED;
                *synd = MLX5_DRIVER_SYND;
                return -EIO;
@@ -452,6 +458,7 @@ const char *mlx5_command_str(int command)
        MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
        MLX5_COMMAND_STR_CASE(QUERY_ISSI);
        MLX5_COMMAND_STR_CASE(SET_ISSI);
+       MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
        MLX5_COMMAND_STR_CASE(CREATE_MKEY);
        MLX5_COMMAND_STR_CASE(QUERY_MKEY);
        MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
@@ -599,6 +606,12 @@ const char *mlx5_command_str(int command)
        MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
        MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
        MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
+       MLX5_COMMAND_STR_CASE(CREATE_XRQ);
+       MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
+       MLX5_COMMAND_STR_CASE(QUERY_XRQ);
+       MLX5_COMMAND_STR_CASE(ARM_XRQ);
+       MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
+       MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
        default: return "unknown command opcode";
        }
 }
@@ -677,7 +690,7 @@ struct mlx5_ifc_mbox_out_bits {
 
 struct mlx5_ifc_mbox_in_bits {
        u8         opcode[0x10];
-       u8         reserved_at_10[0x10];
+       u8         uid[0x10];
 
        u8         reserved_at_20[0x10];
        u8         op_mod[0x10];
@@ -697,6 +710,7 @@ static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
        u8  status;
        u16 opcode;
        u16 op_mod;
+       u16 uid;
 
        mlx5_cmd_mbox_status(out, &status, &syndrome);
        if (!status)
@@ -704,8 +718,15 @@ static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 
        opcode = MLX5_GET(mbox_in, in, opcode);
        op_mod = MLX5_GET(mbox_in, in, op_mod);
+       uid    = MLX5_GET(mbox_in, in, uid);
 
-       mlx5_core_err(dev,
+       if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
+               mlx5_core_err_rl(dev,
+                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
+                       mlx5_command_str(opcode), opcode, op_mod,
+                       cmd_status_str(status), status, syndrome);
+       else
+               mlx5_core_dbg(dev,
                      "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
                      mlx5_command_str(opcode),
                      opcode, op_mod,
@@ -1022,7 +1043,10 @@ static ssize_t dbg_write(struct file *filp, const char __user *buf,
        if (!dbg->in_msg || !dbg->out_msg)
                return -ENOMEM;
 
-       if (copy_from_user(lbuf, buf, sizeof(lbuf)))
+       if (count < sizeof(lbuf) - 1)
+               return -EINVAL;
+
+       if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
                return -EFAULT;
 
        lbuf[sizeof(lbuf) - 1] = 0;
@@ -1226,21 +1250,12 @@ static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
 {
        struct mlx5_core_dev *dev = filp->private_data;
        struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
-       int copy;
-
-       if (*pos)
-               return 0;
 
        if (!dbg->out_msg)
                return -ENOMEM;
 
-       copy = min_t(int, count, dbg->outlen);
-       if (copy_to_user(buf, dbg->out_msg, copy))
-               return -EFAULT;
-
-       *pos += copy;
-
-       return copy;
+       return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
+                                      dbg->outlen);
 }
 
 static const struct file_operations dfops = {
@@ -1258,19 +1273,11 @@ static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
        char outlen[8];
        int err;
 
-       if (*pos)
-               return 0;
-
        err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
        if (err < 0)
                return err;
 
-       if (copy_to_user(buf, &outlen, err))
-               return -EFAULT;
-
-       *pos += err;
-
-       return err;
+       return simple_read_from_buffer(buf, count, pos, outlen, err);
 }
 
 static ssize_t outlen_write(struct file *filp, const char __user *buf,
index 413080a312a7fdba0d159559032d09eeea173460..90fabd612b6cd84f1420afa151cc6c3b0103acfb 100644 (file)
@@ -150,22 +150,13 @@ static ssize_t average_read(struct file *filp, char __user *buf, size_t count,
        int ret;
        char tbuf[22];
 
-       if (*pos)
-               return 0;
-
        stats = filp->private_data;
        spin_lock_irq(&stats->lock);
        if (stats->n)
                field = div64_u64(stats->sum, stats->n);
        spin_unlock_irq(&stats->lock);
        ret = snprintf(tbuf, sizeof(tbuf), "%llu\n", field);
-       if (ret > 0) {
-               if (copy_to_user(buf, tbuf, ret))
-                       return -EFAULT;
-       }
-
-       *pos += ret;
-       return ret;
+       return simple_read_from_buffer(buf, count, pos, tbuf, ret);
 }
 
 static ssize_t average_write(struct file *filp, const char __user *buf,
@@ -442,9 +433,6 @@ static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count,
        u64 field;
        int ret;
 
-       if (*pos)
-               return 0;
-
        desc = filp->private_data;
        d = (void *)(desc - desc->i) - sizeof(*d);
        switch (d->type) {
@@ -470,13 +458,7 @@ static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count,
        else
                ret = snprintf(tbuf, sizeof(tbuf), "0x%llx\n", field);
 
-       if (ret > 0) {
-               if (copy_to_user(buf, tbuf, ret))
-                       return -EFAULT;
-       }
-
-       *pos += ret;
-       return ret;
+       return simple_read_from_buffer(buf, count, pos, tbuf, ret);
 }
 
 static const struct file_operations fops = {
index 09f178a3fcabb4082229a4f4985fc47295482d7f..0240aee9189eb90b551be15642344428f9485d83 100644 (file)
@@ -138,6 +138,8 @@ TRACE_EVENT(mlx5_fs_del_fg,
        {MLX5_FLOW_CONTEXT_ACTION_MOD_HDR,       "MOD_HDR"},\
        {MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH,     "VLAN_PUSH"},\
        {MLX5_FLOW_CONTEXT_ACTION_VLAN_POP,      "VLAN_POP"},\
+       {MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2,   "VLAN_PUSH_2"},\
+       {MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2,    "VLAN_POP_2"},\
        {MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}
 
 TRACE_EVENT(mlx5_fs_set_fte,
index 91f1209886ffdbb37af33ac32369f312296f8bfa..f32e69170b30e60bb8ec9c915d4d2e2e46b5851f 100644 (file)
@@ -70,9 +70,9 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
                flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
                                     MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
        else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
-               flow_act.vlan.ethtype = ntohs(attr->vlan_proto);
-               flow_act.vlan.vid = attr->vlan_vid;
-               flow_act.vlan.prio = attr->vlan_prio;
+               flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto);
+               flow_act.vlan[0].vid = attr->vlan_vid;
+               flow_act.vlan[0].prio = attr->vlan_prio;
        }
 
        if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
index 5a00deff54576429460ee10fd25ea3bc62f28485..6a62b84e57f4fcb90fb54c7e8fb1ccfb9c686503 100644 (file)
@@ -349,9 +349,15 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
 
        vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);
 
-       MLX5_SET(vlan, vlan, ethtype, fte->action.vlan.ethtype);
-       MLX5_SET(vlan, vlan, vid, fte->action.vlan.vid);
-       MLX5_SET(vlan, vlan, prio, fte->action.vlan.prio);
+       MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype);
+       MLX5_SET(vlan, vlan, vid, fte->action.vlan[0].vid);
+       MLX5_SET(vlan, vlan, prio, fte->action.vlan[0].prio);
+
+       vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan_2);
+
+       MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype);
+       MLX5_SET(vlan, vlan, vid, fte->action.vlan[1].vid);
+       MLX5_SET(vlan, vlan, prio, fte->action.vlan[1].prio);
 
        in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,
                                      match_value);
index f1a86cea86a0e24c5128e50f23bbba8a33112b7d..f880ffc9acd6337f378aa76c019abbf4baf86626 100644 (file)
@@ -1465,7 +1465,9 @@ static bool check_conflicting_actions(u32 action1, u32 action2)
                             MLX5_FLOW_CONTEXT_ACTION_DECAP |
                             MLX5_FLOW_CONTEXT_ACTION_MOD_HDR  |
                             MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
-                            MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))
+                            MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
+                            MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 |
+                            MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2))
                return true;
 
        return false;
@@ -1824,7 +1826,7 @@ search_again_locked:
 
        g = alloc_auto_flow_group(ft, spec);
        if (IS_ERR(g)) {
-               rule = (void *)g;
+               rule = ERR_CAST(g);
                up_write_ref_node(&ft->node);
                return rule;
        }
index 615005e6381958c6f8289897993fda27a8693e25..f9b950e1bd85add4bc20551fda0b4869db8e06ee 100644 (file)
@@ -64,7 +64,7 @@
 #include "lib/clock.h"
 
 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
-MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
+MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
 MODULE_LICENSE("Dual BSD/GPL");
 MODULE_VERSION(DRIVER_VERSION);
 
index 023882d9a22e59a7b172aee6a3260606932f4a03..49955117ae365888bdab0464f281e664682e122d 100644 (file)
@@ -66,6 +66,12 @@ do {                                                                 \
                __func__, __LINE__, current->pid,       \
               ##__VA_ARGS__)
 
+#define mlx5_core_err_rl(__dev, format, ...)                           \
+       dev_err_ratelimited(&(__dev)->pdev->dev,                        \
+                          "%s:%d:(pid %d): " format,                   \
+                          __func__, __LINE__, current->pid,            \
+                          ##__VA_ARGS__)
+
 #define mlx5_core_warn(__dev, format, ...)                             \
        dev_warn(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,        \
                 __func__, __LINE__, current->pid,                      \
index f4f02f775c93869ba978ec6dc9be8dd62d7d99a9..0670165afd5fda40aaf1f0a9dc54e570210f9739 100644 (file)
@@ -146,23 +146,6 @@ int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
 }
 EXPORT_SYMBOL(mlx5_core_query_mkey);
 
-int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
-                            u32 *mkey)
-{
-       u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0};
-       u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]   = {0};
-       int err;
-
-       MLX5_SET(query_special_contexts_in, in, opcode,
-                MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
-       err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
-       if (!err)
-               *mkey = MLX5_GET(query_special_contexts_out, out,
-                                dump_fill_mkey);
-       return err;
-}
-EXPORT_SYMBOL(mlx5_core_dump_fill_mkey);
-
 static inline u32 mlx5_get_psv(u32 *out, int psv_index)
 {
        switch (psv_index) {
index 02f72ebf31a78f221b21eaf74ee9b6debcbe998e..0566c6a94805e91212cbae4cd07efe2a398d19b3 100644 (file)
@@ -750,7 +750,7 @@ enum {
 
 #define MLX5_MINI_CQE_ARRAY_SIZE 8
 
-static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
+static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
 {
        return (cqe->op_own >> 2) & 0x3;
 }
@@ -770,14 +770,14 @@ static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
        return (cqe->l4_l3_hdr_type >> 2) & 0x3;
 }
 
-static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
+static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
 {
        return cqe->outer_l3_tunneled & 0x1;
 }
 
-static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
+static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
 {
-       return !!(cqe->l4_l3_hdr_type & 0x1);
+       return cqe->l4_l3_hdr_type & 0x1;
 }
 
 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
@@ -1071,6 +1071,9 @@ enum mlx5_qcam_feature_groups {
 #define MLX5_CAP_GEN(mdev, cap) \
        MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
 
+#define MLX5_CAP_GEN_64(mdev, cap) \
+       MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
+
 #define MLX5_CAP_GEN_MAX(mdev, cap) \
        MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
 
index 80cbb7fdce4a1a9afea00cc7dbfbe16249871b2d..957199c20a0fe335c71605f33998932a1ed66e97 100644 (file)
@@ -138,9 +138,14 @@ enum {
        MLX5_REG_HOST_ENDIANNESS = 0x7004,
        MLX5_REG_MCIA            = 0x9014,
        MLX5_REG_MLCR            = 0x902b,
+       MLX5_REG_MTRC_CAP        = 0x9040,
+       MLX5_REG_MTRC_CONF       = 0x9041,
+       MLX5_REG_MTRC_STDB       = 0x9042,
+       MLX5_REG_MTRC_CTRL       = 0x9043,
        MLX5_REG_MPCNT           = 0x9051,
        MLX5_REG_MTPPS           = 0x9053,
        MLX5_REG_MTPPSE          = 0x9054,
+       MLX5_REG_MPEGC           = 0x9056,
        MLX5_REG_MCQI            = 0x9061,
        MLX5_REG_MCC             = 0x9062,
        MLX5_REG_MCDA            = 0x9063,
@@ -1067,8 +1072,6 @@ int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
                           struct mlx5_core_mkey *mkey);
 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
                         u32 *out, int outlen);
-int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
-                            u32 *mkey);
 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
index 757b4a30281e6e8c82be94db32c7982089817350..c40f2fc68655d368a49a1d7b0904e5eda45bbc78 100644 (file)
@@ -152,6 +152,8 @@ struct mlx5_fs_vlan {
         u8  prio;
 };
 
+#define MLX5_FS_VLAN_DEPTH     2
+
 struct mlx5_flow_act {
        u32 action;
        bool has_flow_tag;
@@ -159,7 +161,7 @@ struct mlx5_flow_act {
        u32 encap_id;
        u32 modify_id;
        uintptr_t esp_id;
-       struct mlx5_fs_vlan vlan;
+       struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
        struct ib_counters *counters;
 };
 
index ac281f5ec9b8077ba859f33eaf61e3f03ecdeb3d..22f54bedfaaec4d44d15bc9a3d298d0261bc6c19 100644 (file)
@@ -75,6 +75,15 @@ enum {
        MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
 };
 
+enum {
+       MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
+       MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
+};
+
+enum {
+       MLX5_OBJ_TYPE_UCTX = 0x0004,
+};
+
 enum {
        MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
        MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
@@ -242,6 +251,8 @@ enum {
        MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
        MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
        MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
+       MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
+       MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
        MLX5_CMD_OP_MAX
 };
 
@@ -326,7 +337,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
        u8         reserved_at_9[0x1];
        u8         pop_vlan[0x1];
        u8         push_vlan[0x1];
-       u8         reserved_at_c[0x14];
+       u8         reserved_at_c[0x1];
+       u8         pop_vlan_2[0x1];
+       u8         push_vlan_2[0x1];
+       u8         reserved_at_f[0x11];
 
        u8         reserved_at_20[0x2];
        u8         log_max_ft_size[0x6];
@@ -874,7 +888,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         log_max_eq_sz[0x8];
        u8         reserved_at_e8[0x2];
        u8         log_max_mkey[0x6];
-       u8         reserved_at_f0[0xc];
+       u8         reserved_at_f0[0x8];
+       u8         dump_fill_mkey[0x1];
+       u8         reserved_at_f9[0x3];
        u8         log_max_eq[0x4];
 
        u8         max_indirection[0x8];
@@ -1113,7 +1129,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_3f8[0x3];
        u8         log_max_current_uc_list[0x5];
 
-       u8         reserved_at_400[0x80];
+       u8         general_obj_types[0x40];
+
+       u8         reserved_at_440[0x40];
 
        u8         reserved_at_480[0x3];
        u8         log_max_l2_table[0x5];
@@ -1668,7 +1686,11 @@ struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
 
        u8         rx_buffer_full_low[0x20];
 
-       u8         reserved_at_1c0[0x600];
+       u8         rx_icrc_encapsulated_high[0x20];
+
+       u8         rx_icrc_encapsulated_low[0x20];
+
+       u8         reserved_at_200[0x5c0];
 };
 
 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
@@ -2367,6 +2389,8 @@ enum {
        MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
        MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
        MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
 };
 
 struct mlx5_ifc_vlan_bits {
@@ -2397,7 +2421,9 @@ struct mlx5_ifc_flow_context_bits {
 
        u8         modify_header_id[0x20];
 
-       u8         reserved_at_100[0x100];
+       struct mlx5_ifc_vlan_bits push_vlan_2;
+
+       u8         reserved_at_120[0xe0];
 
        struct mlx5_ifc_fte_match_param_bits match_value;
 
@@ -8030,9 +8056,23 @@ struct mlx5_ifc_peir_reg_bits {
        u8         error_type[0x8];
 };
 
-struct mlx5_ifc_pcam_enhanced_features_bits {
-       u8         reserved_at_0[0x76];
+struct mlx5_ifc_mpegc_reg_bits {
+       u8         reserved_at_0[0x30];
+       u8         field_select[0x10];
+
+       u8         tx_overflow_sense[0x1];
+       u8         mark_cqe[0x1];
+       u8         mark_cnp[0x1];
+       u8         reserved_at_43[0x1b];
+       u8         tx_lossy_overflow_oper[0x2];
+
+       u8         reserved_at_60[0x100];
+};
 
+struct mlx5_ifc_pcam_enhanced_features_bits {
+       u8         reserved_at_0[0x6d];
+       u8         rx_icrc_encapsulated_counter[0x1];
+       u8         reserved_at_6e[0x8];
        u8         pfcc_mask[0x1];
        u8         reserved_at_77[0x4];
        u8         rx_buffer_fullness_counters[0x1];
@@ -8077,7 +8117,11 @@ struct mlx5_ifc_pcam_reg_bits {
 };
 
 struct mlx5_ifc_mcam_enhanced_features_bits {
-       u8         reserved_at_0[0x7b];
+       u8         reserved_at_0[0x74];
+       u8         mark_tx_action_cnp[0x1];
+       u8         mark_tx_action_cqe[0x1];
+       u8         dynamic_tx_overflow[0x1];
+       u8         reserved_at_77[0x4];
        u8         pcie_outbound_stalled[0x1];
        u8         tx_overflow_buffer_pkt[0x1];
        u8         mtpps_enh_out_per_adj[0x1];
@@ -8092,7 +8136,11 @@ struct mlx5_ifc_mcam_access_reg_bits {
        u8         mcqi[0x1];
        u8         reserved_at_1f[0x1];
 
-       u8         regs_95_to_64[0x20];
+       u8         regs_95_to_87[0x9];
+       u8         mpegc[0x1];
+       u8         regs_85_to_68[0x12];
+       u8         tracer_registers[0x4];
+
        u8         regs_63_to_32[0x20];
        u8         regs_31_to_0[0x20];
 };
@@ -9115,4 +9163,113 @@ struct mlx5_ifc_dealloc_memic_out_bits {
        u8         reserved_at_40[0x40];
 };
 
+struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
+       u8         opcode[0x10];
+       u8         uid[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         obj_type[0x10];
+
+       u8         obj_id[0x20];
+
+       u8         reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+
+       u8         syndrome[0x20];
+
+       u8         obj_id[0x20];
+
+       u8         reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_umem_bits {
+       u8         modify_field_select[0x40];
+
+       u8         reserved_at_40[0x5b];
+       u8         log_page_size[0x5];
+
+       u8         page_offset[0x20];
+
+       u8         num_of_mtt[0x40];
+
+       struct mlx5_ifc_mtt_bits  mtt[0];
+};
+
+struct mlx5_ifc_uctx_bits {
+       u8         modify_field_select[0x40];
+
+       u8         reserved_at_40[0x1c0];
+};
+
+struct mlx5_ifc_create_umem_in_bits {
+       struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
+       struct mlx5_ifc_umem_bits                     umem;
+};
+
+struct mlx5_ifc_create_uctx_in_bits {
+       struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
+       struct mlx5_ifc_uctx_bits                     uctx;
+};
+
+struct mlx5_ifc_mtrc_string_db_param_bits {
+       u8         string_db_base_address[0x20];
+
+       u8         reserved_at_20[0x8];
+       u8         string_db_size[0x18];
+};
+
+struct mlx5_ifc_mtrc_cap_bits {
+       u8         trace_owner[0x1];
+       u8         trace_to_memory[0x1];
+       u8         reserved_at_2[0x4];
+       u8         trc_ver[0x2];
+       u8         reserved_at_8[0x14];
+       u8         num_string_db[0x4];
+
+       u8         first_string_trace[0x8];
+       u8         num_string_trace[0x8];
+       u8         reserved_at_30[0x28];
+
+       u8         log_max_trace_buffer_size[0x8];
+
+       u8         reserved_at_60[0x20];
+
+       struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
+
+       u8         reserved_at_280[0x180];
+};
+
+struct mlx5_ifc_mtrc_conf_bits {
+       u8         reserved_at_0[0x1c];
+       u8         trace_mode[0x4];
+       u8         reserved_at_20[0x18];
+       u8         log_trace_buffer_size[0x8];
+       u8         trace_mkey[0x20];
+       u8         reserved_at_60[0x3a0];
+};
+
+struct mlx5_ifc_mtrc_stdb_bits {
+       u8         string_db_index[0x4];
+       u8         reserved_at_4[0x4];
+       u8         read_size[0x18];
+       u8         start_offset[0x20];
+       u8         string_db_data[0];
+};
+
+struct mlx5_ifc_mtrc_ctrl_bits {
+       u8         trace_status[0x2];
+       u8         reserved_at_2[0x2];
+       u8         arm_event[0x1];
+       u8         reserved_at_5[0xb];
+       u8         modify_field_select[0x10];
+       u8         reserved_at_20[0x2b];
+       u8         current_timestamp52_32[0x15];
+       u8         current_timestamp31_0[0x20];
+       u8         reserved_at_80[0x180];
+};
+
 #endif /* MLX5_IFC_H */