Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
authorSaeed Mahameed <saeedm@mellanox.com>
Mon, 23 Jul 2018 21:58:46 +0000 (14:58 -0700)
committerSaeed Mahameed <saeedm@mellanox.com>
Mon, 23 Jul 2018 21:58:46 +0000 (14:58 -0700)
mlx5 core infrastructure updates and fixes.

From Eran:
 - Add MPEGC (Management PCIe General Configuration) registers and btis
 - Fix tristate and description for MLX5 module

rom Feras:
 - Add hardware structures for the firmware tracer

From Jainbo:
 - Core support for double vlan push/pop steering action

From Max:
 - Add XRQ commands definitions

From Noa:
 - Add missing SET_DRIVER_VERSION command translation

From Roi:
 - Use ERR_CAST() instead of coding it

From Tariq:
 - Better return types for CQE API

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
1  2 
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
include/linux/mlx5/mlx5_ifc.h

index 384c1fa490811ee651919c139b9cd9e724d4ff81,041c18faea46bd01f7359962fdf13e1f4f77a3d6..f498c7730c5b105cb23f41611ec84f7992dba830
@@@ -278,6 -278,7 +278,7 @@@ static int mlx5_internal_err_ret_value(
        case MLX5_CMD_OP_DESTROY_PSV:
        case MLX5_CMD_OP_DESTROY_SRQ:
        case MLX5_CMD_OP_DESTROY_XRC_SRQ:
+       case MLX5_CMD_OP_DESTROY_XRQ:
        case MLX5_CMD_OP_DESTROY_DCT:
        case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
        case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
        case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
        case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
        case MLX5_CMD_OP_FPGA_DESTROY_QP:
+       case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
                return MLX5_CMD_STAT_OK;
  
        case MLX5_CMD_OP_QUERY_HCA_CAP:
        case MLX5_CMD_OP_CREATE_XRC_SRQ:
        case MLX5_CMD_OP_QUERY_XRC_SRQ:
        case MLX5_CMD_OP_ARM_XRC_SRQ:
+       case MLX5_CMD_OP_CREATE_XRQ:
+       case MLX5_CMD_OP_QUERY_XRQ:
+       case MLX5_CMD_OP_ARM_XRQ:
        case MLX5_CMD_OP_CREATE_DCT:
        case MLX5_CMD_OP_DRAIN_DCT:
        case MLX5_CMD_OP_QUERY_DCT:
        case MLX5_CMD_OP_FPGA_MODIFY_QP:
        case MLX5_CMD_OP_FPGA_QUERY_QP:
        case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
+       case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
                *status = MLX5_DRIVER_STATUS_ABORTED;
                *synd = MLX5_DRIVER_SYND;
                return -EIO;
@@@ -452,6 -458,7 +458,7 @@@ const char *mlx5_command_str(int comman
        MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
        MLX5_COMMAND_STR_CASE(QUERY_ISSI);
        MLX5_COMMAND_STR_CASE(SET_ISSI);
+       MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
        MLX5_COMMAND_STR_CASE(CREATE_MKEY);
        MLX5_COMMAND_STR_CASE(QUERY_MKEY);
        MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
        MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
        MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
        MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
+       MLX5_COMMAND_STR_CASE(CREATE_XRQ);
+       MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
+       MLX5_COMMAND_STR_CASE(QUERY_XRQ);
+       MLX5_COMMAND_STR_CASE(ARM_XRQ);
+       MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
+       MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
        default: return "unknown command opcode";
        }
  }
@@@ -677,7 -690,7 +690,7 @@@ struct mlx5_ifc_mbox_out_bits 
  
  struct mlx5_ifc_mbox_in_bits {
        u8         opcode[0x10];
-       u8         reserved_at_10[0x10];
+       u8         uid[0x10];
  
        u8         reserved_at_20[0x10];
        u8         op_mod[0x10];
@@@ -697,6 -710,7 +710,7 @@@ static int mlx5_cmd_check(struct mlx5_c
        u8  status;
        u16 opcode;
        u16 op_mod;
+       u16 uid;
  
        mlx5_cmd_mbox_status(out, &status, &syndrome);
        if (!status)
  
        opcode = MLX5_GET(mbox_in, in, opcode);
        op_mod = MLX5_GET(mbox_in, in, op_mod);
+       uid    = MLX5_GET(mbox_in, in, uid);
  
-       mlx5_core_err(dev,
+       if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
+               mlx5_core_err_rl(dev,
+                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
+                       mlx5_command_str(opcode), opcode, op_mod,
+                       cmd_status_str(status), status, syndrome);
+       else
+               mlx5_core_dbg(dev,
                      "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
                      mlx5_command_str(opcode),
                      opcode, op_mod,
@@@ -807,7 -828,6 +828,7 @@@ static void cmd_work_handler(struct wor
        unsigned long flags;
        bool poll_cmd = ent->polling;
        int alloc_ret;
 +      int cmd_mode;
  
        sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
        down(sem);
        set_signature(ent, !cmd->checksum_disabled);
        dump_command(dev, ent, 1);
        ent->ts1 = ktime_get_ns();
 +      cmd_mode = cmd->mode;
  
        if (ent->callback)
                schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
        iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
        mmiowb();
        /* if not in polling don't use ent after this point */
 -      if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
 +      if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
                poll_timeout(ent);
                /* make sure we read the descriptor after ownership is SW */
                rmb();
@@@ -1022,7 -1041,10 +1043,10 @@@ static ssize_t dbg_write(struct file *f
        if (!dbg->in_msg || !dbg->out_msg)
                return -ENOMEM;
  
-       if (copy_from_user(lbuf, buf, sizeof(lbuf)))
+       if (count < sizeof(lbuf) - 1)
+               return -EINVAL;
+       if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
                return -EFAULT;
  
        lbuf[sizeof(lbuf) - 1] = 0;
@@@ -1226,21 -1248,12 +1250,12 @@@ static ssize_t data_read(struct file *f
  {
        struct mlx5_core_dev *dev = filp->private_data;
        struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
-       int copy;
-       if (*pos)
-               return 0;
  
        if (!dbg->out_msg)
                return -ENOMEM;
  
-       copy = min_t(int, count, dbg->outlen);
-       if (copy_to_user(buf, dbg->out_msg, copy))
-               return -EFAULT;
-       *pos += copy;
-       return copy;
+       return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
+                                      dbg->outlen);
  }
  
  static const struct file_operations dfops = {
@@@ -1258,19 -1271,11 +1273,11 @@@ static ssize_t outlen_read(struct file 
        char outlen[8];
        int err;
  
-       if (*pos)
-               return 0;
        err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
        if (err < 0)
                return err;
  
-       if (copy_to_user(buf, &outlen, err))
-               return -EFAULT;
-       *pos += err;
-       return err;
+       return simple_read_from_buffer(buf, count, pos, outlen, err);
  }
  
  static ssize_t outlen_write(struct file *filp, const char __user *buf,
  {
        struct mlx5_core_dev *dev = filp->private_data;
        struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 -      char outlen_str[8];
 +      char outlen_str[8] = {0};
        int outlen;
        void *ptr;
        int err;
        if (copy_from_user(outlen_str, buf, count))
                return -EFAULT;
  
 -      outlen_str[7] = 0;
 -
        err = sscanf(outlen_str, "%d", &outlen);
        if (err < 0)
                return err;
index 91f1209886ffdbb37af33ac32369f312296f8bfa,8f50ce80ff66045651ae4e15d2924a8a037bdf5f..f32e69170b30e60bb8ec9c915d4d2e2e46b5851f
@@@ -70,9 -70,9 +70,9 @@@ mlx5_eswitch_add_offloaded_rule(struct 
                flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
                                     MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
        else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
-               flow_act.vlan.ethtype = ntohs(attr->vlan_proto);
-               flow_act.vlan.vid = attr->vlan_vid;
-               flow_act.vlan.prio = attr->vlan_prio;
+               flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto);
+               flow_act.vlan[0].vid = attr->vlan_vid;
+               flow_act.vlan[0].prio = attr->vlan_prio;
        }
  
        if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
@@@ -1079,8 -1079,8 +1079,8 @@@ static int mlx5_devlink_eswitch_check(s
        if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
                return -EOPNOTSUPP;
  
 -      if (!MLX5_CAP_GEN(dev, vport_group_manager))
 -              return -EOPNOTSUPP;
 +      if(!MLX5_ESWITCH_MANAGER(dev))
 +              return -EPERM;
  
        if (dev->priv.eswitch->mode == SRIOV_NONE)
                return -EOPNOTSUPP;
index f1a86cea86a0e24c5128e50f23bbba8a33112b7d,29b86232f13adadbd87db469987f8595ef098440..f880ffc9acd6337f378aa76c019abbf4baf86626
@@@ -32,7 -32,6 +32,7 @@@
  
  #include <linux/mutex.h>
  #include <linux/mlx5/driver.h>
 +#include <linux/mlx5/eswitch.h>
  
  #include "mlx5_core.h"
  #include "fs_core.h"
@@@ -1465,7 -1464,9 +1465,9 @@@ static bool check_conflicting_actions(u
                             MLX5_FLOW_CONTEXT_ACTION_DECAP |
                             MLX5_FLOW_CONTEXT_ACTION_MOD_HDR  |
                             MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
-                            MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))
+                            MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
+                            MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 |
+                            MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2))
                return true;
  
        return false;
@@@ -1824,7 -1825,7 +1826,7 @@@ search_again_locked
  
        g = alloc_auto_flow_group(ft, spec);
        if (IS_ERR(g)) {
-               rule = (void *)g;
+               rule = ERR_CAST(g);
                up_write_ref_node(&ft->node);
                return rule;
        }
@@@ -2653,7 -2654,7 +2655,7 @@@ int mlx5_init_fs(struct mlx5_core_dev *
                        goto err;
        }
  
 -      if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
 +      if (MLX5_ESWITCH_MANAGER(dev)) {
                if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ft_support)) {
                        err = init_fdb_root_ns(steering);
                        if (err)
index ac281f5ec9b8077ba859f33eaf61e3f03ecdeb3d,ae12120ef02103c23b2278c5ddd7d9de38ed246d..22f54bedfaaec4d44d15bc9a3d298d0261bc6c19
@@@ -75,6 -75,15 +75,15 @@@ enum 
        MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  };
  
+ enum {
+       MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
+       MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
+ };
+ enum {
+       MLX5_OBJ_TYPE_UCTX = 0x0004,
+ };
  enum {
        MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
        MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
        MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
        MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
        MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
+       MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
+       MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
        MLX5_CMD_OP_MAX
  };
  
@@@ -326,7 -337,10 +337,10 @@@ struct mlx5_ifc_flow_table_prop_layout_
        u8         reserved_at_9[0x1];
        u8         pop_vlan[0x1];
        u8         push_vlan[0x1];
-       u8         reserved_at_c[0x14];
+       u8         reserved_at_c[0x1];
+       u8         pop_vlan_2[0x1];
+       u8         push_vlan_2[0x1];
+       u8         reserved_at_f[0x11];
  
        u8         reserved_at_20[0x2];
        u8         log_max_ft_size[0x6];
@@@ -874,7 -888,9 +888,9 @@@ struct mlx5_ifc_cmd_hca_cap_bits 
        u8         log_max_eq_sz[0x8];
        u8         reserved_at_e8[0x2];
        u8         log_max_mkey[0x6];
-       u8         reserved_at_f0[0xc];
+       u8         reserved_at_f0[0x8];
+       u8         dump_fill_mkey[0x1];
+       u8         reserved_at_f9[0x3];
        u8         log_max_eq[0x4];
  
        u8         max_indirection[0x8];
        u8         vnic_env_queue_counters[0x1];
        u8         ets[0x1];
        u8         nic_flow_table[0x1];
 -      u8         eswitch_flow_table[0x1];
 +      u8         eswitch_manager[0x1];
        u8         device_memory[0x1];
        u8         mcam_reg[0x1];
        u8         pcam_reg[0x1];
        u8         reserved_at_3f8[0x3];
        u8         log_max_current_uc_list[0x5];
  
-       u8         reserved_at_400[0x80];
+       u8         general_obj_types[0x40];
+       u8         reserved_at_440[0x40];
  
        u8         reserved_at_480[0x3];
        u8         log_max_l2_table[0x5];
@@@ -1668,7 -1686,11 +1686,11 @@@ struct mlx5_ifc_eth_extended_cntrs_grp_
  
        u8         rx_buffer_full_low[0x20];
  
-       u8         reserved_at_1c0[0x600];
+       u8         rx_icrc_encapsulated_high[0x20];
+       u8         rx_icrc_encapsulated_low[0x20];
+       u8         reserved_at_200[0x5c0];
  };
  
  struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
@@@ -2367,6 -2389,8 +2389,8 @@@ enum 
        MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
        MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
        MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
  };
  
  struct mlx5_ifc_vlan_bits {
@@@ -2397,7 -2421,9 +2421,9 @@@ struct mlx5_ifc_flow_context_bits 
  
        u8         modify_header_id[0x20];
  
-       u8         reserved_at_100[0x100];
+       struct mlx5_ifc_vlan_bits push_vlan_2;
+       u8         reserved_at_120[0xe0];
  
        struct mlx5_ifc_fte_match_param_bits match_value;
  
@@@ -8030,9 -8056,23 +8056,23 @@@ struct mlx5_ifc_peir_reg_bits 
        u8         error_type[0x8];
  };
  
- struct mlx5_ifc_pcam_enhanced_features_bits {
-       u8         reserved_at_0[0x76];
+ struct mlx5_ifc_mpegc_reg_bits {
+       u8         reserved_at_0[0x30];
+       u8         field_select[0x10];
+       u8         tx_overflow_sense[0x1];
+       u8         mark_cqe[0x1];
+       u8         mark_cnp[0x1];
+       u8         reserved_at_43[0x1b];
+       u8         tx_lossy_overflow_oper[0x2];
+       u8         reserved_at_60[0x100];
+ };
  
+ struct mlx5_ifc_pcam_enhanced_features_bits {
+       u8         reserved_at_0[0x6d];
+       u8         rx_icrc_encapsulated_counter[0x1];
+       u8         reserved_at_6e[0x8];
        u8         pfcc_mask[0x1];
        u8         reserved_at_77[0x4];
        u8         rx_buffer_fullness_counters[0x1];
@@@ -8077,7 -8117,11 +8117,11 @@@ struct mlx5_ifc_pcam_reg_bits 
  };
  
  struct mlx5_ifc_mcam_enhanced_features_bits {
-       u8         reserved_at_0[0x7b];
+       u8         reserved_at_0[0x74];
+       u8         mark_tx_action_cnp[0x1];
+       u8         mark_tx_action_cqe[0x1];
+       u8         dynamic_tx_overflow[0x1];
+       u8         reserved_at_77[0x4];
        u8         pcie_outbound_stalled[0x1];
        u8         tx_overflow_buffer_pkt[0x1];
        u8         mtpps_enh_out_per_adj[0x1];
@@@ -8092,7 -8136,11 +8136,11 @@@ struct mlx5_ifc_mcam_access_reg_bits 
        u8         mcqi[0x1];
        u8         reserved_at_1f[0x1];
  
-       u8         regs_95_to_64[0x20];
+       u8         regs_95_to_87[0x9];
+       u8         mpegc[0x1];
+       u8         regs_85_to_68[0x12];
+       u8         tracer_registers[0x4];
        u8         regs_63_to_32[0x20];
        u8         regs_31_to_0[0x20];
  };
@@@ -9115,4 -9163,113 +9163,113 @@@ struct mlx5_ifc_dealloc_memic_out_bits 
        u8         reserved_at_40[0x40];
  };
  
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
+       u8         opcode[0x10];
+       u8         uid[0x10];
+       u8         reserved_at_20[0x10];
+       u8         obj_type[0x10];
+       u8         obj_id[0x20];
+       u8         reserved_at_60[0x20];
+ };
+ struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+       u8         syndrome[0x20];
+       u8         obj_id[0x20];
+       u8         reserved_at_60[0x20];
+ };
+ struct mlx5_ifc_umem_bits {
+       u8         modify_field_select[0x40];
+       u8         reserved_at_40[0x5b];
+       u8         log_page_size[0x5];
+       u8         page_offset[0x20];
+       u8         num_of_mtt[0x40];
+       struct mlx5_ifc_mtt_bits  mtt[0];
+ };
+ struct mlx5_ifc_uctx_bits {
+       u8         modify_field_select[0x40];
+       u8         reserved_at_40[0x1c0];
+ };
+ struct mlx5_ifc_create_umem_in_bits {
+       struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
+       struct mlx5_ifc_umem_bits                     umem;
+ };
+ struct mlx5_ifc_create_uctx_in_bits {
+       struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
+       struct mlx5_ifc_uctx_bits                     uctx;
+ };
+ struct mlx5_ifc_mtrc_string_db_param_bits {
+       u8         string_db_base_address[0x20];
+       u8         reserved_at_20[0x8];
+       u8         string_db_size[0x18];
+ };
+ struct mlx5_ifc_mtrc_cap_bits {
+       u8         trace_owner[0x1];
+       u8         trace_to_memory[0x1];
+       u8         reserved_at_2[0x4];
+       u8         trc_ver[0x2];
+       u8         reserved_at_8[0x14];
+       u8         num_string_db[0x4];
+       u8         first_string_trace[0x8];
+       u8         num_string_trace[0x8];
+       u8         reserved_at_30[0x28];
+       u8         log_max_trace_buffer_size[0x8];
+       u8         reserved_at_60[0x20];
+       struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
+       u8         reserved_at_280[0x180];
+ };
+ struct mlx5_ifc_mtrc_conf_bits {
+       u8         reserved_at_0[0x1c];
+       u8         trace_mode[0x4];
+       u8         reserved_at_20[0x18];
+       u8         log_trace_buffer_size[0x8];
+       u8         trace_mkey[0x20];
+       u8         reserved_at_60[0x3a0];
+ };
+ struct mlx5_ifc_mtrc_stdb_bits {
+       u8         string_db_index[0x4];
+       u8         reserved_at_4[0x4];
+       u8         read_size[0x18];
+       u8         start_offset[0x20];
+       u8         string_db_data[0];
+ };
+ struct mlx5_ifc_mtrc_ctrl_bits {
+       u8         trace_status[0x2];
+       u8         reserved_at_2[0x2];
+       u8         arm_event[0x1];
+       u8         reserved_at_5[0xb];
+       u8         modify_field_select[0x10];
+       u8         reserved_at_20[0x2b];
+       u8         current_timestamp52_32[0x15];
+       u8         current_timestamp31_0[0x20];
+       u8         reserved_at_80[0x180];
+ };
  #endif /* MLX5_IFC_H */