Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
authorLinus Torvalds <torvalds@woody.linux-foundation.org>
Sun, 22 Jul 2007 18:22:59 +0000 (11:22 -0700)
committerLinus Torvalds <torvalds@woody.linux-foundation.org>
Sun, 22 Jul 2007 18:22:59 +0000 (11:22 -0700)
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (60 commits)
  [ARM] 4524/1: S3C: Move register out of include/asm-arm/arch-s3c2410
  [ARM] 4523/1: S3C: Remove FIFO_MAX from uncompression headers
  [ARM] 4522/1: S3C: split include/asm-arm/arch/memory.h
  [ARM] 4521/2: S3C: Reorganise VA mapping headers
  [ARM] 4520/1: S3C: Remove old VA values from static map
  [ARM] 4519/1: S3C: split S3C2400 values out of S3C24XX map.h
  [ARM] 4518/1: S3C: Rename watchdog configuration options
  [ARM] 4517/1: S3C: Fix debug macros for ARM926 output
  [ARM] 4516/1: S3C: Fix uncompressor serial output for ARM926
  [ARM] 4515/1: S3C: Move uncompress code to plat-s3c
  [ARM] 4514/1: S3C: Rename DEBUG_S3C2410_PORT and DEBUG_S3C_UART
  [ARM] 4513/1: S3C: Rename CONFIG_S3C2410_LOWLEVEL_UART_PORT
  [ARM] 4512/1: S3C: rename the debug macros for per-cpu updates
  [ARM] 4511/1: S3C: updated LLSERIAL Kconfig defines for CPU support
  [ARM] 4510/1: S3C: split debug-macro support into plat-s3c
  [ARM] 4509/1: S3C: Create initial arch/arm/plat-s3c
  [ARM] 4508/1: S3C: Move items to include/asm-arm/plat-s3c
  [ARM] 4461/1: MXC platform and i.MX31ADS core support
  [ARM] 4507/1: pxa2xx clock_event_device
  [ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later
  ...

159 files changed:
MAINTAINERS
arch/arm/Kconfig
arch/arm/Kconfig.debug
arch/arm/Makefile
arch/arm/boot/Makefile
arch/arm/boot/compressed/Makefile
arch/arm/boot/compressed/head.S
arch/arm/configs/em_x270_defconfig [new file with mode: 0644]
arch/arm/configs/s3c2410_defconfig
arch/arm/mach-at91/at91rm9200_devices.c
arch/arm/mach-iop32x/Kconfig
arch/arm/mach-iop32x/Makefile
arch/arm/mach-iop32x/em7210.c [new file with mode: 0644]
arch/arm/mach-iop32x/irq.c
arch/arm/mach-ixp4xx/common.c
arch/arm/mach-ks8695/irq.c
arch/arm/mach-mx3/Kconfig [new file with mode: 0644]
arch/arm/mach-mx3/Makefile [new file with mode: 0644]
arch/arm/mach-mx3/Makefile.boot [new file with mode: 0644]
arch/arm/mach-mx3/mm.c [new file with mode: 0644]
arch/arm/mach-mx3/mx31ads.c [new file with mode: 0644]
arch/arm/mach-mx3/time.c [new file with mode: 0644]
arch/arm/mach-ns9xxx/Makefile
arch/arm/mach-ns9xxx/board-a9m9750dev.c
arch/arm/mach-ns9xxx/generic.c
arch/arm/mach-ns9xxx/irq.c
arch/arm/mach-ns9xxx/mach-cc9p9360js.c
arch/arm/mach-pxa/Kconfig
arch/arm/mach-pxa/Makefile
arch/arm/mach-pxa/devices.h
arch/arm/mach-pxa/em-x270.c [new file with mode: 0644]
arch/arm/mach-pxa/generic.c
arch/arm/mach-pxa/pm.c
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-pxa/sleep.S
arch/arm/mach-pxa/time.c
arch/arm/mach-rpc/riscpc.c
arch/arm/mach-s3c2410/Kconfig
arch/arm/mach-s3c2410/clock.c
arch/arm/mach-s3c2410/dma.c
arch/arm/mach-s3c2410/mach-amlm5900.c
arch/arm/mach-s3c2410/mach-bast.c
arch/arm/mach-s3c2410/mach-h1940.c
arch/arm/mach-s3c2410/mach-n30.c
arch/arm/mach-s3c2410/mach-otom.c
arch/arm/mach-s3c2410/mach-qt2410.c
arch/arm/mach-s3c2410/mach-smdk2410.c
arch/arm/mach-s3c2410/mach-vr1000.c
arch/arm/mach-s3c2410/s3c2410.c
arch/arm/mach-s3c2410/sleep.S
arch/arm/mach-s3c2412/Kconfig
arch/arm/mach-s3c2412/clock.c
arch/arm/mach-s3c2412/dma.c
arch/arm/mach-s3c2412/mach-smdk2413.c
arch/arm/mach-s3c2412/mach-vstms.c
arch/arm/mach-s3c2412/s3c2412.c
arch/arm/mach-s3c2440/Kconfig
arch/arm/mach-s3c2440/dma.c
arch/arm/mach-s3c2440/mach-anubis.c
arch/arm/mach-s3c2440/mach-nexcoder.c
arch/arm/mach-s3c2440/mach-osiris.c
arch/arm/mach-s3c2440/mach-rx3715.c
arch/arm/mach-s3c2440/mach-smdk2440.c
arch/arm/mach-s3c2442/Kconfig
arch/arm/mach-s3c2443/Kconfig
arch/arm/mach-s3c2443/dma.c
arch/arm/mach-s3c2443/mach-smdk2443.c
arch/arm/mach-sa1100/Kconfig
arch/arm/mach-sa1100/Makefile
arch/arm/mach-sa1100/jornada720_ssp.c [new file with mode: 0644]
arch/arm/mach-sa1100/neponset.c
arch/arm/mm/Kconfig
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
arch/arm/mm/proc-syms.c
arch/arm/mm/proc-v7.S
arch/arm/plat-iop/time.c
arch/arm/plat-mxc/Kconfig [new file with mode: 0644]
arch/arm/plat-mxc/Makefile [new file with mode: 0644]
arch/arm/plat-mxc/irq.c [new file with mode: 0644]
arch/arm/plat-s3c/Kconfig [new file with mode: 0644]
arch/arm/plat-s3c24xx/Kconfig
arch/arm/plat-s3c24xx/common-smdk.c
arch/arm/plat-s3c24xx/cpu.c
arch/arm/plat-s3c24xx/devs.c
arch/arm/plat-s3c24xx/pm.c
arch/arm/plat-s3c24xx/s3c244x.c
arch/arm/plat-s3c24xx/sleep.S
arch/arm/plat-s3c24xx/time.c
arch/arm/vfp/vfphw.S
arch/arm/vfp/vfpmodule.c
drivers/char/watchdog/Kconfig
drivers/char/watchdog/Makefile
drivers/char/watchdog/iop_wdt.c [new file with mode: 0644]
drivers/net/arm/ether1.c
drivers/net/arm/ether3.c
drivers/net/arm/etherh.c
drivers/scsi/arm/cumana_1.c
drivers/scsi/arm/ecoscsi.c
drivers/scsi/arm/oak.c
drivers/serial/imx.c
drivers/serial/s3c2410.c
include/asm-arm/arch-at91/at91_mci.h
include/asm-arm/arch-iop13xx/iop13xx.h
include/asm-arm/arch-iop13xx/system.h
include/asm-arm/arch-iop13xx/uncompress.h
include/asm-arm/arch-iop32x/uncompress.h
include/asm-arm/arch-mxc/board-mx31ads.h [new file with mode: 0644]
include/asm-arm/arch-mxc/common.h [new file with mode: 0644]
include/asm-arm/arch-mxc/dma.h [new file with mode: 0644]
include/asm-arm/arch-mxc/entry-macro.S [new file with mode: 0644]
include/asm-arm/arch-mxc/hardware.h [new file with mode: 0644]
include/asm-arm/arch-mxc/io.h [new file with mode: 0644]
include/asm-arm/arch-mxc/irqs.h [new file with mode: 0644]
include/asm-arm/arch-mxc/memory.h [new file with mode: 0644]
include/asm-arm/arch-mxc/mx31.h [new file with mode: 0644]
include/asm-arm/arch-mxc/mxc.h [new file with mode: 0644]
include/asm-arm/arch-mxc/system.h [new file with mode: 0644]
include/asm-arm/arch-mxc/timex.h [new file with mode: 0644]
include/asm-arm/arch-mxc/uncompress.h [new file with mode: 0644]
include/asm-arm/arch-mxc/vmalloc.h [new file with mode: 0644]
include/asm-arm/arch-ns9xxx/regs-bbu.h
include/asm-arm/arch-ns9xxx/regs-mem.h
include/asm-arm/arch-ns9xxx/regs-sys.h
include/asm-arm/arch-pxa/pm.h
include/asm-arm/arch-s3c2400/map.h [new file with mode: 0644]
include/asm-arm/arch-s3c2400/memory.h [new file with mode: 0644]
include/asm-arm/arch-s3c2410/debug-macro.S
include/asm-arm/arch-s3c2410/map.h
include/asm-arm/arch-s3c2410/memory.h
include/asm-arm/arch-s3c2410/regs-lcd.h
include/asm-arm/arch-s3c2410/system.h
include/asm-arm/arch-s3c2410/uncompress.h
include/asm-arm/arch-sa1100/jornada720.h [new file with mode: 0644]
include/asm-arm/elf.h
include/asm-arm/floppy.h
include/asm-arm/hardware/iop3xx.h
include/asm-arm/pgtable-nommu.h
include/asm-arm/plat-s3c/debug-macro.S [new file with mode: 0644]
include/asm-arm/plat-s3c/iic.h [moved from include/asm-arm/arch-s3c2410/iic.h with 100% similarity]
include/asm-arm/plat-s3c/map.h [new file with mode: 0644]
include/asm-arm/plat-s3c/nand.h [moved from include/asm-arm/arch-s3c2410/nand.h with 100% similarity]
include/asm-arm/plat-s3c/regs-ac97.h [moved from include/asm-arm/arch-s3c2410/regs-ac97.h with 100% similarity]
include/asm-arm/plat-s3c/regs-adc.h [moved from include/asm-arm/arch-s3c2410/regs-adc.h with 100% similarity]
include/asm-arm/plat-s3c/regs-iic.h [moved from include/asm-arm/arch-s3c2410/regs-iic.h with 100% similarity]
include/asm-arm/plat-s3c/regs-nand.h [moved from include/asm-arm/arch-s3c2410/regs-nand.h with 100% similarity]
include/asm-arm/plat-s3c/regs-rtc.h [moved from include/asm-arm/arch-s3c2410/regs-rtc.h with 100% similarity]
include/asm-arm/plat-s3c/regs-serial.h [moved from include/asm-arm/arch-s3c2410/regs-serial.h with 96% similarity]
include/asm-arm/plat-s3c/regs-timer.h [moved from include/asm-arm/arch-s3c2410/regs-timer.h with 86% similarity]
include/asm-arm/plat-s3c/regs-watchdog.h [moved from include/asm-arm/arch-s3c2410/regs-watchdog.h with 83% similarity]
include/asm-arm/plat-s3c/uncompress.h [new file with mode: 0644]
include/asm-arm/plat-s3c24xx/regs-iis.h [moved from include/asm-arm/arch-s3c2410/regs-iis.h with 100% similarity]
include/asm-arm/plat-s3c24xx/regs-spi.h [moved from include/asm-arm/arch-s3c2410/regs-spi.h with 100% similarity]
include/asm-arm/plat-s3c24xx/regs-udc.h [moved from include/asm-arm/arch-s3c2410/regs-udc.h with 100% similarity]
include/asm-arm/plat-s3c24xx/udc.h [moved from include/asm-arm/arch-s3c2410/udc.h with 100% similarity]
include/asm-arm/thread_info.h
include/asm-arm/unistd.h
include/asm-arm/vfp.h

index a9b9ef614ae7d602c05bad2b101583fe8e6a019a..01f222e51871ba1ed86465119e2329ba74e7afb1 100644 (file)
@@ -463,7 +463,7 @@ S:  Maintained
 
 ARM/HP JORNADA 7XX MACHINE SUPPORT
 P:      Kristoffer Ericson
-M:      kristoffer_e1@hotmail.com
+M:      kristoffer.ericson@gmail.com
 W:      www.jlime.com
 S:      Maintained
 
index a44c6da9bf8363d21169eecb1521ef8f16144e7a..85016313bd1175779772fbfe45d1c798780e064e 100644 (file)
@@ -324,6 +324,12 @@ config ARCH_NS9XXX
 
          <http://www.digi.com/products/microprocessors/index.jsp>
 
+config ARCH_MXC
+       bool "Freescale MXC/iMX-based"
+       select ARCH_MTD_XIP
+       help
+         Support for Freescale MXC/iMX-based family of processors
+
 config ARCH_PNX4008
        bool "Philips Nexperia PNX4008 Mobile"
        help
@@ -432,6 +438,7 @@ source "arch/arm/mach-omap1/Kconfig"
 source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/plat-s3c24xx/Kconfig"
+source "arch/arm/plat-s3c/Kconfig"
 
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
@@ -456,6 +463,8 @@ source "arch/arm/mach-realview/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
+source "arch/arm/plat-mxc/Kconfig"
+
 source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-ns9xxx/Kconfig"
index 40c5eb1f55c7e3572f02ebdc39e12d9020bc1936..18101f5f5f249b0377c1fe4299c9094f6db16af7 100644 (file)
@@ -82,24 +82,24 @@ config DEBUG_CLPS711X_UART2
          output to the second serial port on these devices.  Saying N will
          cause the debug messages to appear on the first serial port.
 
-config DEBUG_S3C2410_PORT
-       depends on DEBUG_LL && ARCH_S3C2410
-       bool "Kernel low-level debugging messages via S3C2410 UART"
+config DEBUG_S3C_PORT
+       depends on DEBUG_LL && PLAT_S3C
+       bool "Kernel low-level debugging messages via S3C UART"
        help
          Say Y here if you want debug print routines to go to one of the
-         S3C2410 internal UARTs. The chosen UART must have been configured
+         S3C internal UARTs. The chosen UART must have been configured
          before it is used.
 
-config DEBUG_S3C2410_UART
-       depends on ARCH_S3C2410
-       int "S3C2410 UART to use for low-level debug"
+config DEBUG_S3C_UART
+       depends on PLAT_S3C
+       int "S3C UART to use for low-level debug"
        default "0"
        help
-         Choice for UART for kernel low-level using S3C2410 UARTS,
+         Choice for UART for kernel low-level using S3C UARTS,
          should be between zero and two. The port must have been
          initialised by the boot-loader before use.
 
          The uncompressor code port configuration is now handled
-         by CONFIG_S3C2410_LOWLEVEL_UART_PORT.
+         by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
 endmenu
index cbd5010d3bc3acb5b64dc99ad5ba380e2f97f409..fa4ea9ff0797b9ff94144b2b69bee97524dd09a0 100644 (file)
@@ -137,6 +137,8 @@ endif
  textofs-$(CONFIG_ARCH_NS9XXX)    := 0x00108000
  machine-$(CONFIG_ARCH_DAVINCI)           := davinci
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
+  incdir-$(CONFIG_ARCH_MXC)       := mxc
+ machine-$(CONFIG_ARCH_MX3)       := mx3
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -183,6 +185,7 @@ core-$(CONFIG_VFP)          += arch/arm/vfp/
 core-$(CONFIG_PLAT_IOP)                += arch/arm/plat-iop/
 core-$(CONFIG_ARCH_OMAP)       += arch/arm/plat-omap/
 core-$(CONFIG_PLAT_S3C24XX)            += arch/arm/plat-s3c24xx/
+core-$(CONFIG_ARCH_MXC)                += arch/arm/plat-mxc/
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 drivers-$(CONFIG_ARCH_CLPS7500)        += drivers/acorn/char/
index ec9c400c7f82d171ba9ccf6e52cdb055bf1a50cb..25f12303b1062d163fcbb846b7e8709e609a640b 100644 (file)
@@ -91,4 +91,12 @@ zinstall: $(obj)/zImage
        $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
        $(obj)/zImage System.map "$(INSTALL_PATH)"
 
+zi:
+       $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+       $(obj)/zImage System.map "$(INSTALL_PATH)"
+
+i:
+       $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+       $(obj)/Image System.map "$(INSTALL_PATH)"
+
 subdir-            := bootp compressed
index a1f1691b67fe212f01c11a5e20f0f5fc78087fd3..6b8cbd69f2490d89b12344a3af53ca162307633d 100644 (file)
@@ -73,7 +73,7 @@ SEDFLAGS      = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
 
 targets       := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
                 head.o misc.o $(OBJS)
-EXTRA_CFLAGS  := -fpic
+EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  :=
 
 # Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
index d7fb5ee1637e8f25e23edcd69b7acbeca019b539..b9b03eda70e5a370b02b3c276cd9db69405af3d7 100644 (file)
@@ -55,7 +55,7 @@
 #elif defined(CONFIG_ARCH_S3C2410)
                .macro loadsp, rb
                mov     \rb, #0x50000000
-               add     \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
+               add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
                .endm
 #else
                .macro  loadsp, rb
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
new file mode 100644 (file)
index 0000000..6bea090
--- /dev/null
@@ -0,0 +1,1265 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22
+# Mon Jul  9 15:18:20 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION="-em-x270"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Intel PXA2xx Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+CONFIG_MACH_EM_X270=y
+CONFIG_PXA27x=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_LEGACY=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_PM_SYSFS_DEPRECATED is not set
+CONFIG_APM_EMULATION=m
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+# CONFIG_BT_HCIUSB_SCO is not set
+CONFIG_BT_HCIUART=m
+# CONFIG_BT_HCIUART_H4 is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_H1900 is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_SHARPSL is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=12000
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+# CONFIG_SMC911X is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=m
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+
+#
+# Misc devices
+#
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_AC97=m
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=m
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+CONFIG_RTC_DRV_V3020=m
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=m
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=y
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
index 1d5150e4d6b3e97cd568e33e21bc1229e45407ad..f8a1645b3d4affd925eb2dfaaf85cd1d1db995a4 100644 (file)
@@ -138,11 +138,11 @@ CONFIG_ARCH_S3C2410=y
 CONFIG_PLAT_S3C24XX=y
 CONFIG_CPU_S3C244X=y
 CONFIG_PM_SIMTEC=y
-# CONFIG_S3C2410_BOOT_WATCHDOG is not set
-# CONFIG_S3C2410_BOOT_ERROR_RESET is not set
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
 # CONFIG_S3C2410_PM_DEBUG is not set
 # CONFIG_S3C2410_PM_CHECK is not set
-CONFIG_S3C2410_LOWLEVEL_UART_PORT=0
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
 CONFIG_S3C2410_DMA=y
 # CONFIG_S3C2410_DMA_DEBUG is not set
 CONFIG_MACH_SMDK=y
@@ -1392,8 +1392,8 @@ CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
-CONFIG_DEBUG_S3C2410_PORT=y
-CONFIG_DEBUG_S3C2410_UART=0
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=0
 
 #
 # Security options
index 70599bcf451cf9c64000f71f2af29a6f849db02a..0417c165d50d0a8e732b60b5ad767cddbe757851 100644 (file)
@@ -477,7 +477,7 @@ void __init at91_add_device_i2c(void) {}
  *  SPI
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 static u64 spi_dmamask = 0xffffffffUL;
 
 static struct resource spi_resources[] = {
@@ -494,7 +494,7 @@ static struct resource spi_resources[] = {
 };
 
 static struct platform_device at91rm9200_spi_device = {
-       .name           = "at91_spi",
+       .name           = "atmel_spi",
        .id             = 0,
        .dev            = {
                                .dma_mask               = &spi_dmamask,
@@ -522,18 +522,14 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                else
                        cs_pin = spi_standard_cs[devices[i].chip_select];
 
-#ifdef CONFIG_SPI_AT91_MANUAL_CS
+               /* enable chip-select pin */
                at91_set_gpio_output(cs_pin, 1);
-#else
-               at91_set_A_periph(cs_pin, 0);
-#endif
 
                /* pass chip-select pin to driver */
                devices[i].controller_data = (void *) cs_pin;
        }
 
        spi_register_board_info(devices, nr_devices);
-       at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
        platform_device_register(&at91rm9200_spi_device);
 }
 #else
index 9bb02b6d7ae1622fbfb002fedc98bdfb9f1857fc..dbe07c9472edcc41130d0ba0a523cdf3e8e31fac 100644 (file)
@@ -42,6 +42,13 @@ config IOP3XX_ATU
           Say N if the IOP is an add in card, the host system owns the PCI
           bus in this case.
 
+config MACH_EM7210
+       bool "Enable support for the Lanner EM7210"
+       help
+         Say Y here if you want to run your kernel on the Lanner EM7210
+         board. Say also Y here if you have a SS4000e Baxter Creek NAS
+         appliance."
+
 endmenu
 
 endif
index 7b05b37e1f94c5ea6d4b49f1e8e9786990864473..cfdf8a137c2b9f8911771d87859b0edb4934019b 100644 (file)
@@ -11,3 +11,4 @@ obj-$(CONFIG_MACH_GLANTANK) += glantank.o
 obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
 obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
 obj-$(CONFIG_MACH_N2100) += n2100.o
+obj-$(CONFIG_MACH_EM7210) += em7210.o
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
new file mode 100644 (file)
index 0000000..c947152
--- /dev/null
@@ -0,0 +1,215 @@
+/*
+ * arch/arm/mach-iop32x/em7210.c
+ *
+ * Board support code for the Lanner EM7210 platforms.
+ *
+ * Based on arch/arm/mach-iop32x/iq31244.c file.
+ *
+ * Copyright (C) 2007 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/pm.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <asm/hardware.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
+#include <asm/arch/time.h>
+
+static void __init em7210_timer_init(void)
+{
+       /* http://www.kwaak.net/fotos/fotos-nas/slide_24.html */
+       /* 33.333 MHz crystal.                                */
+       iop_init_time(200000000);
+}
+
+static struct sys_timer em7210_timer = {
+       .init           = em7210_timer_init,
+       .offset         = iop_gettimeoffset,
+};
+
+/*
+ * EM7210 RTC
+ */
+static struct i2c_board_info __initdata em7210_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+               .type = "rs5c372a",
+       },
+};
+
+/*
+ * EM7210 I/O
+ */
+static struct map_desc em7210_io_desc[] __initdata = {
+       {       /* on-board devices */
+               .virtual        = IQ31244_UART,
+               .pfn            = __phys_to_pfn(IQ31244_UART),
+               .length         = 0x00100000,
+               .type           = MT_DEVICE,
+       },
+};
+
+void __init em7210_map_io(void)
+{
+       iop3xx_map_io();
+       iotable_init(em7210_io_desc, ARRAY_SIZE(em7210_io_desc));
+}
+
+
+/*
+ * EM7210 PCI
+ */
+#define INTA   IRQ_IOP32X_XINT0
+#define INTB   IRQ_IOP32X_XINT1
+#define INTC   IRQ_IOP32X_XINT2
+#define INTD   IRQ_IOP32X_XINT3
+
+static int __init
+em7210_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+       static int pci_irq_table[][4] = {
+               /*
+                * PCI IDSEL/INTPIN->INTLINE
+                * A       B       C       D
+                */
+               {INTB, INTB, INTB, INTB}, /* console / uart */
+               {INTA, INTA, INTA, INTA}, /* 1st 82541      */
+               {INTD, INTD, INTD, INTD}, /* 2nd 82541      */
+               {INTC, INTC, INTC, INTC}, /* GD31244        */
+               {INTD, INTA, INTA, INTA}, /* mini-PCI       */
+               {INTD, INTC, INTA, INTA}, /* NEC USB        */
+       };
+
+       if (pin < 1 || pin > 4)
+               return -1;
+
+       return pci_irq_table[slot % 6][pin - 1];
+}
+
+static struct hw_pci em7210_pci __initdata = {
+       .swizzle        = pci_std_swizzle,
+       .nr_controllers = 1,
+       .setup          = iop3xx_pci_setup,
+       .preinit        = iop3xx_pci_preinit,
+       .scan           = iop3xx_pci_scan_bus,
+       .map_irq        = em7210_pci_map_irq,
+};
+
+static int __init em7210_pci_init(void)
+{
+       if (machine_is_em7210())
+               pci_common_init(&em7210_pci);
+
+       return 0;
+}
+
+subsys_initcall(em7210_pci_init);
+
+
+/*
+ * EM7210 Flash
+ */
+static struct physmap_flash_data em7210_flash_data = {
+       .width          = 2,
+};
+
+static struct resource em7210_flash_resource = {
+       .start          = 0xf0000000,
+       .end            = 0xf1ffffff,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device em7210_flash_device = {
+       .name           = "physmap-flash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &em7210_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &em7210_flash_resource,
+};
+
+
+/*
+ * EM7210 UART
+ * The physical address of the serial port is 0xfe800000,
+ * so it can be used for physical and virtual address.
+ */
+static struct plat_serial8250_port em7210_serial_port[] = {
+       {
+               .mapbase        = IQ31244_UART,
+               .membase        = (char *)IQ31244_UART,
+               .irq            = IRQ_IOP32X_XINT1,
+               .flags          = UPF_SKIP_TEST,
+               .iotype         = UPIO_MEM,
+               .regshift       = 0,
+               .uartclk        = 1843200,
+       },
+       { },
+};
+
+static struct resource em7210_uart_resource = {
+       .start          = IQ31244_UART,
+       .end            = IQ31244_UART + 7,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device em7210_serial_device = {
+       .name           = "serial8250",
+       .id             = PLAT8250_DEV_PLATFORM,
+       .dev            = {
+               .platform_data          = em7210_serial_port,
+       },
+       .num_resources  = 1,
+       .resource       = &em7210_uart_resource,
+};
+
+void em7210_power_off(void)
+{
+       *IOP3XX_GPOE &= 0xfe;
+       *IOP3XX_GPOD |= 0x01;
+}
+
+static void __init em7210_init_machine(void)
+{
+       platform_device_register(&em7210_serial_device);
+       platform_device_register(&iop3xx_i2c0_device);
+       platform_device_register(&iop3xx_i2c1_device);
+       platform_device_register(&em7210_flash_device);
+       platform_device_register(&iop3xx_dma_0_channel);
+       platform_device_register(&iop3xx_dma_1_channel);
+
+       i2c_register_board_info(0, em7210_i2c_devices,
+               ARRAY_SIZE(em7210_i2c_devices));
+
+
+       pm_power_off = em7210_power_off;
+}
+
+MACHINE_START(EM7210, "Lanner EM7210")
+       .phys_io        = IQ31244_UART,
+       .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
+       .boot_params    = 0xa0000100,
+       .map_io         = em7210_map_io,
+       .init_irq       = iop32x_init_irq,
+       .timer          = &em7210_timer,
+       .init_machine   = em7210_init_machine,
+MACHINE_END
index c971171c2905a359bc06a4d32280a859ae1bfeca..55cf0162e8c1acca575ca0b46d82db8774b61dbb 100644 (file)
@@ -63,7 +63,8 @@ void __init iop32x_init_irq(void)
        if (machine_is_glantank() ||
            machine_is_iq80321() ||
            machine_is_iq31244() ||
-           machine_is_n2100())
+           machine_is_n2100() ||
+           machine_is_em7210())
                *IOP3XX_PCIIRSR = 0x0f;
 
        for (i = 0; i < NR_IRQS; i++) {
index 23e7fba6d3e1ff31131854fcec2bec97a8c9a983..c1271c449246ecf743d6bdce0e77e052ad1e74a1 100644 (file)
@@ -188,7 +188,7 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
        *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 
        /* Configure the line as an input */
-       gpio_line_config(line, IXP4XX_GPIO_IN);
+       gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
 
        return 0;
 }
index 2407bba00547bb9b8c338955ab113016c6a60d98..4c3ab43e1046b5f36ecd9c27447b31d33e05003a 100644 (file)
@@ -23,7 +23,6 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/ptrace.h>
 #include <linux/sysdev.h>
 
 #include <asm/hardware.h>
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
new file mode 100644 (file)
index 0000000..5fe8606
--- /dev/null
@@ -0,0 +1,12 @@
+menu "MX3 Options"
+       depends on ARCH_MX3
+
+config MACH_MX31ADS
+       bool "Support MX31ADS platforms"
+       default y
+       help
+         Include support for MX31ADS platform. This includes specific
+         configurations for the board and its peripherals.
+
+endmenu
+
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
new file mode 100644 (file)
index 0000000..cbec997
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y                  := mm.o time.o
+obj-$(CONFIG_MACH_MX31ADS)     += mx31ads.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
new file mode 100644 (file)
index 0000000..e1dd366
--- /dev/null
@@ -0,0 +1,3 @@
+   zreladdr-y  := 0x80008000
+params_phys-y  := 0x80000100
+initrd_phys-y  := 0x80800000
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
new file mode 100644 (file)
index 0000000..41dad48
--- /dev/null
@@ -0,0 +1,64 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+
+/*!
+ * @file mm.c
+ *
+ * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
+ *
+ * @ingroup Memory
+ */
+
+/*!
+ * This table defines static virtual address mappings for I/O regions.
+ * These are the mappings common across all MX3 boards.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+       {
+               .virtual        = X_MEMC_BASE_ADDR_VIRT,
+               .pfn            = __phys_to_pfn(X_MEMC_BASE_ADDR),
+               .length         = X_MEMC_SIZE,
+               .type           = MT_DEVICE
+       }, {
+               .virtual        = AVIC_BASE_ADDR_VIRT,
+               .pfn            = __phys_to_pfn(AVIC_BASE_ADDR),
+               .length         = AVIC_SIZE,
+               .type           = MT_NONSHARED_DEVICE
+       },
+};
+
+/*!
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mxc_map_io(void)
+{
+       iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
new file mode 100644 (file)
index 0000000..7e89bdc
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+
+/*!
+ * @file mx31ads.c
+ *
+ * @brief This file contains the board-specific initialization routines.
+ *
+ * @ingroup System
+ */
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*!
+ * The serial port definition structure.
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+       {
+               .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
+               .mapbase  = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
+               .irq      = EXPIO_INT_XUART_INTA,
+               .uartclk  = 14745600,
+               .regshift = 0,
+               .iotype   = UPIO_MEM,
+               .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+       }, {
+               .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
+               .mapbase  = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
+               .irq      = EXPIO_INT_XUART_INTB,
+               .uartclk  = 14745600,
+               .regshift = 0,
+               .iotype   = UPIO_MEM,
+               .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+       },
+       {},
+};
+
+static struct platform_device serial_device = {
+       .name   = "serial8250",
+       .id     = 0,
+       .dev    = {
+               .platform_data = serial_platform_data,
+       },
+};
+
+static int __init mxc_init_extuart(void)
+{
+       return platform_device_register(&serial_device);
+}
+#else
+static inline int mxc_init_extuart(void)
+{
+       return 0;
+}
+#endif
+
+/*!
+ * This structure defines static mappings for the i.MX31ADS board.
+ */
+static struct map_desc mx31ads_io_desc[] __initdata = {
+       {
+               .virtual        = AIPS1_BASE_ADDR_VIRT,
+               .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
+               .length         = AIPS1_SIZE,
+               .type           = MT_NONSHARED_DEVICE
+       }, {
+               .virtual        = SPBA0_BASE_ADDR_VIRT,
+               .pfn            = __phys_to_pfn(SPBA0_BASE_ADDR),
+               .length         = SPBA0_SIZE,
+               .type           = MT_NONSHARED_DEVICE
+       }, {
+               .virtual        = AIPS2_BASE_ADDR_VIRT,
+               .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
+               .length         = AIPS2_SIZE,
+               .type           = MT_NONSHARED_DEVICE
+       }, {
+               .virtual        = CS4_BASE_ADDR_VIRT,
+               .pfn            = __phys_to_pfn(CS4_BASE_ADDR),
+               .length         = CS4_SIZE / 2,
+               .type           = MT_DEVICE
+       },
+};
+
+/*!
+ * Set up static virtual mappings.
+ */
+void __init mx31ads_map_io(void)
+{
+       mxc_map_io();
+       iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
+}
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+       mxc_init_extuart();
+}
+
+/*
+ * The following uses standard kernel macros defined in arch.h in order to
+ * initialize __mach_desc_MX31ADS data structure.
+ */
+MACHINE_START(MX31ADS, "Freescale MX31ADS")
+       /* Maintainer: Freescale Semiconductor, Inc. */
+       .phys_io        = AIPS1_BASE_ADDR,
+       .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+       .boot_params    = PHYS_OFFSET + 0x100,
+       .map_io         = mx31ads_map_io,
+       .init_irq       = mxc_init_irq,
+       .init_machine   = mxc_board_init,
+       .timer          = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c
new file mode 100644 (file)
index 0000000..e81fb5c
--- /dev/null
@@ -0,0 +1,152 @@
+/*
+ * System Timer Interrupt reconfigured to run in free-run mode.
+ * Author: Vitaly Wool
+ * Copyright 2004 MontaVista Software Inc.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file time.c
+ * @brief This file contains OS tick and wdog timer implementations.
+ *
+ * This file contains OS tick and wdog timer implementations.
+ *
+ * @ingroup Timers
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach/time.h>
+#include <asm/io.h>
+#include <asm/arch/common.h>
+
+/*!
+ * This is the timer interrupt service routine to do required tasks.
+ * It also services the WDOG timer at the frequency of twice per WDOG
+ * timeout value. For example, if the WDOG's timeout value is 4 (2
+ * seconds since the WDOG runs at 0.5Hz), it will be serviced once
+ * every 2/2=1 second.
+ *
+ * @param  irq          GPT interrupt source number (not used)
+ * @param  dev_id       this parameter is not used
+ * @return always returns \b IRQ_HANDLED as defined in
+ *         include/linux/interrupt.h.
+ */
+static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
+{
+       unsigned int next_match;
+
+       write_seqlock(&xtime_lock);
+
+       if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
+               do {
+                       timer_tick();
+                       next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
+                       __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
+                       __raw_writel(next_match, MXC_GPT_GPTOCR1);
+               } while ((signed long)(next_match -
+                                      __raw_readl(MXC_GPT_GPTCNT)) <= 0);
+       }
+
+       write_sequnlock(&xtime_lock);
+
+       return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to obtain the number of microseconds since the last
+ * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
+ *
+ * @return the number of microseconds since the last timer interrupt.
+ */
+static unsigned long mxc_gettimeoffset(void)
+{
+       unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
+
+       /* Get ticks before next timer match */
+       ticks_to_match =
+           __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
+
+       /* We need elapsed ticks since last match */
+       elapsed = LATCH - ticks_to_match;
+
+       /* Now convert them to usec */
+       /* Insure no overflow when calculating the usec below */
+       for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
+               tick_usec /= i;
+               if ((0xFFFFFFFF / tick_usec) > elapsed)
+                       break;
+       }
+       usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
+
+       return usec;
+}
+
+/*!
+ * The OS tick timer interrupt structure.
+ */
+static struct irqaction timer_irq = {
+       .name = "MXC Timer Tick",
+       .flags = IRQF_DISABLED | IRQF_TIMER,
+       .handler = mxc_timer_interrupt
+};
+
+/*!
+ * This function is used to initialize the GPT to produce an interrupt
+ * based on HZ.  It is called by start_kernel() during system startup.
+ */
+void __init mxc_init_time(void)
+{
+       u32 reg, v;
+       reg = __raw_readl(MXC_GPT_GPTCR);
+       reg &= ~GPTCR_ENABLE;
+       __raw_writel(reg, MXC_GPT_GPTCR);
+       reg |= GPTCR_SWR;
+       __raw_writel(reg, MXC_GPT_GPTCR);
+
+       while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
+               cpu_relax();
+
+       reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
+       __raw_writel(reg, MXC_GPT_GPTCR);
+
+       /* TODO: get timer rate from clk driver */
+       v = 66500000;
+
+       __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
+
+       if ((v % CLOCK_TICK_RATE) != 0) {
+               pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
+                       CLOCK_TICK_RATE);
+       }
+       pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
+               v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
+
+       reg = __raw_readl(MXC_GPT_GPTCNT);
+       reg += LATCH;
+       __raw_writel(reg, MXC_GPT_GPTOCR1);
+
+       setup_irq(MXC_INT_GPT, &timer_irq);
+
+       reg = __raw_readl(MXC_GPT_GPTCR);
+       reg =
+           GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
+           GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
+       __raw_writel(reg, MXC_GPT_GPTCR);
+
+       __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
+}
+
+struct sys_timer mxc_timer = {
+       .init = mxc_init_time,
+       .offset = mxc_gettimeoffset,
+};
index 53213a69f601593e37dd5366280e4872b8ccbbb1..4476411b81408704f9d430e51715d1232f95c2d5 100644 (file)
@@ -1,6 +1,7 @@
 obj-y := irq.o time.o generic.o
 
 obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
+obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
 
 obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
 obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
index 25289884a6079d45a4df8b7ae7461865e251bde4..925048e7adfe9c9d048a14cb9914562e8e11cc49 100644 (file)
@@ -77,7 +77,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
 
                desc = irq_desc + FPGA_IRQ(irqno);
 
-               desc_handle_irq(irqno, desc);
+               desc_handle_irq(FPGA_IRQ(irqno), desc);
        }
 }
 
@@ -91,7 +91,7 @@ void __init board_a9m9750dev_init_irq(void)
         * use GPIO 11, because GPIO 32 is used for the LCD
         */
        /* XXX: proper GPIO handling */
-       BBU_GC(2) &= ~0x2000;
+       BBU_GCONFb1(1) &= ~0x2000;
 
        for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
                set_irq_chip(i, &a9m9750dev_fpga_chip);
@@ -178,7 +178,7 @@ void __init board_a9m9750dev_init_machine(void)
 
        /* setup static CS0: memory configuration */
        reg = MEM_SMC(0);
-       REGSET(reg, MEM_SMC, WSMC, OFF);
+       REGSET(reg, MEM_SMC, PSMC, OFF);
        REGSET(reg, MEM_SMC, BSMC, OFF);
        REGSET(reg, MEM_SMC, EW, OFF);
        REGSET(reg, MEM_SMC, PB, 1);
@@ -196,4 +196,3 @@ void __init board_a9m9750dev_init_machine(void)
        platform_add_devices(board_a9m9750dev_devices,
                        ARRAY_SIZE(board_a9m9750dev_devices));
 }
-
index 83e2b6532b2243749d1c02e60dcdac28e1ae6334..d742c921e34dabb42ed10948c32599c4d12dcedb 100644 (file)
@@ -18,6 +18,8 @@
 #include <asm/arch-ns9xxx/regs-mem.h>
 #include <asm/arch-ns9xxx/board.h>
 
+#include "generic.h"
+
 static struct map_desc standard_io_desc[] __initdata = {
        { /* BBus */
                .virtual = io_p2v(0x90000000),
index 83d92724a971cb383c7141968148ddcccf3a9119..b8c7b00522e677d0ee8d5f0ebc72faa1a7ed9a98 100644 (file)
@@ -21,6 +21,15 @@ static void ns9xxx_ack_irq_timer(unsigned int irq)
 {
        u32 tc = SYS_TC(irq - IRQ_TIMER0);
 
+       /*
+        * If the timer is programmed to halt on terminal count, the
+        * timer must be disabled before clearing the interrupt.
+        */
+       if (REGGET(tc, SYS_TCx, REN) == 0) {
+               REGSET(tc, SYS_TCx, TEN, DIS);
+               SYS_TC(irq - IRQ_TIMER0) = tc;
+       }
+
        REGSET(tc, SYS_TCx, INTC, SET);
        SYS_TC(irq - IRQ_TIMER0) = tc;
 
@@ -28,7 +37,7 @@ static void ns9xxx_ack_irq_timer(unsigned int irq)
        SYS_TC(irq - IRQ_TIMER0) = tc;
 }
 
-void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = {
+static void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = {
        [IRQ_TIMER0] = ns9xxx_ack_irq_timer,
        [IRQ_TIMER1] = ns9xxx_ack_irq_timer,
        [IRQ_TIMER2] = ns9xxx_ack_irq_timer,
index d09d5fa5620a4df9b6767baa1e54f6531150ee20..85c8b41105c915818d430ba52c0654817f3fb167 100644 (file)
@@ -20,7 +20,7 @@ static void __init mach_cc9p9360js_init_machine(void)
        board_jscc9p9360_init_machine();
 }
 
-MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
+MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
        .map_io = ns9xxx_map_io,
        .init_irq = ns9xxx_init_irq,
        .init_machine = mach_cc9p9360js_init_machine,
index 5c0a10041cd17c1fc7c9ae97a442d266b4dd8c05..5ebec6d88b5161d0ec3c5d05076a6ff21389d664 100644 (file)
@@ -37,6 +37,10 @@ config MACH_TRIZEPS4
        bool "Keith und Koep Trizeps4 DIMM-Module"
        select PXA27x
 
+config MACH_EM_X270
+       bool "CompuLab EM-x270 platform"
+       select PXA27x
+
 endchoice
 
 if PXA_SHARPSL
index 9093eb1c94ebdfae3a94611a1d586c493ad01d9a..7d6ab5c59ab9757829cd72849d229265ca2cc0d7 100644 (file)
@@ -18,6 +18,7 @@ obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o sp
 obj-$(CONFIG_MACH_AKITA)       += akita-ioexp.o
 obj-$(CONFIG_MACH_POODLE)      += poodle.o corgi_ssp.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
+obj-$(CONFIG_MACH_EM_X270) += em-x270.o
 
 # Support for blinky lights
 led-y := leds.o
index 9a6faff8e5a71f17a4097ced0536e7798f43f91d..636fdb1c049cd6bfac477d203753f09b8aa75e6f 100644 (file)
@@ -1,11 +1,11 @@
-extern struct platform_device pxamci_device;
-extern struct platform_device pxaudc_device;
-extern struct platform_device pxafb_device;
-extern struct platform_device ffuart_device;
-extern struct platform_device btuart_device;
-extern struct platform_device stuart_device;
-extern struct platform_device hwuart_device;
-extern struct platform_device pxai2c_device;
-extern struct platform_device pxai2s_device;
-extern struct platform_device pxaficp_device;
-extern struct platform_device pxartc_device;
+extern struct platform_device pxa_device_mci;
+extern struct platform_device pxa_device_udc;
+extern struct platform_device pxa_device_fb;
+extern struct platform_device pxa_device_ffuart;
+extern struct platform_device pxa_device_btuart;
+extern struct platform_device pxa_device_stuart;
+extern struct platform_device pxa_device_hwuart;
+extern struct platform_device pxa_device_i2c;
+extern struct platform_device pxa_device_i2s;
+extern struct platform_device pxa_device_ficp;
+extern struct platform_device pxa_device_rtc;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
new file mode 100644 (file)
index 0000000..3d0ad50
--- /dev/null
@@ -0,0 +1,354 @@
+/*
+ * Support for CompuLab EM-x270 platform
+ *
+ * Copyright (C) 2007 CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <linux/dm9000.h>
+#include <linux/rtc-v3020.h>
+
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxafb.h>
+#include <asm/arch/ohci.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/bitfield.h>
+
+#include "generic.h"
+
+/* GPIO IRQ usage */
+#define EM_X270_MMC_PD         (105)
+#define EM_X270_ETHIRQ         IRQ_GPIO(41)
+#define EM_X270_MMC_IRQ                IRQ_GPIO(13)
+
+static struct resource em_x270_dm9k_resource[] = {
+       [0] = {
+               .start = PXA_CS2_PHYS,
+               .end   = PXA_CS2_PHYS + 3,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = PXA_CS2_PHYS + 8,
+               .end   = PXA_CS2_PHYS + 8 + 0x3f,
+               .flags = IORESOURCE_MEM,
+       },
+       [2] = {
+               .start = EM_X270_ETHIRQ,
+               .end   = EM_X270_ETHIRQ,
+               .flags = IORESOURCE_IRQ,
+       }
+};
+
+/* for the moment we limit ourselves to 32bit IO until some
+ * better IO routines can be written and tested
+ */
+static struct dm9000_plat_data em_x270_dm9k_platdata = {
+       .flags          = DM9000_PLATF_32BITONLY,
+};
+
+/* Ethernet device */
+static struct platform_device em_x270_dm9k = {
+       .name           = "dm9000",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(em_x270_dm9k_resource),
+       .resource       = em_x270_dm9k_resource,
+       .dev            = {
+               .platform_data = &em_x270_dm9k_platdata,
+       }
+};
+
+/* audio device */
+static struct platform_device em_x270_audio = {
+       .name           = "pxa2xx-ac97",
+       .id             = -1,
+};
+
+/* WM9712 touchscreen controller. Hopefully the driver will make it to
+ * the mainstream sometime */
+static struct platform_device em_x270_ts = {
+       .name           = "wm97xx-ts",
+       .id             = -1,
+};
+
+/* RTC */
+static struct resource em_x270_v3020_resource[] = {
+       [0] = {
+               .start = PXA_CS4_PHYS,
+               .end   = PXA_CS4_PHYS + 3,
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+static struct v3020_platform_data em_x270_v3020_platdata = {
+       .leftshift = 0,
+};
+
+static struct platform_device em_x270_rtc = {
+       .name           = "v3020",
+       .num_resources  = ARRAY_SIZE(em_x270_v3020_resource),
+       .resource       = em_x270_v3020_resource,
+       .id             = -1,
+       .dev            = {
+               .platform_data = &em_x270_v3020_platdata,
+       }
+};
+
+/* NAND flash */
+#define GPIO_NAND_CS   (11)
+#define GPIO_NAND_RB   (56)
+
+static inline void nand_cs_on(void)
+{
+       GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
+}
+
+static void nand_cs_off(void)
+{
+       dsb();
+
+       GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
+}
+
+/* hardware specific access to control-lines */
+static void em_x270_nand_cmd_ctl(struct mtd_info *mtd, int dat,
+                                unsigned int ctrl)
+{
+       struct nand_chip *this = mtd->priv;
+       unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
+
+       dsb();
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               if (ctrl & NAND_ALE)
+                       nandaddr |=  (1 << 3);
+               else
+                       nandaddr &= ~(1 << 3);
+               if (ctrl & NAND_CLE)
+                       nandaddr |=  (1 << 2);
+               else
+                       nandaddr &= ~(1 << 2);
+               if (ctrl & NAND_NCE)
+                       nand_cs_on();
+               else
+                       nand_cs_off();
+       }
+
+       dsb();
+       this->IO_ADDR_W = (void __iomem *)nandaddr;
+       if (dat != NAND_CMD_NONE)
+               writel(dat, this->IO_ADDR_W);
+
+       dsb();
+}
+
+/* read device ready pin */
+static int em_x270_nand_device_ready(struct mtd_info *mtd)
+{
+       dsb();
+
+       return GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB);
+}
+
+static struct mtd_partition em_x270_partition_info[] = {
+       [0] = {
+               .name   = "em_x270-0",
+               .offset = 0,
+               .size   = SZ_4M,
+       },
+       [1] = {
+               .name   = "em_x270-1",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = MTDPART_SIZ_FULL
+       },
+};
+
+static const char *em_x270_part_probes[] = { "cmdlinepart", NULL };
+
+struct platform_nand_data em_x270_nand_platdata = {
+       .chip = {
+               .nr_chips = 1,
+               .chip_offset = 0,
+               .nr_partitions = ARRAY_SIZE(em_x270_partition_info),
+               .partitions = em_x270_partition_info,
+               .chip_delay = 20,
+               .part_probe_types = em_x270_part_probes,
+       },
+       .ctrl = {
+               .hwcontrol = 0,
+               .dev_ready = em_x270_nand_device_ready,
+               .select_chip = 0,
+               .cmd_ctrl = em_x270_nand_cmd_ctl,
+       },
+};
+
+static struct resource em_x270_nand_resource[] = {
+       [0] = {
+               .start = PXA_CS1_PHYS,
+               .end   = PXA_CS1_PHYS + 12,
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device em_x270_nand = {
+       .name           = "gen_nand",
+       .num_resources  = ARRAY_SIZE(em_x270_nand_resource),
+       .resource       = em_x270_nand_resource,
+       .id             = -1,
+       .dev            = {
+               .platform_data = &em_x270_nand_platdata,
+       }
+};
+
+/* platform devices */
+static struct platform_device *platform_devices[] __initdata = {
+       &em_x270_dm9k,
+       &em_x270_audio,
+       &em_x270_ts,
+       &em_x270_rtc,
+       &em_x270_nand,
+};
+
+
+/* PXA27x OHCI controller setup */
+static int em_x270_ohci_init(struct device *dev)
+{
+       /* Set the Power Control Polarity Low */
+       UHCHR = (UHCHR | UHCHR_PCPL) &
+               ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+       /* enable port 2 transiever */
+       UP2OCR = UP2OCR_HXS | UP2OCR_HXOE;
+
+       return 0;
+}
+
+static struct pxaohci_platform_data em_x270_ohci_platform_data = {
+       .port_mode      = PMM_PERPORT_MODE,
+       .init           = em_x270_ohci_init,
+};
+
+
+static int em_x270_mci_init(struct device *dev,
+                           irq_handler_t em_x270_detect_int,
+                           void *data)
+{
+       int err;
+
+       /* setup GPIO for PXA27x MMC controller */
+       pxa_gpio_mode(GPIO32_MMCCLK_MD);
+       pxa_gpio_mode(GPIO112_MMCCMD_MD);
+       pxa_gpio_mode(GPIO92_MMCDAT0_MD);
+       pxa_gpio_mode(GPIO109_MMCDAT1_MD);
+       pxa_gpio_mode(GPIO110_MMCDAT2_MD);
+       pxa_gpio_mode(GPIO111_MMCDAT3_MD);
+
+       /* EM-X270 uses GPIO13 as SD power enable */
+       pxa_gpio_mode(EM_X270_MMC_PD | GPIO_OUT);
+
+       err = request_irq(EM_X270_MMC_IRQ, em_x270_detect_int,
+                         IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                         "MMC card detect", data);
+       if (err) {
+               printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n",
+                      __FUNCTION__, err);
+               return err;
+       }
+
+       return 0;
+}
+
+static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
+{
+       /*
+          FIXME: current hardware implementation does not allow to
+          enable/disable MMC power. This will be fixed in next HW releases,
+          and we'll need to add implmentation here.
+       */
+       return;
+}
+
+static void em_x270_mci_exit(struct device *dev, void *data)
+{
+       free_irq(EM_X270_MMC_IRQ, data);
+}
+
+static struct pxamci_platform_data em_x270_mci_platform_data = {
+       .ocr_mask       = MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31,
+       .init           = em_x270_mci_init,
+       .setpower       = em_x270_mci_setpower,
+       .exit           = em_x270_mci_exit,
+};
+
+/* LCD 480x640 */
+static struct pxafb_mode_info em_x270_lcd_mode = {
+       .pixclock       = 50000,
+       .bpp            = 16,
+       .xres           = 480,
+       .yres           = 640,
+       .hsync_len      = 8,
+       .vsync_len      = 2,
+       .left_margin    = 8,
+       .upper_margin   = 0,
+       .right_margin   = 24,
+       .lower_margin   = 4,
+       .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info em_x270_lcd = {
+       .modes          = &em_x270_lcd_mode,
+       .num_modes      = 1,
+       .cmap_inverse   = 0,
+       .cmap_static    = 0,
+       .lccr0          = LCCR0_PAS,
+       .lccr3          = LCCR3_PixClkDiv(0x01) | LCCR3_Acb(0xff),
+};
+
+static void __init em_x270_init(void)
+{
+       /* setup LCD */
+       set_pxa_fb_info(&em_x270_lcd);
+
+       /* register EM-X270 platform devices */
+       platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+       /* set MCI and OHCI platform parameters */
+       pxa_set_mci_info(&em_x270_mci_platform_data);
+       pxa_set_ohci_info(&em_x270_ohci_platform_data);
+
+       /* setup STUART GPIOs */
+       pxa_gpio_mode(GPIO46_STRXD_MD);
+       pxa_gpio_mode(GPIO47_STTXD_MD);
+
+       /* setup BTUART GPIOs */
+       pxa_gpio_mode(GPIO42_BTRXD_MD);
+       pxa_gpio_mode(GPIO43_BTTXD_MD);
+       pxa_gpio_mode(GPIO44_BTCTS_MD);
+       pxa_gpio_mode(GPIO45_BTRTS_MD);
+
+       /* Setup interrupt for dm9000 */
+       set_irq_type(EM_X270_ETHIRQ, IRQT_RISING);
+}
+
+MACHINE_START(EM_X270, "Compulab EM-x270")
+       .boot_params    = 0xa0000100,
+       .phys_io        = 0x40000000,
+       .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+       .map_io         = pxa_map_io,
+       .init_irq       = pxa27x_init_irq,
+       .timer          = &pxa_timer,
+       .init_machine   = em_x270_init,
+MACHINE_END
index 296539b6359ca43af779f59e5fa078351c14195b..5510f6fdce55e4dc8b2f55f93359e1b245da619a 100644 (file)
@@ -243,7 +243,7 @@ static struct resource pxamci_resources[] = {
 
 static u64 pxamci_dmamask = 0xffffffffUL;
 
-struct platform_device pxamci_device = {
+struct platform_device pxa_device_mci = {
        .name           = "pxa2xx-mci",
        .id             = -1,
        .dev            = {
@@ -256,7 +256,7 @@ struct platform_device pxamci_device = {
 
 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
 {
-       pxamci_device.dev.platform_data = info;
+       pxa_device_mci.dev.platform_data = info;
 }
 
 
@@ -282,7 +282,7 @@ static struct resource pxa2xx_udc_resources[] = {
 
 static u64 udc_dma_mask = ~(u32)0;
 
-struct platform_device pxaudc_device = {
+struct platform_device pxa_device_udc = {
        .name           = "pxa2xx-udc",
        .id             = -1,
        .resource       = pxa2xx_udc_resources,
@@ -308,7 +308,7 @@ static struct resource pxafb_resources[] = {
 
 static u64 fb_dma_mask = ~(u64)0;
 
-struct platform_device pxafb_device = {
+struct platform_device pxa_device_fb = {
        .name           = "pxa2xx-fb",
        .id             = -1,
        .dev            = {
@@ -321,27 +321,27 @@ struct platform_device pxafb_device = {
 
 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
 {
-       pxafb_device.dev.platform_data = info;
+       pxa_device_fb.dev.platform_data = info;
 }
 
 void __init set_pxa_fb_parent(struct device *parent_dev)
 {
-       pxafb_device.dev.parent = parent_dev;
+       pxa_device_fb.dev.parent = parent_dev;
 }
 
-struct platform_device ffuart_device = {
+struct platform_device pxa_device_ffuart= {
        .name           = "pxa2xx-uart",
        .id             = 0,
 };
-struct platform_device btuart_device = {
+struct platform_device pxa_device_btuart = {
        .name           = "pxa2xx-uart",
        .id             = 1,
 };
-struct platform_device stuart_device = {
+struct platform_device pxa_device_stuart = {
        .name           = "pxa2xx-uart",
        .id             = 2,
 };
-struct platform_device hwuart_device = {
+struct platform_device pxa_device_hwuart = {
        .name           = "pxa2xx-uart",
        .id             = 3,
 };
@@ -358,7 +358,7 @@ static struct resource pxai2c_resources[] = {
        },
 };
 
-struct platform_device pxai2c_device = {
+struct platform_device pxa_device_i2c = {
        .name           = "pxa2xx-i2c",
        .id             = 0,
        .resource       = pxai2c_resources,
@@ -367,7 +367,7 @@ struct platform_device pxai2c_device = {
 
 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
 {
-       pxai2c_device.dev.platform_data = info;
+       pxa_device_i2c.dev.platform_data = info;
 }
 
 static struct resource pxai2s_resources[] = {
@@ -382,7 +382,7 @@ static struct resource pxai2s_resources[] = {
        },
 };
 
-struct platform_device pxai2s_device = {
+struct platform_device pxa_device_i2s = {
        .name           = "pxa2xx-i2s",
        .id             = -1,
        .resource       = pxai2s_resources,
@@ -391,7 +391,7 @@ struct platform_device pxai2s_device = {
 
 static u64 pxaficp_dmamask = ~(u32)0;
 
-struct platform_device pxaficp_device = {
+struct platform_device pxa_device_ficp = {
        .name           = "pxa2xx-ir",
        .id             = -1,
        .dev            = {
@@ -402,10 +402,10 @@ struct platform_device pxaficp_device = {
 
 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
 {
-       pxaficp_device.dev.platform_data = info;
+       pxa_device_ficp.dev.platform_data = info;
 }
 
-struct platform_device pxartc_device = {
+struct platform_device pxa_device_rtc = {
        .name           = "sa1100-rtc",
        .id             = -1,
 };
index e66dbc26add1f1f8291e4461b3b2f9a000e86d3c..b59a81a8e7d32d35d1ad9c3b1ce4cc833bf7eb7b 100644 (file)
 #include <asm/arch/lubbock.h>
 #include <asm/mach/time.h>
 
-
-/*
- * Debug macros
- */
-#undef DEBUG
-
-#define SAVE(x)                sleep_save[SLEEP_SAVE_##x] = x
-#define RESTORE(x)     x = sleep_save[SLEEP_SAVE_##x]
-
-#define RESTORE_GPLEVEL(n) do { \
-       GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
-       GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
-} while (0)
-
-/*
- * List of global PXA peripheral registers to preserve.
- * More ones like CP and general purpose register values are preserved
- * with the stack pointer in sleep.S.
- */
-enum { SLEEP_SAVE_START = 0,
-
-       SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
-       SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
-       SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
-       SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
-       SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
-
-       SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
-       SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
-       SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
-       SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
-
-       SLEEP_SAVE_PSTR,
-
-       SLEEP_SAVE_ICMR,
-       SLEEP_SAVE_CKEN,
-
-#ifdef CONFIG_PXA27x
-       SLEEP_SAVE_MDREFR,
-       SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
-       SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
-#endif
-
-       SLEEP_SAVE_CKSUM,
-
-       SLEEP_SAVE_SIZE
-};
-
+struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
+static unsigned long *sleep_save;
 
 int pxa_pm_enter(suspend_state_t state)
 {
-       unsigned long sleep_save[SLEEP_SAVE_SIZE];
-       unsigned long checksum = 0;
+       unsigned long sleep_save_checksum = 0, checksum = 0;
        int i;
-       extern void pxa_cpu_pm_enter(suspend_state_t state);
 
 #ifdef CONFIG_IWMMXT
        /* force any iWMMXt context to ram **/
@@ -86,100 +38,35 @@ int pxa_pm_enter(suspend_state_t state)
                iwmmxt_task_disable(NULL);
 #endif
 
-       SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
-       SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
-       SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
-       SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
-       SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
-
-       SAVE(GAFR0_L); SAVE(GAFR0_U);
-       SAVE(GAFR1_L); SAVE(GAFR1_U);
-       SAVE(GAFR2_L); SAVE(GAFR2_U);
-
-#ifdef CONFIG_PXA27x
-       SAVE(MDREFR);
-       SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
-       SAVE(GAFR3_L); SAVE(GAFR3_U);
-       SAVE(PWER); SAVE(PCFR); SAVE(PRER);
-       SAVE(PFER); SAVE(PKWR);
-#endif
-
-       SAVE(ICMR);
-       ICMR = 0;
-
-       SAVE(CKEN);
-       SAVE(PSTR);
-
-       /* Note: wake up source are set up in each machine specific files */
-
-       /* clear GPIO transition detect  bits */
-       GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
-#ifdef CONFIG_PXA27x
-       GEDR3 = GEDR3;
-#endif
+       pxa_cpu_pm_fns->save(sleep_save);
 
        /* Clear sleep reset status */
        RCSR = RCSR_SMR;
 
        /* before sleeping, calculate and save a checksum */
-       for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
-               checksum += sleep_save[i];
-       sleep_save[SLEEP_SAVE_CKSUM] = checksum;
+       for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
+               sleep_save_checksum += sleep_save[i];
 
        /* *** go zzz *** */
-       pxa_cpu_pm_enter(state);
-
+       pxa_cpu_pm_fns->enter(state);
        cpu_init();
 
        /* after sleeping, validate the checksum */
-       checksum = 0;
-       for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
+       for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
                checksum += sleep_save[i];
 
        /* if invalid, display message and wait for a hardware reset */
-       if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
+       if (checksum != sleep_save_checksum) {
 #ifdef CONFIG_ARCH_LUBBOCK
                LUB_HEXLED = 0xbadbadc5;
 #endif
                while (1)
-                       pxa_cpu_pm_enter(state);
+                       pxa_cpu_pm_fns->enter(state);
        }
 
-       /* ensure not to come back here if it wasn't intended */
-       PSPR = 0;
-
-       /* restore registers */
-       RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
-       RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
-       RESTORE(GAFR0_L); RESTORE(GAFR0_U);
-       RESTORE(GAFR1_L); RESTORE(GAFR1_U);
-       RESTORE(GAFR2_L); RESTORE(GAFR2_U);
-       RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
-       RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
-       RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
-
-#ifdef CONFIG_PXA27x
-       RESTORE(MDREFR);
-       RESTORE_GPLEVEL(3); RESTORE(GPDR3);
-       RESTORE(GAFR3_L); RESTORE(GAFR3_U);
-       RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
-       RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
-       RESTORE(PFER); RESTORE(PKWR);
-#endif
-
-       PSSR = PSSR_RDH | PSSR_PH;
-
-       RESTORE(CKEN);
-
-       ICLR = 0;
-       ICCR = 1;
-       RESTORE(ICMR);
+       pxa_cpu_pm_fns->restore(sleep_save);
 
-       RESTORE(PSTR);
-
-#ifdef DEBUG
-       printk(KERN_DEBUG "*** made it back from resume\n");
-#endif
+       pr_debug("*** made it back from resume\n");
 
        return 0;
 }
@@ -190,3 +77,35 @@ unsigned long sleep_phys_sp(void *sp)
 {
        return virt_to_phys(sp);
 }
+
+static int pxa_pm_valid(suspend_state_t state)
+{
+       if (pxa_cpu_pm_fns)
+               return pxa_cpu_pm_fns->valid(state);
+
+       return -EINVAL;
+}
+
+static struct pm_ops pxa_pm_ops = {
+       .valid          = pxa_pm_valid,
+       .enter          = pxa_pm_enter,
+};
+
+static int __init pxa_pm_init(void)
+{
+       if (!pxa_cpu_pm_fns) {
+               printk(KERN_ERR "no valid pxa_cpu_pm_fns defined\n");
+               return -EINVAL;
+       }
+
+       sleep_save = kmalloc(pxa_cpu_pm_fns->save_size, GFP_KERNEL);
+       if (!sleep_save) {
+               printk(KERN_ERR "failed to alloc memory for pm save\n");
+               return -ENOMEM;
+       }
+
+       pm_set_ops(&pxa_pm_ops);
+       return 0;
+}
+
+device_initcall(pxa_pm_init);
index f36ca448338e380ff76cef2764193a7d83e4949c..6dfcca72e90f65602f8d58140329cc6e2f3273ff 100644 (file)
@@ -110,26 +110,99 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
 
 #ifdef CONFIG_PM
 
-void pxa_cpu_pm_enter(suspend_state_t state)
+#define SAVE(x)                sleep_save[SLEEP_SAVE_##x] = x
+#define RESTORE(x)     x = sleep_save[SLEEP_SAVE_##x]
+
+#define RESTORE_GPLEVEL(n) do { \
+       GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
+       GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
+} while (0)
+
+/*
+ * List of global PXA peripheral registers to preserve.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+enum { SLEEP_SAVE_START = 0,
+
+       SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
+       SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
+       SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
+       SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
+       SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
+
+       SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
+       SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
+       SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
+
+       SLEEP_SAVE_PSTR,
+
+       SLEEP_SAVE_ICMR,
+       SLEEP_SAVE_CKEN,
+
+       SLEEP_SAVE_SIZE
+};
+
+
+static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
+{
+       SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
+       SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
+       SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
+       SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
+       SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
+
+       SAVE(GAFR0_L); SAVE(GAFR0_U);
+       SAVE(GAFR1_L); SAVE(GAFR1_U);
+       SAVE(GAFR2_L); SAVE(GAFR2_U);
+
+       SAVE(ICMR);
+       SAVE(CKEN);
+       SAVE(PSTR);
+}
+
+static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 {
-       extern void pxa_cpu_suspend(unsigned int);
-       extern void pxa_cpu_resume(void);
+       /* restore registers */
+       RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
+       RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
+       RESTORE(GAFR0_L); RESTORE(GAFR0_U);
+       RESTORE(GAFR1_L); RESTORE(GAFR1_U);
+       RESTORE(GAFR2_L); RESTORE(GAFR2_U);
+       RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
+       RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
+       RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
+
+       RESTORE(CKEN);
+       RESTORE(ICMR);
+       RESTORE(PSTR);
+}
 
+static void pxa25x_cpu_pm_enter(suspend_state_t state)
+{
        CKEN = 0;
 
        switch (state) {
        case PM_SUSPEND_MEM:
                /* set resume return address */
                PSPR = virt_to_phys(pxa_cpu_resume);
-               pxa_cpu_suspend(PWRMODE_SLEEP);
+               pxa25x_cpu_suspend(PWRMODE_SLEEP);
                break;
        }
 }
 
-static struct pm_ops pxa25x_pm_ops = {
-       .enter          = pxa_pm_enter,
+static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
+       .save_size      = SLEEP_SAVE_SIZE,
        .valid          = pm_valid_only_mem,
+       .save           = pxa25x_cpu_pm_save,
+       .restore        = pxa25x_cpu_pm_restore,
+       .enter          = pxa25x_cpu_pm_enter,
 };
+
+static void __init pxa25x_init_pm(void)
+{
+       pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
+}
 #endif
 
 void __init pxa25x_init_irq(void)
@@ -139,16 +212,16 @@ void __init pxa25x_init_irq(void)
 }
 
 static struct platform_device *pxa25x_devices[] __initdata = {
-       &pxamci_device,
-       &pxaudc_device,
-       &pxafb_device,
-       &ffuart_device,
-       &btuart_device,
-       &stuart_device,
-       &pxai2c_device,
-       &pxai2s_device,
-       &pxaficp_device,
-       &pxartc_device,
+       &pxa_device_mci,
+       &pxa_device_udc,
+       &pxa_device_fb,
+       &pxa_device_ffuart,
+       &pxa_device_btuart,
+       &pxa_device_stuart,
+       &pxa_device_i2c,
+       &pxa_device_i2s,
+       &pxa_device_ficp,
+       &pxa_device_rtc,
 };
 
 static int __init pxa25x_init(void)
@@ -159,14 +232,14 @@ static int __init pxa25x_init(void)
                if ((ret = pxa_init_dma(16)))
                        return ret;
 #ifdef CONFIG_PM
-               pm_set_ops(&pxa25x_pm_ops);
+               pxa25x_init_pm();
 #endif
                ret = platform_add_devices(pxa25x_devices,
                                           ARRAY_SIZE(pxa25x_devices));
        }
        /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
        if (cpu_is_pxa25x())
-               ret = platform_device_register(&hwuart_device);
+               ret = platform_device_register(&pxa_device_hwuart);
 
        return ret;
 }
index aa5bb02c897bd331c59ce29b1bcbc10c2be83e81..203371ab19db2b87c97359a12eb8d6defabab649 100644 (file)
@@ -126,14 +126,107 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
 
 #ifdef CONFIG_PM
 
-void pxa_cpu_pm_enter(suspend_state_t state)
+#define SAVE(x)                sleep_save[SLEEP_SAVE_##x] = x
+#define RESTORE(x)     x = sleep_save[SLEEP_SAVE_##x]
+
+#define RESTORE_GPLEVEL(n) do { \
+       GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
+       GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
+} while (0)
+
+/*
+ * List of global PXA peripheral registers to preserve.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+enum { SLEEP_SAVE_START = 0,
+
+       SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
+       SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
+       SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
+       SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
+       SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
+
+       SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
+       SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
+       SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
+       SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
+
+       SLEEP_SAVE_PSTR,
+
+       SLEEP_SAVE_ICMR,
+       SLEEP_SAVE_CKEN,
+
+       SLEEP_SAVE_MDREFR,
+       SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
+       SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
+
+       SLEEP_SAVE_SIZE
+};
+
+void pxa27x_cpu_pm_save(unsigned long *sleep_save)
+{
+       SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
+       SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
+       SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
+       SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
+       SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
+
+       SAVE(GAFR0_L); SAVE(GAFR0_U);
+       SAVE(GAFR1_L); SAVE(GAFR1_U);
+       SAVE(GAFR2_L); SAVE(GAFR2_U);
+       SAVE(GAFR3_L); SAVE(GAFR3_U);
+
+       SAVE(MDREFR);
+       SAVE(PWER); SAVE(PCFR); SAVE(PRER);
+       SAVE(PFER); SAVE(PKWR);
+
+       SAVE(ICMR); ICMR = 0;
+       SAVE(CKEN);
+       SAVE(PSTR);
+
+       /* Clear GPIO transition detect bits */
+       GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
+}
+
+void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
+{
+       /* ensure not to come back here if it wasn't intended */
+       PSPR = 0;
+
+       /* restore registers */
+       RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
+       RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
+       RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
+       RESTORE(GAFR0_L); RESTORE(GAFR0_U);
+       RESTORE(GAFR1_L); RESTORE(GAFR1_U);
+       RESTORE(GAFR2_L); RESTORE(GAFR2_U);
+       RESTORE(GAFR3_L); RESTORE(GAFR3_U);
+       RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
+       RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
+       RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
+
+       RESTORE(MDREFR);
+       RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
+       RESTORE(PFER); RESTORE(PKWR);
+
+       PSSR = PSSR_RDH | PSSR_PH;
+
+       RESTORE(CKEN);
+
+       ICLR = 0;
+       ICCR = 1;
+       RESTORE(ICMR);
+       RESTORE(PSTR);
+}
+
+void pxa27x_cpu_pm_enter(suspend_state_t state)
 {
        extern void pxa_cpu_standby(void);
-       extern void pxa_cpu_suspend(unsigned int);
-       extern void pxa_cpu_resume(void);
 
        if (state == PM_SUSPEND_STANDBY)
-               CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0);
+               CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
+                       (1 << CKEN_LCD) | (1 << CKEN_PWM0);
        else
                CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
 
@@ -150,20 +243,28 @@ void pxa_cpu_pm_enter(suspend_state_t state)
        case PM_SUSPEND_MEM:
                /* set resume return address */
                PSPR = virt_to_phys(pxa_cpu_resume);
-               pxa_cpu_suspend(PWRMODE_SLEEP);
+               pxa27x_cpu_suspend(PWRMODE_SLEEP);
                break;
        }
 }
 
-static int pxa27x_pm_valid(suspend_state_t state)
+static int pxa27x_cpu_pm_valid(suspend_state_t state)
 {
        return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 }
 
-static struct pm_ops pxa27x_pm_ops = {
-       .enter          = pxa_pm_enter,
-       .valid          = pxa27x_pm_valid,
+static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
+       .save_size      = SLEEP_SAVE_SIZE,
+       .save           = pxa27x_cpu_pm_save,
+       .restore        = pxa27x_cpu_pm_restore,
+       .valid          = pxa27x_cpu_pm_valid,
+       .enter          = pxa27x_cpu_pm_enter,
 };
+
+static void __init pxa27x_init_pm(void)
+{
+       pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
+}
 #endif
 
 /*
@@ -185,7 +286,7 @@ static struct resource pxa27x_ohci_resources[] = {
        },
 };
 
-static struct platform_device pxaohci_device = {
+static struct platform_device pxa27x_device_ohci = {
        .name           = "pxa27x-ohci",
        .id             = -1,
        .dev            = {
@@ -198,7 +299,7 @@ static struct platform_device pxaohci_device = {
 
 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
 {
-       pxaohci_device.dev.platform_data = info;
+       pxa27x_device_ohci.dev.platform_data = info;
 }
 
 static struct resource i2c_power_resources[] = {
@@ -213,7 +314,7 @@ static struct resource i2c_power_resources[] = {
        },
 };
 
-static struct platform_device pxai2c_power_device = {
+static struct platform_device pxa27x_device_i2c_power = {
        .name           = "pxa2xx-i2c",
        .id             = 1,
        .resource       = i2c_power_resources,
@@ -221,18 +322,18 @@ static struct platform_device pxai2c_power_device = {
 };
 
 static struct platform_device *devices[] __initdata = {
-       &pxamci_device,
-       &pxaudc_device,
-       &pxafb_device,
-       &ffuart_device,
-       &btuart_device,
-       &stuart_device,
-       &pxai2c_device,
-       &pxai2c_power_device,
-       &pxai2s_device,
-       &pxaficp_device,
-       &pxartc_device,
-       &pxaohci_device,
+       &pxa_device_mci,
+       &pxa_device_udc,
+       &pxa_device_fb,
+       &pxa_device_ffuart,
+       &pxa_device_btuart,
+       &pxa_device_stuart,
+       &pxa_device_i2c,
+       &pxa_device_i2s,
+       &pxa_device_ficp,
+       &pxa_device_rtc,
+       &pxa27x_device_i2c_power,
+       &pxa27x_device_ohci,
 };
 
 void __init pxa27x_init_irq(void)
@@ -249,7 +350,7 @@ static int __init pxa27x_init(void)
                if ((ret = pxa_init_dma(32)))
                        return ret;
 #ifdef CONFIG_PM
-               pm_set_ops(&pxa27x_pm_ops);
+               pxa27x_init_pm();
 #endif
                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
        }
index 15874b360e519dd93c3e1f674b464fadb91210e3..aff71fec618ac7468cd3aca861873d86edb578a1 100644 (file)
 
 #include <asm/arch/pxa-regs.h>
 
-#ifdef CONFIG_PXA27x                   // workaround for Errata 50
 #define MDREFR_KDIV    0x200a4000      // all banks
 #define CCCR_SLEEP     0x00000107      // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
-#endif
 
                .text
 
-/*
- * pxa_cpu_suspend()
- *
- * Forces CPU into sleep state.
- *
- * r0 = value for PWRMODE M field for desired sleep state
- */
-
-ENTRY(pxa_cpu_suspend)
-
-#ifndef CONFIG_IWMMXT
-       mra     r2, r3, acc0
-#endif
-       stmfd   sp!, {r2 - r12, lr}             @ save registers on stack
-
+pxa_cpu_save_cp:
        @ get coprocessor registers
        mrc     p14, 0, r3, c6, c0, 0           @ clock configuration, for turbo mode
        mrc     p15, 0, r4, c15, c1, 0          @ CP access reg
@@ -54,12 +38,36 @@ ENTRY(pxa_cpu_suspend)
        mov     r10, sp
        stmfd   sp!, {r3 - r10}
 
-       mov r5, r0                              @ save sleep mode
+       mov     pc, lr
+
+pxa_cpu_save_sp:
        @ preserve phys address of stack
        mov     r0, sp
+       mov     r2, lr
        bl      sleep_phys_sp
        ldr     r1, =sleep_save_sp
        str     r0, [r1]
+       mov     pc, r2
+
+/*
+ * pxa27x_cpu_suspend()
+ *
+ * Forces CPU into sleep state.
+ *
+ * r0 = value for PWRMODE M field for desired sleep state
+ */
+
+ENTRY(pxa27x_cpu_suspend)
+
+#ifndef CONFIG_IWMMXT
+       mra     r2, r3, acc0
+#endif
+       stmfd   sp!, {r2 - r12, lr}             @ save registers on stack
+
+       bl      pxa_cpu_save_cp
+
+       mov     r5, r0                          @ save sleep mode
+       bl      pxa_cpu_save_sp
 
        @ clean data cache
        bl      xscale_flush_kern_cache_all
@@ -80,13 +88,55 @@ ENTRY(pxa_cpu_suspend)
        @ enable SDRAM self-refresh mode
        orr     r5, r5, #MDREFR_SLFRSH
 
-#ifdef CONFIG_PXA27x
        @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
        ldr     r6, =MDREFR_KDIV
        orr     r5, r5, r6
-#endif
 
-#ifdef CONFIG_PXA25x
+       @ Intel PXA270 Specification Update notes problems sleeping
+       @ with core operating above 91 MHz
+       @ (see Errata 50, ...processor does not exit from sleep...)
+
+       ldr     r6, =CCCR
+       ldr     r8, [r6]                @ keep original value for resume
+
+       ldr     r7, =CCCR_SLEEP         @ prepare CCCR sleep value
+       mov     r0, #0x2                @ prepare value for CLKCFG
+
+       @ align execution to a cache line
+       b       pxa_cpu_do_suspend
+
+/*
+ * pxa27x_cpu_suspend()
+ *
+ * Forces CPU into sleep state.
+ *
+ * r0 = value for PWRMODE M field for desired sleep state
+ */
+
+ENTRY(pxa25x_cpu_suspend)
+       stmfd   sp!, {r2 - r12, lr}             @ save registers on stack
+
+       bl      pxa_cpu_save_cp
+
+       mov     r5, r0                          @ save sleep mode
+       bl      pxa_cpu_save_sp
+
+       @ clean data cache
+       bl      xscale_flush_kern_cache_all
+
+       @ prepare value for sleep mode
+       mov     r1, r5                          @ sleep mode
+
+       @ prepare pointer to physical address 0 (virtual mapping in generic.c)
+       mov     r2, #UNCACHED_PHYS_0
+
+       @ prepare SDRAM refresh settings
+       ldr     r4, =MDREFR
+       ldr     r5, [r4]
+
+       @ enable SDRAM self-refresh mode
+       orr     r5, r5, #MDREFR_SLFRSH
+
        @ Intel PXA255 Specification Update notes problems
        @ about suspending with PXBus operating above 133MHz
        @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
@@ -118,30 +168,15 @@ ENTRY(pxa_cpu_suspend)
        mov     r0, #0
        mcr     p14, 0, r0, c6, c0, 0
        orr     r0, r0, #2                      @ initiate change bit
-#endif
-#ifdef CONFIG_PXA27x
-       @ Intel PXA270 Specification Update notes problems sleeping
-       @ with core operating above 91 MHz
-       @ (see Errata 50, ...processor does not exit from sleep...)
-
-       ldr     r6, =CCCR
-       ldr     r8, [r6]                @ keep original value for resume
-
-       ldr     r7, =CCCR_SLEEP         @ prepare CCCR sleep value
-       mov     r0, #0x2                @ prepare value for CLKCFG
-#endif
-
-       @ align execution to a cache line
-       b       1f
+       b       pxa_cpu_do_suspend
 
        .ltorg
        .align  5
-1:
+pxa_cpu_do_suspend:
 
        @ All needed values are now in registers.
        @ These last instructions should be in cache
 
-#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
        @ initiate the frequency change...
        str     r7, [r6]
        mcr     p14, 0, r0, c6, c0, 0
@@ -155,7 +190,6 @@ ENTRY(pxa_cpu_suspend)
        mov     r0, #42
 10:    subs    r0, r0, #1
        bne     10b
-#endif
 
        @ Do not reorder...
        @ Intel PXA270 Specification Update notes problems performing
index 6f91fd2d061ab0b9dc5062d5db3c551e03f6198e..98d27e646b0925a2266eb6fe63f9c29361a4c109 100644 (file)
@@ -1,9 +1,11 @@
 /*
  * arch/arm/mach-pxa/time.c
  *
- * Author:     Nicolas Pitre
- * Created:    Jun 15, 2001
- * Copyright:  MontaVista Software Inc.
+ * PXA clocksource, clockevents, and OST interrupt handlers.
+ * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
+ *
+ * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
+ * by MontaVista Software, Inc.  (Nico, your code rocks!)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/delay.h>
 #include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/clocksource.h>
-
-#include <asm/system.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/leds.h>
-#include <asm/irq.h>
+#include <linux/clockchips.h>
+
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/arch/pxa-regs.h>
 
-
-static int pxa_set_rtc(void)
-{
-       unsigned long current_time = xtime.tv_sec;
-
-       if (RTSR & RTSR_ALE) {
-               /* make sure not to forward the clock over an alarm */
-               unsigned long alarm = RTAR;
-               if (current_time >= alarm && alarm >= RCNR)
-                       return -ERESTARTSYS;
-       }
-       RCNR = current_time;
-       return 0;
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-static unsigned long initial_match;
-static int match_posponed;
-#endif
-
 static irqreturn_t
-pxa_timer_interrupt(int irq, void *dev_id)
+pxa_ost0_interrupt(int irq, void *dev_id)
 {
        int next_match;
-
-       write_seqlock(&xtime_lock);
-
-#ifdef CONFIG_NO_IDLE_HZ
-       if (match_posponed) {
-               match_posponed = 0;
-               OSMR0 = initial_match;
-       }
-#endif
-
-       /* Loop until we get ahead of the free running timer.
-        * This ensures an exact clock tick count and time accuracy.
-        * Since IRQs are disabled at this point, coherence between
-        * lost_ticks(updated in do_timer()) and the match reg value is
-        * ensured, hence we can use do_gettimeofday() from interrupt
-        * handlers.
-        *
-        * HACK ALERT: it seems that the PXA timer regs aren't updated right
-        * away in all cases when a write occurs.  We therefore compare with
-        * 8 instead of 0 in the while() condition below to avoid missing a
-        * match if OSCR has already reached the next OSMR value.
-        * Experience has shown that up to 6 ticks are needed to work around
-        * this problem, but let's use 8 to be conservative.  Note that this
-        * affect things only when the timer IRQ has been delayed by nearly
-        * exactly one tick period which should be a pretty rare event.
+       struct clock_event_device *c = dev_id;
+
+       if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
+               /* Disarm the compare/match, signal the event. */
+               OIER &= ~OIER_E0;
+               c->event_handler(c);
+       } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
+               /* Call the event handler as many times as necessary
+                * to recover missed events, if any (if we update
+                * OSMR0 and OSCR0 is still ahead of us, we've missed
+                * the event).  As we're dealing with that, re-arm the
+                * compare/match for the next event.
+                *
+                * HACK ALERT:
+                *
+                * There's a latency between the instruction that
+                * writes to OSMR0 and the actual commit to the
+                * physical hardware, because the CPU doesn't (have
+                * to) run at bus speed, there's a write buffer
+                * between the CPU and the bus, etc. etc.  So if the
+                * target OSCR0 is "very close", to the OSMR0 load
+                * value, the update to OSMR0 might not get to the
+                * hardware in time and we'll miss that interrupt.
+                *
+                * To be safe, if the new OSMR0 is "very close" to the
+                * target OSCR0 value, we call the event_handler as
+                * though the event actually happened.  According to
+                * Nico's comment in the previous version of this
+                * code, experience has shown that 6 OSCR ticks is
+                * "very close" but he went with 8.  We will use 16,
+                * based on the results of testing on PXA270.
+                *
+                * To be doubly sure, we also tell clkevt via
+                * clockevents_register_device() not to ask for
+                * anything that might put us "very close".
         */
+#define MIN_OSCR_DELTA 16
        do {
-               timer_tick();
-               OSSR = OSSR_M0;  /* Clear match on timer 0 */
+                       OSSR = OSSR_M0;
                next_match = (OSMR0 += LATCH);
-       } while( (signed long)(next_match - OSCR) <= 8 );
-
-       write_sequnlock(&xtime_lock);
+                       c->event_handler(c);
+               } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
+                        && (c->mode == CLOCK_EVT_MODE_PERIODIC));
+       }
 
        return IRQ_HANDLED;
 }
 
-static struct irqaction pxa_timer_irq = {
-       .name           = "PXA Timer Tick",
-       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-       .handler        = pxa_timer_interrupt,
+static int
+pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+       unsigned long irqflags;
+
+       raw_local_irq_save(irqflags);
+       OSMR0 = OSCR + delta;
+       OSSR = OSSR_M0;
+       OIER |= OIER_E0;
+       raw_local_irq_restore(irqflags);
+       return 0;
+}
+
+static void
+pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+       unsigned long irqflags;
+
+       switch (mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               raw_local_irq_save(irqflags);
+               OSMR0 = OSCR + LATCH;
+               OSSR = OSSR_M0;
+               OIER |= OIER_E0;
+               raw_local_irq_restore(irqflags);
+               break;
+
+       case CLOCK_EVT_MODE_ONESHOT:
+               raw_local_irq_save(irqflags);
+               OIER &= ~OIER_E0;
+               raw_local_irq_restore(irqflags);
+               break;
+
+       case CLOCK_EVT_MODE_UNUSED:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+               /* initializing, released, or preparing for suspend */
+               raw_local_irq_save(irqflags);
+               OIER &= ~OIER_E0;
+               raw_local_irq_restore(irqflags);
+               break;
+       }
+}
+
+static struct clock_event_device ckevt_pxa_osmr0 = {
+       .name           = "osmr0",
+       .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+       .shift          = 32,
+       .rating         = 200,
+       .cpumask        = CPU_MASK_CPU0,
+       .set_next_event = pxa_osmr0_set_next_event,
+       .set_mode       = pxa_osmr0_set_mode,
 };
 
-static cycle_t pxa_get_cycles(void)
+static cycle_t pxa_read_oscr(void)
 {
        return OSCR;
 }
 
-static struct clocksource clocksource_pxa = {
-       .name           = "pxa_timer",
+static struct clocksource cksrc_pxa_oscr0 = {
+       .name           = "oscr0",
        .rating         = 200,
-       .read           = pxa_get_cycles,
+       .read           = pxa_read_oscr,
        .mask           = CLOCKSOURCE_MASK(32),
        .shift          = 20,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct irqaction pxa_ost0_irq = {
+       .name           = "ost0",
+       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+       .handler        = pxa_ost0_interrupt,
+       .dev_id         = &ckevt_pxa_osmr0,
+};
+
 static void __init pxa_timer_init(void)
 {
-       struct timespec tv;
-       unsigned long flags;
+       OIER = 0;
+       OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
-       set_rtc = pxa_set_rtc;
+       ckevt_pxa_osmr0.mult =
+               div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
+       ckevt_pxa_osmr0.max_delta_ns =
+               clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
+       ckevt_pxa_osmr0.min_delta_ns =
+               clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
 
-       OIER = 0;               /* disable any timer interrupts */
-       OSSR = 0xf;             /* clear status on all timers */
-       setup_irq(IRQ_OST0, &pxa_timer_irq);
-       local_irq_save(flags);
-       OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
-       OSMR0 = OSCR + LATCH;   /* set initial match */
-       local_irq_restore(flags);
-
-       /*
-        * OSCR runs continuously on PXA and is not written to,
-        * so we can use it as clock source directly.
-        */
-       clocksource_pxa.mult =
-               clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift);
-       clocksource_register(&clocksource_pxa);
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-static int pxa_dyn_tick_enable_disable(void)
-{
-       /* nothing to do */
-       return 0;
-}
+       cksrc_pxa_oscr0.mult =
+               clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
 
-static void pxa_dyn_tick_reprogram(unsigned long ticks)
-{
-       if (ticks > 1) {
-               initial_match = OSMR0;
-               OSMR0 = initial_match + ticks * LATCH;
-               match_posponed = 1;
-       }
-}
+       setup_irq(IRQ_OST0, &pxa_ost0_irq);
 
-static irqreturn_t
-pxa_dyn_tick_handler(int irq, void *dev_id)
-{
-       if (match_posponed) {
-               match_posponed = 0;
-               OSMR0 = initial_match;
-               if ( (signed long)(initial_match - OSCR) <= 8 )
-                       return pxa_timer_interrupt(irq, dev_id);
-       }
-       return IRQ_NONE;
+       clocksource_register(&cksrc_pxa_oscr0);
+       clockevents_register_device(&ckevt_pxa_osmr0);
 }
 
-static struct dyn_tick_timer pxa_dyn_tick = {
-       .enable         = pxa_dyn_tick_enable_disable,
-       .disable        = pxa_dyn_tick_enable_disable,
-       .reprogram      = pxa_dyn_tick_reprogram,
-       .handler        = pxa_dyn_tick_handler,
-};
-#endif
-
 #ifdef CONFIG_PM
 static unsigned long osmr[4], oier;
 
@@ -191,7 +189,10 @@ static void pxa_timer_resume(void)
        OIER = oier;
 
        /*
-        * OSMR0 is the system timer: make sure OSCR is sufficiently behind
+        * OSCR0 is the system timer, which has to increase
+        * monotonically until it rolls over in hardware.  The value
+        * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
+        * which is a handy value to restore to OSCR0.
         */
        OSCR = OSMR0 - LATCH;
 }
@@ -204,7 +205,4 @@ struct sys_timer pxa_timer = {
        .init           = pxa_timer_init,
        .suspend        = pxa_timer_suspend,
        .resume         = pxa_timer_resume,
-#ifdef CONFIG_NO_IDLE_HZ
-       .dyn_tick       = &pxa_dyn_tick,
-#endif
 };
index 570cf937e73b378ea4cecbf91c17d547b16017ad..a454451c97c36ea77ee9abb2a74e6b9f99ff0f6e 100644 (file)
@@ -87,7 +87,7 @@ static void __init rpc_map_io(void)
        /*
         * Turn off floppy.
         */
-       outb(0xc, 0x3f2);
+       writeb(0xc, PCIO_BASE + (0x3f2 << 2));
 
        /*
         * RiscPC can't handle half-word loads and stores
index d4b013b283c3680f63be0b9b8b05b4120ebf3777..e2079cf9266fd44c5f2bff2ab81826585cd65f9b 100644 (file)
@@ -9,6 +9,7 @@ config CPU_S3C2410
        depends on ARCH_S3C2410
        select S3C2410_CLOCK
        select S3C2410_GPIO
+       select CPU_LLSERIAL_S3C2410
        select S3C2410_PM if PM
        help
          Support for S3C2410 and S3C2410A family from the S3C24XX line
index 5b4831c4c1d8dccb556c35a6502c92b238933672..cab9d6265e9ee513d37cae781a89e068721df398 100644 (file)
@@ -37,7 +37,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 
index 67d1ad36397344715a1c085a0abe0ce9b82632ea..80d83739ab9f6c0185eac554b4208c9b7ffb056c 100644 (file)
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/dma.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
        [DMACH_XD0] = {
index 435adcce6482a369e5898de40bfc4bdfb690a6e1..43bb5e1063020fa112cdb9d5e6a2f6c8b7845eca 100644 (file)
@@ -48,7 +48,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/fb.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-gpio.h>
 
index 8b52ea95d4f68523f72782aee1c8ca368a7ddb35..bc926992b4e447de12b0504ff7a3bbfed48bd923 100644 (file)
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 
-#include <asm/arch/nand.h>
-#include <asm/arch/iic.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c/iic.h>
 #include <asm/arch/fb.h>
 
 #include <linux/mtd/mtd.h>
index 5c9bcea7476732d77e6f3081b86956ec9db3f947..9a172b4ad720f51980ab10c928eb2611970f253e 100644 (file)
@@ -30,7 +30,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
@@ -38,7 +38,7 @@
 #include <asm/arch/h1940.h>
 #include <asm/arch/h1940-latch.h>
 #include <asm/arch/fb.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
index 412e50c3d28ac0d518941f77d387971bc2a72324..621f548da610fd297f1d590e898b85d98063e520 100644 (file)
@@ -33,9 +33,9 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/iic.h>
+#include <asm/plat-s3c/iic.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>
index 1f899fa588dfdcaef21d531f3360447366f334b6..717af40e4477d62fcae8a1da4178f159517b57a4 100644 (file)
@@ -29,7 +29,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
index d86e6f18bac9f736ddd7beca0ae9e3a4e88eb88f..e670b1e1631bd2619deb3189e7358bdeeb3ff185 100644 (file)
 
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/fb.h>
-#include <asm/arch/nand.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c24xx/udc.h>
 #include <asm/arch/spi.h>
 #include <asm/arch/spi-gpio.h>
 
index 5852d300d52f67c5a0997b2993083264779f22b2..226550504c85fd05142ed1d7830ae215ce0953f3 100644 (file)
@@ -47,7 +47,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
index 7b624bb0049060c06c41c5c7b7d39fa76ec437d7..9f43f3f124f561eeec3efa9b5bbc16a9c083b5e1 100644 (file)
@@ -39,7 +39,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
 
index 1a86a9803753470acb87ea3476d30c9ece2a87d8..e580303cb0abbd86d1e97429ea21fceaeeb0efec 100644 (file)
@@ -29,7 +29,7 @@
 #include <asm/irq.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/cpu.h>
@@ -40,7 +40,6 @@
 
 static struct map_desc s3c2410_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
-       IODESC_ENT(LCD),
        IODESC_ENT(TIMER),
        IODESC_ENT(WATCHDOG),
 };
index d1eeed2ad47c79f5ed1d94209233957001690f5f..8a9c5a2bb2523295b01c919ad98088da2c415ca7 100644 (file)
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
        /* s3c2410_cpu_suspend
         *
index d5be5d053264da3079782e6abe8436e43759daec..8e8fe48ea47f24f9deb1419f5a0ed7c48693a5a3 100644 (file)
@@ -7,6 +7,7 @@
 config CPU_S3C2412
        bool
        depends on ARCH_S3C2410
+       select CPU_LLSERIAL_S3C2440
        select S3C2412_PM if PM
        select S3C2412_DMA if S3C2410_DMA
        help
index 6a8e4448770bdce38870138b780db90477932bcf..8543dd6df391e17cbeb895beef52af22b0091fb9 100644 (file)
@@ -37,7 +37,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 
index 668cccefe7b066aa4472a91b18469d4b80904617..4b9425c1bf722b8eb25dc4ecf2d15126b0637181 100644 (file)
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
 
index 063af09f899d865a253376304980c4bb634a01c3..b126a530daa661f993304d68a8d6e619852e73af 100644 (file)
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/idle.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 #include <asm/arch/fb.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
index f2fbd65956acd0db2d823c99e82ff3d641349290..32982547cd633fa8f065b18cc601534b783ff51c 100644 (file)
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/idle.h>
 #include <asm/arch/fb.h>
 
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2412.h>
index 782b5814ced24411f356a4566c8f19265de3601b..e0ccb404623f738b373ee3eb227dc987e0b17808 100644 (file)
 #include <asm/arch/idle.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-power.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>
 #include <asm/arch/regs-dsc.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 #include <asm/arch/regs-s3c2412.h>
 
 #include <asm/plat-s3c24xx/s3c2412.h>
@@ -63,7 +63,6 @@ static inline void s3c2412_init_gpio2(void)
 
 static struct map_desc s3c2412_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
-       IODESC_ENT(LCD),
        IODESC_ENT(TIMER),
        IODESC_ENT(WATCHDOG),
 };
index e3bfda098c0f440a52ef2fbc4200857fab0d48c6..f1915bd61d15b862e4198c110a0a499a0f40e378 100644 (file)
@@ -12,6 +12,7 @@ config CPU_S3C2440
        select S3C2410_GPIO
        select S3C2440_DMA if S3C2410_DMA
        select CPU_S3C244X
+       select CPU_LLSERIAL_S3C2440
        help
          Support for S3C2440 Samsung Mobile CPU based systems.
 
index cd035a3ec878be42d8d75b53229db416d04a274a..f509f062e749bcd0b6357921058e4139d76c6ee3 100644 (file)
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
        [DMACH_XD0] = {
index 29c163d300d4cc9f78a4f35654e3559b92497efc..3d3dfa95db8ef7dcfcd668150e7fb4959638213f 100644 (file)
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
index 5e61f2166c76f6583cb923ed6472afbb713f6e97..afe0d7b7e389003235722326ea4a4fa700bd81d6 100644 (file)
@@ -36,7 +36,7 @@
 
 //#include <asm/debug-ll.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2440.h>
index 89f4c9c5777b324ca4f603f4fdeb5ed6dabb2473..0ba7e9060c7bba3ece0df5d9eacbdbeb86d71eac 100644 (file)
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
index 866ff71c01ddf27861192763270f72cf51dac212..b59e6d39f2f267f8cd09508c729665437df2e424 100644 (file)
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/h1940.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 #include <asm/arch/fb.h>
 
 #include <asm/plat-s3c24xx/clock.h>
index e167254e232eb8155156ba994dbed62d1e388229..670115b8a12ea49c3592fa3bdbde0b6dc4f4e875 100644 (file)
@@ -31,7 +31,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
index bf8d87abfab39def97a8c805bef77e142ac38319..88d5fd34fe3bca320a4146feb314ccc5c21163a1 100644 (file)
@@ -11,6 +11,7 @@ config CPU_S3C2442
        select S3C2410_GPIO
        select S3C2410_PM if PM
        select CPU_S3C244X
+       select CPU_LLSERIAL_S3C2440
        help
          Support for S3C2442 Samsung Mobile CPU based systems.
 
index c649bb2e7ce84ef7bddd9761d212480975dcfefa..14252f57375468d4d9809fe5e6475550962a688d 100644 (file)
@@ -8,6 +8,7 @@ config CPU_S3C2443
        bool
        depends on ARCH_S3C2410
        select S3C2443_DMA if S3C2410_DMA
+       select CPU_LLSERIAL_S3C2440
        help
          Support for the S3C2443 SoC from the S3C24XX line
 
index f70e8ccffc3d6e457f7625a8d5a9e1ab16233ab4..fc3ede82af8f77360fef59d0a1e3200d3c60bd5c 100644 (file)
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 #define MAP(x) { \
                [0]     = (x) | DMA_CH_VALID,   \
index b1eb709ee65a3d7a7acb87a3bbbf614b788f7c24..8cd93130ef36bb5434bd4c001cf3388a421195f2 100644 (file)
@@ -31,7 +31,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
index cd67ab1b217b7d9ae1478af363aaa7e646d8c866..f99d9013905fea6ecaad0fd36c965696b5145fe1 100644 (file)
@@ -101,6 +101,16 @@ config SA1100_JORNADA720
          handheld computer.  See <http://www.hp.com/jornada/products/720>
          for details.
 
+config SA1100_JORNADA720_SSP
+       bool "HP Jornada 720 Extended SSP driver"
+       select SA1100_SSP
+       depends on SA1100_JORNADA720
+       help
+         Say Y here if you have a HP Jornada 7xx handheld computer and you
+         want to access devices connected to the MCU. Those include the
+         keyboard, touchscreen, backlight and battery. This driver also activates
+         the generic SSP which it extends.
+
 config SA1100_HACKKIT
        bool "HackKit Core CPU Board"
        help
@@ -145,8 +155,7 @@ config SA1100_SSP
        help
          Say Y here to enable support for the generic PIO SSP driver.
          This isn't for audio support, but for attached sensors and
-         other devices, eg for BadgePAD 4 sensor support, or Jornada
-         720 touchscreen support.
+         other devices, eg for BadgePAD 4 sensor support.
 
 config H3600_SLEEVE
        tristate "Compaq iPAQ Handheld sleeve support"
index e27f15042a22dfec7e492f0fa6d965fec139cf5d..7a61e8d33ab7527240ec74d6cc50812b72a57c71 100644 (file)
@@ -31,6 +31,7 @@ obj-$(CONFIG_SA1100_HACKKIT)          += hackkit.o
 led-$(CONFIG_SA1100_HACKKIT)           += leds-hackkit.o
 
 obj-$(CONFIG_SA1100_JORNADA720)                += jornada720.o
+obj-$(CONFIG_SA1100_JORNADA720_SSP)    += jornada720_ssp.o
 
 obj-$(CONFIG_SA1100_LART)              += lart.o
 led-$(CONFIG_SA1100_LART)              += leds-lart.o
@@ -51,3 +52,4 @@ obj-$(CONFIG_LEDS) += $(led-y)
 # Miscelaneous functions
 obj-$(CONFIG_PM)                       += pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)               += ssp.o
+
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
new file mode 100644 (file)
index 0000000..0a45e1a
--- /dev/null
@@ -0,0 +1,201 @@
+/**
+ *  arch/arm/mac-sa1100/jornada720_ssp.c
+ *
+ *  Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *   Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  SSP driver for the HP Jornada 710/720/728
+ */
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include <asm/hardware.h>
+#include <asm/hardware/ssp.h>
+#include <asm/arch/jornada720.h>
+
+static DEFINE_SPINLOCK(jornada_ssp_lock);
+static unsigned long jornada_ssp_flags;
+
+/**
+ * jornada_ssp_reverse - reverses input byte
+ *
+ * we need to reverse all data we recieve from the mcu due to its physical location
+ * returns : 01110111 -> 11101110
+ */
+u8 inline jornada_ssp_reverse(u8 byte)
+{
+       return
+               ((0x80 & byte) >> 7) |
+               ((0x40 & byte) >> 5) |
+               ((0x20 & byte) >> 3) |
+               ((0x10 & byte) >> 1) |
+               ((0x08 & byte) << 1) |
+               ((0x04 & byte) << 3) |
+               ((0x02 & byte) << 5) |
+               ((0x01 & byte) << 7);
+};
+EXPORT_SYMBOL(jornada_ssp_reverse);
+
+/**
+ * jornada_ssp_byte - waits for ready ssp bus and sends byte
+ *
+ * waits for fifo buffer to clear and then transmits, if it doesn't then we will
+ * timeout after <timeout> rounds. Needs mcu running before its called.
+ *
+ * returns : %mcu output on success
+ *        : %-ETIMEOUT on timeout
+ */
+int jornada_ssp_byte(u8 byte)
+{
+       int timeout = 400000;
+       u16 ret;
+
+       while ((GPLR & GPIO_GPIO10)) {
+               if (!--timeout) {
+                       printk(KERN_WARNING "SSP: timeout while waiting for transmit\n");
+                       return -ETIMEDOUT;
+               }
+               cpu_relax();
+       }
+
+       ret = jornada_ssp_reverse(byte) << 8;
+
+       ssp_write_word(ret);
+       ssp_read_word(&ret);
+
+       return jornada_ssp_reverse(ret);
+};
+EXPORT_SYMBOL(jornada_ssp_byte);
+
+/**
+ * jornada_ssp_inout - decide if input is command or trading byte
+ *
+ * returns : (jornada_ssp_byte(byte)) on success
+ *         : %-ETIMEOUT on timeout failure
+ */
+int jornada_ssp_inout(u8 byte)
+{
+       int ret, i;
+
+       /* true means command byte */
+       if (byte != TXDUMMY) {
+               ret = jornada_ssp_byte(byte);
+               /* Proper return to commands is TxDummy */
+               if (ret != TXDUMMY) {
+                       for (i = 0; i < 256; i++)/* flushing bus */
+                               if (jornada_ssp_byte(TXDUMMY) == -1)
+                                       break;
+                       return -ETIMEDOUT;
+               }
+       } else /* Exchange TxDummy for data */
+               ret = jornada_ssp_byte(TXDUMMY);
+
+       return ret;
+};
+EXPORT_SYMBOL(jornada_ssp_inout);
+
+/**
+ * jornada_ssp_start - enable mcu
+ *
+ */
+int jornada_ssp_start()
+{
+       spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags);
+       GPCR = GPIO_GPIO25;
+       udelay(50);
+       return 0;
+};
+EXPORT_SYMBOL(jornada_ssp_start);
+
+/**
+ * jornada_ssp_end - disable mcu and turn off lock
+ *
+ */
+int jornada_ssp_end()
+{
+       GPSR = GPIO_GPIO25;
+       spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags);
+       return 0;
+};
+EXPORT_SYMBOL(jornada_ssp_end);
+
+static int __init jornada_ssp_probe(struct platform_device *dev)
+{
+       int ret;
+
+       GPSR = GPIO_GPIO25;
+
+       ret = ssp_init();
+
+       /* worked fine, lets not bother with anything else */
+       if (!ret) {
+               printk(KERN_INFO "SSP: device initialized with irq\n");
+               return ret;
+       }
+
+       printk(KERN_WARNING "SSP: initialization failed, trying non-irq solution \n");
+
+       /* init of Serial 4 port */
+       Ser4MCCR0 = 0;
+       Ser4SSCR0 = 0x0387;
+       Ser4SSCR1 = 0x18;
+
+       /* clear out any left over data */
+       ssp_flush();
+
+       /* enable MCU */
+       jornada_ssp_start();
+
+       /* see if return value makes sense */
+       ret = jornada_ssp_inout(GETBRIGHTNESS);
+
+       /* seems like it worked, just feed it with TxDummy to get rid of data */
+       if (ret == TxDummy)
+               jornada_ssp_inout(TXDUMMY);
+
+       jornada_ssp_end();
+
+       /* failed, lets just kill everything */
+       if (ret == -ETIMEDOUT) {
+               printk(KERN_WARNING "SSP: attempts failed, bailing\n");
+               ssp_exit();
+               return -ENODEV;
+       }
+
+       /* all fine */
+       printk(KERN_INFO "SSP: device initialized\n");
+       return 0;
+};
+
+static int jornada_ssp_remove(struct platform_device *dev)
+{
+       /* Note that this doesnt actually remove the driver, since theres nothing to remove
+        * It just makes sure everything is turned off */
+       GPSR = GPIO_GPIO25;
+       ssp_exit();
+       return 0;
+};
+
+struct platform_driver jornadassp_driver = {
+       .probe  = jornada_ssp_probe,
+       .remove = jornada_ssp_remove,
+       .driver = {
+               .name   = "jornada_ssp",
+       },
+};
+
+static int __init jornada_ssp_init(void)
+{
+       return platform_driver_register(&jornadassp_driver);
+}
index 3a0a1ee2542d05535c860f3d0cadb78e0a9a736d..9f1ed15093016b3ebd88a204795efca7d026946b 100644 (file)
@@ -292,6 +292,8 @@ static struct platform_device *devices[] __initdata = {
        &smc91x_device,
 };
 
+extern void sa1110_mb_disable(void);
+
 static int __init neponset_init(void)
 {
        platform_driver_register(&neponset_device_driver);
index e7904bc92c73f846abda2b872f3c3e86139c0cfd..12161ae445dadecae15361fbd5e68a7241b7f1b1 100644 (file)
@@ -345,13 +345,14 @@ config CPU_XSC3
 # ARMv6
 config CPU_V6
        bool "Support ARM V6 processor"
-       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
+       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
+       default y if ARCH_MX3
        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_CACHE_V6
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
-       select CPU_HAS_ASID
+       select CPU_HAS_ASID if MMU
        select CPU_COPY_V6 if MMU
        select CPU_TLB_V6 if MMU
 
@@ -359,7 +360,7 @@ config CPU_V6
 config CPU_32v6K
        bool "Support ARM V6K processor extensions" if !SMP
        depends on CPU_V6
-       default y if SMP
+       default y if SMP && !ARCH_MX3
        help
          Say Y here if your ARMv6 processor supports the 'K' extension.
          This enables the kernel to use some instructions not present
@@ -377,7 +378,7 @@ config CPU_V7
        select CPU_CACHE_V7
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
-       select CPU_HAS_ASID
+       select CPU_HAS_ASID if MMU
        select CPU_COPY_V6 if MMU
        select CPU_TLB_V7 if MMU
 
@@ -405,6 +406,7 @@ config CPU_32v5
 
 config CPU_32v6
        bool
+       select TLS_REG_EMUL if !CPU_32v6K && !MMU
 
 config CPU_32v7
        bool
@@ -598,7 +600,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
@@ -611,12 +613,6 @@ config CPU_CACHE_ROUND_ROBIN
          Say Y here to use the predictable round-robin cache replacement
          policy.  Unless you specifically require this or are unsure, say N.
 
-config CPU_L2CACHE_DISABLE
-       bool "Disable level 2 cache"
-       depends on CPU_V7
-       help
-         Say Y here to disable the level 2 cache.  If unsure, say N.
-
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
index 08a36f1b35d29faf1d4f23b70b7ab96bea318801..b4e9b734e0bd939cddcdc392889368fe43f30846 100644 (file)
@@ -17,6 +17,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/init.h>
+#include <linux/spinlock.h>
 
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 #define CACHE_LINE_SIZE                32
 
 static void __iomem *l2x0_base;
+static DEFINE_SPINLOCK(l2x0_lock);
 
 static inline void sync_writel(unsigned long val, unsigned long reg,
                               unsigned long complete_mask)
 {
+       unsigned long flags;
+
+       spin_lock_irqsave(&l2x0_lock, flags);
        writel(val, l2x0_base + reg);
        /* wait for the operation to complete */
        while (readl(l2x0_base + reg) & complete_mask)
                ;
+       spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static inline void cache_sync(void)
index 3b5e47dc0c9737fe7e996769a45c416bb5201c1d..e5d61ee3d4a1bec9c309f3ba7b91de8ce4f9cb53 100644 (file)
@@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p)
        }
        if (i == ARRAY_SIZE(cache_policies))
                printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
+       if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+               printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
+               cachepolicy = CPOLICY_WRITEBACK;
+       }
        flush_cache_all();
        set_cr(cr_alignment);
 }
@@ -252,13 +256,15 @@ static void __init build_mem_type_table(void)
        int cpu_arch = cpu_architecture();
        int i;
 
+       if (cpu_arch < CPU_ARCH_ARMv6) {
 #if defined(CONFIG_CPU_DCACHE_DISABLE)
-       if (cachepolicy > CPOLICY_BUFFERED)
-               cachepolicy = CPOLICY_BUFFERED;
+               if (cachepolicy > CPOLICY_BUFFERED)
+                       cachepolicy = CPOLICY_BUFFERED;
 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
-       if (cachepolicy > CPOLICY_WRITETHROUGH)
-               cachepolicy = CPOLICY_WRITETHROUGH;
+               if (cachepolicy > CPOLICY_WRITETHROUGH)
+                       cachepolicy = CPOLICY_WRITETHROUGH;
 #endif
+       }
        if (cpu_arch < CPU_ARCH_ARMv5) {
                if (cachepolicy >= CPOLICY_WRITEALLOC)
                        cachepolicy = CPOLICY_WRITEBACK;
index 9f396b4fa0b7c67f95de6deb5a6c2a684f264f60..2b5ba396e3a63ee455e6b73bfff9176c78aef029 100644 (file)
@@ -31,12 +31,14 @@ EXPORT_SYMBOL(__cpuc_coherent_kern_range);
 EXPORT_SYMBOL(cpu_cache);
 #endif
 
+#ifdef CONFIG_MMU
 #ifndef MULTI_USER
 EXPORT_SYMBOL(__cpu_clear_user_page);
 EXPORT_SYMBOL(__cpu_copy_user_page);
 #else
 EXPORT_SYMBOL(cpu_user);
 #endif
+#endif
 
 /*
  * No module should need to touch the TLB (and currently
index 718f4782ee8b943e14d6a4bb6dc9f515ff9c47b4..e0acc5ae6f6ff4a501ee1d74991cdd7b58f2f332 100644 (file)
@@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area)
  *     - we are not using split page tables
  */
 ENTRY(cpu_v7_switch_mm)
+#ifdef CONFIG_MMU
        mov     r2, #0
        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
        orr     r0, r0, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
@@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm)
        isb
        mcr     p15, 0, r1, c13, c0, 1          @ set context ID
        isb
+#endif
        mov     pc, lr
 
 /*
@@ -109,6 +111,7 @@ ENTRY(cpu_v7_switch_mm)
  *       1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v7_set_pte_ext)
+#ifdef CONFIG_MMU
        str     r1, [r0], #-2048                @ linux version
 
        bic     r3, r1, #0x000003f0
@@ -136,6 +139,7 @@ ENTRY(cpu_v7_set_pte_ext)
 
        str     r3, [r0]
        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+#endif
        mov     pc, lr
 
 cpu_v7_name:
@@ -169,6 +173,7 @@ __v7_setup:
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 #endif
        dsb
+#ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
        mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
        orr     r4, r4, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
@@ -176,21 +181,12 @@ __v7_setup:
        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
        mov     r10, #0x1f                      @ domains 0, 1 = manager
        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
-#ifndef CONFIG_CPU_L2CACHE_DISABLE
-       @ L2 cache configuration in the L2 aux control register
-       mrc     p15, 1, r10, c9, c0, 2
-       bic     r10, r10, #(1 << 16)            @ L2 outer cache
-       mcr     p15, 1, r10, c9, c0, 2
-       @ L2 cache is enabled in the aux control register
-       mrc     p15, 0, r10, c1, c0, 1
-       orr     r10, r10, #2
-       mcr     p15, 0, r10, c1, c0, 1
 #endif
-       mrc     p15, 0, r0, c1, c0, 0           @ read control register
-       ldr     r10, cr1_clear                  @ get mask for bits to clear
-       bic     r0, r0, r10                     @ clear bits them
-       ldr     r10, cr1_set                    @ get mask for bits to set
-       orr     r0, r0, r10                     @ set them
+       adr     r5, v7_crval
+       ldmia   r5, {r5, r6}
+       mrc     p15, 0, r0, c1, c0, 0           @ read control register
+       bic     r0, r0, r5                      @ clear bits them
+       orr     r0, r0, r                     @ set them
        mov     pc, lr                          @ return to head.S:__ret
 
        /*
@@ -199,12 +195,9 @@ __v7_setup:
         * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
         *         0 110       0011 1.00 .111 1101 < we want
         */
-       .type   cr1_clear, #object
-       .type   cr1_set, #object
-cr1_clear:
-       .word   0x0120c302
-cr1_set:
-       .word   0x00c0387d
+       .type   v7_crval, #object
+v7_crval:
+       crval   clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
 
 __v7_setup_stack:
        .space  4 * 11                          @ 11 registers
index 100d57ad98ed82636c87282501e4adaaa73f70b1..ba3d21d8fba34c4c458a2d80b660e258ca06a2b3 100644 (file)
@@ -78,6 +78,13 @@ static struct irqaction iop_timer_irq = {
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 };
 
+static unsigned long iop_tick_rate;
+unsigned long get_iop_tick_rate(void)
+{
+       return iop_tick_rate;
+}
+EXPORT_SYMBOL(get_iop_tick_rate);
+
 void __init iop_init_time(unsigned long tick_rate)
 {
        u32 timer_ctl;
@@ -85,6 +92,7 @@ void __init iop_init_time(unsigned long tick_rate)
        ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
        ticks_per_usec = tick_rate / 1000000;
        next_jiffy_time = 0xffffffff;
+       iop_tick_rate = tick_rate;
 
        timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
                        IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
new file mode 100644 (file)
index 0000000..03a65c0
--- /dev/null
@@ -0,0 +1,20 @@
+if ARCH_MXC
+
+menu "Freescale MXC Implementations"
+
+choice
+       prompt "MXC/iMX System Type"
+       default 0
+
+config ARCH_MX3
+       bool "MX3-based"
+       help
+         This enables support for systems based on the Freescale i.MX3 family
+
+endchoice
+
+source "arch/arm/mach-mx3/Kconfig"
+
+endmenu
+
+endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
new file mode 100644 (file)
index 0000000..66ad9c2
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := irq.o
+
+obj-m :=
+obj-n :=
+obj-  :=
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
new file mode 100644 (file)
index 0000000..87d253b
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/common.h>
+
+/*!
+ * Disable interrupt number "irq" in the AVIC
+ *
+ * @param  irq          interrupt source number
+ */
+static void mxc_mask_irq(unsigned int irq)
+{
+       __raw_writel(irq, AVIC_INTDISNUM);
+}
+
+/*!
+ * Enable interrupt number "irq" in the AVIC
+ *
+ * @param  irq          interrupt source number
+ */
+static void mxc_unmask_irq(unsigned int irq)
+{
+       __raw_writel(irq, AVIC_INTENNUM);
+}
+
+static struct irq_chip mxc_avic_chip = {
+       .mask_ack = mxc_mask_irq,
+       .mask = mxc_mask_irq,
+       .unmask = mxc_unmask_irq,
+};
+
+/*!
+ * This function initializes the AVIC hardware and disables all the
+ * interrupts. It registers the interrupt enable and disable functions
+ * to the kernel for each interrupt source.
+ */
+void __init mxc_init_irq(void)
+{
+       int i;
+       u32 reg;
+
+       /* put the AVIC into the reset value with
+        * all interrupts disabled
+        */
+       __raw_writel(0, AVIC_INTCNTL);
+       __raw_writel(0x1f, AVIC_NIMASK);
+
+       /* disable all interrupts */
+       __raw_writel(0, AVIC_INTENABLEH);
+       __raw_writel(0, AVIC_INTENABLEL);
+
+       /* all IRQ no FIQ */
+       __raw_writel(0, AVIC_INTTYPEH);
+       __raw_writel(0, AVIC_INTTYPEL);
+       for (i = 0; i < MXC_MAX_INT_LINES; i++) {
+               set_irq_chip(i, &mxc_avic_chip);
+               set_irq_handler(i, handle_level_irq);
+               set_irq_flags(i, IRQF_VALID);
+       }
+
+       /* Set WDOG2's interrupt the highest priority level (bit 28-31) */
+       reg = __raw_readl(AVIC_NIPRIORITY6);
+       reg |= (0xF << 28);
+       __raw_writel(reg, AVIC_NIPRIORITY6);
+
+       printk(KERN_INFO "MXC IRQ initialized\n");
+}
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
new file mode 100644 (file)
index 0000000..31656c3
--- /dev/null
@@ -0,0 +1,104 @@
+# arch/arm/plat-s3c/Kconfig
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+config PLAT_S3C
+       bool
+       depends on ARCH_S3C2410
+       default y if ARCH_S3C2410
+       select NO_IOPORT
+       help
+         Base platform code for any Samsung S3C device
+
+# low-level serial option nodes
+
+config CPU_LLSERIAL_S3C2410_ONLY
+       bool
+       depends on ARCH_S3C2410
+       default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
+
+config CPU_LLSERIAL_S3C2440_ONLY
+       bool
+       depends on ARCH_S3C2410
+       default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
+
+config CPU_LLSERIAL_S3C2410
+       bool
+       depends on ARCH_S3C2410
+       help
+         Selected if there is an S3C2410 (or register compatible) serial
+         low-level implementation needed
+
+config CPU_LLSERIAL_S3C2440
+       bool
+       depends on ARCH_S3C2410
+       help
+         Selected if there is an S3C2440 (or register compatible) serial
+         low-level implementation needed
+
+# boot configurations
+
+comment "Boot options"
+
+config S3C_BOOT_WATCHDOG
+       bool "S3C Initialisation watchdog"
+       depends on PLAT_S3C && S3C2410_WATCHDOG
+       help
+         Say y to enable the watchdog during the kernel decompression
+         stage. If the kernel fails to uncompress, then the watchdog
+         will trigger a reset and the system should restart.
+
+config S3C_BOOT_ERROR_RESET
+       bool "S3C Reboot on decompression error"
+       depends on PLAT_S3C
+       help
+         Say y here to use the watchdog to reset the system if the
+         kernel decompressor detects an error during decompression.
+
+comment "Power management"
+
+config S3C2410_PM_DEBUG
+       bool "S3C2410 PM Suspend debug"
+       depends on PLAT_S3C && PM
+       help
+         Say Y here if you want verbose debugging from the PM Suspend and
+         Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+         for more information.
+
+config S3C2410_PM_CHECK
+       bool "S3C2410 PM Suspend Memory CRC"
+       depends on PLAT_S3C && PM && CRC32
+       help
+         Enable the PM code's memory area checksum over sleep. This option
+         will generate CRCs of all blocks of memory, and store them before
+         going to sleep. The blocks are then checked on resume for any
+         errors.
+
+         Note, this can take several seconds depending on memory size
+         and CPU speed.
+
+         See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+
+config S3C2410_PM_CHECK_CHUNKSIZE
+       int "S3C2410 PM Suspend CRC Chunksize (KiB)"
+       depends on PLAT_S3C && PM && S3C2410_PM_CHECK
+       default 64
+       help
+         Set the chunksize in Kilobytes of the CRC for checking memory
+         corruption over suspend and resume. A smaller value will mean that
+         the CRC data block will take more memory, but wil identify any
+         faults with better precision.
+
+         See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+
+config S3C_LOWLEVEL_UART_PORT
+       int "S3C UART to use for low-level messages"
+       depends on PLAT_S3C
+       default 0
+       help
+         Choice of which UART port to use for the low-level messages,
+         such as the `Uncompressing...` at start time. The value of
+         this configuration should be between zero and two. The port
+         must have been initialised by the boot-loader before use.
index b972f36d547ccd17190fd4cb698e1aa3e2656043..b66fb3c4e228c75852c7a159eeb986d11f6270b0 100644 (file)
@@ -10,7 +10,7 @@ config PLAT_S3C24XX
        default y if ARCH_S3C2410
        select NO_IOPORT
        help
-         Base platform code for any Samsung S3C device
+         Base platform code for any Samsung S3C24XX device
 
 if PLAT_S3C24XX
 
@@ -26,64 +26,6 @@ config PM_SIMTEC
          Common power management code for systems that are
          compatible with the Simtec style of power management
 
-config S3C2410_BOOT_WATCHDOG
-       bool "S3C2410 Initialisation watchdog"
-       depends on ARCH_S3C2410 && S3C2410_WATCHDOG
-       help
-         Say y to enable the watchdog during the kernel decompression
-         stage. If the kernel fails to uncompress, then the watchdog
-         will trigger a reset and the system should restart.
-
-config S3C2410_BOOT_ERROR_RESET
-       bool "S3C2410 Reboot on decompression error"
-       depends on ARCH_S3C2410
-       help
-         Say y here to use the watchdog to reset the system if the
-         kernel decompressor detects an error during decompression.
-
-config S3C2410_PM_DEBUG
-       bool "S3C2410 PM Suspend debug"
-       depends on ARCH_S3C2410 && PM
-       help
-         Say Y here if you want verbose debugging from the PM Suspend and
-         Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-         for more information.
-
-config S3C2410_PM_CHECK
-       bool "S3C2410 PM Suspend Memory CRC"
-       depends on ARCH_S3C2410 && PM && CRC32
-       help
-         Enable the PM code's memory area checksum over sleep. This option
-         will generate CRCs of all blocks of memory, and store them before
-         going to sleep. The blocks are then checked on resume for any
-         errors.
-
-         Note, this can take several seconds depending on memory size
-         and CPU speed.
-
-         See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-
-config S3C2410_PM_CHECK_CHUNKSIZE
-       int "S3C2410 PM Suspend CRC Chunksize (KiB)"
-       depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK
-       default 64
-       help
-         Set the chunksize in Kilobytes of the CRC for checking memory
-         corruption over suspend and resume. A smaller value will mean that
-         the CRC data block will take more memory, but wil identify any
-         faults with better precision.
-
-         See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-
-config S3C2410_LOWLEVEL_UART_PORT
-       int "S3C2410 UART to use for low-level messages"
-       default 0
-       help
-         Choice of which UART port to use for the low-level messages,
-         such as the `Uncompressing...` at start time. The value of
-         this configuration should be between zero and two. The port
-         must have been initialised by the boot-loader before use.
-
 config S3C2410_DMA
        bool "S3C2410 DMA support"
        depends on ARCH_S3C2410
index 7ed19b23ce56bf40ce310947d78de15decf044fc..398c7ac25296bc8fb63c71354e7fb2384d759c41 100644 (file)
@@ -38,7 +38,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
 
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <asm/plat-s3c24xx/common-smdk.h>
 #include <asm/plat-s3c24xx/devs.h>
index 8ce4904d313178e574188753416dc9750914083e..f513ab083b8f24c9106253b65c8fc185237cfad3 100644 (file)
@@ -38,7 +38,7 @@
 #include <asm/mach/map.h>
 
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/devs.h>
index 5875da0ae0eb89b6cae7158a977b906b59222728..e546e933b3f7648204b9715e88066df1b1b93ffb 100644 (file)
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-serial.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 /* Serial port registrations */
 
index 5692eccdf4d1dd036a056aa2fb22293131636976..eab1850616d860ef5488cbc4f5c489d0f763da49 100644 (file)
@@ -40,7 +40,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
index 767f2e9a3a555beff2d3e05388ad1ac9800f7590..3444b13afac52ad0a9694785f204f50c71c32ade 100644 (file)
@@ -30,7 +30,7 @@
 #include <asm/irq.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>
 #include <asm/arch/regs-dsc.h>
@@ -47,7 +47,6 @@ static struct map_desc s3c244x_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
        IODESC_ENT(TIMER),
        IODESC_ENT(WATCHDOG),
-       IODESC_ENT(LCD),
 };
 
 /* uart initialisation */
index 7b7ae790b00da07ebfede651cd10d2bfa1706e89..d47113bbc34cee98eb8895f0475d7a1c278f46bc 100644 (file)
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
  * reset the UART configuration, only enable if you really need this!
index b7667375bcec891912682260cd62e855d968085c..2ec1daaa0e537a6aed01f4aa62f5d7551ad3e8b8 100644 (file)
@@ -33,7 +33,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/arch/map.h>
-#include <asm/arch/regs-timer.h>
+#include <asm/plat-s3c/regs-timer.h>
 #include <asm/arch/regs-irq.h>
 #include <asm/mach/time.h>
 
index d4b7b229631d5b3fe9db079a3aed284f656beadf..0ac022f800a13578d97db2a6236f2cc16e86ef03 100644 (file)
@@ -74,14 +74,14 @@ vfp_support_entry:
 
        VFPFMRX r1, FPEXC               @ Is the VFP enabled?
        DBGSTR1 "fpexc %08x", r1
-       tst     r1, #FPEXC_ENABLE
+       tst     r1, #FPEXC_EN
        bne     look_for_VFP_exceptions @ VFP is already enabled
 
        DBGSTR1 "enable %x", r10
        ldr     r3, last_VFP_context_address
-       orr     r1, r1, #FPEXC_ENABLE   @ user FPEXC has the enable bit set
+       orr     r1, r1, #FPEXC_EN       @ user FPEXC has the enable bit set
        ldr     r4, [r3, r11, lsl #2]   @ last_VFP_context pointer
-       bic     r5, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled
+       bic     r5, r1, #FPEXC_EX       @ make sure exceptions are disabled
        cmp     r4, r10
        beq     check_for_exception     @ we are returning to the same
                                        @ process, so the registers are
@@ -124,7 +124,7 @@ no_old_VFP_process:
        VFPFMXR FPSCR, r5               @ restore status
 
 check_for_exception:
-       tst     r1, #FPEXC_EXCEPTION
+       tst     r1, #FPEXC_EX
        bne     process_exception       @ might as well handle the pending
                                        @ exception before retrying branch
                                        @ out before setting an FPEXC that
@@ -136,10 +136,10 @@ check_for_exception:
 
 
 look_for_VFP_exceptions:
-       tst     r1, #FPEXC_EXCEPTION
+       tst     r1, #FPEXC_EX
        bne     process_exception
        VFPFMRX r5, FPSCR
-       tst     r5, #FPSCR_IXE          @ IXE doesn't set FPEXC_EXCEPTION !
+       tst     r5, #FPSCR_IXE          @ IXE doesn't set FPEXC_EX !
        bne     process_exception
 
        @ Fall into hand on to next handler - appropriate coproc instr
index 1106b5f9cf197bffda116df9562511374ffd7bd9..04ddab2bd876e3485a0857a124a740fa8f0550be 100644 (file)
@@ -53,7 +53,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                 * case the thread migrates to a different CPU. The
                 * restoring is done lazily.
                 */
-               if ((fpexc & FPEXC_ENABLE) && last_VFP_context[cpu]) {
+               if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) {
                        vfp_save_state(last_VFP_context[cpu], fpexc);
                        last_VFP_context[cpu]->hard.cpu = cpu;
                }
@@ -70,7 +70,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                 * Always disable VFP so we can lazily save/restore the
                 * old state.
                 */
-               fmxr(FPEXC, fpexc & ~FPEXC_ENABLE);
+               fmxr(FPEXC, fpexc & ~FPEXC_EN);
                return NOTIFY_DONE;
        }
 
@@ -81,13 +81,13 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                 */
                memset(vfp, 0, sizeof(union vfp_state));
 
-               vfp->hard.fpexc = FPEXC_ENABLE;
+               vfp->hard.fpexc = FPEXC_EN;
                vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
 
                /*
                 * Disable VFP to ensure we initialise it first.
                 */
-               fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
+               fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
        }
 
        /* flush and release case: Per-thread VFP cleanup. */
@@ -229,7 +229,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
        /*
         * Enable access to the VFP so we can handle the bounce.
         */
-       fmxr(FPEXC, fpexc & ~(FPEXC_EXCEPTION|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));
+       fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));
 
        orig_fpscr = fpscr = fmrx(FPSCR);
 
@@ -248,7 +248,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
        /*
         * Modify fpscr to indicate the number of iterations remaining
         */
-       if (fpexc & FPEXC_EXCEPTION) {
+       if (fpexc & FPEXC_EX) {
                u32 len;
 
                len = fpexc + (1 << FPEXC_LENGTH_BIT);
index ad5cc5f6862fdff08746a91d5068dad490124c8b..16fb23125e96acdab10d128adda7181830fd93ea 100644 (file)
@@ -187,6 +187,22 @@ config PNX4008_WATCHDOG
 
          Say N if you are unsure.
 
+config IOP_WATCHDOG
+       tristate "IOP Watchdog"
+       depends on WATCHDOG && PLAT_IOP
+       select WATCHDOG_NOWAYOUT if (ARCH_IOP32X || ARCH_IOP33X)
+       help
+         Say Y here if to include support for the watchdog timer
+         in the Intel IOP3XX & IOP13XX I/O Processors.  This driver can
+         be built as a module by choosing M. The module will
+         be called iop_wdt.
+
+         Note: The IOP13XX watchdog does an Internal Bus Reset which will
+         affect both cores and the peripherals of the IOP.  The ATU-X
+         and/or ATUe configuration registers will remain intact, but if
+         operating as an Root Complex and/or Central Resource, the PCI-X
+         and/or PCIe busses will also be reset.  THIS IS A VERY BIG HAMMER.
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT
index 3907ec04a4e5f2ce729b90ac732eaa7c83ec9aec..bdb9d5e3bb41ece30f7924cc70adc3ca42518b71 100644 (file)
@@ -35,6 +35,7 @@ obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
 obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
 obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
 obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
+obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/char/watchdog/iop_wdt.c b/drivers/char/watchdog/iop_wdt.c
new file mode 100644 (file)
index 0000000..bbbd91a
--- /dev/null
@@ -0,0 +1,262 @@
+/*
+ * drivers/char/watchdog/iop_wdt.c
+ *
+ * WDT driver for Intel I/O Processors
+ * Copyright (C) 2005, Intel Corporation.
+ *
+ * Based on ixp4xx driver, Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ *     Curt E Bruns <curt.e.bruns@intel.com>
+ *     Peter Milne <peter.milne@d-tacq.com>
+ *     Dan Williams <dan.j.williams@intel.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/uaccess.h>
+#include <asm/hardware.h>
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+static unsigned long wdt_status;
+static unsigned long boot_status;
+
+#define WDT_IN_USE             0
+#define WDT_OK_TO_CLOSE                1
+#define WDT_ENABLED            2
+
+static unsigned long iop_watchdog_timeout(void)
+{
+       return (0xffffffffUL / get_iop_tick_rate());
+}
+
+/**
+ * wdt_supports_disable - determine if we are accessing a iop13xx watchdog
+ * or iop3xx by whether it has a disable command
+ */
+static int wdt_supports_disable(void)
+{
+       int can_disable;
+
+       if (IOP_WDTCR_EN_ARM != IOP_WDTCR_DIS_ARM)
+               can_disable = 1;
+       else
+               can_disable = 0;
+
+       return can_disable;
+}
+
+static void wdt_enable(void)
+{
+       /* Arm and enable the Timer to starting counting down from 0xFFFF.FFFF
+        * Takes approx. 10.7s to timeout
+        */
+       write_wdtcr(IOP_WDTCR_EN_ARM);
+       write_wdtcr(IOP_WDTCR_EN);
+}
+
+/* returns 0 if the timer was successfully disabled */
+static int wdt_disable(void)
+{
+       /* Stop Counting */
+       if (wdt_supports_disable()) {
+               write_wdtcr(IOP_WDTCR_DIS_ARM);
+               write_wdtcr(IOP_WDTCR_DIS);
+               clear_bit(WDT_ENABLED, &wdt_status);
+               printk(KERN_INFO "WATCHDOG: Disabled\n");
+               return 0;
+       } else
+               return 1;
+}
+
+static int iop_wdt_open(struct inode *inode, struct file *file)
+{
+       if (test_and_set_bit(WDT_IN_USE, &wdt_status))
+               return -EBUSY;
+
+       clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+       wdt_enable();
+
+       set_bit(WDT_ENABLED, &wdt_status);
+
+       return nonseekable_open(inode, file);
+}
+
+static ssize_t
+iop_wdt_write(struct file *file, const char *data, size_t len,
+                 loff_t *ppos)
+{
+       if (len) {
+               if (!nowayout) {
+                       size_t i;
+
+                       clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+                       for (i = 0; i != len; i++) {
+                               char c;
+
+                               if (get_user(c, data + i))
+                                       return -EFAULT;
+                               if (c == 'V')
+                                       set_bit(WDT_OK_TO_CLOSE, &wdt_status);
+                       }
+               }
+               wdt_enable();
+       }
+
+       return len;
+}
+
+static struct watchdog_info ident = {
+       .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
+       .identity = "iop watchdog",
+};
+
+static int
+iop_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+                 unsigned long arg)
+{
+       int options;
+       int ret = -ENOTTY;
+
+       switch (cmd) {
+       case WDIOC_GETSUPPORT:
+               if (copy_to_user
+                   ((struct watchdog_info *)arg, &ident, sizeof ident))
+                       ret = -EFAULT;
+               else
+                       ret = 0;
+               break;
+
+       case WDIOC_GETSTATUS:
+               ret = put_user(0, (int *)arg);
+               break;
+
+       case WDIOC_GETBOOTSTATUS:
+               ret = put_user(boot_status, (int *)arg);
+               break;
+
+       case WDIOC_GETTIMEOUT:
+               ret = put_user(iop_watchdog_timeout(), (int *)arg);
+               break;
+
+       case WDIOC_KEEPALIVE:
+               wdt_enable();
+               ret = 0;
+               break;
+
+       case WDIOC_SETOPTIONS:
+               if (get_user(options, (int *)arg))
+                       return -EFAULT;
+
+               if (options & WDIOS_DISABLECARD) {
+                       if (!nowayout) {
+                               if (wdt_disable() == 0) {
+                                       set_bit(WDT_OK_TO_CLOSE, &wdt_status);
+                                       ret = 0;
+                               } else
+                                       ret = -ENXIO;
+                       } else
+                               ret = 0;
+               }
+
+               if (options & WDIOS_ENABLECARD) {
+                       wdt_enable();
+                       ret = 0;
+               }
+               break;
+       }
+
+       return ret;
+}
+
+static int iop_wdt_release(struct inode *inode, struct file *file)
+{
+       int state = 1;
+       if (test_bit(WDT_OK_TO_CLOSE, &wdt_status))
+               if (test_bit(WDT_ENABLED, &wdt_status))
+                       state = wdt_disable();
+
+       /* if the timer is not disbaled reload and notify that we are still
+        * going down
+        */
+       if (state != 0) {
+               wdt_enable();
+               printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - "
+                      "reset in %lu seconds\n", iop_watchdog_timeout());
+       }
+
+       clear_bit(WDT_IN_USE, &wdt_status);
+       clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+       return 0;
+}
+
+static const struct file_operations iop_wdt_fops = {
+       .owner = THIS_MODULE,
+       .llseek = no_llseek,
+       .write = iop_wdt_write,
+       .ioctl = iop_wdt_ioctl,
+       .open = iop_wdt_open,
+       .release = iop_wdt_release,
+};
+
+static struct miscdevice iop_wdt_miscdev = {
+       .minor = WATCHDOG_MINOR,
+       .name = "watchdog",
+       .fops = &iop_wdt_fops,
+};
+
+static int __init iop_wdt_init(void)
+{
+       int ret;
+
+       ret = misc_register(&iop_wdt_miscdev);
+       if (ret == 0)
+               printk("iop watchdog timer: timeout %lu sec\n",
+                      iop_watchdog_timeout());
+
+       /* check if the reset was caused by the watchdog timer */
+       boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0;
+
+       /* Configure Watchdog Timeout to cause an Internal Bus (IB) Reset
+        * NOTE: An IB Reset will Reset both cores in the IOP342
+        */
+       write_wdtsr(IOP13XX_WDTCR_IB_RESET);
+
+       return ret;
+}
+
+static void __exit iop_wdt_exit(void)
+{
+       misc_deregister(&iop_wdt_miscdev);
+}
+
+module_init(iop_wdt_init);
+module_exit(iop_wdt_exit);
+
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
+
+MODULE_AUTHOR("Curt E Bruns <curt.e.bruns@intel.com>");
+MODULE_DESCRIPTION("iop watchdog timer driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
index f21148e7b579ec3e2242b77394d3431e0a0d3700..80f33b6d57138145b6cc41a2a9654803cc0db045 100644 (file)
@@ -36,7 +36,6 @@
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/slab.h>
@@ -75,7 +74,7 @@ static void ether1_timeout(struct net_device *dev);
 
 /* ------------------------------------------------------------------------- */
 
-static char version[] __initdata = "ether1 ethernet driver (c) 2000 Russell King v1.07\n";
+static char version[] __devinitdata = "ether1 ethernet driver (c) 2000 Russell King v1.07\n";
 
 #define BUS_16 16
 #define BUS_8  8
index a7cac695a9bddca757bcd5e22a590f44a2882a6a..3805506a3ab8475f0bf84629b687a2b2da8d7ac1 100644 (file)
@@ -51,7 +51,6 @@
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/slab.h>
@@ -69,7 +68,7 @@
 #include <asm/ecard.h>
 #include <asm/io.h>
 
-static char version[] __initdata = "ether3 ethernet driver (c) 1995-2000 R.M.King v1.17\n";
+static char version[] __devinitdata = "ether3 ethernet driver (c) 1995-2000 R.M.King v1.17\n";
 
 #include "ether3.h"
 
index 769ba69451f4f7887037d2c43fea94b4295a61db..0d37d9d1fd787e2631c53b6982137fe38c6496d2 100644 (file)
@@ -31,7 +31,6 @@
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/slab.h>
index cf9a21cea6d9309b88aa4cb69b2d2addc53aa7a1..49d838e90a241260ea6e2a907b5c7d45c6839753 100644 (file)
@@ -24,7 +24,7 @@
 
 #define CUMANASCSI_PUBLIC_RELEASE 1
 
-#define NCR5380_implementation_fields  int port, ctrl
+#define priv(host)                     ((struct NCR5380_hostdata *)(host)->hostdata)
 #define NCR5380_local_declare()                struct Scsi_Host *_instance
 #define NCR5380_setup(instance)                _instance = instance
 #define NCR5380_read(reg)              cumanascsi_read(_instance, reg)
 #define NCR5380_queue_command          cumanascsi_queue_command
 #define NCR5380_proc_info              cumanascsi_proc_info
 
+#define NCR5380_implementation_fields  \
+       unsigned ctrl;                  \
+       void __iomem *base;             \
+       void __iomem *dma
+
 #define BOARD_NORMAL   0
 #define BOARD_NCR53C400        1
 
@@ -47,192 +52,162 @@ const char *cumanascsi_info(struct Scsi_Host *spnt)
        return "";
 }
 
-#ifdef NOT_EFFICIENT
-#define CTRL(p,v)     outb(*ctrl = (v), (p) - 577)
-#define STAT(p)       inb((p)+1)
-#define IN(p)         inb((p))
-#define OUT(v,p)      outb((v), (p))
-#else
-#define CTRL(p,v)      (p[-2308] = (*ctrl = (v)))
-#define STAT(p)                (p[4])
-#define IN(p)          (*(p))
-#define IN2(p)         ((unsigned short)(*(volatile unsigned long *)(p)))
-#define OUT(v,p)       (*(p) = (v))
-#define OUT2(v,p)      (*((volatile unsigned long *)(p)) = (v))
-#endif
-#define L(v)           (((v)<<16)|((v) & 0x0000ffff))
-#define H(v)           (((v)>>16)|((v) & 0xffff0000))
+#define CTRL   0x16fc
+#define STAT   0x2004
+#define L(v)   (((v)<<16)|((v) & 0x0000ffff))
+#define H(v)   (((v)>>16)|((v) & 0xffff0000))
 
 static inline int
-NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *addr, int len)
+NCR5380_pwrite(struct Scsi_Host *host, unsigned char *addr, int len)
 {
-  int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
-  int oldctrl = *ctrl;
   unsigned long *laddr;
-#ifdef NOT_EFFICIENT
-  int iobase = instance->io_port;
-  int dma_io = iobase & ~(0x3C0000>>2);
-#else
-  volatile unsigned char *iobase = (unsigned char *)ioaddr(instance->io_port);
-  volatile unsigned char *dma_io = (unsigned char *)((int)iobase & ~0x3C0000);
-#endif
+  void __iomem *dma = priv(host)->dma + 0x2000;
 
   if(!len) return 0;
 
-  CTRL(iobase, 0x02);
+  writeb(0x02, priv(host)->base + CTRL);
   laddr = (unsigned long *)addr;
   while(len >= 32)
   {
-    int status;
+    unsigned int status;
     unsigned long v;
-    status = STAT(iobase);
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(!(status & 0x40))
       continue;
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
     len -= 32;
     if(len == 0)
       break;
   }
 
   addr = (unsigned char *)laddr;
-  CTRL(iobase, 0x12);
+  writeb(0x12, priv(host)->base + CTRL);
+
   while(len > 0)
   {
-    int status;
-    status = STAT(iobase);
+    unsigned int status;
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      OUT(*addr++, dma_io);
+      writeb(*addr++, dma);
       if(--len == 0)
         break;
     }
 
-    status = STAT(iobase);
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      OUT(*addr++, dma_io);
+      writeb(*addr++, dma);
       if(--len == 0)
         break;
     }
   }
 end:
-  CTRL(iobase, oldctrl|0x40);
+  writeb(priv(host)->ctrl | 0x40, priv(host)->base + CTRL);
   return len;
 }
 
 static inline int
-NCR5380_pread(struct Scsi_Host *instance, unsigned char *addr, int len)
+NCR5380_pread(struct Scsi_Host *host, unsigned char *addr, int len)
 {
-  int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
-  int oldctrl = *ctrl;
   unsigned long *laddr;
-#ifdef NOT_EFFICIENT
-  int iobase = instance->io_port;
-  int dma_io = iobase & ~(0x3C0000>>2);
-#else
-  volatile unsigned char *iobase = (unsigned char *)ioaddr(instance->io_port);
-  volatile unsigned char *dma_io = (unsigned char *)((int)iobase & ~0x3C0000);
-#endif
+  void __iomem *dma = priv(host)->dma + 0x2000;
 
   if(!len) return 0;
 
-  CTRL(iobase, 0x00);
+  writeb(0x00, priv(host)->base + CTRL);
   laddr = (unsigned long *)addr;
   while(len >= 32)
   {
-    int status;
-    status = STAT(iobase);
+    unsigned int status;
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(!(status & 0x40))
       continue;
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
     len -= 32;
     if(len == 0)
       break;
   }
 
   addr = (unsigned char *)laddr;
-  CTRL(iobase, 0x10);
+  writeb(0x10, priv(host)->base + CTRL);
+
   while(len > 0)
   {
-    int status;
-    status = STAT(iobase);
+    unsigned int status;
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      *addr++ = IN(dma_io);
+      *addr++ = readb(dma);
       if(--len == 0)
         break;
     }
 
-    status = STAT(iobase);
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      *addr++ = IN(dma_io);
+      *addr++ = readb(dma);
       if(--len == 0)
         break;
     }
   }
 end:
-  CTRL(iobase, oldctrl|0x40);
+  writeb(priv(host)->ctrl | 0x40, priv(host)->base + CTRL);
   return len;
 }
 
-#undef STAT
-#undef CTRL
-#undef IN
-#undef OUT
+static unsigned char cumanascsi_read(struct Scsi_Host *host, unsigned int reg)
+{
+       void __iomem *base = priv(host)->base;
+       unsigned char val;
 
-#define CTRL(p,v) outb(*ctrl = (v), (p) - 577)
+       writeb(0, base + CTRL);
 
-static char cumanascsi_read(struct Scsi_Host *instance, int reg)
-{
-       unsigned int iobase = instance->io_port;
-       int i;
-       int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
+       val = readb(base + 0x2100 + (reg << 2));
 
-       CTRL(iobase, 0);
-       i = inb(iobase + 64 + reg);
-       CTRL(iobase, 0x40);
+       priv(host)->ctrl = 0x40;
+       writeb(0x40, base + CTRL);
 
-       return i;
+       return val;
 }
 
-static void cumanascsi_write(struct Scsi_Host *instance, int reg, int value)
+static void cumanascsi_write(struct Scsi_Host *host, unsigned int reg, unsigned int value)
 {
-       int iobase = instance->io_port;
-       int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
+       void __iomem *base = priv(host)->base;
 
-       CTRL(iobase, 0);
-       outb(value, iobase + 64 + reg);
-       CTRL(iobase, 0x40);
-}
+       writeb(0, base + CTRL);
 
-#undef CTRL
+       writeb(value, base + 0x2100 + (reg << 2));
+
+       priv(host)->ctrl = 0x40;
+       writeb(0x40, base + CTRL);
+}
 
 #include "../NCR5380.c"
 
@@ -256,32 +231,46 @@ static int __devinit
 cumanascsi1_probe(struct expansion_card *ec, const struct ecard_id *id)
 {
        struct Scsi_Host *host;
-       int ret = -ENOMEM;
+       int ret;
 
-       host = scsi_host_alloc(&cumanascsi_template, sizeof(struct NCR5380_hostdata));
-       if (!host)
+       ret = ecard_request_resources(ec);
+       if (ret)
                goto out;
 
-        host->io_port = ecard_address(ec, ECARD_IOC, ECARD_SLOW) + 0x800;
+       host = scsi_host_alloc(&cumanascsi_template, sizeof(struct NCR5380_hostdata));
+       if (!host) {
+               ret = -ENOMEM;
+               goto out_release;
+       }
+
+       priv(host)->base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCSLOW),
+                                  ecard_resource_len(ec, ECARD_RES_IOCSLOW));
+       priv(host)->dma = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
+                                 ecard_resource_len(ec, ECARD_RES_MEMC));
+       if (!priv(host)->base || !priv(host)->dma) {
+               ret = -ENOMEM;
+               goto out_unmap;
+       }
+
        host->irq = ec->irq;
 
        NCR5380_init(host, 0);
 
+        priv(host)->ctrl = 0;
+        writeb(0, priv(host)->base + CTRL);
+
        host->n_io_port = 255;
        if (!(request_region(host->io_port, host->n_io_port, "CumanaSCSI-1"))) {
                ret = -EBUSY;
-               goto out_free;
+               goto out_unmap;
        }
 
-        ((struct NCR5380_hostdata *)host->hostdata)->ctrl = 0;
-        outb(0x00, host->io_port - 577);
-
        ret = request_irq(host->irq, cumanascsi_intr, IRQF_DISABLED,
                          "CumanaSCSI-1", host);
        if (ret) {
                printk("scsi%d: IRQ%d not free: %d\n",
                    host->host_no, host->irq, ret);
-               goto out_release;
+               goto out_unmap;
        }
 
        printk("scsi%d: at port 0x%08lx irq %d",
@@ -301,10 +290,12 @@ cumanascsi1_probe(struct expansion_card *ec, const struct ecard_id *id)
 
  out_free_irq:
        free_irq(host->irq, host);
- out_release:
-       release_region(host->io_port, host->n_io_port);
- out_free:
+ out_unmap:
+       iounmap(priv(host)->base);
+       iounmap(priv(host)->dma);
        scsi_host_put(host);
+ out_release:
+       ecard_release_resources(ec);
  out:
        return ret;
 }
@@ -318,8 +309,10 @@ static void __devexit cumanascsi1_remove(struct expansion_card *ec)
        scsi_remove_host(host);
        free_irq(host->irq, host);
        NCR5380_exit(host);
-       release_region(host->io_port, host->n_io_port);
+       iounmap(priv(host)->base);
+       iounmap(priv(host)->dma);
        scsi_host_put(host);
+       ecard_release_resources(ec);
 }
 
 static const struct ecard_id cumanascsi1_cids[] = {
index 378e7af0c5d6760750fe18c9105b1707fdf05527..5265a9884338b90e0d5e8e551f7d0487e6b7c61f 100644 (file)
 #include "../scsi.h"
 #include <scsi/scsi_host.h>
 
-#define NCR5380_implementation_fields  int port, ctrl
-#define NCR5380_local_declare()                struct Scsi_Host *_instance
-#define NCR5380_setup(instance)                _instance = instance
+#define priv(host)                     ((struct NCR5380_hostdata *)(host)->hostdata)
 
-#define NCR5380_read(reg)              ecoscsi_read(_instance, reg)
-#define NCR5380_write(reg, value)      ecoscsi_write(_instance, reg, value)
+#define NCR5380_local_declare()                void __iomem *_base
+#define NCR5380_setup(host)            _base = priv(host)->base
+
+#define NCR5380_read(reg)              ({ writeb(reg | 8, _base); readb(_base + 4); })
+#define NCR5380_write(reg, value)      ({ writeb(reg | 8, _base); writeb(value, _base + 4); })
 
 #define NCR5380_intr                   ecoscsi_intr
 #define NCR5380_queue_command          ecoscsi_queue_command
 #define NCR5380_proc_info              ecoscsi_proc_info
 
+#define NCR5380_implementation_fields  \
+       void __iomem *base
+
 #include "../NCR5380.h"
 
 #define ECOSCSI_PUBLIC_RELEASE 1
 
-static char ecoscsi_read(struct Scsi_Host *instance, int reg)
-{
-  int iobase = instance->io_port;
-  outb(reg | 8, iobase);
-  return inb(iobase + 1);
-}
-
-static void ecoscsi_write(struct Scsi_Host *instance, int reg, int value)
-{
-  int iobase = instance->io_port;
-  outb(reg | 8, iobase);
-  outb(value, iobase + 1);
-}
-
 /*
  * Function : ecoscsi_setup(char *str, int *ints)
  *
@@ -82,73 +72,6 @@ const char * ecoscsi_info (struct Scsi_Host *spnt)
        return "";
 }
 
-#if 0
-#define STAT(p) inw(p + 144)
-
-static inline int NCR5380_pwrite(struct Scsi_Host *host, unsigned char *addr,
-              int len)
-{
-  int iobase = host->io_port;
-printk("writing %p len %d\n",addr, len);
-  if(!len) return -1;
-
-  while(1)
-  {
-    int status;
-    while(((status = STAT(iobase)) & 0x100)==0);
-  }
-}
-
-static inline int NCR5380_pread(struct Scsi_Host *host, unsigned char *addr,
-              int len)
-{
-  int iobase = host->io_port;
-  int iobase2= host->io_port + 0x100;
-  unsigned char *start = addr;
-  int s;
-printk("reading %p len %d\n",addr, len);
-  outb(inb(iobase + 128), iobase + 135);
-  while(len > 0)
-  {
-    int status,b,i, timeout;
-    timeout = 0x07FFFFFF;
-    while(((status = STAT(iobase)) & 0x100)==0)
-    {
-      timeout--;
-      if(status & 0x200 || !timeout)
-      {
-        printk("status = %p\n",status);
-        outb(0, iobase + 135);
-        return 1;
-      }
-    }
-    if(len >= 128)
-    {
-      for(i=0; i<64; i++)
-      {
-        b = inw(iobase + 136);
-        *addr++ = b;
-        *addr++ = b>>8;
-      }
-      len -= 128;
-    }
-    else
-    {
-      b = inw(iobase + 136);
-      *addr ++ = b;
-      len -= 1;
-      if(len)
-        *addr ++ = b>>8;
-      len -= 1;
-    }
-  }
-  outb(0, iobase + 135);
-  printk("first bytes = %02X %02X %02X %20X %02X %02X %02X\n",*start, start[1], start[2], start[3], start[4], start[5], start[6]);
-  return 1;
-}
-#endif
-#undef STAT
-
 #define BOARD_NORMAL   0
 #define BOARD_NCR53C400        1
 
@@ -173,25 +96,36 @@ static struct Scsi_Host *host;
 
 static int __init ecoscsi_init(void)
 {
+       void __iomem *_base;
+       int ret;
 
-       host = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata));
-       if (!host)
-               return 0;
+       if (!request_mem_region(0x33a0000, 4096, "ecoscsi")) {
+               ret = -EBUSY;
+               goto out;
+       }
 
-       host->io_port = 0x80ce8000;
-       host->n_io_port = 144;
-       host->irq = IRQ_NONE;
+       _base = ioremap(0x33a0000, 4096);
+       if (!_base) {
+               ret = -ENOMEM;
+               goto out_release;
+       }
 
-       if (!(request_region(host->io_port, host->n_io_port, "ecoscsi")) )
-               goto unregister_scsi;
+       NCR5380_write(MODE_REG, 0x20);          /* Is it really SCSI? */
+       if (NCR5380_read(MODE_REG) != 0x20)     /* Write to a reg.    */
+               goto out_unmap;
 
-       ecoscsi_write(host, MODE_REG, 0x20);            /* Is it really SCSI? */
-       if (ecoscsi_read(host, MODE_REG) != 0x20) /* Write to a reg.    */
-               goto release_reg;
+       NCR5380_write(MODE_REG, 0x00);          /* it back.           */
+       if (NCR5380_read(MODE_REG) != 0x00)
+               goto out_unmap;
 
-       ecoscsi_write(host, MODE_REG, 0x00 );           /* it back.           */
-       if (ecoscsi_read(host, MODE_REG) != 0x00)
-               goto release_reg;
+       host = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata));
+       if (!host) {
+               ret = -ENOMEM;
+               goto out_unmap;
+       }
+
+       priv(host)->base = _base;
+       host->irq = IRQ_NONE;
 
        NCR5380_init(host, 0);
 
@@ -206,24 +140,20 @@ static int __init ecoscsi_init(void)
        scsi_scan_host(host);
        return 0;
 
-release_reg:
-       release_region(host->io_port, host->n_io_port);
-unregister_scsi:
-       scsi_host_put(host);
-       return -ENODEV;
+ out_unmap:
+       iounmap(_base);
+ out_release:
+       release_mem_region(0x33a0000, 4096);
+ out:
+       return ret;
 }
 
 static void __exit ecoscsi_exit(void)
 {
        scsi_remove_host(host);
-
-       if (shpnt->irq != IRQ_NONE)
-               free_irq(shpnt->irq, NULL);
        NCR5380_exit(host);
-       if (shpnt->io_port)
-               release_region(shpnt->io_port, shpnt->n_io_port);
-
        scsi_host_put(host);
+       release_mem_region(0x33a0000, 4096);
        return 0;
 }
 
index c21b8392c92837ec2af15d43acbb8acdd1bbe22d..849cdf89f7bbdcada963da8678d4b6a5291a4ea5 100644 (file)
 
 #define OAKSCSI_PUBLIC_RELEASE 1
 
-#define NCR5380_read(reg)              oakscsi_read(_instance, reg)
-#define NCR5380_write(reg, value)      oakscsi_write(_instance, reg, value)
+#define priv(host)                     ((struct NCR5380_hostdata *)(host)->hostdata)
+#define NCR5380_local_declare()                void __iomem *_base
+#define NCR5380_setup(host)            _base = priv(host)->base
+
+#define NCR5380_read(reg)              readb(_base + ((reg) << 2))
+#define NCR5380_write(reg, value)      writeb(value, _base + ((reg) << 2))
 #define NCR5380_intr                   oakscsi_intr
 #define NCR5380_queue_command          oakscsi_queue_command
 #define NCR5380_proc_info              oakscsi_proc_info
 
-#define NCR5380_implementation_fields  int port, ctrl
-#define NCR5380_local_declare()                struct Scsi_Host *_instance
-#define NCR5380_setup(instance)                _instance = instance
+#define NCR5380_implementation_fields  \
+       void __iomem *base
 
 #define BOARD_NORMAL   0
 #define BOARD_NCR53C400        1
 #include "../NCR5380.h"
 
 #undef START_DMA_INITIATOR_RECEIVE_REG
-#define START_DMA_INITIATOR_RECEIVE_REG (7 + 128)
+#define START_DMA_INITIATOR_RECEIVE_REG        (128 + 7)
 
 const char * oakscsi_info (struct Scsi_Host *spnt)
 {
        return "";
 }
 
-#define STAT(p)   inw(p + 144)
-extern void inswb(int from, void *to, int len);
+#define STAT   ((128 + 16) << 2)
+#define DATA   ((128 + 8) << 2)
 
 static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *addr,
               int len)
 {
-  int iobase = instance->io_port;
+  void __iomem *base = priv(instance)->base;
+
 printk("writing %p len %d\n",addr, len);
   if(!len) return -1;
 
   while(1)
   {
     int status;
-    while(((status = STAT(iobase)) & 0x100)==0);
+    while (((status = readw(base + STAT)) & 0x100)==0);
   }
 }
 
 static inline int NCR5380_pread(struct Scsi_Host *instance, unsigned char *addr,
               int len)
 {
-  int iobase = instance->io_port;
+  void __iomem *base = priv(instance)->base;
 printk("reading %p len %d\n", addr, len);
   while(len > 0)
   {
-    int status, timeout;
+    unsigned int status, timeout;
     unsigned long b;
     
     timeout = 0x01FFFFFF;
     
-    while(((status = STAT(iobase)) & 0x100)==0)
+    while (((status = readw(base + STAT)) & 0x100)==0)
     {
       timeout--;
       if(status & 0x200 || !timeout)
       {
-        printk("status = %08X\n",status);
+        printk("status = %08X\n", status);
         return 1;
       }
     }
+
     if(len >= 128)
     {
-      inswb(iobase + 136, addr, 128);
+      readsw(base + DATA, addr, 128);
       addr += 128;
       len -= 128;
     }
     else
     {
-      b = (unsigned long) inw(iobase + 136);
+      b = (unsigned long) readw(base + DATA);
       *addr ++ = b;
       len -= 1;
       if(len)
@@ -103,10 +108,8 @@ printk("reading %p len %d\n", addr, len);
   return 0;
 }
 
-#define oakscsi_read(instance,reg)     (inb((instance)->io_port + (reg)))
-#define oakscsi_write(instance,reg,val)        (outb((val), (instance)->io_port + (reg)))
-
 #undef STAT
+#undef DATA
 
 #include "../NCR5380.c"
 
@@ -132,18 +135,26 @@ oakscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
        struct Scsi_Host *host;
        int ret = -ENOMEM;
 
-       host = scsi_host_alloc(&oakscsi_template, sizeof(struct NCR5380_hostdata));
-       if (!host)
+       ret = ecard_request_resources(ec);
+       if (ret)
                goto out;
 
-       host->io_port = ecard_address(ec, ECARD_MEMC, 0);
+       host = scsi_host_alloc(&oakscsi_template, sizeof(struct NCR5380_hostdata));
+       if (!host) {
+               ret = -ENOMEM;
+               goto release;
+       }
+
+       priv(host)->base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
+                                  ecard_resource_len(ec, ECARD_RES_MEMC));
+       if (!priv(host)->base) {
+               ret = -ENOMEM;
+               goto unreg;
+       }
+
        host->irq = IRQ_NONE;
        host->n_io_port = 255;
 
-       ret = -EBUSY;
-       if (!request_region (host->io_port, host->n_io_port, "Oak SCSI"))
-               goto unreg;
-
        NCR5380_init(host, 0);
 
        printk("scsi%d: at port 0x%08lx irqs disabled",
@@ -156,15 +167,17 @@ oakscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 
        ret = scsi_add_host(host, &ec->dev);
        if (ret)
-               goto out_release;
+               goto out_unmap;
 
        scsi_scan_host(host);
        goto out;
 
- out_release:
-       release_region(host->io_port, host->n_io_port);
+ out_unmap:
+       iounmap(priv(host)->base);
  unreg:
        scsi_host_put(host);
+ release:
+       ecard_release_resources(ec);
  out:
        return ret;
 }
@@ -177,8 +190,9 @@ static void __devexit oakscsi_remove(struct expansion_card *ec)
        scsi_remove_host(host);
 
        NCR5380_exit(host);
-       release_region(host->io_port, host->n_io_port);
+       iounmap(priv(host)->base);
        scsi_host_put(host);
+       ecard_release_resources(ec);
 }
 
 static const struct ecard_id oakscsi_cids[] = {
index e42faa4e42829f9f06387ea5e8035f838b5bbd19..dc1967176fe228811b77a27fb2fcb82c41c8274c 100644 (file)
@@ -1114,8 +1114,8 @@ static int __init imx_serial_init(void)
 
 static void __exit imx_serial_exit(void)
 {
-       uart_unregister_driver(&imx_reg);
        platform_driver_unregister(&serial_imx_driver);
+       uart_unregister_driver(&imx_reg);
 }
 
 module_init(imx_serial_init);
index 10bc0209cd661a7b68f7bb7853b0aa10f20751ef..3f26c4b2f322a0e4140a8987c4b21c42894c84b3 100644 (file)
@@ -78,7 +78,7 @@
 
 #include <asm/hardware.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 /* structures */
index 40a9876b661a1162aa11cbd401e7e872c611c390..c2e11cc374ba6a28a1b33bf94f13a523bc73df90 100644 (file)
@@ -26,6 +26,9 @@
 #define AT91_MCI_MR            0x04            /* Mode Register */
 #define                AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
 #define                AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
+#define                AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define                AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define                AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
 #define                AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
 #define                AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
 #define                AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
index d4e4f828577cc51c41bb23221fd15960026f9d88..52b7fab7ef60555f58dd916fafb54891580394d3 100644 (file)
@@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void)
        return id;
 }
 
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+       u32 val;
+       asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+       return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+       asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+       u32 val;
+       asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+       return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+       asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+
+/* RCSR - Reset Cause Status Register  */
+static inline u32 read_rcsr(void)
+{
+       u32 val;
+       asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
+       return val;
+}
+
+extern unsigned long get_iop_tick_rate(void);
 #endif
 
 /*
@@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PBI_LR1                IOP13XX_PBI_OFFSET(0x14)
 
 #define IOP13XX_PROCESSOR_FREQ         IOP13XX_REG_ADDR32(0x2180)
+
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM       0x1e1e1e1e
+#define IOP_WDTCR_EN           0xe1e1e1e1
+#define IOP_WDTCR_DIS_ARM      0x1f1f1f1f
+#define IOP_WDTCR_DIS          0xf1f1f1f1
+#define IOP_RCSR_WDT           (1 << 5) /* reset caused by watchdog timer */
+#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
+#define IOP13XX_WDTCR_IB_RESET (1 << 0)
+
 #endif /* _IOP13XX_HW_H_ */
index 127827058e1f4841e1eb00f248b544b94db6d23a..8575af8db78c7cf3b2c71b92a111133bb19663ca 100644 (file)
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
 
-/* WDTCR CP6 R7 Page 9 */
-static inline u32 read_wdtcr(void)
-{
-       u32 val;
-       asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
-       return val;
-}
-static inline void write_wdtcr(u32 val)
-{
-       asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
-}
-
-/* WDTSR CP6 R8 Page 9 */
-static inline u32 read_wdtsr(void)
-{
-       u32 val;
-       asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
-       return val;
-}
-static inline void write_wdtsr(u32 val)
-{
-       asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
-}
-
-#define IOP13XX_WDTCR_EN_ARM   0x1e1e1e1e
-#define IOP13XX_WDTCR_EN       0xe1e1e1e1
-#define IOP13XX_WDTCR_DIS_ARM  0x1f1f1f1f
-#define IOP13XX_WDTCR_DIS      0xf1f1f1f1
-#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
-#define IOP13XX_WDTCR_IB_RESET (1 << 0)
 static inline void arch_reset(char mode)
 {
        /*
         * Reset the internal bus (warning both cores are reset)
         */
-       write_wdtcr(IOP13XX_WDTCR_EN_ARM);
-       write_wdtcr(IOP13XX_WDTCR_EN);
+       write_wdtcr(IOP_WDTCR_EN_ARM);
+       write_wdtcr(IOP_WDTCR_EN);
        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
        write_wdtcr(0x1000);
 
index b9525d59b7ad3616f94b8e8f7f214c32a6893aef..dd9c2934190e045a9e6872bfe84fa26d3c574fec 100644 (file)
@@ -1,7 +1,6 @@
 #include <asm/types.h>
 #include <linux/serial_reg.h>
 #include <asm/hardware.h>
-#include <asm/processor.h>
 
 #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
@@ -9,7 +8,7 @@
 static inline void putc(char c)
 {
        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
-               cpu_relax();
+               barrier();
        UART_BASE[UART_TX] = c;
 }
 
index e64f52bf2bcefb8a6fed77b39cd0bb1d24479eba..070f15818fe718593c675233b471c5f231fd1d0b 100644 (file)
@@ -26,7 +26,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
        if (machine_is_iq80321())
                uart_base = (volatile u8 *)IQ80321_UART;
-       else if (machine_is_iq31244())
+       else if (machine_is_iq31244() || machine_is_em7210())
                uart_base = (volatile u8 *)IQ31244_UART;
        else
                uart_base = (volatile u8 *)0xfe800000;
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
new file mode 100644 (file)
index 0000000..be29b83
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+
+/*!
+ * @name PBC Controller parameters
+ */
+/*! @{ */
+/*!
+ * Base address of PBC controller
+ */
+#define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
+/* Offsets for the PBC Controller register */
+/*!
+ * PBC Board status register offset
+ */
+#define PBC_BSTAT               0x000002
+/*!
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET          0x000004
+/*!
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR        0x000006
+/*!
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET          0x000008
+/*!
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR        0x00000A
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET          0x00000C
+/*!
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR        0x00000E
+/*!
+ * PBC Board control register 4 set address.
+ */
+#define PBC_BCTRL4_SET          0x000010
+/*!
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR        0x000012
+/*!
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1              0x000014
+/*!
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS           0x000016
+/*!
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS      0x000018
+/*!
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET         0x00001A
+/*!
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/*!
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA      0x010000
+/*!
+ * External UART B.
+ */
+#define PBC_SC16C652_UARTB      0x010010
+/*!
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE      0x020000
+/*!
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE     0x021000
+/*!
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE     0x022000
+/*!
+ * External chip select 0.
+ */
+#define PBC_XCS0                0x040000
+/*!
+ * LCD Display enable.
+ */
+#define PBC_LCD_EN_B            0x060000
+/*!
+ * Code test debug enable.
+ */
+#define PBC_CODE_B              0x070000
+/*!
+ * PSRAM memory select.
+ */
+#define PBC_PSRAM_B             0x5000000
+
+#define PBC_INTSTATUS_REG      (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG    (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG  (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT       IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define EXPIO_INT_LOW_BAT      (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_PB_IRQ       (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR   (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR      (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4         (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5         (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6         (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_RES7         (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT     (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT   (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA   (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB   (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SYNTH_IRQ    (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_CE_INT1      (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_CE_INT2      (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_RES15                (MXC_EXP_IO_BASE + 15)
+
+#define MXC_MAX_EXP_IO_LINES   16
+
+#endif                         /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
new file mode 100644 (file)
index 0000000..23b4350
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_COMMON_H__
+#define __ASM_ARCH_MXC_COMMON_H__
+
+struct sys_timer;
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern struct sys_timer mxc_timer;
+
+#endif
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
new file mode 100644 (file)
index 0000000..65e639d
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+
+/*!
+ * @file dma.h
+ * @brief This file contains Unified DMA API for all MXC platforms.
+ * The API is platform independent.
+ *
+ * @ingroup SDMA
+ */
+#endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
new file mode 100644 (file)
index 0000000..b542433
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+       @ this macro disables fast irq (not implemented)
+       .macro  disable_fiq
+       .endm
+
+       .macro  get_irqnr_preamble, base, tmp
+       .endm
+
+       .macro  arch_ret_to_user, tmp1, tmp2
+       .endm
+
+       @ this macro checks which interrupt occured
+       @ and returns its number in irqnr
+       @ and returns if an interrupt occured in irqstat
+       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+       ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+       @ Load offset & priority of the highest priority
+       @ interrupt pending from AVIC_NIVECSR
+       ldr     \irqstat, [\base, #0x40]
+       @ Shift to get the decoded IRQ number, using ASR so
+       @ 'no interrupt pending' becomes 0xffffffff
+       mov     \irqnr, \irqstat, asr #16
+       @ set zero flag if IRQ + 1 == 0
+       adds    \tmp, \irqnr, #1
+       .endm
+
+       @ irq priority table (not used)
+       .macro  irq_prio_table
+       .endm
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
new file mode 100644 (file)
index 0000000..3c09b92
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file hardware.h
+ * @brief This file contains the hardware definitions of the board.
+ *
+ * @ingroup System
+ */
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+
+#include <asm/sizes.h>
+
+#include <asm/arch/mx31.h>
+
+#include <asm/arch/mxc.h>
+
+#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board specific defines
+ * ---------------------------------------------------------------------------
+ */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
+
+#include <asm/arch/board-mx31ads.h>
+
+#ifndef MXC_MAX_EXP_IO_LINES
+#define MXC_MAX_EXP_IO_LINES 0
+#endif
+
+#define MXC_MAX_VIRTUAL_INTS   16
+#define MXC_VIRTUAL_INTS_BASE  (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ     MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ     (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ     (MXC_VIRTUAL_INTS_BASE + 2)
+
+#define MXC_MAX_INTS            (MXC_MAX_INT_LINES + \
+                                MXC_MAX_GPIO_LINES + \
+                                MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+
+#endif                         /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
new file mode 100644 (file)
index 0000000..cf6c83a
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file io.h
+ * @brief This file contains some memory mapping macros.
+ * @note There is no real ISA or PCI buses. But have to define these macros
+ * for some drivers to compile.
+ *
+ * @ingroup System
+ */
+
+#ifndef __ASM_ARCH_MXC_IO_H__
+#define __ASM_ARCH_MXC_IO_H__
+
+/*! Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*!
+ * io address mapping macro
+ */
+#define __io(a)                        ((void __iomem *)(a))
+
+#define __mem_pci(a)           (a)
+
+#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
new file mode 100644 (file)
index 0000000..e4686c6
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IRQS_H__
+#define __ASM_ARCH_MXC_IRQS_H__
+
+#include <asm/hardware.h>
+
+/*!
+ * @file irqs.h
+ * @brief This file defines the number of normal interrupts and fast interrupts
+ *
+ * @ingroup Interrupt
+ */
+
+#define MXC_IRQ_TO_EXPIO(irq)  ((irq) - MXC_EXP_IO_BASE)
+
+#define MXC_IRQ_TO_GPIO(irq)   ((irq) - MXC_GPIO_INT_BASE)
+#define MXC_GPIO_TO_IRQ(x)     (MXC_GPIO_INT_BASE + x)
+
+/*!
+ * Number of normal interrupts
+ */
+#define NR_IRQS                MXC_MAX_INTS
+
+/*!
+ * Number of fast interrupts
+ */
+#define NR_FIQS                MXC_MAX_INTS
+
+#endif                         /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
new file mode 100644 (file)
index 0000000..c89aac8
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MEMORY_H__
+#define __ASM_ARCH_MXC_MEMORY_H__
+
+#include <asm/hardware.h>
+
+/*!
+ * @file memory.h
+ * @brief This file contains macros needed by the Linux kernel and drivers.
+ *
+ * @ingroup Memory
+ */
+
+/*!
+ * Virtual view <-> DMA view memory address translations
+ * This macro is used to translate the virtual address to an address
+ * suitable to be passed to set_dma_addr()
+ */
+#define __virt_to_bus(a)       __virt_to_phys(a)
+
+/*!
+ * Used to convert an address for DMA operations to an address that the
+ * kernel can use.
+ */
+#define __bus_to_virt(a)       __phys_to_virt(a)
+
+#endif                         /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
new file mode 100644 (file)
index 0000000..85c49c9
--- /dev/null
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX31_H__
+#define __ASM_ARCH_MXC_MX31_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*!
+ * defines the hardware clock tick rate
+ */
+#define CLOCK_TICK_RATE                16625000
+
+/*
+ * MX31 memory map:
+ *
+ * Virt                Phys            Size    What
+ * ---------------------------------------------------------------------------
+ * F8000000    1FFC0000        16K     IRAM
+ * F9000000    30000000        256M    L2CC
+ * FC000000    43F00000        1M      AIPS 1
+ * FC100000    50000000        1M      SPBA
+ * FC200000    53F00000        1M      AIPS 2
+ * FC500000    60000000        128M    ROMPATCH
+ * FC400000    68000000        128M    AVIC
+ *             70000000        256M    IPU (MAX M2)
+ *             80000000        256M    CSD0 SDRAM/DDR
+ *             90000000        256M    CSD1 SDRAM/DDR
+ *             A0000000        128M    CS0 Flash
+ *             A8000000        128M    CS1 Flash
+ *             B0000000        32M     CS2
+ *             B2000000        32M     CS3
+ * F4000000    B4000000        32M     CS4
+ *             B6000000        32M     CS5
+ * FC320000    B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
+ *             C0000000        64M     PCMCIA/CF
+ */
+
+#define CS0_BASE_ADDR          0xA0000000
+#define CS1_BASE_ADDR          0xA8000000
+#define CS2_BASE_ADDR          0xB0000000
+#define CS3_BASE_ADDR          0xB2000000
+
+#define CS4_BASE_ADDR          0xB4000000
+#define CS4_BASE_ADDR_VIRT     0xF4000000
+#define CS4_SIZE               SZ_32M
+
+#define CS5_BASE_ADDR          0xB6000000
+#define PCMCIA_MEM_BASE_ADDR   0xBC000000
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR         0x1FFC0000      /* internal ram */
+#define IRAM_BASE_ADDR_VIRT    0xF8000000
+#define IRAM_SIZE              SZ_16K
+
+/*
+ * L2CC
+ */
+#define L2CC_BASE_ADDR         0x30000000
+#define L2CC_BASE_ADDR_VIRT    0xF9000000
+#define L2CC_SIZE              SZ_1M
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR                0x43F00000
+#define AIPS1_BASE_ADDR_VIRT   0xFC000000
+#define AIPS1_SIZE             SZ_1M
+
+#define MAX_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00004000)
+#define EVTMON_BASE_ADDR       (AIPS1_BASE_ADDR + 0x00008000)
+#define CLKCTL_BASE_ADDR       (AIPS1_BASE_ADDR + 0x0000C000)
+#define ETB_SLOT4_BASE_ADDR    (AIPS1_BASE_ADDR + 0x00010000)
+#define ETB_SLOT5_BASE_ADDR    (AIPS1_BASE_ADDR + 0x00014000)
+#define ECT_CTIO_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00018000)
+#define I2C_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00080000)
+#define I2C3_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00084000)
+#define OTG_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00088000)
+#define ATA_BASE_ADDR          (AIPS1_BASE_ADDR + 0x0008C000)
+#define UART1_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00090000)
+#define UART2_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00094000)
+#define I2C2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00098000)
+#define OWIRE_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0009C000)
+#define SSI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A0000)
+#define CSPI1_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000A4000)
+#define KPP_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A8000)
+#define IOMUXC_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000AC000)
+#define UART4_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000B0000)
+#define UART5_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000B4000)
+#define ECT_IP1_BASE_ADDR      (AIPS1_BASE_ADDR + 0x000B8000)
+#define ECT_IP2_BASE_ADDR      (AIPS1_BASE_ADDR + 0x000BC000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR        0x50000000
+#define SPBA0_BASE_ADDR_VIRT   0xFC100000
+#define SPBA0_SIZE             SZ_1M
+
+#define MMC_SDHC1_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR        (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI2_BASE_ADDR        (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00014000)
+#define SIM1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00018000)
+#define IIM_BASE_ADDR          (SPBA0_BASE_ADDR + 0x0001C000)
+#define ATA_DMA_BASE_ADDR      (SPBA0_BASE_ADDR + 0x00020000)
+#define MSHC1_BASE_ADDR                (SPBA0_BASE_ADDR + 0x00024000)
+#define MSHC2_BASE_ADDR                (SPBA0_BASE_ADDR + 0x00024000)
+#define SPBA_CTRL_BASE_ADDR    (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR                0x53F00000
+#define AIPS2_BASE_ADDR_VIRT   0xFC200000
+#define AIPS2_SIZE             SZ_1M
+#define CCM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00080000)
+#define CSPI3_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00084000)
+#define FIRI_BASE_ADDR         (AIPS2_BASE_ADDR + 0x0008C000)
+#define GPT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
+#define EPIT1_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00094000)
+#define EPIT2_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00098000)
+#define GPIO3_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000A4000)
+#define SCC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000AC000)
+#define SCM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000AE000)
+#define SMN_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000AF000)
+#define RNGA_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000B0000)
+#define IPU_CTRL_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C0000)
+#define AUDMUX_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000C4000)
+#define MPEG4_ENC_BASE_ADDR    (AIPS2_BASE_ADDR + 0x000C8000)
+#define GPIO1_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000CC000)
+#define GPIO2_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000D0000)
+#define SDMA_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D4000)
+#define RTC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D8000)
+#define WDOG_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000DC000)
+#define PWM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000E0000)
+#define RTIC_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000EC000)
+
+/*
+ * ROMP and AVIC
+ */
+#define ROMP_BASE_ADDR         0x60000000
+#define ROMP_BASE_ADDR_VIRT    0xFC500000
+#define ROMP_SIZE              SZ_1M
+
+#define AVIC_BASE_ADDR         0x68000000
+#define AVIC_BASE_ADDR_VIRT    0xFC400000
+#define AVIC_SIZE              SZ_1M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define X_MEMC_BASE_ADDR       0xB8000000
+#define X_MEMC_BASE_ADDR_VIRT  0xFC320000
+#define X_MEMC_SIZE            SZ_64K
+
+#define NFC_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x0000)
+#define ESDCTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR         (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR         (X_MEMC_BASE_ADDR + 0x3000)
+#define EMI_CTL_BASE_ADDR      (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_CTL_BASE_ADDR   EMI_CTL_BASE_ADDR
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR      0x70000000
+#define CSD0_BASE_ADDR         0x80000000
+#define CSD1_BASE_ADDR         0x90000000
+#define CS0_BASE_ADDR          0xA0000000
+#define CS1_BASE_ADDR          0xA8000000
+#define CS2_BASE_ADDR          0xB0000000
+#define CS3_BASE_ADDR          0xB2000000
+
+#define CS4_BASE_ADDR          0xB4000000
+#define CS4_BASE_ADDR_VIRT     0xF4000000
+#define CS4_SIZE               SZ_32M
+
+#define CS5_BASE_ADDR          0xB6000000
+#define PCMCIA_MEM_BASE_ADDR   0xBC000000
+
+/*!
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+       (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
+       ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
+       ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
+       ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
+       ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
+       ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
+       ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
+       ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
+       ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
+       0xDEADBEEF)
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+
+#define IRAM_IO_ADDRESS(x)  \
+       (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
+
+#define L2CC_IO_ADDRESS(x)  \
+       (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
+
+#define AIPS1_IO_ADDRESS(x)  \
+       (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
+
+#define SPBA0_IO_ADDRESS(x)  \
+       (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
+
+#define AIPS2_IO_ADDRESS(x)  \
+       (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
+
+#define ROMP_IO_ADDRESS(x)  \
+       (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)  \
+       (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+       (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+       (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+       (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
+#define PHYS_OFFSET             CSD0_BASE_ADDR
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_PEN_ADS7843    0
+#define MXC_INT_RESV1          1
+#define MXC_INT_CS8900A                2
+#define MXC_INT_I2C3           3
+#define MXC_INT_I2C2           4
+#define MXC_INT_MPEG4_ENCODER  5
+#define MXC_INT_RTIC           6
+#define MXC_INT_FIRI           7
+#define MXC_INT_MMC_SDHC2      8
+#define MXC_INT_MMC_SDHC1      9
+#define MXC_INT_I2C            10
+#define MXC_INT_SSI2           11
+#define MXC_INT_SSI1           12
+#define MXC_INT_CSPI2          13
+#define MXC_INT_CSPI1          14
+#define MXC_INT_ATA            15
+#define MXC_INT_MBX            16
+#define MXC_INT_CSPI3          17
+#define MXC_INT_UART3          18
+#define MXC_INT_IIM            19
+#define MXC_INT_SIM2           20
+#define MXC_INT_SIM1           21
+#define MXC_INT_RNGA           22
+#define MXC_INT_EVTMON         23
+#define MXC_INT_KPP            24
+#define MXC_INT_RTC            25
+#define MXC_INT_PWM            26
+#define MXC_INT_EPIT2          27
+#define MXC_INT_EPIT1          28
+#define MXC_INT_GPT            29
+#define MXC_INT_RESV30         30
+#define MXC_INT_RESV31         31
+#define MXC_INT_UART2          32
+#define MXC_INT_NANDFC         33
+#define MXC_INT_SDMA           34
+#define MXC_INT_USB1           35
+#define MXC_INT_USB2           36
+#define MXC_INT_USB3           37
+#define MXC_INT_USB4           38
+#define MXC_INT_MSHC1          39
+#define MXC_INT_MSHC2          40
+#define MXC_INT_IPU_ERR                41
+#define MXC_INT_IPU_SYN                42
+#define MXC_INT_RESV43         43
+#define MXC_INT_RESV44         44
+#define MXC_INT_UART1          45
+#define MXC_INT_UART4          46
+#define MXC_INT_UART5          47
+#define MXC_INT_ECT            48
+#define MXC_INT_SCC_SCM                49
+#define MXC_INT_SCC_SMN                50
+#define MXC_INT_GPIO2          51
+#define MXC_INT_GPIO1          52
+#define MXC_INT_CCM            53
+#define MXC_INT_PCMCIA         54
+#define MXC_INT_WDOG           55
+#define MXC_INT_GPIO3          56
+#define MXC_INT_RESV57         57
+#define MXC_INT_EXT_POWER      58
+#define MXC_INT_EXT_TEMPER     59
+#define MXC_INT_EXT_SENSOR60   60
+#define MXC_INT_EXT_SENSOR61   61
+#define MXC_INT_EXT_WDOG       62
+#define MXC_INT_EXT_TV         63
+
+#define MXC_MAX_INT_LINES      64
+
+#define MXC_GPIO_INT_BASE      MXC_MAX_INT_LINES
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM          3
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN           32
+
+#define PROD_SIGNATURE         0x1     /* For MX31 */
+
+#define SYSTEM_REV_MIN         CHIP_REV_1_0
+#define SYSTEM_REV_NUM         3
+
+#endif                 /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
new file mode 100644 (file)
index 0000000..0837f1f
--- /dev/null
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_H__
+#define __ASM_ARCH_MXC_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*
+ *****************************************
+ * GPT  Register definitions             *
+ *****************************************
+ */
+#define MXC_GPT_GPTCR          IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
+#define MXC_GPT_GPTPR          IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
+#define MXC_GPT_GPTSR          IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
+#define MXC_GPT_GPTIR          IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
+#define MXC_GPT_GPTOCR1                IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
+#define MXC_GPT_GPTOCR2                IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
+#define MXC_GPT_GPTOCR3                IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
+#define MXC_GPT_GPTICR1                IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
+#define MXC_GPT_GPTICR2                IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
+#define MXC_GPT_GPTCNT         IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
+
+/*!
+ * GPT Control register bit definitions
+ */
+#define GPTCR_FO3                      (1 << 31)
+#define GPTCR_FO2                      (1 << 30)
+#define GPTCR_FO1                      (1 << 29)
+
+#define GPTCR_OM3_SHIFT                        26
+#define GPTCR_OM3_MASK                 (7 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_DISCONNECTED         (0 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_TOGGLE               (1 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_CLEAR                        (2 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_SET                  (3 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_GENERATE_LOW         (7 << GPTCR_OM3_SHIFT)
+
+#define GPTCR_OM2_SHIFT                        23
+#define GPTCR_OM2_MASK                 (7 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_DISCONNECTED         (0 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_TOGGLE               (1 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_CLEAR                        (2 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_SET                  (3 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_GENERATE_LOW         (7 << GPTCR_OM2_SHIFT)
+
+#define GPTCR_OM1_SHIFT                        20
+#define GPTCR_OM1_MASK                 (7 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_DISCONNECTED         (0 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_TOGGLE               (1 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_CLEAR                        (2 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_SET                  (3 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_GENERATE_LOW         (7 << GPTCR_OM1_SHIFT)
+
+#define GPTCR_IM2_SHIFT                        18
+#define GPTCR_IM2_MASK                 (3 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_DISABLE      (0 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_RISING       (1 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_FALLING      (2 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_BOTH         (3 << GPTCR_IM2_SHIFT)
+
+#define GPTCR_IM1_SHIFT                        16
+#define GPTCR_IM1_MASK                 (3 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_DISABLE      (0 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_RISING       (1 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_FALLING      (2 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_BOTH         (3 << GPTCR_IM1_SHIFT)
+
+#define GPTCR_SWR                      (1 << 15)
+#define GPTCR_FRR                      (1 << 9)
+
+#define GPTCR_CLKSRC_SHIFT             6
+#define GPTCR_CLKSRC_MASK              (7 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_NOCLOCK           (0 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_HIGHFREQ          (2 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLKIN             (3 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLK32K            (7 << GPTCR_CLKSRC_SHIFT)
+
+#define GPTCR_STOPEN                   (1 << 5)
+#define GPTCR_DOZEN                    (1 << 4)
+#define GPTCR_WAITEN                   (1 << 3)
+#define GPTCR_DBGEN                    (1 << 2)
+
+#define GPTCR_ENMOD                    (1 << 1)
+#define GPTCR_ENABLE                   (1 << 0)
+
+#define GPTSR_OF1                      (1 << 0)
+#define GPTSR_OF2                      (1 << 1)
+#define GPTSR_OF3                      (1 << 2)
+#define GPTSR_IF1                      (1 << 3)
+#define GPTSR_IF2                      (1 << 4)
+#define GPTSR_ROV                      (1 << 5)
+
+#define GPTIR_OF1IE                    GPTSR_OF1
+#define GPTIR_OF2IE                    GPTSR_OF2
+#define GPTIR_OF3IE                    GPTSR_OF3
+#define GPTIR_IF1IE                    GPTSR_IF1
+#define GPTIR_IF2IE                    GPTSR_IF2
+#define GPTIR_ROVIE                    GPTSR_ROV
+
+/*
+ *****************************************
+ * AVIC Registers                        *
+ *****************************************
+ */
+#define AVIC_BASE              IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL           (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK            (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM          (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM         (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH                (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL                (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH          (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL          (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7       (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6       (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5       (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4       (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3       (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2       (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1       (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0       (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR           (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR           (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH           (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL           (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH           (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL           (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH            (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL            (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH            (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL            (AVIC_BASE + 0x64)      /* fast int pending low */
+
+#define SYSTEM_PREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH                3
+#define IIM_PROD_REV_LEN       5
+
+#endif                         /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
new file mode 100644 (file)
index 0000000..109956b
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_SYSTEM_H__
+#define __ASM_ARCH_MXC_SYSTEM_H__
+
+/*!
+ * @file system.h
+ * @brief This file contains idle and reset functions.
+ *
+ * @ingroup System
+ */
+
+/*!
+ * This function puts the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+static inline void arch_idle(void)
+{
+       cpu_do_idle();
+}
+
+/*
+ * This function resets the system. It is called by machine_restart().
+ *
+ * @param  mode         indicates different kinds of resets
+ */
+static inline void arch_reset(char mode)
+{
+       cpu_reset(0);
+}
+
+#endif                         /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
new file mode 100644 (file)
index 0000000..59019fa
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_TIMEX_H__
+#define __ASM_ARCH_MXC_TIMEX_H__
+
+#include <asm/hardware.h>      /* for CLOCK_TICK_RATE */
+
+#endif                         /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
new file mode 100644 (file)
index 0000000..ec5787d
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ *  include/asm-arm/arch-mxc/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __ASM_ARCH_MXC_UNCOMPRESS_H__
+
+#define __MXC_BOOT_UNCOMPRESS
+
+#include <asm/hardware.h>
+#include <asm/processor.h>
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+
+static void putc(int ch)
+{
+       static unsigned long serial_port = 0;
+
+       if (unlikely(serial_port == 0)) {
+               do {
+                       serial_port = UART1_BASE_ADDR;
+                       if (UART(UCR1) & UCR1_UARTEN)
+                               break;
+                       serial_port = UART2_BASE_ADDR;
+                       if (UART(UCR1) & UCR1_UARTEN)
+                               break;
+                       return;
+               } while (0);
+       }
+
+       while (!(UART(USR2) & USR2_TXFE))
+               cpu_relax();
+
+       UART(TXR) = ch;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif                         /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
new file mode 100644 (file)
index 0000000..83a73da
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2000 Russell King.
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is fre