Merge branch 'tracing-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
authorLinus Torvalds <torvalds@linux-foundation.org>
Tue, 18 May 2010 15:35:04 +0000 (08:35 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Tue, 18 May 2010 15:35:04 +0000 (08:35 -0700)
* 'tracing-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  tracing: Fix "integer as NULL pointer" warning.
  tracing: Fix tracepoint.h DECLARE_TRACE() to allow more than one header
  tracing: Make the documentation clear on trace_event boot option
  ring-buffer: Wrap open-coded WARN_ONCE
  tracing: Convert nop macros to static inlines
  tracing: Fix sleep time function profiling
  tracing: Show sample std dev in function profiling
  tracing: Add documentation for trace commands mod, traceon/traceoff
  ring-buffer: Make benchmark handle missed events
  ring-buffer: Make non-consuming read less expensive with lots of cpus.
  tracing: Add graph output support for irqsoff tracer
  tracing: Have graph flags passed in to ouput functions
  tracing: Add ftrace events for graph tracer
  tracing: Dump either the oops's cpu source or all cpus buffers
  tracing: Fix uninitialized variable of tracing/trace output

525 files changed:
Documentation/RCU/stallwarn.txt
Documentation/RCU/torture.txt
Documentation/RCU/trace.txt
Documentation/filesystems/proc.txt
Documentation/kernel-parameters.txt
Documentation/kprobes.txt
Documentation/scheduler/sched-design-CFS.txt
Documentation/scheduler/sched-rt-group.txt
Documentation/trace/kprobetrace.txt
MAINTAINERS
Makefile
arch/Kconfig
arch/alpha/include/asm/atomic.h
arch/arm/include/asm/atomic.h
arch/arm/include/asm/cacheflush.h
arch/arm/include/asm/smp_twd.h
arch/arm/include/asm/tlbflush.h
arch/arm/kernel/smp_twd.c
arch/arm/lib/clear_user.S
arch/arm/lib/copy_to_user.S
arch/arm/mach-davinci/da830.c
arch/arm/mm/cache-v6.S
arch/arm/mm/cache-v7.S
arch/arm/mm/nommu.c
arch/arm/mm/tlb-v7.S
arch/avr32/include/asm/atomic.h
arch/cris/include/asm/atomic.h
arch/frv/include/asm/atomic.h
arch/h8300/include/asm/atomic.h
arch/ia64/include/asm/atomic.h
arch/m32r/include/asm/atomic.h
arch/m68k/amiga/Makefile
arch/m68k/amiga/platform.c [new file with mode: 0644]
arch/m68k/bvme6000/rtc.c
arch/m68k/hp300/time.h
arch/m68k/include/asm/atomic_mm.h
arch/m68k/include/asm/atomic_no.h
arch/m68k/include/asm/bitops_mm.h
arch/m68k/include/asm/param.h
arch/m68k/kernel/traps.c
arch/m68k/mac/config.c
arch/m68k/mm/fault.c
arch/m68k/mvme16x/rtc.c
arch/m68k/q40/config.c
arch/microblaze/include/asm/uaccess.h
arch/microblaze/kernel/cpu/cache.c
arch/microblaze/kernel/entry-nommu.S
arch/microblaze/kernel/microblaze_ksyms.c
arch/microblaze/kernel/module.c
arch/microblaze/mm/init.c
arch/microblaze/mm/pgtable.c
arch/microblaze/pci/pci-common.c
arch/mips/include/asm/atomic.h
arch/mips/include/asm/i8253.h
arch/mips/include/asm/mipsregs.h
arch/mips/kernel/i8253.c
arch/mips/kernel/scall64-n32.S
arch/mips/math-emu/cp1emu.c
arch/mips/oprofile/op_model_loongson2.c
arch/mn10300/include/asm/atomic.h
arch/parisc/include/asm/atomic.h
arch/powerpc/include/asm/hw_irq.h
arch/powerpc/kernel/asm-offsets.c
arch/powerpc/kernel/dma-swiotlb.c
arch/powerpc/kernel/entry_64.S
arch/powerpc/kernel/irq.c
arch/powerpc/kernel/perf_event.c
arch/powerpc/kernel/time.c
arch/powerpc/kvm/44x_tlb.c
arch/s390/kernel/head31.S
arch/s390/kernel/head64.S
arch/s390/kernel/ptrace.c
arch/s390/kernel/time.c
arch/sh/Kconfig
arch/sh/include/asm/atomic.h
arch/sh/include/asm/hw_breakpoint.h
arch/sh/kernel/hw_breakpoint.c
arch/sh/kernel/ptrace_32.c
arch/sparc/include/asm/atomic_32.h
arch/sparc/include/asm/atomic_64.h
arch/x86/Kconfig
arch/x86/Kconfig.cpu
arch/x86/Kconfig.debug
arch/x86/include/asm/amd_iommu_types.h
arch/x86/include/asm/apic.h
arch/x86/include/asm/atomic.h
arch/x86/include/asm/atomic64_64.h
arch/x86/include/asm/ds.h [deleted file]
arch/x86/include/asm/hw_breakpoint.h
arch/x86/include/asm/i8253.h
arch/x86/include/asm/insn.h
arch/x86/include/asm/k8.h
arch/x86/include/asm/kprobes.h
arch/x86/include/asm/msr-index.h
arch/x86/include/asm/perf_event.h
arch/x86/include/asm/perf_event_p4.h [new file with mode: 0644]
arch/x86/include/asm/processor.h
arch/x86/include/asm/ptrace-abi.h
arch/x86/include/asm/ptrace.h
arch/x86/include/asm/thread_info.h
arch/x86/kernel/Makefile
arch/x86/kernel/amd_iommu.c
arch/x86/kernel/amd_iommu_init.c
arch/x86/kernel/apm_32.c
arch/x86/kernel/cpu/intel.c
arch/x86/kernel/cpu/intel_cacheinfo.c
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_amd.c
arch/x86/kernel/cpu/perf_event_intel.c
arch/x86/kernel/cpu/perf_event_intel_ds.c [new file with mode: 0644]
arch/x86/kernel/cpu/perf_event_intel_lbr.c [new file with mode: 0644]
arch/x86/kernel/cpu/perf_event_p4.c [new file with mode: 0644]
arch/x86/kernel/cpu/perf_event_p6.c
arch/x86/kernel/ds.c [deleted file]
arch/x86/kernel/ds_selftest.c [deleted file]
arch/x86/kernel/ds_selftest.h [deleted file]
arch/x86/kernel/dumpstack.c
arch/x86/kernel/hw_breakpoint.c
arch/x86/kernel/i8253.c
arch/x86/kernel/kprobes.c
arch/x86/kernel/process.c
arch/x86/kernel/process_32.c
arch/x86/kernel/process_64.c
arch/x86/kernel/ptrace.c
arch/x86/kernel/step.c
arch/x86/kernel/traps.c
arch/x86/kvm/svm.c
arch/x86/kvm/vmx.c
arch/x86/kvm/x86.c
arch/x86/kvm/x86.h
arch/x86/lib/Makefile
arch/x86/mm/srat_64.c
arch/x86/oprofile/nmi_int.c
arch/x86/oprofile/op_model_amd.c
arch/x86/oprofile/op_model_p4.c
arch/x86/oprofile/op_model_ppro.c
arch/x86/oprofile/op_x86_model.h
arch/x86/pci/mrst.c
arch/xtensa/include/asm/atomic.h
drivers/acpi/sleep.c
drivers/base/iommu.c
drivers/base/platform.c
drivers/block/amiflop.c
drivers/block/hd.c
drivers/char/serial167.c
drivers/char/tty_io.c
drivers/cpufreq/cpufreq_ondemand.c
drivers/gpio/it8761e_gpio.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/radeon/radeon_state.c
drivers/hid/hid-cherry.c
drivers/hid/hid-core.c
drivers/hid/hid-ids.h
drivers/hid/hid-ntrig.c
drivers/hid/hid-sony.c
drivers/hid/hid-wacom.c
drivers/hid/usbhid/hid-core.c
drivers/hwmon/applesmc.c
drivers/hwmon/asc7621.c
drivers/hwmon/hp_accel.c
drivers/input/gameport/gameport.c
drivers/input/joystick/analog.c
drivers/input/joystick/iforce/iforce-main.c
drivers/input/joystick/iforce/iforce-usb.c
drivers/input/misc/pcspkr.c
drivers/input/mouse/elantech.c
drivers/input/mouse/elantech.h
drivers/input/mouse/psmouse-base.c
drivers/input/touchscreen/ad7877.c
drivers/mfd/wm831x-core.c
drivers/mfd/wm8350-core.c
drivers/mmc/host/at91_mci.c
drivers/mmc/host/atmel-mci.c
drivers/net/a2065.c
drivers/net/ariadne.c
drivers/net/gianfar.c
drivers/net/hydra.c
drivers/net/phy/micrel.c
drivers/net/veth.c
drivers/net/wireless/ath/ar9170/usb.c
drivers/net/wireless/ath/ar9170/usb.h
drivers/net/wireless/iwlwifi/iwl-commands.h
drivers/net/wireless/iwlwifi/iwl-scan.c
drivers/net/wireless/iwlwifi/iwl3945-base.c
drivers/net/zorro8390.c
drivers/oprofile/cpu_buffer.c
drivers/oprofile/oprof.c
drivers/oprofile/oprof.h
drivers/oprofile/timer_int.c
drivers/pci/intel-iommu.c
drivers/pci/setup-bus.c
drivers/s390/block/dasd.c
drivers/scsi/zorro7xx.c
drivers/serial/imx.c
drivers/serial/mpc52xx_uart.c
drivers/usb/core/inode.c
drivers/vhost/vhost.c
drivers/video/amifb.c
drivers/video/bfin-t350mcqb-fb.c
drivers/video/cirrusfb.c
drivers/video/fm2fb.c
drivers/watchdog/Kconfig
drivers/watchdog/mpcore_wdt.c
drivers/xen/manage.c
drivers/zorro/proc.c
drivers/zorro/zorro-driver.c
drivers/zorro/zorro-sysfs.c
drivers/zorro/zorro.c
fs/autofs4/root.c
fs/btrfs/ioctl.c
fs/cachefiles/internal.h
fs/cachefiles/namei.c
fs/cachefiles/security.c
fs/ceph/addr.c
fs/ceph/caps.c
fs/ceph/inode.c
fs/ceph/mds_client.c
fs/ceph/messenger.c
fs/ceph/messenger.h
fs/ceph/osd_client.c
fs/ceph/osd_client.h
fs/ceph/osdmap.c
fs/ceph/osdmap.h
fs/ceph/rados.h
fs/ceph/super.c
fs/cifs/asn1.c
fs/cifs/cifs_debug.c
fs/cifs/cifs_debug.h
fs/cifs/cifs_dfs_ref.c
fs/cifs/cifs_spnego.c
fs/cifs/cifs_unicode.c
fs/cifs/cifsacl.c
fs/cifs/cifsencrypt.c
fs/cifs/cifsfs.c
fs/cifs/cifsfs.h
fs/cifs/cifsglob.h
fs/cifs/cifsproto.h
fs/cifs/cifssmb.c
fs/cifs/connect.c
fs/cifs/dir.c
fs/cifs/dns_resolve.c
fs/cifs/export.c
fs/cifs/file.c
fs/cifs/inode.c
fs/cifs/ioctl.c
fs/cifs/link.c
fs/cifs/misc.c
fs/cifs/netmisc.c
fs/cifs/readdir.c
fs/cifs/sess.c
fs/cifs/transport.c
fs/cifs/xattr.c
fs/compat.c
fs/configfs/dir.c
fs/eventpoll.c
fs/exec.c
fs/jfs/super.c
fs/logfs/dev_bdev.c
fs/logfs/dev_mtd.c
fs/logfs/file.c
fs/logfs/gc.c
fs/logfs/inode.c
fs/logfs/journal.c
fs/logfs/logfs.h
fs/logfs/readwrite.c
fs/logfs/segment.c
fs/logfs/super.c
fs/namei.c
fs/namespace.c
fs/notify/inotify/inotify_fsnotify.c
fs/notify/inotify/inotify_user.c
fs/proc/array.c
fs/proc/task_mmu.c
fs/sysv/dir.c
include/asm-generic/atomic.h
include/asm-generic/dma-mapping-common.h
include/linux/cpuset.h
include/linux/dcache.h
include/linux/debugobjects.h
include/linux/ftrace.h
include/linux/hw_breakpoint.h
include/linux/if_link.h
include/linux/init_task.h
include/linux/iommu.h
include/linux/mm.h
include/linux/mod_devicetable.h
include/linux/perf_event.h
include/linux/platform_device.h
include/linux/ptrace.h
include/linux/rcupdate.h
include/linux/rcutiny.h
include/linux/rcutree.h
include/linux/sched.h
include/linux/srcu.h
include/linux/stop_machine.h
include/linux/tick.h
include/linux/types.h
include/linux/wait.h
include/linux/zorro.h
include/net/sctp/sm.h
include/net/sctp/structs.h
include/net/tcp.h
include/trace/events/lock.h
include/trace/events/sched.h
include/trace/ftrace.h
init/Kconfig
ipc/mqueue.c
kernel/Makefile
kernel/acct.c
kernel/capability.c
kernel/cgroup.c
kernel/cpu.c
kernel/cpuset.c
kernel/cred-internals.h [deleted file]
kernel/cred.c
kernel/exit.c
kernel/fork.c
kernel/hw_breakpoint.c
kernel/kexec.c
kernel/kprobes.c
kernel/lockdep.c
kernel/lockdep_internals.h
kernel/lockdep_proc.c
kernel/module.c
kernel/perf_event.c
kernel/profile.c
kernel/ptrace.c
kernel/rcupdate.c
kernel/rcutiny.c
kernel/rcutiny_plugin.h [new file with mode: 0644]
kernel/rcutorture.c
kernel/rcutree.c
kernel/rcutree.h
kernel/rcutree_plugin.h
kernel/rcutree_trace.c
kernel/sched.c
kernel/sched_debug.c
kernel/sched_fair.c
kernel/sched_features.h
kernel/sched_idletask.c
kernel/sched_rt.c
kernel/softirq.c
kernel/stop_machine.c
kernel/time/tick-sched.c
kernel/time/timer_list.c
kernel/trace/Kconfig
kernel/trace/Makefile
kernel/trace/ftrace.c
kernel/trace/trace.h
kernel/trace/trace_entries.h
kernel/trace/trace_events_filter.c
kernel/trace/trace_hw_branches.c [deleted file]
kernel/trace/trace_kprobe.c
kernel/trace/trace_ksym.c
kernel/trace/trace_sched_switch.c
kernel/trace/trace_sched_wakeup.c
kernel/trace/trace_selftest.c
kernel/user.c
lib/Kconfig.debug
lib/btree.c
lib/debugobjects.c
lib/rwsem.c
mm/hugetlb.c
mm/memcontrol.c
mm/mlock.c
mm/rmap.c
net/core/dev.c
net/core/rtnetlink.c
net/ipv4/arp.c
net/ipv4/ipmr.c
net/ipv4/tcp.c
net/ipv4/udp.c
net/ipv6/datagram.c
net/llc/llc_sap.c
net/mac80211/mlme.c
net/sctp/input.c
net/sctp/sm_sideeffect.c
net/sctp/transport.c
scripts/mod/file2alias.c
security/min_addr.c
sound/core/pcm_native.c
sound/drivers/pcsp/pcsp.h
sound/drivers/pcsp/pcsp_input.c
sound/drivers/pcsp/pcsp_lib.c
sound/oss/dmasound/dmasound_paula.c
sound/pci/hda/patch_conexant.c
sound/pci/hda/patch_realtek.c
sound/pci/hda/patch_sigmatel.c
sound/pci/ice1712/maya44.c
sound/pci/oxygen/xonar_cs43xx.c
tools/perf/Documentation/perf-annotate.txt
tools/perf/Documentation/perf-bench.txt
tools/perf/Documentation/perf-buildid-cache.txt
tools/perf/Documentation/perf-diff.txt
tools/perf/Documentation/perf-inject.txt [new file with mode: 0644]
tools/perf/Documentation/perf-kmem.txt
tools/perf/Documentation/perf-kvm.txt [new file with mode: 0644]
tools/perf/Documentation/perf-list.txt
tools/perf/Documentation/perf-probe.txt
tools/perf/Documentation/perf-record.txt
tools/perf/Documentation/perf-sched.txt
tools/perf/Documentation/perf-stat.txt
tools/perf/Documentation/perf-test.txt [new file with mode: 0644]
tools/perf/Documentation/perf-trace-perl.txt
tools/perf/Documentation/perf-trace-python.txt
tools/perf/Documentation/perf-trace.txt
tools/perf/Makefile
tools/perf/arch/powerpc/Makefile [new file with mode: 0644]
tools/perf/arch/powerpc/util/dwarf-regs.c [new file with mode: 0644]
tools/perf/arch/x86/Makefile [new file with mode: 0644]
tools/perf/arch/x86/util/dwarf-regs.c [new file with mode: 0644]
tools/perf/bench/mem-memcpy.c
tools/perf/bench/sched-messaging.c
tools/perf/bench/sched-pipe.c
tools/perf/builtin-annotate.c
tools/perf/builtin-bench.c
tools/perf/builtin-buildid-cache.c
tools/perf/builtin-buildid-list.c
tools/perf/builtin-diff.c
tools/perf/builtin-help.c
tools/perf/builtin-inject.c [new file with mode: 0644]
tools/perf/builtin-kmem.c
tools/perf/builtin-kvm.c [new file with mode: 0644]
tools/perf/builtin-lock.c
tools/perf/builtin-probe.c
tools/perf/builtin-record.c
tools/perf/builtin-report.c
tools/perf/builtin-sched.c
tools/perf/builtin-stat.c
tools/perf/builtin-test.c [new file with mode: 0644]
tools/perf/builtin-timechart.c
tools/perf/builtin-top.c
tools/perf/builtin-trace.c
tools/perf/builtin.h
tools/perf/command-list.txt
tools/perf/perf-archive.sh
tools/perf/perf.c
tools/perf/perf.h
tools/perf/scripts/perl/Perf-Trace-Util/lib/Perf/Trace/Util.pm
tools/perf/scripts/perl/bin/check-perf-trace-record
tools/perf/scripts/perl/bin/failed-syscalls-record
tools/perf/scripts/perl/bin/failed-syscalls-report
tools/perf/scripts/perl/bin/rw-by-file-record
tools/perf/scripts/perl/bin/rw-by-file-report
tools/perf/scripts/perl/bin/rw-by-pid-record
tools/perf/scripts/perl/bin/rw-by-pid-report
tools/perf/scripts/perl/bin/rwtop-record [new file with mode: 0644]
tools/perf/scripts/perl/bin/rwtop-report [new file with mode: 0644]
tools/perf/scripts/perl/bin/wakeup-latency-record
tools/perf/scripts/perl/bin/wakeup-latency-report
tools/perf/scripts/perl/bin/workqueue-stats-record
tools/perf/scripts/perl/bin/workqueue-stats-report
tools/perf/scripts/perl/failed-syscalls.pl
tools/perf/scripts/perl/rw-by-pid.pl
tools/perf/scripts/perl/rwtop.pl [new file with mode: 0644]
tools/perf/scripts/perl/wakeup-latency.pl
tools/perf/scripts/perl/workqueue-stats.pl
tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
tools/perf/scripts/python/bin/failed-syscalls-by-pid-record
tools/perf/scripts/python/bin/failed-syscalls-by-pid-report
tools/perf/scripts/python/bin/sctop-record [new file with mode: 0644]
tools/perf/scripts/python/bin/sctop-report [new file with mode: 0644]
tools/perf/scripts/python/bin/syscall-counts-by-pid-record
tools/perf/scripts/python/bin/syscall-counts-by-pid-report
tools/perf/scripts/python/bin/syscall-counts-record
tools/perf/scripts/python/bin/syscall-counts-report
tools/perf/scripts/python/sctop.py [new file with mode: 0644]
tools/perf/util/PERF-VERSION-GEN
tools/perf/util/bitmap.c [new file with mode: 0644]
tools/perf/util/build-id.c
tools/perf/util/cache.h
tools/perf/util/callchain.c
tools/perf/util/callchain.h
tools/perf/util/color.c
tools/perf/util/color.h
tools/perf/util/debug.c
tools/perf/util/debug.h
tools/perf/util/event.c
tools/perf/util/event.h
tools/perf/util/header.c
tools/perf/util/header.h
tools/perf/util/hist.c
tools/perf/util/hist.h
tools/perf/util/hweight.c [new file with mode: 0644]
tools/perf/util/include/asm/bitops.h [deleted file]
tools/perf/util/include/asm/hweight.h [new file with mode: 0644]
tools/perf/util/include/dwarf-regs.h [new file with mode: 0644]
tools/perf/util/include/linux/bitmap.h
tools/perf/util/include/linux/bitops.h
tools/perf/util/include/linux/compiler.h
tools/perf/util/include/linux/kernel.h
tools/perf/util/map.c
tools/perf/util/map.h
tools/perf/util/newt.c [new file with mode: 0644]
tools/perf/util/parse-events.c
tools/perf/util/parse-events.h
tools/perf/util/parse-options.c
tools/perf/util/parse-options.h
tools/perf/util/probe-event.c
tools/perf/util/probe-event.h
tools/perf/util/probe-finder.c
tools/perf/util/probe-finder.h
tools/perf/util/pstack.c [new file with mode: 0644]
tools/perf/util/pstack.h [new file with mode: 0644]
tools/perf/util/scripting-engines/trace-event-perl.c
tools/perf/util/scripting-engines/trace-event-python.c
tools/perf/util/session.c
tools/perf/util/session.h
tools/perf/util/sort.c
tools/perf/util/sort.h
tools/perf/util/string.c
tools/perf/util/string.h [deleted file]
tools/perf/util/symbol.c
tools/perf/util/symbol.h
tools/perf/util/thread.c
tools/perf/util/thread.h
tools/perf/util/trace-event-info.c
tools/perf/util/trace-event-parse.c
tools/perf/util/trace-event-read.c
tools/perf/util/trace-event.h
tools/perf/util/util.c
tools/perf/util/util.h
virt/kvm/ioapic.c
virt/kvm/ioapic.h
virt/kvm/iommu.c

index 1423d2570d78833b8421f51e248f4dabbd3f5bc5..44c6dcc93d6dad8e9cee2cadb9f49fa992c5eb00 100644 (file)
@@ -3,35 +3,79 @@ Using RCU's CPU Stall Detector
 The CONFIG_RCU_CPU_STALL_DETECTOR kernel config parameter enables
 RCU's CPU stall detector, which detects conditions that unduly delay
 RCU grace periods.  The stall detector's idea of what constitutes
-"unduly delayed" is controlled by a pair of C preprocessor macros:
+"unduly delayed" is controlled by a set of C preprocessor macros:
 
 RCU_SECONDS_TILL_STALL_CHECK
 
        This macro defines the period of time that RCU will wait from
        the beginning of a grace period until it issues an RCU CPU
-       stall warning.  It is normally ten seconds.
+       stall warning.  This time period is normally ten seconds.
 
 RCU_SECONDS_TILL_STALL_RECHECK
 
        This macro defines the period of time that RCU will wait after
-       issuing a stall warning until it issues another stall warning.
-       It is normally set to thirty seconds.
+       issuing a stall warning until it issues another stall warning
+       for the same stall.  This time period is normally set to thirty
+       seconds.
 
 RCU_STALL_RAT_DELAY
 
-       The CPU stall detector tries to make the offending CPU rat on itself,
-       as this often gives better-quality stack traces.  However, if
-       the offending CPU does not detect its own stall in the number
-       of jiffies specified by RCU_STALL_RAT_DELAY, then other CPUs will
-       complain.  This is normally set to two jiffies.
+       The CPU stall detector tries to make the offending CPU print its
+       own warnings, as this often gives better-quality stack traces.
+       However, if the offending CPU does not detect its own stall in
+       the number of jiffies specified by RCU_STALL_RAT_DELAY, then
+       some other CPU will complain.  This delay is normally set to
+       two jiffies.
 
-The following problems can result in an RCU CPU stall warning:
+When a CPU detects that it is stalling, it will print a message similar
+to the following:
+
+INFO: rcu_sched_state detected stall on CPU 5 (t=2500 jiffies)
+
+This message indicates that CPU 5 detected that it was causing a stall,
+and that the stall was affecting RCU-sched.  This message will normally be
+followed by a stack dump of the offending CPU.  On TREE_RCU kernel builds,
+RCU and RCU-sched are implemented by the same underlying mechanism,
+while on TREE_PREEMPT_RCU kernel builds, RCU is instead implemented
+by rcu_preempt_state.
+
+On the other hand, if the offending CPU fails to print out a stall-warning
+message quickly enough, some other CPU will print a message similar to
+the following:
+
+INFO: rcu_bh_state detected stalls on CPUs/tasks: { 3 5 } (detected by 2, 2502 jiffies)
+
+This message indicates that CPU 2 detected that CPUs 3 and 5 were both
+causing stalls, and that the stall was affecting RCU-bh.  This message
+will normally be followed by stack dumps for each CPU.  Please note that
+TREE_PREEMPT_RCU builds can be stalled by tasks as well as by CPUs,
+and that the tasks will be indicated by PID, for example, "P3421".
+It is even possible for a rcu_preempt_state stall to be caused by both
+CPUs -and- tasks, in which case the offending CPUs and tasks will all
+be called out in the list.
+
+Finally, if the grace period ends just as the stall warning starts
+printing, there will be a spurious stall-warning message:
+
+INFO: rcu_bh_state detected stalls on CPUs/tasks: { } (detected by 4, 2502 jiffies)
+
+This is rare, but does happen from time to time in real life.
+
+So your kernel printed an RCU CPU stall warning.  The next question is
+"What caused it?"  The following problems can result in RCU CPU stall
+warnings:
 
 o      A CPU looping in an RCU read-side critical section.
        
-o      A CPU looping with interrupts disabled.
+o      A CPU looping with interrupts disabled.  This condition can
+       result in RCU-sched and RCU-bh stalls.
 
-o      A CPU looping with preemption disabled.
+o      A CPU looping with preemption disabled.  This condition can
+       result in RCU-sched stalls and, if ksoftirqd is in use, RCU-bh
+       stalls.
+
+o      A CPU looping with bottom halves disabled.  This condition can
+       result in RCU-sched and RCU-bh stalls.
 
 o      For !CONFIG_PREEMPT kernels, a CPU looping anywhere in the kernel
        without invoking schedule().
@@ -39,20 +83,24 @@ o   For !CONFIG_PREEMPT kernels, a CPU looping anywhere in the kernel
 o      A bug in the RCU implementation.
 
 o      A hardware failure.  This is quite unlikely, but has occurred
-       at least once in a former life.  A CPU failed in a running system,
+       at least once in real life.  A CPU failed in a running system,
        becoming unresponsive, but not causing an immediate crash.
        This resulted in a series of RCU CPU stall warnings, eventually
        leading the realization that the CPU had failed.
 
-The RCU, RCU-sched, and RCU-bh implementations have CPU stall warning.
-SRCU does not do so directly, but its calls to synchronize_sched() will
-result in RCU-sched detecting any CPU stalls that might be occurring.
-
-To diagnose the cause of the stall, inspect the stack traces.  The offending
-function will usually be near the top of the stack.  If you have a series
-of stall warnings from a single extended stall, comparing the stack traces
-can often help determine where the stall is occurring, which will usually
-be in the function nearest the top of the stack that stays the same from
-trace to trace.
+The RCU, RCU-sched, and RCU-bh implementations have CPU stall
+warning.  SRCU does not have its own CPU stall warnings, but its
+calls to synchronize_sched() will result in RCU-sched detecting
+RCU-sched-related CPU stalls.  Please note that RCU only detects
+CPU stalls when there is a grace period in progress.  No grace period,
+no CPU stall warnings.
+
+To diagnose the cause of the stall, inspect the stack traces.
+The offending function will usually be near the top of the stack.
+If you have a series of stall warnings from a single extended stall,
+comparing the stack traces can often help determine where the stall
+is occurring, which will usually be in the function nearest the top of
+that portion of the stack which remains the same from trace to trace.
+If you can reliably trigger the stall, ftrace can be quite helpful.
 
 RCU bugs can often be debugged with the help of CONFIG_RCU_TRACE.
index 0e50bc2aa1e2e4f4682f5b5540a49987bfb00884..5d9016795fd825a43f2a4093e4edd870cb92e42c 100644 (file)
@@ -182,16 +182,6 @@ Similarly, sched_expedited RCU provides the following:
        sched_expedited-torture: Reader Pipe:  12660320201 95875 0 0 0 0 0 0 0 0 0
        sched_expedited-torture: Reader Batch:  12660424885 0 0 0 0 0 0 0 0 0 0
        sched_expedited-torture: Free-Block Circulation:  1090795 1090795 1090794 1090793 1090792 1090791 1090790 1090789 1090788 1090787 0
-       state: -1 / 0:0 3:0 4:0
-
-As before, the first four lines are similar to those for RCU.
-The last line shows the task-migration state.  The first number is
--1 if synchronize_sched_expedited() is idle, -2 if in the process of
-posting wakeups to the migration kthreads, and N when waiting on CPU N.
-Each of the colon-separated fields following the "/" is a CPU:state pair.
-Valid states are "0" for idle, "1" for waiting for quiescent state,
-"2" for passed through quiescent state, and "3" when a race with a
-CPU-hotplug event forces use of the synchronize_sched() primitive.
 
 
 USAGE
index 8608fd85e921844ab33406c7f7d32ae7ea6c7d18..efd8cc95c06b1470db165a74a0d99fd33ee17dea 100644 (file)
@@ -256,23 +256,23 @@ o Each element of the form "1/1 0:127 ^0" represents one struct
 The output of "cat rcu/rcu_pending" looks as follows:
 
 rcu_sched:
-  0 np=255892 qsp=53936 cbr=0 cng=14417 gpc=10033 gps=24320 nf=6445 nn=146741
-  1 np=261224 qsp=54638 cbr=0 cng=25723 gpc=16310 gps=2849 nf=5912 nn=155792
-  2 np=237496 qsp=49664 cbr=0 cng=2762 gpc=45478 gps=1762 nf=1201 nn=136629
-  3 np=236249 qsp=48766 cbr=0 cng=286 gpc=48049 gps=1218 nf=207 nn=137723
-  4 np=221310 qsp=46850 cbr=0 cng=26 gpc=43161 gps=4634 nf=3529 nn=123110
-  5 np=237332 qsp=48449 cbr=0 cng=54 gpc=47920 gps=3252 nf=201 nn=137456
-  6 np=219995 qsp=46718 cbr=0 cng=50 gpc=42098 gps=6093 nf=4202 nn=120834
-  7 np=249893 qsp=49390 cbr=0 cng=72 gpc=38400 gps=17102 nf=41 nn=144888
+  0 np=255892 qsp=53936 rpq=85 cbr=0 cng=14417 gpc=10033 gps=24320 nf=6445 nn=146741
+  1 np=261224 qsp=54638 rpq=33 cbr=0 cng=25723 gpc=16310 gps=2849 nf=5912 nn=155792
+  2 np=237496 qsp=49664 rpq=23 cbr=0 cng=2762 gpc=45478 gps=1762 nf=1201 nn=136629
+  3 np=236249 qsp=48766 rpq=98 cbr=0 cng=286 gpc=48049 gps=1218 nf=207 nn=137723
+  4 np=221310 qsp=46850 rpq=7 cbr=0 cng=26 gpc=43161 gps=4634 nf=3529 nn=123110
+  5 np=237332 qsp=48449 rpq=9 cbr=0 cng=54 gpc=47920 gps=3252 nf=201 nn=137456
+  6 np=219995 qsp=46718 rpq=12 cbr=0 cng=50 gpc=42098 gps=6093 nf=4202 nn=120834
+  7 np=249893 qsp=49390 rpq=42 cbr=0 cng=72 gpc=38400 gps=17102 nf=41 nn=144888
 rcu_bh:
-  0 np=146741 qsp=1419 cbr=0 cng=6 gpc=0 gps=0 nf=2 nn=145314
-  1 np=155792 qsp=12597 cbr=0 cng=0 gpc=4 gps=8 nf=3 nn=143180
-  2 np=136629 qsp=18680 cbr=0 cng=0 gpc=7 gps=6 nf=0 nn=117936
-  3 np=137723 qsp=2843 cbr=0 cng=0 gpc=10 gps=7 nf=0 nn=134863
-  4 np=123110 qsp=12433 cbr=0 cng=0 gpc=4 gps=2 nf=0 nn=110671
-  5 np=137456 qsp=4210 cbr=0 cng=0 gpc=6 gps=5 nf=0 nn=133235
-  6 np=120834 qsp=9902 cbr=0 cng=0 gpc=6 gps=3 nf=2 nn=110921
-  7 np=144888 qsp=26336 cbr=0 cng=0 gpc=8 gps=2 nf=0 nn=118542
+  0 np=146741 qsp=1419 rpq=6 cbr=0 cng=6 gpc=0 gps=0 nf=2 nn=145314
+  1 np=155792 qsp=12597 rpq=3 cbr=0 cng=0 gpc=4 gps=8 nf=3 nn=143180
+  2 np=136629 qsp=18680 rpq=1 cbr=0 cng=0 gpc=7 gps=6 nf=0 nn=117936
+  3 np=137723 qsp=2843 rpq=0 cbr=0 cng=0 gpc=10 gps=7 nf=0 nn=134863
+  4 np=123110 qsp=12433 rpq=0 cbr=0 cng=0 gpc=4 gps=2 nf=0 nn=110671
+  5 np=137456 qsp=4210 rpq=1 cbr=0 cng=0 gpc=6 gps=5 nf=0 nn=133235
+  6 np=120834 qsp=9902 rpq=2 cbr=0 cng=0 gpc=6 gps=3 nf=2 nn=110921
+  7 np=144888 qsp=26336 rpq=0 cbr=0 cng=0 gpc=8 gps=2 nf=0 nn=118542
 
 As always, this is once again split into "rcu_sched" and "rcu_bh"
 portions, with CONFIG_TREE_PREEMPT_RCU kernels having an additional
@@ -284,6 +284,9 @@ o   "np" is the number of times that __rcu_pending() has been invoked
 o      "qsp" is the number of times that the RCU was waiting for a
        quiescent state from this CPU.
 
+o      "rpq" is the number of times that the CPU had passed through
+       a quiescent state, but not yet reported it to RCU.
+
 o      "cbr" is the number of times that this CPU had RCU callbacks
        that had passed through a grace period, and were thus ready
        to be invoked.
index a4f30faa4f1f73ad4622b333007525f9134c21c4..1e359b62c40a2eb67e04ab299012760587cab29a 100644 (file)
@@ -316,7 +316,7 @@ address           perms offset  dev   inode      pathname
 08049000-0804a000 rw-p 00001000 03:00 8312       /opt/test
 0804a000-0806b000 rw-p 00000000 00:00 0          [heap]
 a7cb1000-a7cb2000 ---p 00000000 00:00 0
-a7cb2000-a7eb2000 rw-p 00000000 00:00 0          [threadstack:001ff4b4]
+a7cb2000-a7eb2000 rw-p 00000000 00:00 0
 a7eb2000-a7eb3000 ---p 00000000 00:00 0
 a7eb3000-a7ed5000 rw-p 00000000 00:00 0
 a7ed5000-a8008000 r-xp 00000000 03:00 4222       /lib/libc.so.6
@@ -352,7 +352,6 @@ is not associated with a file:
  [stack]                  = the stack of the main process
  [vdso]                   = the "virtual dynamic shared object",
                             the kernel system call handler
- [threadstack:xxxxxxxx]   = the stack of the thread, xxxxxxxx is the stack size
 
  or if empty, the mapping is anonymous.
 
index 907010cea9ada01dcfc301f1ad74cad870e777f8..567b7a8eb878e74bd064c6ab71c36325e045f4d8 100644 (file)
@@ -324,6 +324,8 @@ and is between 256 and 4096 characters. It is defined in the file
                                    they are unmapped. Otherwise they are
                                    flushed before they will be reused, which
                                    is a lot of faster
+                       off       - do not initialize any AMD IOMMU found in
+                                   the system
 
        amijoy.map=     [HW,JOY] Amiga joystick support
                        Map of devices attached to JOY0DAT and JOY1DAT
index 2f9115c0ae627f044f4a22266cd7037c9ba10fd8..61c291cddf1873f1a17ac7d65e4404d6612b7b0d 100644 (file)
@@ -165,8 +165,8 @@ the user entry_handler invocation is also skipped.
 
 1.4 How Does Jump Optimization Work?
 
-If you configured your kernel with CONFIG_OPTPROBES=y (currently
-this option is supported on x86/x86-64, non-preemptive kernel) and
+If your kernel is built with CONFIG_OPTPROBES=y (currently this flag
+is automatically set 'y' on x86/x86-64, non-preemptive kernel) and
 the "debug.kprobes_optimization" kernel parameter is set to 1 (see
 sysctl(8)), Kprobes tries to reduce probe-hit overhead by using a jump
 instruction instead of a breakpoint instruction at each probepoint.
@@ -271,8 +271,6 @@ tweak the kernel's execution path, you need to suppress optimization,
 using one of the following techniques:
 - Specify an empty function for the kprobe's post_handler or break_handler.
  or
-- Config CONFIG_OPTPROBES=n.
- or
 - Execute 'sysctl -w debug.kprobes_optimization=n'
 
 2. Architectures Supported
@@ -307,10 +305,6 @@ it useful to "Compile the kernel with debug info" (CONFIG_DEBUG_INFO),
 so you can use "objdump -d -l vmlinux" to see the source-to-object
 code mapping.
 
-If you want to reduce probing overhead, set "Kprobes jump optimization
-support" (CONFIG_OPTPROBES) to "y". You can find this option under the
-"Kprobes" line.
-
 4. API Reference
 
 The Kprobes API includes a "register" function and an "unregister"
index 6f33593e59e21d898fa38fd59ce297a438dfbdf1..8239ebbcddce1d9b84689b8e1be530243bee5f83 100644 (file)
@@ -211,7 +211,7 @@ provide fair CPU time to each such task group.  For example, it may be
 desirable to first provide fair CPU time to each user on the system and then to
 each task belonging to a user.
 
-CONFIG_GROUP_SCHED strives to achieve exactly that.  It lets tasks to be
+CONFIG_CGROUP_SCHED strives to achieve exactly that.  It lets tasks to be
 grouped and divides CPU time fairly among such groups.
 
 CONFIG_RT_GROUP_SCHED permits to group real-time (i.e., SCHED_FIFO and
@@ -220,38 +220,11 @@ SCHED_RR) tasks.
 CONFIG_FAIR_GROUP_SCHED permits to group CFS (i.e., SCHED_NORMAL and
 SCHED_BATCH) tasks.
 
-At present, there are two (mutually exclusive) mechanisms to group tasks for
-CPU bandwidth control purposes:
-
- - Based on user id (CONFIG_USER_SCHED)
-
-   With this option, tasks are grouped according to their user id.
-
- - Based on "cgroup" pseudo filesystem (CONFIG_CGROUP_SCHED)
-
-   This options needs CONFIG_CGROUPS to be defined, and lets the administrator
+   These options need CONFIG_CGROUPS to be defined, and let the administrator
    create arbitrary groups of tasks, using the "cgroup" pseudo filesystem.  See
    Documentation/cgroups/cgroups.txt for more information about this filesystem.
 
-Only one of these options to group tasks can be chosen and not both.
-
-When CONFIG_USER_SCHED is defined, a directory is created in sysfs for each new
-user and a "cpu_share" file is added in that directory.
-
-       # cd /sys/kernel/uids
-       # cat 512/cpu_share             # Display user 512's CPU share
-       1024
-       # echo 2048 > 512/cpu_share     # Modify user 512's CPU share
-       # cat 512/cpu_share             # Display user 512's CPU share
-       2048
-       #
-
-CPU bandwidth between two users is divided in the ratio of their CPU shares.
-For example: if you would like user "root" to get twice the bandwidth of user
-"guest," then set the cpu_share for both the users such that "root"'s cpu_share
-is twice "guest"'s cpu_share.
-
-When CONFIG_CGROUP_SCHED is defined, a "cpu.shares" file is created for each
+When CONFIG_FAIR_GROUP_SCHED is defined, a "cpu.shares" file is created for each
 group created using the pseudo filesystem.  See example steps below to create
 task groups and modify their CPU share using the "cgroups" pseudo filesystem.
 
@@ -273,24 +246,3 @@ task groups and modify their CPU share using the "cgroups" pseudo filesystem.
 
        # #Launch gmplayer (or your favourite movie player)
        # echo <movie_player_pid> > multimedia/tasks
-
-8. Implementation note: user namespaces
-
-User namespaces are intended to be hierarchical.  But they are currently
-only partially implemented.  Each of those has ramifications for CFS.
-
-First, since user namespaces are hierarchical, the /sys/kernel/uids
-presentation is inadequate.  Eventually we will likely want to use sysfs
-tagging to provide private views of /sys/kernel/uids within each user
-namespace.
-
-Second, the hierarchical nature is intended to support completely
-unprivileged use of user namespaces.  So if using user groups, then
-we want the users in a user namespace to be children of the user
-who created it.
-
-That is currently unimplemented.  So instead, every user in a new
-user namespace will receive 1024 shares just like any user in the
-initial user namespace.  Note that at the moment creation of a new
-user namespace requires each of CAP_SYS_ADMIN, CAP_SETUID, and
-CAP_SETGID.
index 86eabe6c3419fd4f26aba47a090ecc1caff9a1fd..605b0d40329d843f6c3b838cd4afa5e38438d31e 100644 (file)
@@ -126,23 +126,12 @@ priority!
 2.3 Basis for grouping tasks
 ----------------------------
 
-There are two compile-time settings for allocating CPU bandwidth. These are
-configured using the "Basis for grouping tasks" multiple choice menu under
-General setup > Group CPU Scheduler:
-
-a. CONFIG_USER_SCHED (aka "Basis for grouping tasks" =  "user id")
-
-This lets you use the virtual files under
-"/sys/kernel/uids/<uid>/cpu_rt_runtime_us" to control he CPU time reserved for
-each user .
-
-The other option is:
-
-.o CONFIG_CGROUP_SCHED (aka "Basis for grouping tasks" = "Control groups")
+Enabling CONFIG_RT_GROUP_SCHED lets you explicitly allocate real
+CPU bandwidth to task groups.
 
 This uses the /cgroup virtual file system and
 "/cgroup/<cgroup>/cpu.rt_runtime_us" to control the CPU time reserved for each
-control group instead.
+control group.
 
 For more information on working with control groups, you should read
 Documentation/cgroups/cgroups.txt as well.
@@ -161,8 +150,7 @@ For now, this can be simplified to just the following (but see Future plans):
 ===============
 
 There is work in progress to make the scheduling period for each group
-("/sys/kernel/uids/<uid>/cpu_rt_period_us" or
-"/cgroup/<cgroup>/cpu.rt_period_us" respectively) configurable as well.
+("/cgroup/<cgroup>/cpu.rt_period_us") configurable as well.
 
 The constraint on the period is that a subgroup must have a smaller or
 equal period to its parent. But realistically its not very useful _yet_
index a9100b28eb844da1974dd24dcaa2a320887eddda..ec94748ae65bf1c55c1359c5c9d71aac714b2e5e 100644 (file)
@@ -40,7 +40,9 @@ Synopsis of kprobe_events
   $stack       : Fetch stack address.
   $retval      : Fetch return value.(*)
   +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**)
-  NAME=FETCHARG: Set NAME as the argument name of FETCHARG.
+  NAME=FETCHARG : Set NAME as the argument name of FETCHARG.
+  FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types
+                 (u8/u16/u32/u64/s8/s16/s32/s64) are supported.
 
   (*) only for return probe.
   (**) this is useful for fetching a field of data structures.
index d5b0b1b6dc527d4dcfb52db4460520fc395d52cb..28332e1b0863c2b19e86c913f3508b20db97a502 100644 (file)
@@ -4165,6 +4165,7 @@ OPROFILE
 M:     Robert Richter <robert.richter@amd.com>
 L:     oprofile-list@lists.sf.net
 S:     Maintained
+F:     arch/*/include/asm/oprofile*.h
 F:     arch/*/oprofile/
 F:     drivers/oprofile/
 F:     include/linux/oprofile.h
@@ -4353,13 +4354,13 @@ M:      Paul Mackerras <paulus@samba.org>
 M:     Ingo Molnar <mingo@elte.hu>
 M:     Arnaldo Carvalho de Melo <acme@redhat.com>
 S:     Supported
-F:     kernel/perf_event.c
+F:     kernel/perf_event*.c
 F:     include/linux/perf_event.h
-F:     arch/*/kernel/perf_event.c
-F:     arch/*/kernel/*/perf_event.c
-F:     arch/*/kernel/*/*/perf_event.c
+F:     arch/*/kernel/perf_event*.c
+F:     arch/*/kernel/*/perf_event*.c
+F:     arch/*/kernel/*/*/perf_event*.c
 F:     arch/*/include/asm/perf_event.h
-F:     arch/*/lib/perf_event.c
+F:     arch/*/lib/perf_event*.c
 F:     arch/*/kernel/perf_callchain.c
 F:     tools/perf/
 
@@ -5492,7 +5493,7 @@ S:        Maintained
 F:     drivers/mmc/host/tmio_mmc.*
 
 TMPFS (SHMEM FILESYSTEM)
-M:     Hugh Dickins <hugh.dickins@tiscali.co.uk>
+M:     Hugh Dickins <hughd@google.com>
 L:     linux-mm@kvack.org
 S:     Maintained
 F:     include/linux/shmem_fs.h
index 701bc65b3952fdae5964caffad108cfbca672131..ebc8225f7a96734d316b67de361caa446830033b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 34
-EXTRAVERSION = -rc7
+EXTRAVERSION =
 NAME = Sheep on Meth
 
 # *DOCUMENTATION*
index e5eb1337a5377f5b131b2ba70efd8263b8057404..acda512da2e21b52a972bb4255404fab3fce7015 100644 (file)
@@ -42,15 +42,10 @@ config KPROBES
          If in doubt, say "N".
 
 config OPTPROBES
-       bool "Kprobes jump optimization support (EXPERIMENTAL)"
-       default y
-       depends on KPROBES
+       def_bool y
+       depends on KPROBES && HAVE_OPTPROBES
        depends on !PREEMPT
-       depends on HAVE_OPTPROBES
        select KALLSYMS_ALL
-       help
-         This option will allow kprobes to optimize breakpoint to
-         a jump for reducing its overhead.
 
 config HAVE_EFFICIENT_UNALIGNED_ACCESS
        bool
@@ -142,6 +137,17 @@ config HAVE_HW_BREAKPOINT
        bool
        depends on PERF_EVENTS
 
+config HAVE_MIXED_BREAKPOINTS_REGS
+       bool
+       depends on HAVE_HW_BREAKPOINT
+       help
+         Depending on the arch implementation of hardware breakpoints,
+         some of them have separate registers for data and instruction
+         breakpoints addresses, others have mixed registers to store
+         them but define the access type in a control register.
+         Select this option if your arch implements breakpoints under the
+         latter fashion.
+
 config HAVE_USER_RETURN_NOTIFIER
        bool
 
index 610dff44d94b9bfae101f76149f965b4400d07ff..e756d04b6cd5dcdf07b4f394b8be15f1814c4849 100644 (file)
@@ -17,8 +17,8 @@
 #define ATOMIC_INIT(i)         ( (atomic_t) { (i) } )
 #define ATOMIC64_INIT(i)       ( (atomic64_t) { (i) } )
 
-#define atomic_read(v)         ((v)->counter + 0)
-#define atomic64_read(v)       ((v)->counter + 0)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
+#define atomic64_read(v)       (*(volatile long *)&(v)->counter)
 
 #define atomic_set(v,i)                ((v)->counter = (i))
 #define atomic64_set(v,i)      ((v)->counter = (i))
index e8ddec2cb158763d5d0a7741d44ee9e25d90696d..a0162fa9456496662adb28898fcb44776e628414 100644 (file)
@@ -24,7 +24,7 @@
  * strex/ldrex monitor on some implementations. The reason we can use it for
  * atomic_set() is the clrex or dummy strex done on every exception return.
  */
-#define atomic_read(v) ((v)->counter)
+#define atomic_read(v) (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)        (((v)->counter) = (i))
 
 #if __LINUX_ARM_ARCH__ >= 6
index 0d08d4170b64d08f2206ce292489a917a8cb0e99..4656a24058d21f75d30097ae5b06a1b66863bdd9 100644 (file)
@@ -371,6 +371,10 @@ static inline void __flush_icache_all(void)
 #ifdef CONFIG_ARM_ERRATA_411920
        extern void v6_icache_inval_all(void);
        v6_icache_inval_all();
+#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
+       asm("mcr        p15, 0, %0, c7, c1, 0   @ invalidate I-cache inner shareable\n"
+           :
+           : "r" (0));
 #else
        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
            :
index 7be0978b2625c9e365fde3d28ca4679d1e9c4933..634f357be6bb787d8a578cfa90a99b7742529b19 100644 (file)
@@ -1,6 +1,23 @@
 #ifndef __ASMARM_SMP_TWD_H
 #define __ASMARM_SMP_TWD_H
 
+#define TWD_TIMER_LOAD                 0x00
+#define TWD_TIMER_COUNTER              0x04
+#define TWD_TIMER_CONTROL              0x08
+#define TWD_TIMER_INTSTAT              0x0C
+
+#define TWD_WDOG_LOAD                  0x20
+#define TWD_WDOG_COUNTER               0x24
+#define TWD_WDOG_CONTROL               0x28
+#define TWD_WDOG_INTSTAT               0x2C
+#define TWD_WDOG_RESETSTAT             0x30
+#define TWD_WDOG_DISABLE               0x34
+
+#define TWD_TIMER_CONTROL_ENABLE       (1 << 0)
+#define TWD_TIMER_CONTROL_ONESHOT      (0 << 1)
+#define TWD_TIMER_CONTROL_PERIODIC     (1 << 1)
+#define TWD_TIMER_CONTROL_IT_ENABLE    (1 << 2)
+
 struct clock_event_device;
 
 extern void __iomem *twd_base;
index e085e2c545ebabad792dfa6e25fb149eb3cada27..bd863d8608cd04013e76e9b6ebde8225e0c078d7 100644 (file)
@@ -46,6 +46,9 @@
 #define TLB_V7_UIS_FULL (1 << 20)
 #define TLB_V7_UIS_ASID (1 << 21)
 
+/* Inner Shareable BTB operation (ARMv7 MP extensions) */
+#define TLB_V7_IS_BTB  (1 << 22)
+
 #define TLB_L2CLEAN_FR (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN     (1 << 30)
 #define TLB_WB         (1 << 31)
 #endif
 
 #ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
                         TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
 #else
 #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
@@ -339,6 +342,12 @@ static inline void local_flush_tlb_all(void)
                dsb();
                isb();
        }
+       if (tlb_flag(TLB_V7_IS_BTB)) {
+               /* flush the branch target cache */
+               asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
+               dsb();
+               isb();
+       }
 }
 
 static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -376,6 +385,12 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                dsb();
        }
+       if (tlb_flag(TLB_V7_IS_BTB)) {
+               /* flush the branch target cache */
+               asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
+               dsb();
+               isb();
+       }
 }
 
 static inline void
@@ -416,6 +431,12 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                dsb();
        }
+       if (tlb_flag(TLB_V7_IS_BTB)) {
+               /* flush the branch target cache */
+               asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
+               dsb();
+               isb();
+       }
 }
 
 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -454,6 +475,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
                dsb();
                isb();
        }
+       if (tlb_flag(TLB_V7_IS_BTB)) {
+               /* flush the branch target cache */
+               asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
+               dsb();
+               isb();
+       }
 }
 
 /*
index ea02a7b1c244af0afd610f6fc00c7f836f72ae4d..7c5f0c024db7e468aba3a185bded3bf3fde7073a 100644 (file)
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
 
-#define TWD_TIMER_LOAD                         0x00
-#define TWD_TIMER_COUNTER              0x04
-#define TWD_TIMER_CONTROL              0x08
-#define TWD_TIMER_INTSTAT              0x0C
-
-#define TWD_WDOG_LOAD                  0x20
-#define TWD_WDOG_COUNTER               0x24
-#define TWD_WDOG_CONTROL               0x28
-#define TWD_WDOG_INTSTAT               0x2C
-#define TWD_WDOG_RESETSTAT             0x30
-#define TWD_WDOG_DISABLE               0x34
-
-#define TWD_TIMER_CONTROL_ENABLE       (1 << 0)
-#define TWD_TIMER_CONTROL_ONESHOT      (0 << 1)
-#define TWD_TIMER_CONTROL_PERIODIC     (1 << 1)
-#define TWD_TIMER_CONTROL_IT_ENABLE    (1 << 2)
-
 /* set up by the platform code */
 void __iomem *twd_base;
 
index 5e3f99620c0440d7f73981cd325e938a0c2a2c27..14a0d988c82cb41ab88acd4d924bf75aa87efce3 100644 (file)
@@ -45,6 +45,7 @@ USER(         strnebt r2, [r0])
                mov     r0, #0
                ldmfd   sp!, {r1, pc}
 ENDPROC(__clear_user)
+ENDPROC(__clear_user_std)
 
                .pushsection .fixup,"ax"
                .align  0
index 027b69bdbad1b1db71319eb4f393d1dfea58e859..d066df686e17877c9e5efbbd57e07615398f6a0a 100644 (file)
@@ -93,6 +93,7 @@ WEAK(__copy_to_user)
 #include "copy_template.S"
 
 ENDPROC(__copy_to_user)
+ENDPROC(__copy_to_user_std)
 
        .pushsection .fixup,"ax"
        .align 0
index 122e61a9f505a6e3142a8a203c765f879ad53802..e8cb982f5e8ebe932e4f2ba131e2a3812eea1bcd 100644 (file)
@@ -410,7 +410,7 @@ static struct clk_lookup da830_clks[] = {
        CLK("davinci-mcasp.0",  NULL,           &mcasp0_clk),
        CLK("davinci-mcasp.1",  NULL,           &mcasp1_clk),
        CLK("davinci-mcasp.2",  NULL,           &mcasp2_clk),
-       CLK("musb_hdrc",        NULL,           &usb20_clk),
+       CLK(NULL,               "usb20",        &usb20_clk),
        CLK(NULL,               "aemif",        &aemif_clk),
        CLK(NULL,               "aintc",        &aintc_clk),
        CLK(NULL,               "secu_mgr",     &secu_mgr_clk),
index 9d89c67a1cc3902c32b5aed501d27f28b091695c..e46ecd8471383102b52e5c6475873f3f4bdfc65d 100644 (file)
@@ -211,6 +211,9 @@ v6_dma_inv_range:
        mcrne   p15, 0, r1, c7, c15, 1          @ clean & invalidate unified line
 #endif
 1:
+#ifdef CONFIG_SMP
+       str     r0, [r0]                        @ write for ownership
+#endif
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D line
 #else
@@ -231,6 +234,9 @@ v6_dma_inv_range:
 v6_dma_clean_range:
        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
+#ifdef CONFIG_SMP
+       ldr     r2, [r0]                        @ read for ownership
+#endif
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c10, 1          @ clean D line
 #else
@@ -251,6 +257,10 @@ v6_dma_clean_range:
 ENTRY(v6_dma_flush_range)
        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
+#ifdef CONFIG_SMP
+       ldr     r2, [r0]                        @ read for ownership
+       str     r2, [r0]                        @ write for ownership
+#endif
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 #else
@@ -273,7 +283,9 @@ ENTRY(v6_dma_map_area)
        add     r1, r1, r0
        teq     r2, #DMA_FROM_DEVICE
        beq     v6_dma_inv_range
-       b       v6_dma_clean_range
+       teq     r2, #DMA_TO_DEVICE
+       beq     v6_dma_clean_range
+       b       v6_dma_flush_range
 ENDPROC(v6_dma_map_area)
 
 /*
@@ -283,9 +295,6 @@ ENDPROC(v6_dma_map_area)
  *     - dir   - DMA direction
  */
 ENTRY(v6_dma_unmap_area)
-       add     r1, r1, r0
-       teq     r2, #DMA_TO_DEVICE
-       bne     v6_dma_inv_range
        mov     pc, lr
 ENDPROC(v6_dma_unmap_area)
 
index bcd64f265870804532dc6012274bca6e398a0622..06a90dcfc60a6f0cc0b88d5a02bfefdbfeb8610a 100644 (file)
@@ -167,7 +167,11 @@ ENTRY(v7_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mov     r0, #0
+#ifdef CONFIG_SMP
+       mcr     p15, 0, r0, c7, c1, 6           @ invalidate BTB Inner Shareable
+#else
        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
+#endif
        dsb
        isb
        mov     pc, lr
index 9bfeb6b9509ad3480bd33a664e51b4f94311bfbb..33b327379f0756e14eff3d9f0cd23a2f022eb112 100644 (file)
@@ -65,6 +65,15 @@ void flush_dcache_page(struct page *page)
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                      unsigned long uaddr, void *dst, const void *src,
+                      unsigned long len)
+{
+       memcpy(dst, src, len);
+       if (vma->vm_flags & VM_EXEC)
+               __cpuc_coherent_user_range(uaddr, uaddr + len);
+}
+
 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
                                size_t size, unsigned int mtype)
 {
@@ -87,8 +96,8 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
-                           unsigned int mtype, void *caller)
+void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+                                  unsigned int mtype, void *caller)
 {
        return __arm_ioremap(phys_addr, size, mtype);
 }
index 0cb1848bd876010a850edf2f9831cdf855f01c50..f3f288a9546d2a89f4f6d940c6387062ef8ff143 100644 (file)
@@ -50,7 +50,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
        cmp     r0, r1
        blo     1b
        mov     ip, #0
+#ifdef CONFIG_SMP
+       mcr     p15, 0, ip, c7, c1, 6           @ flush BTAC/BTB Inner Shareable
+#else
        mcr     p15, 0, ip, c7, c5, 6           @ flush BTAC/BTB
+#endif
        dsb
        mov     pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -79,7 +83,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
        cmp     r0, r1
        blo     1b
        mov     r2, #0
+#ifdef CONFIG_SMP
+       mcr     p15, 0, r2, c7, c1, 6           @ flush BTAC/BTB Inner Shareable
+#else
        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
+#endif
        dsb
        isb
        mov     pc, lr
index b131c27ddf5785883a1c28a3078cf6f1bd5a5c0e..bbce6a1c6bb67b873918a32fc68e9a6ea1e5890b 100644 (file)
@@ -19,7 +19,7 @@
 
 #define ATOMIC_INIT(i)  { (i) }
 
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v, i)       (((v)->counter) = i)
 
 /*
index a6aca819e9f334050d6927146fa0a2941901c1e6..88dc9b9c4ba051f84988926c4ab304af8091bc27 100644 (file)
@@ -15,7 +15,7 @@
 
 #define ATOMIC_INIT(i)  { (i) }
 
-#define atomic_read(v) ((v)->counter)
+#define atomic_read(v) (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i) (((v)->counter) = (i))
 
 /* These should be written in asm but we do it in C for now. */
index 00a57af79afc6b7d6d45fd1046dd96abdf35184b..fae32c7fdcb6619c487f3786993c70b6b0481788 100644 (file)
@@ -36,7 +36,7 @@
 #define smp_mb__after_atomic_inc()     barrier()
 
 #define ATOMIC_INIT(i)         { (i) }
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v, i)       (((v)->counter) = (i))
 
 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
index 33c8c0fa9583e0c2794cf0950006d824da961778..e936804b7508758112b853bfca42f9992ebadb44 100644 (file)
@@ -10,7 +10,7 @@
 
 #define ATOMIC_INIT(i) { (i) }
 
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v, i)       (((v)->counter) = i)
 
 #include <asm/system.h>
index 88405cb0832ae88e48f2770e5d8af797d519a346..4e1948447a00834969be528f7ac2a6a681ba1b44 100644 (file)
@@ -21,8 +21,8 @@
 #define ATOMIC_INIT(i)         ((atomic_t) { (i) })
 #define ATOMIC64_INIT(i)       ((atomic64_t) { (i) })
 
-#define atomic_read(v)         ((v)->counter)
-#define atomic64_read(v)       ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
+#define atomic64_read(v)       (*(volatile long *)&(v)->counter)
 
 #define atomic_set(v,i)                (((v)->counter) = (i))
 #define atomic64_set(v,i)      (((v)->counter) = (i))
index 63f0cf0f50dde3949725305e42fa6472971c6f45..d44a51e5271b7b5b10a5d8610ce1076f4e536be5 100644 (file)
@@ -26,7 +26,7 @@
  *
  * Atomically reads the value of @v.
  */
-#define atomic_read(v) ((v)->counter)
+#define atomic_read(v) (*(volatile int *)&(v)->counter)
 
 /**
  * atomic_set - set atomic variable
index 6a0d7650f980fcdcbd5d5ab3b4547f4120bc65b8..11dd30b16b3bc35b19f1d1e1c5e7ad7e9d73531d 100644 (file)
@@ -2,6 +2,6 @@
 # Makefile for Linux arch/m68k/amiga source directory
 #
 
-obj-y          := config.o amiints.o cia.o chipram.o amisound.o
+obj-y          := config.o amiints.o cia.o chipram.o amisound.o platform.o
 
 obj-$(CONFIG_AMIGA_PCMCIA)     += pcmcia.o
diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c
new file mode 100644 (file)
index 0000000..38f18bf
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ *  Copyright (C) 2007-2009 Geert Uytterhoeven
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/zorro.h>
+
+#include <asm/amigahw.h>
+
+
+#ifdef CONFIG_ZORRO
+
+static const struct resource zorro_resources[] __initconst = {
+       /* Zorro II regions (on Zorro II/III) */
+       {
+               .name   = "Zorro II exp",
+               .start  = 0x00e80000,
+               .end    = 0x00efffff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .name   = "Zorro II mem",
+               .start  = 0x00200000,
+               .end    = 0x009fffff,
+               .flags  = IORESOURCE_MEM,
+       },
+       /* Zorro III regions (on Zorro III only) */
+       {
+               .name   = "Zorro III exp",
+               .start  = 0xff000000,
+               .end    = 0xffffffff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .name   = "Zorro III cfg",
+               .start  = 0x40000000,
+               .end    = 0x7fffffff,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+
+static int __init amiga_init_bus(void)
+{
+       if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO))
+               return -ENODEV;
+
+       platform_device_register_simple("amiga-zorro", -1, zorro_resources,
+                                       AMIGAHW_PRESENT(ZORRO3) ? 4 : 2);
+       return 0;
+}
+
+subsys_initcall(amiga_init_bus);
+
+#endif /* CONFIG_ZORRO */
+
+
+static int __init amiga_init_devices(void)
+{
+       if (!MACH_IS_AMIGA)
+               return -ENODEV;
+
+       /* video hardware */
+       if (AMIGAHW_PRESENT(AMI_VIDEO))
+               platform_device_register_simple("amiga-video", -1, NULL, 0);
+
+
+       /* sound hardware */
+       if (AMIGAHW_PRESENT(AMI_AUDIO))
+               platform_device_register_simple("amiga-audio", -1, NULL, 0);
+
+
+       /* storage interfaces */
+       if (AMIGAHW_PRESENT(AMI_FLOPPY))
+               platform_device_register_simple("amiga-floppy", -1, NULL, 0);
+
+       return 0;
+}
+
+device_initcall(amiga_init_devices);
index b46ea1714a890aa8aae707a7fe1315f3d594ec20..cb8617bb194ba638eed418f27aff8fa61a9e1591 100644 (file)
@@ -9,7 +9,6 @@
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/miscdevice.h>
-#include <linux/smp_lock.h>
 #include <linux/ioport.h>
 #include <linux/capability.h>
 #include <linux/fcntl.h>
 static unsigned char days_in_mo[] =
 {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
 
-static char rtc_status;
+static atomic_t rtc_status = ATOMIC_INIT(1);
 
-static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-                    unsigned long arg)
+static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
        volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
        unsigned char msr;
@@ -132,29 +130,20 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 }
 
 /*
- *     We enforce only one user at a time here with the open/close.
- *     Also clear the previous interrupt data on an open, and clean
- *     up things on a close.
+ * We enforce only one user at a time here with the open/close.
  */
-
 static int rtc_open(struct inode *inode, struct file *file)
 {
-       lock_kernel();
-       if(rtc_status) {
-               unlock_kernel();
+       if (!atomic_dec_and_test(&rtc_status)) {
+               atomic_inc(&rtc_status);
                return -EBUSY;
        }
-
-       rtc_status = 1;
-       unlock_kernel();
        return 0;
 }
 
 static int rtc_release(struct inode *inode, struct file *file)
 {
-       lock_kernel();
-       rtc_status = 0;
-       unlock_kernel();
+       atomic_inc(&rtc_status);
        return 0;
 }
 
@@ -163,9 +152,9 @@ static int rtc_release(struct inode *inode, struct file *file)
  */
 
 static const struct file_operations rtc_fops = {
-       .ioctl =        rtc_ioctl,
-       .open =         rtc_open,
-       .release =      rtc_release,
+       .unlocked_ioctl = rtc_ioctl,
+       .open           = rtc_open,
+       .release        = rtc_release,
 };
 
 static struct miscdevice rtc_dev = {
index f5b3d098b0f5e1295a7f2653941de23c387ec227..7b98242960de76b58da5cd7fb1e72d0985091c0b 100644 (file)
@@ -1,4 +1,2 @@
 extern void hp300_sched_init(irq_handler_t vector);
-extern unsigned long hp300_gettimeoffset (void);
-
-
+extern unsigned long hp300_gettimeoffset(void);
index d9d2ed6474356f244dd5d585bc5840a5c16a9f99..6a223b3f7e74abe9faeed1345901171bca95a114 100644 (file)
@@ -15,7 +15,7 @@
 
 #define ATOMIC_INIT(i) { (i) }
 
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v, i)       (((v)->counter) = i)
 
 static inline void atomic_add(int i, atomic_t *v)
index 5674cb9449bd81278fa67e319a0b66abca0efd39..289310c63a8a5c361fe2f659205bd827b9889e7c 100644 (file)
@@ -15,7 +15,7 @@
 
 #define ATOMIC_INIT(i) { (i) }
 
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v, i)       (((v)->counter) = i)
 
 static __inline__ void atomic_add(int i, atomic_t *v)
index 9bde784e7bad038a41d471a22af238587a998aad..b4ecdaada5201b11281f57548d36daf3fff16342 100644 (file)
@@ -365,6 +365,10 @@ static inline int minix_test_bit(int nr, const void *vaddr)
 #define ext2_set_bit_atomic(lock, nr, addr)    test_and_set_bit((nr) ^ 24, (unsigned long *)(addr))
 #define ext2_clear_bit(nr, addr)               __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
 #define ext2_clear_bit_atomic(lock, nr, addr)  test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
+#define ext2_find_next_zero_bit(addr, size, offset) \
+       generic_find_next_zero_le_bit((unsigned long *)addr, size, offset)
+#define ext2_find_next_bit(addr, size, offset) \
+       generic_find_next_le_bit((unsigned long *)addr, size, offset)
 
 static inline int ext2_test_bit(int nr, const void *vaddr)
 {
@@ -394,10 +398,9 @@ static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
        return (p - addr) * 32 + res;
 }
 
-static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
-                                         unsigned offset)
+static inline unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
+               unsigned long size, unsigned long offset)
 {
-       const unsigned long *addr = vaddr;
        const unsigned long *p = addr + (offset >> 5);
        int bit = offset & 31UL, res;
 
@@ -437,10 +440,9 @@ static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
        return (p - addr) * 32 + res;
 }
 
-static inline int ext2_find_next_bit(const void *vaddr, unsigned size,
-                                    unsigned offset)
+static inline unsigned long generic_find_next_le_bit(const unsigned long *addr,
+               unsigned long size, unsigned long offset)
 {
-       const unsigned long *addr = vaddr;
        const unsigned long *p = addr + (offset >> 5);
        int bit = offset & 31UL, res;
 
index 85c41b75aa78d5f3dfa57f7f78fde49680a1a819..36265ccf5c7b520577d3729db545cfc8ea1a8b6b 100644 (file)
@@ -1,26 +1,12 @@
 #ifndef _M68K_PARAM_H
 #define _M68K_PARAM_H
 
-#ifdef __KERNEL__
-# define HZ            CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ       100             /* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC        (USER_HZ)       /* like times() */
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
 #ifdef __uClinux__
 #define EXEC_PAGESIZE  4096
 #else
 #define EXEC_PAGESIZE  8192
 #endif
 
-#ifndef NOGROUP
-#define NOGROUP                (-1)
-#endif
-
-#define MAXHOSTNAMELEN 64      /* max length of hostname */
+#include <asm-generic/param.h>
 
 #endif /* _M68K_PARAM_H */
index aacd6d17b83373b4bab02b0710e69978b5472c08..ada4f4cca811b6ea14e0406619d8d7181ae60b77 100644 (file)
@@ -455,7 +455,7 @@ static inline void access_error040(struct frame *fp)
 
                if (do_page_fault(&fp->ptregs, addr, errorcode)) {
 #ifdef DEBUG
-                       printk("do_page_fault() !=0 \n");
+                       printk("do_page_fault() !=0\n");
 #endif
                        if (user_mode(&fp->ptregs)){
                                /* delay writebacks after signal delivery */
index 0356da9bf763abacdb678c7af196a091fd7300d3..1c16b1baf8dbf9e7b03f22cd663192c83aa07cf7 100644 (file)
@@ -148,7 +148,7 @@ static void mac_cache_card_flush(int writeback)
 void __init config_mac(void)
 {
        if (!MACH_IS_MAC)
-               printk(KERN_ERR "ERROR: no Mac, but config_mac() called!! \n");
+               printk(KERN_ERR "ERROR: no Mac, but config_mac() called!!\n");
 
        mach_sched_init = mac_sched_init;
        mach_init_IRQ = mac_init_IRQ;
@@ -867,7 +867,7 @@ static void __init mac_identify(void)
         */
        iop_preinit();
 
-       printk(KERN_INFO "Detected Macintosh model: %d \n", model);
+       printk(KERN_INFO "Detected Macintosh model: %d\n", model);
 
        /*
         * Report booter data:
@@ -878,12 +878,12 @@ static void __init mac_identify(void)
                mac_bi_data.videoaddr, mac_bi_data.videorow,
                mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF,
                mac_bi_data.dimensions >> 16);
-       printk(KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx \n",
+       printk(KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx\n",
                mac_bi_data.videological, mac_orig_videoaddr,
                mac_bi_data.sccbase);
-       printk(KERN_DEBUG " Boottime: 0x%lx GMTBias: 0x%lx \n",
+       printk(KERN_DEBUG " Boottime: 0x%lx GMTBias: 0x%lx\n",
                mac_bi_data.boottime, mac_bi_data.gmtbias);
-       printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n",
+       printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx\n",
                mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize);
 
        iop_init();
index d0e35cf99fc69a531cb0239277c3351525c13773..a96394a0333d3d3c82cd70fbd4beb4764b02f018 100644 (file)
@@ -154,7 +154,6 @@ good_area:
         * the fault.
         */
 
- survive:
        fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
 #ifdef DEBUG
        printk("handle_mm_fault returns %d\n",fault);
@@ -180,15 +179,10 @@ good_area:
  */
 out_of_memory:
        up_read(&mm->mmap_sem);
-       if (is_global_init(current)) {
-               yield();
-               down_read(&mm->mmap_sem);
-               goto survive;
-       }
-
-       printk("VM: killing process %s\n", current->comm);
-       if (user_mode(regs))
-               do_group_exit(SIGKILL);
+       if (!user_mode(regs))
+               goto no_context;
+       pagefault_out_of_memory();
+       return 0;
 
 no_context:
        current->thread.signo = SIGBUS;
index 8da9c250d3e198e3a2b27d795b66ce9896fb13e1..11ac6f63967a24ac134e406d253400f3ff496bb0 100644 (file)
@@ -9,7 +9,6 @@
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/miscdevice.h>
-#include <linux/smp_lock.h>
 #include <linux/ioport.h>
 #include <linux/capability.h>
 #include <linux/fcntl.h>
@@ -36,8 +35,7 @@ static const unsigned char days_in_mo[] =
 
 static atomic_t rtc_ready = ATOMIC_INIT(1);
 
-static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-                    unsigned long arg)
+static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
        volatile MK48T08ptr_t rtc = (MK48T08ptr_t)MVME_RTC_BASE;
        unsigned long flags;
@@ -120,22 +118,15 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 }
 
 /*
- *     We enforce only one user at a time here with the open/close.
- *     Also clear the previous interrupt data on an open, and clean
- *     up things on a close.
+ * We enforce only one user at a time here with the open/close.
  */
-
 static int rtc_open(struct inode *inode, struct file *file)
 {
-       lock_kernel();
        if( !atomic_dec_and_test(&rtc_ready) )
        {
                atomic_inc( &rtc_ready );
-               unlock_kernel();
                return -EBUSY;
        }
-       unlock_kernel();
-
        return 0;
 }
 
@@ -150,9 +141,9 @@ static int rtc_release(struct inode *inode, struct file *file)
  */
 
 static const struct file_operations rtc_fops = {
-       .ioctl =        rtc_ioctl,
-       .open =         rtc_open,
-       .release =      rtc_release,
+       .unlocked_ioctl = rtc_ioctl,
+       .open           = rtc_open,
+       .release        = rtc_release,
 };
 
 static struct miscdevice rtc_dev=
index 31ab3f08bbda25ad37be9a26abeb3f511c25b554..ad10fecec2fe665d7dcf86936da97eae6bd25d0c 100644 (file)
@@ -126,7 +126,7 @@ static void q40_reset(void)
 {
         halted = 1;
         printk("\n\n*******************************************\n"
-               "Called q40_reset : press the RESET button!! \n"
+               "Called q40_reset : press the RESET button!!\n"
                "*******************************************\n");
        Q40_LED_ON();
        while (1)
index 446bec29b142bc5509a445f28146c166c756cb11..26460d15b338b65847bef4bd1925ca5a8ea40dff 100644 (file)
@@ -182,6 +182,39 @@ extern long __user_bad(void);
  * Returns zero on success, or -EFAULT on error.
  * On error, the variable @x is set to zero.
  */
+#define get_user(x, ptr)                                               \
+       __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user_check(x, ptr, size)                                 \
+({                                                                     \
+       unsigned long __gu_val = 0;                                     \
+       const typeof(*(ptr)) __user *__gu_addr = (ptr);                 \
+       int __gu_err = 0;                                               \
+                                                                       \
+       if (access_ok(VERIFY_READ, __gu_addr, size)) {                  \
+               switch (size) {                                         \
+               case 1:                                                 \
+                       __get_user_asm("lbu", __gu_addr, __gu_val,      \
+                                      __gu_err);                       \
+                       break;                                          \
+               case 2:                                                 \
+                       __get_user_asm("lhu", __gu_addr, __gu_val,      \
+                                      __gu_err);                       \
+                       break;                                          \
+               case 4:                                                 \
+                       __get_user_asm("lw", __gu_addr, __gu_val,       \
+                                      __gu_err);                       \
+                       break;                                          \
+               default:                                                \
+                       __gu_err = __user_bad();                        \
+                       break;                                          \
+               }                                                       \
+       } else {                                                        \
+               __gu_err = -EFAULT;                                     \
+       }                                                               \
+       x = (typeof(*(ptr)))__gu_val;                                   \
+       __gu_err;                                                       \
+})
 
 #define __get_user(x, ptr)                                             \
 ({                                                                     \
@@ -206,12 +239,6 @@ extern long __user_bad(void);
 })
 
 
-#define get_user(x, ptr)                                               \
-({                                                                     \
-       access_ok(VERIFY_READ, (ptr), sizeof(*(ptr)))                   \
-               ? __get_user((x), (ptr)) : -EFAULT;                     \
-})
-
 #define __put_user_asm(insn, __gu_ptr, __gu_val, __gu_err)     \
 ({                                                             \
        __asm__ __volatile__ (                                  \
@@ -266,6 +293,42 @@ extern long __user_bad(void);
  *
  * Returns zero on success, or -EFAULT on error.
  */
+#define put_user(x, ptr)                                               \
+       __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_check(x, ptr, size)                                 \
+({                                                                     \
+       typeof(*(ptr)) __pu_val;                                        \
+       typeof(*(ptr)) __user *__pu_addr = (ptr);                       \
+       int __pu_err = 0;                                               \
+                                                                       \
+       __pu_val = (x);                                                 \
+       if (access_ok(VERIFY_WRITE, __pu_addr, size)) {                 \
+               switch (size) {                                         \
+               case 1:                                                 \
+                       __put_user_asm("sb", __pu_addr, __pu_val,       \
+                                      __pu_err);                       \
+                       break;                                          \
+               case 2:                                                 \
+                       __put_user_asm("sh", __pu_addr, __pu_val,       \
+                                      __pu_err);                       \
+                       break;                                          \
+               case 4:                                                 \
+                       __put_user_asm("sw", __pu_addr, __pu_val,       \
+                                      __pu_err);                       \
+                       break;                                          \
+               case 8:                                                 \
+                       __put_user_asm_8(__pu_addr, __pu_val, __pu_err);\
+                       break;                                          \
+               default:                                                \
+                       __pu_err = __user_bad();                        \
+                       break;                                          \
+               }                                                       \
+       } else {                                                        \
+               __pu_err = -EFAULT;                                     \
+       }                                                               \
+       __pu_err;                                                       \
+})
 
 #define __put_user(x, ptr)                                             \
 ({                                                                     \
@@ -290,18 +353,6 @@ extern long __user_bad(void);
        __gu_err;                                                       \
 })
 
-#ifndef CONFIG_MMU
-
-#define put_user(x, ptr)       __put_user((x), (ptr))
-
-#else /* CONFIG_MMU */
-
-#define put_user(x, ptr)                                               \
-({                                                                     \
-       access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr)))                  \
-               ? __put_user((x), (ptr)) : -EFAULT;                     \
-})
-#endif /* CONFIG_MMU */
 
 /* copy_to_from_user */
 #define __copy_from_user(to, from, n)  \
index 21c3a92394de998dd17452ffa1f0f1ede0351ba2..109876e8d643a3b51eb41a91e7fc8adb9e1a5ec9 100644 (file)
@@ -137,8 +137,9 @@ do {                                                                        \
 do {                                                                   \
        int step = -line_length;                                        \
        int align = ~(line_length - 1);                                 \
+       int count;                                                      \
        end = ((end & align) == end) ? end - line_length : end & align; \
-       int count = end - start;                                        \
+       count = end - start;                                            \
        WARN_ON(count < 0);                                             \
                                                                        \
        __asm__ __volatile__ (" 1:      " #op " %0, %1;                 \
index 391d6197fc3bbfb309f7bf1824c16ef80d2ca4cc..8cc18cd2cce6a6f34186597dd7a66013066fa2aa 100644 (file)
@@ -476,6 +476,8 @@ ENTRY(ret_from_fork)
        nop
 
 work_pending:
+       enable_irq
+
        andi    r11, r19, _TIF_NEED_RESCHED
        beqi    r11, 1f
        bralid  r15, schedule
index bc4dcb7d3861c50aff24b152f37655c80c937d95..ff85f77180355fe6ba8a6c5c1cdeecfa25b5fa75 100644 (file)
@@ -52,3 +52,14 @@ EXPORT_SYMBOL_GPL(_ebss);
 extern void _mcount(void);
 EXPORT_SYMBOL(_mcount);
 #endif
+
+/*
+ * Assembly functions that may be used (directly or indirectly) by modules
+ */
+EXPORT_SYMBOL(__copy_tofrom_user);
+EXPORT_SYMBOL(__strncpy_user);
+
+#ifdef CONFIG_OPT_LIB_ASM
+EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(memmove);
+#endif
index cbecf110dc30dbd584672b680dad3920448138fa..0e73f6606547ce03f1be8c048971b9de6275c3a0 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/string.h>
 
 #include <asm/pgtable.h>
+#include <asm/cacheflush.h>
 
 void *module_alloc(unsigned long size)
 {
@@ -151,6 +152,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
 int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
                struct module *module)
 {
+       flush_dcache();
        return 0;
 }
 
index f42c2dde8b1cbd1752e81cea5e671b9070de0e1c..cca3579d4268d07aab1910a463180f9dd271a4e6 100644 (file)
@@ -47,6 +47,7 @@ unsigned long memory_start;
 EXPORT_SYMBOL(memory_start);
 unsigned long memory_end; /* due to mm/nommu.c */
 unsigned long memory_size;
+EXPORT_SYMBOL(memory_size);
 
 /*
  * paging_init() sets up the page tables - in fact we've already done this.
index 784557fb28cfc5dac6e67b77e85fc865d3332bbf..59bf2335a4ce06a9691c02b6f683036579a1381e 100644 (file)
@@ -42,6 +42,7 @@
 
 unsigned long ioremap_base;
 unsigned long ioremap_bot;
+EXPORT_SYMBOL(ioremap_bot);
 
 /* The maximum lowmem defaults to 768Mb, but this can be configured to
  * another value.
index 01c8c97c15b772c6d0bde3e753ac620cbbb8902b..9cb782b8e036f763b09d61054652897da5c9141b 100644 (file)
@@ -1507,7 +1507,7 @@ void pcibios_finish_adding_to_bus(struct pci_bus *bus)
        pci_bus_add_devices(bus);
 
        /* Fixup EEH */
-       eeh_add_device_tree_late(bus);
+       /* eeh_add_device_tree_late(bus); */
 }
 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
 
index 519197ede0898f2ce7bd0a3019fd4ac1f541d057..59dc0c7ef7334b2e28e4b508e03f84e8f2ea2aca 100644 (file)
@@ -29,7 +29,7 @@
  *
  * Atomically reads the value of @v.
  */
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 
 /*
  * atomic_set - set atomic variable
@@ -410,7 +410,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
  * @v: pointer of type atomic64_t
  *
  */
-#define atomic64_read(v)       ((v)->counter)
+#define atomic64_read(v)       (*(volatile long *)&(v)->counter)
 
 /*
  * atomic64_set - set atomic variable
index 032ca73f181bec27c0f7b741862ada66ec104342..48bb82372994c839f9e0f2d9be04b57bac38580c 100644 (file)
@@ -12,7 +12,7 @@
 #define PIT_CH0                        0x40
 #define PIT_CH2                        0x42
 
-extern spinlock_t i8253_lock;
+extern raw_spinlock_t i8253_lock;
 
 extern void setup_pit_timer(void);
 
index 49382d5e891a35a98b09be21abcdb13366b2cca9..c6e3c93ce7c7a5aad8267d88f8c0089301d1e239 100644 (file)
 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 
+/*
+ * Bits 18 - 20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD   0x001c0000
+
 /*
  * X the exception cause indicator
  * E the exception enable
 #define FPU_CSR_UDF_S   0x00000008
 #define FPU_CSR_INE_S   0x00000004
 
-/* rounding mode */
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM     0x00000003
 #define FPU_CSR_RN      0x0     /* nearest */
 #define FPU_CSR_RZ      0x1     /* towards zero */
 #define FPU_CSR_RU      0x2     /* towards +Infinity */
index ed5c441615e471cf4b4c1888bcce3eec9c84e6fa..94794062a1777814c03428b27576796fe3f2a7a7 100644 (file)
@@ -15,7 +15,7 @@
 #include <asm/io.h>
 #include <asm/time.h>
 
-DEFINE_SPINLOCK(i8253_lock);
+DEFINE_RAW_SPINLOCK(i8253_lock);
 EXPORT_SYMBOL(i8253_lock);
 
 /*
@@ -26,7 +26,7 @@ EXPORT_SYMBOL(i8253_lock);
 static void init_pit_timer(enum clock_event_mode mode,
                           struct clock_event_device *evt)
 {
-       spin_lock(&i8253_lock);
+       raw_spin_lock(&i8253_lock);
 
        switch(mode) {
        case CLOCK_EVT_MODE_PERIODIC:
@@ -55,7 +55,7 @@ static void init_pit_timer(enum clock_event_mode mode,
                /* Nothing to do here */
                break;
        }
-       spin_unlock(&i8253_lock);
+       raw_spin_unlock(&i8253_lock);
 }
 
 /*
@@ -65,10 +65,10 @@ static void init_pit_timer(enum clock_event_mode mode,
  */
 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
 {
-       spin_lock(&i8253_lock);
+       raw_spin_lock(&i8253_lock);
        outb_p(delta & 0xff , PIT_CH0); /* LSB */
        outb(delta >> 8 , PIT_CH0);     /* MSB */
-       spin_unlock(&i8253_lock);
+       raw_spin_unlock(&i8253_lock);
 
        return 0;
 }
@@ -137,7 +137,7 @@ static cycle_t pit_read(struct clocksource *cs)
        static int old_count;
        static u32 old_jifs;
 
-       spin_lock_irqsave(&i8253_lock, flags);
+       raw_spin_lock_irqsave(&i8253_lock, flags);
        /*
         * Although our caller may have the read side of xtime_lock,
         * this is now a seqlock, and we are cheating in this routine
@@ -183,7 +183,7 @@ static cycle_t pit_read(struct clocksource *cs)
        old_count = count;
        old_jifs = jifs;
 
-       spin_unlock_irqrestore(&i8253_lock, flags);
+       raw_spin_unlock_irqrestore(&i8253_lock, flags);
 
        count = (LATCH - 1) - count;
 
index 44337ba03717a573119659fcc94fec11c9564b61..a5297e2a353aede2279664446611de8100bf1f98 100644 (file)
@@ -385,7 +385,7 @@ EXPORT(sysn32_call_table)
        PTR     sys_fchmodat
        PTR     sys_faccessat
        PTR     compat_sys_pselect6
-       PTR     sys_ppoll                       /* 6265 */
+       PTR     compat_sys_ppoll                /* 6265 */
        PTR     sys_unshare
        PTR     sys_splice
        PTR     sys_sync_file_range
index 8f2f8e9d8b212ae5897c0aabee5dd35c46837680..f2338d1c0b4889a0bf216f1af9ac9e8adedb3ec1 100644 (file)
@@ -78,6 +78,9 @@ DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
 #define FPCREG_RID     0       /* $0  = revision id */
 #define FPCREG_CSR     31      /* $31 = csr */
 
+/* Determine rounding mode from the RM bits of the FCSR */
+#define modeindex(v) ((v) & FPU_CSR_RM)
+
 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
 static const unsigned char ieee_rm[4] = {
        [FPU_CSR_RN] = IEEE754_RN,
@@ -384,10 +387,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
                                        (void *) (xcp->cp0_epc),
                                        MIPSInst_RT(ir), value);
 #endif
-                               value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
-                               ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
-                               /* convert to ieee library modes */
-                               ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
+
+                               /*
+                                * Don't write reserved bits,
+                                * and convert to ieee library modes
+                                */
+                               ctx->fcr31 = (value &
+                                               ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
+                                               ieee_rm[modeindex(value)];
                        }
                        if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
                                return SIGFPE;
index 29e2326b62577b3d2f6c5ae2a2620ce0e532d731..fa3bf661ae299c1ca8d4012851bd6530c4828888 100644 (file)
@@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
         */
 
        /* Check whether the irq belongs to me */
-       enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
+       enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
        if (!enabled)
                return IRQ_NONE;
        enabled = reg.cnt1_enabled | reg.cnt2_enabled;
index 5bf5be9566dece295d8922a8c3c54aa9f5420615..e41222d6c2fd1a5d3a97a20482c09ff10b652eba 100644 (file)
@@ -31,7 +31,7 @@
  * Atomically reads the value of @v.  Note that the guaranteed
  * useful range of an atomic_t is only 24 bits.
  */
-#define atomic_read(v) ((v)->counter)
+#define atomic_read(v) (*(volatile int *)&(v)->counter)
 
 /**
  * atomic_set - set atomic variable
index 716634d1f5466645c7e6028bda01ca1abd1aeeac..f81955934aebf4dbf0e97add2e45bb6cdc9042fa 100644 (file)
@@ -189,7 +189,7 @@ static __inline__ void atomic_set(atomic_t *v, int i)
 
 static __inline__ int atomic_read(const atomic_t *v)
 {
-       return v->counter;
+       return (*(volatile int *)&(v)->counter);
 }
 
 /* exported interface */
@@ -286,7 +286,7 @@ atomic64_set(atomic64_t *v, s64 i)
 static __inline__ s64
 atomic64_read(const atomic64_t *v)
 {
-       return v->counter;
+       return (*(volatile long *)&(v)->counter);
 }
 
 #define atomic64_add(i,v)      ((void)(__atomic64_add_return( ((s64)(i)),(v))))
index 9f4c9d4f5803d10638b159abf8202e4283e5bca6..bd100fcf40d0c1263e81e5d737e2ec6cfc32b025 100644 (file)
@@ -130,43 +130,5 @@ static inline int irqs_disabled_flags(unsigned long flags)
  */
 struct irq_chip;
 
-#ifdef CONFIG_PERF_EVENTS
-
-#ifdef CONFIG_PPC64
-static inline unsigned long test_perf_event_pending(void)
-{
-       unsigned long x;
-
-       asm volatile("lbz %0,%1(13)"
-               : "=r" (x)
-               : "i" (offsetof(struct paca_struct, perf_event_pending)));
-       return x;
-}
-
-static inline void set_perf_event_pending(void)
-{
-       asm volatile("stb %0,%1(13)" : :
-               "r" (1),
-               "i" (offsetof(struct paca_struct, perf_event_pending)));
-}
-
-static inline void clear_perf_event_pending(void)
-{
-       asm volatile("stb %0,%1(13)" : :
-               "r" (0),
-               "i" (offsetof(struct paca_struct, perf_event_pending)));
-}
-#endif /* CONFIG_PPC64 */
-
-#else  /* CONFIG_PERF_EVENTS */
-
-static inline unsigned long test_perf_event_pending(void)
-{
-       return 0;
-}
-
-static inline void clear_perf_event_pending(void) {}
-#endif /* CONFIG_PERF_EVENTS */
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_HW_IRQ_H */
index 957ceb7059c57a8a2bd7c5ffd9330a361baaf160..c09138d150d41eae784608074aa1416ff40265d5 100644 (file)
@@ -133,7 +133,6 @@ int main(void)
        DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
        DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
        DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
-       DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_event_pending));
        DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
 #ifdef CONFIG_PPC_MM_SLICES
        DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
index 59c928564a038e490e260fb28862f022659d4d6f..4ff4da2c238bcd8585775cb4f2cb1432b89330c4 100644 (file)
@@ -1,7 +1,8 @@
 /*
  * Contains routines needed to support swiotlb for ppc.
  *
- * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Author: Becky Bruce
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -70,7 +71,7 @@ static int ppc_swiotlb_bus_notify(struct notifier_block *nb,
        sd->max_direct_dma_addr = 0;
 
        /* May need to bounce if the device can't address all of DRAM */
-       if (dma_get_mask(dev) < lmb_end_of_DRAM())
+       if ((dma_get_mask(dev) + 1) < lmb_end_of_DRAM())
                set_dma_ops(dev, &swiotlb_dma_ops);
 
        return NOTIFY_DONE;
index 07109d843787118dba501c5b9bb383912348417b..42e9d908914a0e47117cfe7f3dcc5fe50d215d98 100644 (file)
@@ -556,15 +556,6 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
 2:
        TRACE_AND_RESTORE_IRQ(r5);
 
-#ifdef CONFIG_PERF_EVENTS
-       /* check paca->perf_event_pending if we're enabling ints */
-       lbz     r3,PACAPERFPEND(r13)
-       and.    r3,r3,r5
-       beq     27f
-       bl      .perf_event_do_pending
-27:
-#endif /* CONFIG_PERF_EVENTS */
-
        /* extract EE bit and use it to restore paca->hard_enabled */
        ld      r3,_MSR(r1)
        rldicl  r4,r3,49,63             /* r0 = (r3 >> 15) & 1 */
index 64f6f2031c226901dc54105c7a0f433566e2846d..066bd31551d5414fb0a7a43ed85964c64665f042 100644 (file)
@@ -53,7 +53,6 @@
 #include <linux/bootmem.h>
 #include <linux/pci.h>
 #include <linux/debugfs.h>
-#include <linux/perf_event.h>
 
 #include <asm/uaccess.h>
 #include <asm/system.h>
@@ -145,11 +144,6 @@ notrace void raw_local_irq_restore(unsigned long en)
        }
 #endif /* CONFIG_PPC_STD_MMU_64 */
 
-       if (test_perf_event_pending()) {
-               clear_perf_event_pending();
-               perf_event_do_pending();
-       }
-
        /*
         * if (get_paca()->hard_enabled) return;
         * But again we need to take care that gcc gets hard_enabled directly
index 08460a2e9f4126228367bfaefaac76baeb5d09a7..43b83c35cf54b0dfb07bc5abef8ee558d5f3cd9c 100644 (file)
@@ -35,6 +35,9 @@ struct cpu_hw_events {
        u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
        unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
        unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
+
+       unsigned int group_flag;
+       int n_txn_start;
 };
 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 
@@ -718,66 +721,6 @@ static int collect_events(struct perf_event *group, int max_count,
        return n;
 }
 
-static void event_sched_in(struct perf_event *event)
-{
-       event->state = PERF_EVENT_STATE_ACTIVE;
-       event->oncpu = smp_processor_id();
-       event->tstamp_running += event->ctx->time - event->tstamp_stopped;
-       if (is_software_event(event))
-               event->pmu->enable(event);
-}
-
-/*
- * Called to enable a whole group of events.
- * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
- * Assumes the caller has disabled interrupts and has
- * frozen the PMU with hw_perf_save_disable.
- */
-int hw_perf_group_sched_in(struct perf_event *group_leader,
-              struct perf_cpu_context *cpuctx,
-              struct perf_event_context *ctx)
-{
-       struct cpu_hw_events *cpuhw;
-       long i, n, n0;
-       struct perf_event *sub;
-
-       if (!ppmu)
-               return 0;
-       cpuhw = &__get_cpu_var(cpu_hw_events);
-       n0 = cpuhw->n_events;
-       n = collect_events(group_leader, ppmu->n_counter - n0,
-                          &cpuhw->event[n0], &cpuhw->events[n0],
-                          &cpuhw->flags[n0]);
-       if (n < 0)
-               return -EAGAIN;
-       if (check_excludes(cpuhw->event, cpuhw->flags, n0, n))
-               return -EAGAIN;
-       i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0);
-       if (i < 0)
-               return -EAGAIN;
-       cpuhw->n_events = n0 + n;
-       cpuhw->n_added += n;
-
-       /*
-        * OK, this group can go on; update event states etc.,
-        * and enable any software events
-        */
-       for (i = n0; i < n0 + n; ++i)
-               cpuhw->event[i]->hw.config = cpuhw->events[i];
-       cpuctx->active_oncpu += n;
-       n = 1;
-       event_sched_in(group_leader);
-       list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
-               if (sub->state != PERF_EVENT_STATE_OFF) {
-                       event_sched_in(sub);
-                       ++n;
-               }
-       }
-       ctx->nr_active += n;
-
-       return 1;
-}
-
 /*
  * Add a event to the PMU.
  * If all events are not already frozen, then we disable and
@@ -805,12 +748,22 @@ static int power_pmu_enable(struct perf_event *event)
        cpuhw->event[n0] = event;
        cpuhw->events[n0] = event->hw.config;
        cpuhw->flags[n0] = event->hw.event_base;
+
+       /*
+        * If group events scheduling transaction was started,
+        * skip the schedulability test here, it will be peformed
+        * at commit time(->commit_txn) as a whole
+        */
+       if (cpuhw->group_flag & PERF_EVENT_TXN_STARTED)
+               goto nocheck;
+
        if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
                goto out;
        if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
                goto out;
-
        event->hw.config = cpuhw->events[n0];
+
+nocheck:
        ++cpuhw->n_events;
        ++cpuhw->n_added;
 
@@ -896,11 +849,65 @@ static void power_pmu_unthrottle(struct perf_event *event)
        local_irq_restore(flags);
 }
 
+/*
+ * Start group events scheduling transaction
+ * Set the flag to make pmu::enable() not perform the
+ * schedulability test, it will be performed at commit time
+ */
+void power_pmu_start_txn(const struct pmu *pmu)
+{
+       struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+       cpuhw->group_flag |= PERF_EVENT_TXN_STARTED;
+       cpuhw->n_txn_start = cpuhw->n_events;
+}
+
+/*
+ * Stop group events scheduling transaction
+ * Clear the flag and pmu::enable() will perform the
+ * schedulability test.
+ */
+void power_pmu_cancel_txn(const struct pmu *pmu)
+{
+       struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+       cpuhw->group_flag &= ~PERF_EVENT_TXN_STARTED;
+}
+
+/*
+ * Commit group events scheduling transaction
+ * Perform the group schedulability test as a whole
+ * Return 0 if success
+ */
+int power_pmu_commit_txn(const struct pmu *pmu)
+{
+       struct cpu_hw_events *cpuhw;
+       long i, n;
+
+       if (!ppmu)
+               return -EAGAIN;
+       cpuhw = &__get_cpu_var(cpu_hw_events);
+       n = cpuhw->n_events;
+       if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
+               return -EAGAIN;
+       i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
+       if (i < 0)
+               return -EAGAIN;
+
+       for (i = cpuhw->n_txn_start; i < n; ++i)
+               cpuhw->event[i]->hw.config = cpuhw->events[i];
+
+       return 0;
+}
+
 struct pmu power_pmu = {
        .enable         = power_pmu_enable,
        .disable        = power_pmu_disable,
        .read           = power_pmu_read,
        .unthrottle     = power_pmu_unthrottle,
+       .start_txn      = power_pmu_start_txn,
+       .cancel_txn     = power_pmu_cancel_txn,
+       .commit_txn     = power_pmu_commit_txn,
 };
 
 /*
index 1b16b9a3e49a57dbc0e444e230528763b1faa762..0441bbdadbd12b0b41cf94c89bc401da7a642a1f 100644 (file)
@@ -532,25 +532,60 @@ void __init iSeries_time_init_early(void)
 }
 #endif /* CONFIG_PPC_ISERIES */
 
-#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_PPC32)
-DEFINE_PER_CPU(u8, perf_event_pending);
+#ifdef CONFIG_PERF_EVENTS
 
-void set_perf_event_pending(void)
+/*
+ * 64-bit uses a byte in the PACA, 32-bit uses a per-cpu variable...
+ */
+#ifdef CONFIG_PPC64
+static inline unsigned long test_perf_event_pending(void)
 {
-       get_cpu_var(perf_event_pending) = 1;
-       set_dec(1);
-       put_cpu_var(perf_event_pending);
+       unsigned long x;
+
+       asm volatile("lbz %0,%1(13)"
+               : "=r" (x)
+               : "i" (offsetof(struct paca_struct, perf_event_pending)));
+       return x;
 }
 
+static inline void set_perf_event_pending_flag(void)
+{
+       asm volatile("stb %0,%1(13)" : :
+               "r" (1),
+               "i" (offsetof(struct paca_struct, perf_event_pending)));
+}
+
+static inline void clear_perf_event_pending(void)
+{
+       asm volatile("stb %0,%1(13)" : :
+               "r" (0),
+               "i" (offsetof(struct paca_struct, perf_event_pending)));
+}
+
+#else /* 32-bit */
+
+DEFINE_PER_CPU(u8, perf_event_pending);
+
+#define set_perf_event_pending_flag()  __get_cpu_var(perf_event_pending) = 1
 #define test_perf_event_pending()      __get_cpu_var(perf_event_pending)
 #define clear_perf_event_pending()     __get_cpu_var(perf_event_pending) = 0
 
-#else  /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
+#endif /* 32 vs 64 bit */
+
+void set_perf_event_pending(void)
+{
+       preempt_disable();
+       set_perf_event_pending_flag();
+       set_dec(1);
+       preempt_enable();
+}
+
+#else  /* CONFIG_PERF_EVENTS */
 
 #define test_perf_event_pending()      0
 #define clear_perf_event_pending()
 
-#endif /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
+#endif /* CONFIG_PERF_EVENTS */
 
 /*
  * For iSeries shared processors, we have to let the hypervisor
@@ -582,10 +617,6 @@ void timer_interrupt(struct pt_regs * regs)
        set_dec(DECREMENTER_MAX);
 
 #ifdef CONFIG_PPC32
-       if (test_perf_event_pending()) {
-               clear_perf_event_pending();
-               perf_event_do_pending();
-       }
        if (atomic_read(&ppc_n_lost_interrupts) != 0)
                do_IRQ(regs);
 #endif
@@ -604,6 +635,11 @@ void timer_interrupt(struct pt_regs * regs)
 
        calculate_steal_time();
 
+       if (test_perf_event_pending()) {
+               clear_perf_event_pending();
+               perf_event_do_pending();
+       }
+
 #ifdef CONFIG_PPC_ISERIES
        if (firmware_has_feature(FW_FEATURE_ISERIES))
                get_lppaca()->int_dword.fields.decr_int = 0;
index 2570fcc7665ddd9376f2db851371efef80fa2045..812312542e50cd9b42d73df0b02168d5a678ac7e 100644 (file)
@@ -440,7 +440,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
        unsigned int gtlb_index;
 
        gtlb_index = kvmppc_get_gpr(vcpu, ra);
-       if (gtlb_index > KVM44x_GUEST_TLB_SIZE) {
+       if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
                printk("%s: index %d\n", __func__, gtlb_index);
                kvmppc_dump_vcpu(vcpu);
                return EMULATE_FAIL;
index 1bbcc499d455c87096b84f89bab35a629a5ab388..b8f8dc126102e7a0734eeb037376919e2a34ca62 100644 (file)
@@ -82,7 +82,7 @@ startup_continue:
 _ehead:
 
 #ifdef CONFIG_SHARED_KERNEL
-       .org    0x100000
+       .org    0x100000 - 0x11000      # head.o ends at 0x11000
 #endif
 
 #
index 1f70970de0aa2b0fae5f0c428475e21e82d73100..cdef68717416cedce7b46d41599bde1f2be9821c 100644 (file)
@@ -80,7 +80,7 @@ startup_continue:
 _ehead:
 
 #ifdef CONFIG_SHARED_KERNEL
-       .org    0x100000
+       .org    0x100000 - 0x11000      # head.o ends at 0x11000
 #endif
 
 #
index 33fdc5a7976472831185126e419a637807e48b1d..9f654da4cecc82377fcd0abf7bd7acfe617eec08 100644 (file)
@@ -640,7 +640,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 
 asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
 {
-       long ret;
+       long ret = 0;
 
        /* Do the secure computing check first. */
        secure_computing(regs->gprs[2]);
@@ -649,7 +649,6 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
         * The sysc_tracesys code in entry.S stored the system
         * call number to gprs[2].
         */
-       ret = regs->gprs[2];
        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
            (tracehook_report_syscall_entry(regs) ||
             regs->gprs[2] >= NR_syscalls)) {
@@ -671,7 +670,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
                                    regs->gprs[2], regs->orig_gpr2,
                                    regs->gprs[3], regs->gprs[4],
                                    regs->gprs[5]);
-       return ret;
+       return ret ?: regs->gprs[2];
 }
 
 asmlinkage void do_syscall_trace_exit(struct pt_regs *regs)
index d906bf19c14a2a309d7aca26d0903a5503987559..a2163c95eb9845ffac908bf09b7af1bb5084cf3c 100644 (file)
@@ -391,7 +391,6 @@ static void __init time_init_wq(void)
        if (time_sync_wq)
                return;
        time_sync_wq = create_singlethread_workqueue("timesync");
-       stop_machine_create();
 }
 
 /*
index 8d90564c2bcfe7dee87dbb5e814e4ed6db054504..e6d8ab5cfa9d18b8bd5bf97cce9de7ed44bd1285 100644 (file)
@@ -44,6 +44,7 @@ config SUPERH32
        select HAVE_FUNCTION_GRAPH_TRACER
        select HAVE_ARCH_KGDB
        select HAVE_HW_BREAKPOINT
+       select HAVE_MIXED_BREAKPOINTS_REGS
        select PERF_EVENTS if HAVE_HW_BREAKPOINT
        select ARCH_HIBERNATION_POSSIBLE if MMU
 
index 275a448ae8c27bd38bb6cd19fbe7280d8b54198a..c7983124d99dfb6a31bfbf5233f48ba77a168119 100644 (file)
@@ -13,7 +13,7 @@
 
 #define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
 
-#define atomic_read(v)         ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)                ((v)->counter = (i))
 
 #if defined(CONFIG_GUSA_RB)
index 965dd780d51b9a1b061d3ad1b8d7bac13d7895ac..e14cad96798ffe10f43b16615792f8dd30225de2 100644 (file)
@@ -46,10 +46,14 @@ struct pmu;
 /* Maximum number of UBC channels */
 #define HBP_NUM                2
 
+static inline int hw_breakpoint_slots(int type)
+{
+       return HBP_NUM;
+}
+
 /* arch/sh/kernel/hw_breakpoint.c */
-extern int arch_check_va_in_userspace(unsigned long va, u16 hbp_len);
-extern int arch_validate_hwbkpt_settings(struct perf_event *bp,
-                                        struct task_struct *tsk);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
                                           unsigned long val, void *data);
 
index 675eea7785d9c8a91fa9db53950e37f30e756765..1f2cf6229862e47f9a311652cb6e5cf4c34585c4 100644 (file)
@@ -119,26 +119,17 @@ static int get_hbp_len(u16 hbp_len)
        return len_in_bytes;
 }
 
-/*
- * Check for virtual address in user space.
- */
-int arch_check_va_in_userspace(unsigned long va, u16 hbp_len)
-{
-       unsigned int len;
-
-       len = get_hbp_len(hbp_len);
-
-       return (va <= TASK_SIZE - len);
-}
-
 /*
  * Check for virtual address in kernel space.
  */
-static int arch_check_va_in_kernelspace(unsigned long va, u8 hbp_len)
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
 {
        unsigned int len;
+       unsigned long va;
+       struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 
-       len = get_hbp_len(hbp_len);
+       va = info->address;
+       len = get_hbp_len(info->len);
 
        return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
 }
@@ -226,8 +217,7 @@ static int arch_build_bp_info(struct perf_event *bp)
 /*
  * Validate the arch-specific HW Breakpoint register settings
  */
-int arch_validate_hwbkpt_settings(struct perf_event *bp,
-                                 struct task_struct *tsk)
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
 {
        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
        unsigned int align;
@@ -270,15 +260,6 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp,
        if (info->address & align)
                return -EINVAL;
 
-       /* Check that the virtual address is in the proper range */
-       if (tsk) {
-               if (!arch_check_va_in_userspace(info->address, info->len))
-                       return -EFAULT;
-       } else {
-               if (!arch_check_va_in_kernelspace(info->address, info->len))
-                       return -EFAULT;
-       }
-
        return 0;
 }
 
@@ -363,8 +344,7 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
                perf_bp_event(bp, args->regs);
 
                /* Deliver the signal to userspace */
-               if (arch_check_va_in_userspace(bp->attr.bp_addr,
-                                              bp->attr.bp_len)) {
+               if (!arch_check_bp_in_kernelspace(bp)) {
                        siginfo_t info;
 
                        info.si_signo = args->signr;
index 7759a9a93211279d8df3a3d4217b7d723146a195..d4104ce9fe53c8a01fc354c41e0d57c5359a1d68 100644 (file)
@@ -85,7 +85,7 @@ static int set_single_step(struct task_struct *tsk, unsigned long addr)
 
        bp = thread->ptrace_bps[0];
        if (!bp) {
-               hw_breakpoint_init(&attr);
+               ptrace_breakpoint_init(&attr);
 
                attr.bp_addr = addr;
                attr.bp_len = HW_BREAKPOINT_LEN_2;
index f0d343c3b956580265210d4fb6a059f2bde2ddd4..7ae128b19d3f6552a847acf4cc0c707f9766f9c7 100644 (file)
@@ -25,7 +25,7 @@ extern int atomic_cmpxchg(atomic_t *, int, int);
 extern int atomic_add_unless(atomic_t *, int, int);
 extern void atomic_set(atomic_t *, int);
 
-#define atomic_read(v)          ((v)->counter)
+#define atomic_read(v)          (*(volatile int *)&(v)->counter)
 
 #define atomic_add(i, v)       ((void)__atomic_add_return( (int)(i), (v)))
 #define atomic_sub(i, v)       ((void)__atomic_add_return(-(int)(i), (v)))
index f2e48009989e1e57f552066d8ae9890264590d5c..2050ca02c4230cff6c447ee3d84c5f3e058cb24b 100644 (file)
@@ -13,8 +13,8 @@
 #define ATOMIC_INIT(i)         { (i) }
 #define ATOMIC64_INIT(i)       { (i) }
 
-#define atomic_read(v)         ((v)->counter)
-#define atomic64_read(v)       ((v)->counter)
+#define atomic_read(v)         (*(volatile int *)&(v)->counter)
+#define atomic64_read(v)       (*(volatile long *)&(v)->counter)
 
 #define atomic_set(v, i)       (((v)->counter) = i)
 #define atomic64_set(v, i)     (((v)->counter) = i)
index 9458685902bddecc3f221012389085084bfb23ef..01177dcbe261e3e1639cd6abaf907f784c2f40ca 100644 (file)
@@ -53,11 +53,15 @@ config X86
        select HAVE_KERNEL_LZMA
        select HAVE_KERNEL_LZO
        select HAVE_HW_BREAKPOINT
+       select HAVE_MIXED_BREAKPOINTS_REGS
        select PERF_EVENTS
        select ANON_INODES
        select HAVE_ARCH_KMEMCHECK
        select HAVE_USER_RETURN_NOTIFIER
 
+config INSTRUCTION_DECODER
+       def_bool (KPROBES || PERF_EVENTS)
+
 config OUTPUT_FORMAT
        string
        default "elf32-i386" if X86_32
index a19829374e6a006b80a5db969a19c4f7dbae3449..918fbb1855cc027bb2fb7b6a77daeb2a21fda9cd 100644 (file)
@@ -502,23 +502,3 @@ config CPU_SUP_UMC_32
          CPU might render the kernel unbootable.
 
          If unsure, say N.
-
-config X86_DS
-       def_bool X86_PTRACE_BTS
-       depends on X86_DEBUGCTLMSR
-       select HAVE_HW_BRANCH_TRACER
-
-config X86_PTRACE_BTS
-       bool "Branch Trace Store"
-       default y
-       depends on X86_DEBUGCTLMSR
-       depends on BROKEN
-       ---help---
-         This adds a ptrace interface to the hardware's branch trace store.
-
-         Debuggers may use it to collect an execution trace of the debugged
-         application in order to answer the question 'how did I get here?'.
-         Debuggers may trace user mode as well as kernel mode.
-
-         Say Y unless there is no application development on this machine
-         and you want to save a small amount of code size.
index bc01e3ebfeb29bfbfe6d60b42276bc6565cf2e66..bd58c8abbfbddf3f5ceacc4267635e7f2e6c77c9 100644 (file)
@@ -174,15 +174,6 @@ config IOMMU_LEAK
          Add a simple leak tracer to the IOMMU code. This is useful when you
          are debugging a buggy device driver that leaks IOMMU mappings.
 
-config X86_DS_SELFTEST
-    bool "DS selftest"
-    default y
-    depends on DEBUG_KERNEL
-    depends on X86_DS
-       ---help---
-         Perform Debug Store selftests at boot time.
-         If in doubt, say "N".
-
 config HAVE_MMIOTRACE_SUPPORT
        def_bool y
 
index 86a0ff0aeac7eadd306a6e5812844f992a0d7010..7014e88bc7798af33f681724ff90cf09eda52af5 100644 (file)
                                (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 #define PM_ALIGNED(lvl, addr)  ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 
+/*
+ * Returns the page table level to use for a given page size
+ * Pagesize is expected to be a power-of-two
+ */
+#define PAGE_SIZE_LEVEL(pagesize) \
+               ((__ffs(pagesize) - 12) / 9)
+/*
+ * Returns the number of ptes to use for a given page size
+ * Pagesize is expected to be a power-of-two
+ */
+#define PAGE_SIZE_PTE_COUNT(pagesize) \
+               (1ULL << ((__ffs(pagesize) - 12) % 9))
+
+/*
+ * Aligns a given io-virtual address to a given page size
+ * Pagesize is expected to be a power-of-two
+ */
+#define PAGE_SIZE_ALIGN(address, pagesize) \
+               ((address) & ~((pagesize) - 1))
+/*
+ * Creates an IOMMU PTE for an address an a given pagesize
+ * The PTE has no permission bits set
+ * Pagesize is expected to be a power-of-two larger than 4096
+ */
+#define PAGE_SIZE_PTE(address, pagesize)               \
+               (((address) | ((pagesize) - 1)) &       \
+                (~(pagesize >> 1)) & PM_ADDR_MASK)
+
+/*
+ * Takes a PTE value with mode=0x07 and returns the page size it maps
+ */
+#define PTE_PAGE_SIZE(pte) \
+       (1ULL << (1 + ffz(((pte) | 0xfffULL))))
+
 #define IOMMU_PTE_P  (1ULL << 0)
 #define IOMMU_PTE_TV (1ULL << 1)
 #define IOMMU_PTE_U  (1ULL << 59)
index b4ac2cdcb64fd603643fa8409a753b4c5859d918..1fa03e04ae4475e9bdc342aa117d9048a4e93105 100644 (file)
@@ -373,6 +373,7 @@ extern atomic_t init_deasserted;
 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 #endif
 
+#ifdef CONFIG_X86_LOCAL_APIC
 static inline u32 apic_read(u32 reg)
 {
        return apic->read(reg);
@@ -403,10 +404,19 @@ static inline u32 safe_apic_wait_icr_idle(void)
        return apic->safe_wait_icr_idle();
 }
 
+#else /* CONFIG_X86_LOCAL_APIC */
+
+static inline u32 apic_read(u32 reg) { return 0; }
+static inline void apic_write(u32 reg, u32 val) { }
+static inline u64 apic_icr_read(void) { return 0; }
+static inline void apic_icr_write(u32 low, u32 high) { }
+static inline void apic_wait_icr_idle(void) { }
+static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
+
+#endif /* CONFIG_X86_LOCAL_APIC */
 
 static inline void ack_APIC_irq(void)
 {
-#ifdef CONFIG_X86_LOCAL_APIC
        /*
         * ack_APIC_irq() actually gets compiled as a single instruction
         * ... yummie.
@@ -414,7 +424,6 @@ static inline void ack_APIC_irq(void)
 
        /* Docs say use 0 for future compatibility */
        apic_write(APIC_EOI, 0);
-#endif
 }
 
 static inline unsigned default_get_apic_id(unsigned long x)
index 8f8217b9bdac67a7312959cad211232f60fbb8ce..37b39d27abe01ad24aa2b2abfd60467ab0d063ce 100644 (file)
@@ -22,7 +22,7 @@
  */
 static inline int atomic_read(const atomic_t *v)
 {
-       return v->counter;
+       return (*(volatile int *)&(v)->counter);
 }
 
 /**
index 51c5b405692952bf9ed7e342ee724bfc202f4017..b014e235ea8dfc31f63520fcab82805dbdc8daa8 100644 (file)
@@ -18,7 +18,7 @@
  */
 static inline long atomic64_read(const atomic64_t *v)
 {
-       return v->counter;
+       return (*(volatile long *)&(v)->counter);
 }
 
 /**
diff --git a/arch/x86/include/asm/ds.h b/arch/x86/include/asm/ds.h
deleted file mode 100644 (file)
index 70dac19..0000000
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Debug Store (DS) support
- *
- * This provides a low-level interface to the hardware's Debug Store
- * feature that is used for branch trace store (BTS) and
- * precise-event based sampling (PEBS).
- *
- * It manages:
- * - DS and BTS hardware configuration
- * - buffer overflow handling (to be done)
- * - buffer access
- *
- * It does not do:
- * - security checking (is the caller allowed to trace the task)
- * - buffer allocation (memory accounting)
- *
- *
- * Copyright (C) 2007-2009 Intel Corporation.
- * Markus Metzger <markus.t.metzger@intel.com>, 2007-2009
- */
-
-#ifndef _ASM_X86_DS_H
-#define _ASM_X86_DS_H
-
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/err.h>
-
-
-#ifdef CONFIG_X86_DS
-
-struct task_struct;
-struct ds_context;
-struct ds_tracer;
-struct bts_tracer;
-struct pebs_tracer;
-
-typedef void (*bts_ovfl_callback_t)(struct bts_tracer *);
-typedef void (*pebs_ovfl_callback_t)(struct pebs_tracer *);
-
-
-/*
- * A list of features plus corresponding macros to talk about them in
- * the ds_request function's flags parameter.
- *
- * We use the enum to index an array of corresponding control bits;
- * we use the macro to index a flags bit-vector.
- */
-enum ds_feature {
-       dsf_bts = 0,
-       dsf_bts_kernel,
-#define BTS_KERNEL (1 << dsf_bts_kernel)
-       /* trace kernel-mode branches */
-
-       dsf_bts_user,
-#define BTS_USER (1 << dsf_bts_user)
-       /* trace user-mode branches */
-
-       dsf_bts_overflow,
-       dsf_bts_max,
-       dsf_pebs = dsf_bts_max,
-
-       dsf_pebs_max,
-       dsf_ctl_max = dsf_pebs_max,
-       dsf_bts_timestamps = dsf_ctl_max,
-#define BTS_TIMESTAMPS (1 << dsf_bts_timestamps)
-       /* add timestamps into BTS trace */
-
-#define BTS_USER_FLAGS (BTS_KERNEL | BTS_USER | BTS_TIMESTAMPS)
-};
-
-
-/*
- * Request BTS or PEBS
- *
- * Due to alignement constraints, the actual buffer may be slightly
- * smaller than the requested or provided buffer.
- *
- * Returns a pointer to a tracer structure on success, or
- * ERR_PTR(errcode) on failure.
- *
- * The interrupt threshold is independent from the overflow callback
- * to allow users to use their own overflow interrupt handling mechanism.
- *
- * The function might sleep.
- *
- * task: the task to request recording for
- * cpu:  the cpu to request recording for
- * base: the base pointer for the (non-pageable) buffer;
- * size: the size of the provided buffer in bytes
- * ovfl: pointer to a function to be called on buffer overflow;
- *       NULL if cyclic buffer requested
- * th: the interrupt threshold in records from the end of the buffer;
- *     -1 if no interrupt threshold is requested.
- * flags: a bit-mask of the above flags
- */
-extern struct bts_tracer *ds_request_bts_task(struct task_struct *task,
-                                             void *base, size_t size,
-                                             bts_ovfl_callback_t ovfl,
-                                             size_t th, unsigned int flags);
-extern struct bts_tracer *ds_request_bts_cpu(int cpu, void *base, size_t size,
-                                            bts_ovfl_callback_t ovfl,
-                                            size_t th, unsigned int flags);
-extern struct pebs_tracer *ds_request_pebs_task(struct task_struct *task,
-                                               void *base, size_t size,
-                                               pebs_ovfl_callback_t ovfl,
-                                               size_t th, unsigned int flags);
-extern struct pebs_tracer *ds_request_pebs_cpu(int cpu,
-                                              void *base, size_t size,
-                                              pebs_ovfl_callback_t ovfl,
-                                              size_t th, unsigned int flags);
-
-/*
- * Release BTS or PEBS resources
- * Suspend and resume BTS or PEBS tracing
- *
- * Must be called with irq's enabled.
- *
- * tracer: the tracer handle returned from ds_request_~()
- */
-extern void ds_release_bts(struct bts_tracer *tracer);
-extern void ds_suspend_bts(struct bts_tracer *tracer);
-extern void ds_resume_bts(struct bts_tracer *tracer);
-extern void ds_release_pebs(struct pebs_tracer *tracer);
-extern void ds_suspend_pebs(struct pebs_tracer *tracer);
-extern void ds_resume_pebs(struct pebs_tracer *tracer);
-
-/*
- * Release BTS or PEBS resources
- * Suspend and resume BTS or PEBS tracing
- *
- * Cpu tracers must call this on the traced cpu.
- * Task tracers must call ds_release_~_noirq() for themselves.
- *
- * May be called with irq's disabled.
- *
- * Returns 0 if successful;
- * -EPERM if the cpu tracer does not trace the current cpu.
- * -EPERM if the task tracer does not trace itself.
- *
- * tracer: the tracer handle returned from ds_request_~()
- */
-extern int ds_release_bts_noirq(struct bts_tracer *tracer);
-extern int ds_suspend_bts_noirq(struct bts_tracer *tracer);
-extern int ds_resume_bts_noirq(struct bts_tracer *tracer);
-extern int ds_release_pebs_noirq(struct pebs_tracer *tracer);
-extern int ds_suspend_pebs_noirq(struct pebs_tracer *tracer);
-extern int ds_resume_pebs_noirq(struct pebs_tracer *tracer);
-
-
-/*
- * The raw DS buffer state as it is used for BTS and PEBS recording.
- *
- * This is the low-level, arch-dependent interface for working
- * directly on the raw trace data.
- */
-struct ds_trace {
-       /* the number of bts/pebs records */
-       size_t n;
-       /* the size of a bts/pebs record in bytes */
-       size_t size;
-       /* pointers into the raw buffer:
-          - to the first entry */
-       void *begin;
-       /* - one beyond the last entry */
-       void *end;
-       /* - one beyond the newest entry */
-       void *top;
-       /* - the interrupt threshold */
-       void *ith;
-       /* flags given on ds_request() */
-       unsigned int flags;
-};
-
-/*
- * An arch-independent view on branch trace data.
- */
-enum bts_qualifier {
-       bts_invalid,
-#define BTS_INVALID bts_invalid
-
-       bts_branch,
-#define BTS_BRANCH bts_branch
-
-       bts_task_arrives,
-#define BTS_TASK_ARRIVES bts_task_arrives
-
-       bts_task_departs,
-#define BTS_TASK_DEPARTS bts_task_departs
-
-       bts_qual_bit_size = 4,
-       bts_qual_max = (1 << bts_qual_bit_size),
-};
-
-struct bts_struct {
-       __u64 qualifier;
-       union {
-               /* BTS_BRANCH */
-               struct {
-                       __u64 from;
-                       __u64 to;
-               } lbr;
-               /* BTS_TASK_ARRIVES or BTS_TASK_DEPARTS */
-               struct {
-                       __u64 clock;
-                       pid_t pid;
-               } event;
-       } variant;
-};
-
-
-/*
- * The BTS state.
- *
- * This gives access to the raw DS state and adds functions to provide
- * an arch-independent view of the BTS data.
- */
-struct bts_trace {
-       struct ds_trace ds;
-
-       int (*read)(struct bts_tracer *tracer, const void *at,
-                   struct bts_struct *out);
-       int (*write)(struct bts_tracer *tracer, const struct bts_struct *in);
-};
-
-
-/*
- * The PEBS state.
- *
- * This gives access to the raw DS state and the PEBS-specific counter
- * reset value.
- */
-struct pebs_trace {
-       struct ds_trace ds;
-
-       /* the number of valid counters in the below array */
-       unsigned int counters;
-
-#define MAX_PEBS_COUNTERS 4
-       /* the counter reset value */
-       unsigned long long counter_reset[MAX_PEBS_COUNTERS];
-};
-
-
-/*
- * Read the BTS or PEBS trace.
- *
- * Returns a view on the trace collected for the parameter tracer.
- *
- * The view remains valid as long as the traced task is not running or
- * the tracer is suspended.
- * Writes into the trace buffer are not reflected.
- *
- * tracer: the tracer handle returned from ds_request_~()
- */
-extern const struct bts_trace *ds_read_bts(struct bts_tracer *tracer);
-extern const struct pebs_trace *ds_read_pebs(struct pebs_tracer *tracer);
-
-
-/*
- * Reset the write pointer of the BTS/PEBS buffer.
- *
- * Returns 0 on success; -Eerrno on error
- *
- * tracer: the tracer handle returned from ds_request_~()
- */
-extern int ds_reset_bts(struct bts_tracer *tracer);
-extern int ds_reset_pebs(struct pebs_tracer *tracer);
-
-/*
- * Set the PEBS counter reset value.
- *
- * Returns 0 on success; -Eerrno on error
- *
- * tracer: the tracer handle returned from ds_request_pebs()
- * counter: the index of the counter
- * value: the new counter reset value
- */
-extern int ds_set_pebs_reset(struct pebs_tracer *tracer,
-                            unsigned int counter, u64 value);
-
-/*
- * Initialization
- */
-struct cpuinfo_x86;
-extern void __cpuinit ds_init_intel(struct cpuinfo_x86 *);
-
-/*
- * Context switch work
- */
-extern void ds_switch_to(struct task_struct *prev, struct task_struct *next);
-
-#else /* CONFIG_X86_DS */
-
-struct cpuinfo_x86;
-static inline void __cpuinit ds_init_intel(struct cpuinfo_x86 *ignored) {}
-static inline void ds_switch_to(struct task_struct *prev,
-                               struct task_struct *next) {}
-
-#endif /* CONFIG_X86_DS */
-#endif /* _ASM_X86_DS_H */
index 2a1bd8f4f23ad34bafa49c829e18172d17569d50..942255310e6a16391b3e0a5bcbcd59ccafece3d6 100644 (file)
@@ -41,12 +41,16 @@ struct arch_hw_breakpoint {
 /* Total number of available HW breakpoint registers */
 #define HBP_NUM 4
 
+static inline int hw_breakpoint_slots(int type)
+{
+       return HBP_NUM;
+}
+
 struct perf_event;
 struct pmu;
 
-extern int arch_check_va_in_userspace(unsigned long va, u8 hbp_len);
-extern int arch_validate_hwbkpt_settings(struct perf_event *bp,
-                                        struct task_struct *tsk);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
                                           unsigned long val, void *data);
 
index 1edbf89680fd57e577e6ccae74e5ef110d285414..fc1f579fb965157cec8ce23376a59ff5a23280e9 100644 (file)
@@ -6,7 +6,7 @@
 #define PIT_CH0                        0x40
 #define PIT_CH2                        0x42
 
-extern spinlock_t i8253_lock;
+extern raw_spinlock_t i8253_lock;
 
 extern struct clock_event_device *global_clock_event;
 
index 96c2e0ad04ca04f94d2a7974007dd647a4142549..88c765e16410beecf7be2bfdad19b0cf4918ec46 100644 (file)
@@ -68,6 +68,8 @@ struct insn {
        const insn_byte_t *next_byte;
 };
 
+#define MAX_INSN_SIZE  16
+
 #define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
 #define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
 #define X86_MODRM_RM(modrm) ((modrm) & 0x07)
index f70e60071fe80039e4d439cca6667f65729bcbd5..af00bd1d208934941f00ba7e911c20dd868a3f2b 100644 (file)
@@ -16,11 +16,16 @@ extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
 extern int k8_scan_nodes(void);
 
 #ifdef CONFIG_K8_NB
+extern int num_k8_northbridges;
+
 static inline struct pci_dev *node_to_k8_nb_misc(int node)
 {
        return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
 }
+
 #else
+#define num_k8_northbridges 0
+
 static inline struct pci_dev *node_to_k8_nb_misc(int node)
 {
        return NULL;
index 4ffa345a8ccbd7d2b7db8debd7caa090aceaf8a5..54788253915739a2a07faa87f8186ab261e0a065 100644 (file)
@@ -24,6 +24,7 @@
 #include <linux/types.h>
 #include <linux/ptrace.h>
 #include <linux/percpu.h>
+#include <asm/insn.h>
 
 #define  __ARCH_WANT_KPROBES_INSN_SLOT
 
@@ -36,7 +37,6 @@ typedef u8 kprobe_opcode_t;
 #define RELATIVEJUMP_SIZE 5
 #define RELATIVECALL_OPCODE 0xe8
 #define RELATIVE_ADDR_SIZE 4
-#define MAX_INSN_SIZE 16
 #define MAX_STACK_SIZE 64
 #define MIN_STACK_SIZE(ADDR)                                          \
        (((MAX_STACK_SIZE) < (((unsigned long)current_thread_info()) + \
index 4604e6a54d36eb2fe13fdc88b432d6c018252087..bc473acfa7f97ea52e9800a4afc038d543e84ce2 100644 (file)
 #define MSR_IA32_LASTINTTOIP           0x000001de
 
 /* DEBUGCTLMSR bits (others vary by model): */
-#define _DEBUGCTLMSR_LBR       0 /* last branch recording */
-#define _DEBUGCTLMSR_BTF       1 /* single-step on branches */
-
-#define DEBUGCTLMSR_LBR                (1UL << _DEBUGCTLMSR_LBR)
-#define DEBUGCTLMSR_BTF                (1UL << _DEBUGCTLMSR_BTF)
+#define DEBUGCTLMSR_LBR                        (1UL <<  0) /* last branch recording */
+#define DEBUGCTLMSR_BTF                        (1UL <<  1) /* single-step on branches */
+#define DEBUGCTLMSR_TR                 (1UL <<  6)
+#define DEBUGCTLMSR_BTS                        (1UL <<  7)
+#define DEBUGCTLMSR_BTINT              (1UL <<  8)
+#define DEBUGCTLMSR_BTS_OFF_OS         (1UL <<  9)
+#define DEBUGCTLMSR_BTS_OFF_USR                (1UL << 10)
+#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
 
 #define MSR_IA32_MC0_CTL               0x00000400
 #define MSR_IA32_MC0_STATUS            0x00000401
 #define MSR_P4_U2L_ESCR0               0x000003b0
 #define MSR_P4_U2L_ESCR1               0x000003b1
 
+#define MSR_P4_PEBS_MATRIX_VERT                0x000003f2
+
 /* Intel Core-based CPU performance counters */
 #define MSR_CORE_PERF_FIXED_CTR0       0x00000309
 #define MSR_CORE_PERF_FIXED_CTR1       0x0000030a
index db6109a885a76a6ecd116c59baae0088007ffc45..254883d0c7e088424ed983154613b4ad889435e1 100644 (file)
@@ -5,7 +5,7 @@
  * Performance event hw details:
  */
 
-#define X86_PMC_MAX_GENERIC                                    8
+#define X86_PMC_MAX_GENERIC                                   32
 #define X86_PMC_MAX_FIXED                                      3
 
 #define X86_PMC_IDX_GENERIC                                    0
 #define MSR_ARCH_PERFMON_EVENTSEL0                          0x186
 #define MSR_ARCH_PERFMON_EVENTSEL1                          0x187
 
-#define ARCH_PERFMON_EVENTSEL_ENABLE                     (1 << 22)
-#define ARCH_PERFMON_EVENTSEL_ANY                        (1 << 21)
-#define ARCH_PERFMON_EVENTSEL_INT                        (1 << 20)
-#define ARCH_PERFMON_EVENTSEL_OS                         (1 << 17)
-#define ARCH_PERFMON_EVENTSEL_USR                        (1 << 16)
-
-/*
- * Includes eventsel and unit mask as well:
- */
-
-
-#define INTEL_ARCH_EVTSEL_MASK         0x000000FFULL
-#define INTEL_ARCH_UNIT_MASK           0x0000FF00ULL
-#define INTEL_ARCH_EDGE_MASK           0x00040000ULL
-#define INTEL_ARCH_INV_MASK            0x00800000ULL
-#define INTEL_ARCH_CNT_MASK            0xFF000000ULL
-#define INTEL_ARCH_EVENT_MASK  (INTEL_ARCH_UNIT_MASK|INTEL_ARCH_EVTSEL_MASK)
-
-/*
- * filter mask to validate fixed counter events.
- * the following filters disqualify for fixed counters:
- *  - inv
- *  - edge
- *  - cnt-mask
- *  The other filters are supported by fixed counters.
- *  The any-thread option is supported starting with v3.
- */
-#define INTEL_ARCH_FIXED_MASK \
-       (INTEL_ARCH_CNT_MASK| \
-        INTEL_ARCH_INV_MASK| \
-        INTEL_ARCH_EDGE_MASK|\
-        INTEL_ARCH_UNIT_MASK|\
-        INTEL_ARCH_EVENT_MASK)
+#define ARCH_PERFMON_EVENTSEL_EVENT                    0x000000FFULL
+#define ARCH_PERFMON_EVENTSEL_UMASK                    0x0000FF00ULL
+#define ARCH_PERFMON_EVENTSEL_USR                      (1ULL << 16)
+#define ARCH_PERFMON_EVENTSEL_OS                       (1ULL << 17)
+#define ARCH_PERFMON_EVENTSEL_EDGE                     (1ULL << 18)
+#define ARCH_PERFMON_EVENTSEL_INT                      (1ULL << 20)
+#define ARCH_PERFMON_EVENTSEL_ANY                      (1ULL << 21)
+#define ARCH_PERFMON_EVENTSEL_ENABLE                   (1ULL << 22)
+#define ARCH_PERFMON_EVENTSEL_INV                      (1ULL << 23)
+#define ARCH_PERFMON_EVENTSEL_CMASK                    0xFF000000ULL
+
+#define AMD64_EVENTSEL_EVENT   \
+       (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
+#define INTEL_ARCH_EVENT_MASK  \
+       (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
+
+#define X86_RAW_EVENT_MASK             \
+       (ARCH_PERFMON_EVENTSEL_EVENT |  \
+        ARCH_PERFMON_EVENTSEL_UMASK |  \
+        ARCH_PERFMON_EVENTSEL_EDGE  |  \
+        ARCH_PERFMON_EVENTSEL_INV   |  \
+        ARCH_PERFMON_EVENTSEL_CMASK)
+#define AMD64_RAW_EVENT_MASK           \
+       (X86_RAW_EVENT_MASK          |  \
+        AMD64_EVENTSEL_EVENT)
 
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK                (0x00 << 8)
@@ -67,7 +59,7 @@
 union cpuid10_eax {
        struct {
                unsigned int version_id:8;
-               unsigned int num_events:8;
+               unsigned int num_counters:8;
                unsigned int bit_width:8;
                unsigned int mask_length:8;
        } split;
@@ -76,7 +68,7 @@ union cpuid10_eax {
 
 union cpuid10_edx {
        struct {
-               unsigned int num_events_fixed:4;
+               unsigned int num_counters_fixed:4;
                unsigned int reserved:28;
        } split;
        unsigned int full;
@@ -136,6 +128,18 @@ extern void perf_events_lapic_init(void);
 
 #define PERF_EVENT_INDEX_OFFSET                        0
 
+/*
+ * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
+ * This flag is otherwise unused and ABI specified to be 0, so nobody should
+ * care what we do with it.
+ */
+#define PERF_EFLAGS_EXACT      (1UL << 3)
+
+struct pt_regs;
+extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+extern unsigned long perf_misc_flags(struct pt_regs *regs);
+#define perf_misc_flags(regs)  perf_misc_flags(regs)
+
 #else
 static inline void init_hw_perf_events(void)           { }
 static inline void perf_events_lapic_init(void)        { }
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
new file mode 100644 (file)
index 0000000..b05400a
--- /dev/null
@@ -0,0 +1,794 @@
+/*
+ * Netburst Perfomance Events (P4, old Xeon)
+ */
+
+#ifndef PERF_EVENT_P4_H
+#define PERF_EVENT_P4_H
+
+#include <linux/cpu.h>
+#include <linux/bitops.h>
+
+/*
+ * NetBurst has perfomance MSRs shared between
+ * threads if HT is turned on, ie for both logical
+ * processors (mem: in turn in Atom with HT support
+ * perf-MSRs are not shared and every thread has its
+ * own perf-MSRs set)
+ */
+#define ARCH_P4_TOTAL_ESCR     (46)
+#define ARCH_P4_RESERVED_ESCR  (2) /* IQ_ESCR(0,1) not always present */
+#define ARCH_P4_MAX_ESCR       (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
+#define ARCH_P4_MAX_CCCR       (18)
+#define ARCH_P4_MAX_COUNTER    (ARCH_P4_MAX_CCCR / 2)
+
+#define P4_ESCR_EVENT_MASK     0x7e000000U
+#define P4_ESCR_EVENT_SHIFT    25
+#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U
+#define P4_ESCR_EVENTMASK_SHIFT        9
+#define P4_ESCR_TAG_MASK       0x000001e0U
+#define P4_ESCR_TAG_SHIFT      5
+#define P4_ESCR_TAG_ENABLE     0x00000010U
+#define P4_ESCR_T0_OS          0x00000008U
+#define P4_ESCR_T0_USR         0x00000004U
+#define P4_ESCR_T1_OS          0x00000002U
+#define P4_ESCR_T1_USR         0x00000001U
+
+#define P4_ESCR_EVENT(v)       ((v) << P4_ESCR_EVENT_SHIFT)
+#define P4_ESCR_EMASK(v)       ((v) << P4_ESCR_EVENTMASK_SHIFT)
+#define P4_ESCR_TAG(v)         ((v) << P4_ESCR_TAG_SHIFT)
+
+/* Non HT mask */
+#define P4_ESCR_MASK                   \
+       (P4_ESCR_EVENT_MASK     |       \
+       P4_ESCR_EVENTMASK_MASK  |       \
+       P4_ESCR_TAG_MASK        |       \
+       P4_ESCR_TAG_ENABLE      |       \
+       P4_ESCR_T0_OS           |       \
+       P4_ESCR_T0_USR)
+
+/* HT mask */
+#define P4_ESCR_MASK_HT                        \
+       (P4_ESCR_MASK | P4_ESCR_T1_OS | P4_ESCR_T1_USR)
+
+#define P4_CCCR_OVF                    0x80000000U
+#define P4_CCCR_CASCADE                        0x40000000U
+#define P4_CCCR_OVF_PMI_T0             0x04000000U
+#define P4_CCCR_OVF_PMI_T1             0x08000000U
+#define P4_CCCR_FORCE_OVF              0x02000000U
+#define P4_CCCR_EDGE                   0x01000000U
+#define P4_CCCR_THRESHOLD_MASK         0x00f00000U
+#define P4_CCCR_THRESHOLD_SHIFT                20
+#define P4_CCCR_COMPLEMENT             0x00080000U
+#define P4_CCCR_COMPARE                        0x00040000U
+#define P4_CCCR_ESCR_SELECT_MASK       0x0000e000U
+#define P4_CCCR_ESCR_SELECT_SHIFT      13
+#define P4_CCCR_ENABLE                 0x00001000U
+#define P4_CCCR_THREAD_SINGLE          0x00010000U
+#define P4_CCCR_THREAD_BOTH            0x00020000U
+#define P4_CCCR_THREAD_ANY             0x00030000U
+#define P4_CCCR_RESERVED               0x00000fffU
+
+#define P4_CCCR_THRESHOLD(v)           ((v) << P4_CCCR_THRESHOLD_SHIFT)
+#define P4_CCCR_ESEL(v)                        ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
+
+/* Custom bits in reerved CCCR area */
+#define P4_CCCR_CACHE_OPS_MASK         0x0000003fU
+
+
+/* Non HT mask */
+#define P4_CCCR_MASK                           \
+       (P4_CCCR_OVF                    |       \
+       P4_CCCR_CASCADE                 |       \
+       P4_CCCR_OVF_PMI_T0              |       \
+       P4_CCCR_FORCE_OVF               |       \
+       P4_CCCR_EDGE                    |       \
+       P4_CCCR_THRESHOLD_MASK          |       \
+       P4_CCCR_COMPLEMENT              |       \
+       P4_CCCR_COMPARE                 |       \
+       P4_CCCR_ESCR_SELECT_MASK        |       \
+       P4_CCCR_ENABLE)
+
+/* HT mask */
+#define P4_CCCR_MASK_HT        (P4_CCCR_MASK | P4_CCCR_THREAD_ANY)
+
+#define P4_GEN_ESCR_EMASK(class, name, bit)    \
+       class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
+#define P4_ESCR_EMASK_BIT(class, name)         class##__##name
+
+/*
+ * config field is 64bit width and consists of
+ * HT << 63 | ESCR << 32 | CCCR
+ * where HT is HyperThreading bit (since ESCR
+ * has it reserved we may use it for own purpose)
+ *
+ * note that this is NOT the addresses of respective
+ * ESCR and CCCR but rather an only packed value should
+ * be unpacked and written to a proper addresses
+ *
+ * the base idea is to pack as much info as
+ * possible
+ */
+#define p4_config_pack_escr(v)         (((u64)(v)) << 32)
+#define p4_config_pack_cccr(v)         (((u64)(v)) & 0xffffffffULL)
+#define p4_config_unpack_escr(v)       (((u64)(v)) >> 32)
+#define p4_config_unpack_cccr(v)       (((u64)(v)) & 0xffffffffULL)
+
+#define p4_config_unpack_emask(v)                      \
+       ({                                              \
+               u32 t = p4_config_unpack_escr((v));     \
+               t = t &  P4_ESCR_EVENTMASK_MASK;        \
+               t = t >> P4_ESCR_EVENTMASK_SHIFT;       \
+               t;                                      \
+       })
+
+#define p4_config_unpack_event(v)                      \
+       ({                                              \
+               u32 t = p4_config_unpack_escr((v));     \
+               t = t &  P4_ESCR_EVENT_MASK;            \
+               t = t >> P4_ESCR_EVENT_SHIFT;           \
+               t;                                      \
+       })
+
+#define p4_config_unpack_cache_event(v)        (((u64)(v)) & P4_CCCR_CACHE_OPS_MASK)
+
+#define P4_CONFIG_HT_SHIFT             63
+#define P4_CONFIG_HT                   (1ULL << P4_CONFIG_HT_SHIFT)
+
+static inline bool p4_is_event_cascaded(u64 config)
+{
+       u32 cccr = p4_config_unpack_cccr(config);
+       return !!(cccr & P4_CCCR_CASCADE);
+}
+
+static inline int p4_ht_config_thread(u64 config)
+{
+       return !!(config & P4_CONFIG_HT);
+}
+
+static inline u64 p4_set_ht_bit(u64 config)
+{
+       return config | P4_CONFIG_HT;
+}
+
+static inline u64 p4_clear_ht_bit(u64 config)
+{
+       return config & ~P4_CONFIG_HT;
+}
+
+static inline int p4_ht_active(void)
+{
+#ifdef CONFIG_SMP
+       return smp_num_siblings > 1;
+#endif
+       return 0;
+}
+
+static inline int p4_ht_thread(int cpu)
+{
+#ifdef CONFIG_SMP
+       if (smp_num_siblings == 2)
+               return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map));
+#endif
+       return 0;
+}
+
+static inline int p4_should_swap_ts(u64 config, int cpu)
+{
+       return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
+}
+
+static inline u32 p4_default_cccr_conf(int cpu)
+{
+       /*
+        * Note that P4_CCCR_THREAD_ANY is "required" on
+        * non-HT machines (on HT machines we count TS events
+        * regardless the state of second logical processor
+        */
+       u32 cccr = P4_CCCR_THREAD_ANY;
+
+       if (!p4_ht_thread(cpu))
+               cccr |= P4_CCCR_OVF_PMI_T0;
+       else
+               cccr |= P4_CCCR_OVF_PMI_T1;
+
+       return cccr;
+}
+
+static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
+{
+       u32 escr = 0;
+
+       if (!p4_ht_thread(cpu)) {
+               if (!exclude_os)
+                       escr |= P4_ESCR_T0_OS;
+               if (!exclude_usr)
+                       escr |= P4_ESCR_T0_USR;
+       } else {
+               if (!exclude_os)
+                       escr |= P4_ESCR_T1_OS;
+               if (!exclude_usr)
+                       escr |= P4_ESCR_T1_USR;
+       }
+
+       return escr;
+}
+
+enum P4_EVENTS {
+       P4_EVENT_TC_DELIVER_MODE,
+       P4_EVENT_BPU_FETCH_REQUEST,
+       P4_EVENT_ITLB_REFERENCE,
+       P4_EVENT_MEMORY_CANCEL,
+       P4_EVENT_MEMORY_COMPLETE,
+       P4_EVENT_LOAD_PORT_REPLAY,
+       P4_EVENT_STORE_PORT_REPLAY,
+       P4_EVENT_MOB_LOAD_REPLAY,
+       P4_EVENT_PAGE_WALK_TYPE,
+       P4_EVENT_BSQ_CACHE_REFERENCE,
+       P4_EVENT_IOQ_ALLOCATION,
+       P4_EVENT_IOQ_ACTIVE_ENTRIES,
+       P4_EVENT_FSB_DATA_ACTIVITY,
+       P4_EVENT_BSQ_ALLOCATION,
+       P4_EVENT_BSQ_ACTIVE_ENTRIES,
+       P4_EVENT_SSE_INPUT_ASSIST,
+       P4_EVENT_PACKED_SP_UOP,
+       P4_EVENT_PACKED_DP_UOP,
+       P4_EVENT_SCALAR_SP_UOP,
+       P4_EVENT_SCALAR_DP_UOP,
+       P4_EVENT_64BIT_MMX_UOP,
+       P4_EVENT_128BIT_MMX_UOP,
+       P4_EVENT_X87_FP_UOP,
+       P4_EVENT_TC_MISC,
+       P4_EVENT_GLOBAL_POWER_EVENTS,
+       P4_EVENT_TC_MS_XFER,
+       P4_EVENT_UOP_QUEUE_WRITES,
+       P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
+       P4_EVENT_RETIRED_BRANCH_TYPE,
+       P4_EVENT_RESOURCE_STALL,
+       P4_EVENT_WC_BUFFER,
+       P4_EVENT_B2B_CYCLES,
+       P4_EVENT_BNR,
+       P4_EVENT_SNOOP,
+       P4_EVENT_RESPONSE,
+       P4_EVENT_FRONT_END_EVENT,
+       P4_EVENT_EXECUTION_EVENT,
+       P4_EVENT_REPLAY_EVENT,
+       P4_EVENT_INSTR_RETIRED,
+       P4_EVENT_UOPS_RETIRED,
+       P4_EVENT_UOP_TYPE,
+       P4_EVENT_BRANCH_RETIRED,
+       P4_EVENT_MISPRED_BRANCH_RETIRED,
+       P4_EVENT_X87_ASSIST,
+       P4_EVENT_MACHINE_CLEAR,
+       P4_EVENT_INSTR_COMPLETED,
+};
+
+#define P4_OPCODE(event)               event##_OPCODE
+#define P4_OPCODE_ESEL(opcode)         ((opcode & 0x00ff) >> 0)
+#define P4_OPCODE_EVNT(opcode)         ((opcode & 0xff00) >> 8)
+#define P4_OPCODE_PACK(event, sel)     (((event) << 8) | sel)
+
+/*
+ * Comments below the event represent ESCR restriction
+ * for this event and counter index per ESCR
+ *
+ * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
+ * processor builds (family 0FH, models 01H-02H). These MSRs
+ * are not available on later versions, so that we don't use
+ * them completely
+ *
+ * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
+ * working so that we should not use this CCCR and respective
+ * counter as result
+ */
+enum P4_EVENT_OPCODES {
+       P4_OPCODE(P4_EVENT_TC_DELIVER_MODE)             = P4_OPCODE_PACK(0x01, 0x01),
+       /*
+        * MSR_P4_TC_ESCR0:     4, 5
+        * MSR_P4_TC_ESCR1:     6, 7
+        */
+
+       P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST)           = P4_OPCODE_PACK(0x03, 0x00),
+       /*
+        * MSR_P4_BPU_ESCR0:    0, 1
+        * MSR_P4_BPU_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_ITLB_REFERENCE)              = P4_OPCODE_PACK(0x18, 0x03),
+       /*
+        * MSR_P4_ITLB_ESCR0:   0, 1
+        * MSR_P4_ITLB_ESCR1:   2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_MEMORY_CANCEL)               = P4_OPCODE_PACK(0x02, 0x05),
+       /*
+        * MSR_P4_DAC_ESCR0:    8, 9
+        * MSR_P4_DAC_ESCR1:    10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_MEMORY_COMPLETE)             = P4_OPCODE_PACK(0x08, 0x02),
+       /*
+        * MSR_P4_SAAT_ESCR0:   8, 9
+        * MSR_P4_SAAT_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY)            = P4_OPCODE_PACK(0x04, 0x02),
+       /*
+        * MSR_P4_SAAT_ESCR0:   8, 9
+        * MSR_P4_SAAT_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY)           = P4_OPCODE_PACK(0x05, 0x02),
+       /*
+        * MSR_P4_SAAT_ESCR0:   8, 9
+        * MSR_P4_SAAT_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY)             = P4_OPCODE_PACK(0x03, 0x02),
+       /*
+        * MSR_P4_MOB_ESCR0:    0, 1
+        * MSR_P4_MOB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE)              = P4_OPCODE_PACK(0x01, 0x04),
+       /*
+        * MSR_P4_PMH_ESCR0:    0, 1
+        * MSR_P4_PMH_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE)         = P4_OPCODE_PACK(0x0c, 0x07),
+       /*
+        * MSR_P4_BSU_ESCR0:    0, 1
+        * MSR_P4_BSU_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_IOQ_ALLOCATION)              = P4_OPCODE_PACK(0x03, 0x06),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES)          = P4_OPCODE_PACK(0x1a, 0x06),
+       /*
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY)           = P4_OPCODE_PACK(0x17, 0x06),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_BSQ_ALLOCATION)              = P4_OPCODE_PACK(0x05, 0x07),
+       /*
+        * MSR_P4_BSU_ESCR0:    0, 1
+        */
+
+       P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES)          = P4_OPCODE_PACK(0x06, 0x07),
+       /*
+        * NOTE: no ESCR name in docs, it's guessed
+        * MSR_P4_BSU_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST)            = P4_OPCODE_PACK(0x34, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_PACKED_SP_UOP)               = P4_OPCODE_PACK(0x08, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_PACKED_DP_UOP)               = P4_OPCODE_PACK(0x0c, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_SCALAR_SP_UOP)               = P4_OPCODE_PACK(0x0a, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_SCALAR_DP_UOP)               = P4_OPCODE_PACK(0x0e, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_64BIT_MMX_UOP)               = P4_OPCODE_PACK(0x02, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_128BIT_MMX_UOP)              = P4_OPCODE_PACK(0x1a, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_X87_FP_UOP)                  = P4_OPCODE_PACK(0x04, 0x01),
+       /*
+        * MSR_P4_FIRM_ESCR0:   8, 9
+        * MSR_P4_FIRM_ESCR1:   10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_TC_MISC)                     = P4_OPCODE_PACK(0x06, 0x01),
+       /*
+        * MSR_P4_TC_ESCR0:     4, 5
+        * MSR_P4_TC_ESCR1:     6, 7
+        */
+
+       P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS)         = P4_OPCODE_PACK(0x13, 0x06),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_TC_MS_XFER)                  = P4_OPCODE_PACK(0x05, 0x00),
+       /*
+        * MSR_P4_MS_ESCR0:     4, 5
+        * MSR_P4_MS_ESCR1:     6, 7
+        */
+
+       P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES)            = P4_OPCODE_PACK(0x09, 0x00),
+       /*
+        * MSR_P4_MS_ESCR0:     4, 5
+        * MSR_P4_MS_ESCR1:     6, 7
+        */
+
+       P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02),
+       /*
+        * MSR_P4_TBPU_ESCR0:   4, 5
+        * MSR_P4_TBPU_ESCR1:   6, 7
+        */
+
+       P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE)         = P4_OPCODE_PACK(0x04, 0x02),
+       /*
+        * MSR_P4_TBPU_ESCR0:   4, 5
+        * MSR_P4_TBPU_ESCR1:   6, 7
+        */
+
+       P4_OPCODE(P4_EVENT_RESOURCE_STALL)              = P4_OPCODE_PACK(0x01, 0x01),
+       /*
+        * MSR_P4_ALF_ESCR0:    12, 13, 16
+        * MSR_P4_ALF_ESCR1:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_WC_BUFFER)                   = P4_OPCODE_PACK(0x05, 0x05),
+       /*
+        * MSR_P4_DAC_ESCR0:    8, 9
+        * MSR_P4_DAC_ESCR1:    10, 11
+        */
+
+       P4_OPCODE(P4_EVENT_B2B_CYCLES)                  = P4_OPCODE_PACK(0x16, 0x03),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_BNR)                         = P4_OPCODE_PACK(0x08, 0x03),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_SNOOP)                       = P4_OPCODE_PACK(0x06, 0x03),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_RESPONSE)                    = P4_OPCODE_PACK(0x04, 0x03),
+       /*
+        * MSR_P4_FSB_ESCR0:    0, 1
+        * MSR_P4_FSB_ESCR1:    2, 3
+        */
+
+       P4_OPCODE(P4_EVENT_FRONT_END_EVENT)             = P4_OPCODE_PACK(0x08, 0x05),
+       /*
+        * MSR_P4_CRU_ESCR2:    12, 13, 16
+        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_EXECUTION_EVENT)             = P4_OPCODE_PACK(0x0c, 0x05),
+       /*
+        * MSR_P4_CRU_ESCR2:    12, 13, 16
+        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_REPLAY_EVENT)                = P4_OPCODE_PACK(0x09, 0x05),
+       /*
+        * MSR_P4_CRU_ESCR2:    12, 13, 16
+        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_INSTR_RETIRED)               = P4_OPCODE_PACK(0x02, 0x04),
+       /*
+        * MSR_P4_CRU_ESCR0:    12, 13, 16
+        * MSR_P4_CRU_ESCR1:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_UOPS_RETIRED)                = P4_OPCODE_PACK(0x01, 0x04),
+       /*
+        * MSR_P4_CRU_ESCR0:    12, 13, 16
+        * MSR_P4_CRU_ESCR1:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_UOP_TYPE)                    = P4_OPCODE_PACK(0x02, 0x02),
+       /*
+        * MSR_P4_RAT_ESCR0:    12, 13, 16
+        * MSR_P4_RAT_ESCR1:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_BRANCH_RETIRED)              = P4_OPCODE_PACK(0x06, 0x05),
+       /*
+        * MSR_P4_CRU_ESCR2:    12, 13, 16
+        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED)      = P4_OPCODE_PACK(0x03, 0x04),
+       /*
+        * MSR_P4_CRU_ESCR0:    12, 13, 16
+        * MSR_P4_CRU_ESCR1:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_X87_ASSIST)                  = P4_OPCODE_PACK(0x03, 0x05),
+       /*
+        * MSR_P4_CRU_ESCR2:    12, 13, 16
+        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_MACHINE_CLEAR)               = P4_OPCODE_PACK(0x02, 0x05),
+       /*
+        * MSR_P4_CRU_ESCR2:    12, 13, 16
+        * MSR_P4_CRU_ESCR3:    14, 15, 17
+        */
+
+       P4_OPCODE(P4_EVENT_INSTR_COMPLETED)             = P4_OPCODE_PACK(0x07, 0x04),
+       /*
+        * MSR_P4_CRU_ESCR0:    12, 13, 16
+        * MSR_P4_CRU_ESCR1:    14, 15, 17
+        */
+};
+
+/*
+ * a caller should use P4_ESCR_EMASK_NAME helper to
+ * pick the EventMask needed, for example
+ *
+ *     P4_ESCR_EMASK_NAME(P4_EVENT_TC_DELIVER_MODE, DD)
+ */
+enum P4_ESCR_EMASKS {
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
+       P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
+       P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
+       P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
+       P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
+       P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
+       P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
+
+       P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
+       P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
+};
+
+/* P4 PEBS: stale for a while */
+#define P4_PEBS_METRIC_MASK    0x00001fffU
+#define P4_PEBS_UOB_TAG                0x01000000U
+#define P4_PEBS_ENABLE         0x02000000U
+
+/* Replay metrics for MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT */
+#define P4_PEBS__1stl_cache_load_miss_retired  0x3000001
+#define P4_PEBS__2ndl_cache_load_miss_retired  0x3000002
+#define P4_PEBS__dtlb_load_miss_retired                0x3000004
+#define P4_PEBS__dtlb_store_miss_retired       0x3000004
+#define P4_PEBS__dtlb_all_miss_retired         0x3000004
+#define P4_PEBS__tagged_mispred_branch         0x3018000
+#define P4_PEBS__mob_load_replay_retired       0x3000200
+#define P4_PEBS__split_load_retired            0x3000400
+#define P4_PEBS__split_store_retired           0x3000400
+
+#define P4_VERT__1stl_cache_load_miss_retired  0x0000001
+#define P4_VERT__2ndl_cache_load_miss_retired  0x0000001
+#define P4_VERT__dtlb_load_miss_retired                0x0000001
+#define P4_VERT__dtlb_store_miss_retired       0x0000002
+#define P4_VERT__dtlb_all_miss_retired         0x0000003
+#define P4_VERT__tagged_mispred_branch         0x0000010
+#define P4_VERT__mob_load_replay_retired       0x0000001
+#define P4_VERT__split_load_retired            0x0000001
+#define P4_VERT__split_store_retired           0x0000002
+
+enum P4_CACHE_EVENTS {
+       P4_CACHE__NONE,
+
+       P4_CACHE__1stl_cache_load_miss_retired,
+       P4_CACHE__2ndl_cache_load_miss_retired,
+       P4_CACHE__dtlb_load_miss_retired,
+       P4_CACHE__dtlb_store_miss_retired,
+       P4_CACHE__itlb_reference_hit,
+       P4_CACHE__itlb_reference_miss,
+
+       P4_CACHE__MAX
+};
+
+#endif /* PERF_EVENT_P4_H */
index b753ea59703a114f056b32d9b1455622d7b131a9..32428b410b55007efd526e902d5f5e5b330474f0 100644 (file)
@@ -21,7 +21,6 @@ struct mm_struct;
 #include <asm/msr.h>
 #include <asm/desc_defs.h>
 #include <asm/nops.h>
-#include <asm/ds.h>
 
 #include <linux/personality.h>
 #include <linux/cpumask.h>
@@ -29,6 +28,7 @@ struct mm_struct;
 #include <linux/threads.h>
 #include <linux/math64.h>
 #include <linux/init.h>
+#include <linux/err.h>
 
 #define HBP_NUM 4
 /*
@@ -473,10 +473,6 @@ struct thread_struct {
        unsigned long           iopl;
        /* Max allowed port in the bitmap, in bytes: */
        unsigned                io_bitmap_max;
-/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
-       unsigned long   debugctlmsr;
-       /* Debug Store context; see asm/ds.h */
-       struct ds_context       *ds_ctx;
 };
 
 static inline unsigned long native_get_debugreg(int regno)
@@ -803,7 +799,7 @@ extern void cpu_init(void);
 
 static inline unsigned long get_debugctlmsr(void)
 {
-    unsigned long debugctlmsr = 0;
+       unsigned long debugctlmsr = 0;
 
 #ifndef CONFIG_X86_DEBUGCTLMSR
        if (boot_cpu_data.x86 < 6)
@@ -811,21 +807,6 @@ static inline unsigned long get_debugctlmsr(void)
 #endif
        rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 
-    return debugctlmsr;
-}
-
-static inline unsigned long get_debugctlmsr_on_cpu(int cpu)
-{
-       u64 debugctlmsr = 0;
-       u32 val1, val2;
-
-#ifndef CONFIG_X86_DEBUGCTLMSR
-       if (boot_cpu_data.x86 < 6)
-               return 0;
-#endif
-       rdmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &val1, &val2);
-       debugctlmsr = val1 | ((u64)val2 << 32);
-
        return debugctlmsr;
 }
 
@@ -838,18 +819,6 @@ static inline void update_debugctlmsr(unsigned long debugctlmsr)
        wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 }
 
-static inline void update_debugctlmsr_on_cpu(int cpu,
-                                            unsigned long debugctlmsr)
-{
-#ifndef CONFIG_X86_DEBUGCTLMSR
-       if (boot_cpu_data.x86 < 6)
-               return;
-#endif
-       wrmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,
-                    (u32)((u64)debugctlmsr),
-                    (u32)((u64)debugctlmsr >> 32));
-}
-
 /*
  * from system description table in BIOS. Mostly for MCA use, but
  * others may find it useful:
index 86723035a5150ea3016a7d3fd18b0192bdbd0a3a..52b098a6eebbfa8b72d4e4b90fdecff89af3af40 100644 (file)
 
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
-
-/* configuration/status structure used in PTRACE_BTS_CONFIG and
-   PTRACE_BTS_STATUS commands.
-*/
-struct ptrace_bts_config {
-       /* requested or actual size of BTS buffer in bytes */
-       __u32 size;
-       /* bitmask of below flags */
-       __u32 flags;
-       /* buffer overflow signal */
-       __u32 signal;
-       /* actual size of bts_struct in bytes */
-       __u32 bts_size;
-};
-#endif /* __ASSEMBLY__ */
-
-#define PTRACE_BTS_O_TRACE     0x1 /* branch trace */
-#define PTRACE_BTS_O_SCHED     0x2 /* scheduling events w/ jiffies */
-#define PTRACE_BTS_O_SIGNAL     0x4 /* send SIG<signal> on buffer overflow
-                                      instead of wrapping around */
-#define PTRACE_BTS_O_ALLOC     0x8 /* (re)allocate buffer */
-
-#define PTRACE_BTS_CONFIG      40
-/* Configure branch trace recording.
-   ADDR points to a struct ptrace_bts_config.
-   DATA gives the size of that buffer.
-   A new buffer is allocated, if requested in the flags.
-   An overflow signal may only be requested for new buffers.
-   Returns the number of bytes read.
-*/
-#define PTRACE_BTS_STATUS      41
-/* Return the current configuration in a struct ptrace_bts_config
-   pointed to by ADDR; DATA gives the size of that buffer.
-   Returns the number of bytes written.
-*/
-#define PTRACE_BTS_SIZE                42
-/* Return the number of available BTS records for draining.
-   DATA and ADDR are ignored.
-*/
-#define PTRACE_BTS_GET         43
-/* Get a single BTS record.
-   DATA defines the index into the BTS array, where 0 is the newest
-   entry, and higher indices refer to older entries.
-   ADDR is pointing to struct bts_struct (see asm/ds.h).
-*/
-#define PTRACE_BTS_CLEAR       44
-/* Clear the BTS buffer.
-   DATA and ADDR are ignored.
-*/
-#define PTRACE_BTS_DRAIN       45
-/* Read all available BTS records and clear the buffer.
-   ADDR points to an array of struct bts_struct.
-   DATA gives the size of that buffer.
-   BTS records are read from oldest to newest.
-   Returns number of BTS records drained.
-*/
+#endif
 
 #endif /* _ASM_X86_PTRACE_ABI_H */
index 69a686a7dff0bd991e6cde83e057e3884ea805ba..78cd1ea945008da5c1405e0db89201b78dd90d7a 100644 (file)
@@ -289,12 +289,6 @@ extern int do_get_thread_area(struct task_struct *p, int idx,
 extern int do_set_thread_area(struct task_struct *p, int idx,
                              struct user_desc __user *info, int can_allocate);
 
-#ifdef CONFIG_X86_PTRACE_BTS
-extern void ptrace_bts_untrace(struct task_struct *tsk);
-
-#define arch_ptrace_untrace(tsk)       ptrace_bts_untrace(tsk)
-#endif /* CONFIG_X86_PTRACE_BTS */
-
 #endif /* __KERNEL__ */
 
 #endif /* !__ASSEMBLY__ */
index e0d28901e9691ee53fcd57edf0fa08a6cd5ce8c2..d017ed5502e27d747a99e048884e28c3316f0bd0 100644 (file)
@@ -92,8 +92,7 @@ struct thread_info {
 #define TIF_IO_BITMAP          22      /* uses I/O bitmap */
 #define TIF_FREEZE             23      /* is freezing for suspend */
 #define TIF_FORCED_TF          24      /* true if TF in eflags artificially */
-#define TIF_DEBUGCTLMSR                25      /* uses thread_struct.debugctlmsr */
-#define TIF_DS_AREA_MSR                26      /* uses thread_struct.ds_area_msr */
+#define TIF_BLOCKSTEP          25      /* set when we want DEBUGCTLMSR_BTF */
 #define TIF_LAZY_MMU_UPDATES   27      /* task is updating the mmu lazily */
 #define TIF_SYSCALL_TRACEPOINT 28      /* syscall tracepoint instrumentation */
 
@@ -115,8 +114,7 @@ struct thread_info {
 #define _TIF_IO_BITMAP         (1 << TIF_IO_BITMAP)
 #define _TIF_FREEZE            (1 << TIF_FREEZE)
 #define _TIF_FORCED_TF         (1 << TIF_FORCED_TF)
-#define _TIF_DEBUGCTLMSR       (1 << TIF_DEBUGCTLMSR)
-#define _TIF_DS_AREA_MSR       (1 << TIF_DS_AREA_MSR)
+#define _TIF_BLOCKSTEP         (1 << TIF_BLOCKSTEP)
 #define _TIF_LAZY_MMU_UPDATES  (1 << TIF_LAZY_MMU_UPDATES)
 #define _TIF_SYSCALL_TRACEPOINT        (1 << TIF_SYSCALL_TRACEPOINT)
 
@@ -147,7 +145,7 @@ struct thread_info {
 
 /* flags to check in __switch_to() */
 #define _TIF_WORK_CTXSW                                                        \
-       (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_NOTSC)
+       (_TIF_IO_BITMAP|_TIF_NOTSC|_TIF_BLOCKSTEP)
 
 #define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
 #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
index 4c58352209e0e89114778a80f66e3025d315e670..e77b220837214cef81deff278e2f79ef1ed202a7 100644 (file)
@@ -47,8 +47,6 @@ obj-$(CONFIG_X86_TRAMPOLINE)  += trampoline.o
 obj-y                          += process.o
 obj-y                          += i387.o xsave.o
 obj-y                          += ptrace.o
-obj-$(CONFIG_X86_DS)           += ds.o
-obj-$(CONFIG_X86_DS_SELFTEST)          += ds_selftest.o
 obj-$(CONFIG_X86_32)           += tls.o
 obj-$(CONFIG_IA32_EMULATION)   += tls.o
 obj-y                          += step.o
index f854d89b7edf6cdc933043732497020e4cdb48a2..fa5a1474cd182db250e189cfc8b262683f2585ba 100644 (file)
@@ -731,18 +731,22 @@ static bool increase_address_space(struct protection_domain *domain,
 
 static u64 *alloc_pte(struct protection_domain *domain,
                      unsigned long address,
-                     int end_lvl,
+                     unsigned long page_size,
                      u64 **pte_page,
                      gfp_t gfp)
 {
+       int level, end_lvl;
        u64 *pte, *page;
-       int level;
+
+       BUG_ON(!is_power_of_2(page_size));
 
        while (address > PM_LEVEL_SIZE(domain->mode))
                increase_address_space(domain, gfp);
 
-       level =  domain->mode - 1;
-       pte   = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
+       level   = domain->mode - 1;
+       pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
+       address = PAGE_SIZE_ALIGN(address, page_size);
+       end_lvl = PAGE_SIZE_LEVEL(page_size);
 
        while (level > end_lvl) {
                if (!IOMMU_PTE_PRESENT(*pte)) {
@@ -752,6 +756,10 @@ static u64 *alloc_pte(struct protection_domain *domain,
                        *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
                }
 
+               /* No level skipping support yet */
+               if (PM_PTE_LEVEL(*pte) != level)
+                       return NULL;
+
                level -= 1;
 
                pte = IOMMU_PTE_PAGE(*pte);
@@ -769,28 +777,47 @@ static u64 *alloc_pte(struct protection_domain *domain,
  * This function checks if there is a PTE for a given dma address. If
  * there is one, it returns the pointer to it.
  */
-static u64 *fetch_pte(struct protection_domain *domain,
-                     unsigned long address, int map_size)
+static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
 {
        int level;
        u64 *pte;
 
-       level =  domain->mode - 1;
-       pte   = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
+       if (address > PM_LEVEL_SIZE(domain->mode))
+               return NULL;
+
+       level   =  domain->mode - 1;
+       pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
 
-       while (level > map_size) {
+       while (level > 0) {
+
+               /* Not Present */
                if (!IOMMU_PTE_PRESENT(*pte))
                        return NULL;
 
+               /* Large PTE */
+               if (PM_PTE_LEVEL(*pte) == 0x07) {
+                       unsigned long pte_mask, __pte;
+
+                       /*
+                        * If we have a series of large PTEs, make
+                        * sure to return a pointer to the first one.
+                        */
+                       pte_mask = PTE_PAGE_SIZE(*pte);
+                       pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
+                       __pte    = ((unsigned long)pte) & pte_mask;
+
+                       return (u64 *)__pte;
+               }
+
+               /* No level skipping support yet */
+               if (PM_PTE_LEVEL(*pte) != level)
+                       return NULL;
+
                level -= 1;
 
+               /* Walk to the next level */
                pte = IOMMU_PTE_PAGE(*pte);
                pte = &pte[PM_LEVEL_INDEX(level, address)];
-
-               if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
-                       pte = NULL;
-                       break;
-               }
        }
 
        return pte;
@@ -807,44 +834,84 @@ static int iommu_map_page(struct protection_domain *dom,
                          unsigned long bus_addr,
                          unsigned long phys_addr,
                          int prot,
-                         int map_size)
+                         unsigned long page_size)
 {
        u64 __pte, *pte;
-
-       bus_addr  = PAGE_ALIGN(bus_addr);
-       phys_addr = PAGE_ALIGN(phys_addr);
-
-       BUG_ON(!PM_ALIGNED(map_size, bus_addr));
-       BUG_ON(!PM_ALIGNED(map_size, phys_addr));
+       int i, count;
 
        if (!(prot & IOMMU_PROT_MASK))