clk: stm32mp1: parent clocks update

Fixes parent clock for axi, fdcan, sai and adc12 clocks.

Fixes: e51d297e9a92 ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6a31f7f434ce47739bdeb548aa6154a013dfe1ae..be2ed35977ca980550ddf3029cdeef5738872670 100644 (file)
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -121,7 +121,7 @@ static const char * const cpu_src[] = {
 };
 
 static const char * const axi_src[] = {
-       "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
+       "ck_hsi", "ck_hse", "pll2_p"
 };
 
 static const char * const per_src[] = {
@@ -225,19 +225,19 @@ static const char * const usart6_src[] = {
 };
 
 static const char * const fdcan_src[] = {
-       "ck_hse", "pll3_q", "pll4_q"
+       "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 };
 
 static const char * const sai_src[] = {
-       "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
+       "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 };
 
 static const char * const sai2_src[] = {
-       "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
+       "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 };
 
 static const char * const adc12_src[] = {
-       "pll4_q", "ck_per"
+       "pll4_r", "ck_per", "pll3_q"
 };
 
 static const char * const dsi_src[] = {