Merge tag 'exynos-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
authorArnd Bergmann <arnd@arndb.de>
Thu, 20 Jun 2013 20:17:38 +0000 (22:17 +0200)
committerArnd Bergmann <arnd@arndb.de>
Thu, 20 Jun 2013 20:17:38 +0000 (22:17 +0200)
From Kukjin Kim:

2nd exynos dt update based on tags/exynos-dt-1
- enable RTC on exynos5250 snow and Arndale boards
- add support LCD and PWM for exynos4210 Origen board
- update bootargs to support 8GiB for exynos5440 SSDK5440 and SD5v1 boards
- enable spi and add opp level for exynos5440
- add example doc for samsung-pinctrl dt bindings

* tag 'exynos-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: Set BUCK7 as always on for Origen board
  ARM: dts: Add FIMD node to Origen4210 board
  ARM: dts: Add LCD related pinctrl entries for exynos4210
  ARM: dts: Add PWM related pinctrl entries for exynos4210
  Documentation: Add examples to samsung-pinctrl device tree bindings documentation
  ARM: dts: Enable RTC node for exynos5250-snow
  ARM: dts: Enable RTC node for Arndale
  ARM: dts: Removing pdma for exynos5440
  ARM: dts: update bootargs to support 8GiB for SSDK5440 and SD5v1
  ARM: dts: Add more opp levels in exynos5440
  ARM: dts: Add wm8994 regulator support on smdk5250
  ARM: dts: enable spi for EXYNOS5440 SOC

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
557 files changed:
Documentation/bcache.txt
Documentation/devices.txt
Documentation/devicetree/bindings/arm/ste-nomadik.txt
Documentation/devicetree/bindings/bus/imx-weim.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/altr_socfpga.txt
Documentation/devicetree/bindings/clock/imx5-clock.txt
Documentation/devicetree/bindings/clock/imx6q-clock.txt
Documentation/devicetree/bindings/clock/imx6sl-clock.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
Documentation/devicetree/bindings/clock/st,nomadik.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/vf610-clock.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/zynq-7000.txt
Documentation/devicetree/bindings/mfd/ab8500.txt
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
Documentation/kernel-parameters.txt
Documentation/m68k/kernel-options.txt
MAINTAINERS
Makefile
arch/arm/Kconfig.debug
arch/arm/boot/compressed/Makefile
arch/arm/boot/compressed/debug.S
arch/arm/boot/compressed/head-sa1100.S
arch/arm/boot/compressed/head-shark.S
arch/arm/boot/compressed/head.S
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/aks-cdu.dts
arch/arm/boot/dts/am33xx.dtsi
arch/arm/boot/dts/animeo_ip.dts
arch/arm/boot/dts/armada-370-db.dts
arch/arm/boot/dts/armada-370-mirabox.dts
arch/arm/boot/dts/armada-370-rd.dts
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-370.dtsi
arch/arm/boot/dts/armada-xp-db.dts
arch/arm/boot/dts/armada-xp-gp.dts
arch/arm/boot/dts/armada-xp-mv78460.dtsi
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
arch/arm/boot/dts/armada-xp.dtsi
arch/arm/boot/dts/at91-ariag25.dts
arch/arm/boot/dts/at91-foxg20.dts [new file with mode: 0644]
arch/arm/boot/dts/at91rm9200.dtsi
arch/arm/boot/dts/at91rm9200ek.dts
arch/arm/boot/dts/at91sam9260.dtsi
arch/arm/boot/dts/at91sam9263.dtsi
arch/arm/boot/dts/at91sam9263ek.dts
arch/arm/boot/dts/at91sam9g15.dtsi
arch/arm/boot/dts/at91sam9g15ek.dts
arch/arm/boot/dts/at91sam9g20.dtsi
arch/arm/boot/dts/at91sam9g20ek.dts
arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
arch/arm/boot/dts/at91sam9g25.dtsi
arch/arm/boot/dts/at91sam9g25ek.dts
arch/arm/boot/dts/at91sam9g35.dtsi
arch/arm/boot/dts/at91sam9g35ek.dts
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9m10g45ek.dts
arch/arm/boot/dts/at91sam9n12.dtsi
arch/arm/boot/dts/at91sam9n12ek.dts
arch/arm/boot/dts/at91sam9x25.dtsi
arch/arm/boot/dts/at91sam9x25ek.dts
arch/arm/boot/dts/at91sam9x35.dtsi
arch/arm/boot/dts/at91sam9x35ek.dts
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/at91sam9x5cm.dtsi
arch/arm/boot/dts/at91sam9x5ek.dtsi
arch/arm/boot/dts/bcm2835-rpi-b.dts
arch/arm/boot/dts/ccu8540.dts [new file with mode: 0644]
arch/arm/boot/dts/ccu9540.dts
arch/arm/boot/dts/dbx5x0.dtsi
arch/arm/boot/dts/dove-cubox.dts
arch/arm/boot/dts/ethernut5.dts
arch/arm/boot/dts/evk-pro3.dts
arch/arm/boot/dts/exynos5440.dtsi
arch/arm/boot/dts/ge863-pro3.dtsi
arch/arm/boot/dts/href.dtsi
arch/arm/boot/dts/hrefprev60.dts
arch/arm/boot/dts/hrefv60plus.dts
arch/arm/boot/dts/imx23.dtsi
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts [new file with mode: 0644]
arch/arm/boot/dts/imx27-phytec-phycore-som.dts [new file with mode: 0644]
arch/arm/boot/dts/imx27-phytec-phycore.dts [deleted file]
arch/arm/boot/dts/imx27.dtsi
arch/arm/boot/dts/imx28-apf28dev.dts
arch/arm/boot/dts/imx28-cfa10036.dts
arch/arm/boot/dts/imx28-cfa10049.dts
arch/arm/boot/dts/imx28-cfa10055.dts [new file with mode: 0644]
arch/arm/boot/dts/imx28-cfa10057.dts [new file with mode: 0644]
arch/arm/boot/dts/imx28-m28evk.dts
arch/arm/boot/dts/imx28.dtsi
arch/arm/boot/dts/imx51-apf51.dts
arch/arm/boot/dts/imx51.dtsi
arch/arm/boot/dts/imx53-m53evk.dts [new file with mode: 0644]
arch/arm/boot/dts/imx53-mba53.dts
arch/arm/boot/dts/imx53-qsb.dts
arch/arm/boot/dts/imx53-tqma53.dtsi
arch/arm/boot/dts/imx53-tx53.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx53.dtsi
arch/arm/boot/dts/imx6dl-sabreauto.dts
arch/arm/boot/dts/imx6dl-sabresd.dts
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q-phytec-pbab01.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx6q-sabreauto.dts
arch/arm/boot/dts/imx6q-sabresd.dts
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6sl-evk.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6sl.dtsi [new file with mode: 0644]
arch/arm/boot/dts/kirkwood-6281.dtsi
arch/arm/boot/dts/kirkwood-6282.dtsi
arch/arm/boot/dts/kirkwood-cloudbox.dts
arch/arm/boot/dts/kirkwood-dns320.dts
arch/arm/boot/dts/kirkwood-dns325.dts
arch/arm/boot/dts/kirkwood-dnskw.dtsi
arch/arm/boot/dts/kirkwood-dockstar.dts
arch/arm/boot/dts/kirkwood-dreamplug.dts
arch/arm/boot/dts/kirkwood-goflexnet.dts
arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
arch/arm/boot/dts/kirkwood-ib62x0.dts
arch/arm/boot/dts/kirkwood-iconnect.dts
arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
arch/arm/boot/dts/kirkwood-is2.dts
arch/arm/boot/dts/kirkwood-km_kirkwood.dts
arch/arm/boot/dts/kirkwood-lsxl.dtsi
arch/arm/boot/dts/kirkwood-mplcec4.dts
arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
arch/arm/boot/dts/kirkwood-ns2.dts
arch/arm/boot/dts/kirkwood-ns2lite.dts
arch/arm/boot/dts/kirkwood-ns2max.dts
arch/arm/boot/dts/kirkwood-ns2mini.dts
arch/arm/boot/dts/kirkwood-nsa310.dts
arch/arm/boot/dts/kirkwood-openblocks_a6.dts
arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi [new file with mode: 0644]
arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts [new file with mode: 0644]
arch/arm/boot/dts/kirkwood-sheevaplug.dts [new file with mode: 0644]
arch/arm/boot/dts/kirkwood-topkick.dts
arch/arm/boot/dts/kirkwood-ts219-6281.dts
arch/arm/boot/dts/kirkwood-ts219-6282.dts
arch/arm/boot/dts/kirkwood-ts219.dtsi
arch/arm/boot/dts/kirkwood.dtsi
arch/arm/boot/dts/kizbox.dts
arch/arm/boot/dts/lpc32xx.dtsi
arch/arm/boot/dts/mpa1600.dts
arch/arm/boot/dts/omap2.dtsi
arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap4-panda-common.dtsi
arch/arm/boot/dts/omap4-sdp.dts
arch/arm/boot/dts/omap4.dtsi
arch/arm/boot/dts/omap5.dtsi
arch/arm/boot/dts/picoxcell-pc3x2.dtsi
arch/arm/boot/dts/picoxcell-pc3x3.dtsi
arch/arm/boot/dts/pm9g45.dts
arch/arm/boot/dts/prima2.dtsi
arch/arm/boot/dts/pxa2xx.dtsi
arch/arm/boot/dts/r8a73a4.dtsi
arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts [new file with mode: 0644]
arch/arm/boot/dts/r8a7740.dtsi
arch/arm/boot/dts/r8a7779.dtsi
arch/arm/boot/dts/r8a7790.dtsi
arch/arm/boot/dts/s3c2416-pinctrl.dtsi [new file with mode: 0644]
arch/arm/boot/dts/s3c2416-smdk2416.dts [new file with mode: 0644]
arch/arm/boot/dts/s3c2416.dtsi [new file with mode: 0644]
arch/arm/boot/dts/s3c24xx.dtsi [new file with mode: 0644]
arch/arm/boot/dts/sama5d3.dtsi
arch/arm/boot/dts/sama5d31ek.dts
arch/arm/boot/dts/sama5d33ek.dts
arch/arm/boot/dts/sama5d34ek.dts
arch/arm/boot/dts/sama5d35ek.dts
arch/arm/boot/dts/sama5d3xcm.dtsi
arch/arm/boot/dts/sama5d3xdm.dtsi
arch/arm/boot/dts/sama5d3xmb.dtsi
arch/arm/boot/dts/sh7372.dtsi
arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
arch/arm/boot/dts/snowball.dts
arch/arm/boot/dts/socfpga.dtsi
arch/arm/boot/dts/socfpga_cyclone5.dts
arch/arm/boot/dts/socfpga_vt.dts
arch/arm/boot/dts/spear13xx.dtsi
arch/arm/boot/dts/spear3xx.dtsi
arch/arm/boot/dts/spear600.dtsi
arch/arm/boot/dts/ste-nomadik-s8815.dts
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
arch/arm/boot/dts/stuib.dtsi
arch/arm/boot/dts/sun4i-a10-cubieboard.dts
arch/arm/boot/dts/sun4i-a10.dtsi
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts [new file with mode: 0644]
arch/arm/boot/dts/sun5i-a10s.dtsi [new file with mode: 0644]
arch/arm/boot/dts/sun5i-a13-olinuxino.dts
arch/arm/boot/dts/sun5i-a13.dtsi
arch/arm/boot/dts/tegra114-dalmore.dts
arch/arm/boot/dts/tegra114-pluto.dts
arch/arm/boot/dts/tegra114.dtsi
arch/arm/boot/dts/tegra20-colibri-512.dtsi
arch/arm/boot/dts/tegra20-harmony.dts
arch/arm/boot/dts/tegra20-iris-512.dts
arch/arm/boot/dts/tegra20-medcom-wide.dts
arch/arm/boot/dts/tegra20-paz00.dts
arch/arm/boot/dts/tegra20-plutux.dts
arch/arm/boot/dts/tegra20-seaboard.dts
arch/arm/boot/dts/tegra20-tamonten.dtsi
arch/arm/boot/dts/tegra20-tec.dts
arch/arm/boot/dts/tegra20-trimslice.dts
arch/arm/boot/dts/tegra20-ventana.dts
arch/arm/boot/dts/tegra20-whistler.dts
arch/arm/boot/dts/tegra20.dtsi
arch/arm/boot/dts/tegra30-beaver.dts
arch/arm/boot/dts/tegra30-cardhu-a02.dts
arch/arm/boot/dts/tegra30-cardhu-a04.dts
arch/arm/boot/dts/tegra30-cardhu.dtsi
arch/arm/boot/dts/tegra30.dtsi
arch/arm/boot/dts/tny_a9260.dts
arch/arm/boot/dts/tny_a9263.dts
arch/arm/boot/dts/tny_a9g20.dts
arch/arm/boot/dts/usb_a9260.dts
arch/arm/boot/dts/usb_a9260_common.dtsi
arch/arm/boot/dts/usb_a9263.dts
arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
arch/arm/boot/dts/usb_a9g20.dts
arch/arm/boot/dts/usb_a9g20_common.dtsi [new file with mode: 0644]
arch/arm/boot/dts/usb_a9g20_lpw.dts [new file with mode: 0644]
arch/arm/boot/dts/vf610-pinfunc.h [new file with mode: 0644]
arch/arm/boot/dts/vf610-twr.dts [new file with mode: 0644]
arch/arm/boot/dts/vf610.dtsi [new file with mode: 0644]
arch/arm/boot/dts/vt8500-bv07.dts
arch/arm/boot/dts/vt8500.dtsi
arch/arm/boot/dts/wm8505-ref.dts
arch/arm/boot/dts/wm8505.dtsi
arch/arm/boot/dts/wm8650-mid.dts
arch/arm/boot/dts/wm8650.dtsi
arch/arm/boot/dts/wm8750-apc8750.dts [new file with mode: 0644]
arch/arm/boot/dts/wm8750.dtsi [new file with mode: 0644]
arch/arm/boot/dts/wm8850-w70v2.dts
arch/arm/boot/dts/wm8850.dtsi
arch/arm/boot/dts/zynq-7000.dtsi
arch/arm/boot/dts/zynq-zc702.dts
arch/arm/boot/dts/zynq-zc706.dts [new file with mode: 0644]
arch/arm/boot/dts/zynq-zed.dts [new file with mode: 0644]
arch/arm/configs/at91_dt_defconfig
arch/arm/configs/at91rm9200_defconfig
arch/arm/configs/at91sam9260_9g20_defconfig [moved from arch/arm/configs/at91sam9g20_defconfig with 67% similarity]
arch/arm/configs/at91sam9260_defconfig [deleted file]
arch/arm/configs/at91sam9261_9g10_defconfig [moved from arch/arm/configs/at91sam9261_defconfig with 91% similarity]
arch/arm/configs/at91sam9263_defconfig
arch/arm/configs/at91sam9g45_defconfig
arch/arm/configs/imx_v6_v7_defconfig
arch/arm/configs/nhk8815_defconfig
arch/arm/configs/sama5_defconfig
arch/arm/include/asm/percpu.h
arch/arm/include/debug/imx-uart.h
arch/arm/kernel/topology.c
arch/arm/mach-at91/Kconfig.non_dt
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9x5.c
arch/arm/mach-at91/board-sam9261ek.c
arch/arm/mach-at91/board-usb-a926x.c [deleted file]
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/clk-imx51-imx53.c
arch/arm/mach-imx/clk-imx6q.c
arch/arm/mach-imx/clk-imx6sl.c [new file with mode: 0644]
arch/arm/mach-imx/clk-pllv3.c
arch/arm/mach-imx/clk-vf610.c [new file with mode: 0644]
arch/arm/mach-imx/clk.c
arch/arm/mach-imx/clk.h
arch/arm/mach-imx/common.h
arch/arm/mach-imx/hardware.h
arch/arm/mach-imx/imx25-dt.c
arch/arm/mach-imx/imx27-dt.c
arch/arm/mach-imx/imx31-dt.c
arch/arm/mach-imx/imx51-dt.c
arch/arm/mach-imx/irq-common.c
arch/arm/mach-imx/mach-imx53.c
arch/arm/mach-imx/mach-imx6q.c
arch/arm/mach-imx/mach-imx6sl.c [new file with mode: 0644]
arch/arm/mach-imx/mach-pca100.c
arch/arm/mach-imx/mach-vf610.c [new file with mode: 0644]
arch/arm/mach-imx/mm-imx1.c
arch/arm/mach-imx/mm-imx21.c
arch/arm/mach-imx/mm-imx25.c
arch/arm/mach-imx/mm-imx27.c
arch/arm/mach-imx/mm-imx3.c
arch/arm/mach-imx/mm-imx5.c
arch/arm/mach-imx/system.c
arch/arm/mach-imx/ulpi.c [deleted file]
arch/arm/mach-imx/ulpi.h
arch/arm/mach-kirkwood/mpp.c
arch/arm/mach-mxs/Kconfig
arch/arm/mach-mxs/mach-mxs.c
arch/arm/mach-nomadik/Kconfig
arch/arm/mach-nomadik/cpu-8815.c
arch/arm/mach-omap2/clock36xx.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-prima2/pm.c
arch/arm/mach-prima2/rstc.c
arch/arm/mach-s3c24xx/Kconfig
arch/arm/mach-s3c24xx/Makefile
arch/arm/mach-s3c24xx/mach-s3c2416-dt.c [new file with mode: 0644]
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/Makefile
arch/arm/mach-shmobile/board-armadillo800eva-reference.c [new file with mode: 0644]
arch/arm/mach-shmobile/include/mach/r8a7740.h
arch/arm/mach-shmobile/intc-r8a7740.c
arch/arm/mach-shmobile/setup-r8a7740.c
arch/arm/mach-ux500/cpu-db8500.c
arch/arm/mach-zynq/common.c
arch/arm/mach-zynq/slcr.c
arch/arm/plat-samsung/pm.c
arch/mips/include/asm/mmu_context.h
arch/mips/include/uapi/asm/kvm.h
arch/mips/kernel/ftrace.c
arch/mips/kernel/idle.c
arch/mips/kvm/kvm_mips.c
arch/powerpc/include/asm/cputable.h
arch/powerpc/include/asm/exception-64s.h
arch/powerpc/include/asm/kvm_asm.h
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/entry_64.S
arch/powerpc/kernel/exceptions-64s.S
arch/powerpc/kernel/irq.c
arch/powerpc/kernel/pci-common.c
arch/powerpc/kernel/process.c
arch/powerpc/kernel/traps.c
arch/powerpc/kvm/44x_tlb.c
arch/powerpc/kvm/booke.c
arch/powerpc/kvm/e500_mmu.c
arch/powerpc/kvm/e500mc.c
arch/powerpc/perf/core-book3s.c
arch/powerpc/platforms/pseries/eeh_pseries.c
arch/s390/include/asm/pgtable.h
arch/s390/kernel/dumpstack.c
arch/s390/kernel/irq.c
arch/s390/kernel/sclp.S
arch/s390/pci/pci.c
arch/sparc/kernel/prom_common.c
arch/x86/boot/compressed/eboot.c
arch/x86/include/asm/efi.h
arch/x86/include/uapi/asm/bootparam.h
arch/x86/kernel/relocate_kernel_64.S
arch/x86/mm/init.c
arch/x86/platform/efi/efi.c
arch/x86/tools/relocs.c
arch/x86/xen/smp.c
block/blk-core.c
crypto/Kconfig
drivers/acpi/scan.c
drivers/acpi/video.c
drivers/base/regmap/regcache-rbtree.c
drivers/base/regmap/regcache.c
drivers/base/regmap/regmap-debugfs.c
drivers/block/cciss.c
drivers/block/mtip32xx/mtip32xx.c
drivers/block/nvme-core.c
drivers/block/nvme-scsi.c
drivers/block/pktcdvd.c
drivers/block/rbd.c
drivers/bluetooth/Kconfig
drivers/bluetooth/btmrvl_sdio.c
drivers/bus/Kconfig
drivers/bus/Makefile
drivers/bus/imx-weim.c [new file with mode: 0644]
drivers/clk/Makefile
drivers/clk/clk-nomadik.c
drivers/clk/clk-zynq.c [deleted file]
drivers/clk/zynq/Makefile [new file with mode: 0644]
drivers/clk/zynq/clkc.c [new file with mode: 0644]
drivers/clk/zynq/pll.c [new file with mode: 0644]
drivers/clocksource/cadence_ttc_timer.c
drivers/clocksource/nomadik-mtu.c
drivers/crypto/sahara.c
drivers/crypto/ux500/cryp/cryp_core.c
drivers/crypto/ux500/hash/hash_core.c
drivers/gpu/drm/gma500/cdv_intel_display.c
drivers/gpu/drm/gma500/framebuffer.c
drivers/gpu/drm/gma500/psb_intel_display.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/hid/hid-multitouch.c
drivers/hwmon/adm1021.c
drivers/md/bcache/Kconfig
drivers/md/bcache/bcache.h
drivers/md/bcache/stats.c
drivers/md/bcache/super.c
drivers/md/bcache/writeback.c
drivers/md/md.c
drivers/md/raid1.c
drivers/md/raid10.c
drivers/md/raid5.c
drivers/misc/mei/init.c
drivers/misc/mei/nfc.c
drivers/misc/mei/pci-me.c
drivers/misc/sgi-gru/grufile.c
drivers/net/bonding/bond_main.c
drivers/net/bonding/bonding.h
drivers/net/ethernet/broadcom/tg3.c
drivers/net/ethernet/dec/tulip/interrupt.c
drivers/net/ethernet/emulex/benet/be_main.c
drivers/net/ethernet/renesas/sh_eth.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/ti/davinci_mdio.c
drivers/net/macvlan.c
drivers/net/team/team.c
drivers/net/team/team_mode_random.c
drivers/net/team/team_mode_roundrobin.c
drivers/net/tun.c
drivers/net/usb/cdc_ether.c
drivers/net/usb/qmi_wwan.c
drivers/net/wireless/ath/ath9k/Kconfig
drivers/net/wireless/ath/ath9k/Makefile
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
drivers/net/wireless/ath/ath9k/init.c
drivers/net/wireless/ath/ath9k/rc.h
drivers/net/wireless/b43/main.c
drivers/net/wireless/iwlegacy/common.h
drivers/net/wireless/mwifiex/debugfs.c
drivers/net/wireless/rtlwifi/pci.c
drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
drivers/net/wireless/rtlwifi/usb.c
drivers/net/wireless/rtlwifi/wifi.h
drivers/net/wireless/ti/wl12xx/scan.c
drivers/net/wireless/ti/wl12xx/wl12xx.h
drivers/net/wireless/ti/wl18xx/scan.c
drivers/net/xen-netback/netback.c
drivers/of/base.c
drivers/pinctrl/pinctrl-nomadik.c
drivers/regulator/ab8500.c
drivers/rtc/rtc-at91rm9200.c
drivers/rtc/rtc-cmos.c
drivers/rtc/rtc-tps6586x.c
drivers/rtc/rtc-twl.c
drivers/s390/net/netiucv.c
drivers/spi/spi-sh-hspi.c
drivers/spi/spi-topcliff-pch.c
drivers/spi/spi-xilinx.c
drivers/tty/serial/xilinx_uartps.c
drivers/usb/chipidea/core.c
drivers/usb/chipidea/udc.c
drivers/usb/serial/f81232.c
drivers/usb/serial/pl2303.c
drivers/usb/serial/spcp8x5.c
drivers/vhost/net.c
drivers/vhost/vhost.c
drivers/vhost/vhost.h
drivers/xen/tmem.c
fs/aio.c
fs/btrfs/disk-io.c
fs/btrfs/inode.c
fs/btrfs/relocation.c
fs/ceph/locks.c
fs/ceph/mds_client.c
fs/ceph/super.h
fs/file_table.c
fs/namei.c
fs/ncpfs/dir.c
fs/ocfs2/dlm/dlmrecovery.c
fs/ocfs2/namei.c
fs/proc/kmsg.c
fs/xfs/xfs_attr_leaf.h
fs/xfs/xfs_btree.c
fs/xfs/xfs_dir2_format.h
fs/xfs/xfs_log_recover.c
fs/xfs/xfs_mount.c
include/asm-generic/kvm_para.h
include/dt-bindings/clock/imx6sl-clock.h [new file with mode: 0644]
include/dt-bindings/clock/tegra114-car.h [new file with mode: 0644]
include/dt-bindings/clock/tegra20-car.h [new file with mode: 0644]
include/dt-bindings/clock/tegra30-car.h [new file with mode: 0644]
include/dt-bindings/clock/vf610-clock.h [new file with mode: 0644]
include/dt-bindings/dma/at91.h [new file with mode: 0644]
include/dt-bindings/gpio/tegra-gpio.h [new file with mode: 0644]
include/dt-bindings/pinctrl/at91.h [new file with mode: 0644]
include/linux/clk/zynq.h
include/linux/cpu.h
include/linux/filter.h
include/linux/if_team.h
include/linux/math64.h
include/linux/scatterlist.h
include/linux/smp.h
include/linux/swapops.h
include/linux/syslog.h
include/linux/tracepoint.h
include/net/bluetooth/hci_core.h
include/net/bluetooth/mgmt.h
include/net/ip_tunnels.h
include/sound/soc-dapm.h
include/uapi/linux/kvm.h
init/Kconfig
kernel/audit.c
kernel/audit_tree.c
kernel/cpu.c
kernel/exit.c
kernel/printk.c
kernel/rcutree.c
kernel/rcutree.h
kernel/softirq.c
kernel/sys.c
kernel/trace/trace.c
kernel/trace/trace.h
lib/mpi/mpicoder.c
mm/frontswap.c
mm/hugetlb.c
mm/memcontrol.c
mm/migrate.c
mm/page_alloc.c
mm/swap_state.c
mm/swapfile.c
net/9p/client.c
net/batman-adv/bat_iv_ogm.c
net/batman-adv/bridge_loop_avoidance.c
net/batman-adv/sysfs.c
net/bluetooth/hci_core.c
net/bluetooth/l2cap_core.c
net/bluetooth/mgmt.c
net/bluetooth/smp.c
net/ceph/osd_client.c
net/core/filter.c
net/core/sock_diag.c
net/ipv4/ip_tunnel.c
net/ipv4/ip_vti.c
net/l2tp/l2tp_ppp.c
net/netfilter/ipvs/ip_vs_ctl.c
net/netfilter/nfnetlink_acct.c
net/netfilter/nfnetlink_cttimeout.c
net/netfilter/nfnetlink_queue_core.c
net/netfilter/xt_TCPMSS.c
net/netlink/af_netlink.c
net/packet/af_packet.c
net/sched/sch_api.c
net/sctp/outqueue.c
net/sctp/socket.c
scripts/Makefile.lib
scripts/dtc/dtc-lexer.l
scripts/dtc/dtc-lexer.lex.c_shipped
scripts/dtc/dtc-parser.tab.c_shipped
scripts/dtc/dtc-parser.tab.h_shipped
sound/core/pcm_native.c
sound/soc/codecs/cs42l52.c
sound/soc/codecs/tlv320aic3x.c
sound/soc/codecs/wm5102.c
sound/soc/codecs/wm5110.c
sound/soc/codecs/wm8994.c
sound/soc/soc-dapm.c
sound/soc/soc-pcm.c
tools/power/x86/turbostat/turbostat.c

index 77db8809bd9648b94097be84e81677fb6008f460..b3a7e7d384f6583ede08ffec4957c6f40c45172b 100644 (file)
@@ -319,7 +319,10 @@ cache<0..n>
   Symlink to each of the cache devices comprising this cache set. 
 
 cache_available_percent
-  Percentage of cache device free.
+  Percentage of cache device which doesn't contain dirty data, and could
+  potentially be used for writeback.  This doesn't mean this space isn't used
+  for clean cached data; the unused statistic (in priority_stats) is typically
+  much lower.
 
 clear_stats
   Clears the statistics associated with this cache
@@ -423,8 +426,11 @@ nbuckets
   Total buckets in this cache
 
 priority_stats
-  Statistics about how recently data in the cache has been accessed.  This can
-  reveal your working set size.
+  Statistics about how recently data in the cache has been accessed.
+  This can reveal your working set size.  Unused is the percentage of
+  the cache that doesn't contain any data.  Metadata is bcache's
+  metadata overhead.  Average is the average priority of cache buckets.
+  Next is a list of quantiles with the priority threshold of each.
 
 written
   Sum of all data that has been written to the cache; comparison with
index 08f01e79c41a3e2f3902db5cc19e2ccaa34b382b..b9015912bca6bb6ea7a73ef4dc2a94f189346385 100644 (file)
@@ -498,12 +498,8 @@ Your cooperation is appreciated.
 
                Each device type has 5 bits (32 minors).
 
- 13 block      8-bit MFM/RLL/IDE controller
-                 0 = /dev/xda          First XT disk whole disk
-                64 = /dev/xdb          Second XT disk whole disk
-
-               Partitions are handled in the same way as IDE disks
-               (see major number 3).
+ 13 block      Previously used for the XT disk (/dev/xdN)
+               Deleted in kernel v3.9.
 
  14 char       Open Sound System (OSS)
                  0 = /dev/mixer        Mixer control
index 19bca04b81c91c3dab487177f88a3057dd991f92..6256ec31666d51cb833c5d78ecfcf30293cefed2 100644 (file)
@@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings
 For various board the "board" node may contain specific properties
 that pertain to this particular board, such as board-specific GPIOs.
 
+Required root node property: src
+- Nomadik System and reset controller used for basic chip control, clock
+  and reset line control.
+- compatible: must be "stericsson,nomadik,src"
+
 Boards with the Nomadik SoC include:
 
 S8815 "MiniKit" manufactured by Calao Systems:
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644 (file)
index 0000000..cedc2a9
--- /dev/null
@@ -0,0 +1,49 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+
+The term "wireless" does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+
+The actual devices are instantiated from the child nodes of a WEIM node.
+
+Required properties:
+
+ - compatible:         Should be set to "fsl,imx6q-weim"
+ - reg:                        A resource specifier for the register space
+                       (see the example below)
+ - clocks:             the clock, see the example below.
+ - #address-cells:     Must be set to 2 to allow memory address translation
+ - #size-cells:                Must be set to 1 to allow CS address passing
+ - ranges:             Must be set up to reflect the memory layout with four
+                       integer values for each chip-select line in use:
+
+                          <cs-number> 0 <physical address of mapping> <size>
+
+Timing property for child nodes. It is mandatory, not optional.
+
+ - fsl,weim-cs-timing: The timing array, contains 6 timing values for the
+                       child node. We can get the CS index from the child
+                       node's "reg" property. This property contains the values
+                       for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
+                       EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+
+Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
+
+       weim: weim@021b8000 {
+               compatible = "fsl,imx6q-weim";
+               reg = <0x021b8000 0x4000>;
+               clocks = <&clks 196>;
+               #address-cells = <2>;
+               #size-cells = <1>;
+               ranges = <0 0 0x08000000 0x08000000>;
+
+               nor@0,0 {
+                       compatible = "cfi-flash";
+                       reg = <0 0 0x02000000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       bank-width = <2>;
+                       fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+                                       0x0000c000 0x1404a38e 0x00000000>;
+               };
+       };
index bd0c8416a5c82cbfd6b6c021b73556438bf5caa2..0045433eae1f81ef4b3263ba18fa0e6ec8c018e6 100644 (file)
@@ -9,6 +9,9 @@ Required properties:
        "altr,socfpga-pll-clock" - for a PLL clock
        "altr,socfpga-perip-clock" - The peripheral clock divided from the
                PLL clock.
+       "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+               can get gated.
+
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
        either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
 
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+        and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+        and width.
index d71b4b2c077daa410a53951893229ecbac59a892..f46f5625d8ada4e907474d304a0ebd541f269acc 100644 (file)
@@ -184,6 +184,19 @@ clocks and IDs.
        cko2                    170
        srtc_gate               171
        pata_gate               172
+       sata_gate               173
+       spdif_xtal_sel          174
+       spdif0_sel              175
+       spdif1_sel              176
+       spdif0_pred             177
+       spdif0_podf             178
+       spdif1_pred             179
+       spdif1_podf             180
+       spdif0_com_sel          181
+       spdif1_com_sel          182
+       spdif0_gate             183
+       spdif1_gate             184
+       spdif_ipg_gate          185
 
 Examples (for mx53):
 
index 6deb6fd1c7cd07d718c94c81c13a6ec01f641151..a0e104f0527e058843c1f01a33997ff64d8f37cb 100644 (file)
@@ -208,6 +208,7 @@ clocks and IDs.
        pll4_post_div           193
        pll5_post_div           194
        pll5_video_div          195
+       eim_slow                196
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
new file mode 100644 (file)
index 0000000..15e40bd
--- /dev/null
@@ -0,0 +1,10 @@
+* Clock bindings for Freescale i.MX6 SoloLite
+
+Required properties:
+- compatible: Should be "fsl,imx6sl-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6sl-clock.h
+for the full list of i.MX6 SoloLite clock IDs.
index d6cb083b90a2c5675e42f253982645cf2a16a27d..0c80c267710451918297675c1e47f2020e183cff 100644 (file)
@@ -12,253 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
   the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
-
-  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-
-  0    unassigned
-  1    unassigned
-  2    unassigned
-  3    unassigned
-  4    rtc
-  5    timer
-  6    uarta
-  7    unassigned      (register bit affects uartb and vfir)
-  8    unassigned
-  9    sdmmc2
-  10   unassigned      (register bit affects spdif_in and spdif_out)
-  11   i2s1
-  12   i2c1
-  13   ndflash
-  14   sdmmc1
-  15   sdmmc4
-  16   unassigned
-  17   pwm
-  18   i2s2
-  19   epp
-  20   unassigned      (register bit affects vi and vi_sensor)
-  21   2d
-  22   usbd
-  23   isp
-  24   3d
-  25   unassigned
-  26   disp2
-  27   disp1
-  28   host1x
-  29   vcp
-  30   i2s0
-  31   unassigned
-
-  32   unassigned
-  33   unassigned
-  34   apbdma
-  35   unassigned
-  36   kbc
-  37   unassigned
-  38   unassigned
-  39   unassigned      (register bit affects fuse and fuse_burn)
-  40   kfuse
-  41   sbc1
-  42   nor
-  43   unassigned
-  44   sbc2
-  45   unassigned
-  46   sbc3
-  47   i2c5
-  48   dsia
-  49   unassigned
-  50   mipi
-  51   hdmi
-  52   csi
-  53   unassigned
-  54   i2c2
-  55   uartc
-  56   mipi-cal
-  57   emc
-  58   usb2
-  59   usb3
-  60   msenc
-  61   vde
-  62   bsea
-  63   bsev
-
-  64   unassigned
-  65   uartd
-  66   unassigned
-  67   i2c3
-  68   sbc4
-  69   sdmmc3
-  70   unassigned
-  71   owr
-  72   afi
-  73   csite
-  74   unassigned
-  75   unassigned
-  76   la
-  77   trace
-  78   soc_therm
-  79   dtv
-  80   ndspeed
-  81   i2cslow
-  82   dsib
-  83   tsec
-  84   unassigned
-  85   unassigned
-  86   unassigned
-  87   unassigned
-  88   unassigned
-  89   xusb_host
-  90   unassigned
-  91   msenc
-  92   csus
-  93   unassigned
-  94   unassigned
-  95   unassigned      (bit affects xusb_dev and xusb_dev_src)
-
-  96   unassigned
-  97   unassigned
-  98   unassigned
-  99   mselect
-  100  tsensor
-  101  i2s3
-  102  i2s4
-  103  i2c4
-  104  sbc5
-  105  sbc6
-  106  d_audio
-  107  apbif
-  108  dam0
-  109  dam1
-  110  dam2
-  111  hda2codec_2x
-  112  unassigned
-  113  audio0_2x
-  114  audio1_2x
-  115  audio2_2x
-  116  audio3_2x
-  117  audio4_2x
-  118  spdif_2x
-  119  actmon
-  120  extern1
-  121  extern2
-  122  extern3
-  123  unassigned
-  124  unassigned
-  125  hda
-  126  unassigned
-  127  se
-
-  128  hda2hdmi
-  129  unassigned
-  130  unassigned
-  131  unassigned
-  132  unassigned
-  133  unassigned
-  134  unassigned
-  135  unassigned
-  136  unassigned
-  137  unassigned
-  138  unassigned
-  139  unassigned
-  140  unassigned
-  141  unassigned
-  142  unassigned
-  143  unassigned      (bit affects xusb_falcon_src, xusb_fs_src,
-                        xusb_host_src and xusb_ss_src)
-  144  cilab
-  145  cilcd
-  146  cile
-  147  dsialp
-  148  dsiblp
-  149  unassigned
-  150  dds
-  151  unassigned
-  152  dp2
-  153  amx
-  154  adx
-  155  unassigned      (bit affects dfll_ref and dfll_soc)
-  156  xusb_ss
-
-  192  uartb
-  193  vfir
-  194  spdif_in
-  195  spdif_out
-  196  vi
-  197  vi_sensor
-  198  fuse
-  199  fuse_burn
-  200  clk_32k
-  201  clk_m
-  202  clk_m_div2
-  203  clk_m_div4
-  204  pll_ref
-  205  pll_c
-  206  pll_c_out1
-  207  pll_c2
-  208  pll_c3
-  209  pll_m
-  210  pll_m_out1
-  211  pll_p
-  212  pll_p_out1
-  213  pll_p_out2
-  214  pll_p_out3
-  215  pll_p_out4
-  216  pll_a
-  217  pll_a_out0
-  218  pll_d
-  219  pll_d_out0
-  220  pll_d2
-  221  pll_d2_out0
-  222  pll_u
-  223  pll_u_480M
-  224  pll_u_60M
-  225  pll_u_48M
-  226  pll_u_12M
-  227  pll_x
-  228  pll_x_out0
-  229  pll_re_vco
-  230  pll_re_out
-  231  pll_e_out0
-  232  spdif_in_sync
-  233  i2s0_sync
-  234  i2s1_sync
-  235  i2s2_sync
-  236  i2s3_sync
-  237  i2s4_sync
-  238  vimclk_sync
-  239  audio0
-  240  audio1
-  241  audio2
-  242  audio3
-  243  audio4
-  244  spdif
-  245  clk_out_1
-  246  clk_out_2
-  247  clk_out_3
-  248  blink
-  252  xusb_host_src
-  253  xusb_falcon_src
-  254  xusb_fs_src
-  255  xusb_ss_src
-  256  xusb_dev_src
-  257  xusb_dev
-  258  xusb_hs_src
-  259  sclk
-  260  hclk
-  261  pclk
-  262  cclk_g
-  263  cclk_lp
-  264  dfll_ref
-  265  dfll_soc
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
+  <dt-bindings/clock/tegra114-car.h>.
 
 Example SoC include file:
 
@@ -270,7 +26,7 @@ Example SoC include file:
        };
 
        usb@c5004000 {
-               clocks = <&tegra_car 58>; /* usb2 */
+               clocks = <&tegra_car TEGRA114_CLK_USB2>;
        };
 };
 
index e885680f6b4524116d27331f1c44904c9c082e85..fcfed5bf73fb8ad6c862457165445577bd25694f 100644 (file)
@@ -12,155 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
   the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
-
-  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 95 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-
-  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
-  above.
-
-  0    cpu
-  1    unassigned
-  2    unassigned
-  3    ac97
-  4    rtc
-  5    tmr
-  6    uart1
-  7    unassigned      (register bit affects uart2 and vfir)
-  8    gpio
-  9    sdmmc2
-  10   unassigned      (register bit affects spdif_in and spdif_out)
-  11   i2s1
-  12   i2c1
-  13   ndflash
-  14   sdmmc1
-  15   sdmmc4
-  16   twc
-  17   pwm
-  18   i2s2
-  19   epp
-  20   unassigned      (register bit affects vi and vi_sensor)
-  21   2d
-  22   usbd
-  23   isp
-  24   3d
-  25   ide
-  26   disp2
-  27   disp1
-  28   host1x
-  29   vcp
-  30   unassigned
-  31   cache2
-
-  32   mem
-  33   ahbdma
-  34   apbdma
-  35   unassigned
-  36   kbc
-  37   stat_mon
-  38   pmc
-  39   fuse
-  40   kfuse
-  41   sbc1
-  42   snor
-  43   spi1
-  44   sbc2
-  45   xio
-  46   sbc3
-  47   dvc
-  48   dsi
-  49   unassigned      (register bit affects tvo and cve)
-  50   mipi
-  51   hdmi
-  52   csi
-  53   tvdac
-  54   i2c2
-  55   uart3
-  56   unassigned
-  57   emc
-  58   usb2
-  59   usb3
-  60   mpe
-  61   vde
-  62   bsea
-  63   bsev
-
-  64   speedo
-  65   uart4
-  66   uart5
-  67   i2c3
-  68   sbc4
-  69   sdmmc3
-  70   pcie
-  71   owr
-  72   afi
-  73   csite
-  74   unassigned
-  75   avpucq
-  76   la
-  77   unassigned
-  78   unassigned
-  79   unassigned
-  80   unassigned
-  81   unassigned
-  82   unassigned
-  83   unassigned
-  84   irama
-  85   iramb
-  86   iramc
-  87   iramd
-  88   cram2
-  89   audio_2x        a/k/a audio_2x_sync_clk
-  90   clk_d
-  91   unassigned
-  92   sus
-  93   cdev2
-  94   cdev1
-  95   unassigned
-
-  96   uart2
-  97   vfir
-  98   spdif_in
-  99   spdif_out
-  100  vi
-  101  vi_sensor
-  102  tvo
-  103  cve
-  104  osc
-  105  clk_32k         a/k/a clk_s
-  106  clk_m
-  107  sclk
-  108  cclk
-  109  hclk
-  110  pclk
-  111  blink
-  112  pll_a
-  113  pll_a_out0
-  114  pll_c
-  115  pll_c_out1
-  116  pll_d
-  117  pll_d_out0
-  118  pll_e
-  119  pll_m
-  120  pll_m_out1
-  121  pll_p
-  122  pll_p_out1
-  123  pll_p_out2
-  124  pll_p_out3
-  125  pll_p_out4
-  126  pll_s
-  127  pll_u
-  128  pll_x
-  129  cop             a/k/a avp
-  130  audio           a/k/a audio_sync_clk
-  131  pll_ref
-  132  twd
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
+  <dt-bindings/clock/tegra20-car.h>.
 
 Example SoC include file:
 
@@ -172,7 +26,7 @@ Example SoC include file:
        };
 
        usb@c5004000 {
-               clocks = <&tegra_car 58>; /* usb2 */
+               clocks = <&tegra_car TEGRA20_CLK_USB2>;
        };
 };
 
index f3da3be5fcadc460fdaa84fb172107b7c8111f02..0f714081e986b5c722d29d42a3599bd2399369cc 100644 (file)
@@ -12,212 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
   the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
-
-  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-
-  0    cpu
-  1    unassigned
-  2    unassigned
-  3    unassigned
-  4    rtc
-  5    timer
-  6    uarta
-  7    unassigned      (register bit affects uartb and vfir)
-  8    gpio
-  9    sdmmc2
-  10   unassigned      (register bit affects spdif_in and spdif_out)
-  11   i2s1
-  12   i2c1
-  13   ndflash
-  14   sdmmc1
-  15   sdmmc4
-  16   unassigned
-  17   pwm
-  18   i2s2
-  19   epp
-  20   unassigned      (register bit affects vi and vi_sensor)
-  21   2d
-  22   usbd
-  23   isp
-  24   3d
-  25   unassigned
-  26   disp2
-  27   disp1
-  28   host1x
-  29   vcp
-  30   i2s0
-  31   cop_cache
-
-  32   mc
-  33   ahbdma
-  34   apbdma
-  35   unassigned
-  36   kbc
-  37   statmon
-  38   pmc
-  39   unassigned      (register bit affects fuse and fuse_burn)
-  40   kfuse
-  41   sbc1
-  42   nor
-  43   unassigned
-  44   sbc2
-  45   unassigned
-  46   sbc3
-  47   i2c5
-  48   dsia
-  49   unassigned      (register bit affects cve and tvo)
-  50   mipi
-  51   hdmi
-  52   csi
-  53   tvdac
-  54   i2c2
-  55   uartc
-  56   unassigned
-  57   emc
-  58   usb2
-  59   usb3
-  60   mpe
-  61   vde
-  62   bsea
-  63   bsev
-
-  64   speedo
-  65   uartd
-  66   uarte
-  67   i2c3
-  68   sbc4
-  69   sdmmc3
-  70   pcie
-  71   owr
-  72   afi
-  73   csite
-  74   pciex
-  75   avpucq
-  76   la
-  77   unassigned
-  78   unassigned
-  79   dtv
-  80   ndspeed
-  81   i2cslow
-  82   dsib
-  83   unassigned
-  84   irama
-  85   iramb
-  86   iramc
-  87   iramd
-  88   cram2
-  89   unassigned
-  90   audio_2x        a/k/a audio_2x_sync_clk
-  91   unassigned
-  92   csus
-  93   cdev2
-  94   cdev1
-  95   unassigned
-
-  96   cpu_g
-  97   cpu_lp
-  98   3d2
-  99   mselect
-  100  tsensor
-  101  i2s3
-  102  i2s4
-  103  i2c4
-  104  sbc5
-  105  sbc6
-  106  d_audio
-  107  apbif
-  108  dam0
-  109  dam1
-  110  dam2
-  111  hda2codec_2x
-  112  atomics
-  113  audio0_2x
-  114  audio1_2x
-  115  audio2_2x
-  116  audio3_2x
-  117  audio4_2x
-  118  audio5_2x
-  119  actmon
-  120  extern1
-  121  extern2
-  122  extern3
-  123  sata_oob
-  124  sata
-  125  hda
-  127  se
-  128  hda2hdmi
-  129  sata_cold
-
-  160  uartb
-  161  vfir
-  162  spdif_in
-  163  spdif_out
-  164  vi
-  165  vi_sensor
-  166  fuse
-  167  fuse_burn
-  168  cve
-  169  tvo
-
-  170  clk_32k
-  171  clk_m
-  172  clk_m_div2
-  173  clk_m_div4
-  174  pll_ref
-  175  pll_c
-  176  pll_c_out1
-  177  pll_m
-  178  pll_m_out1
-  179  pll_p
-  180  pll_p_out1
-  181  pll_p_out2
-  182  pll_p_out3
-  183  pll_p_out4
-  184  pll_a
-  185  pll_a_out0
-  186  pll_d
-  187  pll_d_out0
-  188  pll_d2
-  189  pll_d2_out0
-  190  pll_u
-  191  pll_x
-  192  pll_x_out0
-  193  pll_e
-  194  spdif_in_sync
-  195  i2s0_sync
-  196  i2s1_sync
-  197  i2s2_sync
-  198  i2s3_sync
-  199  i2s4_sync
-  200  vimclk
-  201  audio0
-  202  audio1
-  203  audio2
-  204  audio3
-  205  audio4
-  206  audio5
-  207  clk_out_1 (extern1)
-  208  clk_out_2 (extern2)
-  209  clk_out_3 (extern3)
-  210  sclk
-  211  blink
-  212  cclk_g
-  213  cclk_lp
-  214  twd
-  215  cml0
-  216  cml1
-  217  hclk
-  218  pclk
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
+  <dt-bindings/clock/tegra30-car.h>.
 
 Example SoC include file:
 
@@ -229,7 +26,7 @@ Example SoC include file:
        };
 
        usb@c5004000 {
-               clocks = <&tegra_car 58>; /* usb2 */
+               clocks = <&tegra_car TEGRA30_CLK_USB2>;
        };
 };
 
diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt
new file mode 100644 (file)
index 0000000..7fc0977
--- /dev/null
@@ -0,0 +1,104 @@
+ST Microelectronics Nomadik SRC System Reset and Control
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The Nomadik SRC controller is responsible of controlling chrystals,
+PLLs and clock gates.
+
+Required properties for the SRC node:
+- compatible: must be "stericsson,nomadik-src"
+- reg: must contain the SRC register base and size
+
+Optional properties for the SRC node:
+- disable-sxtalo: if present this will disable the SXTALO
+  i.e. the driver output for the slow 32kHz chrystal, if the
+  board has its own circuitry for providing this oscillator
+- disable-mxtal: if present this will disable the MXTALO,
+  i.e. the driver output for the main (~19.2 MHz) chrystal,
+  if the board has its own circuitry for providing this
+  osciallator
+
+
+PLL nodes: these nodes represent the two PLLs on the system,
+which should both have the main chrystal, represented as a
+fixed frequency clock, as parent.
+
+Required properties for the two PLL nodes:
+- compatible: must be "st,nomadik-pll-clock"
+- clock-cells: must be 0
+- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
+- clocks: this clock will have main chrystal as parent
+
+
+HCLK nodes: these represent the clock gates on individual
+lines from the HCLK clock tree and the gate for individual
+lines from the PCLK clock tree.
+
+Requires properties for the HCLK nodes:
+- compatible: must be "st,nomadik-hclk-clock"
+- clock-cells: must be 0
+- clock-id: must be the clock ID from 0 to 63 according to
+  this table:
+
+       0:  HCLKDMA0
+       1:  HCLKSMC
+       2:  HCLKSDRAM
+       3:  HCLKDMA1
+       4:  HCLKCLCD
+       5:  PCLKIRDA
+       6:  PCLKSSP
+       7:  PCLKUART0
+       8:  PCLKSDI
+       9:  PCLKI2C0
+       10: PCLKI2C1
+       11: PCLKUART1
+       12: PCLMSP0
+       13: HCLKUSB
+       14: HCLKDIF
+       15: HCLKSAA
+       16: HCLKSVA
+       17: PCLKHSI
+       18: PCLKXTI
+       19: PCLKUART2
+       20: PCLKMSP1
+       21: PCLKMSP2
+       22: PCLKOWM
+       23: HCLKHPI
+       24: PCLKSKE
+       25: PCLKHSEM
+       26: HCLK3D
+       27: HCLKHASH
+       28: HCLKCRYP
+       29: PCLKMSHC
+       30: HCLKUSBM
+       31: HCLKRNG
+       (32, 33, 34, 35 RESERVED)
+       36: CLDCLK
+       37: IRDACLK
+       38: SSPICLK
+       39: UART0CLK
+       40: SDICLK
+       41: I2C0CLK
+       42: I2C1CLK
+       43: UART1CLK
+       44: MSPCLK0
+       45: USBCLK
+       46: DIFCLK
+       47: IPI2CCLK
+       48: IPBMCCLK
+       49: HSICLKRX
+       50: HSICLKTX
+       51: UART2CLK
+       52: MSPCLK1
+       53: MSPCLK2
+       54: OWMCLK
+       (55 RESERVED)
+       56: SKECLK
+       (57 RESERVED)
+       58: 3DCLK
+       59: PCLKMSP3
+       60: MSPCLK3
+       61: MSHCCLK
+       62: USBMCLK
+       63: RNGCCLK
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
new file mode 100644 (file)
index 0000000..c80863d
--- /dev/null
@@ -0,0 +1,26 @@
+* Clock bindings for Freescale Vybrid VF610 SOC
+
+Required properties:
+- compatible: Should be "fsl,vf610-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
+for the full list of VF610 clock IDs.
+
+Examples:
+
+clks: ccm@4006b000 {
+       compatible = "fsl,vf610-ccm";
+       reg = <0x4006b000 0x1000>;
+       #clock-cells = <1>;
+};
+
+uart1: serial@40028000 {
+       compatible = "fsl,vf610-uart";
+       reg = <0x40028000 0x1000>;
+       interrupts = <0 62 0x04>;
+       clocks = <&clks VF610_CLK_UART1>;
+       clock-names = "ipg";
+};
index 23ae1db1bc13c5a359f9d8a8556d06f49a4a616e..d99af878f5d7db6f59d6160f251edec22d902ed8 100644 (file)
@@ -6,50 +6,99 @@ The purpose of this document is to document their usage.
 See clock_bindings.txt for more information on the generic clock bindings.
 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
 
-== PLLs ==
-
-Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
+== Clock Controller ==
+The clock controller is a logical abstraction of Zynq's clock tree. It reads
+required input clock frequencies from the devicetree and acts as clock provider
+for all clock consumers of PS clocks.
 
 Required properties:
-- #clock-cells : shall be 0 (only one clock is output from this node)
-- compatible : "xlnx,zynq-pll"
-- reg : pair of u32 values, which are the address offsets within the SLCR
-        of the relevant PLL_CTRL register and PLL_CFG register respectively
-- clocks : phandle for parent clock.  should be the phandle for ps_clk
+ - #clock-cells : Must be 1
+ - compatible : "xlnx,ps7-clkc"
+ - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
+                     (usually 33 MHz oscillators are used for Zynq platforms)
+ - clock-output-names : List of strings used to name the clock outputs. Shall be
+                       a list of the outputs given below.
 
 Optional properties:
-- clock-output-names : name of the output clock
-
-Example:
-       armpll: armpll {
-               #clock-cells = <0>;
-               compatible = "xlnx,zynq-pll";
-               clocks = <&ps_clk>;
-               reg = <0x100 0x110>;
-               clock-output-names = "armpll";
-       };
-
-== Peripheral clocks ==
+ - clocks : as described in the clock bindings
+ - clock-names : as described in the clock bindings
 
-Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
+Clock inputs:
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source.
+ - swdt_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - mio_clk_XX          # with XX = 00..53
+...
 
-Required properties:
-- #clock-cells : shall be 1
-- compatible : "xlnx,zynq-periph-clock"
-- reg : a single u32 value, describing the offset within the SLCR where
-        the CLK_CTRL register is found for this peripheral
-- clocks : phandle for parent clocks.  should hold phandles for
-           the IO_PLL, ARM_PLL, and DDR_PLL in order
-- clock-output-names : names of the output clock(s).  For peripherals that have
-                       two output clocks (for example, the UART), two clocks
-                       should be listed.
+Clock outputs:
+ 0:  armpll
+ 1:  ddrpll
+ 2:  iopll
+ 3:  cpu_6or4x
+ 4:  cpu_3or2x
+ 5:  cpu_2x
+ 6:  cpu_1x
+ 7:  ddr2x
+ 8:  ddr3x
+ 9:  dci
+ 10: lqspi
+ 11: smc
+ 12: pcap
+ 13: gem0
+ 14: gem1
+ 15: fclk0
+ 16: fclk1
+ 17: fclk2
+ 18: fclk3
+ 19: can0
+ 20: can1
+ 21: sdio0
+ 22: sdio1
+ 23: uart0
+ 24: uart1
+ 25: spi0
+ 26: spi1
+ 27: dma
+ 28: usb0_aper
+ 29: usb1_aper
+ 30: gem0_aper
+ 31: gem1_aper
+ 32: sdio0_aper
+ 33: sdio1_aper
+ 34: spi0_aper
+ 35: spi1_aper
+ 36: can0_aper
+ 37: can1_aper
+ 38: i2c0_aper
+ 39: i2c1_aper
+ 40: uart0_aper
+ 41: uart1_aper
+ 42: gpio_aper
+ 43: lqspi_aper
+ 44: smc_aper
+ 45: swdt
+ 46: dbg_trc
+ 47: dbg_apb
 
 Example:
-       uart_clk: uart_clk {
+       clkc: clkc {
                #clock-cells = <1>;
-               compatible = "xlnx,zynq-periph-clock";
-               clocks = <&iopll &armpll &ddrpll>;
-               reg = <0x154>;
-               clock-output-names = "uart0_ref_clk",
-                                    "uart1_ref_clk";
+               compatible = "xlnx,ps7-clkc";
+               ps-clk-frequency = <33333333>;
+               clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                               "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                               "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                               "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                               "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                               "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                               "gem1_aper", "sdio0_aper", "sdio1_aper",
+                               "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                               "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                               "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                               "dbg_trc", "dbg_apb";
+               # optional props
+               clocks = <&clkc 16>, <&clk_foo>;
+               clock-names = "gem1_emio_clk", "can_mio_clk_23";
        };
index c3a14e0ad0addf57715902618482a5593344f8da..cd9e90c5d1715b495d03448d35235dddb0b6d051 100644 (file)
@@ -120,7 +120,7 @@ ab8500 {
                                   "USB_LINK_STATUS",
                                   "USB_ADP_PROBE_PLUG",
                                   "USB_ADP_PROBE_UNPLUG";
-                vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
                 v-ape-supply = <&db8500_vape_reg>;
                 musb_1v8-supply = <&db8500_vsmps2_reg>;
         };
index bcfdab5d442ea0808ecba98a3a3306bce885ff54..3a7caf7a744a98d0b08538b157c12441e31d2987 100644 (file)
@@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding:
 
 Examples:
 usdhc@0219c000 { /* uSDHC4 */
-       fsl,card-wired;
+       non-removable;
        vmmc-supply = <&reg_3p3v>;
        status = "okay";
        pinctrl-names = "default";
index 2a3feabd3b224e0a75a2a266cb822052163f9620..34c1505774bfc46fd27ce318aa041fd66dc3a321 100644 (file)
@@ -1,7 +1,7 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
index 34c952883276c32d46cc7643f4e90a482707102b..df0933043a5be46f705a450e3956f92d8ef77600 100644 (file)
@@ -6,27 +6,10 @@ Practice : Universal Serial Bus" with the following modifications
 and additions :
 
 Required properties :
- - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
-   used in host mode.
- - phy_type : Should be one of "ulpi" or "utmi".
- - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
-   activated for the bus to be powered.
- - nvidia,phy : phandle of the PHY instance, the controller is connected to.
-
-Required properties for phy_type == ulpi:
-  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
+ - compatible : Should be "nvidia,tegra20-ehci".
+ - nvidia,phy : phandle of the PHY that the controller is connected to.
+ - clocks : Contains a single entry which defines the USB controller's clock.
 
 Optional properties:
-  - dr_mode : dual role mode. Indicates the working mode for
-   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
-   or "otg".  Default to "host" if not defined for backward compatibility.
-      host means this is a host controller
-      peripheral means it is device controller
-      otg means it can operate as either ("on the go")
-  - nvidia,has-legacy-mode : boolean indicates whether this controller can
-    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
-    registers are accessed through the APB_MISC base address instead of
-    the USB controller. Since this is a legacy issue it probably does not
-    warrant a compatible string of its own.
-  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
-    USB ports, which need reset twice due to hardware issues.
+ - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
+   USB ports, which need reset twice due to hardware issues.
index 6bdaba2f0aa19a5e3c4b6a207a87123f44065382..c4c9e9e664aac3461a378d2ab249ba0ca662b2b2 100644 (file)
@@ -4,14 +4,49 @@ The device node for Tegra SOC USB PHY:
 
 Required properties :
  - compatible : Should be "nvidia,tegra20-usb-phy".
- - reg : Address and length of the register set for the USB PHY interface.
- - phy_type : Should be one of "ulpi" or "utmi".
+ - reg : Defines the following set of registers, in the order listed:
+   - The PHY's own register set.
+     Always present.
+   - The register set of the PHY containing the UTMI pad control registers.
+     Present if-and-only-if phy_type == utmi.
+ - phy_type : Should be one of "utmi", "ulpi" or "hsic".
+ - clocks : Defines the clocks listed in the clock-names property.
+ - clock-names : The following clock names must be present:
+   - reg: The clock needed to access the PHY's own registers. This is the
+     associated EHCI controller's clock. Always present.
+   - pll_u: PLL_U. Always present.
+   - timer: The timeout clock (clk_m). Present if phy_type == utmi.
+   - utmi-pads: The clock needed to access the UTMI pad control registers.
+     Present if phy_type == utmi.
+   - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
+     Present if phy_type == ulpi, and ULPI link mode is in use.
 
 Required properties for phy_type == ulpi:
   - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
 
+Required PHY timing params for utmi phy:
+  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
+    start of sync launches RxActive
+  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
+  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
+    before declare IDLE.
+  - nvidia,term-range-adj : Range adjusment on terminations
+  - nvidia,xcvr-setup : HS driver output control
+  - nvidia,xcvr-lsfslew : LS falling slew rate control.
+  - nvidia,xcvr-lsrslew :  LS rising slew rate control.
+
 Optional properties:
   - nvidia,has-legacy-mode : boolean indicates whether this controller can
     operate in legacy mode (as APX 2500 / 2600). In legacy mode some
     registers are accessed through the APB_MISC base address instead of
-    the USB controller.
\ No newline at end of file
+    the USB controller.
+  - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
+    optimizations for the devices that are always connected. e.g. modem.
+  - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
+    "host", "peripheral", or "otg". Defaults to "host" if not defined.
+      host means this is a host controller
+      peripheral means it is device controller
+      otg means it can operate as either ("on the go")
+
+Required properties for dr_mode == otg:
+  - vbus-supply: regulator for VBUS
index 6e3b18a8afc6a8749d3d91fd559e2bd5c62cadfc..2fe6e767b3d6013f3d1023c2e518b0466fa27e2f 100644 (file)
@@ -3351,9 +3351,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        plus one apbt timer for broadcast timer.
                        x86_mrst_timer=apbt_only | lapic_and_apbt
 
-       xd=             [HW,XT] Original XT pre-IDE (RLL encoded) disks.
-       xd_geo=         See header of drivers/block/xd.c.
-
        xen_emul_unplug=                [HW,X86,XEN]
                        Unplug Xen emulated devices
                        Format: [unplug0,][unplug1]
index 97d45f276fe6e235801b8e1584c9609574d9cc4e..eaf32a1fd0b1095f6c42b707476faf5c1636068c 100644 (file)
@@ -80,8 +80,6 @@ Valid names are:
   /dev/sdd: -> 0x0830 (forth SCSI disk)
   /dev/sde: -> 0x0840 (fifth SCSI disk)
   /dev/fd : -> 0x0200 (floppy disk)
-  /dev/xda: -> 0x0c00 (first XT disk, unused in Linux/m68k)
-  /dev/xdb: -> 0x0c40 (second XT disk, unused in Linux/m68k)
 
   The name must be followed by a decimal number, that stands for the
 partition number. Internally, the value of the number is just
index 250dc970c62d03e59d6053e7ac346a4364f3f600..5be702cc8449d3edb8107256bb03bac25d937238 100644 (file)
@@ -5766,7 +5766,7 @@ M:        Matthew Wilcox <willy@linux.intel.com>
 L:     linux-nvme@lists.infradead.org
 T:     git git://git.infradead.org/users/willy/linux-nvme.git
 S:     Supported
-F:     drivers/block/nvme.c
+F:     drivers/block/nvme*
 F:     include/linux/nvme.h
 
 OMAP SUPPORT
@@ -7624,7 +7624,7 @@ F:        drivers/clk/spear/
 SPI SUBSYSTEM
 M:     Mark Brown <broonie@kernel.org>
 M:     Grant Likely <grant.likely@linaro.org>
-L:     spi-devel-general@lists.sourceforge.net
+L:     linux-spi@vger.kernel.org
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
 Q:     http://patchwork.kernel.org/project/spi-devel-general/list/
 S:     Maintained
@@ -9004,7 +9004,7 @@ S:        Maintained
 F:     drivers/net/wireless/wl3501*
 
 WM97XX TOUCHSCREEN DRIVERS
-M:     Mark Brown <broonie@opensource.wolfsonmicro.com>
+M:     Mark Brown <broonie@kernel.org>
 M:     Liam Girdwood <lrg@slimlogic.co.uk>
 L:     linux-input@vger.kernel.org
 T:     git git://opensource.wolfsonmicro.com/linux-2.6-touch
@@ -9014,7 +9014,6 @@ F:        drivers/input/touchscreen/*wm97*
 F:     include/linux/wm97xx.h
 
 WOLFSON MICROELECTRONICS DRIVERS
-M:     Mark Brown <broonie@opensource.wolfsonmicro.com>
 L:     patches@opensource.wolfsonmicro.com
 T:     git git://opensource.wolfsonmicro.com/linux-2.6-asoc
 T:     git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
index 90400165125e4adc85ac9d757dfa5b73c190b6c8..c6863b55f7c7a48d53338d51d6c5a6b711cbadc1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 10
 SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Unicycling Gorilla
 
 # *DOCUMENTATION*
index 1d41908d5cda0644a31a9048c882369f21db235b..29f7623553c195703e0cd1a610cb5ec4165c4ae1 100644 (file)
@@ -251,6 +251,13 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX6Q/DL.
 
+       config DEBUG_IMX6SL_UART
+               bool "i.MX6SL Debug UART"
+               depends on SOC_IMX6SL
+               help
+                 Say Y here if you want kernel low-level debugging support
+                 on i.MX6SL.
+
        config DEBUG_MMP_UART2
                bool "Kernel low-level debugging message via MMP UART2"
                depends on ARCH_MMP
@@ -532,7 +539,8 @@ config DEBUG_IMX_UART_PORT
                                                DEBUG_IMX35_UART || \
                                                DEBUG_IMX51_UART || \
                                                DEBUG_IMX53_UART || \
-                                               DEBUG_IMX6Q_UART
+                                               DEBUG_IMX6Q_UART || \
+                                               DEBUG_IMX6SL_UART
        default 1
        depends on ARCH_MXC
        help
@@ -631,7 +639,8 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX35_UART || \
                                 DEBUG_IMX51_UART || \
                                 DEBUG_IMX53_UART ||\
-                                DEBUG_IMX6Q_UART
+                                DEBUG_IMX6Q_UART || \
+                                DEBUG_IMX6SL_UART
        default "debug/mvebu.S" if DEBUG_MVEBU_UART
        default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
        default "debug/nomadik.S" if DEBUG_NOMADIK_UART
index 3580d57ea21841285bc687d928f39268a325edc1..79e9bdbfc491a29521939aa2747862fc491c6d6d 100644 (file)
@@ -124,7 +124,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
index 6e8382d5b7a4d31418a934565a473b823ffe5b6f..5392ee63338fac3453f30b125366e03241158133 100644 (file)
@@ -1,6 +1,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#ifndef CONFIG_DEBUG_SEMIHOSTING
+
 #include CONFIG_DEBUG_LL_INCLUDE
 
 ENTRY(putc)
@@ -10,3 +12,29 @@ ENTRY(putc)
        busyuart r3, r1
        mov      pc, lr
 ENDPROC(putc)
+
+#else
+
+ENTRY(putc)
+       adr     r1, 1f
+       ldmia   r1, {r2, r3}
+       add     r2, r2, r1
+       ldr     r1, [r2, r3]
+       strb    r0, [r1]
+       mov     r0, #0x03               @ SYS_WRITEC
+   ARM(        svc     #0x123456       )
+ THUMB(        svc     #0xab           )
+       mov     pc, lr
+       .align  2
+1:     .word   _GLOBAL_OFFSET_TABLE_ - .
+       .word   semi_writec_buf(GOT)
+ENDPROC(putc)
+
+       .bss
+       .global semi_writec_buf
+       .type   semi_writec_buf, %object
+semi_writec_buf:
+       .space  4
+       .size   semi_writec_buf, 4
+
+#endif
index 6179d94dd5c665a634e5e2913a916c96c9652c84..3115e313d9f65a31ad746b7d8d282741a5b1f765 100644 (file)
@@ -11,6 +11,7 @@
 #include <asm/mach-types.h>
 
                .section        ".start", "ax"
+               .arch   armv4
 
 __SA1100_start:
 
index 089c560e07f13947ed68ab446edcc9de40c30604..92b56897ed64014037b48eb0e677bb633d646be1 100644 (file)
@@ -18,6 +18,7 @@
        
                .section        ".start", "ax"
 
+               .arch armv4
                b       __beginning
        
 __ofw_data:    .long   0                               @ the number of memory blocks
index fe4d9c3ad761c8dfaadce6e214d709417947f396..032a8d987148b6a24c97d7ec05467bef14b82ab0 100644 (file)
@@ -11,6 +11,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+       .arch   armv7-a
 /*
  * Debugging stuff
  *
@@ -805,8 +806,8 @@ call_cache_fn:      adr     r12, proc_types
                .align  2
                .type   proc_types,#object
 proc_types:
-               .word   0x00000000              @ old ARM ID
-               .word   0x0000f000
+               .word   0x41000000              @ old ARM ID
+               .word   0xff00f000
                mov     pc, lr
  THUMB(                nop                             )
                mov     pc, lr
index f0895c581a89be8668a99db10e6873ae94be0cef..242a4937fe6f7347ef8c93f453988878e09eec74 100644 (file)
@@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
 # sam9g20
+dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
 dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
 # sam9g45
 dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
@@ -84,6 +86,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
        kirkwood-ns2max.dtb \
        kirkwood-ns2mini.dtb \
        kirkwood-nsa310.dtb \
+       kirkwood-sheevaplug.dtb \
+       kirkwood-sheevaplug-esata.dtb \
        kirkwood-topkick.dtb \
        kirkwood-ts219-6281.dtb \
        kirkwood-ts219-6282.dtb \
@@ -103,13 +107,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx27-apf27.dtb \
        imx27-apf27dev.dtb \
        imx27-pdk.dtb \
-       imx27-phytec-phycore.dtb \
+       imx27-phytec-phycore-som.dtb \
+       imx27-phytec-phycore-rdk.dtb \
        imx31-bug.dtb \
        imx51-apf51.dtb \
        imx51-apf51dev.dtb \
        imx51-babbage.dtb \
        imx53-ard.dtb \
        imx53-evk.dtb \
+       imx53-m53evk.dtb \
        imx53-mba53.dtb \
        imx53-qsb.dtb \
        imx53-smd.dtb \
@@ -117,10 +123,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx6dl-sabresd.dtb \
        imx6dl-wandboard.dtb \
        imx6q-arm2.dtb \
+       imx6q-phytec-pbab01.dtb \
        imx6q-sabreauto.dtb \
        imx6q-sabrelite.dtb \
        imx6q-sabresd.dtb \
-       imx6q-sbc6x.dtb
+       imx6q-sbc6x.dtb \
+       imx6sl-evk.dtb \
+       vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx23-olinuxino.dtb \
        imx23-stmp378x_devb.dtb \
@@ -130,6 +139,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx28-cfa10036.dtb \
        imx28-cfa10037.dtb \
        imx28-cfa10049.dtb \
+       imx28-cfa10055.dtb \
+       imx28-cfa10057.dtb \
        imx28-evk.dtb \
        imx28-m28evk.dtb \
        imx28-sps1.dtb \
@@ -158,10 +169,13 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
        hrefprev60.dtb \
        hrefv60plus.dtb \
+       ccu8540.dtb \
        ccu9540.dtb
+dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
        r8a7740-armadillo800eva.dtb \
        r8a7778-bockw.dtb \
+       r8a7740-armadillo800eva-reference.dtb \
        r8a7779-marzen-reference.dtb \
        r8a7790-lager.dtb \
        sh73a0-kzm9g.dtb \
@@ -181,6 +195,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
        sun4i-a10-cubieboard.dtb \
        sun4i-a10-mini-xplus.dtb \
        sun4i-a10-hackberry.dtb \
+       sun5i-a10s-olinuxino-micro.dtb \
        sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra20-iris-512.dtb \
@@ -207,8 +222,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
        wm8505-ref.dtb \
        wm8650-mid.dtb \
+       wm8750-apc8750.dtb \
        wm8850-w70v2.dtb
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
+       zynq-zc706.dtb \
+       zynq-zed.dtb
 
 targets += dtbs
 targets += $(dtb-y)
index 29b9f15e7599571b920285772f37c63d69f6b40d..54cb5cf8604aaeb2a164155ea40a651a47690e8c 100644 (file)
@@ -9,7 +9,7 @@
 
 /dts-v1/;
 
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 
 / {
        chosen {
@@ -46,7 +46,7 @@
                        };
 
                        usb1: gadget@fffa4000 {
-                               atmel,vbus-gpio = <&pioC 15 0>;
+                               atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
                };
                compatible = "gpio-leds";
 
                red {
-                       gpios = <&pioC 10 0>;
+                       gpios = <&pioC 10 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "none";
                };
 
                green {
-                       gpios = <&pioA 5 1>;
+                       gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                        default-state = "on";
                };
 
                yellow {
-                       gpios = <&pioB 20 1>;
+                       gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
 
                blue {
-                       gpios = <&pioB 21 1>;
+                       gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
        };
index 1460d9b88adfee928d8c150ae56812abbb2b2d28..27c99c106620c9c4ac1d6965878e9d87b16b2166 100644 (file)
        };
 
        cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
                cpu@0 {
                        compatible = "arm,cortex-a8";
+                       device_type = "cpu";
+                       reg = <0>;
 
                        /*
                         * To consider voltage drop between PMIC and SoC,
                        ti,hwmods = "gpmc";
                        reg = <0x50000000 0x2000>;
                        interrupts = <100>;
-                       num-cs = <7>;
-                       num-waitpins = <2>;
+                       gpmc,num-cs = <7>;
+                       gpmc,num-waitpins = <2>;
                        #address-cells = <2>;
                        #size-cells = <1>;
                        status = "disabled";
index 5160210f74da8c1f588c42b83e86194082022b83..3a1de9eb51112f2eb0c6eb00b5b20026985800b5 100644 (file)
@@ -7,7 +7,7 @@
  */
 
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
        model = "Somfy Animeo IP";
 
                usb0: ohci@00500000 {
                        num-ports = <2>;
-                       atmel,vbus-gpio = <&pioB 15 1>;
+                       atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
                        status = "okay";
                };
        };
 
                power_green {
                        label = "power_green";
-                       gpios = <&pioC 17 0>;
+                       gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
 
                power_red {
                        label = "power_red";
-                       gpios = <&pioA 2 0>;
+                       gpios = <&pioA 2 GPIO_ACTIVE_HIGH>;
                };
 
                tx_green {
                        label = "tx_green";
-                       gpios = <&pioC 19 0>;
+                       gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
                };
 
                tx_red {
                        label = "tx_red";
-                       gpios = <&pioC 18 0>;
+                       gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
                };
        };
 
 
                keyswitch_in {
                        label = "keyswitch_in";
-                       gpios = <&pioB 1 0>;
+                       gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
                        linux,code = <28>;
                        gpio-key,wakeup;
                };
 
                error_in {
                        label = "error_in";
-                       gpios = <&pioB 2 0>;
+                       gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
                        linux,code = <29>;
                        gpio-key,wakeup;
                };
 
                btn {
                        label = "btn";
-                       gpios = <&pioC 23 0>;
+                       gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
                        linux,code = <31>;
                        gpio-key,wakeup;
                };
index 2353b1f13704b66e39284757b5442f5256bf01ba..beee1699d49eb553a474a9186b508b6fb1da4230 100644 (file)
@@ -74,6 +74,7 @@
                                 */
                                status = "disabled";
                                /* No CD or WP GPIOs */
+                               broken-cd;
                        };
 
                        usb@50000 {
index 14e36e19d5152caedc8e8056a723fa885c3495ce..45b107763e3b7c88f1632ef8bf00adb6027258b5 100644 (file)
@@ -99,6 +99,7 @@
                                 * No CD or WP GPIOs: SDIO interface used for
                                 * Wifi/Bluetooth chip
                                 */
+                                broken-cd;
                        };
 
                        usb@50000 {
index 130f8390a7e42d2f1e92057399cd6a6f54183cdc..89c21106cfa93de89fac1c9209efff44dad2ef06 100644 (file)
@@ -64,6 +64,7 @@
                                pinctrl-names = "default";
                                status = "okay";
                                /* No CD or WP GPIOs */
+                               broken-cd;
                        };
 
                        usb@50000 {
index 550eb772c30e4c47c2f7f0896469a033dee3e23b..a679b6697a981c69b962784a752a128166fb7769 100644 (file)
        model = "Marvell Armada 370 and XP SoC";
        compatible = "marvell,armada-370-xp";
 
+       aliases {
+               eth0 = &eth0;
+               eth1 = &eth1;
+       };
+
        cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
                cpu@0 {
                        compatible = "marvell,sheeva-v7";
+                       device_type = "cpu";
+                       reg = <0>;
                };
        };
 
                                reg = <0x72004 0x4>;
                        };
 
-                       ethernet@70000 {
+                       eth0: ethernet@70000 {
                                compatible = "marvell,armada-370-neta";
                                reg = <0x70000 0x2500>;
                                interrupts = <8>;
                                status = "disabled";
                        };
 
-                       ethernet@74000 {
+                       eth1: ethernet@74000 {
                                compatible = "marvell,armada-370-neta";
                                reg = <0x74000 0x2500>;
                                interrupts = <10>;
                                reg = <0xd4000 0x200>;
                                interrupts = <54>;
                                clocks = <&gateclk 17>;
+                               bus-width = <4>;
+                               cap-sdio-irq;
+                               cap-sd-highspeed;
+                               cap-mmc-highspeed;
                                status = "disabled";
                        };
 
index aee2b1866ce2ede35fbd58a6bbea1e29ac6b16ea..fa3dfc6b4c6a88c27d459f7587df7f334d1cd386 100644 (file)
 
                                bus-range = <0x00 0xff>;
 
-                               reg = <0x40000 0x2000>, <0x80000 0x2000>;
-
-                               reg-names = "pcie0.0", "pcie1.0";
-
                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
index d6cc8bf8272e387281c30a0130914c1e961fa69f..e28e68ff864dbd40c2aca2a00d25e74cc0f70137 100644 (file)
        };
 
        soc {
+               ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                         0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                         0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
+
                internal-regs {
                        serial@12000 {
                                clock-frequency = <250000000>;
                                pinctrl-names = "default";
                                status = "okay";
                                /* No CD or WP GPIOs */
+                               broken-cd;
                        };
 
                        usb@50000 {
                                        status = "okay";
                                };
                        };
+
+                       devbus-bootcs@10400 {
+                               status = "okay";
+                               ranges = <0 0xf0000000 0x1000000>;
+
+                               /* Device Bus parameters are required */
+
+                               /* Read parameters */
+                               devbus,bus-width    = <8>;
+                               devbus,turn-off-ps  = <60000>;
+                               devbus,badr-skew-ps = <0>;
+                               devbus,acc-first-ps = <124000>;
+                               devbus,acc-next-ps  = <248000>;
+                               devbus,rd-setup-ps  = <0>;
+                               devbus,rd-hold-ps   = <0>;
+
+                               /* Write parameters */
+                               devbus,sync-enable = <0>;
+                               devbus,wr-high-ps  = <60000>;
+                               devbus,wr-low-ps   = <60000>;
+                               devbus,ale-wr-ps   = <60000>;
+
+                               /* NOR 16 MiB */
+                               nor@0 {
+                                       compatible = "cfi-flash";
+                                       reg = <0 0x1000000>;
+                                       bank-width = <2>;
+                               };
+                       };
                };
        };
 };
index 3ee63d128e27cf27b3c8f6c5211bcf05b6dadc9e..c87b2de29c30161a1c032c21d80c07c422ecb2f6 100644 (file)
@@ -39,8 +39,9 @@
        };
 
        soc {
-               ranges = <0          0 0xd0000000 0x100000
-                         0xf0000000 0 0xf0000000 0x1000000>;
+               ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
+                         0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
+                         0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
 
                internal-regs {
                        serial@12000 {
                                phy-mode = "rgmii-id";
                        };
 
+                       /* Front-side USB slot */
+                       usb@50000 {
+                               status = "okay";
+                       };
+
+                       /* Back-side USB slot */
+                       usb@51000 {
+                               status = "okay";
+                       };
+
                        spi0: spi@10600 {
                                status = "okay";
 
index 6ab56bd35de926aaab239966f87bb78b193dac2d..386f0ce48453361aaceede735d9bf4acf6cfeb6a 100644 (file)
@@ -23,6 +23,7 @@
                gpio0 = &gpio0;
                gpio1 = &gpio1;
                gpio2 = &gpio2;
+               eth3 = &eth3;
        };
 
 
                                interrupts = <91>;
                        };
 
-                       ethernet@34000 {
+                       eth3: ethernet@34000 {
                                compatible = "marvell,armada-370-neta";
                                reg = <0x34000 0x2500>;
                                interrupts = <14>;
index 46b785064dd869917afa981103136459a5826922..8f510458ea863150575213056e333fe90e2ccb81 100644 (file)
@@ -27,8 +27,9 @@
        };
 
        soc {
-               ranges = <0          0 0xd0000000 0x100000
-                         0xf0000000 0 0xf0000000 0x8000000>;
+               ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                         0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                         0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
 
                internal-regs {
                        serial@12000 {
                                nr-ports = <2>;
                                status = "okay";
                        };
+
+                       /* Front side USB 0 */
                        usb@50000 {
                                status = "okay";
                        };
+
+                       /* Front side USB 1 */
                        usb@51000 {
                                status = "okay";
                        };
 
+                       /* USB interface in the mini-PCIe connector */
+                       usb@52000 {
+                               status = "okay";
+                       };
+
                        devbus-bootcs@10400 {
                                status = "okay";
                                ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
index 5b902f9a3af29a84fd0ee83000c8d0f2ffa280ea..e481d54b565cf8296a103c73d79439a06b7e4cd9 100644 (file)
        model = "Marvell Armada XP family SoC";
        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+       aliases {
+               eth2 = &eth2;
+       };
+
        soc {
                internal-regs {
                        L2: l2-cache {
@@ -86,7 +90,7 @@
                                reg = <0x18200 0x500>;
                        };
 
-                       ethernet@30000 {
+                       eth2: ethernet@30000 {
                                compatible = "marvell,armada-370-neta";
                                reg = <0x30000 0x2500>;
                                interrupts = <12>;
index c7aebba4e8e737a28e884e1700894577160faf92..cce45f5177f9f0aef6b40e0e775617f47398c48e 100644 (file)
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
+#include "at91sam9g25.dtsi"
 
 / {
        model = "Acme Systems Aria G25";
@@ -21,6 +21,7 @@
                serial3 = &usart2;
                serial4 = &usart3;
                serial5 = &uart0;
+               serial6 = &uart1;
        };
 
        chosen {
                                status = "okay";
                        };
 
+                       /*
+                        * UART0/1 pins are marked as GPIO on
+                        * Aria documentation.
+                        * Change to "okay" if you need additional serial ports
+                        */
                        uart0: serial@f8040000 {
-                               compatible = "atmel,at91sam9260-usart";
-                               reg = <0xf8040000 0x200>;
-                               interrupts = <15 4 5>;
-                               pinctrl-names = "default";
-                               pinctrl-0 = <&pinctrl_uart0>;
-                               status = "okay";
+                               status = "disabled";
+                       };
+
+                       uart1: serial@f8044000 {
+                               status = "disabled";
                        };
 
                        adc0: adc@f804c000 {
                                        };
                                };
                        };
+
+                       rtc@fffffeb0 {
+                               status = "okay";
+                       };
                };
 
                usb0: ohci@00600000 {
                /* little green LED in middle of Aria G25 module */
                aria_led {
                        label = "aria_led";
-                       gpios = <&pioB 8 0>; /* PB8 */
+                       gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
                        linux,default-trigger = "heartbeat";
                };
 
 
        onewire@0 {
                compatible = "w1-gpio";
-               gpios = <&pioA 21 1>;
+               gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_w1_0>;
        };
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
new file mode 100644 (file)
index 0000000..cbe9673
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
+ *
+ * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC)
+ *
+ * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+       model = "Acme Systems FoxG20";
+       compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+       chosen {
+               bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+       };
+
+       memory {
+               reg = <0x20000000 0x4000000>;
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               main_clock: clock@0 {
+                       compatible = "atmel,osc", "fixed-clock";
+                       clock-frequency = <18432000>;
+               };
+       };
+
+       ahb {
+               apb {
+                       usb1: gadget@fffa4000 {
+                               atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
+                               status = "okay";
+                       };
+
+                       mmc0: mmc@fffa8000 {
+                               pinctrl-0 = <
+                                       &pinctrl_mmc0_clk
+                                       &pinctrl_mmc0_slot1_cmd_dat0
+                                       &pinctrl_mmc0_slot1_dat1_3>;
+                               status = "okay";
+
+                               slot@1 {
+                                       reg = <1>;
+                                       bus-width = <4>;
+                               };
+                       };
+
+                       usart0: serial@fffb0000 {
+                               pinctrl-0 =
+                                       <&pinctrl_usart0
+                                        &pinctrl_usart0_rts
+                                        &pinctrl_usart0_cts
+                                       >;
+                               status = "okay";
+                       };
+
+                       usart1: serial@fffb4000 {
+                               status = "okay";
+                       };
+
+                       usart2: serial@fffb8000 {
+                               status = "okay";
+                       };
+
+                       macb0: ethernet@fffc4000 {
+                               phy-mode = "rmii";
+                               status = "okay";
+                       };
+
+                       usart3: serial@fffd0000 {
+                               status = "okay";
+                       };
+
+                       uart0: serial@fffd4000 {
+                               status = "okay";
+                       };
+
+                       uart1: serial@fffd8000 {
+                               status = "okay";
+                       };
+
+                       dbgu: serial@fffff200 {
+                               status = "okay";
+                       };
+
+                       pinctrl@fffff400 {
+                               board {
+                                       pinctrl_pck0_as_mck: pck0_as_mck {
+                                               atmel,pins =
+                                                       <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+                               };
+
+                               mmc0_slot1 {
+                                       pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                               atmel,pins =
+                                                       <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* CD pin */
+                                       };
+                               };
+
+                               i2c0 {
+                                       pinctrl_i2c0: i2c0-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* TWD (SDA), open drain */
+                                                        AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* TWCK (SCL), open drain */
+                                       };
+                               };
+                       };
+
+                       watchdog@fffffd40 {
+                               status = "okay";
+                       };
+               };
+
+               usb0: ohci@00500000 {
+                       num-ports = <2>;
+                       status = "okay";
+               };
+       };
+
+       i2c@0 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_i2c0>;
+               i2c-gpio,delay-us = <5>;        /* ~85 kHz */
+               status = "okay";
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               /* red LED marked "PC7" near mini USB (device) receptacle */
+               user_led {
+                       label = "user_led";
+                       gpios = <&pioC 7 GPIO_ACTIVE_HIGH>;     /* PC7 */
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       gpio_keys {
+               compatible = "gpio-keys";
+
+               btn {
+                       label = "Button";
+                       gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
+                       linux,code = <0x103>;
+                       gpio-key,wakeup;
+               };
+       };
+};
index 5d3ed5aafc699b071f6a1044ed9cb4948d6ee726..34c03806fe061b2828f7398b5b67ade8b3d5c0f2 100644 (file)
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
        model = "Atmel AT91RM9200 family SoC";
                ssc2 = &ssc2;
        };
        cpus {
-               cpu@0 {
+               #address-cells = <0>;
+               #size-cells = <0>;
+
+               cpu {
                        compatible = "arm,arm920t";
+                       device_type = "cpu";
                };
        };
 
                        st: timer@fffffd00 {
                                compatible = "atmel,at91rm9200-st";
                                reg = <0xfffffd00 0x100>;
-                               interrupts = <1 4 7>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
 
                        tcb0: timer@fffa0000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffa0000 0x100>;
-                               interrupts = <17 4 0 18 4 0 19 4 0>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+                                             18 IRQ_TYPE_LEVEL_HIGH 0
+                                             19 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
 
                        tcb1: timer@fffa4000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffa4000 0x100>;
-                               interrupts = <20 4 0 21 4 0 22 4 0>;
+                               interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
+                                             21 IRQ_TYPE_LEVEL_HIGH 0
+                                             22 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
 
                        i2c0: i2c@fffb8000 {
                                compatible = "atmel,at91rm9200-i2c";
                                reg = <0xfffb8000 0x4000>;
-                               interrupts = <12 4 6>;
+                               interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_twi>;
                                #address-cells = <1>;
                        mmc0: mmc@fffb4000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfffb4000 0x4000>;
-                               interrupts = <10 4 0>;
+                               interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
                        ssc0: ssc@fffd0000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffd0000 0x4000>;
-                               interrupts = <14 4 5>;
+                               interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disable";
                        ssc1: ssc@fffd4000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffd4000 0x4000>;
-                               interrupts = <15 4 5>;
+                               interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                status = "disable";
                        ssc2: ssc@fffd8000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffd8000 0x4000>;
-                               interrupts = <16 4 5>;
+                               interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
                                status = "disable";
                        macb0: ethernet@fffbc000 {
                                compatible = "cdns,at91rm9200-emac", "cdns,emac";
                                reg = <0xfffbc000 0x4000>;
-                               interrupts = <24 4 3>;
+                               interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
                                phy-mode = "rmii";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                       <0 30 0x1 0x0   /* PA30 periph A */
-                                                        0 31 0x1 0x1>; /* PA31 periph with pullup */
+                                                       <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A */
+                                                        AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA31 periph with pullup */
                                        };
                                };
 
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                       <0 17 0x1 0x0   /* PA17 periph A */
-                                                        0 18 0x1 0x0>; /* PA18 periph A */
+                                                       <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                        AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
                                        };
 
                                        pinctrl_uart0_rts: uart0_rts-0 {
                                                atmel,pins =
-                                                       <0 20 0x1 0x0>; /* PA20 periph A */
+                                                       <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
                                        };
 
                                        pinctrl_uart0_cts: uart0_cts-0 {
                                                atmel,pins =
-                                                       <0 21 0x1 0x0>; /* PA21 periph A */
+                                                       <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                        };
                                };
 
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                       <1 20 0x1 0x1   /* PB20 periph A with pullup */
-                                                        1 21 0x1 0x0>; /* PB21 periph A */
+                                                       <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB20 periph A with pullup */
+                                                        AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
                                        };
 
                                        pinctrl_uart1_rts: uart1_rts-0 {
                                                atmel,pins =
-                                                       <1 24 0x1 0x0>; /* PB24 periph A */
+                                                       <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
                                        };
 
                                        pinctrl_uart1_cts: uart1_cts-0 {
                                                atmel,pins =
-                                                       <1 26 0x1 0x0>; /* PB26 periph A */
+                                                       <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
                                        };
 
                                        pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
                                                atmel,pins =
-                                                       <1 19 0x1 0x0   /* PB19 periph A */
-                                                        1 25 0x1 0x0>; /* PB25 periph A */
+                                                       <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB19 periph A */
+                                                        AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
                                        };
 
                                        pinctrl_uart1_dcd: uart1_dcd-0 {
                                                atmel,pins =
-                                                       <1 23 0x1 0x0>; /* PB23 periph A */
+                                                       <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
                                        };
 
                                        pinctrl_uart1_ri: uart1_ri-0 {
                                                atmel,pins =
-                                                       <1 18 0x1 0x0>; /* PB18 periph A */
+                                                       <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                        };
                                };
 
                                uart2 {
                                        pinctrl_uart2: uart2-0 {
                                                atmel,pins =
-                                                       <0 22 0x1 0x0   /* PA22 periph A */
-                                                        0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                                       <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA22 periph A */
+                                                        AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
                                        };
 
                                        pinctrl_uart2_rts: uart2_rts-0 {
                                                atmel,pins =
-                                                       <0 30 0x2 0x0>; /* PA30 periph B */
+                                                       <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                        };
 
                                        pinctrl_uart2_cts: uart2_cts-0 {
                                                atmel,pins =
-                                                       <0 31 0x2 0x0>; /* PA31 periph B */
+                                                       <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
                                        };
                                };
 
                                uart3 {
                                        pinctrl_uart3: uart3-0 {
                                                atmel,pins =
-                                                       <0 5 0x2 0x1    /* PA5 periph B with pullup */
-                                                        0 6 0x2 0x0>;  /* PA6 periph B */
+                                                       <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
+                                                        AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PA6 periph B */
                                        };
 
                                        pinctrl_uart3_rts: uart3_rts-0 {
                                                atmel,pins =
-                                                       <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                       <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                        };
 
                                        pinctrl_uart3_cts: uart3_cts-0 {
                                                atmel,pins =
-                                                       <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                       <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                        };
                                };
 
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                       <2 2 0x0 0x1    /* PC2 gpio RDY pin pull_up */
-                                                        1 1 0x0 0x1>;  /* PB1 gpio CD pin pull_up */
+                                                       <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PC2 gpio RDY pin pull_up */
+                                                        AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;    /* PB1 gpio CD pin pull_up */
                                        };
                                };
 
                                macb {
                                        pinctrl_macb_rmii: macb_rmii-0 {
                                                atmel,pins =
-                                                       <0 7 0x1 0x0    /* PA7 periph A */
-                                                        0 8 0x1 0x0    /* PA8 periph A */
-                                                        0 9 0x1 0x0    /* PA9 periph A */
-                                                        0 10 0x1 0x0   /* PA10 periph A */
-                                                        0 11 0x1 0x0   /* PA11 periph A */
-                                                        0 12 0x1 0x0   /* PA12 periph A */
-                                                        0 13 0x1 0x0   /* PA13 periph A */
-                                                        0 14 0x1 0x0   /* PA14 periph A */
-                                                        0 15 0x1 0x0   /* PA15 periph A */
-                                                        0 16 0x1 0x0>; /* PA16 periph A */
+                                                       <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A */
+                                                        AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A */
+                                                        AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
+                                                        AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A */
+                                                        AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A */
+                                                        AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
+                                                        AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
+                                                        AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
+                                                        AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
+                                                        AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
                                        };
 
                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                atmel,pins =
-                                                       <1 12 0x2 0x0   /* PB12 periph B */
-                                                        1 13 0x2 0x0   /* PB13 periph B */
-                                                        1 14 0x2 0x0   /* PB14 periph B */
-                                                        1 15 0x2 0x0   /* PB15 periph B */
-                                                        1 16 0x2 0x0   /* PB16 periph B */
-                                                        1 17 0x2 0x0   /* PB17 periph B */
-                                                        1 18 0x2 0x0   /* PB18 periph B */
-                                                        1 19 0x2 0x0>; /* PB19 periph B */
+                                                       <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB12 periph B */
+                                                        AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB13 periph B */
+                                                        AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB14 periph B */
+                                                        AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB15 periph B */
+                                                        AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB16 periph B */
+                                                        AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB17 periph B */
+                                                        AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB18 periph B */
+                                                        AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
                                        };
                                };
 
                                mmc0 {
                                        pinctrl_mmc0_clk: mmc0_clk-0 {
                                                atmel,pins =
-                                                       <0 27 0x1 0x0>; /* PA27 periph A */
+                                                       <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
                                        };
 
                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                atmel,pins =
-                                                       <0 28 0x1 0x1   /* PA28 periph A with pullup */
-                                                        0 29 0x1 0x1>; /* PA29 periph A with pullup */
+                                                       <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA28 periph A with pullup */
+                                                        AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA29 periph A with pullup */
                                        };
 
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                       <1 3 0x2 0x1    /* PB3 periph B with pullup */
-                                                        1 4 0x2 0x1    /* PB4 periph B with pullup */
-                                                        1 5 0x2 0x1>;  /* PB5 periph B with pullup */
+                                                       <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
+                                                        AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
+                                                        AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PB5 periph B with pullup */
                                        };
 
                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                atmel,pins =
-                                                       <0 8 0x2 0x1    /* PA8 periph B with pullup */
-                                                        0 9 0x2 0x1>;  /* PA9 periph B with pullup */
+                                                       <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
+                                                        AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA9 periph B with pullup */
                                        };
 
                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                atmel,pins =
-                                                       <0 10 0x2 0x1   /* PA10 periph B with pullup */
-                                                        0 11 0x2 0x1   /* PA11 periph B with pullup */
-                                                        0 12 0x2 0x1>; /* PA12 periph B with pullup */
+                                                       <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA10 periph B with pullup */
+                                                        AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA11 periph B with pullup */
+                                                        AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA12 periph B with pullup */
                                        };
                                };
 
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                       <1 0 0x1 0x0    /* PB0 periph A */
-                                                        1 1 0x1 0x0    /* PB1 periph A */
-                                                        1 2 0x1 0x0>;  /* PB2 periph A */
+                                                       <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
+                                                        AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
+                                                        AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A */
                                        };
 
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                       <1 3 0x1 0x0    /* PB3 periph A */
-                                                        1 4 0x1 0x0    /* PB4 periph A */
-                                                        1 5 0x1 0x0>;  /* PB5 periph A */
+                                                       <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
+                                                        AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                        AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                        };
                                };
 
                                ssc1 {
                                        pinctrl_ssc1_tx: ssc1_tx-0 {
                                                atmel,pins =
-                                                       <1 6 0x1 0x0    /* PB6 periph A */
-                                                        1 7 0x1 0x0    /* PB7 periph A */
-                                                        1 8 0x1 0x0>;  /* PB8 periph A */
+                                                       <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                        AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                        AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                        };
 
                                        pinctrl_ssc1_rx: ssc1_rx-0 {
                                                atmel,pins =
-                                                       <1 9 0x1 0x0    /* PB9 periph A */
-                                                        1 10 0x1 0x0   /* PB10 periph A */
-                                                        1 11 0x1 0x0>; /* PB11 periph A */
+                                                       <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                        AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A */
+                                                        AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                        };
                                };
 
                                ssc2 {
                                        pinctrl_ssc2_tx: ssc2_tx-0 {
                                                atmel,pins =
-                                                       <1 12 0x1 0x0   /* PB12 periph A */
-                                                        1 13 0x1 0x0   /* PB13 periph A */
-                                                        1 14 0x1 0x0>; /* PB14 periph A */
+                                                       <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                        AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
+                                                        AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
                                        };
 
                                        pinctrl_ssc2_rx: ssc2_rx-0 {
                                                atmel,pins =
-                                                       <1 15 0x1 0x0   /* PB15 periph A */
-                                                        1 16 0x1 0x0   /* PB16 periph A */
-                                                        1 17 0x1 0x0>; /* PB17 periph A */
+                                                       <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
+                                                        AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                        AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
                                        };
                                };
 
                                twi {
                                        pinctrl_twi: twi-0 {
                                                atmel,pins =
-                                                       <0 25 0x1 0x2   /* PA25 periph A with multi drive */
-                                                        0 26 0x1 0x2>; /* PA26 periph A with multi drive */
+                                                       <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* PA25 periph A with multi drive */
+                                                        AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* PA26 periph A with multi drive */
                                        };
 
                                        pinctrl_twi_gpio: twi_gpio-0 {
                                                atmel,pins =
-                                                       <0 25 0x0 0x2   /* PA25 GPIO with multi drive */
-                                                        0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
+                                                       <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
+                                                        AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;       /* PA26 GPIO with multi drive */
+                                       };
+                               };
+
+                               tcb0 {
+                                       pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                               atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                               atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                               atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                               atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                               atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                               atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                               atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                               atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                               atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+                               };
+
+                               tcb1 {
+                                       pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                               atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                               atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                               atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                               atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                               atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                               atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                               atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                               atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                       };
+
+                                       pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                               atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                        };
                                };
 
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                       interrupts = <2 4 1>;
+                                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
                                pioB: gpio@fffff600 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                       interrupts = <3 4 1>;
+                                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
                                pioC: gpio@fffff800 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                       interrupts = <4 4 1>;
+                                       interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
                                pioD: gpio@fffffa00 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffffa00 0x200>;
-                                       interrupts = <5 4 1>;
+                                       interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffff200 0x200>;
-                               interrupts = <1 4 7>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        usart0: serial@fffc0000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffc0000 0x200>;
-                               interrupts = <6 4 5>;
+                               interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                        usart1: serial@fffc4000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffc4000 0x200>;
-                               interrupts = <7 4 5>;
+                               interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                        usart2: serial@fffc8000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffc8000 0x200>;
-                               interrupts = <8 4 5>;
+                               interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                        usart3: serial@fffcc000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffcc000 0x200>;
-                               interrupts = <23 4 5>;
+                               interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                        usb1: gadget@fffb0000 {
                                compatible = "atmel,at91rm9200-udc";
                                reg = <0xfffb0000 0x4000>;
-                               interrupts = <11 4 2>;
+                               interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
                                status = "disabled";
                        };
                };
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
                        nand-ecc-mode = "soft";
-                       gpios = <&pioC 2 0
+                       gpios = <&pioC 2 GPIO_ACTIVE_HIGH
                                 0
-                                &pioB 1 0
+                                &pioB 1 GPIO_ACTIVE_HIGH
                                >;
                        status = "disabled";
                };
                usb0: ohci@00300000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00300000 0x100000>;
-                       interrupts = <23 4 2>;
+                       interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
 
        i2c@0 {
                compatible = "i2c-gpio";
-               gpios = <&pioA 25 0 /* sda */
-                        &pioA 26 0 /* scl */
+               gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
+                        &pioA 26 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
index e586d85f8e23ec6d26ce94cb97670995c9943e35..14058125d123af81516b2a86dfab14a2b04a4624 100644 (file)
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 
 / {
        model = "Atmel AT91RM9200 evaluation kit";
@@ -50,7 +50,7 @@
                        };
 
                        usb1: gadget@fffb0000 {
-                               atmel,vbus-gpio = <&pioD 4 0>;
+                               atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
                };
 
                ds2 {
                        label = "green";
-                       gpios = <&pioB 0 0x1>;
+                       gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "mmc0";
                };
 
                ds4 {
                        label = "yellow";
-                       gpios = <&pioB 1 0x1>;
+                       gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "heartbeat";
                };
 
                ds6 {
                        label = "red";
-                       gpios = <&pioB 2 0x1>;
+                       gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
                };
        };
 };
index 84c4bef2d7268760a6d927bd8ed2fdf7d547ea59..c7ccbcbffb3e6b283e6f7976271f42703fc7b90e 100644 (file)
@@ -8,7 +8,10 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
        model = "Atmel AT91SAM9260 family SoC";
                ssc0 = &ssc0;
        };
        cpus {
-               cpu@0 {
-                       compatible = "arm,arm926ejs";
+               #address-cells = <0>;
+               #size-cells = <0>;
+
+               cpu {
+                       compatible = "arm,arm926ej-s";
+                       device_type = "cpu";
                };
        };
 
                        pit: timer@fffffd30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffd30 0xf>;
-                               interrupts = <1 4 7>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
 
                        tcb0: timer@fffa0000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffa0000 0x100>;
-                               interrupts = <17 4 0 18 4 0 19 4 0>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+                                             18 IRQ_TYPE_LEVEL_HIGH 0
+                                             19 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
 
                        tcb1: timer@fffdc000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffdc000 0x100>;
-                               interrupts = <26 4 0 27 4 0 28 4 0>;
+                               interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+                                             27 IRQ_TYPE_LEVEL_HIGH 0
+                                             28 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
 
                        pinctrl@fffff400 {
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                       <1 14 0x1 0x0   /* PB14 periph A */
-                                                        1 15 0x1 0x1>; /* PB15 periph with pullup */
+                                                       <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
+                                                        AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB15 periph with pullup */
                                        };
                                };
 
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                       <1 4 0x1 0x0    /* PB4 periph A */
-                                                        1 5 0x1 0x0>;  /* PB5 periph A */
+                                                       <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                        AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                        };
 
                                        pinctrl_usart0_rts: usart0_rts-0 {
                                                atmel,pins =
-                                                       <1 26 0x1 0x0>; /* PB26 periph A */
+                                                       <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
                                        };
 
                                        pinctrl_usart0_cts: usart0_cts-0 {
                                                atmel,pins =
-                                                       <1 27 0x1 0x0>; /* PB27 periph A */
+                                                       <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
                                        };
 
                                        pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
                                                atmel,pins =
-                                                       <1 24 0x1 0x0   /* PB24 periph A */
-                                                        1 22 0x1 0x0>; /* PB22 periph A */
+                                                       <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB24 periph A */
+                                                        AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
                                        };
 
                                        pinctrl_usart0_dcd: usart0_dcd-0 {
                                                atmel,pins =
-                                                       <1 23 0x1 0x0>; /* PB23 periph A */
+                                                       <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
                                        };
 
                                        pinctrl_usart0_ri: usart0_ri-0 {
                                                atmel,pins =
-                                                       <1 25 0x1 0x0>; /* PB25 periph A */
+                                                       <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
                                        };
                                };
 
                                usart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                       <1 6 0x1 0x1    /* PB6 periph A with pullup */
-                                                        1 7 0x1 0x0>;  /* PB7 periph A */
+                                                       <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
+                                                        AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
                                        };
 
                                        pinctrl_usart1_rts: usart1_rts-0 {
                                                atmel,pins =
-                                                       <1 28 0x1 0x0>; /* PB28 periph A */
+                                                       <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
                                        };
 
                                        pinctrl_usart1_cts: usart1_cts-0 {
                                                atmel,pins =
-                                                       <1 29 0x1 0x0>; /* PB29 periph A */
+                                                       <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
                                        };
                                };
 
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                       <1 8 0x1 0x1    /* PB8 periph A with pullup */
-                                                        1 9 0x1 0x0>;  /* PB9 periph A */
+                                                       <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
+                                                        AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB9 periph A */
                                        };
 
                                        pinctrl_usart2_rts: usart2_rts-0 {
                                                atmel,pins =
-                                                       <0 4 0x1 0x0>;  /* PA4 periph A */
+                                                       <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA4 periph A */
                                        };
 
                                        pinctrl_usart2_cts: usart2_cts-0 {
                                                atmel,pins =
-                                                       <0 5 0x1 0x0>;  /* PA5 periph A */
+                                                       <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA5 periph A */
                                        };
                                };
 
                                usart3 {
                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                       <1 10 0x1 0x1   /* PB10 periph A with pullup */
-                                                        1 11 0x1 0x0>; /* PB11 periph A */
+                                                       <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB10 periph A with pullup */
+                                                        AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                        };
 
                                        pinctrl_usart3_rts: usart3_rts-0 {
                                                atmel,pins =
-                                                       <2 8 0x2 0x0>;  /* PC8 periph B */
+                                                       <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC8 periph B */
                                        };
 
                                        pinctrl_usart3_cts: usart3_cts-0 {
                                                atmel,pins =
-                                                       <2 10 0x2 0x0>; /* PC10 periph B */
+                                                       <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
                                        };
                                };
 
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                       <0 31 0x2 0x1   /* PA31 periph B with pullup */
-                                                        0 30 0x2 0x0>; /* PA30 periph B */
+                                                       <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA31 periph B with pullup */
+                                                        AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                        };
                                };
 
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                       <1 12 0x1 0x1   /* PB12 periph A with pullup */
-                                                        1 13 0x1 0x0>; /* PB13 periph A */
+                                                       <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB12 periph A with pullup */
+                                                        AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
                                        };
                                };
 
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                       <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
-                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                       <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP     /* PC13 gpio RDY pin pull_up */
+                                                        AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                        };
                                };
 
                                macb {
                                        pinctrl_macb_rmii: macb_rmii-0 {
                                                atmel,pins =
-                                                       <0 12 0x1 0x0   /* PA12 periph A */
-                                                        0 13 0x1 0x0   /* PA13 periph A */
-                                                        0 14 0x1 0x0   /* PA14 periph A */
-                                                        0 15 0x1 0x0   /* PA15 periph A */
-                                                        0 16 0x1 0x0   /* PA16 periph A */
-                                                        0 17 0x1 0x0   /* PA17 periph A */
-                                                        0 18 0x1 0x0   /* PA18 periph A */
-                                                        0 19 0x1 0x0   /* PA19 periph A */
-                                                        0 20 0x1 0x0   /* PA20 periph A */
-                                                        0 21 0x1 0x0>; /* PA21 periph A */
+                                                       <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
+                                                        AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
+                                                        AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
+                                                        AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
+                                                        AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA16 periph A */
+            &nb