media: replace all <spaces><tab> occurrences
authorMauro Carvalho Chehab <mchehab@s-opensource.com>
Thu, 4 Jan 2018 18:08:56 +0000 (13:08 -0500)
committerMauro Carvalho Chehab <mchehab@s-opensource.com>
Thu, 4 Jan 2018 18:15:05 +0000 (13:15 -0500)
There are a lot of places where sequences of space/tabs are
found. Get rid of all spaces before tabs.

Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
135 files changed:
drivers/media/common/saa7146/saa7146_video.c
drivers/media/dvb-core/Makefile
drivers/media/dvb-frontends/au8522_priv.h
drivers/media/dvb-frontends/drx39xyj/drx_driver.h
drivers/media/dvb-frontends/stb0899_drv.c
drivers/media/dvb-frontends/stb0899_drv.h
drivers/media/dvb-frontends/stb0899_priv.h
drivers/media/dvb-frontends/stv0900_core.c
drivers/media/dvb-frontends/stv0900_init.h
drivers/media/dvb-frontends/stv0900_priv.h
drivers/media/dvb-frontends/stv090x.c
drivers/media/dvb-frontends/stv090x_priv.h
drivers/media/dvb-frontends/stv6110x.c
drivers/media/dvb-frontends/stv6110x_priv.h
drivers/media/dvb-frontends/tda10023.c
drivers/media/firewire/firedtv-avc.c
drivers/media/firewire/firedtv-fe.c
drivers/media/i2c/cx25840/cx25840-core.c
drivers/media/i2c/cx25840/cx25840-core.h
drivers/media/i2c/cx25840/cx25840-ir.c
drivers/media/i2c/ks0127.c
drivers/media/i2c/ov7670.c
drivers/media/i2c/saa6752hs.c
drivers/media/i2c/saa7115.c
drivers/media/i2c/saa7127.c
drivers/media/i2c/saa717x.c
drivers/media/i2c/ths7303.c
drivers/media/i2c/tvaudio.c
drivers/media/i2c/tvp7002_reg.h
drivers/media/i2c/vpx3220.c
drivers/media/pci/bt8xx/bttv-cards.c
drivers/media/pci/bt8xx/bttv-input.c
drivers/media/pci/bt8xx/bttv.h
drivers/media/pci/bt8xx/bttvp.h
drivers/media/pci/cx18/cx18-alsa-pcm.c
drivers/media/pci/cx18/cx18-av-audio.c
drivers/media/pci/cx18/cx18-av-core.c
drivers/media/pci/cx18/cx18-av-core.h
drivers/media/pci/cx18/cx18-cards.c
drivers/media/pci/cx18/cx18-cards.h
drivers/media/pci/cx18/cx18-driver.h
drivers/media/pci/cx18/cx18-firmware.c
drivers/media/pci/cx18/cx18-mailbox.c
drivers/media/pci/cx18/cx18-streams.c
drivers/media/pci/cx18/cx18-vbi.c
drivers/media/pci/cx18/cx23418.h
drivers/media/pci/cx23885/cimax2.c
drivers/media/pci/cx23885/cx23885-video.c
drivers/media/pci/cx23885/cx23885.h
drivers/media/pci/cx23885/cx23888-ir.c
drivers/media/pci/ivtv/ivtv-cards.h
drivers/media/pci/ivtv/ivtv-driver.h
drivers/media/pci/ivtv/ivtv-firmware.c
drivers/media/pci/ivtv/ivtv-i2c.c
drivers/media/pci/ivtv/ivtv-ioctl.c
drivers/media/pci/ivtv/ivtv-mailbox.c
drivers/media/pci/mantis/mantis_reg.h
drivers/media/pci/mantis/mantis_vp1041.c
drivers/media/pci/meye/meye.c
drivers/media/pci/saa7134/saa7134-cards.c
drivers/media/pci/saa7134/saa7134-dvb.c
drivers/media/pci/saa7134/saa7134-video.c
drivers/media/pci/saa7134/saa7134.h
drivers/media/pci/saa7146/hexium_gemini.c
drivers/media/pci/saa7146/hexium_orion.c
drivers/media/pci/saa7146/mxb.c
drivers/media/pci/ttpci/av7110.h
drivers/media/pci/ttpci/budget-av.c
drivers/media/pci/ttpci/budget-ci.c
drivers/media/pci/zoran/zoran_driver.c
drivers/media/pci/zoran/zr36057.h
drivers/media/platform/Makefile
drivers/media/platform/arv.c
drivers/media/platform/coda/coda_regs.h
drivers/media/platform/davinci/dm355_ccdc_regs.h
drivers/media/platform/davinci/dm644x_ccdc_regs.h
drivers/media/platform/davinci/isif_regs.h
drivers/media/platform/davinci/vpfe_capture.c
drivers/media/platform/davinci/vpif.h
drivers/media/platform/davinci/vpss.c
drivers/media/platform/exynos4-is/fimc-core.c
drivers/media/platform/m2m-deinterlace.c
drivers/media/platform/omap/omap_vout.c
drivers/media/platform/sh_vou.c
drivers/media/radio/radio-aimslab.c
drivers/media/radio/radio-aztech.c
drivers/media/radio/radio-cadet.c
drivers/media/radio/radio-gemtek.c
drivers/media/radio/radio-rtrack2.c
drivers/media/radio/radio-sf16fmi.c
drivers/media/radio/radio-sf16fmr2.c
drivers/media/radio/radio-tea5764.c
drivers/media/radio/radio-terratec.c
drivers/media/radio/tea575x.c
drivers/media/rc/keymaps/rc-behold-columbus.c
drivers/media/rc/keymaps/rc-winfast-usbii-deluxe.c
drivers/media/tuners/mxl5005s.c
drivers/media/tuners/tda827x.h
drivers/media/tuners/tda9887.c
drivers/media/tuners/tuner-simple.c
drivers/media/tuners/tuner-xc2028.c
drivers/media/tuners/tuner-xc2028.h
drivers/media/usb/au0828/au0828-cards.h
drivers/media/usb/au0828/au0828-video.c
drivers/media/usb/au0828/au0828.h
drivers/media/usb/cpia2/cpia2_usb.c
drivers/media/usb/cx231xx/cx231xx-audio.c
drivers/media/usb/cx231xx/cx231xx-avcore.c
drivers/media/usb/cx231xx/cx231xx-core.c
drivers/media/usb/cx231xx/cx231xx-i2c.c
drivers/media/usb/cx231xx/cx231xx-pcb-cfg.h
drivers/media/usb/cx231xx/cx231xx-reg.h
drivers/media/usb/dvb-usb/az6027.c
drivers/media/usb/gspca/stv06xx/stv06xx.c
drivers/media/usb/hdpvr/hdpvr-video.c
drivers/media/usb/hdpvr/hdpvr.h
drivers/media/usb/pwc/pwc.h
drivers/media/usb/siano/smsusb.c
drivers/media/usb/stk1160/Makefile
drivers/media/usb/stkwebcam/stk-sensor.c
drivers/media/usb/uvc/uvc_driver.c
drivers/media/usb/uvc/uvc_isight.c
drivers/media/v4l2-core/v4l2-compat-ioctl32.c
drivers/media/v4l2-core/v4l2-ioctl.c
include/media/drv-intf/cx2341x.h
include/media/drv-intf/msp3400.h
include/media/drv-intf/saa7146.h
include/media/i2c/bt819.h
include/media/i2c/m52790.h
include/media/i2c/saa7115.h
include/media/i2c/upd64031a.h
include/media/v4l2-common.h
include/uapi/linux/dvb/video.h
include/uapi/linux/v4l2-controls.h
include/uapi/linux/videodev2.h

index 5dfc1f27d1cf7f5792c0f0ea83653eff4a187a41..0dfa0c09d646fdcd147437f871b49a995803af87 100644 (file)
@@ -1001,9 +1001,9 @@ const struct v4l2_ioctl_ops saa7146_video_ioctl_ops = {
        .vidioc_try_fmt_vid_overlay  = vidioc_try_fmt_vid_overlay,
        .vidioc_s_fmt_vid_overlay    = vidioc_s_fmt_vid_overlay,
 
-       .vidioc_overlay              = vidioc_overlay,
-       .vidioc_g_fbuf               = vidioc_g_fbuf,
-       .vidioc_s_fbuf               = vidioc_s_fbuf,
+       .vidioc_overlay              = vidioc_overlay,
+       .vidioc_g_fbuf               = vidioc_g_fbuf,
+       .vidioc_s_fbuf               = vidioc_s_fbuf,
        .vidioc_reqbufs              = vidioc_reqbufs,
        .vidioc_querybuf             = vidioc_querybuf,
        .vidioc_qbuf                 = vidioc_qbuf,
@@ -1012,7 +1012,7 @@ const struct v4l2_ioctl_ops saa7146_video_ioctl_ops = {
        .vidioc_s_std                = vidioc_s_std,
        .vidioc_streamon             = vidioc_streamon,
        .vidioc_streamoff            = vidioc_streamoff,
-       .vidioc_g_parm               = vidioc_g_parm,
+       .vidioc_g_parm               = vidioc_g_parm,
        .vidioc_subscribe_event      = v4l2_ctrl_subscribe_event,
        .vidioc_unsubscribe_event    = v4l2_event_unsubscribe,
 };
index 05827ee2a40606291f8c5ae1e41756500ccaa2aa..3a105d82019a0288b37f7a7143b1e8c79adffb42 100644 (file)
@@ -7,7 +7,7 @@ dvb-net-$(CONFIG_DVB_NET) := dvb_net.o
 dvb-vb2-$(CONFIG_DVB_MMSP) := dvb_vb2.o
 
 dvb-core-objs := dvbdev.o dmxdev.o dvb_demux.o                 \
-                dvb_ca_en50221.o dvb_frontend.o                \
+                dvb_ca_en50221.o dvb_frontend.o                \
                 $(dvb-net-y) dvb_ringbuffer.o $(dvb-vb2-y) dvb_math.o
 
 obj-$(CONFIG_DVB_CORE) += dvb-core.o
index f02dac958db65337ae5c0dc6564b8d9d7b28d530..2043c174475377b9542ebcf1acdffc9d88642923 100644 (file)
@@ -99,7 +99,7 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H         0x0A5
 #define AU8522_AGC_CONTROL_RANGE_REG0A6H               0x0A6
 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H             0x0A7
-#define AU8522_TUNER_AGC_RF_STOP_REG0A8H               0x0A8
+#define AU8522_TUNER_AGC_RF_STOP_REG0A8H               0x0A8
 #define AU8522_TUNER_AGC_RF_START_REG0A9H              0x0A9
 #define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH            0x0AA
 #define AU8522_TUNER_AGC_IF_STOP_REG0ABH               0x0AB
@@ -110,18 +110,18 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 
 /* Receiver registers */
 #define AU8522_FRMREGTHRD1_REG0B0H                     0x0B0
-#define AU8522_FRMREGAGC1H_REG0B1H                     0x0B1
-#define AU8522_FRMREGSHIFT1_REG0B2H                    0x0B2
-#define AU8522_TOREGAGC1_REG0B3H                       0x0B3
-#define AU8522_TOREGASHIFT1_REG0B4H                    0x0B4
+#define AU8522_FRMREGAGC1H_REG0B1H                     0x0B1
+#define AU8522_FRMREGSHIFT1_REG0B2H                    0x0B2
+#define AU8522_TOREGAGC1_REG0B3H                       0x0B3
+#define AU8522_TOREGASHIFT1_REG0B4H                    0x0B4
 #define AU8522_FRMREGBBH_REG0B5H                       0x0B5
-#define AU8522_FRMREGBBM_REG0B6H                       0x0B6
-#define AU8522_FRMREGBBL_REG0B7H                       0x0B7
+#define AU8522_FRMREGBBM_REG0B6H                       0x0B6
+#define AU8522_FRMREGBBL_REG0B7H                       0x0B7
 /* 0xB8 TO 0xD7 are the filter coefficients */
-#define AU8522_FRMREGTHRD2_REG0D8H                     0x0D8
-#define AU8522_FRMREGAGC2H_REG0D9H                     0x0D9
-#define AU8522_TOREGAGC2_REG0DAH                       0x0DA
-#define AU8522_TOREGSHIFT2_REG0DBH                     0x0DB
+#define AU8522_FRMREGTHRD2_REG0D8H                     0x0D8
+#define AU8522_FRMREGAGC2H_REG0D9H                     0x0D9
+#define AU8522_TOREGAGC2_REG0DAH                       0x0DA
+#define AU8522_TOREGSHIFT2_REG0DBH                     0x0DB
 #define AU8522_FRMREGPILOTH_REG0DCH                    0x0DC
 #define AU8522_FRMREGPILOTM_REG0DDH                    0x0DD
 #define AU8522_FRMREGPILOTL_REG0DEH                    0x0DE
@@ -134,9 +134,9 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 #define AU8522_CHIP_MODE_REG0FEH                       0x0FE
 
 /* I2C bus control registers */
-#define AU8522_I2C_CONTROL_REG0_REG090H                0x090
-#define AU8522_I2C_CONTROL_REG1_REG091H                0x091
-#define AU8522_I2C_STATUS_REG092H                      0x092
+#define AU8522_I2C_CONTROL_REG0_REG090H                        0x090
+#define AU8522_I2C_CONTROL_REG1_REG091H                        0x091
+#define AU8522_I2C_STATUS_REG092H                      0x092
 #define AU8522_I2C_WR_DATA0_REG093H                    0x093
 #define AU8522_I2C_WR_DATA1_REG094H                    0x094
 #define AU8522_I2C_WR_DATA2_REG095H                    0x095
@@ -156,48 +156,48 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 
 #define AU8522_ENA_USB_REG101H                         0x101
 
-#define AU8522_I2S_CTRL_0_REG110H                      0x110
-#define AU8522_I2S_CTRL_1_REG111H                      0x111
-#define AU8522_I2S_CTRL_2_REG112H                      0x112
+#define AU8522_I2S_CTRL_0_REG110H                      0x110
+#define AU8522_I2S_CTRL_1_REG111H                      0x111
+#define AU8522_I2S_CTRL_2_REG112H                      0x112
 
-#define AU8522_FRMREGFFECONTROL_REG121H                0x121
-#define AU8522_FRMREGDFECONTROL_REG122H                0x122
+#define AU8522_FRMREGFFECONTROL_REG121H                        0x121
+#define AU8522_FRMREGDFECONTROL_REG122H                        0x122
 
-#define AU8522_CARRFREQOFFSET0_REG201H                         0x201
+#define AU8522_CARRFREQOFFSET0_REG201H                 0x201
 #define AU8522_CARRFREQOFFSET1_REG202H                 0x202
 
 #define AU8522_DECIMATION_GAIN_REG21AH                 0x21A
-#define AU8522_FRMREGIFSLP_REG21BH                     0x21B
-#define AU8522_FRMREGTHRDL2_REG21CH                    0x21C
-#define AU8522_FRMREGSTEP3DB_REG21DH                   0x21D
+#define AU8522_FRMREGIFSLP_REG21BH                     0x21B
+#define AU8522_FRMREGTHRDL2_REG21CH                    0x21C
+#define AU8522_FRMREGSTEP3DB_REG21DH                   0x21D
 #define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH            0x21E
-#define AU8522_FRMREGPLLMODE_REG21FH                   0x21F
-#define AU8522_FRMREGCSTHRD_REG220H                    0x220
-#define AU8522_FRMREGCRLOCKDMAX_REG221H                0x221
-#define AU8522_FRMREGCRPERIODMASK_REG222H              0x222
-#define AU8522_FRMREGCRLOCK0THH_REG223H                0x223
-#define AU8522_FRMREGCRLOCK1THH_REG224H                0x224
-#define AU8522_FRMREGCRLOCK0THL_REG225H                0x225
-#define AU8522_FRMREGCRLOCK1THL_REG226H                0x226
+#define AU8522_FRMREGPLLMODE_REG21FH                   0x21F
+#define AU8522_FRMREGCSTHRD_REG220H                    0x220
+#define AU8522_FRMREGCRLOCKDMAX_REG221H                        0x221
+#define AU8522_FRMREGCRPERIODMASK_REG222H              0x222
+#define AU8522_FRMREGCRLOCK0THH_REG223H                        0x223
+#define AU8522_FRMREGCRLOCK1THH_REG224H                        0x224
+#define AU8522_FRMREGCRLOCK0THL_REG225H                        0x225
+#define AU8522_FRMREGCRLOCK1THL_REG226H                        0x226
 #define AU_FRMREGPLLACQPHASESCL_REG227H                        0x227
-#define AU8522_FRMREGFREQFBCTRL_REG228H                0x228
+#define AU8522_FRMREGFREQFBCTRL_REG228H                        0x228
 
 /* Analog TV Decoder */
 #define AU8522_TVDEC_STATUS_REG000H                    0x000
 #define AU8522_TVDEC_INT_STATUS_REG001H                        0x001
-#define AU8522_TVDEC_MACROVISION_STATUS_REG002H        0x002
+#define AU8522_TVDEC_MACROVISION_STATUS_REG002H                0x002
 #define AU8522_TVDEC_SHARPNESSREG009H                  0x009
 #define AU8522_TVDEC_BRIGHTNESS_REG00AH                        0x00A
 #define AU8522_TVDEC_CONTRAST_REG00BH                  0x00B
 #define AU8522_TVDEC_SATURATION_CB_REG00CH             0x00C
 #define AU8522_TVDEC_SATURATION_CR_REG00DH             0x00D
 #define AU8522_TVDEC_HUE_H_REG00EH                     0x00E
-#define AU8522_TVDEC_HUE_L_REG00FH                     0x00F
+#define AU8522_TVDEC_HUE_L_REG00FH                     0x00F
 #define AU8522_TVDEC_INT_MASK_REG010H                  0x010
 #define AU8522_VIDEO_MODE_REG011H                      0x011
 #define AU8522_TVDEC_PGA_REG012H                       0x012
 #define AU8522_TVDEC_COMB_MODE_REG015H                 0x015
-#define AU8522_REG016H                                 0x016
+#define AU8522_REG016H                                 0x016
 #define AU8522_TVDED_DBG_MODE_REG060H                  0x060
 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H              0x061
 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H              0x062
@@ -207,13 +207,13 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H            0x066
 #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H            0x067
 #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H            0x068
-#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H            0x069
+#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H            0x069
 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH            0x06A
-#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH            0x06B
-#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH           0x06C
-#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH           0x06D
-#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH           0x06E
-#define AU8522_TVDEC_UV_SEP_THR_REG06FH                0x06F
+#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH            0x06B
+#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH           0x06C
+#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH           0x06D
+#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH           0x06E
+#define AU8522_TVDEC_UV_SEP_THR_REG06FH                        0x06F
 #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H         0x070
 #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H         0x073
 #define AU8522_TVDEC_DCAGC_CTRL_REG077H                        0x077
@@ -229,42 +229,42 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 
 #define AU8522_TVDEC_CHROMA_AGC_REG401H                0x401
 #define AU8522_TVDEC_CHROMA_SFT_REG402H                0x402
-#define AU8522_FILTER_COEF_R410                0x410
-#define AU8522_FILTER_COEF_R411                0x411
-#define AU8522_FILTER_COEF_R412                0x412
-#define AU8522_FILTER_COEF_R413                0x413
-#define AU8522_FILTER_COEF_R414                0x414
-#define AU8522_FILTER_COEF_R415                0x415
-#define AU8522_FILTER_COEF_R416                0x416
-#define AU8522_FILTER_COEF_R417                0x417
-#define AU8522_FILTER_COEF_R418                0x418
-#define AU8522_FILTER_COEF_R419                0x419
-#define AU8522_FILTER_COEF_R41A                0x41A
-#define AU8522_FILTER_COEF_R41B                0x41B
-#define AU8522_FILTER_COEF_R41C                0x41C
-#define AU8522_FILTER_COEF_R41D                0x41D
-#define AU8522_FILTER_COEF_R41E                0x41E
-#define AU8522_FILTER_COEF_R41F                0x41F
-#define AU8522_FILTER_COEF_R420                0x420
-#define AU8522_FILTER_COEF_R421                0x421
-#define AU8522_FILTER_COEF_R422                0x422
-#define AU8522_FILTER_COEF_R423                0x423
-#define AU8522_FILTER_COEF_R424                0x424
-#define AU8522_FILTER_COEF_R425                0x425
-#define AU8522_FILTER_COEF_R426                0x426
-#define AU8522_FILTER_COEF_R427                0x427
-#define AU8522_FILTER_COEF_R428                0x428
-#define AU8522_FILTER_COEF_R429                0x429
-#define AU8522_FILTER_COEF_R42A                0x42A
-#define AU8522_FILTER_COEF_R42B                0x42B
-#define AU8522_FILTER_COEF_R42C                0x42C
-#define AU8522_FILTER_COEF_R42D                0x42D
+#define AU8522_FILTER_COEF_R410                        0x410
+#define AU8522_FILTER_COEF_R411                        0x411
+#define AU8522_FILTER_COEF_R412                        0x412
+#define AU8522_FILTER_COEF_R413                        0x413
+#define AU8522_FILTER_COEF_R414                        0x414
+#define AU8522_FILTER_COEF_R415                        0x415
+#define AU8522_FILTER_COEF_R416                        0x416
+#define AU8522_FILTER_COEF_R417                        0x417
+#define AU8522_FILTER_COEF_R418                        0x418
+#define AU8522_FILTER_COEF_R419                        0x419
+#define AU8522_FILTER_COEF_R41A                        0x41A
+#define AU8522_FILTER_COEF_R41B                        0x41B
+#define AU8522_FILTER_COEF_R41C                        0x41C
+#define AU8522_FILTER_COEF_R41D                        0x41D
+#define AU8522_FILTER_COEF_R41E                        0x41E
+#define AU8522_FILTER_COEF_R41F                        0x41F
+#define AU8522_FILTER_COEF_R420                        0x420
+#define AU8522_FILTER_COEF_R421                        0x421
+#define AU8522_FILTER_COEF_R422                        0x422
+#define AU8522_FILTER_COEF_R423                        0x423
+#define AU8522_FILTER_COEF_R424                        0x424
+#define AU8522_FILTER_COEF_R425                        0x425
+#define AU8522_FILTER_COEF_R426                        0x426
+#define AU8522_FILTER_COEF_R427                        0x427
+#define AU8522_FILTER_COEF_R428                        0x428
+#define AU8522_FILTER_COEF_R429                        0x429
+#define AU8522_FILTER_COEF_R42A                        0x42A
+#define AU8522_FILTER_COEF_R42B                        0x42B
+#define AU8522_FILTER_COEF_R42C                        0x42C
+#define AU8522_FILTER_COEF_R42D                        0x42D
 
 /* VBI Control Registers */
-#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H       0x004
-#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H       0x005
-#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H          0x006
-#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H           0x007
+#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H       0x004
+#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H       0x005
+#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H          0x006
+#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H           0x007
 #define AU8522_TVDEC_VBI_CTRL_H_REG017H                        0x017
 #define AU8522_TVDEC_VBI_CTRL_L_REG018H                        0x018
 #define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H       0x019
@@ -272,10 +272,10 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 #define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH          0x01B
 #define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH          0x01C
 #define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH       0x01E
-#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH       0x01F
-#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H       0x020
-#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H      0x021
-#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H      0x022
+#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH       0x01F
+#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H       0x020
+#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H      0x021
+#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H      0x022
 #define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H      0x023
 
 #define AU8522_REG071H                                 0x071
@@ -315,17 +315,17 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 #define AU8522_GPIO_DATA_REG0E2H                       0x0E2
 
 /* Audio Control Registers */
-#define AU8522_AUDIOAGC_REG0EEH                        0x0EE
-#define AU8522_AUDIO_STATUS_REG0F0H                    0x0F0
-#define AU8522_AUDIO_MODE_REG0F1H                      0x0F1
-#define AU8522_AUDIO_VOLUME_L_REG0F2H                  0x0F2
-#define AU8522_AUDIO_VOLUME_R_REG0F3H                  0x0F3
-#define AU8522_AUDIO_VOLUME_REG0F4H                    0x0F4
-#define AU8522_FRMREGAUPHASE_REG0F7H                   0x0F7
+#define AU8522_AUDIOAGC_REG0EEH                                0x0EE
+#define AU8522_AUDIO_STATUS_REG0F0H                    0x0F0
+#define AU8522_AUDIO_MODE_REG0F1H                      0x0F1
+#define AU8522_AUDIO_VOLUME_L_REG0F2H                  0x0F2
+#define AU8522_AUDIO_VOLUME_R_REG0F3H                  0x0F3
+#define AU8522_AUDIO_VOLUME_REG0F4H                    0x0F4
+#define AU8522_FRMREGAUPHASE_REG0F7H                   0x0F7
 #define AU8522_REG0F9H                                 0x0F9
 
-#define AU8522_AUDIOAGC2_REG605H                       0x605
-#define AU8522_AUDIOFREQ_REG606H                       0x606
+#define AU8522_AUDIOAGC2_REG605H                       0x605
+#define AU8522_AUDIOFREQ_REG606H                       0x606
 
 
 /**************************************************************/
@@ -356,53 +356,53 @@ int au8522_led_ctrl(struct au8522_state *state, int led);
 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M            0x02
 
 
-#define AU8522_INPUT_CONTROL_REG081H_ATSC                      0xC4
+#define AU8522_INPUT_CONTROL_REG081H_ATSC                      0xC4
 #define AU8522_INPUT_CONTROL_REG081H_ATVRF                     0xC4
 #define AU8522_INPUT_CONTROL_REG081H_ATVRF13                   0xC4
-#define AU8522_INPUT_CONTROL_REG081H_J83B64                    0xC4
-#define AU8522_INPUT_CONTROL_REG081H_J83B256                   0xC4
-#define AU8522_INPUT_CONTROL_REG081H_CVBS                      0x20
+#define AU8522_INPUT_CONTROL_REG081H_J83B64                    0xC4
+#define AU8522_INPUT_CONTROL_REG081H_J83B256                   0xC4
+#define AU8522_INPUT_CONTROL_REG081H_CVBS                      0x20
 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1                  0xA2
 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2                  0xA0
 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3                  0x69
 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4                  0x68
-#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF              0x28
+#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF              0x28
 /* CH1 AS Y,CH3 AS C */
-#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13               0x23
+#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13               0x23
 /* CH2 AS Y,CH4 AS C */
-#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24               0x20
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC               0x0C
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64             0x09
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256                    0x09
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS               0x12
-#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF              0x1A
+#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24               0x20
+#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC               0x0C
+#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64             0x09
+#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256            0x09
+#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS               0x12
+#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF              0x1A
 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13            0x1A
 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO             0x02
 
 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR           0x00
 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO          0x9C
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS            0x9D
+#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS            0x9D
 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC            0xE8
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256                 0xCA
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64                  0xCA
-#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF                   0xDD
+#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256         0xCA
+#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64          0xCA
+#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF           0xDD
 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13         0xDD
 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL             0xDD
 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM              0xDD
 
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC            0x80
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256                 0x80
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64                  0x80
+#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256         0x80
+#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64          0x80
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC     0x40
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256  0x40
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64   0x40
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR    0x00
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF           0x01
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13         0x01
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO                  0x04
+#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO          0x04
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS            0x01
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM                     0x03
-#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS             0x09
+#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM             0x03
+#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS             0x09
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL             0x01
 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM              0x01
 
index 855685b6b38669d035d9b14b420033f4a1d1c487..1ec20eecc4331edeef6e9b5c337fd7027a4ff68b 100644 (file)
@@ -932,7 +932,7 @@ STRUCTS
  * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
  */
 struct drxu_code_info {
-       char                    *mc_file;
+       char                    *mc_file;
 };
 
 /*
index 2c5427c77db727906ba1f1bae517189c40745b16..3c654ae16e787997128d7c5f16d50dfd16dd070f 100644 (file)
@@ -1583,15 +1583,15 @@ static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe)
 static const struct dvb_frontend_ops stb0899_ops = {
        .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
        .info = {
-               .name                   = "STB0899 Multistandard",
+               .name                   = "STB0899 Multistandard",
                .frequency_min          = 950000,
-               .frequency_max          = 2150000,
+               .frequency_max          = 2150000,
                .frequency_stepsize     = 0,
                .frequency_tolerance    = 0,
-               .symbol_rate_min        =  5000000,
-               .symbol_rate_max        = 45000000,
+               .symbol_rate_min        =  5000000,
+               .symbol_rate_max        = 45000000,
 
-               .caps                   = FE_CAN_INVERSION_AUTO |
+               .caps                   = FE_CAN_INVERSION_AUTO |
                                          FE_CAN_FEC_AUTO       |
                                          FE_CAN_2G_MODULATION  |
                                          FE_CAN_QPSK
index 6c285aee7edf2a351a7bb697d7bbc99eec0aa7e8..f65f9a8266f809f7028b544b376de8f068a3ba3a 100644 (file)
@@ -82,7 +82,7 @@ enum stb0899_inversion {
  * 1. POWER ON/OFF             (index 0)
  * 2. FE_HAS_LOCK/LOCK_LOSS    (index 1)
  *
- * @gpio       = one of the above listed GPIO's
+ * @gpio       = one of the above listed GPIO's
  * @level      = output state: pulled up or low
  */
 struct stb0899_postproc {
index 86d140e4c5edcd10a63c6b274b39431e1a1582d8..3285cd1ba60af28e10cc7d0c66a0d293c84f7832 100644 (file)
@@ -252,7 +252,7 @@ extern int stb0899_write_s2reg(struct stb0899_state *state,
 extern int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
 
 
-#define STB0899_READ_S2REG(DEVICE, REG)        (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG))
+#define STB0899_READ_S2REG(DEVICE, REG)                (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG))
 //#define STB0899_WRITE_S2REG(DEVICE, REG, DATA)       (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA))
 
 /* stb0899_algo.c      */
index 0b739725e3c0c06c9fb14f42ed09e5322a613968..72f17b97ca04c30d0e25ea3af8801a9f61eb4b22 100644 (file)
@@ -1929,7 +1929,7 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
        switch (demod) {
        case 0:
        case 1:
-               init_params.dmd_ref_clk         = config->xtal;
+               init_params.dmd_ref_clk         = config->xtal;
                init_params.demod_mode          = config->demod_mode;
                init_params.rolloff             = STV0900_35;
                init_params.path1_ts_clock      = config->path1_mode;
index 411941442086e4d5abc806f6029328ec7ed11652..550ef4a0f6549c68f7db072db944d1bf7047023d 100644 (file)
@@ -148,8 +148,8 @@ struct stv0900_short_frames_car_loop_optim_vs_mod {
 
 /* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
 static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = {
-       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
        { STV0900_QPSK_12,      0x1C,   0x0D,   0x1B,   0x2C,   0x3A,
                                0x1C,   0x2A,   0x3B,   0x2A,   0x1B },
        { STV0900_QPSK_35,      0x2C,   0x0D,   0x2B,   0x2C,   0x3A,
@@ -176,15 +176,15 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = {
                                0x0B,   0x39,   0x1A,   0x19,   0x0A },
        { STV0900_8PSK_89,      0x3B,   0x3B,   0x0B,   0x2B,   0x2A,
                                0x0B,   0x39,   0x1A,   0x29,   0x39 },
-       { STV0900_8PSK_910,     0x3B,   0x3B,   0x0B,   0x2B,   0x2A,
+       { STV0900_8PSK_910,     0x3B,   0x3B,   0x0B,   0x2B,   0x2A,
                                0x0B,   0x39,   0x1A,   0x29,   0x39 }
 };
 
 
 /* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
 static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
-       /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+       /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
        { STV0900_QPSK_12,      0x1F,   0x3F,   0x1E,   0x3F,   0x3D,
                                0x1F,   0x3D,   0x3E,   0x3D,   0x1E },
        { STV0900_QPSK_35,      0x2F,   0x3F,   0x2E,   0x2F,   0x3D,
@@ -211,7 +211,7 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
                                0x1e,   0x3c,   0x2d,   0x2c,   0x1d },
        { STV0900_8PSK_89,      0x3e,   0x3e,   0x1e,   0x2e,   0x3d,
                                0x1e,   0x0d,   0x2d,   0x3c,   0x1d },
-       { STV0900_8PSK_910,     0x3e,   0x3e,   0x1e,   0x2e,   0x3d,
+       { STV0900_8PSK_910,     0x3e,   0x3e,   0x1e,   0x2e,   0x3d,
                                0x1e,   0x1d,   0x2d,   0x0d,   0x1d },
 };
 
@@ -219,8 +219,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
 
 /* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */
 static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = {
-       /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+       /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
        { STV0900_16APSK_23,    0x0C,   0x0C,   0x0C,   0x0C,   0x1D,
                                0x0C,   0x3C,   0x0C,   0x2C,   0x0C },
        { STV0900_16APSK_34,    0x0C,   0x0C,   0x0C,   0x0C,   0x0E,
@@ -248,8 +248,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = {
 
 /* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */
 static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = {
-       /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+       /* Modcod               2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
        { STV0900_QPSK_14,      0x0F,   0x3F,   0x0E,   0x3F,   0x2D,
                                0x2F,   0x2D,   0x1F,   0x3D,   0x3E },
        { STV0900_QPSK_13,      0x0F,   0x3F,   0x0E,   0x3F,   0x2D,
@@ -275,10 +275,10 @@ struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = {
 };
 
 static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = {
-       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
        { STV0900_QPSK_12,      0x3C,   0x2C,   0x0C,   0x2C,   0x1B,
-                               0x2C,   0x1B,   0x1C,   0x0B,   0x3B },
+                               0x2C,   0x1B,   0x1C,   0x0B,   0x3B },
        { STV0900_QPSK_35,      0x0D,   0x0D,   0x0C,   0x0D,   0x1B,
                                0x3C,   0x1B,   0x1C,   0x0B,   0x3B },
        { STV0900_QPSK_23,      0x1D,   0x0D,   0x0C,   0x1D,   0x2B,
@@ -309,8 +309,8 @@ static      const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = {
 
 static const
 struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = {
-       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
+       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff */
        { STV0900_16APSK_23,    0x0A,   0x0A,   0x0A,   0x0A,   0x1A,
                                0x0A,   0x3A,   0x0A,   0x2A,   0x0A },
        { STV0900_16APSK_34,    0x0A,   0x0A,   0x0A,   0x0A,   0x0B,
@@ -337,8 +337,8 @@ struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = {
 
 static const
 struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut30[3] = {
-       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
-                               10MPoff 20MPon  20MPoff 30MPon  30MPoff*/
+       /*Modcod                2MPon   2MPoff  5MPon   5MPoff  10MPon
+                               10MPoff 20MPon  20MPoff 30MPon  30MPoff*/
        { STV0900_QPSK_14,      0x0C,   0x3C,   0x0B,   0x3C,   0x2A,
                                0x2C,   0x2A,   0x1C,   0x3A,   0x3B },
        { STV0900_QPSK_13,      0x0C,   0x3C,   0x0B,   0x3C,   0x2A,
index 7a95f955627b8fdc8882fc7ed6110ec17528227b..d1fc06ff27d38b421182c15cd1d7aed2d18f3655 100644 (file)
@@ -243,7 +243,7 @@ struct stv0900_init_params{
 
        u8      tun1_maddress;
        int     tuner1_adc;
-       int     tuner1_type;
+       int     tuner1_type;
 
        /* IQ from the tuner1 to the demod */
        enum stv0900_iq_inversion       tun1_iq_inv;
index 20641bd2f9775b6aa688a554bdf61f65ce384c44..9133f65d4623bc34c5558a6f6855013aa501c244 100644 (file)
@@ -677,7 +677,7 @@ static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
 
 /* Cut 3.0 Short Frame Tracking CR Loop */
 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
-       /* MODCOD         2M    5M    10M   20M   30M */
+       /* MODCOD         2M    5M    10M   20M   30M */
        { STV090x_QPSK,   0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
        { STV090x_8PSK,   0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
        { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
@@ -701,7 +701,7 @@ static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
        u8 buf;
 
        struct i2c_msg msg[] = {
-               { .addr = config->address, .flags       = 0,            .buf = b0,   .len = 2 },
+               { .addr = config->address, .flags       = 0,            .buf = b0,   .len = 2 },
                { .addr = config->address, .flags       = I2C_M_RD,     .buf = &buf, .len = 1 }
        };
 
@@ -4906,11 +4906,11 @@ static const struct dvb_frontend_ops stv090x_ops = {
        .info = {
                .name                   = "STV090x Multistandard",
                .frequency_min          = 950000,
-               .frequency_max          = 2150000,
+               .frequency_max          = 2150000,
                .frequency_stepsize     = 0,
                .frequency_tolerance    = 0,
-               .symbol_rate_min        = 1000000,
-               .symbol_rate_max        = 45000000,
+               .symbol_rate_min        = 1000000,
+               .symbol_rate_max        = 45000000,
                .caps                   = FE_CAN_INVERSION_AUTO |
                                          FE_CAN_FEC_AUTO       |
                                          FE_CAN_QPSK           |
@@ -4953,7 +4953,7 @@ struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
        state->frontend.ops                     = stv090x_ops;
        state->frontend.demodulator_priv        = state;
        state->demod                            = demod;
-       state->demod_mode                       = config->demod_mode; /* Single or Dual mode */
+       state->demod_mode                       = config->demod_mode; /* Single or Dual mode */
        state->device                           = config->device;
        state->rolloff                          = STV090x_RO_35; /* default */
 
index 37c9f93a8a6a3bacb9ab09729835ee9b26118559..fdda2185db9d77234f237226967b1815e8dbd0e3 100644 (file)
@@ -231,7 +231,7 @@ struct stv090x_tab {
 };
 
 struct stv090x_internal {
-       struct i2c_adapter      *i2c_adap;
+       struct i2c_adapter      *i2c_adap;
        u8                      i2c_addr;
 
        struct mutex            demod_lock; /* Lock access to shared register */
index d4ac29ac9b4fb9d3895a08f99a034eb0ced360bc..d8950028d0211b94b47958657e96d3a7959fd531 100644 (file)
@@ -46,7 +46,7 @@ static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
        u8 b0[] = { reg };
        u8 b1[] = { 0 };
        struct i2c_msg msg[] = {
-               { .addr = config->addr, .flags = 0,        .buf = b0, .len = 1 },
+               { .addr = config->addr, .flags = 0,        .buf = b0, .len = 1 },
                { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 }
        };
 
index a993aba27b7ef33e8c7a48dc849950f737504b28..109dfaf4ba4261334845db616364435f9f39c4c0 100644 (file)
 
 #define STV6110x_SETFIELD(mask, bitf, val)                             \
        (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) <<        \
-                                 STV6110x_OFFST_##bitf))) |            \
+                                 STV6110x_OFFST_##bitf))) |            \
                          (val << STV6110x_OFFST_##bitf))
 
 #define STV6110x_GETFIELD(bitf, val)                                   \
-       ((val >> STV6110x_OFFST_##bitf) &                               \
+       ((val >> STV6110x_OFFST_##bitf) &                               \
        ((1 << STV6110x_WIDTH_##bitf) - 1))
 
 #define MAKEWORD16(a, b)                       (((a) << 8) | (b))
@@ -68,7 +68,7 @@
 struct stv6110x_state {
        struct i2c_adapter              *i2c;
        const struct stv6110x_config    *config;
-       u8                              regs[8];
+       u8                              regs[8];
 
        const struct stv6110x_devctl    *devctl;
 };
index abe27029fe93208ffebde030a1608c3e91168508..6c84916234e3f9c1f2ee98901caf78652ebac00f 100644 (file)
@@ -211,7 +211,7 @@ static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr)
 
                BDRX=1<<(24+NDEC);
                BDRX*=sr;
-               do_div(BDRX, state->sysclk);    /* BDRX/=SYSCLK; */
+               do_div(BDRX, state->sysclk);    /* BDRX/=SYSCLK; */
 
                BDR=(s32)BDRX;
        }
index 37db04f8104d536fa573c9c4c62390047ac82f68..1c933b2cf7603cdc045c49671997d5f13a4e9a37 100644 (file)
@@ -47,7 +47,7 @@
 #define AVC_OPCODE_DSIT                        0xc8
 #define AVC_OPCODE_DSD                 0xcb
 
-#define DESCRIPTOR_TUNER_STATUS        0x80
+#define DESCRIPTOR_TUNER_STATUS                0x80
 #define DESCRIPTOR_SUBUNIT_IDENTIFIER  0x00
 
 #define SFE_VENDOR_DE_COMPANYID_0      0x00 /* OUI of Digital Everywhere */
@@ -688,7 +688,7 @@ int avc_tuner_get_ts(struct firedtv *fdtv)
        c->operand[2] = 0xff;   /* status */
        c->operand[3] = 0x20;   /* system id = DVB */
        c->operand[4] = 0x00;   /* antenna number */
-       c->operand[5] = 0x0;    /* system_specific_search_flags */
+       c->operand[5] = 0x0;    /* system_specific_search_flags */
        c->operand[6] = sl;     /* system_specific_multiplex selection_length */
        /*
         * operand[7]: valid_flags[0]
index 86efeb10d2f2cb07d03eb0669c61a36bb936b462..a2ef4ede8ebed061dd2b8396b5eb08f96b9abde7 100644 (file)
@@ -165,7 +165,7 @@ void fdtv_frontend_init(struct firedtv *fdtv, const char *name)
        ops->read_snr                   = fdtv_read_snr;
        ops->read_ucblocks              = fdtv_read_uncorrected_blocks;
 
-       ops->diseqc_send_master_cmd     = fdtv_diseqc_send_master_cmd;
+       ops->diseqc_send_master_cmd     = fdtv_diseqc_send_master_cmd;
        ops->diseqc_send_burst          = fdtv_diseqc_send_burst;
        ops->set_tone                   = fdtv_set_tone;
        ops->set_voltage                = fdtv_set_voltage;
@@ -220,7 +220,7 @@ void fdtv_frontend_init(struct firedtv *fdtv, const char *name)
                fi->symbol_rate_min     = 870000;
                fi->symbol_rate_max     = 6900000;
 
-               fi->caps                = FE_CAN_INVERSION_AUTO |
+               fi->caps                = FE_CAN_INVERSION_AUTO |
                                          FE_CAN_QAM_16         |
                                          FE_CAN_QAM_32         |
                                          FE_CAN_QAM_64         |
@@ -236,7 +236,7 @@ void fdtv_frontend_init(struct firedtv *fdtv, const char *name)
                fi->frequency_max       = 861000000;
                fi->frequency_stepsize  = 62500;
 
-               fi->caps                = FE_CAN_INVERSION_AUTO         |
+               fi->caps                = FE_CAN_INVERSION_AUTO         |
                                          FE_CAN_FEC_2_3                |
                                          FE_CAN_TRANSMISSION_MODE_AUTO |
                                          FE_CAN_GUARD_INTERVAL_AUTO    |
index 4a9c137095fee502eebe19e0994cc3c051832576..98be63ae85901e7087c3101d5d796faffbbfdb90 100644 (file)
@@ -1263,7 +1263,7 @@ static int set_input(struct i2c_client *client, enum cx25840_video_input vid_inp
 static int set_v4lstd(struct i2c_client *client)
 {
        struct cx25840_state *state = to_state(i2c_get_clientdata(client));
-       u8 fmt = 0;     /* zero is autodetect */
+       u8 fmt = 0;     /* zero is autodetect */
        u8 pal_m = 0;
 
        /* First tests should be against specific std */
index 55432ed42714ac474483624f0b1bd1c14b42177f..fb13a624d2e3650758d85a157d76041b88b4ea8e 100644 (file)
@@ -118,7 +118,7 @@ static inline bool is_cx23888(struct cx25840_state *state)
 }
 
 /* ----------------------------------------------------------------------- */
-/* cx25850-core.c                                                         */
+/* cx25850-core.c                                                         */
 int cx25840_write(struct i2c_client *client, u16 addr, u8 value);
 int cx25840_write4(struct i2c_client *client, u16 addr, u32 value);
 u8 cx25840_read(struct i2c_client *client, u16 addr);
index 548382b2b2e65f5db1ffd026ee9c9fb25efc1b38..ad7f66c7aac87f1ca36658e9a535e6d59e453983 100644 (file)
@@ -28,7 +28,7 @@ static unsigned int ir_debug;
 module_param(ir_debug, int, 0644);
 MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
 
-#define CX25840_IR_REG_BASE    0x200
+#define CX25840_IR_REG_BASE    0x200
 
 #define CX25840_IR_CNTRL_REG   0x200
 #define CNTRL_WIN_3_3  0x00000000
index ab536c4a711558fb22cf5dd0ab22cb4b770a49f2..5905ed6f8397ecd5b77b75f664b2eb2ecd94614f 100644 (file)
@@ -195,7 +195,7 @@ struct adjust {
 struct ks0127 {
        struct v4l2_subdev sd;
        v4l2_std_id     norm;
-       u8              regs[256];
+       u8              regs[256];
 };
 
 static inline struct ks0127 *to_ks0127(struct v4l2_subdev *sd)
index c6c32f6497772e198d95e9265dbd0c817b251cdd..fd229bc8a0e5bdf30c78f2af2f6e8d2e4b846a26 100644 (file)
@@ -412,12 +412,12 @@ static struct regval_list ov7670_fmt_yuv422[] = {
        { REG_COM1, 0 },        /* CCIR601 */
        { REG_COM15, COM15_R00FF },
        { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
-       { 0x4f, 0x80 },         /* "matrix coefficient 1" */
-       { 0x50, 0x80 },         /* "matrix coefficient 2" */
+       { 0x4f, 0x80 },         /* "matrix coefficient 1" */
+       { 0x50, 0x80 },         /* "matrix coefficient 2" */
        { 0x51, 0    },         /* vb */
-       { 0x52, 0x22 },         /* "matrix coefficient 4" */
-       { 0x53, 0x5e },         /* "matrix coefficient 5" */
-       { 0x54, 0x80 },         /* "matrix coefficient 6" */
+       { 0x52, 0x22 },         /* "matrix coefficient 4" */
+       { 0x53, 0x5e },         /* "matrix coefficient 5" */
+       { 0x54, 0x80 },         /* "matrix coefficient 6" */
        { REG_COM13, COM13_GAMMA|COM13_UVSAT },
        { 0xff, 0xff },
 };
@@ -427,13 +427,13 @@ static struct regval_list ov7670_fmt_rgb565[] = {
        { REG_RGB444, 0 },      /* No RGB444 please */
        { REG_COM1, 0x0 },      /* CCIR601 */
        { REG_COM15, COM15_RGB565 },
-       { REG_COM9, 0x38 },     /* 16x gain ceiling; 0x8 is reserved bit */
-       { 0x4f, 0xb3 },         /* "matrix coefficient 1" */
-       { 0x50, 0xb3 },         /* "matrix coefficient 2" */
+       { REG_COM9, 0x38 },     /* 16x gain ceiling; 0x8 is reserved bit */
+       { 0x4f, 0xb3 },         /* "matrix coefficient 1" */
+       { 0x50, 0xb3 },         /* "matrix coefficient 2" */
        { 0x51, 0    },         /* vb */
-       { 0x52, 0x3d },         /* "matrix coefficient 4" */
-       { 0x53, 0xa7 },         /* "matrix coefficient 5" */
-       { 0x54, 0xe4 },         /* "matrix coefficient 6" */
+       { 0x52, 0x3d },         /* "matrix coefficient 4" */
+       { 0x53, 0xa7 },         /* "matrix coefficient 5" */
+       { 0x54, 0xe4 },         /* "matrix coefficient 6" */
        { REG_COM13, COM13_GAMMA|COM13_UVSAT },
        { 0xff, 0xff },
 };
@@ -443,13 +443,13 @@ static struct regval_list ov7670_fmt_rgb444[] = {
        { REG_RGB444, R444_ENABLE },    /* Enable xxxxrrrr ggggbbbb */
        { REG_COM1, 0x0 },      /* CCIR601 */
        { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
-       { REG_COM9, 0x38 },     /* 16x gain ceiling; 0x8 is reserved bit */
-       { 0x4f, 0xb3 },         /* "matrix coefficient 1" */
-       { 0x50, 0xb3 },         /* "matrix coefficient 2" */
+       { REG_COM9, 0x38 },     /* 16x gain ceiling; 0x8 is reserved bit */
+       { 0x4f, 0xb3 },         /* "matrix coefficient 1" */
+       { 0x50, 0xb3 },         /* "matrix coefficient 2" */
        { 0x51, 0    },         /* vb */
-       { 0x52, 0x3d },         /* "matrix coefficient 4" */
-       { 0x53, 0xa7 },         /* "matrix coefficient 5" */
-       { 0x54, 0xe4 },         /* "matrix coefficient 6" */
+       { 0x52, 0x3d },         /* "matrix coefficient 4" */
+       { 0x53, 0xa7 },         /* "matrix coefficient 5" */
+       { 0x54, 0xe4 },         /* "matrix coefficient 6" */
        { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 },  /* Magic rsvd bit */
        { 0xff, 0xff },
 };
@@ -667,7 +667,7 @@ static struct ov7670_format_struct {
        {
                .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
                .colorspace     = V4L2_COLORSPACE_SRGB,
-               .regs           = ov7670_fmt_yuv422,
+               .regs           = ov7670_fmt_yuv422,
                .cmatrix        = { 128, -128, 0, -34, -94, 128 },
        },
        {
@@ -685,7 +685,7 @@ static struct ov7670_format_struct {
        {
                .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
                .colorspace     = V4L2_COLORSPACE_SRGB,
-               .regs           = ov7670_fmt_raw,
+               .regs           = ov7670_fmt_raw,
                .cmatrix        = { 0, 0, 0, 0, 0, 0 },
        },
 };
index 7202d3a3219a73dc9db084206ed48e0a6891f129..170cc65c4f23146cd616754094b422ba7ffe60cb 100644 (file)
@@ -72,8 +72,8 @@ struct saa6752hs_mpeg_params {
        /* video */
        enum v4l2_mpeg_video_aspect     vi_aspect;
        enum v4l2_mpeg_video_bitrate_mode vi_bitrate_mode;
-       __u32                           vi_bitrate;
-       __u32                           vi_bitrate_peak;
+       __u32                           vi_bitrate;
+       __u32                           vi_bitrate_peak;
 };
 
 static const struct v4l2_format v4l2_format_table[] =
@@ -98,8 +98,8 @@ struct saa6752hs_state {
                struct v4l2_ctrl *video_bitrate;
                struct v4l2_ctrl *video_bitrate_peak;
        };
-       u32                           revision;
-       int                           has_ac3;
+       u32                           revision;
+       int                           has_ac3;
        struct saa6752hs_mpeg_params  params;
        enum saa6752hs_videoformat    video_format;
        v4l2_std_id                   standard;
index 7dd6cff6d811b7240008616ddee026111c511646..e216cd7684094fd80fe64e2f1dd588e7b643f8f5 100644 (file)
@@ -748,7 +748,7 @@ static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
        u32 acni;
        u32 hz;
        u64 f;
-       u8 acc = 0;     /* reg 0x3a, audio clock control */
+       u8 acc = 0;     /* reg 0x3a, audio clock control */
 
        /* Checks for chips that don't have audio clock (saa7111, saa7113) */
        if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
index 01784d441ae6e4f343597c893146ff9d1cb86144..e58a150cec5ca3be0e63bc177ca4083f3d51d207 100644 (file)
@@ -132,109 +132,109 @@ struct i2c_reg_value {
 };
 
 static const struct i2c_reg_value saa7129_init_config_extra[] = {
-       { SAA7127_REG_OUTPUT_PORT_CONTROL,              0x38 },
-       { SAA7127_REG_VTRIG,                            0xfa },
+       { SAA7127_REG_OUTPUT_PORT_CONTROL,              0x38 },
+       { SAA7127_REG_VTRIG,                            0xfa },
        { 0, 0 }
 };
 
 static const struct i2c_reg_value saa7127_init_config_common[] = {
-       { SAA7127_REG_WIDESCREEN_CONFIG,                0x0d },
-       { SAA7127_REG_WIDESCREEN_ENABLE,                0x00 },
-       { SAA7127_REG_COPYGEN_0,                        0x77 },
-       { SAA7127_REG_COPYGEN_1,                        0x41 },
-       { SAA7127_REG_COPYGEN_2,                        0x00 }, /* Macrovision enable/disable */
-       { SAA7127_REG_OUTPUT_PORT_CONTROL,              0xbf },
-       { SAA7127_REG_GAIN_LUMINANCE_RGB,               0x00 },
-       { SAA7127_REG_GAIN_COLORDIFF_RGB,               0x00 },
-       { SAA7127_REG_INPUT_PORT_CONTROL_1,             0x80 }, /* for color bars */
-       { SAA7127_REG_LINE_21_ODD_0,                    0x77 },
-       { SAA7127_REG_LINE_21_ODD_1,                    0x41 },
-       { SAA7127_REG_LINE_21_EVEN_0,                   0x88 },
-       { SAA7127_REG_LINE_21_EVEN_1,                   0x41 },
-       { SAA7127_REG_RCV_PORT_CONTROL,                 0x12 },
-       { SAA7127_REG_VTRIG,                            0xf9 },
-       { SAA7127_REG_HTRIG_HI,                         0x00 },
-       { SAA7127_REG_RCV2_OUTPUT_START,                0x41 },
-       { SAA7127_REG_RCV2_OUTPUT_END,                  0xc3 },
-       { SAA7127_REG_RCV2_OUTPUT_MSBS,                 0x00 },
-       { SAA7127_REG_TTX_REQUEST_H_START,              0x3e },
-       { SAA7127_REG_TTX_REQUEST_H_DELAY_LENGTH,       0xb8 },
-       { SAA7127_REG_CSYNC_ADVANCE_VSYNC_SHIFT,        0x03 },
-       { SAA7127_REG_TTX_ODD_REQ_VERT_START,           0x15 },
-       { SAA7127_REG_TTX_ODD_REQ_VERT_END,             0x16 },
-       { SAA7127_REG_TTX_EVEN_REQ_VERT_START,          0x15 },
-       { SAA7127_REG_TTX_EVEN_REQ_VERT_END,            0x16 },
-       { SAA7127_REG_FIRST_ACTIVE,                     0x1a },
-       { SAA7127_REG_LAST_ACTIVE,                      0x01 },
-       { SAA7127_REG_MSB_VERTICAL,                     0xc0 },
-       { SAA7127_REG_DISABLE_TTX_LINE_LO_0,            0x00 },
-       { SAA7127_REG_DISABLE_TTX_LINE_LO_1,            0x00 },
+       { SAA7127_REG_WIDESCREEN_CONFIG,                0x0d },
+       { SAA7127_REG_WIDESCREEN_ENABLE,                0x00 },
+       { SAA7127_REG_COPYGEN_0,                        0x77 },
+       { SAA7127_REG_COPYGEN_1,                        0x41 },
+       { SAA7127_REG_COPYGEN_2,                        0x00 }, /* Macrovision enable/disable */
+       { SAA7127_REG_OUTPUT_PORT_CONTROL,              0xbf },
+       { SAA7127_REG_GAIN_LUMINANCE_RGB,               0x00 },
+       { SAA7127_REG_GAIN_COLORDIFF_RGB,               0x00 },
+       { SAA7127_REG_INPUT_PORT_CONTROL_1,             0x80 }, /* for color bars */
+       { SAA7127_REG_LINE_21_ODD_0,                    0x77 },
+       { SAA7127_REG_LINE_21_ODD_1,                    0x41 },
+       { SAA7127_REG_LINE_21_EVEN_0,                   0x88 },
+       { SAA7127_REG_LINE_21_EVEN_1,                   0x41 },
+       { SAA7127_REG_RCV_PORT_CONTROL,                 0x12 },
+       { SAA7127_REG_VTRIG,                            0xf9 },
+       { SAA7127_REG_HTRIG_HI,                         0x00 },
+       { SAA7127_REG_RCV2_OUTPUT_START,                0x41 },
+       { SAA7127_REG_RCV2_OUTPUT_END,                  0xc3 },
+       { SAA7127_REG_RCV2_OUTPUT_MSBS,                 0x00 },
+       { SAA7127_REG_TTX_REQUEST_H_START,              0x3e },
+       { SAA7127_REG_TTX_REQUEST_H_DELAY_LENGTH,       0xb8 },
+       { SAA7127_REG_CSYNC_ADVANCE_VSYNC_SHIFT,        0x03 },
+       { SAA7127_REG_TTX_ODD_REQ_VERT_START,           0x15 },
+       { SAA7127_REG_TTX_ODD_REQ_VERT_END,             0x16 },
+       { SAA7127_REG_TTX_EVEN_REQ_VERT_START,          0x15 },
+       { SAA7127_REG_TTX_EVEN_REQ_VERT_END,            0x16 },
+       { SAA7127_REG_FIRST_ACTIVE,                     0x1a },
+       { SAA7127_REG_LAST_ACTIVE,                      0x01 },
+       { SAA7127_REG_MSB_VERTICAL,                     0xc0 },
+       { SAA7127_REG_DISABLE_TTX_LINE_LO_0,            0x00 },
+       { SAA7127_REG_DISABLE_TTX_LINE_LO_1,            0x00 },
        { 0, 0 }
 };
 
 #define SAA7127_60HZ_DAC_CONTROL 0x15
 static const struct i2c_reg_value saa7127_init_config_60hz[] = {
-       { SAA7127_REG_BURST_START,                      0x19 },
+       { SAA7127_REG_BURST_START,                      0x19 },
        /* BURST_END is also used as a chip ID in saa7127_probe */
-       { SAA7127_REG_BURST_END,                        0x1d },
-       { SAA7127_REG_CHROMA_PHASE,                     0xa3 },
-       { SAA7127_REG_GAINU,                            0x98 },
-       { SAA7127_REG_GAINV,                            0xd3 },
-       { SAA7127_REG_BLACK_LEVEL,                      0x39 },
-       { SAA7127_REG_BLANKING_LEVEL,                   0x2e },
-       { SAA7127_REG_VBI_BLANKING,                     0x2e },
-       { SAA7127_REG_DAC_CONTROL,                      0x15 },
-       { SAA7127_REG_BURST_AMP,                        0x4d },
-       { SAA7127_REG_SUBC3,                            0x1f },
-       { SAA7127_REG_SUBC2,                            0x7c },
-       { SAA7127_REG_SUBC1,                            0xf0 },
-       { SAA7127_REG_SUBC0,                            0x21 },
-       { SAA7127_REG_MULTI,                            0x90 },
-       { SAA7127_REG_CLOSED_CAPTION,                   0x11 },
+       { SAA7127_REG_BURST_END,                        0x1d },
+       { SAA7127_REG_CHROMA_PHASE,                     0xa3 },
+       { SAA7127_REG_GAINU,                            0x98 },
+       { SAA7127_REG_GAINV,                            0xd3 },
+       { SAA7127_REG_BLACK_LEVEL,                      0x39 },
+       { SAA7127_REG_BLANKING_LEVEL,                   0x2e },
+       { SAA7127_REG_VBI_BLANKING,                     0x2e },
+       { SAA7127_REG_DAC_CONTROL,                      0x15 },
+       { SAA7127_REG_BURST_AMP,                        0x4d },
+       { SAA7127_REG_SUBC3,                            0x1f },
+       { SAA7127_REG_SUBC2,                            0x7c },
+       { SAA7127_REG_SUBC1,                            0xf0 },
+       { SAA7127_REG_SUBC0,                            0x21 },
+       { SAA7127_REG_MULTI,                            0x90 },
+       { SAA7127_REG_CLOSED_CAPTION,                   0x11 },
        { 0, 0 }
 };
 
 #define SAA7127_50HZ_PAL_DAC_CONTROL 0x02
 static struct i2c_reg_value saa7127_init_config_50hz_pal[] = {
-       { SAA7127_REG_BURST_START,                      0x21 },
+       { SAA7127_REG_BURST_START,                      0x21 },
        /* BURST_END is also used as a chip ID in saa7127_probe */
-       { SAA7127_REG_BURST_END,                        0x1d },
-       { SAA7127_REG_CHROMA_PHASE,                     0x3f },
-       { SAA7127_REG_GAINU,                            0x7d },
-       { SAA7127_REG_GAINV,                            0xaf },
-       { SAA7127_REG_BLACK_LEVEL,                      0x33 },
-       { SAA7127_REG_BLANKING_LEVEL,                   0x35 },
-       { SAA7127_REG_VBI_BLANKING,                     0x35 },
-       { SAA7127_REG_DAC_CONTROL,                      0x02 },
-       { SAA7127_REG_BURST_AMP,                        0x2f },
-       { SAA7127_REG_SUBC3,                            0xcb },
-       { SAA7127_REG_SUBC2,                            0x8a },
-       { SAA7127_REG_SUBC1,                            0x09 },
-       { SAA7127_REG_SUBC0,                            0x2a },
-       { SAA7127_REG_MULTI,                            0xa0 },
-       { SAA7127_REG_CLOSED_CAPTION,                   0x00 },
+       { SAA7127_REG_BURST_END,                        0x1d },
+       { SAA7127_REG_CHROMA_PHASE,                     0x3f },
+       { SAA7127_REG_GAINU,                            0x7d },
+       { SAA7127_REG_GAINV,                            0xaf },
+       { SAA7127_REG_BLACK_LEVEL,                      0x33 },
+       { SAA7127_REG_BLANKING_LEVEL,                   0x35 },
+       { SAA7127_REG_VBI_BLANKING,                     0x35 },
+       { SAA7127_REG_DAC_CONTROL,                      0x02 },
+       { SAA7127_REG_BURST_AMP,                        0x2f },
+       { SAA7127_REG_SUBC3,                            0xcb },
+       { SAA7127_REG_SUBC2,                            0x8a },
+       { SAA7127_REG_SUBC1,                            0x09 },
+       { SAA7127_REG_SUBC0,                            0x2a },
+       { SAA7127_REG_MULTI,                            0xa0 },
+       { SAA7127_REG_CLOSED_CAPTION,                   0x00 },
        { 0, 0 }
 };
 
 #define SAA7127_50HZ_SECAM_DAC_CONTROL 0x08
 static struct i2c_reg_value saa7127_init_config_50hz_secam[] = {
-       { SAA7127_REG_BURST_START,                      0x21 },
+       { SAA7127_REG_BURST_START,                      0x21 },
        /* BURST_END is also used as a chip ID in saa7127_probe */
-       { SAA7127_REG_BURST_END,                        0x1d },
-       { SAA7127_REG_CHROMA_PHASE,                     0x3f },
-       { SAA7127_REG_GAINU,                            0x6a },
-       { SAA7127_REG_GAINV,                            0x81 },
-       { SAA7127_REG_BLACK_LEVEL,                      0x33 },
-       { SAA7127_REG_BLANKING_LEVEL,                   0x35 },
-       { SAA7127_REG_VBI_BLANKING,                     0x35 },
-       { SAA7127_REG_DAC_CONTROL,                      0x08 },
-       { SAA7127_REG_BURST_AMP,                        0x2f },
-       { SAA7127_REG_SUBC3,                            0xb2 },
-       { SAA7127_REG_SUBC2,                            0x3b },
-       { SAA7127_REG_SUBC1,                            0xa3 },
-       { SAA7127_REG_SUBC0,                            0x28 },
-       { SAA7127_REG_MULTI,                            0x90 },
-       { SAA7127_REG_CLOSED_CAPTION,                   0x00 },
+       { SAA7127_REG_BURST_END,                        0x1d },
+       { SAA7127_REG_CHROMA_PHASE,                     0x3f },
+       { SAA7127_REG_GAINU,                            0x6a },
+       { SAA7127_REG_GAINV,                            0x81 },
+       { SAA7127_REG_BLACK_LEVEL,                      0x33 },
+       { SAA7127_REG_BLANKING_LEVEL,                   0x35 },
+       { SAA7127_REG_VBI_BLANKING,                     0x35 },
+       { SAA7127_REG_DAC_CONTROL,                      0x08 },
+       { SAA7127_REG_BURST_AMP,                        0x2f },
+       { SAA7127_REG_SUBC3,                            0xb2 },
+       { SAA7127_REG_SUBC2,                            0x3b },
+       { SAA7127_REG_SUBC1,                            0xa3 },
+       { SAA7127_REG_SUBC0,                            0x28 },
+       { SAA7127_REG_MULTI,                            0x90 },
+       { SAA7127_REG_CLOSED_CAPTION,                   0x00 },
        { 0, 0 }
 };
 
index 102467e00fb3f461401f068c3224dbf4bc339fdf..668c39cc29e8e8a68d8c384b02b81a10917d67c0 100644 (file)
@@ -82,13 +82,13 @@ static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 /* ----------------------------------------------------------------------- */
 
 /* for audio mode */
-#define TUNER_AUDIO_MONO       0  /* LL */
-#define TUNER_AUDIO_STEREO     1  /* LR */
-#define TUNER_AUDIO_LANG1      2  /* LL */
-#define TUNER_AUDIO_LANG2      3  /* RR */
+#define TUNER_AUDIO_MONO       0  /* LL */
+#define TUNER_AUDIO_STEREO     1  /* LR */
+#define TUNER_AUDIO_LANG1      2  /* LL */
+#define TUNER_AUDIO_LANG2      3  /* RR */
 
-#define SAA717X_NTSC_WIDTH     (704)
-#define SAA717X_NTSC_HEIGHT    (480)
+#define SAA717X_NTSC_WIDTH     (704)
+#define SAA717X_NTSC_HEIGHT    (480)
 
 /* ----------------------------------------------------------------------- */
 
index 71a31352135c6d08b7d3590b70cb50e1a801f0f4..8206bf7a5a8fa4b3e6950465ae9b83dc85afe928 100644 (file)
@@ -319,7 +319,7 @@ static const struct v4l2_subdev_core_ops ths7303_core_ops = {
 
 static const struct v4l2_subdev_ops ths7303_ops = {
        .core   = &ths7303_core_ops,
-       .video  = &ths7303_video_ops,
+       .video  = &ths7303_video_ops,
 };
 
 static int ths7303_probe(struct i2c_client *client,
index e6edda524856fca2f6ea4cca5e0899523514dd04..772164b848ef18e91677ec0612ec5ee40275f90f 100644 (file)
@@ -134,7 +134,7 @@ struct CHIPSTATE {
        /* thread */
        struct task_struct   *thread;
        struct timer_list    wt;
-       int                  audmode;
+       int                  audmode;
 };
 
 static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
index 933673561fa25d095acc59797874ffd896462858..3c8c8b0a6a4c7194cb2b87ca3cea8c908464382e 100644 (file)
 #define TVP7002_L_FRAME_STAT_LSBS      0x37
 #define TVP7002_L_FRAME_STAT_MSBS      0x38
 #define TVP7002_CLK_L_STAT_LSBS                0x39
-#define TVP7002_CLK_L_STAT_MSBS        0x3a
+#define TVP7002_CLK_L_STAT_MSBS                0x3a
 #define TVP7002_HSYNC_W                        0x3b
 #define TVP7002_VSYNC_W                 0x3c
-#define TVP7002_L_LENGTH_TOL           0x3d
+#define TVP7002_L_LENGTH_TOL           0x3d
 /* Reserved 0x3e */
 #define TVP7002_VIDEO_BWTH_CTL         0x3f
 #define TVP7002_AVID_START_PIXEL_LSBS  0x40
 #define TVP7002_AVID_START_PIXEL_MSBS   0x41
-#define TVP7002_AVID_STOP_PIXEL_LSBS   0x42
+#define TVP7002_AVID_STOP_PIXEL_LSBS   0x42
 #define TVP7002_AVID_STOP_PIXEL_MSBS    0x43
 #define TVP7002_VBLK_F_0_START_L_OFF   0x44
 #define TVP7002_VBLK_F_1_START_L_OFF    0x45
index 67de79b2d55039704ef589949690d4b60502bcf1..c3549fa55b62cab9ff406b8d203293f1acd7b0a3 100644 (file)
@@ -201,7 +201,7 @@ static const unsigned short init_pal[] = {
                                 * skipped by the VFE) */
        0x8b, 16,               /* Horizontal begin */
        0x8c, 768,              /* Horizontal length */
-       0x8d, 784,              /* Number of pixels
+       0x8d, 784,              /* Number of pixels
                                 * Must be >= Horizontal begin + Horizontal length */
        0x8f, 0xc00,            /* Disable window 2 */
        0xf0, 0x77,             /* 13.5 MHz transport, Forced
index 7dcf509e66d9e8cf7e542868e2aa89e262b293fb..1902732f90e1c4f1c403078f7840db434176de88 100644 (file)
@@ -373,8 +373,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 2, 0, 0, 0 },
-               .gpiomute       = 10,
+               .gpiomux        = { 2, 0, 0, 0 },
+               .gpiomute       = 10,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -385,8 +385,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 1, 2, 3 },
-               .gpiomute       = 4,
+               .gpiomux        = { 0, 1, 2, 3 },
+               .gpiomute       = 4,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -397,8 +397,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 4, 0, 2, 3 },
-               .gpiomute       = 1,
+               .gpiomux        = { 4, 0, 2, 3 },
+               .gpiomute       = 1,
                .no_msp34xx     = 1,
                .tuner_type     = TUNER_PHILIPS_NTSC,
                .tuner_addr     = ADDR_UNSET,
@@ -414,7 +414,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0 },
+               .gpiomux        = { 0 },
                .tuner_type     = TUNER_ABSENT,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -425,8 +425,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 3,
                .muxsel         = MUXSEL(2, 3, 1, 0),
-               .gpiomux        = { 0, 1, 0, 1 },
-               .gpiomute       = 3,
+               .gpiomux        = { 0, 1, 0, 1 },
+               .gpiomute       = 3,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -437,7 +437,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 3,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomask       = 0x0f,
-               .gpiomux        = { 0x0c, 0x04, 0x08, 0x04 },
+               .gpiomux        = { 0x0c, 0x04, 0x08, 0x04 },
                /*                0x04 for some cards ?? */
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -451,7 +451,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 3,
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 0, 0),
-               .gpiomux        = { 0 },
+               .gpiomux        = { 0 },
                .tuner_type     = TUNER_ABSENT,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -464,8 +464,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xc00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0xc00, 0x800, 0x400 },
-               .gpiomute       = 0xc00,
+               .gpiomux        = { 0, 0xc00, 0x800, 0x400 },
+               .gpiomute       = 0xc00,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -477,7 +477,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 3,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 1, 1, 2, 3 },
+               .gpiomux        = { 1, 1, 2, 3 },
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -489,8 +489,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x0f, /* old: 7 */
                .muxsel         = MUXSEL(2, 0, 1, 1),
-               .gpiomux        = { 0, 1, 2, 3 },
-               .gpiomute       = 4,
+               .gpiomux        = { 0, 1, 2, 3 },
+               .gpiomute       = 4,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -502,8 +502,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x3014f,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x20001,0x10001, 0, 0 },
-               .gpiomute       = 10,
+               .gpiomux        = { 0x20001,0x10001, 0, 0 },
+               .gpiomute       = 10,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -516,7 +516,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 13, 14, 11, 7 },
+               .gpiomux        = { 13, 14, 11, 7 },
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -527,7 +527,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 13, 14, 11, 7 },
+               .gpiomux        = { 13, 14, 11, 7 },
                .msp34xx_alt    = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
@@ -542,8 +542,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 2, 1, 3 }, /* old: {0, 1, 2, 3, 4} */
-               .gpiomute       = 4,
+               .gpiomux        = { 0, 2, 1, 3 }, /* old: {0, 1, 2, 3, 4} */
+               .gpiomute       = 4,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -555,8 +555,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0, 1, 0 },
-               .gpiomute       = 10,
+               .gpiomux        = { 0, 0, 1, 0 },
+               .gpiomute       = 10,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -571,7 +571,7 @@ struct tvcard bttv_tvcards[] = {
                .muxsel         = MUXSEL(2, 3, 1, 1),
                /* 2003-10-20 by "Anton A. Arapov" <arapov@mail.ru> */
                .gpiomux        = { 0x001e00, 0, 0x018000, 0x014000 },
-               .gpiomute       = 0x002000,
+               .gpiomute       = 0x002000,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -583,8 +583,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x8300f8,
                .muxsel         = MUXSEL(2, 3, 1, 1, 0),
-               .gpiomux        = { 0x4fa007,0xcfa007,0xcfa007,0xcfa007 },
-               .gpiomute       = 0xcfa007,
+               .gpiomux        = { 0x4fa007,0xcfa007,0xcfa007,0xcfa007 },
+               .gpiomute       = 0xcfa007,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .volume_gpio    = winview_volume,
@@ -597,7 +597,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 1, 0, 0, 0 },
+               .gpiomux        = { 1, 0, 0, 0 },
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -608,7 +608,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = NO_SVHS,
                .gpiomask       = 0x8dff00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0 },
+               .gpiomux        = { 0 },
                .no_msp34xx     = 1,
                .tuner_type     = TUNER_ABSENT,
                .tuner_addr     = ADDR_UNSET,
@@ -631,8 +631,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1800,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
+               .gpiomute       = 0x1800,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL_I,
                .tuner_addr     = ADDR_UNSET,
@@ -644,8 +644,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xc00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 1, 0x800, 0x400 },
-               .gpiomute       = 0xc00,
+               .gpiomux        = { 0, 1, 0x800, 0x400 },
+               .gpiomute       = 0xc00,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -659,7 +659,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 0), /* input 2 is digital */
                /* .digital_mode= DIGITAL_MODE_CAMERA, */
-               .gpiomux        = { 0, 0, 0, 0 },
+               .gpiomux        = { 0, 0, 0, 0 },
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_ALPS_TSBB5_PAL_I,
@@ -674,8 +674,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xe00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = {0x400, 0x400, 0x400, 0x400 },
-               .gpiomute       = 0xc00,
+               .gpiomux        = {0x400, 0x400, 0x400, 0x400 },
+               .gpiomute       = 0xc00,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -690,7 +690,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x1f0fff,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0x20000, 0x30000, 0x10000, 0 },
-               .gpiomute       = 0x40000,
+               .gpiomute       = 0x40000,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
                .audio_mode_gpio= terratv_audio,
@@ -702,8 +702,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 3,
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 0, 1, 1),
-               .gpiomux        = { 0, 1, 2, 3 },
-               .gpiomute       = 4,
+               .gpiomux        = { 0, 1, 2, 3 },
+               .gpiomute       = 4,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -714,8 +714,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1800,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
+               .gpiomute       = 0x1800,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_SECAM,
                .tuner_addr     = ADDR_UNSET,
@@ -729,8 +729,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1f0fff,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x20000, 0x30000, 0x10000, 0x00000 },
-               .gpiomute       = 0x40000,
+               .gpiomux        = { 0x20000, 0x30000, 0x10000, 0x00000 },
+               .gpiomute       = 0x40000,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
                .audio_mode_gpio= terratv_audio,
@@ -774,7 +774,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 1, /* was: 4 */
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 0, 0),
-               .gpiomux        = { 0 },
+               .gpiomux        = { 0 },
                .tuner_type     = TUNER_ABSENT,
                .tuner_addr     = ADDR_UNSET,
                .muxsel_hook    = PXC200_muxsel,
@@ -787,8 +787,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1800,  /* 0x8dfe00 */
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0x0800, 0x1000, 0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomux        = { 0, 0x0800, 0x1000, 0x1000 },
+               .gpiomute       = 0x1800,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -800,7 +800,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 3,
                .gpiomask       = 1,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 1, 0, 0, 0 },
+               .gpiomux        = { 1, 0, 0, 0 },
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -814,7 +814,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0 },
+               .gpiomux        = { 0 },
                .tuner_type     = TUNER_ABSENT,
                .tuner_addr     = ADDR_UNSET,
        },
@@ -825,8 +825,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xffff00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x500, 0, 0x300, 0x900 },
-               .gpiomute       = 0x900,
+               .gpiomux        = { 0x500, 0, 0x300, 0x900 },
+               .gpiomute       = 0x900,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -840,8 +840,8 @@ struct tvcard bttv_tvcards[] = {
                .muxsel         = MUXSEL(2, 3, 1, 1, 0),
                /* Alexander Varakin <avarakin@hotmail.com> [stereo version] */
                .gpiomask       = 0xb33000,
-               .gpiomux        = { 0x122000,0x1000,0x0000,0x620000 },
-               .gpiomute       = 0x800000,
+               .gpiomux        = { 0x122000,0x1000,0x0000,0x620000 },
+               .gpiomute       = 0x800000,
                /* Audio Routing for "WinFast 2000 XP" (no tv stereo !)
                        gpio23 -- hef4052:nEnable (0x800000)
                        gpio12 -- hef4052:A1
@@ -867,8 +867,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1800,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
+               .gpiomute       = 0x1800,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -882,8 +882,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1800,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
+               .gpiomute       = 0x1800,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -896,8 +896,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xff,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x21, 0x20, 0x24, 0x2c },
-               .gpiomute       = 0x29,
+               .gpiomux        = { 0x21, 0x20, 0x24, 0x2c },
+               .gpiomute       = 0x29,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
@@ -910,8 +910,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x551e00,
                .muxsel         = MUXSEL(2, 3, 1, 0),
-               .gpiomux        = { 0x551400, 0x551200, 0, 0 },
-               .gpiomute       = 0x551c00,
+               .gpiomux        = { 0x551400, 0x551200, 0, 0 },
+               .gpiomute       = 0x551c00,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL_I,
                .tuner_addr     = ADDR_UNSET,
@@ -924,8 +924,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x03000F,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 2, 0xd0001, 0, 0 },
-               .gpiomute       = 1,
+               .gpiomux        = { 2, 0xd0001, 0, 0 },
+               .gpiomute       = 1,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -939,8 +939,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 4, 0, 2, 3 },
-               .gpiomute       = 1,
+               .gpiomux        = { 4, 0, 2, 3 },
+               .gpiomute       = 1,
                .no_msp34xx     = 1,
                .tuner_type     = TUNER_PHILIPS_NTSC,
                .tuner_addr     = ADDR_UNSET,
@@ -954,7 +954,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 13, 4, 11, 7 },
+               .gpiomux        = { 13, 4, 11, 7 },
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -968,7 +968,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0, 0, 0},
+               .gpiomux        = { 0, 0, 0, 0},
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL_I,
@@ -981,8 +981,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xe00b,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0xff9ff6, 0xff9ff6, 0xff1ff7, 0 },
-               .gpiomute       = 0xff3ffc,
+               .gpiomux        = { 0xff9ff6, 0xff9ff6, 0xff1ff7, 0 },
+               .gpiomute       = 0xff3ffc,
                .no_msp34xx     = 1,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -996,8 +996,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = NO_SVHS,
                .gpiomask       = 3,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 1, 1, 0, 2 },
-               .gpiomute       = 3,
+               .gpiomux        = { 1, 1, 0, 2 },
+               .gpiomute       = 3,
                .no_msp34xx     = 1,
                .pll            = PLL_NONE,
                .tuner_type     = UNSET,
@@ -1010,7 +1010,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 3,
                .gpiomask       = 0,
                .muxsel         = MUXSEL(2, 3, 1, 0, 0),
-               .gpiomux        = { 0 },
+               .gpiomux        = { 0 },
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_ABSENT,
@@ -1023,8 +1023,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xbcf03f,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0xbc803f, 0xbc903f, 0xbcb03f, 0 },
-               .gpiomute       = 0xbcb03f,
+               .gpiomux        = { 0xbc803f, 0xbc903f, 0xbcb03f, 0 },
+               .gpiomute       = 0xbcb03f,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_4039FR5_NTSC,
@@ -1037,8 +1037,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x70000,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x20000, 0x30000, 0x10000, 0 },
-               .gpiomute       = 0x40000,
+               .gpiomux        = { 0x20000, 0x30000, 0x10000, 0 },
+               .gpiomute       = 0x40000,
                .no_msp34xx     = 1,
                .pll            = PLL_35,
                .tuner_type     = TUNER_PHILIPS_PAL_I,
@@ -1054,8 +1054,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = {2,0,0,0 },
-               .gpiomute       = 1,
+               .gpiomux        = {2,0,0,0 },
+               .gpiomute       = 1,
                .pll            = PLL_28,
                .tuner_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
@@ -1067,7 +1067,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x010f00,
                .muxsel         = MUXSEL(2, 3, 0, 0),
-               .gpiomux        = {0x10000, 0, 0x10000, 0 },
+               .gpiomux        = {0x10000, 0, 0x10000, 0 },
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_ALPS_TSHC6_NTSC,
@@ -1083,8 +1083,8 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0xAA0000,
                .muxsel         = MUXSEL(2, 3, 1, 1, 0), /* in 4 is digital */
                /* .digital_mode= DIGITAL_MODE_CAMERA, */
-               .gpiomux        = { 0x20000, 0, 0x80000, 0x80000 },
-               .gpiomute       = 0xa8000,
+               .gpiomux        = { 0x20000, 0, 0x80000, 0x80000 },
+               .gpiomute       = 0xa8000,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL_I,
@@ -1108,7 +1108,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 0, 1, 1),
                .gpiomux        = { 0, 1, 2, 3 },
-               .gpiomute       = 4,
+               .gpiomute       = 4,
                .pll            = PLL_28,
                .tuner_type     = UNSET /* TUNER_ALPS_TMDH2_NTSC */,
                .tuner_addr     = ADDR_UNSET,
@@ -1123,8 +1123,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 3,
                .gpiomask       = 0x03000F,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 1, 0xd0001, 0, 0 },
-               .gpiomute       = 10,
+               .gpiomux        = { 1, 0xd0001, 0, 0 },
+               .gpiomute       = 10,
                                /* sound path (5 sources):
                                MUX1 (mask 0x03), Enable Pin 0x08 (0=enable, 1=disable)
                                        0= ext. Audio IN
@@ -1147,8 +1147,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x1c,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0, 0, 0x10, 8 },
-               .gpiomute       = 4,
+               .gpiomux        = { 0, 0, 0x10, 8 },
+               .gpiomute       = 4,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1166,8 +1166,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x18e0,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x0000,0x0800,0x1000,0x1000 },
-               .gpiomute       = 0x18e0,
+               .gpiomux        = { 0x0000,0x0800,0x1000,0x1000 },
+               .gpiomute       = 0x18e0,
                        /* For cards with tda9820/tda9821:
                                0x0000: Tuner normal stereo
                                0x0080: Tuner A2 SAP (second audio program = Zweikanalton)
@@ -1186,7 +1186,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0xF,
                .muxsel         = MUXSEL(2, 3, 1, 0),
                .gpiomux        = { 2, 0, 0, 0 },
-               .gpiomute       = 10,
+               .gpiomute       = 10,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1202,7 +1202,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x1800,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 0x800, 0x1000, 0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomute       = 0x1800,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1232,7 +1232,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0xe00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0x400, 0x400, 0x400, 0x400 },
-               .gpiomute       = 0x800,
+               .gpiomute       = 0x800,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_4036FY5_NTSC,
                .tuner_addr     = ADDR_UNSET,
@@ -1246,7 +1246,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x03000F,
                .muxsel         = MUXSEL(2, 3, 1, 0),
                .gpiomux        = { 2, 0, 0, 0 },
-               .gpiomute       = 1,
+               .gpiomute       = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1263,7 +1263,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 11,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 2, 0, 0, 1 },
-               .gpiomute       = 8,
+               .gpiomute       = 8,
                .pll            = PLL_35,
                .tuner_type     = TUNER_TEMIC_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1293,7 +1293,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0xFF,
                .muxsel         = MUXSEL(2, 3, 1, 0),
                .gpiomux        = { 1, 0, 4, 4 },
-               .gpiomute       = 9,
+               .gpiomute       = 9,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1306,8 +1306,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xf03f,
                .muxsel         = MUXSEL(2, 3, 1, 0),
-               .gpiomux        = { 0xbffe, 0, 0xbfff, 0 },
-               .gpiomute       = 0xbffe,
+               .gpiomux        = { 0xbffe, 0, 0xbfff, 0 },
+               .gpiomute       = 0xbffe,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_4006FN5_MULTI_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1322,7 +1322,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = NO_SVHS,
                .gpiomask       = 1,
                .muxsel         = MUXSEL(2, 3, 0, 1),
-               .gpiomux        = { 0, 0, 1, 0 },
+               .gpiomux        = { 0, 0, 1, 0 },
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TEMIC_4006FN5_MULTI_PAL,
@@ -1339,8 +1339,8 @@ struct tvcard bttv_tvcards[] = {
                                /* Radio changed from 1e80 to 0x800 to make
                                FlyVideo2000S in .hu happy (gm)*/
                                /* -dk-???: set mute=0x1800 for tda9874h daughterboard */
-               .gpiomux        = { 0x0000,0x0800,0x1000,0x1000 },
-               .gpiomute       = 0x1800,
+               .gpiomux        = { 0x0000,0x0800,0x1000,0x1000 },
+               .gpiomute       = 0x1800,
                .audio_mode_gpio= fv2000s_audio,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
@@ -1354,8 +1354,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0xffff00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x500, 0x500, 0x300, 0x900 },
-               .gpiomute       = 0x900,
+               .gpiomux        = { 0x500, 0x500, 0x300, 0x900 },
+               .gpiomute       = 0x900,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -1389,7 +1389,7 @@ struct tvcard bttv_tvcards[] = {
                /* 0x100000: 1=MSP enabled (0=disable again)
                * 0x010000: Connected to "S0" on tda9880 (0=Pal/BG, 1=NTSC) */
                .gpiomux        = {0x947fff, 0x987fff,0x947fff,0x947fff },
-               .gpiomute       = 0x947fff,
+               .gpiomute       = 0x947fff,
                /* tvtuner, radio,   external,internal, mute,  stereo
                * tuner, Composit, SVid, Composit-on-Svid-adapter */
                .muxsel         = MUXSEL(2, 3, 0, 1),
@@ -1409,7 +1409,7 @@ struct tvcard bttv_tvcards[] = {
                /* 0x100000: 1=MSP enabled (0=disable again)
                * 0x010000: Connected to "S0" on tda9880 (0=Pal/BG, 1=NTSC) */
                .gpiomux        = {0x947fff, 0x987fff,0x947fff,0x947fff },
-               .gpiomute       = 0x947fff,
+               .gpiomute       = 0x947fff,
                /* tvtuner, radio,   external,internal, mute,  stereo
                * tuner, Composit, SVid, Composit-on-Svid-adapter */
                .muxsel         = MUXSEL(2, 3, 0, 1),
@@ -1438,7 +1438,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 0, 11, 7 }, /* TV and Radio with same GPIO ! */
-               .gpiomute       = 13,
+               .gpiomute       = 13,
                .pll            = PLL_28,
                .tuner_type     = TUNER_LG_PAL_I_FM,
                .tuner_addr     = ADDR_UNSET,
@@ -1473,8 +1473,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x3f,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 0x01, 0x00, 0x03, 0x03 },
-               .gpiomute       = 0x09,
+               .gpiomux        = { 0x01, 0x00, 0x03, 0x03 },
+               .gpiomute       = 0x09,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
@@ -1525,7 +1525,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x1C800F,  /* Bit0-2: Audio select, 8-12:remote control 14:remote valid 15:remote reset */
                .muxsel         = MUXSEL(2, 1, 1),
                .gpiomux        = { 0, 1, 2, 2 },
-               .gpiomute       = 4,
+               .gpiomute       = 4,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
                .pll            = PLL_28,
@@ -1542,7 +1542,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x140007,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 1, 2, 3 },
-               .gpiomute       = 4,
+               .gpiomute       = 4,
                .tuner_type     = TUNER_PHILIPS_NTSC,
                .tuner_addr     = ADDR_UNSET,
                .audio_mode_gpio= windvr_audio,
@@ -1575,7 +1575,7 @@ struct tvcard bttv_tvcards[] = {
                                                * gpiomux =1: lower volume, 2+3: mute
                                                * btwincap uses 0x80000/0x80003
                                                */
-               .gpiomute       = 4,
+               .gpiomute       = 4,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
@@ -1626,7 +1626,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x0f0f80,
                .muxsel         = MUXSEL(2, 3, 1, 0),
                .gpiomux        = {0x030000, 0x010000, 0, 0 },
-               .gpiomute       = 0x020000,
+               .gpiomute       = 0x020000,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_NTSC_M,
@@ -1829,7 +1829,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 1, 2, 3},
-               .gpiomute       = 4,
+               .gpiomute       = 4,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
                .pll            = PLL_28,
@@ -1872,7 +1872,7 @@ struct tvcard bttv_tvcards[] = {
                .muxsel         = MUXSEL(2, 3, 1, 0),
                /*                  Tuner, Radio, external, internal, off,  on */
                .gpiomux        = { 0x08,  0x0f,  0x0a,     0x08 },
-               .gpiomute       = 0x0f,
+               .gpiomute       = 0x0f,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_NTSC,
@@ -2139,7 +2139,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x008007,
                .muxsel         = MUXSEL(2, 3, 0, 0),
                .gpiomux        = { 0, 0, 0, 0 },
-               .gpiomute       = 0x000003,
+               .gpiomute       = 0x000003,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -2182,7 +2182,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x008007,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 1, 2, 2 },
-               .gpiomute       = 3,
+               .gpiomute       = 3,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -2297,7 +2297,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0xFF,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 2, 0, 0, 0 },
-               .gpiomute       = 10,
+               .gpiomute       = 10,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_PAL,
                .tuner_addr     = ADDR_UNSET,
@@ -2326,7 +2326,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x3f,
                .muxsel         = MUXSEL(2, 3, 1, 0),
                .gpiomux        = {0x31, 0x31, 0x31, 0x31 },
-               .gpiomute       = 0x31,
+               .gpiomute       = 0x31,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_NTSC_M,
@@ -2440,7 +2440,7 @@ struct tvcard bttv_tvcards[] = {
                .muxsel         = MUXSEL(2, 3, 1),
                .gpiomask       = 0x00e00007,
                .gpiomux        = { 0x00400005, 0, 0x00000001, 0 },
-               .gpiomute       = 0x00c00007,
+               .gpiomute       = 0x00c00007,
                .no_msp34xx     = 1,
                .no_tda7432     = 1,
                .has_dvb        = 1,
@@ -2455,7 +2455,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x01fe00,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0x001e00, 0, 0x018000, 0x014000 },
-               .gpiomute       = 0x002000,
+               .gpiomute       = 0x002000,
                .pll            = PLL_28,
                .tuner_type     = TUNER_YMEC_TVF66T5_B_DFF,
                .tuner_addr     = 0xc1 >>1,
@@ -2470,7 +2470,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x001c0007,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 1, 2, 2 },
-               .gpiomute       = 3,
+               .gpiomute       = 3,
                .pll            = PLL_28,
                .tuner_type     = TUNER_TENA_9533_DI,
                .tuner_addr     = ADDR_UNSET,
@@ -2505,7 +2505,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x3f,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0x21, 0x20, 0x24, 0x2c },
-               .gpiomute       = 0x29,
+               .gpiomute       = 0x29,
                .no_msp34xx     = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_YMEC_TVF_5533MF,
@@ -2549,8 +2549,8 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 15,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 2, 0, 0, 0 },
-               .gpiomute       = 1,
+               .gpiomux        = { 2, 0, 0, 0 },
+               .gpiomute       = 1,
                .pll            = PLL_28,
                .tuner_type     = TUNER_PHILIPS_NTSC,
                .tuner_addr     = ADDR_UNSET,
@@ -2563,7 +2563,7 @@ struct tvcard bttv_tvcards[] = {
                .svhs           = 2,
                .gpiomask       = 0x108007,
                .muxsel         = MUXSEL(2, 3, 1, 1),
-               .gpiomux        = { 100000, 100002, 100002, 100000 },
+               .gpiomux        = { 100000, 100002, 100002, 100000 },
                .no_msp34xx     = 1,
                .no_tda7432     = 1,
                .pll            = PLL_28,
@@ -2599,7 +2599,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 7,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 1, 2, 3 },
-               .gpiomute       = 4,
+               .gpiomute       = 4,
                .tuner_type     = TUNER_TEMIC_4009FR5_PAL,
                .tuner_addr     = ADDR_UNSET,
                .pll            = PLL_28,
@@ -2635,7 +2635,7 @@ struct tvcard bttv_tvcards[] = {
                .muxsel         = MUXSEL(2, 3, 1),
                .gpiomask       = 0x00e00007,
                .gpiomux        = { 0x00400005, 0, 0x00000001, 0 },
-               .gpiomute       = 0x00c00007,
+               .gpiomute       = 0x00c00007,
                .no_msp34xx     = 1,
                .no_tda7432     = 1,
        },
@@ -2679,7 +2679,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x008007,
                .muxsel         = MUXSEL(2, 3, 1, 1),
                .gpiomux        = { 0, 1, 2, 2 }, /* CONTVFMi */
-               .gpiomute       = 3, /* CONTVFMi */
+               .gpiomute       = 3, /* CONTVFMi */
                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* TCL MK3 */
                .tuner_addr     = ADDR_UNSET,
                .pll            = PLL_28,
@@ -2702,7 +2702,7 @@ struct tvcard bttv_tvcards[] = {
                .gpiomask       = 0x060040,
                .muxsel         = MUXSEL(2, 3, 3),
                .gpiomux        = { 0x60000, 0x60000, 0x20000, 0x20000 },
-               .gpiomute       = 0,
+               .gpiomute       = 0,
                .tuner_type     = TUNER_TCL_MF02GIP_5N,
                .tuner_addr     = ADDR_UNSET,
                .pll            = PLL_28,
@@ -2752,8 +2752,8 @@ struct tvcard bttv_tvcards[] = {
                /* Bruno Christo <bchristo@inf.ufsm.br>
                 *
                 * GeoVision GV-800(S) has 4 Conexant Fusion 878A:
-                *      1 audio input  per BT878A = 4 audio inputs
-                *      4 video inputs per BT878A = 16 video inputs
+                *      1 audio input  per BT878A = 4 audio inputs
+                *      4 video inputs per BT878A = 16 video inputs
                 * This is the first BT878A chip of the GV-800(S). It's the
                 * "master" chip and it controls the video inputs through an
                 * analog multiplexer (a CD22M3494) via some GPIO pins. The
@@ -2779,8 +2779,8 @@ struct tvcard bttv_tvcards[] = {
                /* Bruno Christo <bchristo@inf.ufsm.br>
                 *
                 * GeoVision GV-800(S) has 4 Conexant Fusion 878A:
-                *      1 audio input  per BT878A = 4 audio inputs
-                *      4 video inputs per BT878A = 16 video inputs
+                *      1 audio input  per BT878A = 4 audio inputs
+                *      4 video inputs per BT878A = 16 video inputs
                 * The 3 other BT878A chips are "slave" chips of the GV-800(S)
                 * and should use this card type.
                 * The audio input is not working yet.
@@ -4784,9 +4784,9 @@ static void gv800s_write(struct bttv *btv,
        * GPIO bits 0-9 are used for the analog switch:
        *   00 - 03:    camera selector
        *   04 - 06:    878A (controller) selector
-       *   16:         cselect
+       *   16:         cselect
        *   17:         strobe
-       *   18:         data (1->on, 0->off)
+       *   18:         data (1->on, 0->off)
        *   19:         reset
        */
        const u32 ADDRESS = ((xaddr&0xf) | (yaddr&3)<<4);
@@ -4882,7 +4882,7 @@ void __init bttv_check_chipset(void)
        int pcipci_fail = 0;
        struct pci_dev *dev = NULL;
 
-       if (pci_pci_problems & (PCIPCI_FAIL|PCIAGP_FAIL))       /* should check if target is AGP */
+       if (pci_pci_problems & (PCIPCI_FAIL|PCIAGP_FAIL))       /* should check if target is AGP */
                pcipci_fail = 1;
        if (pci_pci_problems & (PCIPCI_TRITON|PCIPCI_NATOMA|PCIPCI_VIAETBF))
                triton1 = 1;
index ac7674700685d443357ff98a9402150a437f2f15..da49c5567db5045eb33842a7cb923db1826d6db3 100644 (file)
@@ -349,12 +349,12 @@ static int get_key_pv951(struct IR_i2c *ir, enum rc_proto *protocol,
         * NOTE:
         * lirc_i2c maps the pv951 code as:
         *      addr = 0x61D6
-        *      cmd = bit_reverse (b)
+        *      cmd = bit_reverse (b)
         * So, it seems that this device uses NEC extended
         * I decided to not fix the table, due to two reasons:
-        *      1) Without the actual device, this is only a guess;
-        *      2) As the addr is not reported via I2C, nor can be changed,
-        *         the device is bound to the vendor-provided RC.
+        *      1) Without the actual device, this is only a guess;
+        *      2) As the addr is not reported via I2C, nor can be changed,
+        *         the device is bound to the vendor-provided RC.
         */
 
        *protocol = RC_PROTO_UNKNOWN;
index cc555a4d4462c1491039f1b1f5b338c45d66c01b..a27384adadd2ef95996c1bad407ffcf7574347e6 100644 (file)
 #define BTTV_BOARD_PV_M4900                0x8b
 #define BTTV_BOARD_OSPREY440               0x8c
 #define BTTV_BOARD_ASOUND_SKYEYE          0x8d
-#define BTTV_BOARD_SABRENT_TVFM           0x8e
+#define BTTV_BOARD_SABRENT_TVFM                   0x8e
 #define BTTV_BOARD_HAUPPAUGE_IMPACTVCB     0x8f
 #define BTTV_BOARD_MACHTV_MAGICTV          0x90
 #define BTTV_BOARD_SSAI_SECURITY          0x91
@@ -265,7 +265,7 @@ extern struct tvcard bttv_tvcards[];
  * that they are changed to octal.  One should not use hex number, macros, or
  * anything else with this macro.  Just use plain integers from 0 to 3.
  */
-#define _MUXSELf(a)            0##a << 30
+#define _MUXSELf(a)            0##a << 30
 #define _MUXSELe(a, b...)      0##a << 28 | _MUXSELf(b)
 #define _MUXSELd(a, b...)      0##a << 26 | _MUXSELe(b)
 #define _MUXSELc(a, b...)      0##a << 24 | _MUXSELd(b)
index cb1b5e61113015453734048a5be566f39b9f89a4..7a86e729516677695473e44b479d639596224e0a 100644 (file)
@@ -141,7 +141,7 @@ struct bttv_ir {
        bool                    rc5_gpio;   /* Is RC5 legacy GPIO enabled? */
        u32                     last_bit;   /* last raw bit seen */
        u32                     code;       /* raw code under construction */
-       ktime_t                                         base_time;  /* time of last seen code */
+       ktime_t                                         base_time;  /* time of last seen code */
        bool                    active;     /* building raw code */
 };
 
@@ -400,8 +400,8 @@ struct bttv {
        int                        i2c_state, i2c_rc;
        int                        i2c_done;
        wait_queue_head_t          i2c_queue;
-       struct v4l2_subdev        *sd_msp34xx;
-       struct v4l2_subdev        *sd_tvaudio;
+       struct v4l2_subdev        *sd_msp34xx;
+       struct v4l2_subdev        *sd_tvaudio;
        struct v4l2_subdev        *sd_tda7432;
 
        /* video4linux (1) */
index aadd76466aecb5b90ba4b3eb912654d3baee6781..4f31042a442ace9562bd348661d26fb88e8f3d58 100644 (file)
@@ -41,7 +41,7 @@ MODULE_PARM_DESC(pcm_debug, "enable debug messages for pcm");
 #define dprintk(fmt, arg...) do {                                      \
            if (pcm_debug)                                              \
                printk(KERN_INFO "cx18-alsa-pcm %s: " fmt,              \
-                                 __func__, ##arg);                     \
+                                 __func__, ##arg);                     \
        } while (0)
 
 static const struct snd_pcm_hardware snd_cx18_hw_capture = {
index 8b95e9aae576c33e85b4c83680d9872b401dfba0..3abc54cbe4a16b3e45a878ccdc279f0cbfcafc17 100644 (file)
@@ -31,7 +31,7 @@ static int set_audclk_freq(struct cx18 *cx, u32 freq)
         * would ideally be:
         *
         * NTSC Color subcarrier freq * 8 =
-        *      4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
+        *      4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
         *
         * The accidents of history and rationale that explain from where this
         * combination of magic numbers originate can be found in:
index cf8817e9c8b9b7f10905c7ad1201ac73269da8d7..eda343322ee0c98dbb0cb1568036bb8f167e1d05 100644 (file)
@@ -236,10 +236,10 @@ static void cx18_av_initialize(struct v4l2_subdev *sd)
         */
        cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
 
-/*     if(dwEnable && dw3DCombAvailable) { */
-/*             CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
+/*     if(dwEnable && dw3DCombAvailable) { */
+/*             CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
 /*    } else { */
-/*             CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
+/*             CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
 /*    } */
        cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
        default_volume = cx18_av_read(cx, 0x8d4);
@@ -319,13 +319,13 @@ void cx18_av_std_setup(struct cx18 *cx)
                 * vblank656: half lines after line 625/mid-313 of blanked video
                 * vblank:    half lines, after line 5/317, of blanked video
                 * vactive:   half lines of active video +
-                *              5 half lines after the end of active video
+                *              5 half lines after the end of active video
                 *
                 * As far as I can tell:
                 * vblank656 starts counting from the falling edge of the first
-                *      vsync pulse (start of line 1 or mid-313)
+                *      vsync pulse (start of line 1 or mid-313)
                 * vblank starts counting from the after the 5 vsync pulses and
-                *      5 or 4 equalization pulses (start of line 6 or 318)
+                *      5 or 4 equalization pulses (start of line 6 or 318)
                 *
                 * For 625 line systems the driver will extract VBI information
                 * from lines 6-23 and lines 318-335 (but the slicer can only
@@ -395,9 +395,9 @@ void cx18_av_std_setup(struct cx18 *cx)
                 *
                 * As far as I can tell:
                 * vblank656 starts counting from the falling edge of the first
-                *      vsync pulse (start of line 4 or mid-266)
+                *      vsync pulse (start of line 4 or mid-266)
                 * vblank starts counting from the after the 6 vsync pulses and
-                *      6 or 5 equalization pulses (start of line 10 or 272)
+                *      6 or 5 equalization pulses (start of line 10 or 272)
                 *
                 * For 525 line systems the driver will extract VBI information
                 * from lines 10-21 and lines 273-284.
@@ -851,7 +851,7 @@ static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
        struct cx18_av_state *state = to_cx18_av_state(sd);
        struct cx18 *cx = v4l2_get_subdevdata(sd);
 
-       u8 fmt = 0;     /* zero is autodetect */
+       u8 fmt = 0;     /* zero is autodetect */
        u8 pal_m = 0;
 
        if (state->radio == 0 && state->std == norm)
index c976ce6e7a78aa2f1bccb41393e0e6bdaaab13df..1a37f269d2e46051db252d5af5c70b110a20120e 100644 (file)
@@ -349,7 +349,7 @@ static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 }
 
 /* ----------------------------------------------------------------------- */
-/* cx18_av-core.c                                                         */
+/* cx18_av-core.c                                                         */
 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
index 11e898e66ce907f2dae812e9f87d620f55bad3da..c2cf965d639e8d89e613e078ce2eab69054d45f4 100644 (file)
@@ -388,7 +388,7 @@ static const struct cx18_card cx18_card_cnxt_raptor_pal = {
                { CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 },
        },
        .audio_inputs = {
-               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
+               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
                { CX18_CARD_INPUT_LINE_IN1,  CX18_AV_AUDIO_SERIAL1, 1 },
                { CX18_CARD_INPUT_LINE_IN2,  CX18_AV_AUDIO_SERIAL2, 1 },
        },
@@ -439,7 +439,7 @@ static const struct cx18_card cx18_card_toshiba_qosmio_dvbt = {
                { CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
        },
        .audio_inputs = {
-               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
+               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
                { CX18_CARD_INPUT_LINE_IN1,  CX18_AV_AUDIO_SERIAL1, 1 },
        },
        .tuners = {
@@ -485,7 +485,7 @@ static const struct cx18_card cx18_card_leadtek_pvr2100 = {
                { CX18_CARD_INPUT_COMPONENT1, 1, CX18_AV_COMPONENT1 },
        },
        .audio_inputs = {
-               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
+               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
                { CX18_CARD_INPUT_LINE_IN1,  CX18_AV_AUDIO_SERIAL1, 1 },
        },
        .tuners = {
@@ -538,7 +538,7 @@ static const struct cx18_card cx18_card_leadtek_dvr3100h = {
                { CX18_CARD_INPUT_COMPONENT1, 1, CX18_AV_COMPONENT1 },
        },
        .audio_inputs = {
-               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
+               { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
                { CX18_CARD_INPUT_LINE_IN1,  CX18_AV_AUDIO_SERIAL1, 1 },
        },
        .tuners = {
index 5478f62b5cf3df0fdbb6db1cfea1b87d5877b535..02d0fb703a41dea11a58079085d8dccb01629806 100644 (file)
 
 /* video inputs */
 #define        CX18_CARD_INPUT_VID_TUNER       1
-#define        CX18_CARD_INPUT_SVIDEO1         2
-#define        CX18_CARD_INPUT_SVIDEO2         3
-#define        CX18_CARD_INPUT_COMPOSITE1      4
-#define        CX18_CARD_INPUT_COMPOSITE2      5
-#define        CX18_CARD_INPUT_COMPONENT1      6
+#define        CX18_CARD_INPUT_SVIDEO1         2
+#define        CX18_CARD_INPUT_SVIDEO2         3
+#define        CX18_CARD_INPUT_COMPOSITE1      4
+#define        CX18_CARD_INPUT_COMPOSITE2      5
+#define        CX18_CARD_INPUT_COMPONENT1      6
 
 /* audio inputs */
 #define        CX18_CARD_INPUT_AUD_TUNER       1
-#define        CX18_CARD_INPUT_LINE_IN1        2
-#define        CX18_CARD_INPUT_LINE_IN2        3
+#define        CX18_CARD_INPUT_LINE_IN1        2
+#define        CX18_CARD_INPUT_LINE_IN2        3
 
 #define CX18_CARD_MAX_VIDEO_INPUTS 6
 #define CX18_CARD_MAX_AUDIO_INPUTS 3
-#define CX18_CARD_MAX_TUNERS      2
+#define CX18_CARD_MAX_TUNERS      2
 
 /* V4L2 capability aliases */
 #define CX18_CAP_ENCODER (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TUNER | \
@@ -51,7 +51,7 @@
                          V4L2_CAP_SLICED_VBI_CAPTURE)
 
 struct cx18_card_video_input {
-       u8  video_type;         /* video input type */
+       u8  video_type;         /* video input type */
        u8  audio_index;        /* index in cx18_card_audio_input array */
        u32 video_input;        /* hardware video input */
 };
@@ -74,7 +74,7 @@ struct cx18_card_pci_info {
 /* The mask is the set of bits used by the operation */
 
 struct cx18_gpio_init { /* set initial GPIO DIR and OUT values */
-       u32 direction;  /* DIR setting. Leave to 0 if no init is needed */
+       u32 direction;  /* DIR setting. Leave to 0 if no init is needed */
        u32 initial_value;
 };
 
@@ -86,16 +86,16 @@ struct cx18_gpio_i2c_slave_reset {
        u32 ir_reset_mask;  /* GPIO to reset the Zilog Z8F0811 IR contoller */
 };
 
-struct cx18_gpio_audio_input {         /* select tuner/line in input */
-       u32 mask;               /* leave to 0 if not supported */
+struct cx18_gpio_audio_input { /* select tuner/line in input */
+       u32 mask;               /* leave to 0 if not supported */
        u32 tuner;
        u32 linein;
        u32 radio;
 };
 
 struct cx18_card_tuner {
-       v4l2_std_id std;        /* standard for which the tuner is suitable */
-       int         tuner;      /* tuner ID (from tuner.h) */
+       v4l2_std_id std;        /* standard for which the tuner is suitable */
+       int         tuner;      /* tuner ID (from tuner.h) */
 };
 
 struct cx18_card_tuner_i2c {
@@ -128,8 +128,8 @@ struct cx18_card {
        struct cx18_card_audio_input radio_input;
 
        /* GPIO card-specific settings */
-       u8 xceive_pin;          /* XCeive tuner GPIO reset pin */
-       struct cx18_gpio_init            gpio_init;
+       u8 xceive_pin;          /* XCeive tuner GPIO reset pin */
+       struct cx18_gpio_init            gpio_init;
        struct cx18_gpio_i2c_slave_reset gpio_i2c_slave_reset;
        struct cx18_gpio_audio_input    gpio_audio_input;
 
index 3492023a867590198b8b5de203508294d0fb2a5c..0b707faca543ccc34513282b479fbd9b2c0706c9 100644 (file)
@@ -75,8 +75,8 @@
 /* Supported cards */
 #define CX18_CARD_HVR_1600_ESMT              0 /* Hauppauge HVR 1600 (ESMT memory) */
 #define CX18_CARD_HVR_1600_SAMSUNG    1        /* Hauppauge HVR 1600 (Samsung memory) */
-#define CX18_CARD_COMPRO_H900        2 /* Compro VideoMate H900 */
-#define CX18_CARD_YUAN_MPC718        3 /* Yuan MPC718 */
+#define CX18_CARD_COMPRO_H900        2 /* Compro VideoMate H900 */
+#define CX18_CARD_YUAN_MPC718        3 /* Yuan MPC718 */
 #define CX18_CARD_CNXT_RAPTOR_PAL     4        /* Conexant Raptor PAL */
 #define CX18_CARD_TOSHIBA_QOSMIO_DVBT 5 /* Toshiba Qosmio Interal DVB-T/Analog*/
 #define CX18_CARD_LEADTEK_PVR2100     6 /* Leadtek WinFast PVR2100 */
@@ -99,9 +99,9 @@
 #define PCI_DEVICE_ID_CX23418 0x5b7a
 
 /* subsystem vendor ID */
-#define CX18_PCI_ID_HAUPPAUGE          0x0070
-#define CX18_PCI_ID_COMPRO             0x185b
-#define CX18_PCI_ID_YUAN               0x12ab
+#define CX18_PCI_ID_HAUPPAUGE          0x0070
+#define CX18_PCI_ID_COMPRO             0x185b
+#define CX18_PCI_ID_YUAN               0x12ab
 #define CX18_PCI_ID_CONEXANT           0x14f1
 #define CX18_PCI_ID_TOSHIBA            0x1179
 #define CX18_PCI_ID_LEADTEK            0x107D
@@ -260,7 +260,7 @@ struct cx18_options {
 #define CX18_F_M_NEED_SWAP  0  /* mdl buffer data must be endianness swapped */
 
 /* per-stream, s_flags */
-#define CX18_F_S_CLAIMED       3       /* this stream is claimed */
+#define CX18_F_S_CLAIMED       3       /* this stream is claimed */
 #define CX18_F_S_STREAMING      4      /* the fw is decoding/encoding this stream */
 #define CX18_F_S_INTERNAL_USE  5       /* this stream is used internally (sliced VBI processing) */
 #define CX18_F_S_STREAMOFF     7       /* signal end of stream EOS */
@@ -268,12 +268,12 @@ struct cx18_options {
 #define CX18_F_S_STOPPING      9       /* telling the fw to stop capturing */
 
 /* per-cx18, i_flags */
-#define CX18_F_I_LOADED_FW             0       /* Loaded firmware 1st time */
-#define CX18_F_I_EOS                   4       /* End of encoder stream */
-#define CX18_F_I_RADIO_USER            5       /* radio tuner is selected */
-#define CX18_F_I_ENC_PAUSED            13      /* the encoder is paused */
-#define CX18_F_I_INITED                        21      /* set after first open */
-#define CX18_F_I_FAILED                        22      /* set if first open failed */
+#define CX18_F_I_LOADED_FW             0       /* Loaded firmware 1st time */
+#define CX18_F_I_EOS                   4       /* End of encoder stream */
+#define CX18_F_I_RADIO_USER            5       /* radio tuner is selected */
+#define CX18_F_I_ENC_PAUSED            13      /* the encoder is paused */
+#define CX18_F_I_INITED                        21      /* set after first open */
+#define CX18_F_I_FAILED                        22      /* set if first open failed */
 
 /* These are the VBI types as they appear in the embedded VBI private packets. */
 #define CX18_SLICED_TYPE_TELETEXT_B     (1)
@@ -370,7 +370,7 @@ struct cx18_stream {
           is not actually created. */
        struct video_device video_dev;  /* v4l2_dev is NULL when stream not created */
        struct cx18_dvb *dvb;           /* DVB / Digital Transport */
-       struct cx18 *cx;                /* for ease of use */
+       struct cx18 *cx;                /* for ease of use */
        const char *name;               /* name of the stream */
        int type;                       /* stream type */
        u32 handle;                     /* task handle */
@@ -525,14 +525,14 @@ struct vbi_info {
         * into the MPEG PS stream.
         *
         * In each sliced_mpeg_data[] buffer is:
-        *      16 byte MPEG-2 PS Program Pack Header
-        *      16 byte MPEG-2 Private Stream 1 PES Header
-        *       4 byte magic number: "itv0" or "ITV0"
-        *       4 byte first  field line mask, if "itv0"
-        *       4 byte second field line mask, if "itv0"
-        *      36 lines, if "ITV0"; or <36 lines, if "itv0"; of sliced VBI data
+        *      16 byte MPEG-2 PS Program Pack Header
+        *      16 byte MPEG-2 Private Stream 1 PES Header
+        *       4 byte magic number: "itv0" or "ITV0"
+        *       4 byte first  field line mask, if "itv0"
+        *       4 byte second field line mask, if "itv0"
+        *      36 lines, if "ITV0"; or <36 lines, if "itv0"; of sliced VBI data
         *
-        *      Each line in the payload is
+        *      Each line in the payload is
         *       1 byte line header derived from the SDID (WSS, CC, VPS, etc.)
         *      42 bytes of line data
         *
@@ -583,7 +583,7 @@ struct cx18 {
        u8 nof_inputs;          /* number of video inputs */
        u8 nof_audio_inputs;    /* number of audio inputs */
        u32 v4l2_cap;           /* V4L2 capabilities of card */
-       u32 hw_flags;           /* Hardware description of the board */
+       u32 hw_flags;           /* Hardware description of the board */
        unsigned int free_mdl_idx;
        struct cx18_scb __iomem *scb; /* pointer to SCB */
        struct mutex epu2apu_mb_lock; /* protect driver to chip mailbox in SCB*/
@@ -602,10 +602,10 @@ struct cx18 {
        u32 dualwatch_stereo_mode;
 
        struct mutex serialize_lock;    /* mutex used to serialize open/close/start/stop/ioctl operations */
-       struct cx18_options options;    /* User options */
+       struct cx18_options options;    /* User options */
        int stream_buffers[CX18_MAX_STREAMS]; /* # of buffers for each stream */
        int stream_buf_size[CX18_MAX_STREAMS]; /* Stream buffer size */
-       struct cx18_stream streams[CX18_MAX_STREAMS];   /* Stream data */
+       struct cx18_stream streams[CX18_MAX_STREAMS];   /* Stream data */
        struct snd_cx18_card *alsa; /* ALSA interface for PCM capture stream */
        void (*pcm_announce_callback)(struct snd_cx18_card *card, u8 *pcm_data,
                                      size_t num_bytes);
index 1b34ea1c3730561c5b24d6c6283072c3cb2dafbd..498a1854b3b05031b461749db85c43793f625e35 100644 (file)
 #include "cx18-cards.h"
 #include <linux/firmware.h>
 
-#define CX18_PROC_SOFT_RESET           0xc70010
-#define CX18_DDR_SOFT_RESET            0xc70014
-#define CX18_CLOCK_SELECT1             0xc71000
-#define CX18_CLOCK_SELECT2             0xc71004
-#define CX18_HALF_CLOCK_SELECT1        0xc71008
-#define CX18_HALF_CLOCK_SELECT2        0xc7100C
-#define CX18_CLOCK_POLARITY1           0xc71010
-#define CX18_CLOCK_POLARITY2           0xc71014
-#define CX18_ADD_DELAY_ENABLE1         0xc71018
-#define CX18_ADD_DELAY_ENABLE2         0xc7101C
-#define CX18_CLOCK_ENABLE1             0xc71020
-#define CX18_CLOCK_ENABLE2             0xc71024
-
-#define CX18_REG_BUS_TIMEOUT_EN        0xc72024
-
-#define CX18_FAST_CLOCK_PLL_INT        0xc78000
-#define CX18_FAST_CLOCK_PLL_FRAC       0xc78004
-#define CX18_FAST_CLOCK_PLL_POST       0xc78008
-#define CX18_FAST_CLOCK_PLL_PRESCALE   0xc7800C
+#define CX18_PROC_SOFT_RESET           0xc70010
+#define CX18_DDR_SOFT_RESET            0xc70014
+#define CX18_CLOCK_SELECT1             0xc71000
+#define CX18_CLOCK_SELECT2             0xc71004
+#define CX18_HALF_CLOCK_SELECT1                0xc71008
+#define CX18_HALF_CLOCK_SELECT2                0xc7100C
+#define CX18_CLOCK_POLARITY1           0xc71010
+#define CX18_CLOCK_POLARITY2           0xc71014
+#define CX18_ADD_DELAY_ENABLE1         0xc71018
+#define CX18_ADD_DELAY_ENABLE2         0xc7101C
+#define CX18_CLOCK_ENABLE1             0xc71020
+#define CX18_CLOCK_ENABLE2             0xc71024
+
+#define CX18_REG_BUS_TIMEOUT_EN                0xc72024
+
+#define CX18_FAST_CLOCK_PLL_INT                0xc78000
+#define CX18_FAST_CLOCK_PLL_FRAC       0xc78004
+#define CX18_FAST_CLOCK_PLL_POST       0xc78008
+#define CX18_FAST_CLOCK_PLL_PRESCALE   0xc7800C
 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
 
-#define CX18_SLOW_CLOCK_PLL_INT        0xc78014
-#define CX18_SLOW_CLOCK_PLL_FRAC       0xc78018
-#define CX18_SLOW_CLOCK_PLL_POST       0xc7801C
+#define CX18_SLOW_CLOCK_PLL_INT                0xc78014
+#define CX18_SLOW_CLOCK_PLL_FRAC       0xc78018
+#define CX18_SLOW_CLOCK_PLL_POST       0xc7801C
 #define CX18_MPEG_CLOCK_PLL_INT                0xc78040
 #define CX18_MPEG_CLOCK_PLL_FRAC       0xc78044
 #define CX18_MPEG_CLOCK_PLL_POST       0xc78048
-#define CX18_PLL_POWER_DOWN            0xc78088
+#define CX18_PLL_POWER_DOWN            0xc78088
 #define CX18_SW1_INT_STATUS             0xc73104
 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
 #define CX18_SW2_INT_SET                0xc73140
 #define CX18_SW2_INT_STATUS             0xc73144
-#define CX18_ADEC_CONTROL              0xc78120
+#define CX18_ADEC_CONTROL              0xc78120
 
-#define CX18_DDR_REQUEST_ENABLE        0xc80000
-#define CX18_DDR_CHIP_CONFIG           0xc80004
-#define CX18_DDR_REFRESH               0xc80008
-#define CX18_DDR_TIMING1               0xc8000C
-#define CX18_DDR_TIMING2               0xc80010
+#define CX18_DDR_REQUEST_ENABLE                0xc80000
+#define CX18_DDR_CHIP_CONFIG           0xc80004
+#define CX18_DDR_REFRESH               0xc80008
+#define CX18_DDR_TIMING1               0xc8000C
+#define CX18_DDR_TIMING2               0xc80010
 #define CX18_DDR_POWER_REG             0xc8001C
 
-#define CX18_DDR_TUNE_LANE             0xc80048
-#define CX18_DDR_INITIAL_EMRS          0xc80054
-#define CX18_DDR_MB_PER_ROW_7          0xc8009C
-#define CX18_DDR_BASE_63_ADDR          0xc804FC
-
-#define CX18_WMB_CLIENT02              0xc90108
-#define CX18_WMB_CLIENT05              0xc90114
-#define CX18_WMB_CLIENT06              0xc90118
-#define CX18_WMB_CLIENT07              0xc9011C
-#define CX18_WMB_CLIENT08              0xc90120
-#define CX18_WMB_CLIENT09              0xc90124
-#define CX18_WMB_CLIENT10              0xc90128
-#define CX18_WMB_CLIENT11              0xc9012C
-#define CX18_WMB_CLIENT12              0xc90130
-#define CX18_WMB_CLIENT13              0xc90134
-#define CX18_WMB_CLIENT14              0xc90138
-
-#define CX18_DSP0_INTERRUPT_MASK       0xd0004C
+#define CX18_DDR_TUNE_LANE             0xc80048
+#define CX18_DDR_INITIAL_EMRS          0xc80054
+#define CX18_DDR_MB_PER_ROW_7          0xc8009C
+#define CX18_DDR_BASE_63_ADDR          0xc804FC
+
+#define CX18_WMB_CLIENT02              0xc90108
+#define CX18_WMB_CLIENT05              0xc90114
+#define CX18_WMB_CLIENT06              0xc90118
+#define CX18_WMB_CLIENT07              0xc9011C
+#define CX18_WMB_CLIENT08              0xc90120
+#define CX18_WMB_CLIENT09              0xc90124
+#define CX18_WMB_CLIENT10              0xc90128
+#define CX18_WMB_CLIENT11              0xc9012C
+#define CX18_WMB_CLIENT12              0xc90130
+#define CX18_WMB_CLIENT13              0xc90134
+#define CX18_WMB_CLIENT14              0xc90138
+
+#define CX18_DSP0_INTERRUPT_MASK       0xd0004C
 
 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
@@ -229,7 +229,7 @@ void cx18_init_power(struct cx18 *cx, int lowpwr)
         * would ideally be:
         *
         * NTSC Color subcarrier freq * 8 =
-        *      4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
+        *      4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
         *
         * The accidents of history and rationale that explain from where this
         * combination of magic numbers originate can be found in:
index 763f960fc918bbc22e230204fd1ffe752458c320..f66dd63e1994eb40e3df1d7c7dd725b2176f1495 100644 (file)
@@ -35,7 +35,7 @@ struct cx18_api_info {
        u32 cmd;
        u8 flags;               /* Flags, see above */
        u8 rpu;                 /* Processing unit */
-       const char *name;       /* The name of the command */
+       const char *name;       /* The name of the command */
 };
 
 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
@@ -43,9 +43,9 @@ struct cx18_api_info {
 static const struct cx18_api_info api_info[] = {
        /* MPEG encoder API */
        API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
-       API_ENTRY(CPU, CX18_EPU_DEBUG,                          0),
-       API_ENTRY(CPU, CX18_CREATE_TASK,                        0),
-       API_ENTRY(CPU, CX18_DESTROY_TASK,                       0),
+       API_ENTRY(CPU, CX18_EPU_DEBUG,                          0),
+       API_ENTRY(CPU, CX18_CREATE_TASK,                        0),
+       API_ENTRY(CPU, CX18_DESTROY_TASK,                       0),
        API_ENTRY(CPU, CX18_CPU_CAPTURE_START,                  API_SLOW),
        API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP,                   API_SLOW),
        API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE,                  0),
index b9c6831c21c3d0517c927f32bca543d90628406c..a594cfdeca200079337ae198a82a987999f8bcdd 100644 (file)
@@ -29,7 +29,7 @@
 #include "cx18-scb.h"
 #include "cx18-dvb.h"
 
-#define CX18_DSP0_INTERRUPT_MASK       0xd0004C
+#define CX18_DSP0_INTERRUPT_MASK       0xd0004C
 
 static const struct v4l2_file_operations cx18_v4l2_enc_fops = {
        .owner = THIS_MODULE,
index 72c74d60c6fbf6f5b711e32be144d54b7a969aaa..81f1e27436fda9017a8aa77bd42123fa2ef7436c 100644 (file)
@@ -47,7 +47,7 @@ static void copy_vbi_data(struct cx18 *cx, int lines, u32 pts_stamp)
                0x00, 0x00, 0x01, 0xbd,             /* Priv Stream 1 start */
                0x00, 0x1a,                         /* length */
                0x84, 0x80, 0x07,                   /* flags, hdr data len */
-               0x21, 0x00, 0x5d, 0x63, 0xa7,       /* PTS, markers */
+               0x21, 0x00, 0x5d, 0x63, 0xa7,       /* PTS, markers */
                0xff, 0xff                          /* stuffing */
        };
        const int sd = sizeof(mpeg_hdr_data);   /* start of vbi data */
index 901ed7fac10f00855ab214f80bfa3920561de56b..15205b6629522ede1be391805bdf6e5729ede52e 100644 (file)
 
 #include <media/drv-intf/cx2341x.h>
 
-#define MGR_CMD_MASK                           0x40000000
+#define MGR_CMD_MASK                           0x40000000
 /* The MSB of the command code indicates that this is the completion of a
    command */
-#define MGR_CMD_MASK_ACK                       (MGR_CMD_MASK | 0x80000000)
+#define MGR_CMD_MASK_ACK                       (MGR_CMD_MASK | 0x80000000)
 
 /* Description: This command creates a new instance of a certain task
    IN[0]  - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
    OUT[0] - Task handle. This handle is passed along with commands to
            dispatch to the right instance of the task
    ReturnCode - One of the ERR_SYS_... */
-#define CX18_CREATE_TASK                       (MGR_CMD_MASK | 0x0001)
+#define CX18_CREATE_TASK                       (MGR_CMD_MASK | 0x0001)
 
 /* Description: This command destroys an instance of a task
    IN[0] - Task handle. Hanlde of the task to destroy
    ReturnCode - One of the ERR_SYS_... */
-#define CX18_DESTROY_TASK                      (MGR_CMD_MASK | 0x0002)
+#define CX18_DESTROY_TASK                      (MGR_CMD_MASK | 0x0002)
 
 /* All commands for CPU have the following mask set */
-#define CPU_CMD_MASK                           0x20000000
-#define CPU_CMD_MASK_DEBUG                     (CPU_CMD_MASK | 0x00000000)
-#define CPU_CMD_MASK_ACK                       (CPU_CMD_MASK | 0x80000000)
-#define CPU_CMD_MASK_CAPTURE                   (CPU_CMD_MASK | 0x00020000)
-#define CPU_CMD_MASK_TS                        (CPU_CMD_MASK | 0x00040000)
+#define CPU_CMD_MASK                           0x20000000
+#define CPU_CMD_MASK_DEBUG                     (CPU_CMD_MASK | 0x00000000)
+#define CPU_CMD_MASK_ACK                       (CPU_CMD_MASK | 0x80000000)
+#define CPU_CMD_MASK_CAPTURE                   (CPU_CMD_MASK | 0x00020000)
+#define CPU_CMD_MASK_TS                                (CPU_CMD_MASK | 0x00040000)
 
-#define EPU_CMD_MASK                           0x02000000
-#define EPU_CMD_MASK_DEBUG                     (EPU_CMD_MASK | 0x000000)
-#define EPU_CMD_MASK_DE                        (EPU_CMD_MASK | 0x040000)
+#define EPU_CMD_MASK                           0x02000000
+#define EPU_CMD_MASK_DEBUG                     (EPU_CMD_MASK | 0x000000)
+#define EPU_CMD_MASK_DE                                (EPU_CMD_MASK | 0x040000)
 
-#define APU_CMD_MASK                           0x10000000
-#define APU_CMD_MASK_ACK                       (APU_CMD_MASK | 0x80000000)
+#define APU_CMD_MASK                           0x10000000
+#define APU_CMD_MASK_ACK                       (APU_CMD_MASK | 0x80000000)
 
 #define CX18_APU_ENCODING_METHOD_MPEG          (0 << 28)
 #define CX18_APU_ENCODING_METHOD_AC3           (1 << 28)
@@ -67,7 +67,7 @@
 
 /* Description: Command APU to reset the AI
    ReturnCode - ??? */
-#define CX18_APU_RESETAI                       (APU_CMD_MASK | 0x05)
+#define CX18_APU_RESETAI                       (APU_CMD_MASK | 0x05)
 
 /* Description: This command indicates that a Memory Descriptor List has been
    filled with the requested channel type
    IN[1] - Offset of the MDL_ACK from the beginning of the local DDR.
    IN[2] - Number of CNXT_MDL_ACK structures in the array pointed to by IN[1]
    ReturnCode - One of the ERR_DE_... */
-#define CX18_EPU_DMA_DONE                              (EPU_CMD_MASK_DE | 0x0001)
+#define CX18_EPU_DMA_DONE                      (EPU_CMD_MASK_DE | 0x0001)
 
 /* Something interesting happened
    IN[0] - A value to log
    IN[1] - An offset of a string in the MiniMe memory;
           0/zero/NULL means "I have nothing to say" */
-#define CX18_EPU_DEBUG                                 (EPU_CMD_MASK_DEBUG | 0x0003)
+#define CX18_EPU_DEBUG                         (EPU_CMD_MASK_DEBUG | 0x0003)
 
 /* Reads memory/registers (32-bit)
    IN[0] - Address
 /* Description: This command starts streaming with the set channel type
    IN[0] - Task handle. Handle of the task to start
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_CAPTURE_START                 (CPU_CMD_MASK_CAPTURE | 0x0002)
+#define CX18_CPU_CAPTURE_START                 (CPU_CMD_MASK_CAPTURE | 0x0002)
 
 /* Description: This command stops streaming with the set channel type
    IN[0] - Task handle. Handle of the task to stop
    IN[1] - 0 = stop at end of GOP, 1 = stop at end of frame (MPEG only)
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_CAPTURE_STOP                  (CPU_CMD_MASK_CAPTURE | 0x0003)
+#define CX18_CPU_CAPTURE_STOP                  (CPU_CMD_MASK_CAPTURE | 0x0003)
 
 /* Description: This command pauses streaming with the set channel type
    IN[0] - Task handle. Handle of the task to pause
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_CAPTURE_PAUSE                 (CPU_CMD_MASK_CAPTURE | 0x0007)
+#define CX18_CPU_CAPTURE_PAUSE                 (CPU_CMD_MASK_CAPTURE | 0x0007)
 
 /* Description: This command resumes streaming with the set channel type
    IN[0] - Task handle. Handle of the task to resume
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_CAPTURE_RESUME                (CPU_CMD_MASK_CAPTURE | 0x0008)
-
-#define CAPTURE_CHANNEL_TYPE_NONE              0
-#define CAPTURE_CHANNEL_TYPE_MPEG              1
-#define CAPTURE_CHANNEL_TYPE_INDEX             2
-#define CAPTURE_CHANNEL_TYPE_YUV               3
-#define CAPTURE_CHANNEL_TYPE_PCM               4
-#define CAPTURE_CHANNEL_TYPE_VBI               5
+#define CX18_CPU_CAPTURE_RESUME                        (CPU_CMD_MASK_CAPTURE | 0x0008)
+
+#define CAPTURE_CHANNEL_TYPE_NONE              0
+#define CAPTURE_CHANNEL_TYPE_MPEG              1
+#define CAPTURE_CHANNEL_TYPE_INDEX             2
+#define CAPTURE_CHANNEL_TYPE_YUV               3
+#define CAPTURE_CHANNEL_TYPE_PCM               4
+#define CAPTURE_CHANNEL_TYPE_VBI               5
 #define CAPTURE_CHANNEL_TYPE_SLICED_VBI                6
 #define CAPTURE_CHANNEL_TYPE_TS                        7
-#define CAPTURE_CHANNEL_TYPE_MAX               15
+#define CAPTURE_CHANNEL_TYPE_MAX               15
 
 /* Description: This command sets the channel type. This can only be done
    when stopped.
    IN[0] - Task handle. Handle of the task to start
    IN[1] - Channel Type. See Below.
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_SET_CHANNEL_TYPE                      (CPU_CMD_MASK_CAPTURE + 1)
+#define CX18_CPU_SET_CHANNEL_TYPE              (CPU_CMD_MASK_CAPTURE + 1)
 
 /* Description: Set stream output type
    IN[0] - task handle. Handle of the task to start
    IN[4] - reserved
    IN[5] - frame rate, 0 - 29.97f/s, 1 - 25f/s
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_SET_VIDEO_IN                  (CPU_CMD_MASK_CAPTURE | 0x0004)
+#define CX18_CPU_SET_VIDEO_IN                  (CPU_CMD_MASK_CAPTURE | 0x0004)
 
 /* Description: Set video frame rate
    IN[0] - task handle. Handle of the task to start
    IN[3] - video peak rate
    IN[4] - system mux rate
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_SET_VIDEO_RATE                (CPU_CMD_MASK_CAPTURE | 0x0005)
+#define CX18_CPU_SET_VIDEO_RATE                        (CPU_CMD_MASK_CAPTURE | 0x0005)
 
 /* Description: Set video output resolution
    IN[0] - task handle
                                3 = horizontal/vertical, 4 = diagonal
    IN[3] - strength, temporal 0 - 31, spatial 0 - 15
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_SET_FILTER_PARAM              (CPU_CMD_MASK_CAPTURE | 0x0009)
+#define CX18_CPU_SET_FILTER_PARAM              (CPU_CMD_MASK_CAPTURE | 0x0009)
 
 /* Description: This command set spatial filter type
    IN[0] - Task handle.
                      3 = 2D H/V separable, 4 = 2D symmetric non-separable
    IN[2] - chroma type: 0 - disable, 1 = 1D horizontal
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_SET_SPATIAL_FILTER_TYPE       (CPU_CMD_MASK_CAPTURE | 0x000C)
+#define CX18_CPU_SET_SPATIAL_FILTER_TYPE       (CPU_CMD_MASK_CAPTURE | 0x000C)
 
 /* Description: This command set coring levels for median filter
    IN[0] - Task handle.
    IN[3] - chroma_high
    IN[4] - chroma_low
    ReturnCode - One of the ERR_CAPTURE_... */
-#define CX18_CPU_SET_MEDIAN_CORING             (CPU_CMD_MASK_CAPTURE | 0x000E)
+#define CX18_CPU_SET_MEDIAN_CORING             (CPU_CMD_MASK_CAPTURE | 0x000E)
 
 /* Description: This command set the picture type mask for index file
    IN[0] - Task handle (ignored by firmware)
-   IN[1] -     0 = disable index file output
+   IN[1] -     0 = disable index file output
                        1 = output I picture
                        2 = P picture
                        4 = B picture
                        other = illegal */
-#define CX18_CPU_SET_INDEXTABLE                (CPU_CMD_MASK_CAPTURE | 0x0010)
+#define CX18_CPU_SET_INDEXTABLE                        (CPU_CMD_MASK_CAPTURE | 0x0010)
 
 /* Description: Set audio parameters
    IN[0] - task handle. Handle of the task to start
 /* Description: Set stream output type
    IN[0] - task handle. Handle of the task to start
    IN[1] - subType
-           SET_INITIAL_SCR                     1
+           SET_INITIAL_SCR                     1
            SET_QUALITY_MODE            2
            SET_VIM_PROTECT_MODE        3
            SET_PTS_CORRECTION          4
                        bit 0:  output user data, 1 - enable
                        bit 1:  output private stream, 1 - enable
                        bit 2:  mux option, 0 - in GOP, 1 - in picture
-                       bit[7:0]        private stream ID
+                       bit[7:0]        private stream ID
    IN[5] - insertion period while mux option is in picture
    ReturnCode - VBI data offset */
 #define CX18_CPU_SET_SLICED_VBI_PARAM          (CPU_CMD_MASK_CAPTURE | 0x0020)
 #define CX18_CPU_SET_VFC_PARAM                  (CPU_CMD_MASK_CAPTURE | 0x0023)
 
 /* Below is the list of commands related to the data exchange */
-#define CPU_CMD_MASK_DE                        (CPU_CMD_MASK | 0x040000)
+#define CPU_CMD_MASK_DE                                (CPU_CMD_MASK | 0x040000)
 
 /* Description: This command provides the physical base address of the local
    DDR as viewed by EPU
    IN[0] - Physical offset where EPU has the local DDR mapped
    ReturnCode - One of the ERR_DE_... */
-#define CPU_CMD_DE_SetBase                     (CPU_CMD_MASK_DE | 0x0001)
+#define CPU_CMD_DE_SetBase                     (CPU_CMD_MASK_DE | 0x0001)
 
 /* Description: This command provides the offsets in the device memory where
    the 2 cx18_mdl_ack blocks reside
    IN[2] - Offset of the second cx18_mdl_ack from the beginning of the
           local DDR.
    ReturnCode - One of the ERR_DE_... */
-#define CX18_CPU_DE_SET_MDL_ACK                        (CPU_CMD_MASK_DE | 0x0002)
+#define CX18_CPU_DE_SET_MDL_ACK                        (CPU_CMD_MASK_DE | 0x0002)
 
 /* Description: This command provides the offset to a Memory Descriptor List
    IN[0] - Task handle. Handle of the task to start
    IN[3] - Buffer ID
    IN[4] - Total buffer length
    ReturnCode - One of the ERR_DE_... */
-#define CX18_CPU_DE_SET_MDL                    (CPU_CMD_MASK_DE | 0x0005)
+#define CX18_CPU_DE_SET_MDL                    (CPU_CMD_MASK_DE | 0x0005)
 
 /* Description: This command requests return of all current Memory
    Descriptor Lists to the driver
    IN[0] - Task handle. Handle of the task to start
    ReturnCode - One of the ERR_DE_... */
-#define CX18_CPU_DE_RELEASE_MDL                (CPU_CMD_MASK_DE | 0x0006)
+#define CX18_CPU_DE_RELEASE_MDL                        (CPU_CMD_MASK_DE | 0x0006)
 
 /* Description: This command signals the cpu that the dat buffer has been
    consumed and ready for re-use.
index 96f75f658b1b9496bc1c315e665fc1548f9c293a..19c005f4a57d4ce51cc9ec8759860ade55183c75 100644 (file)
@@ -54,7 +54,7 @@
 #define NETUP_CI_CTL           0x04
 #define NETUP_CI_RD            1
 
-#define NETUP_IRQ_DETAM        0x1
+#define NETUP_IRQ_DETAM                0x1
 #define NETUP_IRQ_IRQAM                0x4
 
 static unsigned int ci_dbg;
index ecc580af01481d1cef7431aa201204af5f7fa00a..a03dcb6629530896835340c4d2786065488d2c82 100644 (file)
@@ -1146,7 +1146,7 @@ static struct video_device cx23885_vbi_template;
 static struct video_device cx23885_video_template = {
        .name                 = "cx23885-video",
        .fops                 = &video_fops,
-       .ioctl_ops            = &video_ioctl_ops,
+       .ioctl_ops            = &video_ioctl_ops,
        .tvnorms              = CX23885_NORMS,
 };
 
index 6aab713e047668444e8756595ff19edc1901dba5..2a17209eb4f637d65d65d947e3dd7b341840805f 100644 (file)
@@ -357,7 +357,7 @@ struct cx23885_audio_dev {
 
 struct cx23885_dev {
        atomic_t                   refcount;
-       struct v4l2_device         v4l2_dev;
+       struct v4l2_device         v4l2_dev;
        struct v4l2_ctrl_handler   ctrl_handler;
 
        /* pci stuff */
@@ -407,7 +407,7 @@ struct cx23885_dev {
        unsigned int               tuner_bus;
        unsigned int               radio_type;
        unsigned char              radio_addr;
-       struct v4l2_subdev         *sd_cx25840;
+       struct v4l2_subdev         *sd_cx25840;
        struct work_struct         cx25840_work;
 
        /* Infrared */
index b0d4e4437b8754780fbcfb7a95eeff8924859e86..00329f668b590260713d3dab844179398f55b465 100644 (file)
@@ -29,7 +29,7 @@ static unsigned int ir_888_debug;
 module_param(ir_888_debug, int, 0644);
 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
 
-#define CX23888_IR_REG_BASE    0x170000
+#define CX23888_IR_REG_BASE    0x170000
 /*
  * These CX23888 register offsets have a straightforward one to one mapping
  * to the CX23885 register offsets of 0x200 through 0x218
index 06e7b4ed6444829cfd4cdc769c026189850c23c4..1557a6ea4dd933ee2073d8afe8c114e3b73b3477 100644 (file)
 #define IVTV_CARDS_H
 
 /* Supported cards */
-#define IVTV_CARD_PVR_250            0 /* WinTV PVR 250 */
-#define IVTV_CARD_PVR_350            1 /* encoder, decoder, tv-out */
-#define IVTV_CARD_PVR_150            2 /* WinTV PVR 150 and PVR 500 (really just two
+#define IVTV_CARD_PVR_250            0 /* WinTV PVR 250 */
+#define IVTV_CARD_PVR_350            1 /* encoder, decoder, tv-out */
+#define IVTV_CARD_PVR_150            2 /* WinTV PVR 150 and PVR 500 (really just two
                                           PVR150s on one PCI board) */
-#define IVTV_CARD_M179               3 /* AVerMedia M179 (encoder only) */
-#define IVTV_CARD_MPG600             4 /* Kuroutoshikou ITVC16-STVLP/YUAN MPG600, encoder only */
-#define IVTV_CARD_MPG160             5 /* Kuroutoshikou ITVC15-STVLP/YUAN MPG160
+#define IVTV_CARD_M179               3 /* AVerMedia M179 (encoder only) */
+#define IVTV_CARD_MPG600             4 /* Kuroutoshikou ITVC16-STVLP/YUAN MPG600, encoder only */
+#define IVTV_CARD_MPG160             5 /* Kuroutoshikou ITVC15-STVLP/YUAN MPG160
                                           cx23415 based, but does not have tv-out */
-#define IVTV_CARD_PG600              6 /* YUAN PG600/DIAMONDMM PVR-550 based on the CX Falcon 2 */
-#define IVTV_CARD_AVC2410            7 /* Adaptec AVC-2410 */
-#define IVTV_CARD_AVC2010            8 /* Adaptec AVD-2010 (No Tuner) */
-#define IVTV_CARD_TG5000TV           9 /* NAGASE TRANSGEAR 5000TV, encoder only */
+#define IVTV_CARD_PG600                      6 /* YUAN PG600/DIAMONDMM PVR-550 based on the CX Falcon 2 */
+#define IVTV_CARD_AVC2410            7 /* Adaptec AVC-2410 */
+#define IVTV_CARD_AVC2010            8 /* Adaptec AVD-2010 (No Tuner) */
+#define IVTV_CARD_TG5000TV           9 /* NAGASE TRANSGEAR 5000TV, encoder only */
 #define IVTV_CARD_VA2000MAX_SNT6     10 /* VA2000MAX-STN6 */
-#define IVTV_CARD_CX23416GYC        11 /* Kuroutoshikou CX23416GYC-STVLP (Yuan MPG600GR OEM) */
-#define IVTV_CARD_GV_MVPRX          12 /* I/O Data GV-MVP/RX, RX2, RX2W */
-#define IVTV_CARD_GV_MVPRX2E        13 /* I/O Data GV-MVP/RX2E */
+#define IVTV_CARD_CX23416GYC        11 /* Kuroutoshikou CX23416GYC-STVLP (Yuan MPG600GR OEM) */
+#define IVTV_CARD_GV_MVPRX          12 /* I/O Data GV-MVP/RX, RX2, RX2W */
+#define IVTV_CARD_GV_MVPRX2E        13 /* I/O Data GV-MVP/RX2E */
 #define IVTV_CARD_GOTVIEW_PCI_DVD    14        /* GotView PCI DVD */
 #define IVTV_CARD_GOTVIEW_PCI_DVD2   15        /* GotView PCI DVD2 */
 #define IVTV_CARD_YUAN_MPC622        16        /* Yuan MPC622 miniPCI */
-#define IVTV_CARD_DCTMTVP1          17 /* DIGITAL COWBOY DCT-MTVP1 */
+#define IVTV_CARD_DCTMTVP1          17 /* DIGITAL COWBOY DCT-MTVP1 */
 #define IVTV_CARD_PG600V2           18 /* Yuan PG600V2/GotView PCI DVD Lite */
 #define IVTV_CARD_CLUB3D            19 /* Club3D ZAP-TV1x01 */
 #define IVTV_CARD_AVERTV_MCE116             20 /* AVerTV MCE 116 Plus */
@@ -52,7 +52,7 @@
 #define IVTV_CARD_BUFFALO_MV5L       25 /* Buffalo PC-MV5L/PCI card */
 #define IVTV_CARD_AVER_ULTRA1500MCE  26 /* AVerMedia UltraTV 1500 MCE */
 #define IVTV_CARD_KIKYOU             27 /* Sony VAIO Giga Pocket (ENX Kikyou) */
-#define IVTV_CARD_LAST                      27
+#define IVTV_CARD_LAST              27
 
 /* Variants of existing cards but with the same PCI IDs. The driver
    detects these based on other device information.
@@ -61,7 +61,7 @@
    must be adjusted accordingly. */
 
 /* PVR-350 V1 (uses saa7114) */
-#define IVTV_CARD_PVR_350_V1        (IVTV_CARD_LAST+1)
+#define IVTV_CARD_PVR_350_V1        (IVTV_CARD_LAST+1)
 /* 2 variants of Kuroutoshikou CX23416GYC-STVLP (Yuan MPG600GR OEM) */
 #define IVTV_CARD_CX23416GYC_NOGR    (IVTV_CARD_LAST+2)
 #define IVTV_CARD_CX23416GYC_NOGRYCS (IVTV_CARD_LAST+3)
 #define PCI_DEVICE_ID_IVTV16 0x0016
 
 /* subsystem vendor ID */
-#define IVTV_PCI_ID_HAUPPAUGE          0x0070
-#define IVTV_PCI_ID_HAUPPAUGE_ALT1     0x0270
-#define IVTV_PCI_ID_HAUPPAUGE_ALT2     0x4070
-#define IVTV_PCI_ID_ADAPTEC            0x9005
-#define IVTV_PCI_ID_ASUSTEK            0x1043
-#define IVTV_PCI_ID_AVERMEDIA          0x1461
+#define IVTV_PCI_ID_HAUPPAUGE          0x0070
+#define IVTV_PCI_ID_HAUPPAUGE_ALT1     0x0270
+#define IVTV_PCI_ID_HAUPPAUGE_ALT2     0x4070
+#define IVTV_PCI_ID_ADAPTEC            0x9005
+#define IVTV_PCI_ID_ASUSTEK            0x1043
+#define IVTV_PCI_ID_AVERMEDIA          0x1461
 #define IVTV_PCI_ID_YUAN1              0x12ab
-#define IVTV_PCI_ID_YUAN2              0xff01
-#define IVTV_PCI_ID_YUAN3              0xffab
-#define IVTV_PCI_ID_YUAN4              0xfbab
-#define IVTV_PCI_ID_DIAMONDMM          0xff92
-#define IVTV_PCI_ID_IODATA             0x10fc
-#define IVTV_PCI_ID_MELCO              0x1154
+#define IVTV_PCI_ID_YUAN2              0xff01
+#define IVTV_PCI_ID_YUAN3              0xffab
+#define IVTV_PCI_ID_YUAN4              0xfbab
+#define IVTV_PCI_ID_DIAMONDMM          0xff92
+#define IVTV_PCI_ID_IODATA             0x10fc
+#define IVTV_PCI_ID_MELCO              0x1154
 #define IVTV_PCI_ID_GOTVIEW1           0xffac
-#define IVTV_PCI_ID_GOTVIEW2           0xffad
-#define IVTV_PCI_ID_SONY               0x104d
+#define IVTV_PCI_ID_GOTVIEW2           0xffad
+#define IVTV_PCI_ID_SONY               0x104d
 
 /* hardware flags, no gaps allowed */
 #define IVTV_HW_CX25840                        (1 << 0)
 
 /* video inputs */
 #define        IVTV_CARD_INPUT_VID_TUNER       1
-#define        IVTV_CARD_INPUT_SVIDEO1         2
-#define        IVTV_CARD_INPUT_SVIDEO2         3
-#define        IVTV_CARD_INPUT_COMPOSITE1      4
-#define        IVTV_CARD_INPUT_COMPOSITE2      5
-#define        IVTV_CARD_INPUT_COMPOSITE3      6
+#define        IVTV_CARD_INPUT_SVIDEO1         2
+#define        IVTV_CARD_INPUT_SVIDEO2         3
+#define        IVTV_CARD_INPUT_COMPOSITE1      4
+#define        IVTV_CARD_INPUT_COMPOSITE2      5
+#define        IVTV_CARD_INPUT_COMPOSITE3      6
 
 /* audio inputs */
 #define        IVTV_CARD_INPUT_AUD_TUNER       1
-#define        IVTV_CARD_INPUT_LINE_IN1        2
-#define        IVTV_CARD_INPUT_LINE_IN2        3
+#define        IVTV_CARD_INPUT_LINE_IN1        2
+#define        IVTV_CARD_INPUT_LINE_IN2        3
 
 #define IVTV_CARD_MAX_VIDEO_INPUTS 6
 #define IVTV_CARD_MAX_AUDIO_INPUTS 3
-#define IVTV_CARD_MAX_TUNERS      3
+#define IVTV_CARD_MAX_TUNERS      3
 
 /* SAA71XX HW inputs */
 #define IVTV_SAA71XX_COMPOSITE0 0
                          V4L2_CAP_SLICED_VBI_OUTPUT | V4L2_CAP_VIDEO_OUTPUT_OVERLAY)
 
 struct ivtv_card_video_input {
-       u8  video_type;         /* video input type */
+       u8  video_type;         /* video input type */
        u8  audio_index;        /* index in ivtv_card_audio_input array */
        u16 video_input;        /* hardware video input */
 };
@@ -199,55 +199,55 @@ struct ivtv_card_pci_info {
 
 /* The mask is the set of bits used by the operation */
 
-struct ivtv_gpio_init {        /* set initial GPIO DIR and OUT values */
-       u16 direction;          /* DIR setting. Leave to 0 if no init is needed */
+struct ivtv_gpio_init {                /* set initial GPIO DIR and OUT values */
+       u16 direction;          /* DIR setting. Leave to 0 if no init is needed */
        u16 initial_value;
 };
 
-struct ivtv_gpio_video_input {         /* select tuner/line in input */
-       u16 mask;               /* leave to 0 if not supported */
+struct ivtv_gpio_video_input { /* select tuner/line in input */
+       u16 mask;               /* leave to 0 if not supported */
        u16 tuner;
        u16 composite;
        u16 svideo;
 };
 
-struct ivtv_gpio_audio_input {         /* select tuner/line in input */
-       u16 mask;               /* leave to 0 if not supported */
+struct ivtv_gpio_audio_input { /* select tuner/line in input */
+       u16 mask;               /* leave to 0 if not supported */
        u16 tuner;
        u16 linein;
        u16 radio;
 };
 
 struct ivtv_gpio_audio_mute {
-       u16 mask;               /* leave to 0 if not supported */
+       u16 mask;               /* leave to 0 if not supported */
        u16 mute;               /* set this value to mute, 0 to unmute */
 };
 
 struct ivtv_gpio_audio_mode {
-       u16 mask;               /* leave to 0 if not supported */
-       u16 mono;               /* set audio to mono */
-       u16 stereo;             /* set audio to stereo */
+       u16 mask;               /* leave to 0 if not supported */
+       u16 mono;               /* set audio to mono */
+       u16 stereo;             /* set audio to stereo */
        u16 lang1;              /* set audio to the first language */
        u16 lang2;              /* set audio to the second language */
-       u16 both;               /* both languages are output */
+       u16 both;               /* both languages are output */
 };
 
 struct ivtv_gpio_audio_freq {
-       u16 mask;               /* leave to 0 if not supported */
+       u16 mask;               /* leave to 0 if not supported */
        u16 f32000;
        u16 f44100;
        u16 f48000;
 };
 
 struct ivtv_gpio_audio_detect {
-       u16 mask;               /* leave to 0 if not supported */
-       u16 stereo;             /* if the input matches this value then
+       u16 mask;               /* leave to 0 if not supported */
+       u16 stereo;             /* if the input matches this value then
                                   stereo is detected */
 };
 
 struct ivtv_card_tuner {
-       v4l2_std_id std;        /* standard for which the tuner is suitable */
-       int         tuner;      /* tuner ID (from tuner.h) */
+       v4l2_std_id std;        /* standard for which the tuner is suitable */
+       int         tuner;      /* tuner ID (from tuner.h) */
 };
 
 struct ivtv_card_tuner_i2c {
@@ -272,17 +272,17 @@ struct ivtv_card {
        struct ivtv_card_audio_input radio_input;
        int nof_outputs;
        const struct ivtv_card_output *video_outputs;
-       u8 gr_config;           /* config byte for the ghost reduction device */
-       u8 xceive_pin;          /* XCeive tuner GPIO reset pin */
+       u8 gr_config;           /* config byte for the ghost reduction device */
+       u8 xceive_pin;          /* XCeive tuner GPIO reset pin */
 
        /* GPIO card-specific settings */
-       struct ivtv_gpio_init           gpio_init;
+       struct ivtv_gpio_init           gpio_init;
        struct ivtv_gpio_video_input    gpio_video_input;
-       struct ivtv_gpio_audio_input    gpio_audio_input;
-       struct ivtv_gpio_audio_mute     gpio_audio_mute;
-       struct ivtv_gpio_audio_mode     gpio_audio_mode;
-       struct ivtv_gpio_audio_freq     gpio_audio_freq;
-       struct ivtv_gpio_audio_detect   gpio_audio_detect;
+       struct ivtv_gpio_audio_input    gpio_audio_input;
+       struct ivtv_gpio_audio_mute     gpio_audio_mute;
+       struct ivtv_gpio_audio_mode     gpio_audio_mode;
+       struct ivtv_gpio_audio_freq     gpio_audio_freq;
+       struct ivtv_gpio_audio_detect   gpio_audio_detect;
 
        struct ivtv_card_tuner tuners[IVTV_CARD_MAX_TUNERS];
        struct ivtv_card_tuner_i2c *i2c;
index d27c5c2c07ea1e13f75a0071a9460d5234d82189..cafba6b1055df7f214906c187d6d80f4d05278b9 100644 (file)
@@ -76,7 +76,7 @@
 #define IVTV_ENCODER_SIZE      0x00800000      /* Total size is 0x01000000, but only first half is used */
 #define IVTV_DECODER_OFFSET    0x01000000
 #define IVTV_DECODER_SIZE      0x00800000      /* Total size is 0x01000000, but only first half is used */
-#define IVTV_REG_OFFSET        0x02000000
+#define IVTV_REG_OFFSET                0x02000000
 #define IVTV_REG_SIZE          0x00010000
 
 /* Maximum ivtv driver instances. Some people have a huge number of
 #define IVTV_DMA_SG_OSD_ENT    (2883584/PAGE_SIZE)     /* sg entities */
 
 /* DMA Registers */
-#define IVTV_REG_DMAXFER       (0x0000)
-#define IVTV_REG_DMASTATUS     (0x0004)
-#define IVTV_REG_DECDMAADDR    (0x0008)
-#define IVTV_REG_ENCDMAADDR    (0x000c)
-#define IVTV_REG_DMACONTROL    (0x0010)
-#define IVTV_REG_IRQSTATUS     (0x0040)
-#define IVTV_REG_IRQMASK       (0x0048)
+#define IVTV_REG_DMAXFER       (0x0000)
+#define IVTV_REG_DMASTATUS     (0x0004)
+#define IVTV_REG_DECDMAADDR    (0x0008)
+#define IVTV_REG_ENCDMAADDR    (0x000c)
+#define IVTV_REG_DMACONTROL    (0x0010)
+#define IVTV_REG_IRQSTATUS     (0x0040)
+#define IVTV_REG_IRQMASK       (0x0048)
 
 /* Setup Registers */
-#define IVTV_REG_ENC_SDRAM_REFRESH     (0x07F8)
-#define IVTV_REG_ENC_SDRAM_PRECHARGE   (0x07FC)
-#define IVTV_REG_DEC_SDRAM_REFRESH     (0x08F8)
-#define IVTV_REG_DEC_SDRAM_PRECHARGE   (0x08FC)
-#define IVTV_REG_VDM                   (0x2800)
-#define IVTV_REG_AO                    (0x2D00)
-#define IVTV_REG_BYTEFLUSH             (0x2D24)
-#define IVTV_REG_SPU                   (0x9050)
-#define IVTV_REG_HW_BLOCKS             (0x9054)
-#define IVTV_REG_VPU                   (0x9058)
-#define IVTV_REG_APU                   (0xA064)
+#define IVTV_REG_ENC_SDRAM_REFRESH     (0x07F8)
+#define IVTV_REG_ENC_SDRAM_PRECHARGE   (0x07FC)
+#define IVTV_REG_DEC_SDRAM_REFRESH     (0x08F8)
+#define IVTV_REG_DEC_SDRAM_PRECHARGE   (0x08FC)
+#define IVTV_REG_VDM                   (0x2800)
+#define IVTV_REG_AO                    (0x2D00)
+#define IVTV_REG_BYTEFLUSH             (0x2D24)
+#define IVTV_REG_SPU                   (0x9050)
+#define IVTV_REG_HW_BLOCKS             (0x9054)
+#define IVTV_REG_VPU                   (0x9058)
+#define IVTV_REG_APU                   (0xA064)
 
 /* Other registers */
 #define IVTV_REG_DEC_LINE_FIELD                (0x28C0)
@@ -158,7 +158,7 @@ extern int ivtv_fw_debug;
 
 #define IVTV_DEBUG_HIGH_VOL(x, type, fmt, args...) \
        do { \
-               if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL))   \
+               if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL))   \
                        v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args);  \
        } while (0)
 #define IVTV_DEBUG_HI_WARN(fmt, args...)  IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_WARN,  "warn",  fmt , ## args)
@@ -226,9 +226,9 @@ struct ivtv_mailbox_data {
 /* per-stream, s_flags */
 #define IVTV_F_S_DMA_PENDING   0       /* this stream has pending DMA */
 #define IVTV_F_S_DMA_HAS_VBI   1       /* the current DMA request also requests VBI data */
-#define IVTV_F_S_NEEDS_DATA    2       /* this decoding stream needs more data */
+#define IVTV_F_S_NEEDS_DATA    2       /* this decoding stream needs more data */
 
-#define IVTV_F_S_CLAIMED       3       /* this stream is claimed */
+#define IVTV_F_S_CLAIMED       3       /* this stream is claimed */
 #define IVTV_F_S_STREAMING      4      /* the fw is decoding/encoding this stream */
 #define IVTV_F_S_INTERNAL_USE  5       /* this stream is used internally (sliced VBI processing) */
 #define IVTV_F_S_PASSTHROUGH   6       /* this stream is in passthrough mode */
@@ -239,35 +239,35 @@ struct ivtv_mailbox_data {
 #define IVTV_F_S_PIO_HAS_VBI   1       /* the current PIO request also requests VBI data */
 
 /* per-ivtv, i_flags */
-#define IVTV_F_I_DMA              0    /* DMA in progress */
-#define IVTV_F_I_UDMA             1    /* UDMA in progress */
-#define IVTV_F_I_UDMA_PENDING     2    /* UDMA pending */
-#define IVTV_F_I_SPEED_CHANGE     3    /* a speed change is in progress */
-#define IVTV_F_I_EOS              4    /* end of encoder stream reached */
-#define IVTV_F_I_RADIO_USER       5    /* the radio tuner is selected */
-#define IVTV_F_I_DIG_RST          6    /* reset digitizer */
-#define IVTV_F_I_DEC_YUV          7    /* YUV instead of MPG is being decoded */
-#define IVTV_F_I_UPDATE_CC        9    /* CC should be updated */
-#define IVTV_F_I_UPDATE_WSS       10   /* WSS should be updated */
-#define IVTV_F_I_UPDATE_VPS       11   /* VPS should be updated */
-#define IVTV_F_I_DECODING_YUV     12   /* this stream is YUV frame decoding */
-#define IVTV_F_I_ENC_PAUSED       13   /* the encoder is paused */
-#define IVTV_F_I_VALID_DEC_TIMINGS 14  /* last_dec_timing is valid */
-#define IVTV_F_I_HAVE_WORK        15   /* used in the interrupt handler: there is work to be done */
+#define IVTV_F_I_DMA              0    /* DMA in progress */
+#define IVTV_F_I_UDMA             1    /* UDMA in progress */
+#define IVTV_F_I_UDMA_PENDING     2    /* UDMA pending */
+#define IVTV_F_I_SPEED_CHANGE     3    /* a speed change is in progress */
+#define IVTV_F_I_EOS              4    /* end of encoder stream reached */
+#define IVTV_F_I_RADIO_USER       5    /* the radio tuner is selected */
+#define IVTV_F_I_DIG_RST          6    /* reset digitizer */
+#define IVTV_F_I_DEC_YUV          7    /* YUV instead of MPG is being decoded */
+#define IVTV_F_I_UPDATE_CC        9    /* CC should be updated */
+#define IVTV_F_I_UPDATE_WSS       10   /* WSS should be updated */
+#define IVTV_F_I_UPDATE_VPS       11   /* VPS should be updated */
+#define IVTV_F_I_DECODING_YUV     12   /* this stream is YUV frame decoding */
+#define IVTV_F_I_ENC_PAUSED       13   /* the encoder is paused */
+#define IVTV_F_I_VALID_DEC_TIMINGS 14  /* last_dec_timing is valid */
+#define IVTV_F_I_HAVE_WORK        15   /* used in the interrupt handler: there is work to be done */
 #define IVTV_F_I_WORK_HANDLER_VBI  16  /* there is work to be done for VBI */
 #define IVTV_F_I_WORK_HANDLER_YUV  17  /* there is work to be done for YUV */
 #define IVTV_F_I_WORK_HANDLER_PIO  18  /* there is work to be done for PIO */
 #define IVTV_F_I_PIO              19   /* PIO in progress */
-#define IVTV_F_I_DEC_PAUSED       20   /* the decoder is paused */
-#define IVTV_F_I_INITED                   21   /* set after first open */
-#define IVTV_F_I_FAILED                   22   /* set if first open failed */
+#define IVTV_F_I_DEC_PAUSED       20   /* the decoder is paused */
+#define IVTV_F_I_INITED                   21   /* set after first open */
+#define IVTV_F_I_FAILED                   22   /* set if first open failed */
 #define IVTV_F_I_WORK_HANDLER_PCM  23  /* there is work to be done for PCM */
 
 /* Event notifications */
 #define IVTV_F_I_EV_DEC_STOPPED           28   /* decoder stopped event */
-#define IVTV_F_I_EV_VSYNC         29   /* VSYNC event */
-#define IVTV_F_I_EV_VSYNC_FIELD    30  /* VSYNC event field (0 = first, 1 = second field) */
-#define IVTV_F_I_EV_VSYNC_ENABLED  31  /* VSYNC event enabled */
+#define IVTV_F_I_EV_VSYNC         29   /* VSYNC event */
+#define IVTV_F_I_EV_VSYNC_FIELD    30  /* VSYNC event field (0 = first, 1 = second field) */
+#define IVTV_F_I_EV_VSYNC_ENABLED  31  /* VSYNC event enabled */
 
 /* Scatter-Gather array element, used in DMA transfers */
 struct ivtv_sg_element {
@@ -330,13 +330,13 @@ struct ivtv_stream {
        /* These first four fields are always set, even if the stream
           is not actually created. */
        struct video_device vdev;       /* vdev.v4l2_dev is NULL if there is no device */
-       struct ivtv *itv;               /* for ease of use */
+       struct ivtv *itv;               /* for ease of use */
        const char *name;               /* name of the stream */
        int type;                       /* stream type */
        u32 caps;                       /* V4L2 capabilities */
 
        struct v4l2_fh *fh;             /* pointer to the streaming filehandle */
-       spinlock_t qlock;               /* locks access to the queues */
+       spinlock_t qlock;               /* locks access to the queues */
        unsigned long s_flags;          /* status flags, see above */
        int dma;                        /* can be PCI_DMA_TODEVICE, PCI_DMA_FROMDEVICE or PCI_DMA_NONE */
        u32 pending_offset;
@@ -564,7 +564,7 @@ struct vbi_info {
 
        /* Raw VBI compatibility hack */
 
-       u32 frame;                              /* frame counter hack needed for backwards compatibility
+       u32 frame;                              /* frame counter hack needed for backwards compatibility
                                                   of old VBI software */
 
        /* Sliced VBI output data */
@@ -620,7 +620,7 @@ struct ivtv {
        u8 nof_inputs;                  /* number of video inputs */
        u8 nof_audio_inputs;            /* number of audio inputs */
        u32 v4l2_cap;                   /* V4L2 capabilities of card */
-       u32 hw_flags;                   /* hardware description of the board */
+       u32 hw_flags;                   /* hardware description of the board */
        v4l2_std_id tuner_std;          /* the norm of the card's tuner (fixed) */
        struct v4l2_subdev *sd_video;   /* controlling video decoder subdev */
        struct v4l2_subdev *sd_audio;   /* controlling audio subdev */
@@ -629,7 +629,7 @@ struct ivtv {
        volatile void __iomem *enc_mem; /* pointer to mapped encoder memory */
        volatile void __iomem *dec_mem; /* pointer to mapped decoder memory */
        volatile void __iomem *reg_mem; /* pointer to mapped registers */
-       struct ivtv_options options;    /* user options */
+       struct ivtv_options options;    /* user options */
 
        struct v4l2_device v4l2_dev;
        struct cx2341x_handler cxhdl;
@@ -668,7 +668,7 @@ struct ivtv {
 
        /* Streams */
        int stream_buf_size[IVTV_MAX_STREAMS];          /* stream buffer size */
-       struct ivtv_stream streams[IVTV_MAX_STREAMS];   /* stream data */
+       struct ivtv_stream streams[IVTV_MAX_STREAMS];   /* stream data */
        atomic_t capturing;             /* count number of active capture streams */
        atomic_t decoding;              /* count number of active decoding streams */
 
@@ -704,7 +704,7 @@ struct ivtv {
        /* Mailbox */
        struct ivtv_mailbox_data enc_mbox;              /* encoder mailboxes */
        struct ivtv_mailbox_data dec_mbox;              /* decoder mailboxes */
-       struct ivtv_api_cache api_cache[256];           /* cached API commands */
+       struct ivtv_api_cache api_cache[256];           /* cached API commands */
 
 
        /* I2C */
@@ -828,7 +828,7 @@ static inline int ivtv_raw_vbi(const struct ivtv *itv)
 
 /* Call the specified callback for all subdevs matching hw (if 0, then
    match them all). Ignore any errors. */
-#define ivtv_call_hw(itv, hw, o, f, args...)                           \
+#define ivtv_call_hw(itv, hw, o, f, args...)                           \
        v4l2_device_mask_call_all(&(itv)->v4l2_dev, hw, o, f, ##args)
 
 #define ivtv_call_all(itv, o, f, args...) ivtv_call_hw(itv, 0, o, f , ##args)
index ba279fdb3df8c8f07f0b5b17a1f692f6e614da28..9f05472fca2087cc30cf9f06a2ba68fbe01040bb 100644 (file)
 #include <linux/firmware.h>
 #include <media/i2c/saa7127.h>
 
-#define IVTV_MASK_SPU_ENABLE           0xFFFFFFFE
-#define IVTV_MASK_VPU_ENABLE15                 0xFFFFFFF6
-#define IVTV_MASK_VPU_ENABLE16                 0xFFFFFFFB
-#define IVTV_CMD_VDM_STOP              0x00000000
-#define IVTV_CMD_AO_STOP               0x00000005
-#define IVTV_CMD_APU_PING              0x00000000
-#define IVTV_CMD_VPU_STOP15            0xFFFFFFFE
-#define IVTV_CMD_VPU_STOP16            0xFFFFFFEE
-#define IVTV_CMD_HW_BLOCKS_RST                 0xFFFFFFFF
-#define IVTV_CMD_SPU_STOP              0x00000001
-#define IVTV_CMD_SDRAM_PRECHARGE_INIT  0x0000001A
-#define IVTV_CMD_SDRAM_REFRESH_INIT    0x80000640
-#define IVTV_SDRAM_SLEEPTIME           600
-
-#define IVTV_DECODE_INIT_MPEG_FILENAME         "v4l-cx2341x-init.mpg"
-#define IVTV_DECODE_INIT_MPEG_SIZE     (152*1024)
+#define IVTV_MASK_SPU_ENABLE           0xFFFFFFFE
+#define IVTV_MASK_VPU_ENABLE15         0xFFFFFFF6
+#define IVTV_MASK_VPU_ENABLE16         0xFFFFFFFB
+#define IVTV_CMD_VDM_STOP              0x00000000
+#define IVTV_CMD_AO_STOP               0x00000005
+#define IVTV_CMD_APU_PING              0x00000000
+#define IVTV_CMD_VPU_STOP15            0xFFFFFFFE
+#define IVTV_CMD_VPU_STOP16            0xFFFFFFEE
+#define IVTV_CMD_HW_BLOCKS_RST         0xFFFFFFFF
+#define IVTV_CMD_SPU_STOP              0x00000001
+#define IVTV_CMD_SDRAM_PRECHARGE_INIT  0x0000001A
+#define IVTV_CMD_SDRAM_REFRESH_INIT    0x80000640
+#define IVTV_SDRAM_SLEEPTIME           600
+
+#define IVTV_DECODE_INIT_MPEG_FILENAME "v4l-cx2341x-init.mpg"
+#define IVTV_DECODE_INIT_MPEG_SIZE     (152*1024)
 
 /* Encoder/decoder firmware sizes */
-#define IVTV_FW_ENC_SIZE               (376836)
-#define IVTV_FW_DEC_SIZE               (256*1024)
+#define IVTV_FW_ENC_SIZE               (376836)
+#define IVTV_FW_DEC_SIZE               (256*1024)
 
 static int load_fw_direct(const char *fn, volatile u8 __iomem *mem, struct ivtv *itv, long size)
 {
index 66696e6ee587c8276552719adf7414d29424e710..522cd111e3998b83d3814b837361be15d2e1c213 100644 (file)
 
 #define IVTV_CS53L32A_I2C_ADDR         0x11
 #define IVTV_M52790_I2C_ADDR           0x48
-#define IVTV_CX25840_I2C_ADDR          0x44
-#define IVTV_SAA7115_I2C_ADDR          0x21
-#define IVTV_SAA7127_I2C_ADDR          0x44
-#define IVTV_SAA717x_I2C_ADDR          0x21
-#define IVTV_MSP3400_I2C_ADDR          0x40
-#define IVTV_HAUPPAUGE_I2C_ADDR        0x50
-#define IVTV_WM8739_I2C_ADDR           0x1a
+#define IVTV_CX25840_I2C_ADDR          0x44
+#define IVTV_SAA7115_I2C_ADDR          0x21
+#define IVTV_SAA7127_I2C_ADDR          0x44
+#define IVTV_SAA717x_I2C_ADDR          0x21
+#define IVTV_MSP3400_I2C_ADDR          0x40
+#define IVTV_HAUPPAUGE_I2C_ADDR                0x50
+#define IVTV_WM8739_I2C_ADDR           0x1a
 #define IVTV_WM8775_I2C_ADDR           0x1b
 #define IVTV_TEA5767_I2C_ADDR          0x60
-#define IVTV_UPD64031A_I2C_ADDR        0x12
-#define IVTV_UPD64083_I2C_ADDR                 0x5c
-#define IVTV_VP27SMPX_I2C_ADDR         0x5b
-#define IVTV_M52790_I2C_ADDR           0x48
+#define IVTV_UPD64031A_I2C_ADDR                0x12
+#define IVTV_UPD64083_I2C_ADDR         0x5c
+#define IVTV_VP27SMPX_I2C_ADDR         0x5b
+#define IVTV_M52790_I2C_ADDR           0x48
 #define IVTV_AVERMEDIA_IR_RX_I2C_ADDR  0x40
-#define IVTV_HAUP_EXT_IR_RX_I2C_ADDR   0x1a
-#define IVTV_HAUP_INT_IR_RX_I2C_ADDR   0x18
+#define IVTV_HAUP_EXT_IR_RX_I2C_ADDR   0x1a
+#define IVTV_HAUP_INT_IR_RX_I2C_ADDR   0x18
 #define IVTV_Z8F0811_IR_TX_I2C_ADDR    0x70
 #define IVTV_Z8F0811_IR_RX_I2C_ADDR    0x71
 #define IVTV_ADAPTEC_IR_ADDR           0x6b
index 670462d195b55c9738d669ec421e00ed4b3878a3..4cdc6d2be85de973e3548001ba54a3f78c237207 100644 (file)
@@ -1884,65 +1884,65 @@ static long ivtv_default(struct file *file, void *fh, bool valid_prio,
 }
 
 static const struct v4l2_ioctl_ops ivtv_ioctl_ops = {
-       .vidioc_querycap                    = ivtv_querycap,
-       .vidioc_s_audio                     = ivtv_s_audio,
-       .vidioc_g_audio                     = ivtv_g_audio,
-       .vidioc_enumaudio                   = ivtv_enumaudio,
-       .vidioc_s_audout                    = ivtv_s_audout,
-       .vidioc_g_audout                    = ivtv_g_audout,
-       .vidioc_enum_input                  = ivtv_enum_input,
-       .vidioc_enum_output                 = ivtv_enum_output,
-       .vidioc_enumaudout                  = ivtv_enumaudout,
-       .vidioc_cropcap                     = ivtv_cropcap,
+       .vidioc_querycap                    = ivtv_querycap,
+       .vidioc_s_audio                     = ivtv_s_audio,
+       .vidioc_g_audio                     = ivtv_g_audio,
+       .vidioc_enumaudio                   = ivtv_enumaudio,
+       .vidioc_s_audout                    = ivtv_s_audout,
+       .vidioc_g_audout                    = ivtv_g_audout,
+       .vidioc_enum_input                  = ivtv_enum_input,
+       .vidioc_enum_output                 = ivtv_enum_output,
+       .vidioc_enumaudout                  = ivtv_enumaudout,
+       .vidioc_cropcap                     = ivtv_cropcap,
        .vidioc_s_selection                 = ivtv_s_selection,
        .vidioc_g_selection                 = ivtv_g_selection,
-       .vidioc_g_input                     = ivtv_g_input,
-       .vidioc_s_input                     = ivtv_s_input,
-       .vidioc_g_output                    = ivtv_g_output,
-       .vidioc_s_output                    = ivtv_s_output,
-       .vidioc_g_frequency                 = ivtv_g_frequency,
-       .vidioc_s_frequency                 = ivtv_s_frequency,
-       .vidioc_s_tuner                     = ivtv_s_tuner,
-       .vidioc_g_tuner                     = ivtv_g_tuner,
-       .vidioc_g_enc_index                 = ivtv_g_enc_index,
+       .vidioc_g_input                     = ivtv_g_input,
+       .vidioc_s_input                     = ivtv_s_input,
+       .vidioc_g_output                    = ivtv_g_output,
+       .vidioc_s_output                    = ivtv_s_output,
+       .vidioc_g_frequency                 = ivtv_g_frequency,
+       .vidioc_s_frequency                 = ivtv_s_frequency,
+       .vidioc_s_tuner                     = ivtv_s_tuner,
+       .vidioc_g_tuner                     = ivtv_g_tuner,
+       .vidioc_g_enc_index                 = ivtv_g_enc_index,
        .vidioc_g_fbuf                      = ivtv_g_fbuf,
        .vidioc_s_fbuf                      = ivtv_s_fbuf,
-       .vidioc_g_std                       = ivtv_g_std,
-       .vidioc_s_std                       = ivtv_s_std,
+       .vidioc_g_std                       = ivtv_g_std,
+       .vidioc_s_std                       = ivtv_s_std,
        .vidioc_overlay                     = ivtv_overlay,
        .vidioc_log_status                  = ivtv_log_status,
-       .vidioc_enum_fmt_vid_cap            = ivtv_enum_fmt_vid_cap,
-       .vidioc_encoder_cmd                 = ivtv_encoder_cmd,
-       .vidioc_try_encoder_cmd             = ivtv_try_encoder_cmd,
+       .vidioc_enum_fmt_vid_cap            = ivtv_enum_fmt_vid_cap,
+       .vidioc_encoder_cmd                 = ivtv_encoder_cmd,
+       .vidioc_try_encoder_cmd             = ivtv_try_encoder_cmd,
        .vidioc_decoder_cmd                 = ivtv_decoder_cmd,
        .vidioc_try_decoder_cmd             = ivtv_try_decoder_cmd,
-       .vidioc_enum_fmt_vid_out            = ivtv_enum_fmt_vid_out,
-       .vidioc_g_fmt_vid_cap               = ivtv_g_fmt_vid_cap,
+       .vidioc_enum_fmt_vid_out            = ivtv_enum_fmt_vid_out,
+       .vidioc_g_fmt_vid_cap               = ivtv_g_fmt_vid_cap,
        .vidioc_g_fmt_vbi_cap               = ivtv_g_fmt_vbi_cap,
        .vidioc_g_fmt_sliced_vbi_cap        = ivtv_g_fmt_sliced_vbi_cap,
        .vidioc_g_fmt_vid_out               = ivtv_g_fmt_vid_out,
        .vidioc_g_fmt_vid_out_overlay       = ivtv_g_fmt_vid_out_overlay,
        .vidioc_g_fmt_sliced_vbi_out        = ivtv_g_fmt_sliced_vbi_out,
-       .vidioc_s_fmt_vid_cap               = ivtv_s_fmt_vid_cap,
-       .vidioc_s_fmt_vbi_cap               = ivtv_s_fmt_vbi_cap,
+       .vidioc_s_fmt_vid_cap               = ivtv_s_fmt_vid_cap,
+       .vidioc_s_fmt_vbi_cap               = ivtv_s_fmt_vbi_cap,
        .vidioc_s_fmt_sliced_vbi_cap        = ivtv_s_fmt_sliced_vbi_cap,
        .vidioc_s_fmt_vid_out               = ivtv_s_fmt_vid_out,
        .vidioc_s_fmt_vid_out_overlay       = ivtv_s_fmt_vid_out_overlay,
        .vidioc_s_fmt_sliced_vbi_out        = ivtv_s_fmt_sliced_vbi_out,
-       .vidioc_try_fmt_vid_cap             = ivtv_try_fmt_vid_cap,
+       .vidioc_try_fmt_vid_cap             = ivtv_try_fmt_vid_cap,
        .vidioc_try_fmt_vbi_cap             = ivtv_try_fmt_vbi_cap,
        .vidioc_try_fmt_sliced_vbi_cap      = ivtv_try_fmt_sliced_vbi_cap,
-       .vidioc_try_fmt_vid_out             = ivtv_try_fmt_vid_out,
+       .vidioc_try_fmt_vid_out             = ivtv_try_fmt_vid_out,
        .vidioc_try_fmt_vid_out_overlay     = ivtv_try_fmt_vid_out_overlay,
-       .vidioc_try_fmt_sliced_vbi_out      = ivtv_try_fmt_sliced_vbi_out,
-       .vidioc_g_sliced_vbi_cap            = ivtv_g_sliced_vbi_cap,
+       .vidioc_try_fmt_sliced_vbi_out      = ivtv_try_fmt_sliced_vbi_out,
+       .vidioc_g_sliced_vbi_cap            = ivtv_g_sliced_vbi_cap,
 #ifdef CONFIG_VIDEO_ADV_DEBUG
-       .vidioc_g_register                  = ivtv_g_register,
-       .vidioc_s_register                  = ivtv_s_register,
+       .vidioc_g_register                  = ivtv_g_register,
+       .vidioc_s_register                  = ivtv_s_register,
 #endif
-       .vidioc_default                     = ivtv_default,
-       .vidioc_subscribe_event             = ivtv_subscribe_event,
-       .vidioc_unsubscribe_event           = v4l2_event_unsubscribe,
+       .vidioc_default                     = ivtv_default,
+       .vidioc_subscribe_event             = ivtv_subscribe_event,
+       .vidioc_unsubscribe_event           = v4l2_event_unsubscribe,
 };
 
 void ivtv_set_funcs(struct video_device *vdev)
index 9a2506a5edbebaaa58182ae345462121923ca92a..f317c8f0938d9c50da38d998b9b901399ab8e488 100644 (file)
 #define IVTV_MBOX_FIRMWARE_DONE 0x00000004
 #define IVTV_MBOX_DRIVER_DONE   0x00000002
 #define IVTV_MBOX_DRIVER_BUSY   0x00000001
-#define IVTV_MBOX_FREE                 0x00000000
+#define IVTV_MBOX_FREE         0x00000000
 
 /* Firmware mailbox standard timeout */
-#define IVTV_API_STD_TIMEOUT   0x02000000
+#define IVTV_API_STD_TIMEOUT   0x02000000
 
-#define API_CACHE       (1 << 0)       /* Allow the command to be stored in the cache */
-#define API_RESULT      (1 << 1)       /* Allow 1 second for this cmd to end */
+#define API_CACHE       (1 << 0)       /* Allow the command to be stored in the cache */
+#define API_RESULT      (1 << 1)       /* Allow 1 second for this cmd to end */
 #define API_FAST_RESULT         (3 << 1)       /* Allow 0.1 second for this cmd to end */
-#define API_DMA         (1 << 3)       /* DMA mailbox, has special handling */
-#define API_HIGH_VOL    (1 << 5)       /* High volume command (i.e. called during encoding or decoding) */
-#define API_NO_WAIT_MB          (1 << 4)       /* Command may not wait for a free mailbox */
+#define API_DMA                 (1 << 3)       /* DMA mailbox, has special handling */
+#define API_HIGH_VOL    (1 << 5)       /* High volume command (i.e. called during encoding or decoding) */
+#define API_NO_WAIT_MB  (1 << 4)       /* Command may not wait for a free mailbox */
 #define API_NO_WAIT_RES         (1 << 5)       /* Command may not wait for the result */
 #define API_NO_POLL     (1 << 6)       /* Avoid pointless polling */
 
 struct ivtv_api_info {
        int flags;              /* Flags, see above */
-       const char *name;       /* The name of the command */
+       const char *name;       /* The name of the command */
 };
 
 #define API_ENTRY(x, f) [x] = { (f), #x }
 
 static const struct ivtv_api_info api_info[256] = {
        /* MPEG encoder API */
-       API_ENTRY(CX2341X_ENC_PING_FW,                  API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_START_CAPTURE,            API_RESULT | API_NO_POLL),
-       API_ENTRY(CX2341X_ENC_STOP_CAPTURE,             API_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_AUDIO_ID,             API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_VIDEO_ID,             API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_PCR_ID,               API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_FRAME_RATE,           API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_FRAME_SIZE,           API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_BIT_RATE,             API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_GOP_PROPERTIES,       API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_ASPECT_RATIO,         API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_DNR_FILTER_MODE,      API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_DNR_FILTER_PROPS,     API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_CORING_LEVELS,        API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_SPATIAL_FILTER_TYPE,  API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_VBI_LINE,             API_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_STREAM_TYPE,          API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_OUTPUT_PORT,          API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_AUDIO_PROPERTIES,     API_CACHE),
-       API_ENTRY(CX2341X_ENC_HALT_FW,                  API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_GET_VERSION,              API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_GOP_CLOSURE,          API_CACHE),
-       API_ENTRY(CX2341X_ENC_GET_SEQ_END,              API_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_PGM_INDEX_INFO,       API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_VBI_CONFIG,           API_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_DMA_BLOCK_SIZE,       API_CACHE),
-       API_ENTRY(CX2341X_ENC_GET_PREV_DMA_INFO_MB_10,  API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_GET_PREV_DMA_INFO_MB_9,   API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_SCHED_DMA_TO_HOST,        API_DMA | API_HIGH_VOL),
-       API_ENTRY(CX2341X_ENC_INITIALIZE_INPUT,         API_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_FRAME_DROP_RATE,      API_CACHE),
-       API_ENTRY(CX2341X_ENC_PAUSE_ENCODER,            API_RESULT),
-       API_ENTRY(CX2341X_ENC_REFRESH_INPUT,            API_NO_WAIT_MB | API_HIGH_VOL),
-       API_ENTRY(CX2341X_ENC_SET_COPYRIGHT,            API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_EVENT_NOTIFICATION,   API_RESULT),
-       API_ENTRY(CX2341X_ENC_SET_NUM_VSYNC_LINES,      API_CACHE),
-       API_ENTRY(CX2341X_ENC_SET_PLACEHOLDER,          API_CACHE),
-       API_ENTRY(CX2341X_ENC_MUTE_VIDEO,               API_RESULT),
-       API_ENTRY(CX2341X_ENC_MUTE_AUDIO,               API_RESULT),
+       API_ENTRY(CX2341X_ENC_PING_FW,                  API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_START_CAPTURE,            API_RESULT | API_NO_POLL),
+       API_ENTRY(CX2341X_ENC_STOP_CAPTURE,             API_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_AUDIO_ID,             API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_VIDEO_ID,             API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_PCR_ID,               API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_FRAME_RATE,           API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_FRAME_SIZE,           API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_BIT_RATE,             API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_GOP_PROPERTIES,       API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_ASPECT_RATIO,         API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_DNR_FILTER_MODE,      API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_DNR_FILTER_PROPS,     API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_CORING_LEVELS,        API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_SPATIAL_FILTER_TYPE,  API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_VBI_LINE,             API_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_STREAM_TYPE,          API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_OUTPUT_PORT,          API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_AUDIO_PROPERTIES,     API_CACHE),
+       API_ENTRY(CX2341X_ENC_HALT_FW,                  API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_GET_VERSION,              API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_GOP_CLOSURE,          API_CACHE),
+       API_ENTRY(CX2341X_ENC_GET_SEQ_END,              API_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_PGM_INDEX_INFO,       API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_VBI_CONFIG,           API_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_DMA_BLOCK_SIZE,       API_CACHE),
+       API_ENTRY(CX2341X_ENC_GET_PREV_DMA_INFO_MB_10,  API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_GET_PREV_DMA_INFO_MB_9,   API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_SCHED_DMA_TO_HOST,        API_DMA | API_HIGH_VOL),
+       API_ENTRY(CX2341X_ENC_INITIALIZE_INPUT,         API_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_FRAME_DROP_RATE,      API_CACHE),
+       API_ENTRY(CX2341X_ENC_PAUSE_ENCODER,            API_RESULT),
+       API_ENTRY(CX2341X_ENC_REFRESH_INPUT,            API_NO_WAIT_MB | API_HIGH_VOL),
+       API_ENTRY(CX2341X_ENC_SET_COPYRIGHT,            API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_EVENT_NOTIFICATION,   API_RESULT),
+       API_ENTRY(CX2341X_ENC_SET_NUM_VSYNC_LINES,      API_CACHE),
+       API_ENTRY(CX2341X_ENC_SET_PLACEHOLDER,          API_CACHE),
+       API_ENTRY(CX2341X_ENC_MUTE_VIDEO,               API_RESULT),
+       API_ENTRY(CX2341X_ENC_MUTE_AUDIO,               API_RESULT),
        API_ENTRY(CX2341X_ENC_SET_VERT_CROP_LINE,       API_FAST_RESULT),
-       API_ENTRY(CX2341X_ENC_MISC,                     API_FAST_RESULT),
+       API_ENTRY(CX2341X_ENC_MISC,                     API_FAST_RESULT),
        /* Obsolete PULLDOWN API command */
-       API_ENTRY(0xb1,                                 API_CACHE),
+       API_ENTRY(0xb1,                                 API_CACHE),
 
        /* MPEG decoder API */
-       API_ENTRY(CX2341X_DEC_PING_FW,                  API_FAST_RESULT),
-       API_ENTRY(CX2341X_DEC_START_PLAYBACK,           API_RESULT | API_NO_POLL),
-       API_ENTRY(CX2341X_DEC_STOP_PLAYBACK,            API_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_PLAYBACK_SPEED,       API_RESULT),
-       API_ENTRY(CX2341X_DEC_STEP_VIDEO,               API_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_DMA_BLOCK_SIZE,       API_CACHE),
-       API_ENTRY(CX2341X_DEC_GET_XFER_INFO,            API_FAST_RESULT),
-       API_ENTRY(CX2341X_DEC_GET_DMA_STATUS,           API_FAST_RESULT),
-       API_ENTRY(CX2341X_DEC_SCHED_DMA_FROM_HOST,      API_DMA | API_HIGH_VOL),
-       API_ENTRY(CX2341X_DEC_PAUSE_PLAYBACK,           API_RESULT),
-       API_ENTRY(CX2341X_DEC_HALT_FW,                  API_FAST_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_STANDARD,             API_CACHE),
-       API_ENTRY(CX2341X_DEC_GET_VERSION,              API_FAST_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_STREAM_INPUT,         API_CACHE),
-       API_ENTRY(CX2341X_DEC_GET_TIMING_INFO,          API_RESULT /*| API_NO_WAIT_RES*/),
-       API_ENTRY(CX2341X_DEC_SET_AUDIO_MODE,           API_CACHE),
-       API_ENTRY(CX2341X_DEC_SET_EVENT_NOTIFICATION,   API_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_DISPLAY_BUFFERS,      API_CACHE),
-       API_ENTRY(CX2341X_DEC_EXTRACT_VBI,              API_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_DECODER_SOURCE,       API_FAST_RESULT),
-       API_ENTRY(CX2341X_DEC_SET_PREBUFFERING,         API_CACHE),
+       API_ENTRY(CX2341X_DEC_PING_FW,                  API_FAST_RESULT),
+       API_ENTRY(CX2341X_DEC_START_PLAYBACK,           API_RESULT | API_NO_POLL),
+       API_ENTRY(CX2341X_DEC_STOP_PLAYBACK,            API_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_PLAYBACK_SPEED,       API_RESULT),
+       API_ENTRY(CX2341X_DEC_STEP_VIDEO,               API_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_DMA_BLOCK_SIZE,       API_CACHE),
+       API_ENTRY(CX2341X_DEC_GET_XFER_INFO,            API_FAST_RESULT),
+       API_ENTRY(CX2341X_DEC_GET_DMA_STATUS,           API_FAST_RESULT),
+       API_ENTRY(CX2341X_DEC_SCHED_DMA_FROM_HOST,      API_DMA | API_HIGH_VOL),
+       API_ENTRY(CX2341X_DEC_PAUSE_PLAYBACK,           API_RESULT),
+       API_ENTRY(CX2341X_DEC_HALT_FW,                  API_FAST_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_STANDARD,             API_CACHE),
+       API_ENTRY(CX2341X_DEC_GET_VERSION,              API_FAST_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_STREAM_INPUT,         API_CACHE),
+       API_ENTRY(CX2341X_DEC_GET_TIMING_INFO,          API_RESULT /*| API_NO_WAIT_RES*/),
+       API_ENTRY(CX2341X_DEC_SET_AUDIO_MODE,           API_CACHE),
+       API_ENTRY(CX2341X_DEC_SET_EVENT_NOTIFICATION,   API_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_DISPLAY_BUFFERS,      API_CACHE),
+       API_ENTRY(CX2341X_DEC_EXTRACT_VBI,              API_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_DECODER_SOURCE,       API_FAST_RESULT),
+       API_ENTRY(CX2341X_DEC_SET_PREBUFFERING,         API_CACHE),
 
        /* OSD API */
-       API_ENTRY(CX2341X_OSD_GET_FRAMEBUFFER,          API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_GET_PIXEL_FORMAT,         API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_PIXEL_FORMAT,         API_CACHE),
-       API_ENTRY(CX2341X_OSD_GET_STATE,                API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_STATE,                API_CACHE),
-       API_ENTRY(CX2341X_OSD_GET_OSD_COORDS,           API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_OSD_COORDS,           API_CACHE),
-       API_ENTRY(CX2341X_OSD_GET_SCREEN_COORDS,        API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_SCREEN_COORDS,        API_CACHE),
-       API_ENTRY(CX2341X_OSD_GET_GLOBAL_ALPHA,         API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_GLOBAL_ALPHA,         API_CACHE),
-       API_ENTRY(CX2341X_OSD_SET_BLEND_COORDS,         API_CACHE),
-       API_ENTRY(CX2341X_OSD_GET_FLICKER_STATE,        API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_FLICKER_STATE,        API_CACHE),
-       API_ENTRY(CX2341X_OSD_BLT_COPY,                 API_RESULT),
-       API_ENTRY(CX2341X_OSD_BLT_FILL,                 API_RESULT),
-       API_ENTRY(CX2341X_OSD_BLT_TEXT,                 API_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_FRAMEBUFFER_WINDOW,   API_CACHE),
-       API_ENTRY(CX2341X_OSD_SET_CHROMA_KEY,           API_CACHE),
-       API_ENTRY(CX2341X_OSD_GET_ALPHA_CONTENT_INDEX,  API_FAST_RESULT),
-       API_ENTRY(CX2341X_OSD_SET_ALPHA_CONTENT_INDEX,  API_CACHE)
+       API_ENTRY(CX2341X_OSD_GET_FRAMEBUFFER,          API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_GET_PIXEL_FORMAT,         API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_PIXEL_FORMAT,         API_CACHE),
+       API_ENTRY(CX2341X_OSD_GET_STATE,                API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_STATE,                API_CACHE),
+       API_ENTRY(CX2341X_OSD_GET_OSD_COORDS,           API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_OSD_COORDS,           API_CACHE),
+       API_ENTRY(CX2341X_OSD_GET_SCREEN_COORDS,        API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_SCREEN_COORDS,        API_CACHE),
+       API_ENTRY(CX2341X_OSD_GET_GLOBAL_ALPHA,         API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_GLOBAL_ALPHA,         API_CACHE),
+       API_ENTRY(CX2341X_OSD_SET_BLEND_COORDS,         API_CACHE),
+       API_ENTRY(CX2341X_OSD_GET_FLICKER_STATE,        API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_FLICKER_STATE,        API_CACHE),
+       API_ENTRY(CX2341X_OSD_BLT_COPY,                 API_RESULT),
+       API_ENTRY(CX2341X_OSD_BLT_FILL,                 API_RESULT),
+       API_ENTRY(CX2341X_OSD_BLT_TEXT,                 API_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_FRAMEBUFFER_WINDOW,   API_CACHE),
+       API_ENTRY(CX2341X_OSD_SET_CHROMA_KEY,           API_CACHE),
+       API_ENTRY(CX2341X_OSD_GET_ALPHA_CONTENT_INDEX,  API_FAST_RESULT),
+       API_ENTRY(CX2341X_OSD_SET_ALPHA_CONTENT_INDEX,  API_CACHE)
 };
 
 static int try_mailbox(struct ivtv *itv, struct ivtv_mailbox_data *mbdata, int mb)
index 7761f9dc7fe0e1df467e8c225a78ac76e0bf9ac4..762ed9f7a08e1de66f1dd9b60bf5cb3b53cd8626 100644 (file)
 #define MANTIS_CARD_PLUGOUT            (0x01 <<  0)
 
 #define MANTIS_GPIF_BRADDR             0xa0
-#define MANTIS_GPIF_PCMCIAREG          (0x01           << 27)
-#define MANTIS_GPIF_PCMCIAIOM          (0x01           << 26)
+#define MANTIS_GPIF_PCMCIAREG          (0x01           << 27)
+#define MANTIS_GPIF_PCMCIAIOM          (0x01           << 26)
 #define MANTIS_GPIF_BR_ADDR            (0xfffffff      <<  0)
 
 #define MANTIS_GPIF_BRBYTES            0xa4
-#define MANTIS_GPIF_BRCNT              (0xfff          <<  0)
+#define MANTIS_GPIF_BRCNT              (0xfff          <<  0)
 
 #define MANTIS_PCMCIA_RESET            0xa8
 #define MANTIS_PCMCIA_RSTVAL           (0xff << 0)
index 47e0c48c3abc3afeb184d59407d5272ee59b57d4..0eeccc2d19a52238ba03ed69d9263d4e551a90fb 100644 (file)
@@ -47,70 +47,70 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_1[] = {
        /* 0x0000000b, *//* SYSREG */
        { STB0899_DEV_ID                , 0x30 },
        { STB0899_DISCNTRL1             , 0x32 },
-       { STB0899_DISCNTRL2             , 0x80 },
-       { STB0899_DISRX_ST0             , 0x04 },
-       { STB0899_DISRX_ST1             , 0x00 },
-       { STB0899_DISPARITY             , 0x00 },
+       { STB0899_DISCNTRL2             , 0x80 },
+       { STB0899_DISRX_ST0             , 0x04 },
+       { STB0899_DISRX_ST1             , 0x00 },
+       { STB0899_DISPARITY             , 0x00 },
        { STB0899_DISSTATUS             , 0x20 },
-       { STB0899_DISF22                , 0x99 },
-       { STB0899_DISF22RX              , 0xa8 },
+       { STB0899_DISF22                , 0x99 },
+       { STB0899_DISF22RX              , 0xa8 },
        /* SYSREG ? */
-       { STB0899_ACRPRESC              , 0x11 },
-       { STB0899_ACRDIV1               , 0x0a },
-       { STB0899_ACRDIV2               , 0x05 },
-       { STB0899_DACR1                 , 0x00 },
-       { STB0899_DACR2                 , 0x00 },
-       { STB0899_OUTCFG                , 0x00 },
-       { STB0899_MODECFG               , 0x00 },
+       { STB0899_ACRPRESC              , 0x11 },
+       { STB0899_ACRDIV1               , 0x0a },
+       { STB0899_ACRDIV2               , 0x05 },
+       { STB0899_DACR1                 , 0x00 },
+       { STB0899_DACR2                 , 0x00 },
+       { STB0899_OUTCFG                , 0x00 },
+       { STB0899_MODECFG               , 0x00 },
        { STB0899_IRQSTATUS_3           , 0xfe },
        { STB0899_IRQSTATUS_2           , 0x03 },
        { STB0899_IRQSTATUS_1           , 0x7c },
        { STB0899_IRQSTATUS_0           , 0xf4 },
-       { STB0899_IRQMSK_3              , 0xf3 },
-       { STB0899_IRQMSK_2              , 0xfc },
-       { STB0899_IRQMSK_1              , 0xff },
+       { STB0899_IRQMSK_3              , 0xf3 },
+       { STB0899_IRQMSK_2              , 0xfc },
+       { STB0899_IRQMSK_1              , 0xff },
        { STB0899_IRQMSK_0              , 0xff },
        { STB0899_IRQCFG                , 0x00 },
-       { STB0899_I2CCFG                , 0x88 },
-       { STB0899_I2CRPT                , 0x58 },
+       { STB0899_I2CCFG                , 0x88 },
+       { STB0899_I2CRPT                , 0x58 },
        { STB0899_IOPVALUE5             , 0x00 },
        { STB0899_IOPVALUE4             , 0x33 },
        { STB0899_IOPVALUE3             , 0x6d },
        { STB0899_IOPVALUE2             , 0x90 },
        { STB0899_IOPVALUE1             , 0x60 },
        { STB0899_IOPVALUE0             , 0x00 },
-       { STB0899_GPIO00CFG             , 0x82 },
-       { STB0899_GPIO01CFG             , 0x82 },
-       { STB0899_GPIO02CFG             , 0x82 },
-       { STB0899_GPIO03CFG             , 0x82 },
-       { STB0899_GPIO04CFG             , 0x82 },
-       { STB0899_GPIO05CFG             , 0x82 },
-       { STB0899_GPIO06CFG             , 0x82 },
-       { STB0899_GPIO07CFG             , 0x82 },
-       { STB0899_GPIO08CFG             , 0x82 },
-       { STB0899_GPIO09CFG             , 0x82 },
-       { STB0899_GPIO10CFG             , 0x82 },
-       { STB0899_GPIO11CFG             , 0x82 },
-       { STB0899_GPIO12CFG             , 0x82 },
-       { STB0899_GPIO13CFG             , 0x82 },
-       { STB0899_GPIO14CFG             , 0x82 },
-       { STB0899_GPIO15CFG             , 0x82 },
-       { STB0899_GPIO16CFG             , 0x82 },
-       { STB0899_GPIO17CFG             , 0x82 },
-       { STB0899_GPIO18CFG             , 0x82 },
-       { STB0899_GPIO19CFG             , 0x82 },
-       { STB0899_GPIO20CFG             , 0x82 },
-       { STB0899_SDATCFG               , 0xb8 },
-       { STB0899_SCLTCFG               , 0xba },
-       { STB0899_AGCRFCFG              , 0x1c }, /* 0x11 */
-       { STB0899_GPIO22                , 0x82 }, /* AGCBB2CFG */
-       { STB0899_GPIO21                , 0x91 }, /* AGCBB1CFG */
-       { STB0899_DIRCLKCFG             , 0x82 },
-       { STB0899_CLKOUT27CFG           , 0x7e },
-       { STB0899_STDBYCFG              , 0x82 },
-       { STB0899_CS0CFG                , 0x82 },
-       { STB0899_CS1CFG                , 0x82 },
-       { STB0899_DISEQCOCFG            , 0x20 },
+       { STB0899_GPIO00CFG             , 0x82 },
+       { STB0899_GPIO01CFG             , 0x82 },
+       { STB0899_GPIO02CFG             , 0x82 },
+       { STB0899_GPIO03CFG             , 0x82 },
+       { STB0899_GPIO04CFG             , 0x82 },
+       { STB0899_GPIO05CFG             , 0x82 },
+       { STB0899_GPIO06CFG             , 0x82 },
+       { STB0899_GPIO07CFG             , 0x82 },
+       { STB0899_GPIO08CFG             , 0x82 },
+       { STB0899_GPIO09CFG             , 0x82 },
+       { STB0899_GPIO10CFG             , 0x82 },
+       { STB0899_GPIO11CFG             , 0x82 },
+       { STB0899_GPIO12CFG             , 0x82 },
+       { STB0899_GPIO13CFG             , 0x82 },
+       { STB0899_GPIO14CFG             , 0x82 },
+       { STB0899_GPIO15CFG             , 0x82 },
+       { STB0899_GPIO16CFG             , 0x82 },
+       { STB0899_GPIO17CFG             , 0x82 },
+       { STB0899_GPIO18CFG             , 0x82 },
+       { STB0899_GPIO19CFG             , 0x82 },
+       { STB0899_GPIO20CFG             , 0x82 },
+       { STB0899_SDATCFG               , 0xb8 },
+       { STB0899_SCLTCFG               , 0xba },
+       { STB0899_AGCRFCFG              , 0x1c }, /* 0x11 */
+       { STB0899_GPIO22                , 0x82 }, /* AGCBB2CFG */
+       { STB0899_GPIO21                , 0x91 }, /* AGCBB1CFG */
+       { STB0899_DIRCLKCFG             , 0x82 },
+       { STB0899_CLKOUT27CFG           , 0x7e },
+       { STB0899_STDBYCFG              , 0x82 },
+       { STB0899_CS0CFG                , 0x82 },
+       { STB0899_CS1CFG                , 0x82 },
+       { STB0899_DISEQCOCFG            , 0x20 },
        { STB0899_GPIO32CFG             , 0x82 },
        { STB0899_GPIO33CFG             , 0x82 },
        { STB0899_GPIO34CFG             , 0x82 },
@@ -119,35 +119,35 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_1[] = {
        { STB0899_GPIO37CFG             , 0x82 },
        { STB0899_GPIO38CFG             , 0x82 },
        { STB0899_GPIO39CFG             , 0x82 },
-       { STB0899_NCOARSE               , 0x17 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
-       { STB0899_SYNTCTRL              , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
-       { STB0899_FILTCTRL              , 0x00 },
-       { STB0899_SYSCTRL               , 0x01 },
-       { STB0899_STOPCLK1              , 0x20 },
-       { STB0899_STOPCLK2              , 0x00 },
+       { STB0899_NCOARSE               , 0x17 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
+       { STB0899_SYNTCTRL              , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
+       { STB0899_FILTCTRL              , 0x00 },
+       { STB0899_SYSCTRL               , 0x01 },
+       { STB0899_STOPCLK1              , 0x20 },
+       { STB0899_STOPCLK2              , 0x00 },
        { STB0899_INTBUFSTATUS          , 0x00 },
-       { STB0899_INTBUFCTRL            , 0x0a },
+       { STB0899_INTBUFCTRL            , 0x0a },
        { 0xffff                        , 0xff },
 };
 
 static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
-       { STB0899_DEMOD                 , 0x00 },
-       { STB0899_RCOMPC                , 0xc9 },
-       { STB0899_AGC1CN                , 0x01 },
-       { STB0899_AGC1REF               , 0x10 },
+       { STB0899_DEMOD                 , 0x00 },
+       { STB0899_RCOMPC                , 0xc9 },
+       { STB0899_AGC1CN                , 0x01 },
+       { STB0899_AGC1REF               , 0x10 },
        { STB0899_RTC                   , 0x23 },
-       { STB0899_TMGCFG                , 0x4e },
-       { STB0899_AGC2REF               , 0x34 },
-       { STB0899_TLSR                  , 0x84 },
-       { STB0899_CFD                   , 0xf7 },
+       { STB0899_TMGCFG                , 0x4e },
+       { STB0899_AGC2REF               , 0x34 },
+       { STB0899_TLSR                  , 0x84 },
+       { STB0899_CFD                   , 0xf7 },
        { STB0899_ACLC                  , 0x87 },
-       { STB0899_BCLC                  , 0x94 },
-       { STB0899_EQON                  , 0x41 },
-       { STB0899_LDT                   , 0xf1 },
-       { STB0899_LDT2                  , 0xe3 },
-       { STB0899_EQUALREF              , 0xb4 },
-       { STB0899_TMGRAMP               , 0x10 },
-       { STB0899_TMGTHD                , 0x30 },
+       { STB0899_BCLC                  , 0x94 },
+       { STB0899_EQON                  , 0x41 },
+       { STB0899_LDT                   , 0xf1 },
+       { STB0899_LDT2                  , 0xe3 },
+       { STB0899_EQUALREF              , 0xb4 },
+       { STB0899_TMGRAMP               , 0x10 },
+       { STB0899_TMGTHD                , 0x30 },
        { STB0899_IDCCOMP               , 0xfd },
        { STB0899_QDCCOMP               , 0xff },
        { STB0899_POWERI                , 0x0c },
@@ -166,12 +166,12 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
        { STB0899_NIRL                  , 0x80 },
        { STB0899_ISYMB                 , 0x1d },
        { STB0899_QSYMB                 , 0xa6 },
-       { STB0899_SFRH                  , 0x2f },
-       { STB0899_SFRM                  , 0x68 },
-       { STB0899_SFRL                  , 0x40 },
-       { STB0899_SFRUPH                , 0x2f },
-       { STB0899_SFRUPM                , 0x68 },
-       { STB0899_SFRUPL                , 0x40 },
+       { STB0899_SFRH                  , 0x2f },
+       { STB0899_SFRM                  , 0x68 },
+       { STB0899_SFRL                  , 0x40 },
+       { STB0899_SFRUPH                , 0x2f },
+       { STB0899_SFRUPM                , 0x68 },
+       { STB0899_SFRUPL                , 0x40 },
        { STB0899_EQUAI1                , 0x02 },
        { STB0899_EQUAQ1                , 0xff },
        { STB0899_EQUAI2                , 0x04 },
@@ -183,7 +183,7 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
        { STB0899_EQUAI5                , 0x08 },
        { STB0899_EQUAQ5                , 0xf5 },
        { STB0899_DSTATUS2              , 0x00 },
-       { STB0899_VSTATUS               , 0x00 },
+       { STB0899_VSTATUS               , 0x00 },
        { STB0899_VERROR                , 0x86 },
        { STB0899_IQSWAP                , 0x2a },
        { STB0899_ECNT1M                , 0x00 },
@@ -192,26 +192,26 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
        { STB0899_ECNT2L                , 0x00 },
        { STB0899_ECNT3M                , 0x0a },
        { STB0899_ECNT3L                , 0xad },
-       { STB0899_FECAUTO1              , 0x06 },
+       { STB0899_FECAUTO1              , 0x06 },
        { STB0899_FECM                  , 0x01 },
-       { STB0899_VTH12                 , 0xb0 },
-       { STB0899_VTH23                 , 0x7a },
+       { STB0899_VTH12                 , 0xb0 },
+       { STB0899_VTH23                 , 0x7a },
        { STB0899_VTH34                 , 0x58 },
-       { STB0899_VTH56                 , 0x38 },
-       { STB0899_VTH67                 , 0x34 },
-       { STB0899_VTH78                 , 0x24 },
-       { STB0899_PRVIT                 , 0xff },
-       { STB0899_VITSYNC               , 0x19 },
-       { STB0899_RSULC                 , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
-       { STB0899_TSULC                 , 0x42 },
-       { STB0899_RSLLC                 , 0x41 },
+       { STB0899_VTH56                 , 0x38 },
+       { STB0899_VTH67                 , 0x34 },
+       { STB0899_VTH78                 , 0x24 },
+       { STB0899_PRVIT                 , 0xff },
+       { STB0899_VITSYNC               , 0x19 },
+       { STB0899_RSULC                 , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
+       { STB0899_TSULC                 , 0x42 },
+       { STB0899_RSLLC                 , 0x41 },
        { STB0899_TSLPL                 , 0x12 },
-       { STB0899_TSCFGH                , 0x0c },
-       { STB0899_TSCFGM                , 0x00 },
-       { STB0899_TSCFGL                , 0x00 },
+       { STB0899_TSCFGH                , 0x0c },
+       { STB0899_TSCFGM                , 0x00 },
+       { STB0899_TSCFGL                , 0x00 },
        { STB0899_TSOUT                 , 0x69 }, /* 0x0d for CAM */
-       { STB0899_RSSYNCDEL             , 0x00 },
-       { STB0899_TSINHDELH             , 0x02 },
+       { STB0899_RSSYNCDEL             , 0x00 },
+       { STB0899_TSINHDELH             , 0x02 },
        { STB0899_TSINHDELM             , 0x00 },
        { STB0899_TSINHDELL             , 0x00 },
        { STB0899_TSLLSTKM              , 0x1b },
@@ -222,18 +222,18 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
        { STB0899_PCKLENLL              , 0xcc },
        { STB0899_RSPCKLEN              , 0xbd },
        { STB0899_TSSTATUS              , 0x90 },
-       { STB0899_ERRCTRL1              , 0xb6 },
-       { STB0899_ERRCTRL2              , 0x95 },
-       { STB0899_ERRCTRL3              , 0x8d },
+       { STB0899_ERRCTRL1              , 0xb6 },
+       { STB0899_ERRCTRL2              , 0x95 },
+       { STB0899_ERRCTRL3              , 0x8d },
        { STB0899_DMONMSK1              , 0x27 },
        { STB0899_DMONMSK0              , 0x03 },
-       { STB0899_DEMAPVIT              , 0x5c },
+       { STB0899_DEMAPVIT              , 0x5c },
        { STB0899_PLPARM                , 0x19 },
-       { STB0899_PDELCTRL              , 0x48 },
-       { STB0899_PDELCTRL2             , 0x00 },
-       { STB0899_BBHCTRL1              , 0x00 },
-       { STB0899_BBHCTRL2              , 0x00 },
-       { STB0899_HYSTTHRESH            , 0x77 },
+       { STB0899_PDELCTRL              , 0x48 },
+       { STB0899_PDELCTRL2             , 0x00 },
+       { STB0899_BBHCTRL1              , 0x00 },
+       { STB0899_BBHCTRL2              , 0x00 },
+       { STB0899_HYSTTHRESH            , 0x77 },
        { STB0899_MATCSTM               , 0x00 },
        { STB0899_MATCSTL               , 0x00 },
        { STB0899_UPLCSTM               , 0x00 },
@@ -270,7 +270,7 @@ static struct stb0899_config vp1041_stb0899_config = {
        .init_s2_fec            = stb0899_s2_init_4,
        .init_tst               = stb0899_s1_init_5,
 
-       .demod_address          = 0x68, /*  0xd0 >> 1 */
+       .demod_address          = 0x68, /*  0xd0 >> 1 */
 
        .xtal_freq              = 27000000,
        .inversion              = IQ_SWAP_ON,
index 23999a8cef37763abc52df42360d6730fae587ad..be860ec129b6ad60e4c7f2764bfd79bccdf7acc1 100644 (file)
@@ -1536,7 +1536,7 @@ static const struct v4l2_ioctl_ops meye_ioctl_ops = {
 static const struct video_device meye_template = {
        .name           = "meye",
        .fops           = &meye_fops,
-       .ioctl_ops      = &meye_ioctl_ops,
+       .ioctl_ops      = &meye_ioctl_ops,
        .release        = video_device_release_empty,
 };
 
index 9965d3531c8051a560569dfc0a947a26c863a184..9d6688a82b509466a60522afe6d620c6c7b2627d 100644 (file)
@@ -323,7 +323,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x20,
+               .empress_addr   = 0x20,
 
                .inputs         = {{
                        .type = SAA7134_INPUT_COMPOSITE1,
@@ -454,7 +454,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x20,
+               .empress_addr   = 0x20,
                .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x820000,
                .inputs         = {{
@@ -849,7 +849,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x20,
+               .empress_addr   = 0x20,
                .inputs         = {{
                        .type = SAA7134_INPUT_COMPOSITE1,
                        .vmux = 4,
@@ -1006,7 +1006,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x20,
+               .empress_addr   = 0x20,
                .inputs         = {{
                        .type = SAA7134_INPUT_COMPOSITE1,
                        .vmux = 1,
@@ -1767,7 +1767,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = {{
                        .type = SAA7134_INPUT_TV,
@@ -2412,7 +2412,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x21,
+               .empress_addr   = 0x21,
                .inputs         = {{
                        .type = SAA7134_INPUT_COMPOSITE0,
                        .vmux   = 0,
@@ -3978,13 +3978,13 @@ struct saa7134_board saa7134_boards[] = {
        [SAA7134_BOARD_BEHOLD_407] = {
                /*       Beholder Intl. Ltd. 2008      */
                /*Dmitry Belimov <d.belimov@gmail.com> */
-               .name           = "Beholder BeholdTV 407",
-               .audio_clock    = 0x00187de7,
-               .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
-               .radio_type     = UNSET,
-               .tuner_addr     = ADDR_UNSET,
-               .radio_addr     = ADDR_UNSET,
-               .tda9887_conf   = TDA9887_PRESENT,
+               .name           = "Beholder BeholdTV 407",
+               .audio_clock    = 0x00187de7,
+               .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+               .radio_type     = UNSET,
+               .tuner_addr     = ADDR_UNSET,
+               .radio_addr     = ADDR_UNSET,
+               .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x00008000,
                .inputs = {{
                        .type = SAA7134_INPUT_SVIDEO,
@@ -4006,13 +4006,13 @@ struct saa7134_board saa7134_boards[] = {
        [SAA7134_BOARD_BEHOLD_407FM] = {
                /*       Beholder Intl. Ltd. 2008      */
                /*Dmitry Belimov <d.belimov@gmail.com> */
-               .name           = "Beholder BeholdTV 407 FM",
-               .audio_clock    = 0x00187de7,
-               .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
-               .radio_type     = UNSET,
-               .tuner_addr     = ADDR_UNSET,
-               .radio_addr     = ADDR_UNSET,
-               .tda9887_conf   = TDA9887_PRESENT,
+               .name           = "Beholder BeholdTV 407 FM",
+               .audio_clock    = 0x00187de7,
+               .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+               .radio_type     = UNSET,
+               .tuner_addr     = ADDR_UNSET,
+               .radio_addr     = ADDR_UNSET,
+               .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x00008000,
                .inputs = {{
                        .type = SAA7134_INPUT_SVIDEO,
@@ -4103,7 +4103,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x00008000,
                .inputs         = {{
@@ -4166,7 +4166,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x00008000,
                .inputs         = {{
@@ -4196,7 +4196,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x00008000,
                .inputs         = {{
@@ -4366,7 +4366,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = {{
                        .type = SAA7134_INPUT_TV,
@@ -4394,7 +4394,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = {{
                        .type = SAA7134_INPUT_TV,
@@ -4422,7 +4422,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = {{
                        .type = SAA7134_INPUT_TV,
@@ -4450,7 +4450,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = {{
                        .type = SAA7134_INPUT_TV,
@@ -4481,7 +4481,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x20,
+               .empress_addr   = 0x20,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = { {
                        .type = SAA7134_INPUT_TV,
@@ -4517,7 +4517,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .empress_addr   = 0x20,
+               .empress_addr   = 0x20,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = { {
                        .type = SAA7134_INPUT_TV,
@@ -4554,8 +4554,8 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
-               .empress_addr   = 0x20,
+               .rds_addr       = 0x10,
+               .empress_addr   = 0x20,
                .tda9887_conf   = TDA9887_PRESENT,
                .inputs         = { {
                        .type = SAA7134_INPUT_TV,
@@ -5297,7 +5297,7 @@ struct saa7134_board saa7134_boards[] = {
                .radio_type     = UNSET,
                .tuner_addr     = ADDR_UNSET,
                .radio_addr     = ADDR_UNSET,
-               .rds_addr       = 0x10,
+               .rds_addr       = 0x10,
                .tda9887_conf   = TDA9887_PRESENT,
                .gpiomask       = 0x00008000,
                .inputs         = {{
index b55f9a1d9a63e1da973c9545e3fd847a8da13ae2..a7a63d608dde0c24265113701959a7cb70083ecd 100644 (file)
@@ -1389,7 +1389,7 @@ static int dvb_init(struct saa7134_dev *dev)
                        if (configure_tda827x_fe(dev, &lifeview_trio_config,
                                                 &tda827x_cfg_0) < 0)
                                goto detach_frontend;
-               } else {                /* satellite */
+               } else {                /* satellite */
                        fe0->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap);
                        if (fe0->dvb.frontend) {
                                if (dvb_attach(tda826x_attach, fe0->dvb.frontend, 0x63,
@@ -1659,7 +1659,7 @@ static int dvb_init(struct saa7134_dev *dev)
                        if (configure_tda827x_fe(dev, &asus_tiger_3in1_config,
                                                        &tda827x_cfg_2) < 0)
                                goto detach_frontend;
-               } else {                /* satellite */
+               } else {                /* satellite */
                        fe0->dvb.frontend = dvb_attach(tda10086_attach,
                                                &flydvbs, &dev->i2c_adap);
                        if (fe0->dvb.frontend) {
index 1ae5d2dac3bf43c3c09b2719a14efe67d009ab4b..052e101d898cbc6accd0965c234de04e532ac2af 100644 (file)
@@ -2043,14 +2043,14 @@ static const struct v4l2_ioctl_ops radio_ioctl_ops = {
 struct video_device saa7134_video_template = {
        .name                           = "saa7134-video",
        .fops                           = &video_fops,
-       .ioctl_ops                      = &video_ioctl_ops,
+       .ioctl_ops                      = &video_ioctl_ops,
        .tvnorms                        = SAA7134_NORMS,
 };
 
 struct video_device saa7134_radio_template = {
        .name                   = "saa7134-radio",
        .fops                   = &radio_fops,
-       .ioctl_ops              = &radio_ioctl_ops,
+       .ioctl_ops              = &radio_ioctl_ops,
 };
 
 static const struct v4l2_ctrl_ops saa7134_ctrl_ops = {
index 39c36e6aefbea20dba7f5fafd183d628e9b597b5..d99e937a98c120a3aafa1f739c9ed83257fbe7a8 100644 (file)
@@ -261,8 +261,8 @@ struct saa7134_card_ir {
 #define SAA7134_BOARD_SABRENT_TV_PCB05     115
 #define SAA7134_BOARD_10MOONSTVMASTER3     116
 #define SAA7134_BOARD_AVERMEDIA_SUPER_007  117
-#define SAA7134_BOARD_BEHOLD_401       118
-#define SAA7134_BOARD_BEHOLD_403       119
+#define SAA7134_BOARD_BEHOLD_401       118
+#define SAA7134_BOARD_BEHOLD_403       119
 #define SAA7134_BOARD_BEHOLD_403FM     120
 #define SAA7134_BOARD_BEHOLD_405       121
 #define SAA7134_BOARD_BEHOLD_405FM     122
@@ -581,7 +581,7 @@ struct saa7134_dev {
        /* config info */
        unsigned int               board;
        unsigned int               tuner_type;
-       unsigned int               radio_type;
+       unsigned int               radio_type;
        unsigned char              tuner_addr;
        unsigned char              radio_addr;
 
@@ -592,7 +592,7 @@ struct saa7134_dev {
        struct i2c_adapter         i2c_adap;
        struct i2c_client          i2c_client;
        unsigned char              eedata[256];
-       int                        has_rds;
+       int                        has_rds;
 
        /* video overlay */
        struct v4l2_framebuffer    ovbuf;
index 39357eddee32ac35a8eeeea89c74bca256aa7d94..5817d9cde4d0c0f448679b48ec418cfea02fc2ec 100644 (file)
@@ -70,8 +70,8 @@ struct hexium
        struct video_device     video_dev;
        struct i2c_adapter      i2c_adapter;
 
-       int             cur_input;      /* current input */
-       v4l2_std_id     cur_std;        /* current standard */
+       int             cur_input;      /* current input */
+       v4l2_std_id     cur_std;        /* current standard */
 };
 
 /* Samsung KS0127B decoder default registers */
@@ -138,19 +138,19 @@ static struct hexium_data hexium_input_select[] = {
    are currently *not* supported*/
 static struct saa7146_standard hexium_standards[] = {
        {
-               .name   = "PAL",        .id     = V4L2_STD_PAL,
-               .v_offset       = 28,   .v_field        = 288,
-               .h_offset       = 1,    .h_pixels       = 680,
+               .name   = "PAL",        .id     = V4L2_STD_PAL,
+               .v_offset       = 28,   .v_field        = 288,
+               .h_offset       = 1,    .h_pixels       = 680,
                .v_max_out      = 576,  .h_max_out      = 768,
        }, {
-               .name   = "NTSC",       .id     = V4L2_STD_NTSC,
-               .v_offset       = 28,   .v_field        = 240,
-               .h_offset       = 1,    .h_pixels       = 640,
+               .name   = "NTSC",       .id     = V4L2_STD_NTSC,
+               .v_offset       = 28,   .v_field        = 240,
+               .h_offset       = 1,    .h_pixels       = 640,
                .v_max_out      = 480,  .h_max_out      = 640,
        }, {
-               .name   = "SECAM",      .id     = V4L2_STD_SECAM,
-               .v_offset       = 28,   .v_field        = 288,
-               .h_offset       = 1,    .h_pixels       = 720,
+               .name   = "SECAM",      .id     = V4L2_STD_SECAM,
+               .v_offset       = 28,   .v_field        = 288,
+               .h_offset       = 1,    .h_pixels       = 720,
                .v_max_out      = 576,  .h_max_out      = 768,
        }
 };
index 461e421080f38ba66f18ebbb4b335a6645c0bb66..0a05176c18ab6e55fab01c3e859d738f02d8cf85 100644 (file)
@@ -188,19 +188,19 @@ static struct {
 
 static struct saa7146_standard hexium_standards[] = {
        {
-               .name   = "PAL",        .id     = V4L2_STD_PAL,
-               .v_offset       = 16,   .v_field        = 288,
-               .h_offset       = 1,    .h_pixels       = 680,
+               .name   = "PAL",        .id     = V4L2_STD_PAL,
+               .v_offset       = 16,   .v_field        = 288,
+               .h_offset       = 1,    .h_pixels       = 680,
                .v_max_out      = 576,  .h_max_out      = 768,
        }, {
-               .name   = "NTSC",       .id     = V4L2_STD_NTSC,
-               .v_offset       = 16,   .v_field        = 240,
-               .h_offset       = 1,    .h_pixels       = 640,
+               .name   = "NTSC",       .id     = V4L2_STD_NTSC,
+               .v_offset       = 16,   .v_field        = 240,
+               .h_offset       = 1,    .h_pixels       = 640,
                .v_max_out      = 480,  .h_max_out      = 640,
        }, {
-               .name   = "SECAM",      .id     = V4L2_STD_SECAM,
-               .v_offset       = 16,   .v_field        = 288,
-               .h_offset       = 1,    .h_pixels       = 720,
+               .name   = "SECAM",      .id     = V4L2_STD_SECAM,
+               .v_offset       = 16,   .v_field        = 288,
+               .h_offset       = 1,    .h_pixels       = 720,
                .v_max_out      = 576,  .h_max_out      = 768,
        }
 };
index 2526fc051b65d0d364f8382ea55fdf21a730f4e3..6b5582b7c5955ca1b514712ac83f60a228f6c16c 100644 (file)
@@ -793,24 +793,24 @@ static int std_callback(struct saa7146_dev *dev, struct saa7146_standard *standa
 
 static struct saa7146_standard standard[] = {
        {
-               .name   = "PAL-BG",     .id     = V4L2_STD_PAL_BG,
-               .v_offset       = 0x17, .v_field        = 288,
-               .h_offset       = 0x14, .h_pixels       = 680,
+               .name   = "PAL-BG",     .id     = V4L2_STD_PAL_BG,
+               .v_offset       = 0x17, .v_field        = 288,
+               .h_offset       = 0x14, .h_pixels       = 680,
                .v_max_out      = 576,  .h_max_out      = 768,
        }, {
-               .name   = "PAL-I",      .id     = V4L2_STD_PAL_I,
-               .v_offset       = 0x17, .v_field        = 288,
-               .h_offset       = 0x14, .h_pixels       = 680,
+               .name   = "PAL-I",      .id     = V4L2_STD_PAL_I,
+               .v_offset       = 0x17, .v_field        = 288,
+               .h_offset       = 0x14, .h_pixels       = 680,
                .v_max_out      = 576,  .h_max_out      = 768,
        }, {
-               .name   = "NTSC",       .id     = V4L2_STD_NTSC,
-               .v_offset       = 0x16, .v_field        = 240,
-               .h_offset       = 0x06, .h_pixels       = 708,
+               .name   = "NTS