drm/rockchip: pre dither down when output bpc is 8bit
authorMark Yao <mark.yao@rock-chips.com>
Mon, 23 Apr 2018 10:49:57 +0000 (12:49 +0200)
committerAndrzej Hajda <a.hajda@samsung.com>
Tue, 24 Apr 2018 06:34:47 +0000 (08:34 +0200)
Some encoder have a crc verification check, crc check fail if
input and output data is not equal.

That means encoder input and output need use same color depth,
vop can output 10bit data to encoder, but some panel only support
8bit depth, that would make crc check die.

So pre dither down vop data to 8bit if panel's bpc is 8.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
[seanpaul resolved conflict in rockchip_drm_vop.c]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-22-enric.balletbo@collabora.com
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
drivers/gpu/drm/rockchip/rockchip_vop_reg.c

index 8c884f9ce713a69baaa7c1d4c361ea015831d999..b3f46ed24cdc047dcf49c3709158f746db5e6821 100644 (file)
@@ -218,6 +218,7 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
                                      struct drm_connector_state *conn_state)
 {
        struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+       struct drm_display_info *di = &conn_state->connector->display_info;
 
        /*
         * The hardware IC designed that VOP must output the RGB10 video
@@ -229,6 +230,7 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
 
        s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
        s->output_type = DRM_MODE_CONNECTOR_eDP;
+       s->output_bpc = di->bpc;
 
        return 0;
 }
index 9c064a40458bea01b2cb9c79c781030f763e44e2..3a6ebfc26036e6a5d3fc396d583028e1633a8907 100644 (file)
@@ -36,6 +36,7 @@ struct rockchip_crtc_state {
        struct drm_crtc_state base;
        int output_type;
        int output_mode;
+       int output_bpc;
 };
 #define to_rockchip_crtc_state(s) \
                container_of(s, struct rockchip_crtc_state, base)
index 510cdf076bb1848b05bc8558ea28de5bd41f21b5..026df454a5d54d4a920ea7fe167e4e34894ccae6 100644 (file)
@@ -925,6 +925,12 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
        if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
            !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
                s->output_mode = ROCKCHIP_OUT_MODE_P888;
+
+       if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8)
+               VOP_REG_SET(vop, common, pre_dither_down, 1);
+       else
+               VOP_REG_SET(vop, common, pre_dither_down, 0);
+
        VOP_REG_SET(vop, common, out_mode, s->output_mode);
 
        VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
index 56bbd2e2a8efb95b7ae45ef985175add37abf3a0..084acdd0019a8d3d873e7fd8c590ed6de91313be 100644 (file)
@@ -67,6 +67,7 @@ struct vop_common {
        struct vop_reg cfg_done;
        struct vop_reg dsp_blank;
        struct vop_reg data_blank;
+       struct vop_reg pre_dither_down;
        struct vop_reg dither_down;
        struct vop_reg dither_up;
        struct vop_reg gate_en;
index 2e4eea3459fe60a3a011eef9cb20cd62e4dce14b..08023d3ecb76c07a5c5976acf53e2d5375093529 100644 (file)
@@ -264,6 +264,7 @@ static const struct vop_common rk3288_common = {
        .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
        .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
        .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
+       .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
        .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
        .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
        .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),