spi: lpspi: fix dataloss when SS is inactivated between every words

If we don't use CONT to keep SS activated or use DMA mode without
cs-gpio, SS will be inactivated between every words. The word here
means the data sent once which length can be set as 1/2/4 bytes.

In the isr function, we read the FSR_RXCOUNT just behind the
fsl_lpspi_read_rx_fifo. This causes the value of FSR_RXCOUNT cannot
reflect whether there is still data not sent timely. So do this
judgement by FSR_TXCOUNT.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index 3918639140436e16707f854d8a5a5b9725515ce7..9e117c4635d85eda2518c0d6d4c5dd20e0ce9666 100644 (file)
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -62,7 +62,7 @@
 #define CFGR1_PCSPOL   BIT(8)
 #define CFGR1_NOSTALL  BIT(3)
 #define CFGR1_MASTER   BIT(0)
-#define FSR_RXCOUNT    (BIT(16)|BIT(17)|BIT(18))
+#define FSR_TXCOUNT    (0xFF)
 #define RSR_RXEMPTY    BIT(1)
 #define TCR_CPOL       BIT(31)
 #define TCR_CPHA       BIT(30)
@@ -452,7 +452,7 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
        }
 
        if (temp_SR & SR_MBF ||
-           readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
+           readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
                writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
                fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
                return IRQ_HANDLED;