Merge branch 'drm-radeon-testing' of /ssd/git/drm-radeon-next into drm-next-stage

* 'drm-radeon-testing' of /ssd/git/drm-radeon-next:
  drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond
  drm/ttm: fix function prototype to match implementation
  drm/radeon: use ALIGN instead of open coding it
  drm/radeon/kms: initialize set_surface_reg reg for rs600 asic

diff --combined drivers/gpu/drm/radeon/radeon_drv.h
index 88f4d8669d845fa32ee8253cf852af246c168283,ee484b61bc5cf39833494a357c81853d70ce9b2a..cf911859eac2c7dd7cfa3fe425311ca1e2a7648c
--- 1/drivers/gpu/drm/radeon/radeon_drv.h
--- 2/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@@ -106,10 -106,9 +106,10 @@@
   * 1.29- R500 3D cmd buffer support
   * 1.30- Add support for occlusion queries
   * 1.31- Add support for num Z pipes from GET_PARAM
 + * 1.32- fixes for rv740 setup
   */
  #define DRIVER_MAJOR          1
 -#define DRIVER_MINOR          31
 +#define DRIVER_MINOR          32
  #define DRIVER_PATCHLEVEL     0
  
  enum radeon_cp_microcode_version {
@@@ -268,6 -267,8 +268,8 @@@ typedef struct drm_radeon_private 
  
        u32 scratch_ages[5];
  
+       int have_z_offset;
+ 
        /* starting from here on, data is preserved accross an open */
        uint32_t flags;         /* see radeon_chip_flags */
        resource_size_t fb_aper_offset;

diff --combined drivers/gpu/drm/radeon/radeon_state.c
index 32971b8272cf9fb61c3ea53a9f5a16b4113bc7b9,8e69dc485dcb9bb106db6fe990e1803b7ebd020c..3c32f840dcd2294b3ee5d0af9407f21c9354209e
--- 1/drivers/gpu/drm/radeon/radeon_state.c
--- 2/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@@ -105,6 -105,7 +105,7 @@@ static __inline__ int radeon_check_and_
                        DRM_ERROR("Invalid depth buffer offset\n");
                        return -EINVAL;
                }
+               dev_priv->have_z_offset = 1;
                break;
  
        case RADEON_EMIT_PP_CNTL:
@@@ -898,6 -899,11 +899,11 @@@ static void radeon_cp_dispatch_clear(st
                if (tmp & RADEON_BACK)
                        flags |= RADEON_FRONT;
        }
+       if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
+               if (!dev_priv->have_z_offset)
+                       printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
+               flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
+       }
  
        if (flags & (RADEON_FRONT | RADEON_BACK)) {
  
@@@ -1972,7 -1978,7 +1978,7 @@@ static void radeon_apply_surface_regs(i
   * Note that refcount can be at most 2, since during a free refcount=3
   * might mean we have to allocate a new surface which might not always
   * be available.
 - * For example : we allocate three contigous surfaces ABC. If B is
 + * For example : we allocate three contiguous surfaces ABC. If B is
   * freed, we suddenly need two surfaces to store A and C, which might
   * not always be available.
   */