Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 26 Jul 2010 20:06:39 +0000 (13:06 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 26 Jul 2010 20:06:39 +0000 (13:06 -0700)
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6:
  USB: musb: tusb6010: fix compile error with n8x0_defconfig
  USB: FTDI: Add support for the RT System VX-7 radio programming cable
  USB: add quirk for Broadcom BT dongle
  USB: usb-storage: fix initializations of urb fields
  USB: xhci: Set Mult field in endpoint context correctly.
  USB: sisusbvga: Fix for USB 3.0
  USB: adds Artisman USB dongle to list of quirky devices
  USB: xhci: Set EP0 dequeue ptr after reset of configured device.
  USB: Fix USB3.0 Port Speed Downgrade after port reset
  USB: xHCI: Fix another bug in link TRB activation change.
  USB: option: Add support for AMOI Skypephone S2
  USB: New PIDs for Qualcomm gobi 2000 (qcserial)
  USB: ftdi_sio: support for Signalyzer tools based on FTDI chips
  USB: s3c2410_udc: be aware of connected gadget driver
  USB: Expose vendor-specific ACM channel on Nokia 5230
  USB: Add PID for Sierra 250U to drivers/usb/serial/sierra.c
  USB: option: add support for 1da5:4518

35 files changed:
arch/arm/mach-clps711x/include/mach/debug-macro.S
arch/arm/mach-footbridge/common.c
arch/arm/mach-h720x/include/mach/debug-macro.S
arch/arm/mach-kirkwood/tsx1x-common.c
arch/arm/mach-kirkwood/tsx1x-common.h
arch/arm/mach-ns9xxx/include/mach/debug-macro.S
arch/arm/mach-ns9xxx/include/mach/uncompress.h
arch/arm/mach-pxa/colibri-pxa300.c
arch/arm/mach-pxa/corgi.c
arch/arm/mach-pxa/cpufreq-pxa2xx.c
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-shark/include/mach/debug-macro.S
arch/arm/mach-w90x900/cpu.c
arch/arm/plat-spear/include/plat/debug-macro.S
arch/avr32/include/asm/ioctls.h
arch/avr32/mach-at32ap/include/mach/board.h
arch/x86/kvm/paging_tmpl.h
arch/x86/kvm/x86.c
drivers/char/agp/intel-gtt.c
drivers/char/tpm/tpm_tis.c
drivers/edac/i7core_edac.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_fb.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/pcmcia/pxa2xx_base.c
drivers/serial/atmel_serial.c
drivers/usb/gadget/pxa27x_udc.c
drivers/usb/host/ohci-pxa27x.c

index fedd8076a689a3555a986b5e96bc9348cf4ae77f..072cc6b61ba30b7b6e363040b40d409e8a43e38f 100644 (file)
@@ -11,6 +11,7 @@
  *
 */
 
+#include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
 
                .macro  addruart, rx, tmp
index e3bc3f6f6b105d42c8d4f73d33b4d5f92fc15a81..88b3dd89be89a20b65761de100c7799798ccb1df 100644 (file)
@@ -232,7 +232,7 @@ EXPORT_SYMBOL(__bus_to_virt);
 
 unsigned long __pfn_to_bus(unsigned long pfn)
 {
-       return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
+       return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
 }
 EXPORT_SYMBOL(__pfn_to_bus);
 
index a9ee8f0d48b7f6792ea5004844649c3acb3a5bd0..27cafd12f033cbba19bd507e5a90ac198c1db8e1 100644 (file)
  *
 */
 
-               .equ    io_virt, IO_BASE
-               .equ    io_phys, IO_START
+#include <mach/hardware.h>
+
+               .equ    io_virt, IO_VIRT
+               .equ    io_phys, IO_PHYS
 
                .macro  addruart, rx, tmp
                mrc     p15, 0, \rx, c1, c0
index 7221c20b2afa241b5854c90b90f24352b73572c8..f781164e623fc89e7a4362b3d039f9e58688fd0d 100644 (file)
@@ -77,7 +77,7 @@ struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
        },
 };
 
-void qnap_tsx1x_register_flash(void)
+void __init qnap_tsx1x_register_flash(void)
 {
        spi_register_board_info(qnap_tsx1x_spi_slave_info,
                                ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
index 9a592962a6ea0df6f7546d847a50b150d45243c1..7fa037361b55a5e23738f9a37c8637f64d91b56e 100644 (file)
@@ -1,7 +1,7 @@
 #ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
 #define __ARCH_KIRKWOOD_TSX1X_COMMON_H
 
-extern void qnap_tsx1x_register_flash(void);
+extern void __init qnap_tsx1x_register_flash(void);
 extern void qnap_tsx1x_power_off(void);
 
 #endif
index 0859336a8e6d1be71a8090c1e8ef53b1640c87bc..5c934bdb71583e037c59fdadc3490e43838ff425 100644 (file)
@@ -8,6 +8,7 @@
  * the Free Software Foundation.
  */
 #include <mach/hardware.h>
+#include <asm/memory.h>
 
 #include <mach/regs-board-a9m9750dev.h>
 
index 1b12d324b087d1528c87d828bebec3308be1dbaa..770a68c46e8114f4a7360b559e0ddecd15cfdc57 100644 (file)
@@ -20,50 +20,49 @@ static void putc_dummy(char c, void __iomem *base)
        /* nothing */
 }
 
+static int timeout;
+
 static void putc_ns9360(char c, void __iomem *base)
 {
-       static int t = 0x10000;
        do {
-               if (t)
-                       --t;
+               if (timeout)
+                       --timeout;
 
                if (__raw_readl(base + 8) & (1 << 3)) {
                        __raw_writeb(c, base + 16);
-                       t = 0x10000;
+                       timeout = 0x10000;
                        break;
                }
-       } while (t);
+       } while (timeout);
 }
 
 static void putc_a9m9750dev(char c, void __iomem *base)
 {
-       static int t = 0x10000;
        do {
-               if (t)
-                       --t;
+               if (timeout)
+                       --timeout;
 
                if (__raw_readb(base + 5) & (1 << 5)) {
                        __raw_writeb(c, base);
-                       t = 0x10000;
+                       timeout = 0x10000;
                        break;
                }
-       } while (t);
+       } while (timeout);
 
 }
 
 static void putc_ns921x(char c, void __iomem *base)
 {
-       static int t = 0x10000;
        do {
-               if (t)
-                       --t;
+               if (timeout)
+                       --timeout;
 
                if (!(__raw_readl(base) & (1 << 11))) {
                        __raw_writeb(c, base + 0x0028);
-                       t = 0x10000;
+                       timeout = 0x10000;
                        break;
                }
-       } while (t);
+       } while (timeout);
 }
 
 #define MSCS __REG(0xA0900184)
@@ -89,6 +88,7 @@ static void putc_ns921x(char c, void __iomem *base)
 
 static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
 {
+       timeout = 0x10000;
        if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
                /* ns9360 or ns9750 */
                if (NS9360_UART_ENABLED(NS9360_UARTA)) {
index 45c23fd6df31e9696d2b0c42be0752cba1683217..40b6ac2de876cf8dcc4c0328b72b086e15253eb8 100644 (file)
@@ -26,6 +26,7 @@
 #include <mach/colibri.h>
 #include <mach/ohci.h>
 #include <mach/pxafb.h>
+#include <mach/audio.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -145,7 +146,7 @@ static void __init colibri_pxa300_init_lcd(void)
 static inline void colibri_pxa300_init_lcd(void) {}
 #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
 
-#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
+#if defined(CONFIG_SND_AC97_CODEC) || defined(CONFIG_SND_AC97_CODEC_MODULE)
 static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
        GPIO24_AC97_SYSCLK,
        GPIO23_AC97_nACRESET,
index 3d1dcb9ac08f497fc63e333ee6d20438f20d0d28..51ffa6afb67530e5cde74659319584ac52646593 100644 (file)
@@ -446,7 +446,7 @@ static struct platform_device corgiled_device = {
 static struct pxamci_platform_data corgi_mci_platform_data = {
        .detect_delay_ms        = 250,
        .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
-       .gpio_card_detect       = -1,
+       .gpio_card_detect       = CORGI_GPIO_nSD_DETECT,
        .gpio_card_ro           = CORGI_GPIO_nSD_WP,
        .gpio_power             = CORGI_GPIO_SD_PWR,
 };
index 9e4d9816726ad5d75c0657f9a32d0b36c0ec3aa7..268a9bc6be8a22a4ca0ac4fed742d035753581a3 100644 (file)
@@ -256,13 +256,9 @@ static void init_sdram_rows(void)
 
 static u32 mdrefr_dri(unsigned int freq)
 {
-       u32 dri = 0;
+       u32 interval = freq * SDRAM_TREF / sdram_rows;
 
-       if (cpu_is_pxa25x())
-               dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
-       if (cpu_is_pxa27x())
-               dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
-       return dri;
+       return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
 }
 
 /* find a valid frequency point */
index 0af36177ff085c92f34cd729bd5775f25d948a2f..c059dac02b61412b64b22f869d2e8913404236ed 100644 (file)
@@ -41,10 +41,10 @@ void pxa27x_clear_otgph(void)
 EXPORT_SYMBOL(pxa27x_clear_otgph);
 
 static unsigned long ac97_reset_config[] = {
-       GPIO95_AC97_nRESET,
-       GPIO95_GPIO,
-       GPIO113_AC97_nRESET,
        GPIO113_GPIO,
+       GPIO113_AC97_nRESET,
+       GPIO95_GPIO,
+       GPIO95_AC97_nRESET,
 };
 
 void pxa27x_assert_ac97reset(int reset_gpio, int on)
index 50f071c5bf4d603656a01a9c8c2865bf07ee2eb9..5ea24d4d1ba6e176985b16076b48412952de9aec 100644 (file)
@@ -20,6 +20,9 @@
                strb    \rd, [\rx]
                .endm
 
+               .macro waituart,rd,rx
+               .endm
+
                .macro  busyuart,rd,rx
                mov     \rd, #0
 1001:          add     \rd, \rd, #1
index 642207e18198db20777ef475a27ada0bd2ae0c3d..83c56324a472f16a5f155df056b4cc29ba9e562d 100644 (file)
@@ -93,7 +93,7 @@ static struct clk_lookup nuc900_clkregs[] = {
        DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
        DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
        DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
-       DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
+       DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
        DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
        DEF_CLKLOOK(&clk_ext, NULL, "ext"),
        DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
index 1670734b7e5159d34ada41710c0dc5381fcc4c3a..37fa593884ee64d345add30e2ca9738e238e3511 100644 (file)
@@ -17,8 +17,8 @@
                .macro  addruart, rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                                 @ MMU enabled?
-               moveq   \rx, =SPEAR_DBG_UART_BASE               @ Physical base
-               movne   \rx, =VA_SPEAR_DBG_UART_BASE            @ Virtual base
+               moveq   \rx, #SPEAR_DBG_UART_BASE               @ Physical base
+               movne   \rx, #VA_SPEAR_DBG_UART_BASE            @ Virtual base
                .endm
 
                .macro  senduart, rd, rx
index 0cf2c0a4502bd55769edf2166899a2c47d833f8a..e6ac0b6610763e6a51c30d64c607691c4fe869fe 100644 (file)
@@ -54,6 +54,9 @@
 #define TIOCGPTN       _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK     _IOW('T',0x31, int)  /* Lock/unlock Pty */
 
+#define TIOCGRS485      0x542E
+#define TIOCSRS485      0x542F
+
 #define FIONCLEX       0x5450
 #define FIOCLEX                0x5451
 #define FIOASYNC       0x5452
index c7f25bb1d068e0de55c8d2eeeb9ea817d5232328..61740201b3115eb7988ff3eca6728195f5d90d8b 100644 (file)
@@ -5,6 +5,7 @@
 #define __ASM_ARCH_BOARD_H
 
 #include <linux/types.h>
+#include <linux/serial.h>
 
 #define GPIO_PIN_NONE  (-1)
 
@@ -35,6 +36,7 @@ struct atmel_uart_data {
        short           use_dma_tx;     /* use transmit DMA? */
        short           use_dma_rx;     /* use receive DMA? */
        void __iomem    *regs;          /* virtual base address, if any */
+       struct serial_rs485     rs485;          /* rs485 settings */
 };
 void at32_map_usart(unsigned int hw_id, unsigned int line, int flags);
 struct platform_device *at32_add_device_usart(unsigned int id);
index 89d66ca4d87cb2982ae48c5877580e733ab0cce8..2331bdc2b549569e56f7dcec275c72bf06275928 100644 (file)
@@ -342,6 +342,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
                        /* advance table_gfn when emulating 1gb pages with 4k */
                        if (delta == 0)
                                table_gfn += PT_INDEX(addr, level);
+                       access &= gw->pte_access;
                } else {
                        direct = 0;
                        table_gfn = gw->table_gfn[level - 2];
index 05d571f6f19615cab8a90dec413e0a39537e914a..7fa89c39c64f67df0a62804cfa242ae6a2d6f638 100644 (file)
@@ -1562,7 +1562,7 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
 
        r = -ENOMEM;
        size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
-       entries = vmalloc(size);
+       entries = kmalloc(size, GFP_KERNEL);
        if (!entries)
                goto out;
 
@@ -1581,7 +1581,7 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
        r = n;
 
 out_free:
-       vfree(entries);
+       kfree(entries);
 out:
        return r;
 }
index 9344216183a433a84210b5ebaef0efd57e6aa9c7..a7547150a705235f75f7949f89ebd99a8e3ba329 100644 (file)
@@ -1216,17 +1216,20 @@ static int intel_i915_get_gtt_size(void)
 
                /* G33's GTT size defined in gmch_ctrl */
                pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
-               switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
-               case G33_PGETBL_SIZE_1M:
+               switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+               case I830_GMCH_GMS_STOLEN_512:
+                       size = 512;
+                       break;
+               case I830_GMCH_GMS_STOLEN_1024:
                        size = 1024;
                        break;
-               case G33_PGETBL_SIZE_2M:
-                       size = 2048;
+               case I830_GMCH_GMS_STOLEN_8192:
+                       size = 8*1024;
                        break;
                default:
                        dev_info(&agp_bridge->dev->dev,
                                 "unknown page table size 0x%x, assuming 512KB\n",
-                               (gmch_ctrl & G33_PGETBL_SIZE_MASK));
+                               (gmch_ctrl & I830_GMCH_GMS_MASK));
                        size = 512;
                }
        } else {
index 24314a9cffe83875858b4d2b4aeb0ab5a68acf21..1030f8420137adb8ff7363eb259f9578026fe178 100644 (file)
@@ -623,7 +623,14 @@ static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
 
 static int tpm_tis_pnp_resume(struct pnp_dev *dev)
 {
-       return tpm_pm_resume(&dev->dev);
+       struct tpm_chip *chip = pnp_get_drvdata(dev);
+       int ret;
+
+       ret = tpm_pm_resume(&dev->dev);
+       if (!ret)
+               tpm_continue_selftest(chip);
+
+       return ret;
 }
 
 static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
index cc9357da0e3442ad9666a415f80b3dd29321b6a0..e0187d16dd7c53fd240b58d62005e4c17df14bc4 100644 (file)
@@ -1300,7 +1300,7 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
                if (devno == 0)
                        return -ENODEV;
 
-               i7core_printk(KERN_ERR,
+               i7core_printk(KERN_INFO,
                        "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
                        dev_descr->dev, dev_descr->func,
                        PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
index aee83fa178f6a6dc60c7273eaaae29b43dbe000d..9214119c01540fb5244d3ca383adb1c5ee04722c 100644 (file)
@@ -605,6 +605,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
                case FBC_NOT_TILED:
                        seq_printf(m, "scanout buffer not tiled");
                        break;
+               case FBC_MULTIPLE_PIPES:
+                       seq_printf(m, "multiple pipes are enabled");
+                       break;
                default:
                        seq_printf(m, "unknown reason");
                }
index f00c5ae9556ccb47358ce1f5267dd9cc5cb17a21..2305a1234f1e5727cf835227ff2422ed930ce097 100644 (file)
@@ -1300,7 +1300,7 @@ static void i915_cleanup_compression(struct drm_device *dev)
        struct drm_i915_private *dev_priv = dev->dev_private;
 
        drm_mm_put_block(dev_priv->compressed_fb);
-       if (!IS_GM45(dev))
+       if (dev_priv->compressed_llb)
                drm_mm_put_block(dev_priv->compressed_llb);
 }
 
index d147ab2f5bfcabfc8bc82cd5ccdea93064fa4cf0..2e1744d37ad59e055f37f5c413c6ad3d6c56e02f 100644 (file)
@@ -215,6 +215,7 @@ enum no_fbc_reason {
        FBC_MODE_TOO_LARGE, /* mode too large for compression */
        FBC_BAD_PLANE, /* fbc not supported on plane */
        FBC_NOT_TILED, /* buffer not tiled */
+       FBC_MULTIPLE_PIPES, /* more than one pipe active */
 };
 
 enum intel_pch {
@@ -222,6 +223,8 @@ enum intel_pch {
        PCH_CPT,        /* Cougarpoint PCH */
 };
 
+#define QUIRK_PIPEA_FORCE (1<<0)
+
 struct intel_fbdev;
 
 typedef struct drm_i915_private {
@@ -337,6 +340,8 @@ typedef struct drm_i915_private {
        /* PCH chipset type */
        enum intel_pch pch_type;
 
+       unsigned long quirks;
+
        /* Register state */
        bool modeset_on_lid;
        u8 saveLBB;
index 51bd301cf10d9002555177d95b28e86703145d67..5aa747fc25a9b34161ead103fff6bdba37c092a8 100644 (file)
@@ -3647,6 +3647,7 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
        return ret;
 }
 
+
 int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                       struct drm_file *file_priv,
@@ -3794,7 +3795,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                                unsigned long long total_size = 0;
                                int num_fences = 0;
                                for (i = 0; i < args->buffer_count; i++) {
-                                       obj_priv = object_list[i]->driver_private;
+                                       obj_priv = to_intel_bo(object_list[i]);
 
                                        total_size += object_list[i]->size;
                                        num_fences +=
index 6d9b0288272a7e0c4f424bd66de1964af60e9a22..cf41c672defe9415fc0b656357cb44af00758b7d 100644 (file)
 
 #define PCH_PP_STATUS          0xc7200
 #define PCH_PP_CONTROL         0xc7204
+#define  PANEL_UNLOCK_REGS     (0xabcd << 16)
 #define  EDP_FORCE_VDD         (1 << 3)
 #define  EDP_BLC_ENABLE                (1 << 2)
 #define  PANEL_POWER_RESET     (1 << 1)
index 68dcf36e2793f51fa42aeecb9b67037aa8515205..5e21b31198249349dc5e69265dbe20c8b0a23d02 100644 (file)
@@ -862,8 +862,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        intel_clock_t clock;
        int max_n;
        bool found;
-       /* approximately equals target * 0.00488 */
-       int err_most = (target >> 8) + (target >> 10);
+       /* approximately equals target * 0.00585 */
+       int err_most = (target >> 8) + (target >> 9);
        found = false;
 
        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -1180,8 +1180,12 @@ static void intel_update_fbc(struct drm_crtc *crtc,
        struct drm_framebuffer *fb = crtc->fb;
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj_priv;
+       struct drm_crtc *tmp_crtc;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int plane = intel_crtc->plane;
+       int crtcs_enabled = 0;
+
+       DRM_DEBUG_KMS("\n");
 
        if (!i915_powersave)
                return;
@@ -1199,10 +1203,21 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         * If FBC is already on, we just have to verify that we can
         * keep it that way...
         * Need to disable if:
+        *   - more than one pipe is active
         *   - changing FBC params (stride, fence, mode)
         *   - new fb is too large to fit in compressed buffer
         *   - going to an unsupported config (interlace, pixel multiply, etc.)
         */
+       list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
+               if (tmp_crtc->enabled)
+                       crtcs_enabled++;
+       }
+       DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
+       if (crtcs_enabled > 1) {
+               DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
+               dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
+               goto out_disable;
+       }
        if (intel_fb->obj->size > dev_priv->cfb_size) {
                DRM_DEBUG_KMS("framebuffer too large, disabling "
                                "compression\n");
@@ -1255,7 +1270,7 @@ out_disable:
        }
 }
 
-static int
+int
 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
 {
        struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
@@ -2255,6 +2270,11 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                        intel_wait_for_vblank(dev);
                }
 
+               /* Don't disable pipe A or pipe A PLLs if needed */
+               if (pipeconf_reg == PIPEACONF &&
+                   (dev_priv->quirks & QUIRK_PIPEA_FORCE))
+                       goto skip_pipe_off;
+
                /* Next, disable display pipes */
                temp = I915_READ(pipeconf_reg);
                if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -2270,7 +2290,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                        I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
                        I915_READ(dpll_reg);
                }
-
+       skip_pipe_off:
                /* Wait for the clocks to turn off. */
                udelay(150);
                break;
@@ -2356,8 +2376,6 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
                if (mode->clock * 3 > 27000 * 4)
                        return MODE_CLOCK_HIGH;
        }
-
-       drm_mode_set_crtcinfo(adjusted_mode, 0);
        return true;
 }
 
@@ -3736,6 +3754,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                        if (dev_priv->lvds_dither) {
                                if (HAS_PCH_SPLIT(dev)) {
                                        pipeconf |= PIPE_ENABLE_DITHER;
+                                       pipeconf &= ~PIPE_DITHER_TYPE_MASK;
                                        pipeconf |= PIPE_DITHER_TYPE_ST01;
                                } else
                                        lvds |= LVDS_ENABLE_DITHER;
@@ -4412,7 +4431,8 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
                DRM_DEBUG_DRIVER("upclocking LVDS\n");
 
                /* Unlock panel regs */
-               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                          PANEL_UNLOCK_REGS);
 
                dpll &= ~DISPLAY_RATE_SELECT_FPA1;
                I915_WRITE(dpll_reg, dpll);
@@ -4455,7 +4475,8 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
                DRM_DEBUG_DRIVER("downclocking LVDS\n");
 
                /* Unlock panel regs */
-               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                          PANEL_UNLOCK_REGS);
 
                dpll |= DISPLAY_RATE_SELECT_FPA1;
                I915_WRITE(dpll_reg, dpll);
@@ -4695,7 +4716,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        struct drm_gem_object *obj;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_unpin_work *work;
-       unsigned long flags;
+       unsigned long flags, offset;
        int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
        int ret, pipesrc;
        u32 flip_mask;
@@ -4762,19 +4783,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                while (I915_READ(ISR) & flip_mask)
                        ;
 
+       /* Offset into the new buffer for cases of shared fbs between CRTCs */
+       offset = obj_priv->gtt_offset;
+       offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
+
        BEGIN_LP_RING(4);
        if (IS_I965G(dev)) {
                OUT_RING(MI_DISPLAY_FLIP |
                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                OUT_RING(fb->pitch);
-               OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+               OUT_RING(offset | obj_priv->tiling_mode);
                pipesrc = I915_READ(pipesrc_reg); 
                OUT_RING(pipesrc & 0x0fff0fff);
        } else {
                OUT_RING(MI_DISPLAY_FLIP_I915 |
                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                OUT_RING(fb->pitch);
-               OUT_RING(obj_priv->gtt_offset);
+               OUT_RING(offset);
                OUT_RING(MI_NOOP);
        }
        ADVANCE_LP_RING();
@@ -5506,6 +5531,66 @@ static void intel_init_display(struct drm_device *dev)
        }
 }
 
+/*
+ * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
+ * resume, or other times.  This quirk makes sure that's the case for
+ * affected systems.
+ */
+static void quirk_pipea_force (struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       dev_priv->quirks |= QUIRK_PIPEA_FORCE;
+       DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
+}
+
+struct intel_quirk {
+       int device;
+       int subsystem_vendor;
+       int subsystem_device;
+       void (*hook)(struct drm_device *dev);
+};
+
+struct intel_quirk intel_quirks[] = {
+       /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
+       { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
+       /* HP Mini needs pipe A force quirk (LP: #322104) */
+       { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
+
+       /* Thinkpad R31 needs pipe A force quirk */
+       { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
+       /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
+       { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
+
+       /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
+       { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
+       /* ThinkPad X40 needs pipe A force quirk */
+
+       /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
+       { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
+
+       /* 855 & before need to leave pipe A & dpll A up */
+       { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+       { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+};
+
+static void intel_init_quirks(struct drm_device *dev)
+{
+       struct pci_dev *d = dev->pdev;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
+               struct intel_quirk *q = &intel_quirks[i];
+
+               if (d->device == q->device &&
+                   (d->subsystem_vendor == q->subsystem_vendor ||
+                    q->subsystem_vendor == PCI_ANY_ID) &&
+                   (d->subsystem_device == q->subsystem_device ||
+                    q->subsystem_device == PCI_ANY_ID))
+                       q->hook(dev);
+       }
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5518,6 +5603,8 @@ void intel_modeset_init(struct drm_device *dev)
 
        dev->mode_config.funcs = (void *)&intel_mode_funcs;
 
+       intel_init_quirks(dev);
+
        intel_init_display(dev);
 
        if (IS_I965G(dev)) {
index 1aac59e83bff0c45a0da94e1f083d40d9e30b396..5d42661153116d7371672e6251b7ee06750c022c 100644 (file)
@@ -717,6 +717,51 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
        }
 }
 
+static void ironlake_edp_panel_on (struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+       u32 pp, pp_status;
+
+       pp_status = I915_READ(PCH_PP_STATUS);
+       if (pp_status & PP_ON)
+               return;
+
+       pp = I915_READ(PCH_PP_CONTROL);
+       pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
+       I915_WRITE(PCH_PP_CONTROL, pp);
+       do {
+               pp_status = I915_READ(PCH_PP_STATUS);
+       } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
+
+       if (time_after(jiffies, timeout))
+               DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
+
+       pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
+       I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
+static void ironlake_edp_panel_off (struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+       u32 pp, pp_status;
+
+       pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~POWER_TARGET_ON;
+       I915_WRITE(PCH_PP_CONTROL, pp);
+       do {
+               pp_status = I915_READ(PCH_PP_STATUS);
+       } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
+
+       if (time_after(jiffies, timeout))
+               DRM_DEBUG_KMS("panel off wait timed out\n");
+
+       /* Make sure VDD is enabled so DP AUX will work */
+       pp |= EDP_FORCE_VDD;
+       I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
 static void ironlake_edp_backlight_on (struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -751,14 +796,18 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
        if (mode != DRM_MODE_DPMS_ON) {
                if (dp_reg & DP_PORT_EN) {
                        intel_dp_link_down(intel_encoder, dp_priv->DP);
-                       if (IS_eDP(intel_encoder))
+                       if (IS_eDP(intel_encoder)) {
                                ironlake_edp_backlight_off(dev);
+                               ironlake_edp_backlight_off(dev);
+                       }
                }
        } else {
                if (!(dp_reg & DP_PORT_EN)) {
                        intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
-                       if (IS_eDP(intel_encoder))
+                       if (IS_eDP(intel_encoder)) {
+                               ironlake_edp_panel_on(dev);
                                ironlake_edp_backlight_on(dev);
+                       }
                }
        }
        dp_priv->dpms_mode = mode;
index 72206f37c4fb847c8d32d80c5c893fd3a68a5faa..2f7970be9051a2c5eb308b9a5a4eebc09e6b636c 100644 (file)
@@ -215,6 +215,9 @@ extern void intel_init_clock_gating(struct drm_device *dev);
 extern void ironlake_enable_drps(struct drm_device *dev);
 extern void ironlake_disable_drps(struct drm_device *dev);
 
+extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
+                                     struct drm_gem_object *obj);
+
 extern int intel_framebuffer_init(struct drm_device *dev,
                                  struct intel_framebuffer *ifb,
                                  struct drm_mode_fb_cmd *mode_cmd,
index c3c505244e07367c3a8a3cb17698d60ef5ce5407..3e18c9e7729b6a475ce270d3329acf3d54288f1c 100644 (file)
@@ -98,7 +98,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
 
        mutex_lock(&dev->struct_mutex);
 
-       ret = i915_gem_object_pin(fbo, 64*1024);
+       ret = intel_pin_and_fence_fb_obj(dev, fbo);
        if (ret) {
                DRM_ERROR("failed to pin fb: %d\n", ret);
                goto out_unref;
@@ -236,7 +236,7 @@ int intel_fbdev_destroy(struct drm_device *dev,
 
        drm_framebuffer_cleanup(&ifb->base);
        if (ifb->obj)
-               drm_gem_object_unreference_unlocked(ifb->obj);
+               drm_gem_object_unreference(ifb->obj);
 
        return 0;
 }
index 31df55f0a0a7950a0e59ebce556fc30cde35b891..0eab8df5bf7e1c679b52752311e665e51d3ab21d 100644 (file)
@@ -599,6 +599,26 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
        return 0;
 }
 
+static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
+{
+       DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
+       return 1;
+}
+
+/* The GPU hangs up on these systems if modeset is performed on LID open */
+static const struct dmi_system_id intel_no_modeset_on_lid[] = {
+       {
+               .callback = intel_no_modeset_on_lid_dmi_callback,
+               .ident = "Toshiba Tecra A11",
+               .matches = {
+                       DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                       DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
+               },
+       },
+
+       { }     /* terminating entry */
+};
+
 /*
  * Lid events. Note the use of 'modeset_on_lid':
  *  - we set it on lid close, and reset it on open
@@ -622,6 +642,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
         */
        if (connector)
                connector->status = connector->funcs->detect(connector);
+       /* Don't force modeset on machines where it causes a GPU lockup */
+       if (dmi_check_system(intel_no_modeset_on_lid))
+               return NOTIFY_OK;
        if (!acpi_lid_open()) {
                dev_priv->modeset_on_lid = 1;
                return NOTIFY_OK;
index df4532e91b1a0da9627a7fc5916c2438a5829af1..f370476d5417d49b48540e49432c5f82b97cf53c 100644 (file)
@@ -178,7 +178,6 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                               unsigned long val,
                               struct cpufreq_freqs *freqs)
 {
-#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
        switch (val) {
        case CPUFREQ_PRECHANGE:
                if (freqs->new > freqs->old) {
@@ -186,7 +185,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                               "pre-updating\n",
                               freqs->new / 1000, (freqs->new / 100) % 10,
                               freqs->old / 1000, (freqs->old / 100) % 10);
-                       pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+                       pxa2xx_pcmcia_set_timing(skt);
                }
                break;
 
@@ -196,7 +195,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                               "post-updating\n",
                               freqs->new / 1000, (freqs->new / 100) % 10,
                               freqs->old / 1000, (freqs->old / 100) % 10);
-                       pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+                       pxa2xx_pcmcia_set_timing(skt);
                }
                break;
        }
index eed3c2d8dd1ce010e13e143213b292e1f0ec1569..a182def7007d2c678b1712b9f7ca78fdc80042ca 100644 (file)
@@ -41,6 +41,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/io.h>
+#include <asm/ioctls.h>
 
 #include <asm/mach/serial_at91.h>
 #include <mach/board.h>
index 85b0d8921eae4fbfe14c86c1ac7bf1f9ffae3705..980762453a9c293d6bdda38bdc54317c55a3433c 100644 (file)
@@ -2561,7 +2561,7 @@ static void pxa_udc_shutdown(struct platform_device *_dev)
                udc_disable(udc);
 }
 
-#ifdef CONFIG_CPU_PXA27x
+#ifdef CONFIG_PXA27x
 extern void pxa27x_clear_otgph(void);
 #else
 #define pxa27x_clear_otgph()   do {} while (0)
index a18debdd79b8cec346f7f625baf66a47800affd1..418163894775e36ff129aa96ba107f7e6145ca20 100644 (file)
@@ -203,7 +203,7 @@ static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
        __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
 }
 
-#ifdef CONFIG_CPU_PXA27x
+#ifdef CONFIG_PXA27x
 extern void pxa27x_clear_otgph(void);
 #else
 #define pxa27x_clear_otgph()   do {} while (0)