Merge tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel...
authorDave Airlie <airlied@redhat.com>
Tue, 25 Oct 2016 06:36:13 +0000 (16:36 +1000)
committerDave Airlie <airlied@redhat.com>
Tue, 25 Oct 2016 06:39:43 +0000 (16:39 +1000)
- first slice of the gvt device model (Zhenyu et al)
- compression support for gpu error states (Chris)
- sunset clause on gpu errors resulting in dmesg noise telling users
  how to report them
- .rodata diet from Tvrtko
- switch over lots of macros to only take dev_priv (Tvrtko)
- underrun suppression for dp link training (Ville)
- lspcon (hmdi 2.0 on skl/bxt) support from Shashank Sharma, polish
  from Jani
- gen9 wm fixes from Paulo&Lyude
- updated ddi programming for kbl (Rodrigo)
- respect alternate aux/ddc pins (from vbt) for all ddi ports (Ville)

* tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel: (227 commits)
  drm/i915: Update DRIVER_DATE to 20161024
  drm/i915: Stop setting SNB min-freq-table 0 on powersave setup
  drm/i915/dp: add lane_count check in intel_dp_check_link_status
  drm/i915: Fix whitespace issues
  drm/i915: Clean up DDI DDC/AUX CH sanitation
  drm/i915: Respect alternate_ddc_pin for all DDI ports
  drm/i915: Respect alternate_aux_channel for all DDI ports
  drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7
  drm/i915: KBL - Recommended buffer translation programming for DisplayPort
  drm/i915: Move down skl/kbl ddi iboost and n_edp_entires fixup
  drm/i915: Add a sunset clause to GPU hang logging
  drm/i915: Stop reporting error details in dmesg as well as the error-state
  drm/i915/gvt: do not ignore return value of create_scratch_page
  drm/i915/gvt: fix spare warnings on odd constant _Bool cast
  drm/i915/gvt: mark symbols static where possible
  drm/i915/gvt: fix sparse warnings on different address spaces
  drm/i915/gvt: properly access enabled intel_engine_cs
  drm/i915/gvt: Remove defunct vmap_batch()
  drm/i915/gvt: Use common mapping routines for shadow_bb object
  drm/i915/gvt: Use common mapping routines for indirect_ctx object
  ...

109 files changed:
Documentation/gpu/i915.rst
MAINTAINERS
drivers/gpu/drm/drm_dp_dual_mode_helper.c
drivers/gpu/drm/i915/Kconfig
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/gvt/Makefile
drivers/gpu/drm/i915/gvt/aperture_gm.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/cfg_space.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/cmd_parser.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/cmd_parser.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/debug.h
drivers/gpu/drm/i915/gvt/display.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/display.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/edid.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/edid.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/execlist.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/execlist.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/firmware.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/gtt.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/gtt.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/gvt.c
drivers/gpu/drm/i915/gvt/gvt.h
drivers/gpu/drm/i915/gvt/handlers.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/hypercall.h
drivers/gpu/drm/i915/gvt/interrupt.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/interrupt.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/mmio.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/mmio.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/mpt.h
drivers/gpu/drm/i915/gvt/opregion.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/reg.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/render.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/render.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/sched_policy.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/sched_policy.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/scheduler.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/scheduler.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/trace.h [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/trace_points.c [new file with mode: 0644]
drivers/gpu/drm/i915/gvt/vgpu.c [new file with mode: 0644]
drivers/gpu/drm/i915/i915_cmd_parser.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_context.c
drivers/gpu/drm/i915/i915_gem_evict.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_gem_fence.c
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_gem_gtt.h
drivers/gpu/drm/i915/i915_gem_render_state.c
drivers/gpu/drm/i915/i915_gem_request.c
drivers/gpu/drm/i915/i915_gem_shrinker.c
drivers/gpu/drm/i915/i915_gem_stolen.c
drivers/gpu/drm/i915/i915_gem_tiling.c
drivers/gpu/drm/i915/i915_gpu_error.c
drivers/gpu/drm/i915/i915_guc_submission.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_params.c
drivers/gpu/drm/i915/i915_params.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/i915_sysfs.c
drivers/gpu/drm/i915/intel_audio.c
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_breadcrumbs.c
drivers/gpu/drm/i915/intel_color.c
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_dp_link_training.c
drivers/gpu/drm/i915/intel_dp_mst.c
drivers/gpu/drm/i915/intel_dpll_mgr.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_dsi.c
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
drivers/gpu/drm/i915/intel_dsi_pll.c
drivers/gpu/drm/i915/intel_dvo.c
drivers/gpu/drm/i915/intel_engine_cs.c
drivers/gpu/drm/i915/intel_fbc.c
drivers/gpu/drm/i915/intel_fifo_underrun.c
drivers/gpu/drm/i915/intel_guc_loader.c
drivers/gpu/drm/i915/intel_gvt.c
drivers/gpu/drm/i915/intel_gvt.h
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_i2c.c
drivers/gpu/drm/i915/intel_lrc.c
drivers/gpu/drm/i915/intel_lspcon.c [new file with mode: 0644]
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_overlay.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_psr.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h
drivers/gpu/drm/i915/intel_runtime_pm.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_sprite.c
drivers/gpu/drm/i915/intel_tv.c
drivers/gpu/drm/i915/intel_uncore.c
include/drm/drm_dp_dual_mode_helper.h
include/drm/i915_component.h
include/sound/hda_i915.h
sound/hda/hdac_i915.c
sound/pci/hda/patch_hdmi.c
sound/soc/codecs/hdac_hdmi.c

index 87aaffc22920288ebbe3e6db17f2848843416b33..95ce77ff4342321f95a594397bf13287c85161e3 100644 (file)
@@ -49,6 +49,15 @@ Intel GVT-g Guest Support(vGPU)
 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
    :internal:
 
+Intel GVT-g Host Support(vGPU device model)
+-------------------------------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
+   :doc: Intel GVT-g host support
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
+   :internal:
+
 Display Hardware Handling
 =========================
 
index c4479530634288d1fa2803d1c46b7c233a27facf..e60e0a18822962d8b3eb69af47512bde0e7181d4 100644 (file)
@@ -4064,6 +4064,16 @@ F:       include/drm/i915*
 F:     include/uapi/drm/i915_drm.h
 F:     Documentation/gpu/i915.rst
 
+INTEL GVT-g DRIVERS (Intel GPU Virtualization)
+M:      Zhenyu Wang <zhenyuw@linux.intel.com>
+M:      Zhi Wang <zhi.a.wang@intel.com>
+L:      igvt-g-dev@lists.01.org
+L:      intel-gfx@lists.freedesktop.org
+W:      https://01.org/igvt-g
+T:      git https://github.com/01org/gvt-linux.git
+S:      Supported
+F:      drivers/gpu/drm/i915/gvt/
+
 DRM DRIVERS FOR ATMEL HLCDC
 M:     Boris Brezillon <boris.brezillon@free-electrons.com>
 L:     dri-devel@lists.freedesktop.org
index a7b2a751f6fe77ac1409c4d92b55fd475db7c09a..488355bdafb99d417a898c65bd06b662df0cf5d7 100644 (file)
@@ -148,6 +148,14 @@ static bool is_type2_adaptor(uint8_t adaptor_id)
                              DP_DUAL_MODE_REV_TYPE2);
 }
 
+static bool is_lspcon_adaptor(const char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN],
+                             const uint8_t adaptor_id)
+{
+       return is_hdmi_adaptor(hdmi_id) &&
+               (adaptor_id == (DP_DUAL_MODE_TYPE_TYPE2 |
+                DP_DUAL_MODE_TYPE_HAS_DPCD));
+}
+
 /**
  * drm_dp_dual_mode_detect - Identify the DP dual mode adaptor
  * @adapter: I2C adapter for the DDC bus
@@ -203,6 +211,8 @@ enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(struct i2c_adapter *adapter)
        ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_ADAPTOR_ID,
                                    &adaptor_id, sizeof(adaptor_id));
        if (ret == 0) {
+               if (is_lspcon_adaptor(hdmi_id, adaptor_id))
+                       return DRM_DP_DUAL_MODE_LSPCON;
                if (is_type2_adaptor(adaptor_id)) {
                        if (is_hdmi_adaptor(hdmi_id))
                                return DRM_DP_DUAL_MODE_TYPE2_HDMI;
@@ -364,3 +374,96 @@ const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type)
        }
 }
 EXPORT_SYMBOL(drm_dp_get_dual_mode_type_name);
+
+/**
+ * drm_lspcon_get_mode: Get LSPCON's current mode of operation by
+ * reading offset (0x80, 0x41)
+ * @adapter: I2C-over-aux adapter
+ * @mode: current lspcon mode of operation output variable
+ *
+ * Returns:
+ * 0 on success, sets the current_mode value to appropriate mode
+ * -error on failure
+ */
+int drm_lspcon_get_mode(struct i2c_adapter *adapter,
+                       enum drm_lspcon_mode *mode)
+{
+       u8 data;
+       int ret = 0;
+
+       if (!mode) {
+               DRM_ERROR("NULL input\n");
+               return -EINVAL;
+       }
+
+       /* Read Status: i2c over aux */
+       ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_LSPCON_CURRENT_MODE,
+                                   &data, sizeof(data));
+       if (ret < 0) {
+               DRM_ERROR("LSPCON read(0x80, 0x41) failed\n");
+               return -EFAULT;
+       }
+
+       if (data & DP_DUAL_MODE_LSPCON_MODE_PCON)
+               *mode = DRM_LSPCON_MODE_PCON;
+       else
+               *mode = DRM_LSPCON_MODE_LS;
+       return 0;
+}
+EXPORT_SYMBOL(drm_lspcon_get_mode);
+
+/**
+ * drm_lspcon_set_mode: Change LSPCON's mode of operation by
+ * writing offset (0x80, 0x40)
+ * @adapter: I2C-over-aux adapter
+ * @mode: required mode of operation
+ *
+ * Returns:
+ * 0 on success, -error on failure/timeout
+ */
+int drm_lspcon_set_mode(struct i2c_adapter *adapter,
+                       enum drm_lspcon_mode mode)
+{
+       u8 data = 0;
+       int ret;
+       int time_out = 200;
+       enum drm_lspcon_mode current_mode;
+
+       if (mode == DRM_LSPCON_MODE_PCON)
+               data = DP_DUAL_MODE_LSPCON_MODE_PCON;
+
+       /* Change mode */
+       ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_LSPCON_MODE_CHANGE,
+                                    &data, sizeof(data));
+       if (ret < 0) {
+               DRM_ERROR("LSPCON mode change failed\n");
+               return ret;
+       }
+
+       /*
+        * Confirm mode change by reading the status bit.
+        * Sometimes, it takes a while to change the mode,
+        * so wait and retry until time out or done.
+        */
+       do {
+               ret = drm_lspcon_get_mode(adapter, &current_mode);
+               if (ret) {
+                       DRM_ERROR("can't confirm LSPCON mode change\n");
+                       return ret;
+               } else {
+                       if (current_mode != mode) {
+                               msleep(10);
+                               time_out -= 10;
+                       } else {
+                               DRM_DEBUG_KMS("LSPCON mode changed to %s\n",
+                                               mode == DRM_LSPCON_MODE_LS ?
+                                               "LS" : "PCON");
+                               return 0;
+                       }
+               }
+       } while (time_out);
+
+       DRM_ERROR("LSPCON mode change timed out\n");
+       return -ETIMEDOUT;
+}
+EXPORT_SYMBOL(drm_lspcon_set_mode);
index 7769e469118f2084f4ee84b70f7aa049cd07239c..1c1b19ccb92f38490b892116911eeff004870e35 100644 (file)
@@ -46,6 +46,31 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT
 
          If in doubt, say "N".
 
+config DRM_I915_CAPTURE_ERROR
+       bool "Enable capturing GPU state following a hang"
+       depends on DRM_I915
+       default y
+       help
+         This option enables capturing the GPU state when a hang is detected.
+         This information is vital for triaging hangs and assists in debugging.
+         Please report any hang to
+            https://bugs.freedesktop.org/enter_bug.cgi?product=DRI
+         for triaging.
+
+         If in doubt, say "Y".
+
+config DRM_I915_COMPRESS_ERROR
+       bool "Compress GPU error state"
+       depends on DRM_I915_CAPTURE_ERROR
+       select ZLIB_DEFLATE
+       default y
+       help
+         This option selects ZLIB_DEFLATE if it isn't already
+         selected and causes any error state captured upon a GPU hang
+         to be compressed using zlib.
+
+         If in doubt, say "Y".
+
 config DRM_I915_USERPTR
        bool "Always enable userptr support"
        depends on DRM_I915
index a998c2bce70a0a6c72ac1bb1671b4ebd311e6c40..612340097f4ba2f083076b4ca3c06694b11835f1 100644 (file)
@@ -42,7 +42,6 @@ i915-y += i915_cmd_parser.o \
          i915_gem_stolen.o \
          i915_gem_tiling.o \
          i915_gem_userptr.o \
-         i915_gpu_error.o \
          i915_trace_points.o \
          intel_breadcrumbs.o \
          intel_engine_cs.o \
@@ -102,11 +101,15 @@ i915-y += dvo_ch7017.o \
          intel_dvo.o \
          intel_hdmi.o \
          intel_i2c.o \
+         intel_lspcon.o \
          intel_lvds.o \
          intel_panel.o \
          intel_sdvo.o \
          intel_tv.o
 
+# Post-mortem debug and GPU hang state capture
+i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
+
 # virtual gpu code
 i915-y += i915_vgpu.o
 
index d0f21a6ad60d54608fd7f84b54969be998366d35..34ea4776af70a403532ffbbecabcc2c90740a77a 100644 (file)
@@ -1,5 +1,7 @@
 GVT_DIR := gvt
-GVT_SOURCE := gvt.o
+GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
+       interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
+       execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
 
 ccflags-y                      += -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y                        += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
new file mode 100644 (file)
index 0000000..0d41ebc
--- /dev/null
@@ -0,0 +1,352 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Kevin Tian <kevin.tian@intel.com>
+ *    Dexuan Cui
+ *
+ * Contributors:
+ *    Pei Zhang <pei.zhang@intel.com>
+ *    Min He <min.he@intel.com>
+ *    Niu Bing <bing.niu@intel.com>
+ *    Yulei Zhang <yulei.zhang@intel.com>
+ *    Zhenyu Wang <zhenyuw@linux.intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define MB_TO_BYTES(mb) ((mb) << 20ULL)
+#define BYTES_TO_MB(b) ((b) >> 20ULL)
+
+#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
+#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
+#define HOST_FENCE 4
+
+static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       u32 alloc_flag, search_flag;
+       u64 start, end, size;
+       struct drm_mm_node *node;
+       int retried = 0;
+       int ret;
+
+       if (high_gm) {
+               search_flag = DRM_MM_SEARCH_BELOW;
+               alloc_flag = DRM_MM_CREATE_TOP;
+               node = &vgpu->gm.high_gm_node;
+               size = vgpu_hidden_sz(vgpu);
+               start = gvt_hidden_gmadr_base(gvt);
+               end = gvt_hidden_gmadr_end(gvt);
+       } else {
+               search_flag = DRM_MM_SEARCH_DEFAULT;
+               alloc_flag = DRM_MM_CREATE_DEFAULT;
+               node = &vgpu->gm.low_gm_node;
+               size = vgpu_aperture_sz(vgpu);
+               start = gvt_aperture_gmadr_base(gvt);
+               end = gvt_aperture_gmadr_end(gvt);
+       }
+
+       mutex_lock(&dev_priv->drm.struct_mutex);
+search_again:
+       ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm,
+                                                 node, size, 4096, 0,
+                                                 start, end, search_flag,
+                                                 alloc_flag);
+       if (ret) {
+               ret = i915_gem_evict_something(&dev_priv->ggtt.base,
+                                              size, 4096, 0, start, end, 0);
+               if (ret == 0 && ++retried < 3)
+                       goto search_again;
+
+               gvt_err("fail to alloc %s gm space from host, retried %d\n",
+                               high_gm ? "high" : "low", retried);
+       }
+       mutex_unlock(&dev_priv->drm.struct_mutex);
+       return ret;
+}
+
+static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       int ret;
+
+       ret = alloc_gm(vgpu, false);
+       if (ret)
+               return ret;
+
+       ret = alloc_gm(vgpu, true);
+       if (ret)
+               goto out_free_aperture;
+
+       gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
+                    vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
+
+       gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
+                    vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
+
+       return 0;
+out_free_aperture:
+       mutex_lock(&dev_priv->drm.struct_mutex);
+       drm_mm_remove_node(&vgpu->gm.low_gm_node);
+       mutex_unlock(&dev_priv->drm.struct_mutex);
+       return ret;
+}
+
+static void free_vgpu_gm(struct intel_vgpu *vgpu)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+       mutex_lock(&dev_priv->drm.struct_mutex);
+       drm_mm_remove_node(&vgpu->gm.low_gm_node);
+       drm_mm_remove_node(&vgpu->gm.high_gm_node);
+       mutex_unlock(&dev_priv->drm.struct_mutex);
+}
+
+/**
+ * intel_vgpu_write_fence - write fence registers owned by a vGPU
+ * @vgpu: vGPU instance
+ * @fence: vGPU fence register number
+ * @value: Fence register value to be written
+ *
+ * This function is used to write fence registers owned by a vGPU. The vGPU
+ * fence register number will be translated into HW fence register number.
+ *
+ */
+void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
+               u32 fence, u64 value)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       struct drm_i915_fence_reg *reg;
+       i915_reg_t fence_reg_lo, fence_reg_hi;
+
+       assert_rpm_wakelock_held(dev_priv);
+
+       if (WARN_ON(fence > vgpu_fence_sz(vgpu)))
+               return;
+
+       reg = vgpu->fence.regs[fence];
+       if (WARN_ON(!reg))
+               return;
+
+       fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
+       fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
+
+       I915_WRITE(fence_reg_lo, 0);
+       POSTING_READ(fence_reg_lo);
+
+       I915_WRITE(fence_reg_hi, upper_32_bits(value));
+       I915_WRITE(fence_reg_lo, lower_32_bits(value));
+       POSTING_READ(fence_reg_lo);
+}
+
+static void free_vgpu_fence(struct intel_vgpu *vgpu)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       struct drm_i915_fence_reg *reg;
+       u32 i;
+
+       if (WARN_ON(!vgpu_fence_sz(vgpu)))
+               return;
+
+       intel_runtime_pm_get(dev_priv);
+
+       mutex_lock(&dev_priv->drm.struct_mutex);
+       for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
+               reg = vgpu->fence.regs[i];
+               intel_vgpu_write_fence(vgpu, i, 0);
+               list_add_tail(&reg->link,
+                             &dev_priv->mm.fence_list);
+       }
+       mutex_unlock(&dev_priv->drm.struct_mutex);
+
+       intel_runtime_pm_put(dev_priv);
+}
+
+static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       struct drm_i915_fence_reg *reg;
+       int i;
+       struct list_head *pos, *q;
+
+       intel_runtime_pm_get(dev_priv);
+
+       /* Request fences from host */
+       mutex_lock(&dev_priv->drm.struct_mutex);
+       i = 0;
+       list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
+               reg = list_entry(pos, struct drm_i915_fence_reg, link);
+               if (reg->pin_count || reg->vma)
+                       continue;
+               list_del(pos);
+               vgpu->fence.regs[i] = reg;
+               intel_vgpu_write_fence(vgpu, i, 0);
+               if (++i == vgpu_fence_sz(vgpu))
+                       break;
+       }
+       if (i != vgpu_fence_sz(vgpu))
+               goto out_free_fence;
+
+       mutex_unlock(&dev_priv->drm.struct_mutex);
+       intel_runtime_pm_put(dev_priv);
+       return 0;
+out_free_fence:
+       /* Return fences to host, if fail */
+       for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
+               reg = vgpu->fence.regs[i];
+               if (!reg)
+                       continue;
+               list_add_tail(&reg->link,
+                             &dev_priv->mm.fence_list);
+       }
+       mutex_unlock(&dev_priv->drm.struct_mutex);
+       intel_runtime_pm_put(dev_priv);
+       return -ENOSPC;
+}
+
+static void free_resource(struct intel_vgpu *vgpu)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+
+       gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
+       gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
+       gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
+}
+
+static int alloc_resource(struct intel_vgpu *vgpu,
+               struct intel_vgpu_creation_params *param)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       unsigned long request, avail, max, taken;
+       const char *item;
+
+       if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {
+               gvt_err("Invalid vGPU creation params\n");
+               return -EINVAL;
+       }
+
+       item = "low GM space";
+       max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
+       taken = gvt->gm.vgpu_allocated_low_gm_size;
+       avail = max - taken;
+       request = MB_TO_BYTES(param->low_gm_sz);
+
+       if (request > avail)
+               goto no_enough_resource;
+
+       vgpu_aperture_sz(vgpu) = request;
+
+       item = "high GM space";
+       max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
+       taken = gvt->gm.vgpu_allocated_high_gm_size;
+       avail = max - taken;
+       request = MB_TO_BYTES(param->high_gm_sz);
+
+       if (request > avail)
+               goto no_enough_resource;
+
+       vgpu_hidden_sz(vgpu) = request;
+
+       item = "fence";
+       max = gvt_fence_sz(gvt) - HOST_FENCE;
+       taken = gvt->fence.vgpu_allocated_fence_num;
+       avail = max - taken;
+       request = param->fence_sz;
+
+       if (request > avail)
+               goto no_enough_resource;
+
+       vgpu_fence_sz(vgpu) = request;
+
+       gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);
+       gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);
+       gvt->fence.vgpu_allocated_fence_num += param->fence_sz;
+       return 0;
+
+no_enough_resource:
+       gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item);
+       gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n",
+               vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail),
+               BYTES_TO_MB(max), BYTES_TO_MB(taken));
+       return -ENOSPC;
+}
+
+/**
+ * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
+ * @vgpu: a vGPU
+ *
+ * This function is used to free the HW resource owned by a vGPU.
+ *
+ */
+void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
+{
+       free_vgpu_gm(vgpu);
+       free_vgpu_fence(vgpu);
+       free_resource(vgpu);
+}
+
+/**
+ * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
+ * @vgpu: vGPU
+ * @param: vGPU creation params
+ *
+ * This function is used to allocate HW resource for a vGPU. User specifies
+ * the resource configuration through the creation params.
+ *
+ * Returns:
+ * zero on success, negative error code if failed.
+ *
+ */
+int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
+               struct intel_vgpu_creation_params *param)
+{
+       int ret;
+
+       ret = alloc_resource(vgpu, param);
+       if (ret)
+               return ret;
+
+       ret = alloc_vgpu_gm(vgpu);
+       if (ret)
+               goto out_free_resource;
+
+       ret = alloc_vgpu_fence(vgpu);
+       if (ret)
+               goto out_free_vgpu_gm;
+
+       return 0;
+
+out_free_vgpu_gm:
+       free_vgpu_gm(vgpu);
+out_free_resource:
+       free_resource(vgpu);
+       return ret;
+}
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
new file mode 100644 (file)
index 0000000..4c68774
--- /dev/null
@@ -0,0 +1,288 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Eddie Dong <eddie.dong@intel.com>
+ *    Jike Song <jike.song@intel.com>
+ *
+ * Contributors:
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *    Min He <min.he@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+enum {
+       INTEL_GVT_PCI_BAR_GTTMMIO = 0,
+       INTEL_GVT_PCI_BAR_APERTURE,
+       INTEL_GVT_PCI_BAR_PIO,
+       INTEL_GVT_PCI_BAR_MAX,
+};
+
+/**
+ * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset,
+       void *p_data, unsigned int bytes)
+{
+       struct intel_vgpu *vgpu = __vgpu;
+
+       if (WARN_ON(bytes > 4))
+               return -EINVAL;
+
+       if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
+               return -EINVAL;
+
+       memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
+       return 0;
+}
+
+static int map_aperture(struct intel_vgpu *vgpu, bool map)
+{
+       u64 first_gfn, first_mfn;
+       u64 val;
+       int ret;
+
+       if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
+               return 0;
+
+       val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
+       if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
+               val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
+       else
+               val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
+
+       first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;
+       first_mfn = vgpu_aperture_pa_base(vgpu) >> PAGE_SHIFT;
+
+       ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,
+                                                 first_mfn,
+                                                 vgpu_aperture_sz(vgpu)
+                                                 >> PAGE_SHIFT, map,
+                                                 GVT_MAP_APERTURE);
+       if (ret)
+               return ret;
+
+       vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
+       return 0;
+}
+
+static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
+{
+       u64 start, end;
+       u64 val;
+       int ret;
+
+       if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
+               return 0;
+
+       val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];
+       if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
+               start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
+       else
+               start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
+
+       start &= ~GENMASK(3, 0);
+       end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1;
+
+       ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap);
+       if (ret)
+               return ret;
+
+       vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
+       return 0;
+}
+
+static int emulate_pci_command_write(struct intel_vgpu *vgpu,
+       unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u8 old = vgpu_cfg_space(vgpu)[offset];
+       u8 new = *(u8 *)p_data;
+       u8 changed = old ^ new;
+       int ret;
+
+       if (!(changed & PCI_COMMAND_MEMORY))
+               return 0;
+
+       if (old & PCI_COMMAND_MEMORY) {
+               ret = trap_gttmmio(vgpu, false);
+               if (ret)
+                       return ret;
+               ret = map_aperture(vgpu, false);
+               if (ret)
+                       return ret;
+       } else {
+               ret = trap_gttmmio(vgpu, true);
+               if (ret)
+                       return ret;
+               ret = map_aperture(vgpu, true);
+               if (ret)
+                       return ret;
+       }
+
+       memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);
+       return 0;
+}
+
+static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
+       void *p_data, unsigned int bytes)
+{
+       unsigned int bar_index =
+               (rounddown(offset, 8) % PCI_BASE_ADDRESS_0) / 8;
+       u32 new = *(u32 *)(p_data);
+       bool lo = IS_ALIGNED(offset, 8);
+       u64 size;
+       int ret = 0;
+       bool mmio_enabled =
+               vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
+
+       if (WARN_ON(bar_index >= INTEL_GVT_PCI_BAR_MAX))
+               return -EINVAL;
+
+       if (new == 0xffffffff) {
+               /*
+                * Power-up software can determine how much address
+                * space the device requires by writing a value of
+                * all 1's to the register and then reading the value
+                * back. The device will return 0's in all don't-care
+                * address bits.
+                */
+               size = vgpu->cfg_space.bar[bar_index].size;
+               if (lo) {
+                       new = rounddown(new, size);
+               } else {
+                       u32 val = vgpu_cfg_space(vgpu)[rounddown(offset, 8)];
+                       /* for 32bit mode bar it returns all-0 in upper 32
+                        * bit, for 64bit mode bar it will calculate the
+                        * size with lower 32bit and return the corresponding
+                        * value
+                        */
+                       if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
+                               new &= (~(size-1)) >> 32;
+                       else
+                               new = 0;
+               }
+               /*
+                * Unmapp & untrap the BAR, since guest hasn't configured a
+                * valid GPA
+                */
+               switch (bar_index) {
+               case INTEL_GVT_PCI_BAR_GTTMMIO:
+                       ret = trap_gttmmio(vgpu, false);
+                       break;
+               case INTEL_GVT_PCI_BAR_APERTURE:
+                       ret = map_aperture(vgpu, false);
+                       break;
+               }
+               intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
+       } else {
+               /*
+                * Unmapp & untrap the old BAR first, since guest has
+                * re-configured the BAR
+                */
+               switch (bar_index) {
+               case INTEL_GVT_PCI_BAR_GTTMMIO:
+                       ret = trap_gttmmio(vgpu, false);
+                       break;
+               case INTEL_GVT_PCI_BAR_APERTURE:
+                       ret = map_aperture(vgpu, false);
+                       break;
+               }
+               intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
+               /* Track the new BAR */
+               if (mmio_enabled) {
+                       switch (bar_index) {
+                       case INTEL_GVT_PCI_BAR_GTTMMIO:
+                               ret = trap_gttmmio(vgpu, true);
+                               break;
+                       case INTEL_GVT_PCI_BAR_APERTURE:
+                               ret = map_aperture(vgpu, true);
+                               break;
+                       }
+               }
+       }
+       return ret;
+}
+
+/**
+ * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset,
+       void *p_data, unsigned int bytes)
+{
+       struct intel_vgpu *vgpu = __vgpu;
+       int ret;
+
+       if (WARN_ON(bytes > 4))
+               return -EINVAL;
+
+       if (WARN_ON(offset + bytes >= INTEL_GVT_MAX_CFG_SPACE_SZ))
+               return -EINVAL;
+
+       /* First check if it's PCI_COMMAND */
+       if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
+               if (WARN_ON(bytes > 2))
+                       return -EINVAL;
+               return emulate_pci_command_write(vgpu, offset, p_data, bytes);
+       }
+
+       switch (rounddown(offset, 4)) {
+       case PCI_BASE_ADDRESS_0:
+       case PCI_BASE_ADDRESS_1:
+       case PCI_BASE_ADDRESS_2:
+       case PCI_BASE_ADDRESS_3:
+               if (WARN_ON(!IS_ALIGNED(offset, 4)))
+                       return -EINVAL;
+               return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
+
+       case INTEL_GVT_PCI_SWSCI:
+               if (WARN_ON(!IS_ALIGNED(offset, 4)))
+                       return -EINVAL;
+               ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
+               if (ret)
+                       return ret;
+               break;
+
+       case INTEL_GVT_PCI_OPREGION:
+               if (WARN_ON(!IS_ALIGNED(offset, 4)))
+                       return -EINVAL;
+               ret = intel_vgpu_init_opregion(vgpu, *(u32 *)p_data);
+               if (ret)
+                       return ret;
+
+               memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);
+               break;
+       default:
+               memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);
+               break;
+       }
+       return 0;
+}
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
new file mode 100644 (file)
index 0000000..aafb57e
--- /dev/null
@@ -0,0 +1,2831 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Ke Yu
+ *    Kevin Tian <kevin.tian@intel.com>
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *
+ * Contributors:
+ *    Min He <min.he@intel.com>
+ *    Ping Gao <ping.a.gao@intel.com>
+ *    Tina Zhang <tina.zhang@intel.com>
+ *    Yulei Zhang <yulei.zhang@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+
+#include <linux/slab.h>
+#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
+#include "trace.h"
+
+#define INVALID_OP    (~0U)
+
+#define OP_LEN_MI           9
+#define OP_LEN_2D           10
+#define OP_LEN_3D_MEDIA     16
+#define OP_LEN_MFX_VC       16
+#define OP_LEN_VEBOX       16
+
+#define CMD_TYPE(cmd)  (((cmd) >> 29) & 7)
+
+struct sub_op_bits {
+       int hi;
+       int low;
+};
+struct decode_info {
+       char *name;
+       int op_len;
+       int nr_sub_op;
+       struct sub_op_bits *sub_op;
+};
+
+#define   MAX_CMD_BUDGET                       0x7fffffff
+#define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
+#define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
+#define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
+
+#define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
+#define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
+#define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
+
+/* Render Command Map */
+
+/* MI_* command Opcode (28:23) */
+#define OP_MI_NOOP                          0x0
+#define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
+#define OP_MI_USER_INTERRUPT                0x2
+#define OP_MI_WAIT_FOR_EVENT                0x3
+#define OP_MI_FLUSH                         0x4
+#define OP_MI_ARB_CHECK                     0x5
+#define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
+#define OP_MI_REPORT_HEAD                   0x7
+#define OP_MI_ARB_ON_OFF                    0x8
+#define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
+#define OP_MI_BATCH_BUFFER_END              0xA
+#define OP_MI_SUSPEND_FLUSH                 0xB
+#define OP_MI_PREDICATE                     0xC  /* IVB+ */
+#define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
+#define OP_MI_SET_APPID                     0xE  /* IVB+ */
+#define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
+#define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
+#define OP_MI_DISPLAY_FLIP                  0x14
+#define OP_MI_SEMAPHORE_MBOX                0x16
+#define OP_MI_SET_CONTEXT                   0x18
+#define OP_MI_MATH                          0x1A
+#define OP_MI_URB_CLEAR                     0x19
+#define OP_MI_SEMAPHORE_SIGNAL             0x1B  /* BDW+ */
+#define OP_MI_SEMAPHORE_WAIT               0x1C  /* BDW+ */
+
+#define OP_MI_STORE_DATA_IMM                0x20
+#define OP_MI_STORE_DATA_INDEX              0x21
+#define OP_MI_LOAD_REGISTER_IMM             0x22
+#define OP_MI_UPDATE_GTT                    0x23
+#define OP_MI_STORE_REGISTER_MEM            0x24
+#define OP_MI_FLUSH_DW                      0x26
+#define OP_MI_CLFLUSH                       0x27
+#define OP_MI_REPORT_PERF_COUNT             0x28
+#define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
+#define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
+#define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
+#define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
+#define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
+#define OP_MI_2E                           0x2E  /* BDW+ */
+#define OP_MI_2F                           0x2F  /* BDW+ */
+#define OP_MI_BATCH_BUFFER_START            0x31
+
+/* Bit definition for dword 0 */
+#define _CMDBIT_BB_START_IN_PPGTT      (1UL << 8)
+
+#define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
+
+#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
+#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
+#define BATCH_BUFFER_ADR_SPACE_BIT(x)  (((x) >> 8) & 1U)
+#define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
+
+/* 2D command: Opcode (28:22) */
+#define OP_2D(x)    ((2<<7) | x)
+
+#define OP_XY_SETUP_BLT                             OP_2D(0x1)
+#define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
+#define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
+#define OP_XY_PIXEL_BLT                             OP_2D(0x24)
+#define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
+#define OP_XY_TEXT_BLT                              OP_2D(0x26)
+#define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
+#define OP_XY_COLOR_BLT                             OP_2D(0x50)
+#define OP_XY_PAT_BLT                               OP_2D(0x51)
+#define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
+#define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
+#define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
+#define OP_XY_FULL_BLT                              OP_2D(0x55)
+#define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
+#define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
+#define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
+#define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
+#define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
+#define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
+#define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
+#define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
+#define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
+#define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
+#define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
+
+/* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
+#define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
+       ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
+
+#define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
+
+#define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
+#define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
+#define OP_3D_MEDIA_0_1_4                      OP_3D_MEDIA(0x0, 0x1, 0x04)
+
+#define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
+
+#define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
+
+#define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
+#define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
+#define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
+#define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
+#define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
+
+#define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
+#define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
+#define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
+#define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
+
+#define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
+#define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
+#define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
+#define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
+#define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
+#define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
+#define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
+#define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
+#define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
+#define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
+#define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
+#define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
+#define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
+#define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
+#define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
+#define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
+#define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
+#define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
+#define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
+#define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
+#define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
+#define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
+#define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
+#define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
+#define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
+#define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
+#define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
+#define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
+#define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
+#define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
+#define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
+#define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
+#define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
+#define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
+#define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
+#define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
+#define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
+#define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
+#define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
+#define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
+#define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
+#define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
+#define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
+#define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
+#define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
+#define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
+#define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
+#define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
+#define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
+#define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
+#define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
+#define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
+#define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
+#define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
+#define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
+#define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
+#define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
+#define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
+#define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
+#define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
+
+#define OP_3DSTATE_VF_INSTANCING               OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
+#define OP_3DSTATE_VF_SGVS                     OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
+#define OP_3DSTATE_VF_TOPOLOGY                 OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
+#define OP_3DSTATE_WM_CHROMAKEY                OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
+#define OP_3DSTATE_PS_BLEND                    OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
+#define OP_3DSTATE_WM_DEPTH_STENCIL            OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
+#define OP_3DSTATE_PS_EXTRA                    OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
+#define OP_3DSTATE_RASTER                      OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
+#define OP_3DSTATE_SBE_SWIZ                    OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
+#define OP_3DSTATE_WM_HZ_OP                    OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
+#define OP_3DSTATE_COMPONENT_PACKING           OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
+
+#define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
+#define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
+#define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
+#define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
+#define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
+#define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
+#define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
+#define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
+#define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
+#define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
+#define OP_3DSTATE_MULTISAMPLE_BDW             OP_3D_MEDIA(0x3, 0x0, 0x0D)
+#define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
+#define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
+#define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
+#define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
+#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
+#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
+#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
+#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
+#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
+#define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
+#define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
+#define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
+#define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
+#define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
+#define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
+#define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
+#define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
+
+/* VCCP Command Parser */
+
+/*
+ * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
+ * git://anongit.freedesktop.org/vaapi/intel-driver
+ * src/i965_defines.h
+ *
+ */
+
+#define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
+       (3 << 13 | \
+        (pipeline) << 11 | \
+        (op) << 8 | \
+        (sub_opa) << 5 | \
+        (sub_opb))
+
+#define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
+#define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
+#define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
+#define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
+#define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
+#define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
+#define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
+#define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
+#define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
+#define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
+#define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
+
+#define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
+
+#define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
+#define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
+#define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
+#define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
+#define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
+#define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
+#define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
+#define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
+#define OP_MFD_AVC_DPB_STATE                      OP_MFX(2, 1, 1, 6) /* IVB+ */
+#define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
+#define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
+#define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
+
+#define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
+#define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
+#define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
+#define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
+#define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
+
+#define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
+#define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
+#define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
+#define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
+#define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
+
+#define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
+#define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
+#define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
+
+#define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
+#define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
+#define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
+
+#define OP_VEB(pipeline, op, sub_opa, sub_opb) \
+       (3 << 13 | \
+        (pipeline) << 11 | \
+        (op) << 8 | \
+        (sub_opa) << 5 | \
+        (sub_opb))
+
+#define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
+#define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
+#define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
+
+struct parser_exec_state;
+
+typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
+
+#define GVT_CMD_HASH_BITS   7
+
+/* which DWords need address fix */
+#define ADDR_FIX_1(x1)                 (1 << (x1))
+#define ADDR_FIX_2(x1, x2)             (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
+#define ADDR_FIX_3(x1, x2, x3)         (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
+#define ADDR_FIX_4(x1, x2, x3, x4)     (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
+#define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
+
+struct cmd_info {
+       char *name;
+       u32 opcode;
+
+#define F_LEN_MASK     (1U<<0)
+#define F_LEN_CONST  1U
+#define F_LEN_VAR    0U
+
+/*
+ * command has its own ip advance logic
+ * e.g. MI_BATCH_START, MI_BATCH_END
+ */
+#define F_IP_ADVANCE_CUSTOM (1<<1)
+
+#define F_POST_HANDLE  (1<<2)
+       u32 flag;
+
+#define R_RCS  (1 << RCS)
+#define R_VCS1  (1 << VCS)
+#define R_VCS2  (1 << VCS2)
+#define R_VCS  (R_VCS1 | R_VCS2)
+#define R_BCS  (1 << BCS)
+#define R_VECS (1 << VECS)
+#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
+       /* rings that support this cmd: BLT/RCS/VCS/VECS */
+       uint16_t rings;
+
+       /* devices that support this cmd: SNB/IVB/HSW/... */
+       uint16_t devices;
+
+       /* which DWords are address that need fix up.
+        * bit 0 means a 32-bit non address operand in command
+        * bit 1 means address operand, which could be 32-bit
+        * or 64-bit depending on different architectures.(
+        * defined by "gmadr_bytes_in_cmd" in intel_gvt.
+        * No matter the address length, each address only takes
+        * one bit in the bitmap.
+        */
+       uint16_t addr_bitmap;
+
+       /* flag == F_LEN_CONST : command length
+        * flag == F_LEN_VAR : length bias bits
+        * Note: length is in DWord
+        */
+       uint8_t len;
+
+       parser_cmd_handler handler;
+};
+
+struct cmd_entry {
+       struct hlist_node hlist;
+       struct cmd_info *info;
+};
+
+enum {
+       RING_BUFFER_INSTRUCTION,
+       BATCH_BUFFER_INSTRUCTION,
+       BATCH_BUFFER_2ND_LEVEL,
+};
+
+enum {
+       GTT_BUFFER,
+       PPGTT_BUFFER
+};
+
+struct parser_exec_state {
+       struct intel_vgpu *vgpu;
+       int ring_id;
+
+       int buf_type;
+
+       /* batch buffer address type */
+       int buf_addr_type;
+
+       /* graphics memory address of ring buffer start */
+       unsigned long ring_start;
+       unsigned long ring_size;
+       unsigned long ring_head;
+       unsigned long ring_tail;
+
+       /* instruction graphics memory address */
+       unsigned long ip_gma;
+
+       /* mapped va of the instr_gma */
+       void *ip_va;
+       void *rb_va;
+
+       void *ret_bb_va;
+       /* next instruction when return from  batch buffer to ring buffer */
+       unsigned long ret_ip_gma_ring;
+
+       /* next instruction when return from 2nd batch buffer to batch buffer */
+       unsigned long ret_ip_gma_bb;
+
+       /* batch buffer address type (GTT or PPGTT)
+        * used when ret from 2nd level batch buffer
+        */
+       int saved_buf_addr_type;
+
+       struct cmd_info *info;
+
+       struct intel_vgpu_workload *workload;
+};
+
+#define gmadr_dw_number(s)     \
+       (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
+
+static unsigned long bypass_scan_mask = 0;
+static bool bypass_batch_buffer_scan = true;
+
+/* ring ALL, type = 0 */
+static struct sub_op_bits sub_op_mi[] = {
+       {31, 29},
+       {28, 23},
+};
+
+static struct decode_info decode_info_mi = {
+       "MI",
+       OP_LEN_MI,
+       ARRAY_SIZE(sub_op_mi),
+       sub_op_mi,
+};
+
+/* ring RCS, command type 2 */
+static struct sub_op_bits sub_op_2d[] = {
+       {31, 29},
+       {28, 22},
+};
+
+static struct decode_info decode_info_2d = {
+       "2D",
+       OP_LEN_2D,
+       ARRAY_SIZE(sub_op_2d),
+       sub_op_2d,
+};
+
+/* ring RCS, command type 3 */
+static struct sub_op_bits sub_op_3d_media[] = {
+       {31, 29},
+       {28, 27},
+       {26, 24},
+       {23, 16},
+};
+
+static struct decode_info decode_info_3d_media = {
+       "3D_Media",
+       OP_LEN_3D_MEDIA,
+       ARRAY_SIZE(sub_op_3d_media),
+       sub_op_3d_media,
+};
+
+/* ring VCS, command type 3 */
+static struct sub_op_bits sub_op_mfx_vc[] = {
+       {31, 29},
+       {28, 27},
+       {26, 24},
+       {23, 21},
+       {20, 16},
+};
+
+static struct decode_info decode_info_mfx_vc = {
+       "MFX_VC",
+       OP_LEN_MFX_VC,
+       ARRAY_SIZE(sub_op_mfx_vc),
+       sub_op_mfx_vc,
+};
+
+/* ring VECS, command type 3 */
+static struct sub_op_bits sub_op_vebox[] = {
+       {31, 29},
+       {28, 27},
+       {26, 24},
+       {23, 21},
+       {20, 16},
+};
+
+static struct decode_info decode_info_vebox = {
+       "VEBOX",
+       OP_LEN_VEBOX,
+       ARRAY_SIZE(sub_op_vebox),
+       sub_op_vebox,
+};
+
+static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
+       [RCS] = {
+               &decode_info_mi,
+               NULL,
+               NULL,
+               &decode_info_3d_media,
+               NULL,
+               NULL,
+               NULL,
+               NULL,
+       },
+
+       [VCS] = {
+               &decode_info_mi,
+               NULL,
+               NULL,
+               &decode_info_mfx_vc,
+               NULL,
+               NULL,
+               NULL,
+               NULL,
+       },
+
+       [BCS] = {
+               &decode_info_mi,
+               NULL,
+               &decode_info_2d,
+               NULL,
+               NULL,
+               NULL,
+               NULL,
+               NULL,
+       },
+
+       [VECS] = {
+               &decode_info_mi,
+               NULL,
+               NULL,
+               &decode_info_vebox,
+               NULL,
+               NULL,
+               NULL,
+               NULL,
+       },
+
+       [VCS2] = {
+               &decode_info_mi,
+               NULL,
+               NULL,
+               &decode_info_mfx_vc,
+               NULL,
+               NULL,
+               NULL,
+               NULL,
+       },
+};
+
+static inline u32 get_opcode(u32 cmd, int ring_id)
+{
+       struct decode_info *d_info;
+
+       if (ring_id >= I915_NUM_ENGINES)
+               return INVALID_OP;
+
+       d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
+       if (d_info == NULL)
+               return INVALID_OP;
+
+       return cmd >> (32 - d_info->op_len);
+}
+
+static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
+               unsigned int opcode, int ring_id)
+{
+       struct cmd_entry *e;
+
+       hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
+               if ((opcode == e->info->opcode) &&
+                               (e->info->rings & (1 << ring_id)))
+                       return e->info;
+       }
+       return NULL;
+}
+
+static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
+               u32 cmd, int ring_id)
+{
+       u32 opcode;
+
+       opcode = get_opcode(cmd, ring_id);
+       if (opcode == INVALID_OP)
+               return NULL;
+
+       return find_cmd_entry(gvt, opcode, ring_id);
+}
+
+static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
+{
+       return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
+}
+
+static inline void print_opcode(u32 cmd, int ring_id)
+{
+       struct decode_info *d_info;
+       int i;
+
+       if (ring_id >= I915_NUM_ENGINES)
+               return;
+
+       d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
+       if (d_info == NULL)
+               return;
+
+       gvt_err("opcode=0x%x %s sub_ops:",
+                       cmd >> (32 - d_info->op_len), d_info->name);
+
+       for (i = 0; i < d_info->nr_sub_op; i++)
+               pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
+                                       d_info->sub_op[i].low));
+
+       pr_err("\n");
+}
+
+static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
+{
+       return s->ip_va + (index << 2);
+}
+
+static inline u32 cmd_val(struct parser_exec_state *s, int index)
+{
+       return *cmd_ptr(s, index);
+}
+
+static void parser_exec_state_dump(struct parser_exec_state *s)
+{
+       int cnt = 0;
+       int i;
+
+       gvt_err("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
+                       " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
+                       s->ring_id, s->ring_start, s->ring_start + s->ring_size,
+                       s->ring_head, s->ring_tail);
+
+       gvt_err("  %s %s ip_gma(%08lx) ",
+                       s->buf_type == RING_BUFFER_INSTRUCTION ?
+                       "RING_BUFFER" : "BATCH_BUFFER",
+                       s->buf_addr_type == GTT_BUFFER ?
+                       "GTT" : "PPGTT", s->ip_gma);
+
+       if (s->ip_va == NULL) {
+               gvt_err(" ip_va(NULL)");
+               return;
+       }
+
+       gvt_err("  ip_va=%p: %08x %08x %08x %08x\n",
+                       s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
+                       cmd_val(s, 2), cmd_val(s, 3));
+
+       print_opcode(cmd_val(s, 0), s->ring_id);
+
+       /* print the whole page to trace */
+       pr_err("    ip_va=%p: %08x %08x %08x %08x\n",
+                       s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
+                       cmd_val(s, 2), cmd_val(s, 3));
+
+       s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
+
+       while (cnt < 1024) {
+               pr_err("ip_va=%p: ", s->ip_va);
+               for (i = 0; i < 8; i++)
+                       pr_err("%08x ", cmd_val(s, i));
+               pr_err("\n");
+
+               s->ip_va += 8 * sizeof(u32);
+               cnt += 8;
+       }
+}
+
+static inline void update_ip_va(struct parser_exec_state *s)
+{
+       unsigned long len = 0;
+
+       if (WARN_ON(s->ring_head == s->ring_tail))
+               return;
+
+       if (s->buf_type == RING_BUFFER_INSTRUCTION) {
+               unsigned long ring_top = s->ring_start + s->ring_size;
+
+               if (s->ring_head > s->ring_tail) {
+                       if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
+                               len = (s->ip_gma - s->ring_head);
+                       else if (s->ip_gma >= s->ring_start &&
+                                       s->ip_gma <= s->ring_tail)
+                               len = (ring_top - s->ring_head) +
+                                       (s->ip_gma - s->ring_start);
+               } else
+                       len = (s->ip_gma - s->ring_head);
+
+               s->ip_va = s->rb_va + len;
+       } else {/* shadow batch buffer */
+               s->ip_va = s->ret_bb_va;
+       }
+}
+
+static inline int ip_gma_set(struct parser_exec_state *s,
+               unsigned long ip_gma)
+{
+       WARN_ON(!IS_ALIGNED(ip_gma, 4));
+
+       s->ip_gma = ip_gma;
+       update_ip_va(s);
+       return 0;
+}
+
+static inline int ip_gma_advance(struct parser_exec_state *s,
+               unsigned int dw_len)
+{
+       s->ip_gma += (dw_len << 2);
+
+       if (s->buf_type == RING_BUFFER_INSTRUCTION) {
+               if (s->ip_gma >= s->ring_start + s->ring_size)
+                       s->ip_gma -= s->ring_size;
+               update_ip_va(s);
+       } else {
+               s->ip_va += (dw_len << 2);
+       }
+
+       return 0;
+}
+
+static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
+{
+       if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
+               return info->len;
+       else
+               return (cmd & ((1U << info->len) - 1)) + 2;
+       return 0;
+}
+
+static inline int cmd_length(struct parser_exec_state *s)
+{
+       return get_cmd_length(s->info, cmd_val(s, 0));
+}
+
+/* do not remove this, some platform may need clflush here */
+#define patch_value(s, addr, val) do { \
+       *addr = val; \
+} while (0)
+
+static bool is_shadowed_mmio(unsigned int offset)
+{
+       bool ret = false;
+
+       if ((offset == 0x2168) || /*BB current head register UDW */
+           (offset == 0x2140) || /*BB current header register */
+           (offset == 0x211c) || /*second BB header register UDW */
+           (offset == 0x2114)) { /*second BB header register UDW */
+               ret = true;
+       }
+       return ret;
+}
+
+static int cmd_reg_handler(struct parser_exec_state *s,
+       unsigned int offset, unsigned int index, char *cmd)
+{
+       struct intel_vgpu *vgpu = s->vgpu;
+       struct intel_gvt *gvt = vgpu->gvt;
+
+       if (offset + 4 > gvt->device_info.mmio_size) {
+               gvt_err("%s access to (%x) outside of MMIO range\n",
+                               cmd, offset);
+               return -EINVAL;
+       }
+
+       if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
+               gvt_err("vgpu%d: %s access to non-render register (%x)\n",
+                               s->vgpu->id, cmd, offset);
+               return 0;
+       }
+
+       if (is_shadowed_mmio(offset)) {
+               gvt_err("vgpu%d: found access of shadowed MMIO %x\n",
+                               s->vgpu->id, offset);
+               return 0;
+       }
+
+       if (offset == i915_mmio_reg_offset(DERRMR) ||
+               offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
+               /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
+               patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
+       }
+
+       /* TODO: Update the global mask if this MMIO is a masked-MMIO */
+       intel_gvt_mmio_set_cmd_accessed(gvt, offset);
+       return 0;
+}
+
+#define cmd_reg(s, i) \
+       (cmd_val(s, i) & GENMASK(22, 2))
+
+#define cmd_reg_inhibit(s, i) \
+       (cmd_val(s, i) & GENMASK(22, 18))
+
+#define cmd_gma(s, i) \
+       (cmd_val(s, i) & GENMASK(31, 2))
+
+#define cmd_gma_hi(s, i) \
+       (cmd_val(s, i) & GENMASK(15, 0))
+
+static int cmd_handler_lri(struct parser_exec_state *s)
+{
+       int i, ret = 0;
+       int cmd_len = cmd_length(s);
+       struct intel_gvt *gvt = s->vgpu->gvt;
+
+       for (i = 1; i < cmd_len; i += 2) {
+               if (IS_BROADWELL(gvt->dev_priv) &&
+                               (s->ring_id != RCS)) {
+                       if (s->ring_id == BCS &&
+                                       cmd_reg(s, i) ==
+                                       i915_mmio_reg_offset(DERRMR))
+                               ret |= 0;
+                       else
+                               ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
+               }
+               if (ret)
+                       break;
+               ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
+       }
+       return ret;
+}
+
+static int cmd_handler_lrr(struct parser_exec_state *s)
+{
+       int i, ret = 0;
+       int cmd_len = cmd_length(s);
+
+       for (i = 1; i < cmd_len; i += 2) {
+               if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
+                       ret |= ((cmd_reg_inhibit(s, i) ||
+                                       (cmd_reg_inhibit(s, i + 1)))) ?
+                               -EINVAL : 0;
+               if (ret)
+                       break;
+               ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
+               ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
+       }
+       return ret;
+}
+
+static inline int cmd_address_audit(struct parser_exec_state *s,
+               unsigned long guest_gma, int op_size, bool index_mode);
+
+static int cmd_handler_lrm(struct parser_exec_state *s)
+{
+       struct intel_gvt *gvt = s->vgpu->gvt;
+       int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
+       unsigned long gma;
+       int i, ret = 0;
+       int cmd_len = cmd_length(s);
+
+       for (i = 1; i < cmd_len;) {
+               if (IS_BROADWELL(gvt->dev_priv))
+                       ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
+               if (ret)
+                       break;
+               ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
+               if (cmd_val(s, 0) & (1 << 22)) {
+                       gma = cmd_gma(s, i + 1);
+                       if (gmadr_bytes == 8)
+                               gma |= (cmd_gma_hi(s, i + 2)) << 32;
+                       ret |= cmd_address_audit(s, gma, sizeof(u32), false);
+               }
+               i += gmadr_dw_number(s) + 1;
+       }
+       return ret;
+}
+
+static int cmd_handler_srm(struct parser_exec_state *s)
+{
+       int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+       unsigned long gma;
+       int i, ret = 0;
+       int cmd_len = cmd_length(s);
+
+       for (i = 1; i < cmd_len;) {
+               ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
+               if (cmd_val(s, 0) & (1 << 22)) {
+                       gma = cmd_gma(s, i + 1);
+                       if (gmadr_bytes == 8)
+                               gma |= (cmd_gma_hi(s, i + 2)) << 32;
+                       ret |= cmd_address_audit(s, gma, sizeof(u32), false);
+               }
+               i += gmadr_dw_number(s) + 1;
+       }
+       return ret;
+}
+
+struct cmd_interrupt_event {
+       int pipe_control_notify;
+       int mi_flush_dw;
+       int mi_user_interrupt;
+};
+
+static struct cmd_interrupt_event cmd_interrupt_events[] = {
+       [RCS] = {
+               .pipe_control_notify = RCS_PIPE_CONTROL,
+               .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
+               .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
+       },
+       [BCS] = {
+               .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
+               .mi_flush_dw = BCS_MI_FLUSH_DW,
+               .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
+       },
+       [VCS] = {
+               .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
+               .mi_flush_dw = VCS_MI_FLUSH_DW,
+               .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
+       },
+       [VCS2] = {
+               .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
+               .mi_flush_dw = VCS2_MI_FLUSH_DW,
+               .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
+       },
+       [VECS] = {
+               .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
+               .mi_flush_dw = VECS_MI_FLUSH_DW,
+               .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
+       },
+};
+
+static int cmd_handler_pipe_control(struct parser_exec_state *s)
+{
+       int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+       unsigned long gma;
+       bool index_mode = false;
+       unsigned int post_sync;
+       int ret = 0;
+
+       post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
+
+       /* LRI post sync */
+       if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
+               ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
+       /* post sync */
+       else if (post_sync) {
+               if (post_sync == 2)
+                       ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
+               else if (post_sync == 3)
+                       ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
+               else if (post_sync == 1) {
+                       /* check ggtt*/
+                       if ((cmd_val(s, 2) & (1 << 2))) {
+                               gma = cmd_val(s, 2) & GENMASK(31, 3);
+                               if (gmadr_bytes == 8)
+                                       gma |= (cmd_gma_hi(s, 3)) << 32;
+                               /* Store Data Index */
+                               if (cmd_val(s, 1) & (1 << 21))
+                                       index_mode = true;
+                               ret |= cmd_address_audit(s, gma, sizeof(u64),
+                                               index_mode);
+                       }
+               }
+       }
+
+       if (ret)
+               return ret;
+
+       if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
+               set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
+                               s->workload->pending_events);
+       return 0;
+}
+
+static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
+{
+       set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
+                       s->workload->pending_events);
+       return 0;
+}
+
+static int cmd_advance_default(struct parser_exec_state *s)
+{
+       return ip_gma_advance(s, cmd_length(s));
+}
+
+static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
+{
+       int ret;
+
+       if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
+               s->buf_type = BATCH_BUFFER_INSTRUCTION;
+               ret = ip_gma_set(s, s->ret_ip_gma_bb);
+               s->buf_addr_type = s->saved_buf_addr_type;
+       } else {
+               s->buf_type = RING_BUFFER_INSTRUCTION;
+               s->buf_addr_type = GTT_BUFFER;
+               if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
+                       s->ret_ip_gma_ring -= s->ring_size;
+               ret = ip_gma_set(s, s->ret_ip_gma_ring);
+       }
+       return ret;
+}
+
+struct mi_display_flip_command_info {
+       int pipe;
+       int plane;
+       int event;
+       i915_reg_t stride_reg;
+       i915_reg_t ctrl_reg;
+       i915_reg_t surf_reg;
+       u64 stride_val;
+       u64 tile_val;
+       u64 surf_val;
+       bool async_flip;
+};
+
+struct plane_code_mapping {
+       int pipe;
+       int plane;
+       int event;
+};
+
+static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+       struct plane_code_mapping gen8_plane_code[] = {
+               [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
+               [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
+               [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
+               [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
+               [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
+               [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
+       };
+       u32 dword0, dword1, dword2;
+       u32 v;
+
+       dword0 = cmd_val(s, 0);
+       dword1 = cmd_val(s, 1);
+       dword2 = cmd_val(s, 2);
+
+       v = (dword0 & GENMASK(21, 19)) >> 19;
+       if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
+               return -EINVAL;
+
+       info->pipe = gen8_plane_code[v].pipe;
+       info->plane = gen8_plane_code[v].plane;
+       info->event = gen8_plane_code[v].event;
+       info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
+       info->tile_val = (dword1 & 0x1);
+       info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
+       info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
+
+       if (info->plane == PLANE_A) {
+               info->ctrl_reg = DSPCNTR(info->pipe);
+               info->stride_reg = DSPSTRIDE(info->pipe);
+               info->surf_reg = DSPSURF(info->pipe);
+       } else if (info->plane == PLANE_B) {
+               info->ctrl_reg = SPRCTL(info->pipe);
+               info->stride_reg = SPRSTRIDE(info->pipe);
+               info->surf_reg = SPRSURF(info->pipe);
+       } else {
+               WARN_ON(1);
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static int skl_decode_mi_display_flip(struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+       u32 dword0 = cmd_val(s, 0);
+       u32 dword1 = cmd_val(s, 1);
+       u32 dword2 = cmd_val(s, 2);
+       u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
+
+       switch (plane) {
+       case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
+               info->pipe = PIPE_A;
+               info->event = PRIMARY_A_FLIP_DONE;
+               break;
+       case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
+               info->pipe = PIPE_B;
+               info->event = PRIMARY_B_FLIP_DONE;
+               break;
+       case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
+               info->pipe = PIPE_B;
+               info->event = PRIMARY_C_FLIP_DONE;
+               break;
+       default:
+               gvt_err("unknown plane code %d\n", plane);
+               return -EINVAL;
+       }
+
+       info->pipe = PRIMARY_PLANE;
+       info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
+       info->tile_val = (dword1 & GENMASK(2, 0));
+       info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
+       info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
+
+       info->ctrl_reg = DSPCNTR(info->pipe);
+       info->stride_reg = DSPSTRIDE(info->pipe);
+       info->surf_reg = DSPSURF(info->pipe);
+
+       return 0;
+}
+
+static int gen8_check_mi_display_flip(struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+       u32 stride, tile;
+
+       if (!info->async_flip)
+               return 0;
+
+       if (IS_SKYLAKE(dev_priv)) {
+               stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);
+               tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &
+                               GENMASK(12, 10)) >> 10;
+       } else {
+               stride = (vgpu_vreg(s->vgpu, info->stride_reg) &
+                               GENMASK(15, 6)) >> 6;
+               tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
+       }
+
+       if (stride != info->stride_val)
+               gvt_dbg_cmd("cannot change stride during async flip\n");
+
+       if (tile != info->tile_val)
+               gvt_dbg_cmd("cannot change tile during async flip\n");
+
+       return 0;
+}
+
+static int gen8_update_plane_mmio_from_mi_display_flip(
+               struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+       struct intel_vgpu *vgpu = s->vgpu;
+
+#define write_bits(reg, e, s, v) do { \
+       vgpu_vreg(vgpu, reg) &= ~GENMASK(e, s); \
+       vgpu_vreg(vgpu, reg) |= (v << s); \
+} while (0)
+
+       write_bits(info->surf_reg, 31, 12, info->surf_val);
+       if (IS_SKYLAKE(dev_priv))
+               write_bits(info->stride_reg, 9, 0, info->stride_val);
+       else
+               write_bits(info->stride_reg, 15, 6, info->stride_val);
+       write_bits(info->ctrl_reg, IS_SKYLAKE(dev_priv) ? 12 : 10,
+                  10, info->tile_val);
+
+#undef write_bits
+
+       vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
+       intel_vgpu_trigger_virtual_event(vgpu, info->event);
+       return 0;
+}
+
+static int decode_mi_display_flip(struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+
+       if (IS_BROADWELL(dev_priv))
+               return gen8_decode_mi_display_flip(s, info);
+       if (IS_SKYLAKE(dev_priv))
+               return skl_decode_mi_display_flip(s, info);
+
+       return -ENODEV;
+}
+
+static int check_mi_display_flip(struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+
+       if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+               return gen8_check_mi_display_flip(s, info);
+       return -ENODEV;
+}
+
+static int update_plane_mmio_from_mi_display_flip(
+               struct parser_exec_state *s,
+               struct mi_display_flip_command_info *info)
+{
+       struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+
+       if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+               return gen8_update_plane_mmio_from_mi_display_flip(s, info);
+       return -ENODEV;
+}
+
+static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
+{
+       struct mi_display_flip_command_info info;
+       int ret;
+       int i;
+       int len = cmd_length(s);
+
+       ret = decode_mi_display_flip(s, &info);
+       if (ret) {
+               gvt_err("fail to decode MI display flip command\n");
+               return ret;
+       }
+
+       ret = check_mi_display_flip(s, &info);
+       if (ret) {
+               gvt_err("invalid MI display flip command\n");
+               return ret;
+       }
+
+       ret = update_plane_mmio_from_mi_display_flip(s, &info);
+       if (ret) {
+               gvt_err("fail to update plane mmio\n");
+               return ret;
+       }
+
+       for (i = 0; i < len; i++)
+               patch_value(s, cmd_ptr(s, i), MI_NOOP);
+       return 0;
+}
+
+static bool is_wait_for_flip_pending(u32 cmd)
+{
+       return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
+                       MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
+                       MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
+                       MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
+                       MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
+                       MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
+}
+
+static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
+{
+       u32 cmd = cmd_val(s, 0);
+
+       if (!is_wait_for_flip_pending(cmd))
+               return 0;
+
+       patch_value(s, cmd_ptr(s, 0), MI_NOOP);
+       return 0;
+}
+
+static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
+{
+       unsigned long addr;
+       unsigned long gma_high, gma_low;
+       int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+
+       if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
+               return INTEL_GVT_INVALID_ADDR;
+
+       gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
+       if (gmadr_bytes == 4) {
+               addr = gma_low;
+       } else {
+               gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
+               addr = (((unsigned long)gma_high) << 32) | gma_low;
+       }
+       return addr;
+}
+
+static inline int cmd_address_audit(struct parser_exec_state *s,
+               unsigned long guest_gma, int op_size, bool index_mode)
+{
+       struct intel_vgpu *vgpu = s->vgpu;
+       u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
+       int i;
+       int ret;
+
+       if (op_size > max_surface_size) {
+               gvt_err("command address audit fail name %s\n", s->info->name);
+               return -EINVAL;
+       }
+
+       if (index_mode) {
+               if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
+                       ret = -EINVAL;
+                       goto err;
+               }
+       } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) ||
+                       (!vgpu_gmadr_is_valid(s->vgpu,
+                                             guest_gma + op_size - 1))) {
+               ret = -EINVAL;
+               goto err;
+       }
+       return 0;
+err:
+       gvt_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
+                       s->info->name, guest_gma, op_size);
+
+       pr_err("cmd dump: ");
+       for (i = 0; i < cmd_length(s); i++) {
+               if (!(i % 4))
+                       pr_err("\n%08x ", cmd_val(s, i));
+               else
+                       pr_err("%08x ", cmd_val(s, i));
+       }
+       pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
+                       vgpu->id,
+                       vgpu_aperture_gmadr_base(vgpu),
+                       vgpu_aperture_gmadr_end(vgpu),
+                       vgpu_hidden_gmadr_base(vgpu),
+                       vgpu_hidden_gmadr_end(vgpu));
+       return ret;
+}
+
+static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
+{
+       int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+       int op_size = (cmd_length(s) - 3) * sizeof(u32);
+       int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
+       unsigned long gma, gma_low, gma_high;
+       int ret = 0;
+
+       /* check ppggt */
+       if (!(cmd_val(s, 0) & (1 << 22)))
+               return 0;
+
+       gma = cmd_val(s, 2) & GENMASK(31, 2);
+
+       if (gmadr_bytes == 8) {
+               gma_low = cmd_val(s, 1) & GENMASK(31, 2);
+               gma_high = cmd_val(s, 2) & GENMASK(15, 0);
+               gma = (gma_high << 32) | gma_low;
+               core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
+       }
+       ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
+       return ret;
+}
+
+static inline int unexpected_cmd(struct parser_exec_state *s)
+{
+       gvt_err("vgpu%d: Unexpected %s in command buffer!\n",
+                       s->vgpu->id, s->info->name);
+       return -EINVAL;
+}
+
+static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
+{
+       int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+       int op_size = ((1 << (cmd_val(s, 0) & GENMASK(20, 19) >> 19)) *
+                       sizeof(u32));
+       unsigned long gma, gma_high;
+       int ret = 0;
+
+       if (!(cmd_val(s, 0) & (1 << 22)))
+               return ret;
+
+       gma = cmd_val(s, 1) & GENMASK(31, 2);
+       if (gmadr_bytes == 8) {
+               gma_high = cmd_val(s, 2) & GENMASK(15, 0);
+               gma = (gma_high << 32) | gma;
+       }
+       ret = cmd_address_audit(s, gma, op_size, false);
+       return ret;
+}
+
+static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_clflush(struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_conditional_batch_buffer_end(
+               struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
+{
+       return unexpected_cmd(s);
+}
+
+static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
+{
+       int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+       unsigned long gma;
+       bool index_mode = false;
+       int ret = 0;
+
+       /* Check post-sync and ppgtt bit */
+       if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
+               gma = cmd_val(s, 1) & GENMASK(31, 3);
+               if (gmadr_bytes == 8)
+                       gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
+               /* Store Data Index */
+               if (cmd_val(s, 0) & (1 << 21))
+                       index_mode = true;
+               ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
+       }
+       /* Check notify bit */
+       if ((cmd_val(s, 0) & (1 << 8)))
+               set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
+                               s->workload->pending_events);
+       return ret;
+}
+
+static void addr_type_update_snb(struct parser_exec_state *s)
+{
+       if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
+                       (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
+               s->buf_addr_type = PPGTT_BUFFER;
+       }
+}
+
+
+static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
+               unsigned long gma, unsigned long end_gma, void *va)
+{
+       unsigned long copy_len, offset;
+       unsigned long len = 0;
+       unsigned long gpa;
+
+       while (gma != end_gma) {
+               gpa = intel_vgpu_gma_to_gpa(mm, gma);
+               if (gpa == INTEL_GVT_INVALID_ADDR) {
+                       gvt_err("invalid gma address: %lx\n", gma);
+                       return -EFAULT;
+               }
+
+               offset = gma & (GTT_PAGE_SIZE - 1);
+
+               copy_len = (end_gma - gma) >= (GTT_PAGE_SIZE - offset) ?
+                       GTT_PAGE_SIZE - offset : end_gma - gma;
+
+               intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
+
+               len += copy_len;
+               gma += copy_len;
+       }
+       return 0;
+}
+
+
+/*
+ * Check whether a batch buffer needs to be scanned. Currently
+ * the only criteria is based on privilege.
+ */
+static int batch_buffer_needs_scan(struct parser_exec_state *s)
+{
+       struct intel_gvt *gvt = s->vgpu->gvt;
+
+       if (bypass_batch_buffer_scan)
+               return 0;
+
+       if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
+               /* BDW decides privilege based on address space */
+               if (cmd_val(s, 0) & (1 << 8))
+                       return 0;
+       }
+       return 1;
+}
+
+static uint32_t find_bb_size(struct parser_exec_state *s)
+{
+       unsigned long gma = 0;
+       struct cmd_info *info;
+       uint32_t bb_size = 0;
+       uint32_t cmd_len = 0;
+       bool met_bb_end = false;
+       u32 cmd;
+
+       /* get the start gm address of the batch buffer */
+       gma = get_gma_bb_from_cmd(s, 1);
+       cmd = cmd_val(s, 0);
+
+       info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
+       if (info == NULL) {
+               gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
+                               cmd, get_opcode(cmd, s->ring_id));
+               return -EINVAL;
+       }
+       do {
+               copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
+                               gma, gma + 4, &cmd);
+               info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
+               if (info == NULL) {
+                       gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
+                               cmd, get_opcode(cmd, s->ring_id));
+                       return -EINVAL;
+               }
+
+               if (info->opcode == OP_MI_BATCH_BUFFER_END) {
+                       met_bb_end = true;
+               } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
+                       if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) {
+                               /* chained batch buffer */
+                               met_bb_end = true;
+                       }
+               }
+               cmd_len = get_cmd_length(info, cmd) << 2;
+               bb_size += cmd_len;
+               gma += cmd_len;
+
+       } while (!met_bb_end);
+
+       return bb_size;
+}
+
+static int perform_bb_shadow(struct parser_exec_state *s)
+{
+       struct intel_shadow_bb_entry *entry_obj;
+       unsigned long gma = 0;
+       uint32_t bb_size;
+       void *dst = NULL;
+       int ret = 0;
+
+       /* get the start gm address of the batch buffer */
+       gma = get_gma_bb_from_cmd(s, 1);
+
+       /* get the size of the batch buffer */
+       bb_size = find_bb_size(s);
+
+       /* allocate shadow batch buffer */
+       entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
+       if (entry_obj == NULL)
+               return -ENOMEM;
+
+       entry_obj->obj =
+               i915_gem_object_create(&(s->vgpu->gvt->dev_priv->drm),
+                                      roundup(bb_size, PAGE_SIZE));
+       if (IS_ERR(entry_obj->obj)) {
+               ret = PTR_ERR(entry_obj->obj);
+               goto free_entry;
+       }
+       entry_obj->len = bb_size;
+       INIT_LIST_HEAD(&entry_obj->list);
+
+       dst = i915_gem_object_pin_map(entry_obj->obj, I915_MAP_WB);
+       if (IS_ERR(dst)) {
+               ret = PTR_ERR(dst);
+               goto put_obj;
+       }
+
+       ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);
+       if (ret) {
+               gvt_err("failed to set shadow batch to CPU\n");
+               goto unmap_src;
+       }
+
+       entry_obj->va = dst;
+       entry_obj->bb_start_cmd_va = s->ip_va;
+
+       /* copy batch buffer to shadow batch buffer*/
+       ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
+                             gma, gma + bb_size,
+                             dst);
+       if (ret) {
+               gvt_err("fail to copy guest ring buffer\n");
+               goto unmap_src;
+       }
+
+       list_add(&entry_obj->list, &s->workload->shadow_bb);
+       /*
+        * ip_va saves the virtual address of the shadow batch buffer, while
+        * ip_gma saves the graphics address of the original batch buffer.
+        * As the shadow batch buffer is just a copy from the originial one,
+        * it should be right to use shadow batch buffer'va and original batch
+        * buffer's gma in pair. After all, we don't want to pin the shadow
+        * buffer here (too early).
+        */
+       s->ip_va = dst;
+       s->ip_gma = gma;
+
+       return 0;
+
+unmap_src:
+       i915_gem_object_unpin_map(entry_obj->obj);
+put_obj:
+       i915_gem_object_put(entry_obj->obj);
+free_entry:
+       kfree(entry_obj);
+       return ret;
+}
+
+static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
+{
+       bool second_level;
+       int ret = 0;
+
+       if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
+               gvt_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
+               return -EINVAL;
+       }
+
+       second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
+       if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
+               gvt_err("Jumping to 2nd level BB from RB is not allowed\n");
+               return -EINVAL;
+       }
+
+       s->saved_buf_addr_type = s->buf_addr_type;
+       addr_type_update_snb(s);
+       if (s->buf_type == RING_BUFFER_INSTRUCTION) {
+               s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
+               s->buf_type = BATCH_BUFFER_INSTRUCTION;
+       } else if (second_level) {
+               s->buf_type = BATCH_BUFFER_2ND_LEVEL;
+               s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
+               s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
+       }
+
+       if (batch_buffer_needs_scan(s)) {
+               ret = perform_bb_shadow(s);
+               if (ret < 0)
+                       gvt_err("invalid shadow batch buffer\n");
+       } else {
+               /* emulate a batch buffer end to do return right */
+               ret = cmd_handler_mi_batch_buffer_end(s);
+               if (ret < 0)
+                       return ret;
+       }
+
+       return ret;
+}
+
+static struct cmd_info cmd_info[] = {
+       {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
+
+       {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
+               0, 1, NULL},
+
+       {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
+               0, 1, cmd_handler_mi_user_interrupt},
+
+       {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
+               D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
+
+       {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
+
+       {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
+               D_ALL, 0, 1, NULL},
+
+       {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
+               F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
+               cmd_handler_mi_batch_buffer_end},
+
+       {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
+               0, 1, NULL},
+
+       {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
+               D_ALL, 0, 1, NULL},
+
+       {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
+               NULL},
+
+       {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
+               R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
+
+       {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
+               0, 8, NULL},
+
+       {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
+
+       {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
+               ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
+
+       {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
+               ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
+
+       {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
+               0, 8, cmd_handler_mi_store_data_index},
+
+       {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
+               D_ALL, 0, 8, cmd_handler_lri},
+
+       {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
+               cmd_handler_mi_update_gtt},
+
+       {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
+               D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
+
+       {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
+               cmd_handler_mi_flush_dw},
+
+       {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
+               10, cmd_handler_mi_clflush},
+
+       {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
+               D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
+
+       {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
+               D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
+
+       {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
+               D_ALL, 0, 8, cmd_handler_lrr},
+
+       {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 8, NULL},
+
+       {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
+               ADDR_FIX_1(2), 8, NULL},
+
+       {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
+               ADDR_FIX_1(2), 8, NULL},
+
+       {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
+               8, cmd_handler_mi_op_2e},
+
+       {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
+               8, cmd_handler_mi_op_2f},
+
+       {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
+               F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
+               cmd_handler_mi_batch_buffer_start},
+
+       {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
+               F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
+               cmd_handler_mi_conditional_batch_buffer_end},
+
+       {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
+               R_RCS | R_BCS, D_ALL, 0, 2, NULL},
+
+       {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_2(4, 7), 8, NULL},
+
+       {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               0, 8, NULL},
+
+       {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
+               F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
+
+       {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
+
+       {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               0, 8, NULL},
+
+       {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_1(3), 8, NULL},
+
+       {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
+               D_ALL, 0, 8, NULL},
+
+       {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_1(4), 8, NULL},
+
+       {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_2(4, 5), 8, NULL},
+
+       {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_1(4), 8, NULL},
+
+       {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_2(4, 7), 8, NULL},
+
+       {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
+               D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
+
+       {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
+
+       {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
+               D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
+
+       {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
+               R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
+
+       {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
+               OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
+               F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
+
+       {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
+               D_ALL, ADDR_FIX_1(4), 8, NULL},
+
+       {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
+               F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
+
+       {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
+               D_ALL, ADDR_FIX_1(4), 8, NULL},
+
+       {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
+               D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
+
+       {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
+               F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
+
+       {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
+               OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
+               F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
+
+       {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
+               ADDR_FIX_2(4, 5), 8, NULL},
+
+       {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
+               F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
+
+       {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
+               OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
+               OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BLEND_STATE_POINTERS",
+               OP_3DSTATE_BLEND_STATE_POINTERS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
+               OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_POINTERS_VS",
+               OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_POINTERS_HS",
+               OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_POINTERS_DS",
+               OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_POINTERS_GS",
+               OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_POINTERS_PS",
+               OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
+               OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
+               OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
+               OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
+               OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
+               OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
+               0, 8, NULL},
+
+       {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
+               0, 8, NULL},
+
+       {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
+               0, 8, NULL},
+
+       {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
+               0, 8, NULL},
+
+       {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
+
+       {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
+
+       {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
+
+       {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
+
+       {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
+
+       {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
+
+       {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
+
+       {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
+               NULL},
+
+       {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
+               8, NULL},
+
+       {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
+               R_RCS, D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
+               8, NULL},
+
+       {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
+               NULL},
+
+       {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
+               NULL},
+
+       {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
+               NULL},
+
+       {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
+               R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
+
+       {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
+               R_RCS, D_ALL, 0, 1, NULL},
+
+       {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
+               R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
+               R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
+               0, 8, NULL},
+
+       {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
+               D_ALL, ADDR_FIX_1(2), 8, NULL},
+
+       {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
+               D_ALL, ADDR_FIX_1(2), 8, NULL},
+
+       {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
+               R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
+
+       {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
+               R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
+               R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
+               D_ALL, 0, 9, NULL},
+
+       {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
+               ADDR_FIX_2(2, 4), 8, NULL},
+
+       {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
+               OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
+               F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
+
+       {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
+               F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
+
+       {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
+               OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
+               F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
+
+       {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
+               D_BDW_PLUS, 0, 8, NULL},
+
+       {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
+               ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
+
+       {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
+               1, NULL},
+
+       {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
+               ADDR_FIX_1(1), 8, NULL},
+
+       {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
+               ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
+
+       {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
+               ADDR_FIX_1(1), 8, NULL},
+
+       {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
+
+       {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
+               0, 8, NULL},
+
+       {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
+               D_SKL_PLUS, 0, 8, NULL},
+
+       {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
+               F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
+
+       {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
+               0, 16, NULL},
+
+       {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
+               0, 16, NULL},
+
+       {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
+
+       {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
+               0, 16, NULL},
+
+       {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
+               0, 16, NULL},
+
+       {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
+               0, 16, NULL},
+
+       {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
+               0, 8, NULL},
+
+       {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
+               NULL},
+
+       {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
+               F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
+
+       {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
+               R_VCS, D_BDW_PLUS, 0, 12, NULL},
+
+       {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
+               F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
+
+       {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
+               F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
+
+       {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
+
+       {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 6, NULL},
+
+       {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+       {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
+               R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
+
+       {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
+               0, 16, NULL},
+
+       {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
+
+       {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
+
+       {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
+               R_VCS, D_ALL, 0, 12, NULL},
+
+       {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
+
+       {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
+               0, 12, NULL},
+
+       {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
+               0, 20, NULL},
+};
+
+static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
+{
+       hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
+}
+
+#define GVT_MAX_CMD_LENGTH     20  /* In Dword */
+
+static void trace_cs_command(struct parser_exec_state *s,
+               cycles_t cost_pre_cmd_handler, cycles_t cost_cmd_handler)
+{
+       /* This buffer is used by ftrace to store all commands copied from
+        * guest gma space. Sometimes commands can cross pages, this should
+        * not be handled in ftrace logic. So this is just used as a
+        * 'bounce buffer'
+        */
+       u32 cmd_trace_buf[GVT_MAX_CMD_LENGTH];
+       int i;
+       u32 cmd_len = cmd_length(s);
+       /* The chosen value of GVT_MAX_CMD_LENGTH are just based on
+        * following two considerations:
+        * 1) From observation, most common ring commands is not that long.
+        *    But there are execeptions. So it indeed makes sence to observe
+        *    longer commands.
+        * 2) From the performance and debugging point of view, dumping all
+        *    contents of very commands is not necessary.
+        * We mgith shrink GVT_MAX_CMD_LENGTH or remove this trace event in
+        * future for performance considerations.
+        */
+       if (unlikely(cmd_len > GVT_MAX_CMD_LENGTH)) {
+               gvt_dbg_cmd("cmd length exceed tracing limitation!\n");
+               cmd_len = GVT_MAX_CMD_LENGTH;
+       }
+
+       for (i = 0; i < cmd_len; i++)
+               cmd_trace_buf[i] = cmd_val(s, i);
+
+       trace_gvt_command(s->vgpu->id, s->ring_id, s->ip_gma, cmd_trace_buf,
+                       cmd_len, s->buf_type == RING_BUFFER_INSTRUCTION,
+                       cost_pre_cmd_handler, cost_cmd_handler);
+}
+
+/* call the cmd handler, and advance ip */
+static int cmd_parser_exec(struct parser_exec_state *s)
+{
+       struct cmd_info *info;
+       u32 cmd;
+       int ret = 0;
+       cycles_t t0, t1, t2;
+       struct parser_exec_state s_before_advance_custom;
+
+       t0 = get_cycles();
+
+       cmd = cmd_val(s, 0);
+
+       info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
+       if (info == NULL) {
+               gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
+                               cmd, get_opcode(cmd, s->ring_id));
+               return -EINVAL;
+       }
+
+       gvt_dbg_cmd("%s\n", info->name);
+
+       s->info = info;
+
+       t1 = get_cycles();
+
+       memcpy(&s_before_advance_custom, s, sizeof(struct parser_exec_state));
+
+       if (info->handler) {
+               ret = info->handler(s);
+               if (ret < 0) {
+                       gvt_err("%s handler error\n", info->name);
+                       return ret;
+               }
+       }
+       t2 = get_cycles();
+
+       trace_cs_command(&s_before_advance_custom, t1 - t0, t2 - t1);
+
+       if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
+               ret = cmd_advance_default(s);
+               if (ret) {
+                       gvt_err("%s IP advance error\n", info->name);
+                       return ret;
+               }
+       }
+       return 0;
+}
+
+static inline bool gma_out_of_range(unsigned long gma,
+               unsigned long gma_head, unsigned int gma_tail)
+{
+       if (gma_tail >= gma_head)
+               return (gma < gma_head) || (gma > gma_tail);
+       else
+               return (gma > gma_tail) && (gma < gma_head);
+}
+
+static int command_scan(struct parser_exec_state *s,
+               unsigned long rb_head, unsigned long rb_tail,
+               unsigned long rb_start, unsigned long rb_len)
+{
+
+       unsigned long gma_head, gma_tail, gma_bottom;
+       int ret = 0;
+
+       gma_head = rb_start + rb_head;
+       gma_tail = rb_start + rb_tail;
+       gma_bottom = rb_start +  rb_len;
+
+       gvt_dbg_cmd("scan_start: start=%lx end=%lx\n", gma_head, gma_tail);
+
+       while (s->ip_gma != gma_tail) {
+               if (s->buf_type == RING_BUFFER_INSTRUCTION) {
+                       if (!(s->ip_gma >= rb_start) ||
+                               !(s->ip_gma < gma_bottom)) {
+                               gvt_err("ip_gma %lx out of ring scope."
+                                       "(base:0x%lx, bottom: 0x%lx)\n",
+                                       s->ip_gma, rb_start,
+                                       gma_bottom);
+                               parser_exec_state_dump(s);
+                               return -EINVAL;
+                       }
+                       if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
+                               gvt_err("ip_gma %lx out of range."
+                                       "base 0x%lx head 0x%lx tail 0x%lx\n",
+                                       s->ip_gma, rb_start,
+                                       rb_head, rb_tail);
+                               parser_exec_state_dump(s);
+                               break;
+                       }
+               }
+               ret = cmd_parser_exec(s);
+               if (ret) {
+                       gvt_err("cmd parser error\n");
+                       parser_exec_state_dump(s);
+                       break;
+               }
+       }
+
+       gvt_dbg_cmd("scan_end\n");
+
+       return ret;
+}
+
+static int scan_workload(struct intel_vgpu_workload *workload)
+{
+       unsigned long gma_head, gma_tail, gma_bottom;
+       struct parser_exec_state s;
+       int ret = 0;
+
+       /* ring base is page aligned */
+       if (WARN_ON(!IS_ALIGNED(workload->rb_start, GTT_PAGE_SIZE)))
+               return -EINVAL;
+
+       gma_head = workload->rb_start + workload->rb_head;
+       gma_tail = workload->rb_start + workload->rb_tail;
+       gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
+
+       s.buf_type = RING_BUFFER_INSTRUCTION;
+       s.buf_addr_type = GTT_BUFFER;
+       s.vgpu = workload->vgpu;
+       s.ring_id = workload->ring_id;
+       s.ring_start = workload->rb_start;
+       s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
+       s.ring_head = gma_head;
+       s.ring_tail = gma_tail;
+       s.rb_va = workload->shadow_ring_buffer_va;
+       s.workload = workload;
+
+       if (bypass_scan_mask & (1 << workload->ring_id))
+               return 0;
+
+       ret = ip_gma_set(&s, gma_head);
+       if (ret)
+               goto out;
+
+       ret = command_scan(&s, workload->rb_head, workload->rb_tail,
+               workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
+
+out:
+       return ret;
+}
+
+static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+
+       unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
+       struct parser_exec_state s;
+       int ret = 0;
+
+       /* ring base is page aligned */
+       if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
+               return -EINVAL;
+
+       ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
+       ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
+                       PAGE_SIZE);
+       gma_head = wa_ctx->indirect_ctx.guest_gma;
+       gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
+       gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
+
+       s.buf_type = RING_BUFFER_INSTRUCTION;
+       s.buf_addr_type = GTT_BUFFER;
+       s.vgpu = wa_ctx->workload->vgpu;
+       s.ring_id = wa_ctx->workload->ring_id;
+       s.ring_start = wa_ctx->indirect_ctx.guest_gma;
+       s.ring_size = ring_size;
+       s.ring_head = gma_head;
+       s.ring_tail = gma_tail;
+       s.rb_va = wa_ctx->indirect_ctx.shadow_va;
+       s.workload = wa_ctx->workload;
+
+       ret = ip_gma_set(&s, gma_head);
+       if (ret)
+               goto out;
+
+       ret = command_scan(&s, 0, ring_tail,
+               wa_ctx->indirect_ctx.guest_gma, ring_size);
+out:
+       return ret;
+}
+
+static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
+{
+       struct intel_vgpu *vgpu = workload->vgpu;
+       int ring_id = workload->ring_id;
+       struct i915_gem_context *shadow_ctx = vgpu->shadow_ctx;
+       struct intel_ring *ring = shadow_ctx->engine[ring_id].ring;
+       unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
+       unsigned int copy_len = 0;
+       int ret;
+
+       guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
+
+       /* calculate workload ring buffer size */
+       workload->rb_len = (workload->rb_tail + guest_rb_size -
+                       workload->rb_head) % guest_rb_size;
+
+       gma_head = workload->rb_start + workload->rb_head;
+       gma_tail = workload->rb_start + workload->rb_tail;
+       gma_top = workload->rb_start + guest_rb_size;
+
+       /* allocate shadow ring buffer */
+       ret = intel_ring_begin(workload->req, workload->rb_len / 4);
+       if (ret)
+               return ret;
+
+       /* get shadow ring buffer va */
+       workload->shadow_ring_buffer_va = ring->vaddr + ring->tail;
+
+       /* head > tail --> copy head <-> top */
+       if (gma_head > gma_tail) {
+               ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
+                               gma_head, gma_top,
+                               workload->shadow_ring_buffer_va);
+               if (ret) {
+                       gvt_err("fail to copy guest ring buffer\n");
+                       return ret;
+               }
+               copy_len = gma_top - gma_head;
+               gma_head = workload->rb_start;
+       }
+
+       /* copy head or start <-> tail */
+       ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
+                       gma_head, gma_tail,
+                       workload->shadow_ring_buffer_va + copy_len);
+       if (ret) {
+               gvt_err("fail to copy guest ring buffer\n");
+               return ret;
+       }
+       ring->tail += workload->rb_len;
+       intel_ring_advance(ring);
+       return 0;
+}
+
+int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
+{
+       int ret;
+
+       ret = shadow_workload_ring_buffer(workload);
+       if (ret) {
+               gvt_err("fail to shadow workload ring_buffer\n");
+               return ret;
+       }
+
+       ret = scan_workload(workload);
+       if (ret) {
+               gvt_err("scan workload error\n");
+               return ret;
+       }
+       return 0;
+}
+
+static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+       struct drm_device *dev = &wa_ctx->workload->vgpu->gvt->dev_priv->drm;
+       int ctx_size = wa_ctx->indirect_ctx.size;
+       unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
+       struct drm_i915_gem_object *obj;
+       int ret = 0;
+       void *map;
+
+       obj = i915_gem_object_create(dev,
+                                    roundup(ctx_size + CACHELINE_BYTES,
+                                            PAGE_SIZE));
+       if (IS_ERR(obj))
+               return PTR_ERR(obj);
+
+       /* get the va of the shadow batch buffer */
+       map = i915_gem_object_pin_map(obj, I915_MAP_WB);
+       if (IS_ERR(map)) {
+               gvt_err("failed to vmap shadow indirect ctx\n");
+               ret = PTR_ERR(map);
+               goto put_obj;
+       }
+
+       ret = i915_gem_object_set_to_cpu_domain(obj, false);
+       if (ret) {
+               gvt_err("failed to set shadow indirect ctx to CPU\n");
+               goto unmap_src;
+       }
+
+       ret = copy_gma_to_hva(wa_ctx->workload->vgpu,
+                               wa_ctx->workload->vgpu->gtt.ggtt_mm,
+                               guest_gma, guest_gma + ctx_size,
+                               map);
+       if (ret) {
+               gvt_err("fail to copy guest indirect ctx\n");
+               goto unmap_src;
+       }
+
+       wa_ctx->indirect_ctx.obj = obj;
+       wa_ctx->indirect_ctx.shadow_va = map;
+       return 0;
+
+unmap_src:
+       i915_gem_object_unpin_map(obj);
+put_obj:
+       i915_gem_object_put(wa_ctx->indirect_ctx.obj);
+       return ret;
+}
+
+static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+       uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
+       unsigned char *bb_start_sva;
+
+       per_ctx_start[0] = 0x18800001;
+       per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
+
+       bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
+                               wa_ctx->indirect_ctx.size;
+
+       memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
+
+       return 0;
+}
+
+int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+       int ret;
+
+       if (wa_ctx->indirect_ctx.size == 0)
+               return 0;
+
+       ret = shadow_indirect_ctx(wa_ctx);
+       if (ret) {
+               gvt_err("fail to shadow indirect ctx\n");
+               return ret;
+       }
+
+       combine_wa_ctx(wa_ctx);
+
+       ret = scan_wa_ctx(wa_ctx);
+       if (ret) {
+               gvt_err("scan wa ctx error\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
+               unsigned int opcode, int rings)
+{
+       struct cmd_info *info = NULL;
+       unsigned int ring;
+
+       for_each_set_bit(ring, (unsigned long *)&rings, I915_NUM_ENGINES) {
+               info = find_cmd_entry(gvt, opcode, ring);
+               if (info)
+                       break;
+       }
+       return info;
+}
+
+static int init_cmd_table(struct intel_gvt *gvt)
+{
+       int i;
+       struct cmd_entry *e;
+       struct cmd_info *info;
+       unsigned int gen_type;
+
+       gen_type = intel_gvt_get_device_type(gvt);
+
+       for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
+               if (!(cmd_info[i].devices & gen_type))
+                       continue;
+
+               e = kzalloc(sizeof(*e), GFP_KERNEL);
+               if (!e)
+                       return -ENOMEM;
+
+               e->info = &cmd_info[i];
+               info = find_cmd_entry_any_ring(gvt,
+                               e->info->opcode, e->info->rings);
+               if (info) {
+                       gvt_err("%s %s duplicated\n", e->info->name,
+                                       info->name);
+                       return -EEXIST;
+               }
+
+               INIT_HLIST_NODE(&e->hlist);
+               add_cmd_entry(gvt, e);
+               gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
+                               e->info->name, e->info->opcode, e->info->flag,
+                               e->info->devices, e->info->rings);
+       }
+       return 0;
+}
+
+static void clean_cmd_table(struct intel_gvt *gvt)
+{
+       struct hlist_node *tmp;
+       struct cmd_entry *e;
+       int i;
+
+       hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
+               kfree(e);
+
+       hash_init(gvt->cmd_table);
+}
+
+void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
+{
+       clean_cmd_table(gvt);
+}
+
+int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
+{
+       int ret;
+
+       ret = init_cmd_table(gvt);
+       if (ret) {
+               intel_gvt_clean_cmd_parser(gvt);
+               return ret;
+       }
+       return 0;
+}
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h b/drivers/gpu/drm/i915/gvt/cmd_parser.h
new file mode 100644 (file)
index 0000000..bed3351
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Ke Yu
+ *    Kevin Tian <kevin.tian@intel.com>
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *
+ * Contributors:
+ *    Min He <min.he@intel.com>
+ *    Ping Gao <ping.a.gao@intel.com>
+ *    Tina Zhang <tina.zhang@intel.com>
+ *    Yulei Zhang <yulei.zhang@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+#ifndef _GVT_CMD_PARSER_H_
+#define _GVT_CMD_PARSER_H_
+
+#define GVT_CMD_HASH_BITS 7
+
+void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
+
+int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
+
+int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
+
+int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
+
+#endif
index 7ef412be665fc0c585720c746d86afcb933da6c4..68cba7bd980af8cb9a855ef3ff4a4c446947ebaf 100644 (file)
 #ifndef __GVT_DEBUG_H__
 #define __GVT_DEBUG_H__
 
+#define gvt_err(fmt, args...) \
+       DRM_ERROR("gvt: "fmt, ##args)
+
 #define gvt_dbg_core(fmt, args...) \
        DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
 
-/*
- * Other GVT debug stuff will be introduced in the GVT device model patches.
- */
+#define gvt_dbg_irq(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: irq: "fmt, ##args)
+
+#define gvt_dbg_mm(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: mm: "fmt, ##args)
+
+#define gvt_dbg_mmio(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: mmio: "fmt, ##args)
+
+#define gvt_dbg_dpy(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: dpy: "fmt, ##args)
+
+#define gvt_dbg_el(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: el: "fmt, ##args)
+
+#define gvt_dbg_sched(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: sched: "fmt, ##args)
+
+#define gvt_dbg_render(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: render: "fmt, ##args)
+
+#define gvt_dbg_cmd(fmt, args...) \
+       DRM_DEBUG_DRIVER("gvt: cmd: "fmt, ##args)
 
 #endif
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
new file mode 100644 (file)
index 0000000..c0c884a
--- /dev/null
@@ -0,0 +1,330 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Ke Yu
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *
+ * Contributors:
+ *    Terrence Xu <terrence.xu@intel.com>
+ *    Changbin Du <changbin.du@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+static int get_edp_pipe(struct intel_vgpu *vgpu)
+{
+       u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
+       int pipe = -1;
+
+       switch (data & TRANS_DDI_EDP_INPUT_MASK) {
+       case TRANS_DDI_EDP_INPUT_A_ON:
+       case TRANS_DDI_EDP_INPUT_A_ONOFF:
+               pipe = PIPE_A;
+               break;
+       case TRANS_DDI_EDP_INPUT_B_ONOFF:
+               pipe = PIPE_B;
+               break;
+       case TRANS_DDI_EDP_INPUT_C_ONOFF:
+               pipe = PIPE_C;
+               break;
+       }
+       return pipe;
+}
+
+static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+       if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
+               return 0;
+
+       if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
+               return 0;
+       return 1;
+}
+
+static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+       if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
+               return -EINVAL;
+
+       if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
+               return 1;
+
+       if (edp_pipe_is_enabled(vgpu) &&
+                       get_edp_pipe(vgpu) == pipe)
+               return 1;
+       return 0;
+}
+
+/* EDID with 1024x768 as its resolution */
+static unsigned char virtual_dp_monitor_edid[] = {
+       /*Header*/
+       0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
+       /* Vendor & Product Identification */
+       0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
+       /* Version & Revision */
+       0x01, 0x04,
+       /* Basic Display Parameters & Features */
+       0xa5, 0x34, 0x20, 0x78, 0x23,
+       /* Color Characteristics */
+       0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
+       /* Established Timings: maximum resolution is 1024x768 */
+       0x21, 0x08, 0x00,
+       /* Standard Timings. All invalid */
+       0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
+       0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
+       /* 18 Byte Data Blocks 1: invalid */
+       0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
+       0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
+       /* 18 Byte Data Blocks 2: invalid */
+       0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
+       0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+       /* 18 Byte Data Blocks 3: invalid */
+       0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
+       0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
+       /* 18 Byte Data Blocks 4: invalid */
+       0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
+       0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
+       /* Extension Block Count */
+       0x00,
+       /* Checksum */
+       0xef,
+};
+
+#define DPCD_HEADER_SIZE        0xb
+
+static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
+       0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+       vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
+                       SDE_PORTC_HOTPLUG_CPT |
+                       SDE_PORTD_HOTPLUG_CPT);
+
+       if (IS_SKYLAKE(dev_priv))
+               vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
+                               SDE_PORTE_HOTPLUG_SPT);
+
+       if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B))
+               vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
+
+       if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C))
+               vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
+
+       if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D))
+               vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
+
+       if (IS_SKYLAKE(dev_priv) &&
+                       intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
+               vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
+       }
+
+       if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
+               if (IS_BROADWELL(dev_priv))
+                       vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=
+                               GEN8_PORT_DP_A_HOTPLUG;
+               else
+                       vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
+       }
+}
+
+static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
+{
+       struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
+
+       kfree(port->edid);
+       port->edid = NULL;
+
+       kfree(port->dpcd);
+       port->dpcd = NULL;
+}
+
+static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
+               int type)
+{
+       struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
+
+       port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
+       if (!port->edid)
+               return -ENOMEM;
+
+       port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
+       if (!port->dpcd) {
+               kfree(port->edid);
+               return -ENOMEM;
+       }
+
+       memcpy(port->edid->edid_block, virtual_dp_monitor_edid,
+                       EDID_SIZE);
+       port->edid->data_valid = true;
+
+       memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
+       port->dpcd->data_valid = true;
+       port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
+       port->type = type;
+
+       emulate_monitor_status_change(vgpu);
+       return 0;
+}
+
+/**
+ * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
+ * be turned on/off when a virtual pipe is enabled/disabled.
+ * @gvt: a GVT device
+ *
+ * This function is used to turn on/off vblank timer according to currently
+ * enabled/disabled virtual pipes.
+ *
+ */
+void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
+{
+       struct intel_gvt_irq *irq = &gvt->irq;
+       struct intel_vgpu *vgpu;
+       bool have_enabled_pipe = false;
+       int pipe, id;
+
+       if (WARN_ON(!mutex_is_locked(&gvt->lock)))
+               return;
+
+       hrtimer_cancel(&irq->vblank_timer.timer);
+
+       for_each_active_vgpu(gvt, vgpu, id) {
+               for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
+                       have_enabled_pipe =
+                               pipe_is_enabled(vgpu, pipe);
+                       if (have_enabled_pipe)
+                               break;
+               }
+       }
+
+       if (have_enabled_pipe)
+               hrtimer_start(&irq->vblank_timer.timer,
+                       ktime_add_ns(ktime_get(), irq->vblank_timer.period),
+                       HRTIMER_MODE_ABS);
+}
+
+static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+       struct intel_vgpu_irq *irq = &vgpu->irq;
+       int vblank_event[] = {
+               [PIPE_A] = PIPE_A_VBLANK,
+               [PIPE_B] = PIPE_B_VBLANK,
+               [PIPE_C] = PIPE_C_VBLANK,
+       };
+       int event;
+
+       if (pipe < PIPE_A || pipe > PIPE_C)
+               return;
+
+       for_each_set_bit(event, irq->flip_done_event[pipe],
+                       INTEL_GVT_EVENT_MAX) {
+               clear_bit(event, irq->flip_done_event[pipe]);
+               if (!pipe_is_enabled(vgpu, pipe))
+                       continue;
+
+               vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
+               intel_vgpu_trigger_virtual_event(vgpu, event);
+       }
+
+       if (pipe_is_enabled(vgpu, pipe)) {
+               vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
+               intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
+       }
+}
+
+static void emulate_vblank(struct intel_vgpu *vgpu)
+{
+       int pipe;
+
+       for_each_pipe(vgpu->gvt->dev_priv, pipe)
+               emulate_vblank_on_pipe(vgpu, pipe);
+}
+
+/**
+ * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
+ * @gvt: a GVT device
+ *
+ * This function is used to trigger vblank interrupts for vGPUs on GVT device
+ *
+ */
+void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
+{
+       struct intel_vgpu *vgpu;
+       int id;
+
+       if (WARN_ON(!mutex_is_locked(&gvt->lock)))
+               return;
+
+       for_each_active_vgpu(gvt, vgpu, id)
+               emulate_vblank(vgpu);
+}
+
+/**
+ * intel_vgpu_clean_display - clean vGPU virtual display emulation
+ * @vgpu: a vGPU
+ *
+ * This function is used to clean vGPU virtual display emulation stuffs
+ *
+ */
+void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+       if (IS_SKYLAKE(dev_priv))
+               clean_virtual_dp_monitor(vgpu, PORT_D);
+       else
+               clean_virtual_dp_monitor(vgpu, PORT_B);
+}
+
+/**
+ * intel_vgpu_init_display- initialize vGPU virtual display emulation
+ * @vgpu: a vGPU
+ *
+ * This function is used to initialize vGPU virtual display emulation stuffs
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ *
+ */
+int intel_vgpu_init_display(struct intel_vgpu *vgpu)
+{
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+       intel_vgpu_init_i2c_edid(vgpu);
+
+       if (IS_SKYLAKE(dev_priv))
+               return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D);
+       else
+               return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B);
+}
diff --git a/drivers/gpu/drm/i915/gvt/display.h b/drivers/gpu/drm/i915/gvt/display.h
new file mode 100644 (file)
index 0000000..7a60cb8
--- /dev/null
@@ -0,0 +1,163 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Ke Yu
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *
+ * Contributors:
+ *    Terrence Xu <terrence.xu@intel.com>
+ *    Changbin Du <changbin.du@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+
+#ifndef _GVT_DISPLAY_H_
+#define _GVT_DISPLAY_H_
+
+#define SBI_REG_MAX    20
+#define DPCD_SIZE      0x700
+
+#define intel_vgpu_port(vgpu, port) \
+       (&(vgpu->display.ports[port]))
+
+#define intel_vgpu_has_monitor_on_port(vgpu, port) \
+       (intel_vgpu_port(vgpu, port)->edid && \
+               intel_vgpu_port(vgpu, port)->edid->data_valid)
+
+#define intel_vgpu_port_is_dp(vgpu, port) \
+       ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
+       (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
+       (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
+       (intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
+
+#define INTEL_GVT_MAX_UEVENT_VARS      3
+
+/* DPCD start */
+#define DPCD_SIZE      0x700
+
+/* DPCD */
+#define DP_SET_POWER            0x600
+#define DP_SET_POWER_D0         0x1
+#define AUX_NATIVE_WRITE        0x8
+#define AUX_NATIVE_READ         0x9
+
+#define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
+#define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
+#define AUX_NATIVE_REPLY_NAK    (0x1 << 4)
+#define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
+
+#define AUX_BURST_SIZE          16
+
+/* DPCD addresses */
+#define DPCD_REV                       0x000
+#define DPCD_MAX_LINK_RATE             0x001
+#define DPCD_MAX_LANE_COUNT            0x002
+
+#define DPCD_TRAINING_PATTERN_SET      0x102
+#define        DPCD_SINK_COUNT                 0x200
+#define DPCD_LANE0_1_STATUS            0x202
+#define DPCD_LANE2_3_STATUS            0x203
+#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
+#define DPCD_SINK_STATUS               0x205
+
+/* link training */
+#define DPCD_TRAINING_PATTERN_SET_MASK 0x03
+#define DPCD_LINK_TRAINING_DISABLED    0x00
+#define DPCD_TRAINING_PATTERN_1                0x01
+#define DPCD_TRAINING_PATTERN_2                0x02
+
+#define DPCD_CP_READY_MASK             (1 << 6)
+
+/* lane status */
+#define DPCD_LANES_CR_DONE             0x11
+#define DPCD_LANES_EQ_DONE             0x22
+#define DPCD_SYMBOL_LOCKED             0x44
+
+#define DPCD_INTERLANE_ALIGN_DONE      0x01
+
+#define DPCD_SINK_IN_SYNC              0x03
+/* DPCD end */
+
+#define SBI_RESPONSE_MASK               0x3
+#define SBI_RESPONSE_SHIFT              0x1
+#define SBI_STAT_MASK                   0x1
+#define SBI_STAT_SHIFT                  0x0
+#define SBI_OPCODE_SHIFT                8
+#define SBI_OPCODE_MASK                        (0xff << SBI_OPCODE_SHIFT)
+#define SBI_CMD_IORD                    2
+#define SBI_CMD_IOWR                    3
+#define SBI_CMD_CRRD                    6
+#define SBI_CMD_CRWR                    7
+#define SBI_ADDR_OFFSET_SHIFT           16
+#define SBI_ADDR_OFFSET_MASK            (0xffff << SBI_ADDR_OFFSET_SHIFT)
+
+struct intel_vgpu_sbi_register {
+       unsigned int offset;
+       u32 value;
+};
+
+struct intel_vgpu_sbi {
+       int number;
+       struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
+};
+
+enum intel_gvt_plane_type {
+       PRIMARY_PLANE = 0,
+       CURSOR_PLANE,
+       SPRITE_PLANE,
+       MAX_PLANE
+};
+
+struct intel_vgpu_dpcd_data {
+       bool data_valid;
+       u8 data[DPCD_SIZE];
+};
+
+enum intel_vgpu_port_type {
+       GVT_CRT = 0,
+       GVT_DP_A,
+       GVT_DP_B,
+       GVT_DP_C,
+       GVT_DP_D,
+       GVT_HDMI_B,
+       GVT_HDMI_C,
+       GVT_HDMI_D,
+       GVT_PORT_MAX
+};
+
+struct intel_vgpu_port {
+       /* per display EDID information */
+       struct intel_vgpu_edid_data *edid;
+       /* per display DPCD information */
+       struct intel_vgpu_dpcd_data *dpcd;
+       int type;
+};
+
+void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
+void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);
+
+int intel_vgpu_init_display(struct intel_vgpu *vgpu);
+void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
new file mode 100644 (file)
index 0000000..7e1da1c
--- /dev/null
@@ -0,0 +1,532 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Ke Yu
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *
+ * Contributors:
+ *    Terrence Xu <terrence.xu@intel.com>
+ *    Changbin Du <changbin.du@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GMBUS1_TOTAL_BYTES_SHIFT 16
+#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
+#define gmbus1_total_byte_count(v) (((v) >> \
+       GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
+#define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
+#define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
+#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
+
+/* GMBUS0 bits definitions */
+#define _GMBUS_PIN_SEL_MASK     (0x7)
+
+static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
+{
+       struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
+       unsigned char chr = 0;
+
+       if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
+               gvt_err("Driver tries to read EDID without proper sequence!\n");
+               return 0;
+       }
+       if (edid->current_edid_read >= EDID_SIZE) {
+               gvt_err("edid_get_byte() exceeds the size of EDID!\n");
+               return 0;
+       }
+
+       if (!edid->edid_available) {
+               gvt_err("Reading EDID but EDID is not available!\n");
+               return 0;
+       }
+
+       if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
+               struct intel_vgpu_edid_data *edid_data =
+                       intel_vgpu_port(vgpu, edid->port)->edid;
+
+               chr = edid_data->edid_block[edid->current_edid_read];
+               edid->current_edid_read++;
+       } else {
+               gvt_err("No EDID available during the reading?\n");
+       }
+       return chr;
+}
+
+static inline int get_port_from_gmbus0(u32 gmbus0)
+{
+       int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
+       int port = -EINVAL;
+
+       if (port_select == 2)
+               port = PORT_E;
+       else if (port_select == 4)
+               port = PORT_C;
+       else if (port_select == 5)
+               port = PORT_B;
+       else if (port_select == 6)
+               port = PORT_D;
+       return port;
+}
+
+static void reset_gmbus_controller(struct intel_vgpu *vgpu)
+{
+       vgpu_vreg(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
+       if (!vgpu->display.i2c_edid.edid_available)
+               vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+       vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
+}
+
+/* GMBUS0 */
+static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
+                       unsigned int offset, void *p_data, unsigned int bytes)
+{
+       int port, pin_select;
+
+       memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
+
+       pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
+
+       intel_vgpu_init_i2c_edid(vgpu);
+
+       if (pin_select == 0)
+               return 0;
+
+       port = get_port_from_gmbus0(pin_select);
+       if (WARN_ON(port < 0))
+               return 0;
+
+       vgpu->display.i2c_edid.state = I2C_GMBUS;
+       vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
+
+       vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
+       vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
+
+       if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
+                       !intel_vgpu_port_is_dp(vgpu, port)) {
+               vgpu->display.i2c_edid.port = port;
+               vgpu->display.i2c_edid.edid_available = true;
+               vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
+       } else
+               vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+       return 0;
+}
+
+static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+               void *p_data, unsigned int bytes)
+{
+       struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
+       u32 slave_addr;
+       u32 wvalue = *(u32 *)p_data;
+
+       if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
+               if (!(wvalue & GMBUS_SW_CLR_INT)) {
+                       vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
+                       reset_gmbus_controller(vgpu);
+               }
+               /*
+                * TODO: "This bit is cleared to zero when an event
+                * causes the HW_RDY bit transition to occur "
+                */
+       } else {
+               /*
+                * per bspec setting this bit can cause:
+                * 1) INT status bit cleared
+                * 2) HW_RDY bit asserted
+                */
+               if (wvalue & GMBUS_SW_CLR_INT) {
+                       vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
+                       vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
+               }
+
+               /* For virtualization, we suppose that HW is always ready,
+                * so GMBUS_SW_RDY should always be cleared
+                */
+               if (wvalue & GMBUS_SW_RDY)
+                       wvalue &= ~GMBUS_SW_RDY;
+
+               i2c_edid->gmbus.total_byte_count =
+                       gmbus1_total_byte_count(wvalue);
+               slave_addr = gmbus1_slave_addr(wvalue);
+
+               /* vgpu gmbus only support EDID */
+               if (slave_addr == EDID_ADDR) {
+                       i2c_edid->slave_selected = true;
+               } else if (slave_addr != 0) {
+                       gvt_dbg_dpy(
+                               "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
+                               "       gmbus operations will be ignored.\n",
+                                       vgpu->id, slave_addr);
+               }
+
+               if (wvalue & GMBUS_CYCLE_INDEX)
+                       i2c_edid->current_edid_read =
+                               gmbus1_slave_index(wvalue);
+
+               i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
+               switch (gmbus1_bus_cycle(wvalue)) {
+               case GMBUS_NOCYCLE:
+                       break;
+               case GMBUS_STOP:
+                       /* From spec:
+                        * This can only cause a STOP to be generated
+                        * if a GMBUS cycle is generated, the GMBUS is
+                        * currently in a data/wait/idle phase, or it is in a
+                        * WAIT phase
+                        */
+                       if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
+                               != GMBUS_NOCYCLE) {
+                               intel_vgpu_init_i2c_edid(vgpu);
+                               /* After the 'stop' cycle, hw state would become
+                                * 'stop phase' and then 'idle phase' after a
+                                * few milliseconds. In emulation, we just set
+                                * it as 'idle phase' ('stop phase' is not
+                                * visible in gmbus interface)
+                                */
+                               i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
+                               vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
+                       }
+                       break;
+               case NIDX_NS_W:
+               case IDX_NS_W:
+               case NIDX_STOP:
+               case IDX_STOP:
+                       /* From hw spec the GMBUS phase
+                        * transition like this:
+                        * START (-->INDEX) -->DATA
+                        */
+                       i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
+                       vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
+                       break;
+               default:
+                       gvt_err("Unknown/reserved GMBUS cycle detected!\n");
+                       break;
+               }
+               /*
+                * From hw spec the WAIT state will be
+                * cleared:
+                * (1) in a new GMBUS cycle
+                * (2) by generating a stop
+                */
+               vgpu_vreg(vgpu, offset) = wvalue;
+       }
+       return 0;
+}
+
+static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+       void *p_data, unsigned int bytes)
+{
+       WARN_ON(1);
+       return 0;
+}
+
+static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
+               void *p_data, unsigned int bytes)
+{
+       int i;
+       unsigned char byte_data;
+       struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
+       int byte_left = i2c_edid->gmbus.total_byte_count -
+                               i2c_edid->current_edid_read;
+       int byte_count = byte_left;
+       u32 reg_data = 0;
+
+       /* Data can only be recevied if previous settings correct */
+       if (vgpu_vreg(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
+               if (byte_left <= 0) {
+                       memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
+                       return 0;
+               }
+
+               if (byte_count > 4)
+                       byte_count = 4;
+               for (i = 0; i < byte_count; i++) {
+                       byte_data = edid_get_byte(vgpu);
+                       reg_data |= (byte_data << (i << 3));
+               }
+
+               memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
+               memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
+
+               if (byte_left <= 4) {
+                       switch (i2c_edid->gmbus.cycle_type) {
+                       case NIDX_STOP:
+                       case IDX_STOP:
+                               i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
+                               break;
+                       case NIDX_NS_W:
+                       case IDX_NS_W:
+                       default:
+                               i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
+                               break;
+                       }
+                       intel_vgpu_init_i2c_edid(vgpu);
+               }
+               /*
+                * Read GMBUS3 during send operation,
+                * return the latest written value
+                */
+       } else {
+               memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
+               gvt_err("vgpu%d: warning: gmbus3 read with nothing returned\n",
+                               vgpu->id);
+       }
+       return 0;
+}
+
+static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
+               void *p_data, unsigned int bytes)
+{
+       u32 value = vgpu_vreg(vgpu, offset);
+
+       if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
+               vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
+       memcpy(p_data, (void *)&value, bytes);
+       return 0;
+}
+
+static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+               void *p_data, unsigned int bytes)
+{
+       u32 wvalue = *(u32 *)p_data;
+
+       if (wvalue & GMBUS_INUSE)
+               vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
+       /* All other bits are read-only */
+       return 0;
+}
+
+/**
+ * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
+ * @vgpu: a vGPU
+ *
+ * This function is used to emulate gmbus register mmio read
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ *
+ */
+int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
+       unsigned int offset, void *p_data, unsigned int bytes)
+{
+       if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
+               return -EINVAL;
+
+       if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+               return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
+       else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+               return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
+
+       memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
+       return 0;
+}
+
+/**
+ * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
+ * @vgpu: a vGPU
+ *
+ * This function is used to emulate gmbus register mmio write
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ *
+ */
+int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
+               return -EINVAL;
+
+       if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
+               return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
+       else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
+               return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
+       else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+               return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
+       else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+               return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
+
+       memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
+       return 0;
+}
+
+enum {
+       AUX_CH_CTL = 0,
+       AUX_CH_DATA1,
+       AUX_CH_DATA2,
+       AUX_CH_DATA3,
+       AUX_CH_DATA4,
+       AUX_CH_DATA5
+};
+
+static inline int get_aux_ch_reg(unsigned int offset)
+{
+       int reg;
+
+       switch (offset & 0xff) {
+       case 0x10:
+               reg = AUX_CH_CTL;
+               break;
+       case 0x14:
+               reg = AUX_CH_DATA1;
+               break;
+       case 0x18:
+               reg = AUX_CH_DATA2;
+               break;
+       case 0x1c:
+               reg = AUX_CH_DATA3;
+               break;
+       case 0x20:
+               reg = AUX_CH_DATA4;
+               break;
+       case 0x24:
+               reg = AUX_CH_DATA5;
+               break;
+       default:
+               reg = -1;
+               break;
+       }
+       return reg;
+}
+
+#define AUX_CTL_MSG_LENGTH(reg) \
+       ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
+               DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
+
+/**
+ * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
+ * @vgpu: a vGPU
+ *
+ * This function is used to emulate AUX channel register write
+ *
+ */
+void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
+                               int port_idx,
+                               unsigned int offset,
+                               void *p_data)
+{
+       struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
+       int msg_length, ret_msg_size;
+       int msg, addr, ctrl, op;
+       u32 value = *(u32 *)p_data;
+       int aux_data_for_write = 0;
+       int reg = get_aux_ch_reg(offset);
+
+       if (reg != AUX_CH_CTL) {
+               vgpu_vreg(vgpu, offset) = value;
+               return;
+       }
+
+       msg_length = AUX_CTL_MSG_LENGTH(value);
+       // check the msg in DATA register.
+       msg = vgpu_vreg(vgpu, offset + 4);
+       addr = (msg >> 8) & 0xffff;
+       ctrl = (msg >> 24) & 0xff;
+       op = ctrl >> 4;
+       if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
+               /* The ctl write to clear some states */
+               return;
+       }
+
+       /* Always set the wanted value for vms. */
+       ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
+       vgpu_vreg(vgpu, offset) =
+               DP_AUX_CH_CTL_DONE |
+               ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
+               DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
+
+       if (msg_length == 3) {
+               if (!(op & GVT_AUX_I2C_MOT)) {
+                       /* stop */
+                       intel_vgpu_init_i2c_edid(vgpu);
+               } else {
+                       /* start or restart */
+                       i2c_edid->aux_ch.i2c_over_aux_ch = true;
+                       i2c_edid->aux_ch.aux_ch_mot = true;
+                       if (addr == 0) {
+                               /* reset the address */
+                               intel_vgpu_init_i2c_edid(vgpu);
+                       } else if (addr == EDID_ADDR) {
+                               i2c_edid->state = I2C_AUX_CH;
+                               i2c_edid->port = port_idx;
+                               i2c_edid->slave_selected = true;
+                               if (intel_vgpu_has_monitor_on_port(vgpu,
+                                       port_idx) &&
+                                       intel_vgpu_port_is_dp(vgpu, port_idx))
+                                       i2c_edid->edid_available = true;
+                       }
+               }
+       } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
+               /* TODO
+                * We only support EDID reading from I2C_over_AUX. And
+                * we do not expect the index mode to be used. Right now
+                * the WRITE operation is ignored. It is good enough to
+                * support the gfx driver to do EDID access.
+                */
+       } else {
+               if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
+                       return;
+               if (WARN_ON(msg_length != 4))
+                       return;
+               if (i2c_edid->edid_available && i2c_edid->slave_selected) {
+                       unsigned char val = edid_get_byte(vgpu);
+
+                       aux_data_for_write = (val << 16);
+               }
+       }
+       /* write the return value in AUX_CH_DATA reg which includes:
+        * ACK of I2C_WRITE
+        * returned byte if it is READ
+        */
+
+       aux_data_for_write |= (GVT_AUX_I2C_REPLY_ACK & 0xff) << 24;
+       vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
+}
+
+/**
+ * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
+ * @vgpu: a vGPU
+ *
+ * This function is used to initialize vGPU i2c edid emulation stuffs
+ *
+ */
+void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
+{
+       struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
+
+       edid->state = I2C_NOT_SPECIFIED;
+
+       edid->port = -1;
+       edid->slave_selected = false;
+       edid->edid_available = false;
+       edid->current_edid_read = 0;
+
+       memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
+
+       edid->aux_ch.i2c_over_aux_ch = false;
+       edid->aux_ch.aux_ch_mot = false;
+}
diff --git a/drivers/gpu/drm/i915/gvt/edid.h b/drivers/gpu/drm/i915/gvt/edid.h
new file mode 100644 (file)
index 0000000..de366b1
--- /dev/null
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Ke Yu
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *
+ * Contributors:
+ *    Terrence Xu <terrence.xu@intel.com>
+ *    Changbin Du <changbin.du@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ */
+
+#ifndef _GVT_EDID_H_
+#define _GVT_EDID_H_
+
+#define EDID_SIZE              128
+#define EDID_ADDR              0x50 /* Linux hvm EDID addr */
+
+#define GVT_AUX_NATIVE_WRITE                   0x8
+#define GVT_AUX_NATIVE_READ                    0x9
+#define GVT_AUX_I2C_WRITE                      0x0
+#define GVT_AUX_I2C_READ                       0x1
+#define GVT_AUX_I2C_STATUS                     0x2
+#define GVT_AUX_I2C_MOT                                0x4
+#define GVT_AUX_I2C_REPLY_ACK                  (0x0 << 6)
+
+struct intel_vgpu_edid_data {
+       bool data_valid;
+       unsigned char edid_block[EDID_SIZE];
+};
+
+enum gmbus_cycle_type {
+       GMBUS_NOCYCLE   = 0x0,
+       NIDX_NS_W       = 0x1,
+       IDX_NS_W        = 0x3,
+       GMBUS_STOP      = 0x4,
+       NIDX_STOP       = 0x5,
+       IDX_STOP        = 0x7
+};
+
+/*
+ * States of GMBUS
+ *
+ * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
+ * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are
+ * not considered here. Below describes the usage of GMBUS registers that are
+ * cared by the EDID virtualization
+ *
+ * GMBUS0:
+ *      R/W
+ *      port selection. value of bit0 - bit2 corresponds to the GPIO registers.
+ *
+ * GMBUS1:
+ *      R/W Protect
+ *      Command and Status.
+ *      bit0 is the direction bit: 1 is read; 0 is write.
+ *      bit1 - bit7 is slave 7-bit address.
+ *      bit16 - bit24 total byte count (ignore?)
+ *
+ * GMBUS2:
+ *      Most of bits are read only except bit 15 (IN_USE)
+ *      Status register
+ *      bit0 - bit8 current byte count
+ *      bit 11: hardware ready;
+ *
+ * GMBUS3:
+ *      Read/Write
+ *      Data for transfer
+ */
+
+/* From hw specs, Other phases like START, ADDRESS, INDEX
+ * are invisible to GMBUS MMIO interface. So no definitions
+ * in below enum types
+ */
+enum gvt_gmbus_phase {
+       GMBUS_IDLE_PHASE = 0,
+       GMBUS_DATA_PHASE,
+       GMBUS_WAIT_PHASE,
+       //GMBUS_STOP_PHASE,
+       GMBUS_MAX_PHASE
+};
+
+struct intel_vgpu_i2c_gmbus {
+       unsigned int total_byte_count; /* from GMBUS1 */
+       enum gmbus_cycle_type cycle_type;
+       enum gvt_gmbus_phase phase;
+};
+
+struct intel_vgpu_i2c_aux_ch {
+       bool i2c_over_aux_ch;
+       bool aux_ch_mot;
+};
+
+enum i2c_state {
+       I2C_NOT_SPECIFIED = 0,
+       I2C_GMBUS = 1,
+       I2C_AUX_CH = 2
+};
+
+/* I2C sequences cannot interleave.
+ * GMBUS and AUX_CH sequences cannot interleave.
+ */
+struct intel_vgpu_i2c_edid {
+       enum i2c_state state;
+
+       unsigned int port;
+       bool slave_selected;
+       bool edid_available;
+       unsigned int current_edid_read;
+
+       struct intel_vgpu_i2c_gmbus gmbus;
+       struct intel_vgpu_i2c_aux_ch aux_ch;
+};
+
+void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu);
+
+int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes);
+
+int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes);
+
+void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
+               int port_idx,
+               unsigned int offset,
+               void *p_data);
+
+#endif /*_GVT_EDID_H_*/
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
new file mode 100644 (file)
index 0000000..c1f6019
--- /dev/null
@@ -0,0 +1,860 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ * Contributors:
+ *    Min He <min.he@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *    Ping Gao <ping.a.gao@intel.com>
+ *    Tina Zhang <tina.zhang@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define _EL_OFFSET_STATUS       0x234
+#define _EL_OFFSET_STATUS_BUF   0x370
+#define _EL_OFFSET_STATUS_PTR   0x3A0
+
+#define execlist_ring_mmio(gvt, ring_id, offset) \
+       (gvt->dev_priv->engine[ring_id]->mmio_base + (offset))
+
+#define valid_context(ctx) ((ctx)->valid)
+#define same_context(a, b) (((a)->context_id == (b)->context_id) && \
+               ((a)->lrca == (b)->lrca))
+
+static int context_switch_events[] = {
+       [RCS] = RCS_AS_CONTEXT_SWITCH,
+       [BCS] = BCS_AS_CONTEXT_SWITCH,
+       [VCS] = VCS_AS_CONTEXT_SWITCH,
+       [VCS2] = VCS2_AS_CONTEXT_SWITCH,
+       [VECS] = VECS_AS_CONTEXT_SWITCH,
+};
+
+static int ring_id_to_context_switch_event(int ring_id)
+{
+       if (WARN_ON(ring_id < RCS && ring_id >
+                               ARRAY_SIZE(context_switch_events)))
+               return -EINVAL;
+
+       return context_switch_events[ring_id];
+}
+
+static void switch_virtual_execlist_slot(struct intel_vgpu_execlist *execlist)
+{
+       gvt_dbg_el("[before] running slot %d/context %x pending slot %d\n",
+                       execlist->running_slot ?
+                       execlist->running_slot->index : -1,
+                       execlist->running_context ?
+                       execlist->running_context->context_id : 0,
+                       execlist->pending_slot ?
+                       execlist->pending_slot->index : -1);
+
+       execlist->running_slot = execlist->pending_slot;
+       execlist->pending_slot = NULL;
+       execlist->running_context = execlist->running_context ?
+               &execlist->running_slot->ctx[0] : NULL;
+
+       gvt_dbg_el("[after] running slot %d/context %x pending slot %d\n",
+                       execlist->running_slot ?
+                       execlist->running_slot->index : -1,
+                       execlist->running_context ?
+                       execlist->running_context->context_id : 0,
+                       execlist->pending_slot ?
+                       execlist->pending_slot->index : -1);
+}
+
+static void emulate_execlist_status(struct intel_vgpu_execlist *execlist)
+{
+       struct intel_vgpu_execlist_slot *running = execlist->running_slot;
+       struct intel_vgpu_execlist_slot *pending = execlist->pending_slot;
+       struct execlist_ctx_descriptor_format *desc = execlist->running_context;
+       struct intel_vgpu *vgpu = execlist->vgpu;
+       struct execlist_status_format status;
+       int ring_id = execlist->ring_id;
+       u32 status_reg = execlist_ring_mmio(vgpu->gvt,
+                       ring_id, _EL_OFFSET_STATUS);
+
+       status.ldw = vgpu_vreg(vgpu, status_reg);
+       status.udw = vgpu_vreg(vgpu, status_reg + 4);
+
+       if (running) {
+               status.current_execlist_pointer = !!running->index;
+               status.execlist_write_pointer = !!!running->index;
+               status.execlist_0_active = status.execlist_0_valid =
+                       !!!(running->index);
+               status.execlist_1_active = status.execlist_1_valid =
+                       !!(running->index);
+       } else {
+               status.context_id = 0;
+               status.execlist_0_active = status.execlist_0_valid = 0;
+               status.execlist_1_active = status.execlist_1_valid = 0;
+       }
+
+       status.context_id = desc ? desc->context_id : 0;
+       status.execlist_queue_full = !!(pending);
+
+       vgpu_vreg(vgpu, status_reg) = status.ldw;
+       vgpu_vreg(vgpu, status_reg + 4) = status.udw;
+
+       gvt_dbg_el("vgpu%d: status reg offset %x ldw %x udw %x\n",
+               vgpu->id, status_reg, status.ldw, status.udw);
+}
+
+static void emulate_csb_update(struct intel_vgpu_execlist *execlist,
+               struct execlist_context_status_format *status,
+               bool trigger_interrupt_later)
+{
+       struct intel_vgpu *vgpu = execlist->vgpu;
+       int ring_id = execlist->ring_id;
+       struct execlist_context_status_pointer_format ctx_status_ptr;
+       u32 write_pointer;
+       u32 ctx_status_ptr_reg, ctx_status_buf_reg, offset;
+
+       ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
+                       _EL_OFFSET_STATUS_PTR);
+       ctx_status_buf_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
+                       _EL_OFFSET_STATUS_BUF);
+
+       ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
+
+       write_pointer = ctx_status_ptr.write_ptr;
+
+       if (write_pointer == 0x7)
+               write_pointer = 0;
+       else {
+               ++write_pointer;
+               write_pointer %= 0x6;
+       }
+
+       offset = ctx_status_buf_reg + write_pointer * 8;
+
+       vgpu_vreg(vgpu, offset) = status->ldw;
+       vgpu_vreg(vgpu, offset + 4) = status->udw;
+
+       ctx_status_ptr.write_ptr = write_pointer;
+       vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
+
+       gvt_dbg_el("vgpu%d: w pointer %u reg %x csb l %x csb h %x\n",
+               vgpu->id, write_pointer, offset, status->ldw, status->udw);
+
+       if (trigger_interrupt_later)
+               return;
+
+       intel_vgpu_trigger_virtual_event(vgpu,
+                       ring_id_to_context_switch_event(execlist->ring_id));
+}
+
+static int emulate_execlist_ctx_schedule_out(
+               struct intel_vgpu_execlist *execlist,
+               struct execlist_ctx_descriptor_format *ctx)
+{
+       struct intel_vgpu_execlist_slot *running = execlist->running_slot;
+       struct intel_vgpu_execlist_slot *pending = execlist->pending_slot;
+       struct execlist_ctx_descriptor_format *ctx0 = &running->ctx[0];
+       struct execlist_ctx_descriptor_format *ctx1 = &running->ctx[1];
+       struct execlist_context_status_format status;
+
+       memset(&status, 0, sizeof(status));
+
+       gvt_dbg_el("schedule out context id %x\n", ctx->context_id);
+
+       if (WARN_ON(!same_context(ctx, execlist->running_context))) {
+               gvt_err("schedule out context is not running context,"
+                               "ctx id %x running ctx id %x\n",
+                               ctx->context_id,
+                               execlist->running_context->context_id);
+               return -EINVAL;
+       }
+
+       /* ctx1 is valid, ctx0/ctx is scheduled-out -> element switch */
+       if (valid_context(ctx1) && same_context(ctx0, ctx)) {
+               gvt_dbg_el("ctx 1 valid, ctx/ctx 0 is scheduled-out\n");
+
+               execlist->running_context = ctx1;
+
+               emulate_execlist_status(execlist);
+
+               status.context_complete = status.element_switch = 1;
+               status.context_id = ctx->context_id;
+
+               emulate_csb_update(execlist, &status, false);
+               /*
+                * ctx1 is not valid, ctx == ctx0
+                * ctx1 is valid, ctx1 == ctx
+                *      --> last element is finished
+                * emulate:
+                *      active-to-idle if there is *no* pending execlist
+                *      context-complete if there *is* pending execlist
+                */
+       } else if ((!valid_context(ctx1) && same_context(ctx0, ctx))
+                       || (valid_context(ctx1) && same_context(ctx1, ctx))) {
+               gvt_dbg_el("need to switch virtual execlist slot\n");
+
+               switch_virtual_execlist_slot(execlist);
+
+               emulate_execlist_status(execlist);
+
+               status.context_complete = status.active_to_idle = 1;
+               status.context_id = ctx->context_id;
+
+               if (!pending) {
+                       emulate_csb_update(execlist, &status, false);
+               } else {
+                       emulate_csb_update(execlist, &status, true);
+
+                       memset(&status, 0, sizeof(status));
+
+                       status.idle_to_active = 1;
+                       status.context_id = 0;
+
+                       emulate_csb_update(execlist, &status, false);
+               }
+       } else {
+               WARN_ON(1);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static struct intel_vgpu_execlist_slot *get_next_execlist_slot(
+               struct intel_vgpu_execlist *execlist)
+{
+       struct intel_vgpu *vgpu = execlist->vgpu;
+       int ring_id = execlist->ring_id;
+       u32 status_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
+                       _EL_OFFSET_STATUS);
+       struct execlist_status_format status;
+
+       status.ldw = vgpu_vreg(vgpu, status_reg);
+       status.udw = vgpu_vreg(vgpu, status_reg + 4);
+
+       if (status.execlist_queue_full) {
+               gvt_err("virtual execlist slots are full\n");
+               return NULL;
+       }
+
+       return &execlist->slot[status.execlist_write_pointer];
+}
+
+static int emulate_execlist_schedule_in(struct intel_vgpu_execlist *execlist,
+               struct execlist_ctx_descriptor_format ctx[2])
+{
+       struct intel_vgpu_execlist_slot *running = execlist->running_slot;
+       struct intel_vgpu_execlist_slot *slot =
+               get_next_execlist_slot(execlist);
+
+       struct execlist_ctx_descriptor_format *ctx0, *ctx1;
+       struct execlist_context_status_format status;
+
+       gvt_dbg_el("emulate schedule-in\n");
+
+       if (!slot) {
+               gvt_err("no available execlist slot\n");
+               return -EINVAL;
+       }
+
+       memset(&status, 0, sizeof(status));
+       memset(slot->ctx, 0, sizeof(slot->ctx));
+
+       slot->ctx[0] = ctx[0];
+       slot->ctx[1] = ctx[1];
+
+       gvt_dbg_el("alloc slot index %d ctx 0 %x ctx 1 %x\n",
+                       slot->index, ctx[0].context_id,
+                       ctx[1].context_id);
+
+       /*
+        * no running execlist, make this write bundle as running execlist
+        * -> idle-to-active
+        */
+       if (!running) {
+               gvt_dbg_el("no current running execlist\n");
+
+               execlist->running_slot = slot;
+               execlist->pending_slot = NULL;
+               execlist->running_context = &slot->ctx[0];
+
+               gvt_dbg_el("running slot index %d running context %x\n",
+                               execlist->running_slot->index,
+                               execlist->running_context->context_id);
+
+               emulate_execlist_status(execlist);
+
+               status.idle_to_active = 1;
+               status.context_id = 0;
+
+               emulate_csb_update(execlist, &status, false);
+               return 0;
+       }
+
+       ctx0 = &running->ctx[0];
+       ctx1 = &running->ctx[1];
+
+       gvt_dbg_el("current running slot index %d ctx 0 %x ctx 1 %x\n",
+               running->index, ctx0->context_id, ctx1->context_id);
+
+       /*
+        * already has an running execlist
+        *      a. running ctx1 is valid,
+        *         ctx0 is finished, and running ctx1 == new execlist ctx[0]
+        *      b. running ctx1 is not valid,
+        *         ctx0 == new execlist ctx[0]
+        * ----> lite-restore + preempted
+        */
+       if ((valid_context(ctx1) && same_context(ctx1, &slot->ctx[0]) &&
+               /* condition a */
+               (!same_context(ctx0, execlist->running_context))) ||
+                       (!valid_context(ctx1) &&
+                        same_context(ctx0, &slot->ctx[0]))) { /* condition b */
+               gvt_dbg_el("need to switch virtual execlist slot\n");
+
+               execlist->pending_slot = slot;
+               switch_virtual_execlist_slot(execlist);
+
+               emulate_execlist_status(execlist);
+
+               status.lite_restore = status.preempted = 1;
+               status.context_id = ctx[0].context_id;
+
+               emulate_csb_update(execlist, &status, false);
+       } else {
+               gvt_dbg_el("emulate as pending slot\n");
+               /*
+                * otherwise
+                * --> emulate pending execlist exist + but no preemption case
+                */
+               execlist->pending_slot = slot;
+               emulate_execlist_status(execlist);
+       }
+       return 0;
+}
+
+static void free_workload(struct intel_vgpu_workload *workload)
+{
+       intel_vgpu_unpin_mm(workload->shadow_mm);
+       intel_gvt_mm_unreference(workload->shadow_mm);
+       kmem_cache_free(workload->vgpu->workloads, workload);
+}
+
+#define get_desc_from_elsp_dwords(ed, i) \
+       ((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))
+
+
+#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
+#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
+static int set_gma_to_bb_cmd(struct intel_shadow_bb_entry *entry_obj,
+                            unsigned long add, int gmadr_bytes)
+{
+       if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
+               return -1;
+
+       *((u32 *)(entry_obj->bb_start_cmd_va + (1 << 2))) = add &
+               BATCH_BUFFER_ADDR_MASK;
+       if (gmadr_bytes == 8) {
+               *((u32 *)(entry_obj->bb_start_cmd_va + (2 << 2))) =
+                       add & BATCH_BUFFER_ADDR_HIGH_MASK;
+       }
+
+       return 0;
+}
+
+static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
+{
+       int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
+
+       /* pin the gem object to ggtt */
+       if (!list_empty(&workload->shadow_bb)) {
+               struct intel_shadow_bb_entry *entry_obj =
+                       list_first_entry(&workload->shadow_bb,
+                                        struct intel_shadow_bb_entry,
+                                        list);
+               struct intel_shadow_bb_entry *temp;
+
+               list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
+                               list) {
+                       struct i915_vma *vma;
+
+                       vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0,
+                                                      4, 0);
+                       if (IS_ERR(vma)) {
+                               gvt_err("Cannot pin\n");
+                               return;
+                       }
+
+                       /* FIXME: we are not tracking our pinned VMA leaving it
+                        * up to the core to fix up the stray pin_count upon
+                        * free.
+                        */
+
+                       /* update the relocate gma with shadow batch buffer*/
+                       set_gma_to_bb_cmd(entry_obj,
+                                         i915_ggtt_offset(vma),
+                                         gmadr_bytes);
+               }
+       }
+}
+
+static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+       int ring_id = wa_ctx->workload->ring_id;
+       struct i915_gem_context *shadow_ctx =
+               wa_ctx->workload->vgpu->shadow_ctx;
+       struct drm_i915_gem_object *ctx_obj =
+               shadow_ctx->engine[ring_id].state->obj;
+       struct execlist_ring_context *shadow_ring_context;
+       struct page *page;
+
+       page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
+       shadow_ring_context = kmap_atomic(page);
+
+       shadow_ring_context->bb_per_ctx_ptr.val =
+               (shadow_ring_context->bb_per_ctx_ptr.val &
+               (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
+       shadow_ring_context->rcs_indirect_ctx.val =
+               (shadow_ring_context->rcs_indirect_ctx.val &
+               (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
+
+       kunmap_atomic(shadow_ring_context);
+       return 0;
+}
+
+static void prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+       struct i915_vma *vma;
+       unsigned char *per_ctx_va =
+               (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
+               wa_ctx->indirect_ctx.size;
+
+       if (wa_ctx->indirect_ctx.size == 0)
+               return;
+
+       vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
+                                      0, CACHELINE_BYTES, 0);
+       if (IS_ERR(vma)) {
+               gvt_err("Cannot pin indirect ctx obj\n");
+               return;
+       }
+
+       /* FIXME: we are not tracking our pinned VMA leaving it
+        * up to the core to fix up the stray pin_count upon
+        * free.
+        */
+
+       wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
+
+       wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
+       memset(per_ctx_va, 0, CACHELINE_BYTES);
+
+       update_wa_ctx_2_shadow_ctx(wa_ctx);
+}
+
+static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
+{
+       struct intel_vgpu *vgpu = workload->vgpu;
+       struct execlist_ctx_descriptor_format ctx[2];
+       int ring_id = workload->ring_id;
+
+       intel_vgpu_pin_mm(workload->shadow_mm);
+       intel_vgpu_sync_oos_pages(workload->vgpu);
+       intel_vgpu_flush_post_shadow(workload->vgpu);
+       prepare_shadow_batch_buffer(workload);
+       prepare_shadow_wa_ctx(&workload->wa_ctx);
+       if (!workload->emulate_schedule_in)
+               return 0;
+
+       ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
+       ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0);
+
+       return emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx);
+}
+
+static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
+{
+       /* release all the shadow batch buffer */
+       if (!list_empty(&workload->shadow_bb)) {
+               struct intel_shadow_bb_entry *entry_obj =
+                       list_first_entry(&workload->shadow_bb,
+                                        struct intel_shadow_bb_entry,
+                                        list);
+               struct intel_shadow_bb_entry *temp;
+
+               list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
+                                        list) {
+                       i915_gem_object_unpin_map(entry_obj->obj);
+                       i915_gem_object_put(entry_obj->obj);
+                       list_del(&entry_obj->list);
+                       kfree(entry_obj);
+               }
+       }
+}
+
+static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+       if (wa_ctx->indirect_ctx.size == 0)
+               return;
+
+       i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
+       i915_gem_object_put(wa_ctx->indirect_ctx.obj);
+}
+
+static int complete_execlist_workload(struct intel_vgpu_workload *workload)
+{
+       struct intel_vgpu *vgpu = workload->vgpu;
+       struct intel_vgpu_execlist *execlist =
+               &vgpu->execlist[workload->ring_id];
+       struct intel_vgpu_workload *next_workload;
+       struct list_head *next = workload_q_head(vgpu, workload->ring_id)->next;
+       bool lite_restore = false;
+       int ret;
+
+       gvt_dbg_el("complete workload %p status %d\n", workload,
+                       workload->status);
+
+       release_shadow_batch_buffer(workload);
+       release_shadow_wa_ctx(&workload->wa_ctx);
+
+       if (workload->status || vgpu->resetting)
+               goto out;
+
+       if (!list_empty(workload_q_head(vgpu, workload->ring_id))) {
+               struct execlist_ctx_descriptor_format *this_desc, *next_desc;
+
+               next_workload = container_of(next,
+                               struct intel_vgpu_workload, list);
+               this_desc = &workload->ctx_desc;
+               next_desc = &next_workload->ctx_desc;
+
+               lite_restore = same_context(this_desc, next_desc);
+       }
+
+       if (lite_restore) {
+               gvt_dbg_el("next context == current - no schedule-out\n");
+               free_workload(workload);
+               return 0;
+       }
+
+       ret = emulate_execlist_ctx_schedule_out(execlist, &workload->ctx_desc);
+       if (ret)
+               goto err;
+out:
+       free_workload(workload);
+       return 0;
+err:
+       free_workload(workload);
+       return ret;
+}
+
+#define RING_CTX_OFF(x) \
+       offsetof(struct execlist_ring_context, x)
+
+static void read_guest_pdps(struct intel_vgpu *vgpu,
+               u64 ring_context_gpa, u32 pdp[8])
+{
+       u64 gpa;
+       int i;
+
+       gpa = ring_context_gpa + RING_CTX_OFF(pdp3_UDW.val);
+
+       for (i = 0; i < 8; i++)
+               intel_gvt_hypervisor_read_gpa(vgpu,
+                               gpa + i * 8, &pdp[7 - i], 4);
+}
+
+static int prepare_mm(struct intel_vgpu_workload *workload)
+{
+       struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
+       struct intel_vgpu_mm *mm;
+       int page_table_level;
+       u32 pdp[8];
+
+       if (desc->addressing_mode == 1) { /* legacy 32-bit */
+               page_table_level = 3;
+       } else if (desc->addressing_mode == 3) { /* legacy 64 bit */
+               page_table_level = 4;
+       } else {
+               gvt_err("Advanced Context mode(SVM) is not supported!\n");
+               return -EINVAL;
+       }
+
+       read_guest_pdps(workload->vgpu, workload->ring_context_gpa, pdp);
+
+       mm = intel_vgpu_find_ppgtt_mm(workload->vgpu, page_table_level, pdp);
+       if (mm) {
+               intel_gvt_mm_reference(mm);
+       } else {
+
+               mm = intel_vgpu_create_mm(workload->vgpu, INTEL_GVT_MM_PPGTT,
+                               pdp, page_table_level, 0);
+               if (IS_ERR(mm)) {
+                       gvt_err("fail to create mm object.\n");
+                       return PTR_ERR(mm);
+               }
+       }
+       workload->shadow_mm = mm;
+       return 0;
+}
+
+#define get_last_workload(q) \
+       (list_empty(q) ? NULL : container_of(q->prev, \
+       struct intel_vgpu_workload, list))
+
+static int submit_context(struct intel_vgpu *vgpu, int ring_id,
+               struct execlist_ctx_descriptor_format *desc,
+               bool emulate_schedule_in)
+{
+       struct list_head *q = workload_q_head(vgpu, ring_id);
+       struct intel_vgpu_workload *last_workload = get_last_workload(q);
+       struct intel_vgpu_workload *workload = NULL;
+       u64 ring_context_gpa;
+       u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
+       int ret;
+
+       ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
+                       (u32)((desc->lrca + 1) << GTT_PAGE_SHIFT));
+       if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
+               gvt_err("invalid guest context LRCA: %x\n", desc->lrca);
+               return -EINVAL;
+       }
+
+       intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(ring_header.val), &head, 4);
+
+       intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(ring_tail.val), &tail, 4);
+
+       head &= RB_HEAD_OFF_MASK;
+       tail &= RB_TAIL_OFF_MASK;
+
+       if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
+               gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
+               gvt_dbg_el("ctx head %x real head %lx\n", head,
+                               last_workload->rb_tail);
+               /*
+                * cannot use guest context head pointer here,
+                * as it might not be updated at this time
+                */
+               head = last_workload->rb_tail;
+       }
+
+       gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
+
+       workload = kmem_cache_zalloc(vgpu->workloads, GFP_KERNEL);
+       if (!workload)
+               return -ENOMEM;
+
+       /* record some ring buffer register values for scan and shadow */
+       intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(rb_start.val), &start, 4);
+       intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
+       intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
+
+       INIT_LIST_HEAD(&workload->list);
+       INIT_LIST_HEAD(&workload->shadow_bb);
+
+       init_waitqueue_head(&workload->shadow_ctx_status_wq);
+       atomic_set(&workload->shadow_ctx_active, 0);
+
+       workload->vgpu = vgpu;
+       workload->ring_id = ring_id;
+       workload->ctx_desc = *desc;
+       workload->ring_context_gpa = ring_context_gpa;
+       workload->rb_head = head;
+       workload->rb_tail = tail;
+       workload->rb_start = start;
+       workload->rb_ctl = ctl;
+       workload->prepare = prepare_execlist_workload;
+       workload->complete = complete_execlist_workload;
+       workload->status = -EINPROGRESS;
+       workload->emulate_schedule_in = emulate_schedule_in;
+
+       if (ring_id == RCS) {
+               intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
+               intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
+                       RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
+
+               workload->wa_ctx.indirect_ctx.guest_gma =
+                       indirect_ctx & INDIRECT_CTX_ADDR_MASK;
+               workload->wa_ctx.indirect_ctx.size =
+                       (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
+                       CACHELINE_BYTES;
+               workload->wa_ctx.per_ctx.guest_gma =
+                       per_ctx & PER_CTX_ADDR_MASK;
+               workload->wa_ctx.workload = workload;
+
+               WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
+       }
+
+       if (emulate_schedule_in)
+               memcpy(&workload->elsp_dwords,
+                               &vgpu->execlist[ring_id].elsp_dwords,
+                               sizeof(workload->elsp_dwords));
+
+       gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
+                       workload, ring_id, head, tail, start, ctl);
+
+       gvt_dbg_el("workload %p emulate schedule_in %d\n", workload,
+                       emulate_schedule_in);
+
+       ret = prepare_mm(workload);
+       if (ret) {
+               kmem_cache_free(vgpu->workloads, workload);
+               return ret;
+       }
+
+       queue_workload(workload);
+       return 0;
+}
+
+int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id)
+{
+       struct intel_vgpu_execlist *execlist = &vgpu->execlist[ring_id];
+       struct execlist_ctx_descriptor_format *desc[2], valid_desc[2];
+       unsigned long valid_desc_bitmap = 0;
+       bool emulate_schedule_in = true;
+       int ret;
+       int i;
+
+       memset(valid_desc, 0, sizeof(valid_desc));
+
+       desc[0] = get_desc_from_elsp_dwords(&execlist->elsp_dwords, 1);
+       desc[1] = get_desc_from_elsp_dwords(&execlist->elsp_dwords, 0);
+
+       for (i = 0; i < 2; i++) {
+               if (!desc[i]->valid)
+                       continue;
+
+               if (!desc[i]->privilege_access) {
+                       gvt_err("vgpu%d: unexpected GGTT elsp submission\n",
+                                       vgpu->id);
+                       return -EINVAL;
+               }
+
+               /* TODO: add another guest context checks here. */
+               set_bit(i, &valid_desc_bitmap);
+               valid_desc[i] = *desc[i];
+       }
+
+       if (!valid_desc_bitmap) {
+               gvt_err("vgpu%d: no valid desc in a elsp submission\n",
+                               vgpu->id);
+               return -EINVAL;
+       }
+
+       if (!test_bit(0, (void *)&valid_desc_bitmap) &&
+                       test_bit(1, (void *)&valid_desc_bitmap)) {
+               gvt_err("vgpu%d: weird elsp submission, desc 0 is not valid\n",
+                               vgpu->id);
+               return -EINVAL;
+       }
+
+       /* submit workload */
+       for_each_set_bit(i, (void *)&valid_desc_bitmap, 2) {
+               ret = submit_context(vgpu, ring_id, &valid_desc[i],
+                               emulate_schedule_in);
+               if (ret) {
+                       gvt_err("vgpu%d: fail to schedule workload\n",
+                                       vgpu->id);
+                       return ret;
+               }
+               emulate_schedule_in = false;
+       }
+       return 0;
+}
+
+static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id)
+{
+       struct intel_vgpu_execlist *execlist = &vgpu->execlist[ring_id];
+       struct execlist_context_status_pointer_format ctx_status_ptr;
+       u32 ctx_status_ptr_reg;
+
+       memset(execlist, 0, sizeof(*execlist));
+
+       execlist->vgpu = vgpu;
+       execlist->ring_id = ring_id;
+       execlist->slot[0].index = 0;
+       execlist->slot[1].index = 1;
+
+       ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
+                       _EL_OFFSET_STATUS_PTR);
+
+       ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
+       ctx_status_ptr.read_ptr = ctx_status_ptr.write_ptr = 0x7;
+       vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
+}
+
+void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu)
+{
+       kmem_cache_destroy(vgpu->workloads);
+}
+
+int intel_vgpu_init_execlist(struct intel_vgpu *vgpu)
+{
+       enum intel_engine_id i;
+       struct intel_engine_cs *engine;
+
+       /* each ring has a virtual execlist engine */
+       for_each_engine(engine, vgpu->gvt->dev_priv, i) {
+               init_vgpu_execlist(vgpu, i);
+               INIT_LIST_HEAD(&vgpu->workload_q_head[i]);
+       }
+
+       vgpu->workloads = kmem_cache_create("gvt-g vgpu workload",
+                       sizeof(struct intel_vgpu_workload), 0,
+                       SLAB_HWCACHE_ALIGN,
+                       NULL);
+
+       if (!vgpu->workloads)
+               return -ENOMEM;
+
+       return 0;
+}
+
+void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
+               unsigned long ring_bitmap)
+{
+       int bit;
+       struct list_head *pos, *n;
+       struct intel_vgpu_workload *workload = NULL;
+
+       for_each_set_bit(bit, &ring_bitmap, sizeof(ring_bitmap) * 8) {
+               if (bit >= I915_NUM_ENGINES)
+                       break;
+               /* free the unsubmited workload in the queue */
+               list_for_each_safe(pos, n, &vgpu->workload_q_head[bit]) {
+                       workload = container_of(pos,
+                                       struct intel_vgpu_workload, list);
+                       list_del_init(&workload->list);
+                       free_workload(workload);
+               }
+
+               init_vgpu_execlist(vgpu, bit);
+       }
+}
diff --git a/drivers/gpu/drm/i915/gvt/execlist.h b/drivers/gpu/drm/i915/gvt/execlist.h
new file mode 100644 (file)
index 0000000..635f31c
--- /dev/null
@@ -0,0 +1,188 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Zhiyuan Lv <zhiyuan.lv@intel.com>
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ * Contributors:
+ *    Min He <min.he@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *    Ping Gao <ping.a.gao@intel.com>
+ *    Tina Zhang <tina.zhang@intel.com>
+ *
+ */
+
+#ifndef _GVT_EXECLIST_H_
+#define _GVT_EXECLIST_H_
+
+struct execlist_ctx_descriptor_format {
+       union {
+               u32 udw;
+               u32 context_id;
+       };
+       union {
+               u32 ldw;
+               struct {
+                       u32 valid                  : 1;
+                       u32 force_pd_restore       : 1;
+                       u32 force_restore          : 1;
+                       u32 addressing_mode        : 2;
+                       u32 llc_coherency          : 1;
+                       u32 fault_handling         : 2;
+                       u32 privilege_access       : 1;
+                       u32 reserved               : 3;
+                       u32 lrca                   : 20;
+               };
+       };
+};
+
+struct execlist_status_format {
+       union {
+               u32 ldw;
+               struct {
+                       u32 current_execlist_pointer       :1;
+                       u32 execlist_write_pointer         :1;
+                       u32 execlist_queue_full            :1;
+                       u32 execlist_1_valid               :1;
+                       u32 execlist_0_valid               :1;
+                       u32 last_ctx_switch_reason         :9;
+                       u32 current_active_elm_status      :2;
+                       u32 arbitration_enable             :1;
+                       u32 execlist_1_active              :1;
+                       u32 execlist_0_active              :1;
+                       u32 reserved                       :13;
+               };
+       };
+       union {
+               u32 udw;
+               u32 context_id;
+       };
+};
+
+struct execlist_context_status_pointer_format {
+       union {
+               u32 dw;
+               struct {
+                       u32 write_ptr              :3;
+                       u32 reserved               :5;
+                       u32 read_ptr               :3;
+                       u32 reserved2              :5;
+                       u32 mask                   :16;
+               };
+       };
+};
+
+struct execlist_context_status_format {
+       union {
+               u32 ldw;
+               struct {
+                       u32 idle_to_active         :1;
+                       u32 preempted              :1;
+                       u32 element_switch         :1;
+                       u32 active_to_idle         :1;
+                       u32 context_complete       :1;
+                       u32 wait_on_sync_flip      :1;
+                       u32 wait_on_vblank         :1;
+                       u32 wait_on_semaphore      :1;
+                       u32 wait_on_scanline       :1;
+                       u32 reserved               :2;
+                       u32 semaphore_wait_mode    :1;
+                       u32 display_plane          :3;
+                       u32 lite_restore           :1;
+                       u32 reserved_2             :16;
+               };
+       };
+       union {
+               u32 udw;
+               u32 context_id;
+       };
+};
+
+struct execlist_mmio_pair {
+       u32 addr;
+       u32 val;
+};
+
+/* The first 52 dwords in register state context */
+struct execlist_ring_context {
+       u32 nop1;
+       u32 lri_cmd_1;
+       struct execlist_mmio_pair ctx_ctrl;
+       struct execlist_mmio_pair ring_header;
+       struct execlist_mmio_pair ring_tail;
+       struct execlist_mmio_pair rb_start;
+       struct execlist_mmio_pair rb_ctrl;
+       struct execlist_mmio_pair bb_cur_head_UDW;
+       struct execlist_mmio_pair bb_cur_head_LDW;
+       struct execlist_mmio_pair bb_state;
+       struct execlist_mmio_pair second_bb_addr_UDW;
+       struct execlist_mmio_pair second_bb_addr_LDW;
+       struct execlist_mmio_pair second_bb_state;
+       struct execlist_mmio_pair bb_per_ctx_ptr;
+       struct execlist_mmio_pair rcs_indirect_ctx;
+       struct execlist_mmio_pair rcs_indirect_ctx_offset;
+       u32 nop2;
+       u32 nop3;
+       u32 nop4;
+       u32 lri_cmd_2;
+       struct execlist_mmio_pair ctx_timestamp;
+       struct execlist_mmio_pair pdp3_UDW;
+       struct execlist_mmio_pair pdp3_LDW;
+       struct execlist_mmio_pair pdp2_UDW;
+       struct execlist_mmio_pair pdp2_LDW;
+       struct execlist_mmio_pair pdp1_UDW;
+       struct execlist_mmio_pair pdp1_LDW;
+       struct execlist_mmio_pair pdp0_UDW;
+       struct execlist_mmio_pair pdp0_LDW;
+};
+
+struct intel_vgpu_elsp_dwords {
+       u32 data[4];
+       u32 index;
+};
+
+struct intel_vgpu_execlist_slot {
+       struct execlist_ctx_descriptor_format ctx[2];
+       u32 index;
+};
+
+struct intel_vgpu_execlist {
+       struct intel_vgpu_execlist_slot slot[2];
+       struct intel_vgpu_execlist_slot *running_slot;
+       struct intel_vgpu_execlist_slot *pending_slot;
+       struct execlist_ctx_descriptor_format *running_context;
+       int ring_id;
+       struct intel_vgpu *vgpu;
+       struct intel_vgpu_elsp_dwords elsp_dwords;
+};
+
+void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu);
+
+int intel_vgpu_init_execlist(struct intel_vgpu *vgpu);
+
+int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id);
+
+void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
+               unsigned long ring_bitmap);
+
+#endif /*_GVT_EXECLIST_H_*/
diff --git a/drivers/gpu/drm/i915/gvt/firmware.c b/drivers/gpu/drm/i915/gvt/firmware.c
new file mode 100644 (file)
index 0000000..2fae2a2
--- /dev/null
@@ -0,0 +1,312 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *
+ * Contributors:
+ *    Changbin Du <changbin.du@intel.com>
+ *
+ */
+
+#include <linux/firmware.h>
+#include <linux/crc32.h>
+
+#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
+
+#define FIRMWARE_VERSION (0x0)
+
+struct gvt_firmware_header {
+       u64 magic;
+       u32 crc32;              /* protect the data after this field */
+       u32 version;
+       u64 cfg_space_size;
+       u64 cfg_space_offset;   /* offset in the file */
+       u64 mmio_size;
+       u64 mmio_offset;        /* offset in the file */
+       unsigned char data[1];
+};
+
+#define RD(offset) (readl(mmio + offset.reg))
+#define WR(v, offset) (writel(v, mmio + offset.reg))
+
+static void bdw_forcewake_get(void __iomem *mmio)
+{
+       WR(_MASKED_BIT_DISABLE(0xffff), FORCEWAKE_MT);
+
+       RD(ECOBUS);
+
+       if (wait_for((RD(FORCEWAKE_ACK_HSW) & FORCEWAKE_KERNEL) == 0, 50))
+               gvt_err("fail to wait forcewake idle\n");
+
+       WR(_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL), FORCEWAKE_MT);
+
+       if (wait_for((RD(FORCEWAKE_ACK_HSW) & FORCEWAKE_KERNEL), 50))
+               gvt_err("fail to wait forcewake ack\n");
+
+       if (wait_for((RD(GEN6_GT_THREAD_STATUS_REG) &
+                     GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 50))
+               gvt_err("fail to wait c0 wake up\n");
+}
+
+#undef RD
+#undef WR
+
+#define dev_to_drm_minor(d) dev_get_drvdata((d))
+
+static ssize_t
+gvt_firmware_read(struct file *filp, struct kobject *kobj,
+            struct bin_attribute *attr, char *buf,
+            loff_t offset, size_t count)
+{
+       memcpy(buf, attr->private + offset, count);
+       return count;
+}
+
+static struct bin_attribute firmware_attr = {
+       .attr = {.name = "gvt_firmware", .mode = (S_IRUSR)},
+       .read = gvt_firmware_read,
+       .write = NULL,
+       .mmap = NULL,
+};
+
+static int expose_firmware_sysfs(struct intel_gvt *gvt,
+                                       void __iomem *mmio)
+{
+       struct intel_gvt_device_info *info = &gvt->device_info;
+       struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
+       struct intel_gvt_mmio_info *e;
+       struct gvt_firmware_header *h;
+       void *firmware;
+       void *p;
+       unsigned long size;
+       int i;
+       int ret;
+
+       size = sizeof(*h) + info->mmio_size + info->cfg_space_size - 1;
+       firmware = vmalloc(size);
+       if (!firmware)
+               return -ENOMEM;
+
+       h = firmware;
+
+       h->magic = VGT_MAGIC;
+       h->version = FIRMWARE_VERSION;
+       h->cfg_space_size = info->cfg_space_size;
+       h->cfg_space_offset = offsetof(struct gvt_firmware_header, data);
+       h->mmio_size = info->mmio_size;
+       h->mmio_offset = h->cfg_space_offset + h->cfg_space_size;
+
+       p = firmware + h->cfg_space_offset;
+
+       for (i = 0; i < h->cfg_space_size; i += 4)
+               pci_read_config_dword(pdev, i, p + i);
+
+       memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size);
+
+       p = firmware + h->mmio_offset;
+
+       hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
+               int j;
+
+               for (j = 0; j < e->length; j += 4)
+                       *(u32 *)(p + e->offset + j) =
+                               readl(mmio + e->offset + j);
+       }
+
+       memcpy(gvt->firmware.mmio, p, info->mmio_size);
+
+       firmware_attr.size = size;
+       firmware_attr.private = firmware;
+
+       ret = device_create_bin_file(&pdev->dev, &firmware_attr);
+       if (ret) {
+               vfree(firmware);
+               return ret;
+       }
+       return 0;
+}
+
+static void clean_firmware_sysfs(struct intel_gvt *gvt)
+{
+       struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
+
+       device_remove_bin_file(&pdev->dev, &firmware_attr);
+       vfree(firmware_attr.private);
+}
+
+/**
+ * intel_gvt_free_firmware - free GVT firmware
+ * @gvt: intel gvt device
+ *
+ */
+void intel_gvt_free_firmware(struct intel_gvt *gvt)
+{
+       if (!gvt->firmware.firmware_loaded)
+               clean_firmware_sysfs(gvt);
+
+       kfree(gvt->firmware.cfg_space);
+       kfree(gvt->firmware.mmio);
+}
+
+static int verify_firmware(struct intel_gvt *gvt,
+                          const struct firmware *fw)
+{
+       struct intel_gvt_device_info *info = &gvt->device_info;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       struct pci_dev *pdev = dev_priv->drm.pdev;
+       struct gvt_firmware_header *h;
+       unsigned long id, crc32_start;
+       const void *mem;
+       const char *item;
+       u64 file, request;
+
+       h = (struct gvt_firmware_header *)fw->data;
+
+       crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
+       mem = fw->data + crc32_start;
+
+#define VERIFY(s, a, b) do { \
+       item = (s); file = (u64)(a); request = (u64)(b); \
+       if ((a) != (b)) \
+               goto invalid_firmware; \
+} while (0)
+
+       VERIFY("magic number", h->magic, VGT_MAGIC);
+       VERIFY("version", h->version, FIRMWARE_VERSION);
+       VERIFY("crc32", h->crc32, crc32_le(0, mem, fw->size - crc32_start));
+       VERIFY("cfg space size", h->cfg_space_size, info->cfg_space_size);
+       VERIFY("mmio size", h->mmio_size, info->mmio_size);
+
+       mem = (fw->data + h->cfg_space_offset);
+
+       id = *(u16 *)(mem + PCI_VENDOR_ID);
+       VERIFY("vender id", id, pdev->vendor);
+
+       id = *(u16 *)(mem + PCI_DEVICE_ID);
+       VERIFY("device id", id, pdev->device);
+
+       id = *(u8 *)(mem + PCI_REVISION_ID);
+       VERIFY("revision id", id, pdev->revision);
+
+#undef VERIFY
+       return 0;
+
+invalid_firmware:
+       gvt_dbg_core("Invalid firmware: %s [file] 0x%llx [request] 0x%llx\n",
+                    item, file, request);
+       return -EINVAL;
+}
+
+#define GVT_FIRMWARE_PATH "i915/gvt"
+
+/**
+ * intel_gvt_load_firmware - load GVT firmware
+ * @gvt: intel gvt device
+ *
+ */
+int intel_gvt_load_firmware(struct intel_gvt *gvt)
+{
+       struct intel_gvt_device_info *info = &gvt->device_info;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       struct pci_dev *pdev = dev_priv->drm.pdev;
+       struct intel_gvt_firmware *firmware = &gvt->firmware;
+       struct gvt_firmware_header *h;
+       const struct firmware *fw;
+       char *path;
+       void __iomem *mmio;
+       void *mem;
+       int ret;
+
+       path = kmalloc(PATH_MAX, GFP_KERNEL);
+       if (!path)
+               return -ENOMEM;
+
+       mem = kmalloc(info->cfg_space_size, GFP_KERNEL);
+       if (!mem) {
+               kfree(path);
+               return -ENOMEM;
+       }
+
+       firmware->cfg_space = mem;
+
+       mem = kmalloc(info->mmio_size, GFP_KERNEL);
+       if (!mem) {
+               kfree(path);
+               kfree(firmware->cfg_space);
+               return -ENOMEM;
+       }
+
+       firmware->mmio = mem;
+
+       mmio = pci_iomap(pdev, info->mmio_bar, info->mmio_size);
+       if (!mmio) {
+               kfree(path);
+               kfree(firmware->cfg_space);
+               kfree(firmware->mmio);
+               return -EINVAL;
+       }
+
+       if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv))
+               bdw_forcewake_get(mmio);
+
+       sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%04x.golden_hw_state",
+                GVT_FIRMWARE_PATH, pdev->vendor, pdev->device,
+                pdev->revision);
+
+       gvt_dbg_core("request hw state firmware %s...\n", path);
+
+       ret = request_firmware(&fw, path, &dev_priv->drm.pdev->dev);
+       kfree(path);
+
+       if (ret)
+               goto expose_firmware;
+
+       gvt_dbg_core("success.\n");
+
+       ret = verify_firmware(gvt, fw);
+       if (ret)
+               goto out_free_fw;
+
+       gvt_dbg_core("verified.\n");
+
+       h = (struct gvt_firmware_header *)fw->data;
+
+       memcpy(firmware->cfg_space, fw->data + h->cfg_space_offset,
+              h->cfg_space_size);
+       memcpy(firmware->mmio, fw->data + h->mmio_offset,
+              h->mmio_size);
+
+       release_firmware(fw);
+       firmware->firmware_loaded = true;
+       pci_iounmap(pdev, mmio);
+       return 0;
+
+out_free_fw:
+       release_firmware(fw);
+expose_firmware:
+       expose_firmware_sysfs(gvt, mmio);
+       pci_iounmap(pdev, mmio);
+       return 0;
+}
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
new file mode 100644 (file)
index 0000000..2cc7613
--- /dev/null
@@ -0,0 +1,2232 @@
+/*
+ * GTT virtualization
+ *
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Zhi Wang <zhi.a.wang@intel.com>
+ *    Zhenyu Wang <zhenyuw@linux.intel.com>
+ *    Xiao Zheng <xiao.zheng@intel.com>
+ *
+ * Contributors:
+ *    Min He <min.he@intel.com>
+ *    Bing Niu <bing.niu@intel.com>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
+#include "trace.h"
+
+static bool enable_out_of_sync = false;
+static int preallocated_oos_pages = 8192;
+
+/*
+ * validate a gm address and related range size,
+ * translate it to host gm address
+ */
+bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
+{
+       if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
+                       && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
+               gvt_err("vgpu%d: invalid range gmadr 0x%llx size 0x%x\n",
+                               vgpu->id, addr, size);
+               return false;
+       }
+       return true;
+}
+
+/* translate a guest gmadr to host gmadr */
+int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
+{
+       if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
+                "invalid guest gmadr %llx\n", g_addr))
+               return -EACCES;
+
+       if (vgpu_gmadr_is_aperture(vgpu, g_addr))
+               *h_addr = vgpu_aperture_gmadr_base(vgpu)
+                         + (g_addr - vgpu_aperture_offset(vgpu));
+       else
+               *h_addr = vgpu_hidden_gmadr_base(vgpu)
+                         + (g_addr - vgpu_hidden_offset(vgpu));
+       return 0;
+}
+
+/* translate a host gmadr to guest gmadr */
+int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
+{
+       if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
+                "invalid host gmadr %llx\n", h_addr))
+               return -EACCES;
+
+       if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
+               *g_addr = vgpu_aperture_gmadr_base(vgpu)
+                       + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
+       else
+               *g_addr = vgpu_hidden_gmadr_base(vgpu)
+                       + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
+       return 0;
+}
+
+int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
+                            unsigned long *h_index)
+{
+       u64 h_addr;
+       int ret;
+
+       ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << GTT_PAGE_SHIFT,
+                                      &h_addr);
+       if (ret)
+               return ret;
+
+       *h_index = h_addr >> GTT_PAGE_SHIFT;
+       return 0;
+}
+
+int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
+                            unsigned long *g_index)
+{
+       u64 g_addr;
+       int ret;
+
+       ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << GTT_PAGE_SHIFT,
+                                      &g_addr);
+       if (ret)
+               return ret;
+
+       *g_index = g_addr >> GTT_PAGE_SHIFT;
+       return 0;
+}
+
+#define gtt_type_is_entry(type) \
+       (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
+        && type != GTT_TYPE_PPGTT_PTE_ENTRY \
+        && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
+
+#define gtt_type_is_pt(type) \
+       (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
+
+#define gtt_type_is_pte_pt(type) \
+       (type == GTT_TYPE_PPGTT_PTE_PT)
+
+#define gtt_type_is_root_pointer(type) \
+       (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
+
+#define gtt_init_entry(e, t, p, v) do { \
+       (e)->type = t; \
+       (e)->pdev = p; \
+       memcpy(&(e)->val64, &v, sizeof(v)); \
+} while (0)
+
+enum {
+       GTT_TYPE_INVALID = -1,
+
+       GTT_TYPE_GGTT_PTE,
+
+       GTT_TYPE_PPGTT_PTE_4K_ENTRY,
+       GTT_TYPE_PPGTT_PTE_2M_ENTRY,
+       GTT_TYPE_PPGTT_PTE_1G_ENTRY,
+
+       GTT_TYPE_PPGTT_PTE_ENTRY,
+
+       GTT_TYPE_PPGTT_PDE_ENTRY,
+       GTT_TYPE_PPGTT_PDP_ENTRY,
+       GTT_TYPE_PPGTT_PML4_ENTRY,
+
+       GTT_TYPE_PPGTT_ROOT_ENTRY,
+
+       GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
+       GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
+
+       GTT_TYPE_PPGTT_ENTRY,
+
+       GTT_TYPE_PPGTT_PTE_PT,
+       GTT_TYPE_PPGTT_PDE_PT,
+       GTT_TYPE_PPGTT_PDP_PT,
+       GTT_TYPE_PPGTT_PML4_PT,
+
+       GTT_TYPE_MAX,
+};
+
+/*
+ * Mappings between GTT_TYPE* enumerations.
+ * Following information can be found according to the given type:
+ * - type of next level page table
+ * - type of entry inside this level page table
+ * - type of entry with PSE set
+ *
+ * If the given type doesn't have such a kind of information,
+ * e.g. give a l4 root entry type, then request to get its PSE type,
+ * give a PTE page table type, then request to get its next level page
+ * table type, as we know l4 root entry doesn't have a PSE bit,
+ * and a PTE page table doesn't have a next level page table type,
+ * GTT_TYPE_INVALID will be returned. This is useful when traversing a
+ * page table.
+ */
+
+struct gtt_type_table_entry {
+       int entry_type;
+       int next_pt_type;
+       int pse_entry_type;
+};
+
+#define GTT_TYPE_TABLE_ENTRY(type, e_type, npt_type, pse_type) \
+       [type] = { \
+               .entry_type = e_type, \
+               .next_pt_type = npt_type, \
+               .pse_entry_type = pse_type, \
+       }
+
+static struct gtt_type_table_entry gtt_type_table[] = {
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
+                       GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
+                       GTT_TYPE_PPGTT_PML4_PT,
+                       GTT_TYPE_INVALID),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
+                       GTT_TYPE_PPGTT_PML4_ENTRY,
+                       GTT_TYPE_PPGTT_PDP_PT,
+                       GTT_TYPE_INVALID),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
+                       GTT_TYPE_PPGTT_PML4_ENTRY,
+                       GTT_TYPE_PPGTT_PDP_PT,
+                       GTT_TYPE_INVALID),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
+                       GTT_TYPE_PPGTT_PDP_ENTRY,
+                       GTT_TYPE_PPGTT_PDE_PT,
+                       GTT_TYPE_PPGTT_PTE_1G_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
+                       GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
+                       GTT_TYPE_PPGTT_PDE_PT,
+                       GTT_TYPE_PPGTT_PTE_1G_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
+                       GTT_TYPE_PPGTT_PDP_ENTRY,
+                       GTT_TYPE_PPGTT_PDE_PT,
+                       GTT_TYPE_PPGTT_PTE_1G_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
+                       GTT_TYPE_PPGTT_PDE_ENTRY,
+                       GTT_TYPE_PPGTT_PTE_PT,
+                       GTT_TYPE_PPGTT_PTE_2M_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
+                       GTT_TYPE_PPGTT_PDE_ENTRY,
+                       GTT_TYPE_PPGTT_PTE_PT,
+                       GTT_TYPE_PPGTT_PTE_2M_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
+                       GTT_TYPE_PPGTT_PTE_4K_ENTRY,
+                       GTT_TYPE_INVALID,
+                       GTT_TYPE_INVALID),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
+                       GTT_TYPE_PPGTT_PTE_4K_ENTRY,
+                       GTT_TYPE_INVALID,
+                       GTT_TYPE_INVALID),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
+                       GTT_TYPE_PPGTT_PDE_ENTRY,
+                       GTT_TYPE_INVALID,
+                       GTT_TYPE_PPGTT_PTE_2M_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
+                       GTT_TYPE_PPGTT_PDP_ENTRY,
+                       GTT_TYPE_INVALID,
+                       GTT_TYPE_PPGTT_PTE_1G_ENTRY),
+       GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
+                       GTT_TYPE_GGTT_PTE,
+                       GTT_TYPE_INVALID,
+                       GTT_TYPE_INVALID),
+};
+
+static inline int get_next_pt_type(int type)
+{
+       return gtt_type_table[type].next_pt_type;
+}
+
+static inline int get_entry_type(int type)
+{
+       return gtt_type_table[type].entry_type;
+}
+
+static inline int get_pse_type(int type)
+{
+       return gtt_type_table[type].pse_entry_type;
+}
+
+static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
+{
+       void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
+       u64 pte;
+
+#ifdef readq
+       pte = readq(addr);
+#else
+       pte = ioread32(addr);
+       pte |= ioread32(addr + 4) << 32;
+#endif
+       return pte;
+}
+
+static void write_pte64(struct drm_i915_private *dev_priv,
+               unsigned long index, u64 pte)
+{
+       void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
+
+#ifdef writeq
+       writeq(pte, addr);
+#else
+       iowrite32((u32)pte, addr);
+       iowrite32(pte >> 32, addr + 4);
+#endif
+       I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+       POSTING_READ(GFX_FLSH_CNTL_GEN6);
+}
+
+static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt,
+               struct intel_gvt_gtt_entry *e,
+               unsigned long index, bool hypervisor_access, unsigned long gpa,
+               struct intel_vgpu *vgpu)
+{
+       const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+       int ret;
+
+       if (WARN_ON(info->gtt_entry_size != 8))
+               return e;
+
+       if (hypervisor_access) {
+               ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
+                               (index << info->gtt_entry_size_shift),
+                               &e->val64, 8);
+               WARN_ON(ret);
+       } else if (!pt) {
+               e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
+       } else {
+               e->val64 = *((u64 *)pt + index);
+       }
+       return e;
+}
+
+static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt,
+               struct intel_gvt_gtt_entry *e,
+               unsigned long index, bool hypervisor_access, unsigned long gpa,
+               struct intel_vgpu *vgpu)
+{
+       const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+       int ret;
+
+       if (WARN_ON(info->gtt_entry_size != 8))
+               return e;
+
+       if (hypervisor_access) {
+               ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
+                               (index << info->gtt_entry_size_shift),
+                               &e->val64, 8);
+               WARN_ON(ret);
+       } else if (!pt) {
+               write_pte64(vgpu->gvt->dev_priv, index, e->val64);
+       } else {
+               *((u64 *)pt + index) = e->val64;
+       }
+       return e;
+}
+
+#define GTT_HAW 46
+
+#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
+#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
+#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
+
+static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
+{
+       unsigned long pfn;
+
+       if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
+               pfn = (e->val64 & ADDR_1G_MASK) >> 12;
+       else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
+               pfn = (e->val64 & ADDR_2M_MASK) >> 12;
+       else
+               pfn = (e->val64 & ADDR_4K_MASK) >> 12;
+       return pfn;
+}
+
+static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
+{
+       if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
+               e->val64 &= ~ADDR_1G_MASK;
+               pfn &= (ADDR_1G_MASK >> 12);
+       } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
+               e->val64 &= ~ADDR_2M_MASK;
+               pfn &= (ADDR_2M_MASK >> 12);
+       } else {
+               e->val64 &= ~ADDR_4K_MASK;
+               pfn &= (ADDR_4K_MASK >> 12);
+       }
+
+       e->val64 |= (pfn << 12);
+}
+
+static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
+{
+       /* Entry doesn't have PSE bit. */
+       if (get_pse_type(e->type) == GTT_TYPE_INVALID)
+               return false;
+
+       e->type = get_entry_type(e->type);
+       if (!(e->val64 & (1 << 7)))
+               return false;
+
+       e->type = get_pse_type(e->type);
+       return true;
+}
+
+static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
+{
+       /*
+        * i915 writes PDP root pointer registers without present bit,
+        * it also works, so we need to treat root pointer entry
+        * specifically.
+        */
+       if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
+                       || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
+               return (e->val64 != 0);
+       else
+               return (e->val64 & (1 << 0));
+}
+
+static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
+{
+       e->val64 &= ~(1 << 0);
+}
+
+/*
+ * Per-platform GMA routines.
+ */
+static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
+{
+       unsigned long x = (gma >> GTT_PAGE_SHIFT);
+
+       trace_gma_index(__func__, gma, x);
+       return x;
+}
+
+#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
+static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
+{ \
+       unsigned long x = (exp); \
+       trace_gma_index(__func__, gma, x); \
+       return x; \
+}
+
+DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
+DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
+DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
+DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
+DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
+
+static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
+       .get_entry = gtt_get_entry64,
+       .set_entry = gtt_set_entry64,
+       .clear_present = gtt_entry_clear_present,
+       .test_present = gen8_gtt_test_present,
+       .test_pse = gen8_gtt_test_pse,
+       .get_pfn = gen8_gtt_get_pfn,
+       .set_pfn = gen8_gtt_set_pfn,
+};
+
+static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
+       .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
+       .gma_to_pte_index = gen8_gma_to_pte_index,
+       .gma_to_pde_index = gen8_gma_to_pde_index,
+       .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
+       .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
+       .gma_to_pml4_index = gen8_gma_to_pml4_index,
+};
+
+static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
+               struct intel_gvt_gtt_entry *m)
+{
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       unsigned long gfn, mfn;
+
+       *m = *p;
+
+       if (!ops->test_present(p))
+               return 0;
+
+       gfn = ops->get_pfn(p);
+
+       mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
+       if (mfn == INTEL_GVT_INVALID_ADDR) {
+               gvt_err("fail to translate gfn: 0x%lx\n", gfn);
+               return -ENXIO;
+       }
+
+       ops->set_pfn(m, mfn);
+       return 0;
+}
+
+/*
+ * MM helpers.
+ */
+struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm,
+               void *page_table, struct intel_gvt_gtt_entry *e,
+               unsigned long index)
+{
+       struct intel_gvt *gvt = mm->vgpu->gvt;
+       struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+
+       e->type = mm->page_table_entry_type;
+
+       ops->get_entry(page_table, e, index, false, 0, mm->vgpu);
+       ops->test_pse(e);
+       return e;
+}
+
+struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm,
+               void *page_table, struct intel_gvt_gtt_entry *e,
+               unsigned long index)
+{
+       struct intel_gvt *gvt = mm->vgpu->gvt;
+       struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+
+       return ops->set_entry(page_table, e, index, false, 0, mm->vgpu);
+}
+
+/*
+ * PPGTT shadow page table helpers.
+ */
+static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry(
+               struct intel_vgpu_ppgtt_spt *spt,
+               void *page_table, int type,
+               struct intel_gvt_gtt_entry *e, unsigned long index,
+               bool guest)
+{
+       struct intel_gvt *gvt = spt->vgpu->gvt;
+       struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+
+       e->type = get_entry_type(type);
+
+       if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
+               return e;
+
+       ops->get_entry(page_table, e, index, guest,
+                       spt->guest_page.gfn << GTT_PAGE_SHIFT,
+                       spt->vgpu);
+       ops->test_pse(e);
+       return e;
+}
+
+static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry(
+               struct intel_vgpu_ppgtt_spt *spt,
+               void *page_table, int type,
+               struct intel_gvt_gtt_entry *e, unsigned long index,
+               bool guest)
+{
+       struct intel_gvt *gvt = spt->vgpu->gvt;
+       struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+
+       if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
+               return e;
+
+       return ops->set_entry(page_table, e, index, guest,
+                       spt->guest_page.gfn << GTT_PAGE_SHIFT,
+                       spt->vgpu);
+}
+
+#define ppgtt_get_guest_entry(spt, e, index) \
+       ppgtt_spt_get_entry(spt, NULL, \
+               spt->guest_page_type, e, index, true)
+
+#define ppgtt_set_guest_entry(spt, e, index) \
+       ppgtt_spt_set_entry(spt, NULL, \
+               spt->guest_page_type, e, index, true)
+
+#define ppgtt_get_shadow_entry(spt, e, index) \
+       ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
+               spt->shadow_page.type, e, index, false)
+
+#define ppgtt_set_shadow_entry(spt, e, index) \
+       ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
+               spt->shadow_page.type, e, index, false)
+
+/**
+ * intel_vgpu_init_guest_page - init a guest page data structure
+ * @vgpu: a vGPU
+ * @p: a guest page data structure
+ * @gfn: guest memory page frame number
+ * @handler: function will be called when target guest memory page has
+ * been modified.
+ *
+ * This function is called when user wants to track a guest memory page.
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_init_guest_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_guest_page *p,
+               unsigned long gfn,
+               int (*handler)(void *, u64, void *, int),
+               void *data)
+{
+       INIT_HLIST_NODE(&p->node);
+
+       p->writeprotection = false;
+       p->gfn = gfn;
+       p->handler = handler;
+       p->data = data;
+       p->oos_page = NULL;
+       p->write_cnt = 0;
+
+       hash_add(vgpu->gtt.guest_page_hash_table, &p->node, p->gfn);
+       return 0;
+}
+
+static int detach_oos_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_oos_page *oos_page);
+
+/**
+ * intel_vgpu_clean_guest_page - release the resource owned by guest page data
+ * structure
+ * @vgpu: a vGPU
+ * @p: a tracked guest page
+ *
+ * This function is called when user tries to stop tracking a guest memory
+ * page.
+ */
+void intel_vgpu_clean_guest_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_guest_page *p)
+{
+       if (!hlist_unhashed(&p->node))
+               hash_del(&p->node);
+
+       if (p->oos_page)
+               detach_oos_page(vgpu, p->oos_page);
+
+       if (p->writeprotection)
+               intel_gvt_hypervisor_unset_wp_page(vgpu, p);
+}
+
+/**
+ * intel_vgpu_find_guest_page - find a guest page data structure by GFN.
+ * @vgpu: a vGPU
+ * @gfn: guest memory page frame number
+ *
+ * This function is called when emulation logic wants to know if a trapped GFN
+ * is a tracked guest page.
+ *
+ * Returns:
+ * Pointer to guest page data structure, NULL if failed.
+ */
+struct intel_vgpu_guest_page *intel_vgpu_find_guest_page(
+               struct intel_vgpu *vgpu, unsigned long gfn)
+{
+       struct intel_vgpu_guest_page *p;
+
+       hash_for_each_possible(vgpu->gtt.guest_page_hash_table,
+               p, node, gfn) {
+               if (p->gfn == gfn)
+                       return p;
+       }
+       return NULL;
+}
+
+static inline int init_shadow_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_shadow_page *p, int type)
+{
+       p->vaddr = page_address(p->page);
+       p->type = type;
+
+       INIT_HLIST_NODE(&p->node);
+
+       p->mfn = intel_gvt_hypervisor_virt_to_mfn(p->vaddr);
+       if (p->mfn == INTEL_GVT_INVALID_ADDR)
+               return -EFAULT;
+
+       hash_add(vgpu->gtt.shadow_page_hash_table, &p->node, p->mfn);
+       return 0;
+}
+
+static inline void clean_shadow_page(struct intel_vgpu_shadow_page *p)
+{
+       if (!hlist_unhashed(&p->node))
+               hash_del(&p->node);
+}
+
+static inline struct intel_vgpu_shadow_page *find_shadow_page(
+               struct intel_vgpu *vgpu, unsigned long mfn)
+{
+       struct intel_vgpu_shadow_page *p;
+
+       hash_for_each_possible(vgpu->gtt.shadow_page_hash_table,
+               p, node, mfn) {
+               if (p->mfn == mfn)
+                       return p;
+       }
+       return NULL;
+}
+
+#define guest_page_to_ppgtt_spt(ptr) \
+       container_of(ptr, struct intel_vgpu_ppgtt_spt, guest_page)
+
+#define shadow_page_to_ppgtt_spt(ptr) \
+       container_of(ptr, struct intel_vgpu_ppgtt_spt, shadow_page)
+
+static void *alloc_spt(gfp_t gfp_mask)
+{
+       struct intel_vgpu_ppgtt_spt *spt;
+
+       spt = kzalloc(sizeof(*spt), gfp_mask);
+       if (!spt)
+               return NULL;
+
+       spt->shadow_page.page = alloc_page(gfp_mask);
+       if (!spt->shadow_page.page) {
+               kfree(spt);
+               return NULL;
+       }
+       return spt;
+}
+
+static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
+{
+       __free_page(spt->shadow_page.page);
+       kfree(spt);
+}
+
+static void ppgtt_free_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
+{
+       trace_spt_free(spt->vgpu->id, spt, spt->shadow_page.type);
+
+       clean_shadow_page(&spt->shadow_page);
+       intel_vgpu_clean_guest_page(spt->vgpu, &spt->guest_page);
+       list_del_init(&spt->post_shadow_list);
+
+       free_spt(spt);
+}
+
+static void ppgtt_free_all_shadow_page(struct intel_vgpu *vgpu)
+{
+       struct hlist_node *n;
+       struct intel_vgpu_shadow_page *sp;
+       int i;
+
+       hash_for_each_safe(vgpu->gtt.shadow_page_hash_table, i, n, sp, node)
+               ppgtt_free_shadow_page(shadow_page_to_ppgtt_spt(sp));
+}
+
+static int ppgtt_handle_guest_write_page_table_bytes(void *gp,
+               u64 pa, void *p_data, int bytes);
+
+static int ppgtt_write_protection_handler(void *gp, u64 pa,
+               void *p_data, int bytes)
+{
+       struct intel_vgpu_guest_page *gpt = (struct intel_vgpu_guest_page *)gp;
+       int ret;
+
+       if (bytes != 4 && bytes != 8)
+               return -EINVAL;
+
+       if (!gpt->writeprotection)
+               return -EINVAL;
+
+       ret = ppgtt_handle_guest_write_page_table_bytes(gp,
+               pa, p_data, bytes);
+       if (ret)
+               return ret;
+       return ret;
+}
+
+static int reclaim_one_mm(struct intel_gvt *gvt);
+
+static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_shadow_page(
+               struct intel_vgpu *vgpu, int type, unsigned long gfn)
+{
+       struct intel_vgpu_ppgtt_spt *spt = NULL;
+       int ret;
+
+retry:
+       spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
+       if (!spt) {
+               if (reclaim_one_mm(vgpu->gvt))
+                       goto retry;
+
+               gvt_err("fail to allocate ppgtt shadow page\n");
+               return ERR_PTR(-ENOMEM);
+       }
+
+       spt->vgpu = vgpu;
+       spt->guest_page_type = type;
+       atomic_set(&spt->refcount, 1);
+       INIT_LIST_HEAD(&spt->post_shadow_list);
+
+       /*
+        * TODO: guest page type may be different with shadow page type,
+        *       when we support PSE page in future.
+        */
+       ret = init_shadow_page(vgpu, &spt->shadow_page, type);
+       if (ret) {
+               gvt_err("fail to initialize shadow page for spt\n");
+               goto err;
+       }
+
+       ret = intel_vgpu_init_guest_page(vgpu, &spt->guest_page,
+                       gfn, ppgtt_write_protection_handler, NULL);
+       if (ret) {
+               gvt_err("fail to initialize guest page for spt\n");
+               goto err;
+       }
+
+       trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
+       return spt;
+err:
+       ppgtt_free_shadow_page(spt);
+       return ERR_PTR(ret);
+}
+
+static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page(
+               struct intel_vgpu *vgpu, unsigned long mfn)
+{
+       struct intel_vgpu_shadow_page *p = find_shadow_page(vgpu, mfn);
+
+       if (p)
+               return shadow_page_to_ppgtt_spt(p);
+
+       gvt_err("vgpu%d: fail to find ppgtt shadow page: 0x%lx\n",
+                       vgpu->id, mfn);
+       return NULL;
+}
+
+#define pt_entry_size_shift(spt) \
+       ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
+
+#define pt_entries(spt) \
+       (GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
+
+#define for_each_present_guest_entry(spt, e, i) \
+       for (i = 0; i < pt_entries(spt); i++) \
+       if (spt->vgpu->gvt->gtt.pte_ops->test_present( \
+               ppgtt_get_guest_entry(spt, e, i)))
+
+#define for_each_present_shadow_entry(spt, e, i) \
+       for (i = 0; i < pt_entries(spt); i++) \
+       if (spt->vgpu->gvt->gtt.pte_ops->test_present( \
+               ppgtt_get_shadow_entry(spt, e, i)))
+
+static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
+{
+       int v = atomic_read(&spt->refcount);
+
+       trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
+
+       atomic_inc(&spt->refcount);
+}
+
+static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt);
+
+static int ppgtt_invalidate_shadow_page_by_shadow_entry(struct intel_vgpu *vgpu,
+               struct intel_gvt_gtt_entry *e)
+{
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       struct intel_vgpu_ppgtt_spt *s;
+
+       if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(e->type))))
+               return -EINVAL;
+
+       if (ops->get_pfn(e) == vgpu->gtt.scratch_page_mfn)
+               return 0;
+
+       s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e));
+       if (!s) {
+               gvt_err("vgpu%d: fail to find shadow page: mfn: 0x%lx\n",
+                               vgpu->id, ops->get_pfn(e));
+               return -ENXIO;
+       }
+       return ppgtt_invalidate_shadow_page(s);
+}
+
+static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
+{
+       struct intel_gvt_gtt_entry e;
+       unsigned long index;
+       int ret;
+       int v = atomic_read(&spt->refcount);
+
+       trace_spt_change(spt->vgpu->id, "die", spt,
+                       spt->guest_page.gfn, spt->shadow_page.type);
+
+       trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
+
+       if (atomic_dec_return(&spt->refcount) > 0)
+               return 0;
+
+       if (gtt_type_is_pte_pt(spt->shadow_page.type))
+               goto release;
+
+       for_each_present_shadow_entry(spt, &e, index) {
+               if (!gtt_type_is_pt(get_next_pt_type(e.type))) {
+                       gvt_err("GVT doesn't support pse bit for now\n");
+                       return -EINVAL;
+               }
+               ret = ppgtt_invalidate_shadow_page_by_shadow_entry(
+                               spt->vgpu, &e);
+               if (ret)
+                       goto fail;
+       }
+release:
+       trace_spt_change(spt->vgpu->id, "release", spt,
+                       spt->guest_page.gfn, spt->shadow_page.type);
+       ppgtt_free_shadow_page(spt);
+       return 0;
+fail:
+       gvt_err("vgpu%d: fail: shadow page %p shadow entry 0x%llx type %d\n",
+                       spt->vgpu->id, spt, e.val64, e.type);
+       return ret;
+}
+
+static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt);
+
+static struct intel_vgpu_ppgtt_spt *ppgtt_populate_shadow_page_by_guest_entry(
+               struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
+{
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       struct intel_vgpu_ppgtt_spt *s = NULL;
+       struct intel_vgpu_guest_page *g;
+       int ret;
+
+       if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(we->type)))) {
+               ret = -EINVAL;
+               goto fail;
+       }
+
+       g = intel_vgpu_find_guest_page(vgpu, ops->get_pfn(we));
+       if (g) {
+               s = guest_page_to_ppgtt_spt(g);
+               ppgtt_get_shadow_page(s);
+       } else {
+               int type = get_next_pt_type(we->type);
+
+               s = ppgtt_alloc_shadow_page(vgpu, type, ops->get_pfn(we));
+               if (IS_ERR(s)) {
+                       ret = PTR_ERR(s);
+                       goto fail;
+               }
+
+               ret = intel_gvt_hypervisor_set_wp_page(vgpu, &s->guest_page);
+               if (ret)
+                       goto fail;
+
+               ret = ppgtt_populate_shadow_page(s);
+               if (ret)
+                       goto fail;
+
+               trace_spt_change(vgpu->id, "new", s, s->guest_page.gfn,
+                       s->shadow_page.type);
+       }
+       return s;
+fail:
+       gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n",
+                       vgpu->id, s, we->val64, we->type);
+       return ERR_PTR(ret);
+}
+
+static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
+               struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
+{
+       struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
+
+       se->type = ge->type;
+       se->val64 = ge->val64;
+
+       ops->set_pfn(se, s->shadow_page.mfn);
+}
+
+static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
+{
+       struct intel_vgpu *vgpu = spt->vgpu;
+       struct intel_vgpu_ppgtt_spt *s;
+       struct intel_gvt_gtt_entry se, ge;
+       unsigned long i;
+       int ret;
+
+       trace_spt_change(spt->vgpu->id, "born", spt,
+                       spt->guest_page.gfn, spt->shadow_page.type);
+
+       if (gtt_type_is_pte_pt(spt->shadow_page.type)) {
+               for_each_present_guest_entry(spt, &ge, i) {
+                       ret = gtt_entry_p2m(vgpu, &ge, &se);
+                       if (ret)
+                               goto fail;
+                       ppgtt_set_shadow_entry(spt, &se, i);
+               }
+               return 0;
+       }
+
+       for_each_present_guest_entry(spt, &ge, i) {
+               if (!gtt_type_is_pt(get_next_pt_type(ge.type))) {
+                       gvt_err("GVT doesn't support pse bit now\n");
+                       ret = -EINVAL;
+                       goto fail;
+               }
+
+               s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge);
+               if (IS_ERR(s)) {
+                       ret = PTR_ERR(s);
+                       goto fail;
+               }
+               ppgtt_get_shadow_entry(spt, &se, i);
+               ppgtt_generate_shadow_entry(&se, s, &ge);
+               ppgtt_set_shadow_entry(spt, &se, i);
+       }
+       return 0;
+fail:
+       gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n",
+                       vgpu->id, spt, ge.val64, ge.type);
+       return ret;
+}
+
+static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt,
+               struct intel_gvt_gtt_entry *we, unsigned long index)
+{
+       struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
+       struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
+       struct intel_vgpu *vgpu = spt->vgpu;
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       struct intel_gvt_gtt_entry e;
+       int ret;
+
+       trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type,
+               we->val64, index);
+
+       ppgtt_get_shadow_entry(spt, &e, index);
+       if (!ops->test_present(&e))
+               return 0;
+
+       if (ops->get_pfn(&e) == vgpu->gtt.scratch_page_mfn)
+               return 0;
+
+       if (gtt_type_is_pt(get_next_pt_type(we->type))) {
+               struct intel_vgpu_guest_page *g =
+                       intel_vgpu_find_guest_page(vgpu, ops->get_pfn(we));
+               if (!g) {
+                       gvt_err("fail to find guest page\n");
+                       ret = -ENXIO;
+                       goto fail;
+               }
+               ret = ppgtt_invalidate_shadow_page(guest_page_to_ppgtt_spt(g));
+               if (ret)
+                       goto fail;
+       }
+       ops->set_pfn(&e, vgpu->gtt.scratch_page_mfn);
+       ppgtt_set_shadow_entry(spt, &e, index);
+       return 0;
+fail:
+       gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n",
+                       vgpu->id, spt, we->val64, we->type);
+       return ret;
+}
+
+static int ppgtt_handle_guest_entry_add(struct intel_vgpu_guest_page *gpt,
+               struct intel_gvt_gtt_entry *we, unsigned long index)
+{
+       struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
+       struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
+       struct intel_vgpu *vgpu = spt->vgpu;
+       struct intel_gvt_gtt_entry m;
+       struct intel_vgpu_ppgtt_spt *s;
+       int ret;
+
+       trace_gpt_change(spt->vgpu->id, "add", spt, sp->type,
+               we->val64, index);
+
+       if (gtt_type_is_pt(get_next_pt_type(we->type))) {
+               s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, we);
+               if (IS_ERR(s)) {
+                       ret = PTR_ERR(s);
+                       goto fail;
+               }
+               ppgtt_get_shadow_entry(spt, &m, index);
+               ppgtt_generate_shadow_entry(&m, s, we);
+               ppgtt_set_shadow_entry(spt, &m, index);
+       } else {
+               ret = gtt_entry_p2m(vgpu, we, &m);
+               if (ret)
+                       goto fail;
+               ppgtt_set_shadow_entry(spt, &m, index);
+       }
+       return 0;
+fail:
+       gvt_err("vgpu%d: fail: spt %p guest entry 0x%llx type %d\n", vgpu->id,
+                       spt, we->val64, we->type);
+       return ret;
+}
+
+static int sync_oos_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_oos_page *oos_page)
+{
+       const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+       struct intel_vgpu_ppgtt_spt *spt =
+               guest_page_to_ppgtt_spt(oos_page->guest_page);
+       struct intel_gvt_gtt_entry old, new, m;
+       int index;
+       int ret;
+
+       trace_oos_change(vgpu->id, "sync", oos_page->id,
+                       oos_page->guest_page, spt->guest_page_type);
+
+       old.type = new.type = get_entry_type(spt->guest_page_type);
+       old.val64 = new.val64 = 0;
+
+       for (index = 0; index < (GTT_PAGE_SIZE >> info->gtt_entry_size_shift);
+               index++) {
+               ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
+               ops->get_entry(NULL, &new, index, true,
+                       oos_page->guest_page->gfn << PAGE_SHIFT, vgpu);
+
+               if (old.val64 == new.val64
+                       && !test_and_clear_bit(index, spt->post_shadow_bitmap))
+                       continue;
+
+               trace_oos_sync(vgpu->id, oos_page->id,
+                               oos_page->guest_page, spt->guest_page_type,
+                               new.val64, index);
+
+               ret = gtt_entry_p2m(vgpu, &new, &m);
+               if (ret)
+                       return ret;
+
+               ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
+               ppgtt_set_shadow_entry(spt, &m, index);
+       }
+
+       oos_page->guest_page->write_cnt = 0;
+       list_del_init(&spt->post_shadow_list);
+       return 0;
+}
+
+static int detach_oos_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_oos_page *oos_page)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_vgpu_ppgtt_spt *spt =
+               guest_page_to_ppgtt_spt(oos_page->guest_page);
+
+       trace_oos_change(vgpu->id, "detach", oos_page->id,
+                       oos_page->guest_page, spt->guest_page_type);
+
+       oos_page->guest_page->write_cnt = 0;
+       oos_page->guest_page->oos_page = NULL;
+       oos_page->guest_page = NULL;
+
+       list_del_init(&oos_page->vm_list);
+       list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
+
+       return 0;
+}
+
+static int attach_oos_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_oos_page *oos_page,
+               struct intel_vgpu_guest_page *gpt)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       int ret;
+
+       ret = intel_gvt_hypervisor_read_gpa(vgpu, gpt->gfn << GTT_PAGE_SHIFT,
+               oos_page->mem, GTT_PAGE_SIZE);
+       if (ret)
+               return ret;
+
+       oos_page->guest_page = gpt;
+       gpt->oos_page = oos_page;
+
+       list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
+
+       trace_oos_change(vgpu->id, "attach", gpt->oos_page->id,
+                       gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type);
+       return 0;
+}
+
+static int ppgtt_set_guest_page_sync(struct intel_vgpu *vgpu,
+               struct intel_vgpu_guest_page *gpt)
+{
+       int ret;
+
+       ret = intel_gvt_hypervisor_set_wp_page(vgpu, gpt);
+       if (ret)
+               return ret;
+
+       trace_oos_change(vgpu->id, "set page sync", gpt->oos_page->id,
+                       gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type);
+
+       list_del_init(&gpt->oos_page->vm_list);
+       return sync_oos_page(vgpu, gpt->oos_page);
+}
+
+static int ppgtt_allocate_oos_page(struct intel_vgpu *vgpu,
+               struct intel_vgpu_guest_page *gpt)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt *gtt = &gvt->gtt;
+       struct intel_vgpu_oos_page *oos_page = gpt->oos_page;
+       int ret;
+
+       WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
+
+       if (list_empty(&gtt->oos_page_free_list_head)) {
+               oos_page = container_of(gtt->oos_page_use_list_head.next,
+                       struct intel_vgpu_oos_page, list);
+               ret = ppgtt_set_guest_page_sync(vgpu, oos_page->guest_page);
+               if (ret)
+                       return ret;
+               ret = detach_oos_page(vgpu, oos_page);
+               if (ret)
+                       return ret;
+       } else
+               oos_page = container_of(gtt->oos_page_free_list_head.next,
+                       struct intel_vgpu_oos_page, list);
+       return attach_oos_page(vgpu, oos_page, gpt);
+}
+
+static int ppgtt_set_guest_page_oos(struct intel_vgpu *vgpu,
+               struct intel_vgpu_guest_page *gpt)
+{
+       struct intel_vgpu_oos_page *oos_page = gpt->oos_page;
+
+       if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
+               return -EINVAL;
+
+       trace_oos_change(vgpu->id, "set page out of sync", gpt->oos_page->id,
+                       gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type);
+
+       list_add_tail(&oos_page->vm_list, &vgpu->gtt.oos_page_list_head);
+       return intel_gvt_hypervisor_unset_wp_page(vgpu, gpt);
+}
+
+/**
+ * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
+ * @vgpu: a vGPU
+ *
+ * This function is called before submitting a guest workload to host,
+ * to sync all the out-of-synced shadow for vGPU
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
+{
+       struct list_head *pos, *n;
+       struct intel_vgpu_oos_page *oos_page;
+       int ret;
+
+       if (!enable_out_of_sync)
+               return 0;
+
+       list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
+               oos_page = container_of(pos,
+                               struct intel_vgpu_oos_page, vm_list);
+               ret = ppgtt_set_guest_page_sync(vgpu, oos_page->guest_page);
+               if (ret)
+                       return ret;
+       }
+       return 0;
+}
+
+/*
+ * The heart of PPGTT shadow page table.
+ */
+static int ppgtt_handle_guest_write_page_table(
+               struct intel_vgpu_guest_page *gpt,
+               struct intel_gvt_gtt_entry *we, unsigned long index)
+{
+       struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
+       struct intel_vgpu *vgpu = spt->vgpu;
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       struct intel_gvt_gtt_entry ge;
+
+       int old_present, new_present;
+       int ret;
+
+       ppgtt_get_guest_entry(spt, &ge, index);
+
+       old_present = ops->test_present(&ge);
+       new_present = ops->test_present(we);
+
+       ppgtt_set_guest_entry(spt, we, index);
+
+       if (old_present) {
+               ret = ppgtt_handle_guest_entry_removal(gpt, &ge, index);
+               if (ret)
+                       goto fail;
+       }
+       if (new_present) {
+               ret = ppgtt_handle_guest_entry_add(gpt, we, index);
+               if (ret)
+                       goto fail;
+       }
+       return 0;
+fail:
+       gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d.\n",
+                       vgpu->id, spt, we->val64, we->type);
+       return ret;
+}
+
+static inline bool can_do_out_of_sync(struct intel_vgpu_guest_page *gpt)
+{
+       return enable_out_of_sync
+               && gtt_type_is_pte_pt(
+                       guest_page_to_ppgtt_spt(gpt)->guest_page_type)
+               && gpt->write_cnt >= 2;
+}
+
+static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
+               unsigned long index)
+{
+       set_bit(index, spt->post_shadow_bitmap);
+       if (!list_empty(&spt->post_shadow_list))
+               return;
+
+       list_add_tail(&spt->post_shadow_list,
+                       &spt->vgpu->gtt.post_shadow_list_head);
+}
+
+/**
+ * intel_vgpu_flush_post_shadow - flush the post shadow transactions
+ * @vgpu: a vGPU
+ *
+ * This function is called before submitting a guest workload to host,
+ * to flush all the post shadows for a vGPU.
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
+{
+       struct list_head *pos, *n;
+       struct intel_vgpu_ppgtt_spt *spt;
+       struct intel_gvt_gtt_entry ge, e;
+       unsigned long index;
+       int ret;
+
+       list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
+               spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
+                               post_shadow_list);
+
+               for_each_set_bit(index, spt->post_shadow_bitmap,
+                               GTT_ENTRY_NUM_IN_ONE_PAGE) {
+                       ppgtt_get_guest_entry(spt, &ge, index);
+                       e = ge;
+                       e.val64 = 0;
+                       ppgtt_set_guest_entry(spt, &e, index);
+
+                       ret = ppgtt_handle_guest_write_page_table(
+                                       &spt->guest_page, &ge, index);
+                       if (ret)
+                               return ret;
+                       clear_bit(index, spt->post_shadow_bitmap);
+               }
+               list_del_init(&spt->post_shadow_list);
+       }
+       return 0;
+}
+
+static int ppgtt_handle_guest_write_page_table_bytes(void *gp,
+               u64 pa, void *p_data, int bytes)
+{
+       struct intel_vgpu_guest_page *gpt = (struct intel_vgpu_guest_page *)gp;
+       struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
+       struct intel_vgpu *vgpu = spt->vgpu;
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+       struct intel_gvt_gtt_entry we;
+       unsigned long index;
+       int ret;
+
+       index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
+
+       ppgtt_get_guest_entry(spt, &we, index);
+       memcpy((void *)&we.val64 + (pa & (info->gtt_entry_size - 1)),
+                       p_data, bytes);
+
+       ops->test_pse(&we);
+
+       if (bytes == info->gtt_entry_size) {
+               ret = ppgtt_handle_guest_write_page_table(gpt, &we, index);
+               if (ret)
+                       return ret;
+       } else {
+               struct intel_gvt_gtt_entry ge;
+
+               ppgtt_get_guest_entry(spt, &ge, index);
+
+               if (!test_bit(index, spt->post_shadow_bitmap)) {
+                       ret = ppgtt_handle_guest_entry_removal(gpt,
+                                       &ge, index);
+                       if (ret)
+                               return ret;
+               }
+
+               ppgtt_set_post_shadow(spt, index);
+               ppgtt_set_guest_entry(spt, &we, index);
+       }
+
+       if (!enable_out_of_sync)
+               return 0;
+
+       gpt->write_cnt++;
+
+       if (gpt->oos_page)
+               ops->set_entry(gpt->oos_page->mem, &we, index,
+                               false, 0, vgpu);
+
+       if (can_do_out_of_sync(gpt)) {
+               if (!gpt->oos_page)
+                       ppgtt_allocate_oos_page(vgpu, gpt);
+
+               ret = ppgtt_set_guest_page_oos(vgpu, gpt);
+               if (ret < 0)
+                       return ret;
+       }
+       return 0;
+}
+
+/*
+ * mm page table allocation policy for bdw+
+ *  - for ggtt, only virtual page table will be allocated.
+ *  - for ppgtt, dedicated virtual/shadow page table will be allocated.
+ */
+static int gen8_mm_alloc_page_table(struct intel_vgpu_mm *mm)
+{
+       struct intel_vgpu *vgpu = mm->vgpu;
+       struct intel_gvt *gvt = vgpu->gvt;
+       const struct intel_gvt_device_info *info = &gvt->device_info;
+       void *mem;
+
+       if (mm->type == INTEL_GVT_MM_PPGTT) {
+               mm->page_table_entry_cnt = 4;
+               mm->page_table_entry_size = mm->page_table_entry_cnt *
+                       info->gtt_entry_size;
+               mem = kzalloc(mm->has_shadow_page_table ?
+                       mm->page_table_entry_size * 2
+                               : mm->page_table_entry_size,
+                       GFP_ATOMIC);
+               if (!mem)
+                       return -ENOMEM;
+               mm->virtual_page_table = mem;
+               if (!mm->has_shadow_page_table)
+                       return 0;
+               mm->shadow_page_table = mem + mm->page_table_entry_size;
+       } else if (mm->type == INTEL_GVT_MM_GGTT) {
+               mm->page_table_entry_cnt =
+                       (gvt_ggtt_gm_sz(gvt) >> GTT_PAGE_SHIFT);
+               mm->page_table_entry_size = mm->page_table_entry_cnt *
+                       info->gtt_entry_size;
+               mem = vzalloc(mm->page_table_entry_size);
+               if (!mem)
+                       return -ENOMEM;
+               mm->virtual_page_table = mem;
+       }
+       return 0;
+}
+
+static void gen8_mm_free_page_table(struct intel_vgpu_mm *mm)
+{
+       if (mm->type == INTEL_GVT_MM_PPGTT) {
+               kfree(mm->virtual_page_table);
+       } else if (mm->type == INTEL_GVT_MM_GGTT) {
+               if (mm->virtual_page_table)
+                       vfree(mm->virtual_page_table);
+       }
+       mm->virtual_page_table = mm->shadow_page_table = NULL;
+}
+
+static void invalidate_mm(struct intel_vgpu_mm *mm)
+{
+       struct intel_vgpu *vgpu = mm->vgpu;
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt *gtt = &gvt->gtt;
+       struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+       struct intel_gvt_gtt_entry se;
+       int i;
+
+       if (WARN_ON(!mm->has_shadow_page_table || !mm->shadowed))
+               return;
+
+       for (i = 0; i < mm->page_table_entry_cnt; i++) {
+               ppgtt_get_shadow_root_entry(mm, &se, i);
+               if (!ops->test_present(&se))
+                       continue;
+               ppgtt_invalidate_shadow_page_by_shadow_entry(
+                               vgpu, &se);
+               se.val64 = 0;
+               ppgtt_set_shadow_root_entry(mm, &se, i);
+
+               trace_gpt_change(vgpu->id, "destroy root pointer",
+                               NULL, se.type, se.val64, i);
+       }
+       mm->shadowed = false;
+}
+
+/**
+ * intel_vgpu_destroy_mm - destroy a mm object
+ * @mm: a kref object
+ *
+ * This function is used to destroy a mm object for vGPU
+ *
+ */
+void intel_vgpu_destroy_mm(struct kref *mm_ref)
+{
+       struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
+       struct intel_vgpu *vgpu = mm->vgpu;
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt *gtt = &gvt->gtt;
+
+       if (!mm->initialized)
+               goto out;
+
+       list_del(&mm->list);
+       list_del(&mm->lru_list);
+
+       if (mm->has_shadow_page_table)
+               invalidate_mm(mm);
+
+       gtt->mm_free_page_table(mm);
+out:
+       kfree(mm);
+}
+
+static int shadow_mm(struct intel_vgpu_mm *mm)
+{
+       struct intel_vgpu *vgpu = mm->vgpu;
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt *gtt = &gvt->gtt;
+       struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+       struct intel_vgpu_ppgtt_spt *spt;
+       struct intel_gvt_gtt_entry ge, se;
+       int i;
+       int ret;
+
+       if (WARN_ON(!mm->has_shadow_page_table || mm->shadowed))
+               return 0;
+
+       mm->shadowed = true;
+
+       for (i = 0; i < mm->page_table_entry_cnt; i++) {
+               ppgtt_get_guest_root_entry(mm, &ge, i);
+               if (!ops->test_present(&ge))
+                       continue;
+
+               trace_gpt_change(vgpu->id, __func__, NULL,
+                               ge.type, ge.val64, i);
+
+               spt = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge);
+               if (IS_ERR(spt)) {
+                       gvt_err("fail to populate guest root pointer\n");
+                       ret = PTR_ERR(spt);
+                       goto fail;
+               }
+               ppgtt_generate_shadow_entry(&se, spt, &ge);
+               ppgtt_set_shadow_root_entry(mm, &se, i);
+
+               trace_gpt_change(vgpu->id, "populate root pointer",
+                               NULL, se.type, se.val64, i);
+       }
+       return 0;
+fail:
+       invalidate_mm(mm);
+       return ret;
+}
+
+/**
+ * intel_vgpu_create_mm - create a mm object for a vGPU
+ * @vgpu: a vGPU
+ * @mm_type: mm object type, should be PPGTT or GGTT
+ * @virtual_page_table: page table root pointers. Could be NULL if user wants
+ *     to populate shadow later.
+ * @page_table_level: describe the page table level of the mm object
+ * @pde_base_index: pde root pointer base in GGTT MMIO.
+ *
+ * This function is used to create a mm object for a vGPU.
+ *
+ * Returns:
+ * Zero on success, negative error code in pointer if failed.
+ */
+struct intel_vgpu_mm *intel_vgpu_create_mm(struct intel_vgpu *vgpu,
+               int mm_type, void *virtual_page_table, int page_table_level,
+               u32 pde_base_index)
+{
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt *gtt = &gvt->gtt;
+       struct intel_vgpu_mm *mm;
+       int ret;
+
+       mm = kzalloc(sizeof(*mm), GFP_ATOMIC);
+       if (!mm) {
+               ret = -ENOMEM;
+               goto fail;
+       }
+
+       mm->type = mm_type;
+
+       if (page_table_level == 1)
+               mm->page_table_entry_type = GTT_TYPE_GGTT_PTE;
+       else if (page_table_level == 3)
+               mm->page_table_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
+       else if (page_table_level == 4)
+               mm->page_table_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
+       else {
+               WARN_ON(1);
+               ret = -EINVAL;
+               goto fail;
+       }
+
+       mm->page_table_level = page_table_level;
+       mm->pde_base_index = pde_base_index;
+
+       mm->vgpu = vgpu;
+       mm->has_shadow_page_table = !!(mm_type == INTEL_GVT_MM_PPGTT);
+
+       kref_init(&mm->ref);
+       atomic_set(&mm->pincount, 0);
+       INIT_LIST_HEAD(&mm->list);
+       INIT_LIST_HEAD(&mm->lru_list);
+       list_add_tail(&mm->list, &vgpu->gtt.mm_list_head);
+
+       ret = gtt->mm_alloc_page_table(mm);
+       if (ret) {
+               gvt_err("fail to allocate page table for mm\n");
+               goto fail;
+       }
+
+       mm->initialized = true;
+
+       if (virtual_page_table)
+               memcpy(mm->virtual_page_table, virtual_page_table,
+                               mm->page_table_entry_size);
+
+       if (mm->has_shadow_page_table) {
+               ret = shadow_mm(mm);
+               if (ret)
+                       goto fail;
+               list_add_tail(&mm->lru_list, &gvt->gtt.mm_lru_list_head);
+       }
+       return mm;
+fail:
+       gvt_err("fail to create mm\n");
+       if (mm)
+               intel_gvt_mm_unreference(mm);
+       return ERR_PTR(ret);
+}
+
+/**
+ * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
+ * @mm: a vGPU mm object
+ *
+ * This function is called when user doesn't want to use a vGPU mm object
+ */
+void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
+{
+       if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
+               return;
+
+       atomic_dec(&mm->pincount);
+}
+
+/**
+ * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
+ * @vgpu: a vGPU
+ *
+ * This function is called when user wants to use a vGPU mm object. If this
+ * mm object hasn't been shadowed yet, the shadow will be populated at this
+ * time.
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
+{
+       int ret;
+
+       if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
+               return 0;
+
+       atomic_inc(&mm->pincount);
+
+       if (!mm->shadowed) {
+               ret = shadow_mm(mm);
+               if (ret)
+                       return ret;
+       }
+
+       list_del_init(&mm->lru_list);
+       list_add_tail(&mm->lru_list, &mm->vgpu->gvt->gtt.mm_lru_list_head);
+       return 0;
+}
+
+static int reclaim_one_mm(struct intel_gvt *gvt)
+{
+       struct intel_vgpu_mm *mm;
+       struct list_head *pos, *n;
+
+       list_for_each_safe(pos, n, &gvt->gtt.mm_lru_list_head) {
+               mm = container_of(pos, struct intel_vgpu_mm, lru_list);
+
+               if (mm->type != INTEL_GVT_MM_PPGTT)
+                       continue;
+               if (atomic_read(&mm->pincount))
+                       continue;
+
+               list_del_init(&mm->lru_list);
+               invalidate_mm(mm);
+               return 1;
+       }
+       return 0;
+}
+
+/*
+ * GMA translation APIs.
+ */
+static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
+               struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
+{
+       struct intel_vgpu *vgpu = mm->vgpu;
+       struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+       struct intel_vgpu_ppgtt_spt *s;
+
+       if (WARN_ON(!mm->has_shadow_page_table))
+               return -EINVAL;
+
+       s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e));
+       if (!s)
+               return -ENXIO;
+
+       if (!guest)
+               ppgtt_get_shadow_entry(s, e, index);
+       else
+               ppgtt_get_guest_entry(s, e, index);
+       return 0;
+}
+
+/**
+ * intel_vgpu_gma_to_gpa - translate a gma to GPA
+ * @mm: mm object. could be a PPGTT or GGTT mm object
+ * @gma: graphics memory address in this mm object
+ *
+ * This function is used to translate a graphics memory address in specific
+ * graphics memory space to guest physical address.
+ *
+ * Returns:
+ * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
+ */
+unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
+{
+       struct intel_vgpu *vgpu = mm->vgpu;
+       struct intel_gvt *gvt = vgpu->gvt;
+       struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
+       struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
+       unsigned long gpa = INTEL_GVT_INVALID_ADDR;
+       unsigned long gma_index[4];
+       struct intel_gvt_gtt_entry e;
+       int i, index;
+       int ret;
+
+       if (mm->type != INTEL_GVT_MM_GGTT && mm->type != INTEL_GVT_MM_PPGTT)
+               return INTEL_GVT_INVALID_ADDR;
+
+       if (mm->type == INTEL_GVT_MM_GGTT) {
+               if (!vgpu_gmadr_is_valid(vgpu, gma))
+                       goto err;
+
+               ggtt_get_guest_entry(mm, &e,
+                       gma_ops->gma_to_ggtt_pte_index(gma));
+               gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT)
+                       + (gma & ~GTT_PAGE_MASK);
+
+               trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
+               return gpa;
+       }
+
+       switch (mm->page_table_level) {
+       case 4:
+               ppgtt_get_shadow_root_entry(mm, &e, 0);
+  &