Merge tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel...
authorDave Airlie <airlied@redhat.com>
Tue, 25 Oct 2016 06:36:13 +0000 (16:36 +1000)
committerDave Airlie <airlied@redhat.com>
Tue, 25 Oct 2016 06:39:43 +0000 (16:39 +1000)
- first slice of the gvt device model (Zhenyu et al)
- compression support for gpu error states (Chris)
- sunset clause on gpu errors resulting in dmesg noise telling users
  how to report them
- .rodata diet from Tvrtko
- switch over lots of macros to only take dev_priv (Tvrtko)
- underrun suppression for dp link training (Ville)
- lspcon (hmdi 2.0 on skl/bxt) support from Shashank Sharma, polish
  from Jani
- gen9 wm fixes from Paulo&Lyude
- updated ddi programming for kbl (Rodrigo)
- respect alternate aux/ddc pins (from vbt) for all ddi ports (Ville)

* tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel: (227 commits)
  drm/i915: Update DRIVER_DATE to 20161024
  drm/i915: Stop setting SNB min-freq-table 0 on powersave setup
  drm/i915/dp: add lane_count check in intel_dp_check_link_status
  drm/i915: Fix whitespace issues
  drm/i915: Clean up DDI DDC/AUX CH sanitation
  drm/i915: Respect alternate_ddc_pin for all DDI ports
  drm/i915: Respect alternate_aux_channel for all DDI ports
  drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7
  drm/i915: KBL - Recommended buffer translation programming for DisplayPort
  drm/i915: Move down skl/kbl ddi iboost and n_edp_entires fixup
  drm/i915: Add a sunset clause to GPU hang logging
  drm/i915: Stop reporting error details in dmesg as well as the error-state
  drm/i915/gvt: do not ignore return value of create_scratch_page
  drm/i915/gvt: fix spare warnings on odd constant _Bool cast
  drm/i915/gvt: mark symbols static where possible
  drm/i915/gvt: fix sparse warnings on different address spaces
  drm/i915/gvt: properly access enabled intel_engine_cs
  drm/i915/gvt: Remove defunct vmap_batch()
  drm/i915/gvt: Use common mapping routines for shadow_bb object
  drm/i915/gvt: Use common mapping routines for indirect_ctx object
  ...

1  2 
MAINTAINERS
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_fbc.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_sprite.c
sound/soc/codecs/hdac_hdmi.c

diff --combined MAINTAINERS
index c4479530634288d1fa2803d1c46b7c233a27facf,8af083e4e193ba2e5676efa6f7ef4ebb404d7b21..e60e0a18822962d8b3eb69af47512bde0e7181d4
@@@ -316,14 -316,6 +316,14 @@@ W:       https://01.org/linux-acp
  S:    Supported
  F:    drivers/acpi/fan.c
  
 +ACPI FOR ARM64 (ACPI/arm64)
 +M:    Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
 +M:    Hanjun Guo <hanjun.guo@linaro.org>
 +M:    Sudeep Holla <sudeep.holla@arm.com>
 +L:    linux-acpi@vger.kernel.org
 +S:    Maintained
 +F:    drivers/acpi/arm64
 +
  ACPI THERMAL DRIVER
  M:    Zhang Rui <rui.zhang@intel.com>
  L:    linux-acpi@vger.kernel.org
@@@ -644,15 -636,6 +644,15 @@@ F:       drivers/tty/serial/altera_jtaguart.
  F:    include/linux/altera_uart.h
  F:    include/linux/altera_jtaguart.h
  
 +AMAZON ETHERNET DRIVERS
 +M:    Netanel Belgazal <netanel@annapurnalabs.com>
 +R:    Saeed Bishara <saeed@annapurnalabs.com>
 +R:    Zorik Machulsky <zorik@annapurnalabs.com>
 +L:    netdev@vger.kernel.org
 +S:    Supported
 +F:    Documentation/networking/ena.txt
 +F:    drivers/net/ethernet/amazon/
 +
  AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER
  M:    Tom Lendacky <thomas.lendacky@amd.com>
  M:    Gary Hook <gary.hook@amd.com>
@@@ -827,11 -810,11 +827,11 @@@ L:      alsa-devel@alsa-project.org (moderat
  S:    Maintained
  F:    sound/aoa/
  
 -APEX EMBEDDED SYSTEMS STX104 DAC DRIVER
 +APEX EMBEDDED SYSTEMS STX104 IIO DRIVER
  M:    William Breathitt Gray <vilhelm.gray@gmail.com>
  L:    linux-iio@vger.kernel.org
  S:    Maintained
 -F:    drivers/iio/dac/stx104.c
 +F:    drivers/iio/adc/stx104.c
  
  APM DRIVER
  M:    Jiri Kosina <jikos@kernel.org>
@@@ -874,13 -857,6 +874,13 @@@ F:       drivers/net/phy/mdio-xgene.
  F:    Documentation/devicetree/bindings/net/apm-xgene-enet.txt
  F:    Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
  
 +APPLIED MICRO (APM) X-GENE SOC PMU
 +M:    Tai Nguyen <ttnguyen@apm.com>
 +S:    Supported
 +F:    drivers/perf/xgene_pmu.c
 +F:    Documentation/perf/xgene-pmu.txt
 +F:    Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
 +
  APTINA CAMERA SENSOR PLL
  M:    Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
  L:    linux-media@vger.kernel.org
@@@ -937,17 -913,15 +937,17 @@@ F:      arch/arm/include/asm/floppy.
  
  ARM PMU PROFILING AND DEBUGGING
  M:    Will Deacon <will.deacon@arm.com>
 -R:    Mark Rutland <mark.rutland@arm.com>
 +M:    Mark Rutland <mark.rutland@arm.com>
  S:    Maintained
 +L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  F:    arch/arm*/kernel/perf_*
  F:    arch/arm/oprofile/common.c
  F:    arch/arm*/kernel/hw_breakpoint.c
  F:    arch/arm*/include/asm/hw_breakpoint.h
  F:    arch/arm*/include/asm/perf_event.h
 -F:    drivers/perf/arm_pmu.c
 +F:    drivers/perf/*
  F:    include/linux/perf/arm_pmu.h
 +F:    Documentation/devicetree/bindings/arm/pmu.txt
  
  ARM PORT
  M:    Russell King <linux@armlinux.org.uk>
@@@ -1018,7 -992,6 +1018,7 @@@ M:       Chen-Yu Tsai <wens@csie.org
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
  N:    sun[x456789]i
 +F:    arch/arm/boot/dts/ntc-gr8*
  
  ARM/Allwinner SoC Clock Support
  M:    Emilio López <emilio@elopez.com.ar>
@@@ -1150,11 -1123,6 +1150,11 @@@ F:    drivers/hwtracing/coresight/
  F:    Documentation/trace/coresight.txt
  F:    Documentation/devicetree/bindings/arm/coresight.txt
  F:    Documentation/ABI/testing/sysfs-bus-coresight-devices-*
 +F:    tools/perf/arch/arm/util/pmu.c
 +F:    tools/perf/arch/arm/util/auxtrace.c
 +F:    tools/perf/arch/arm/util/cs-etm.c
 +F:    tools/perf/arch/arm/util/cs-etm.h
 +F:    tools/perf/util/cs-etm.h
  
  ARM/CORGI MACHINE SUPPORT
  M:    Richard Purdie <rpurdie@rpsys.net>
@@@ -1475,7 -1443,6 +1475,7 @@@ F:      arch/arm/mach-orion5x/ts78xx-
  ARM/OXNAS platform support
  M:    Neil Armstrong <narmstrong@baylibre.com>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 +L:    linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers)
  S:    Maintained
  F:    arch/arm/mach-oxnas/
  F:    arch/arm/boot/dts/oxnas*
@@@ -1710,6 -1677,14 +1710,6 @@@ S:     Maintaine
  F:    arch/arm/plat-samsung/s5p-dev-mfc.c
  F:    drivers/media/platform/s5p-mfc/
  
 -ARM/SAMSUNG S5P SERIES TV SUBSYSTEM SUPPORT
 -M:    Kyungmin Park <kyungmin.park@samsung.com>
 -M:    Tomasz Stanislawski <t.stanislaws@samsung.com>
 -L:    linux-arm-kernel@lists.infradead.org
 -L:    linux-media@vger.kernel.org
 -S:    Maintained
 -F:    drivers/media/platform/s5p-tv/
 -
  ARM/SAMSUNG S5P SERIES HDMI CEC SUBSYSTEM SUPPORT
  M:    Kyungmin Park <kyungmin.park@samsung.com>
  L:    linux-arm-kernel@lists.infradead.org
@@@ -1865,10 -1840,8 +1865,10 @@@ F:    arch/arm/mach-uniphier
  F:    arch/arm/mm/cache-uniphier.c
  F:    arch/arm64/boot/dts/socionext/
  F:    drivers/bus/uniphier-system-bus.c
 +F:    drivers/clk/uniphier/
  F:    drivers/i2c/busses/i2c-uniphier*
  F:    drivers/pinctrl/uniphier/
 +F:    drivers/reset/reset-uniphier.c
  F:    drivers/tty/serial/8250/8250_uniphier.c
  N:    uniphier
  
@@@ -2003,13 -1976,6 +2003,13 @@@ S:    Maintaine
  F:    drivers/media/i2c/as3645a.c
  F:    include/media/i2c/as3645a.h
  
 +ASAHI KASEI AK8974 DRIVER
 +M:    Linus Walleij <linus.walleij@linaro.org>
 +L:    linux-iio@vger.kernel.org
 +W:    http://www.akm.com/
 +S:    Supported
 +F:    drivers/iio/magnetometer/ak8974.c
 +
  ASC7621 HARDWARE MONITOR DRIVER
  M:    George Joseph <george.joseph@fairview5.com>
  L:    linux-hwmon@vger.kernel.org
@@@ -2148,6 -2114,11 +2148,6 @@@ M:     Ludovic Desroches <ludovic.desroches
  S:    Maintained
  F:    drivers/mmc/host/atmel-mci.c
  
 -ATMEL AT91 / AT32 SERIAL DRIVER
 -M:    Nicolas Ferre <nicolas.ferre@atmel.com>
 -S:    Supported
 -F:    drivers/tty/serial/atmel_serial.c
 -
  ATMEL AT91 SAMA5D2-Compatible Shutdown Controller
  M:    Nicolas Ferre <nicolas.ferre@atmel.com>
  S:    Supported
@@@ -2252,9 -2223,9 +2252,9 @@@ S:      Maintaine
  F:    drivers/net/wireless/atmel/atmel*
  
  ATMEL MAXTOUCH DRIVER
 -M:    Nick Dyer <nick.dyer@itdev.co.uk>
 -T:    git git://github.com/atmel-maxtouch/linux.git
 -S:    Supported
 +M:    Nick Dyer <nick@shmanahar.org>
 +T:    git git://github.com/ndyer/linux.git
 +S:    Maintained
  F:    Documentation/devicetree/bindings/input/atmel,maxtouch.txt
  F:    drivers/input/touchscreen/atmel_mxt_ts.c
  F:    include/linux/platform_data/atmel_mxt_ts.h
@@@ -2482,7 -2453,6 +2482,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
  S:    Maintained
  F:    block/
  F:    kernel/trace/blktrace.c
 +F:    lib/sbitmap.c
  
  BLOCK2MTD DRIVER
  M:    Joern Engel <joern@lazybastard.org>
@@@ -2606,13 -2576,6 +2606,13 @@@ F:    arch/arm/mach-bcm/bcm_5301x.
  F:    arch/arm/boot/dts/bcm5301x*.dtsi
  F:    arch/arm/boot/dts/bcm470*
  
 +BROADCOM BCM53573 ARM ARCHITECTURE
 +M:    Rafał Miłecki <rafal@milecki.pl>
 +L:    linux-arm-kernel@lists.infradead.org
 +S:    Maintained
 +F:    arch/arm/boot/dts/bcm53573*
 +F:    arch/arm/boot/dts/bcm47189*
 +
  BROADCOM BCM63XX ARM ARCHITECTURE
  M:    Florian Fainelli <f.fainelli@gmail.com>
  M:    bcm-kernel-feedback-list@broadcom.com
@@@ -2812,7 -2775,7 +2812,7 @@@ L:      linux-media@vger.kernel.or
  W:    https://linuxtv.org
  T:    git git://linuxtv.org/media_tree.git
  S:    Odd fixes
 -F:    Documentation/video4linux/bttv/
 +F:    Documentation/media/v4l-drivers/bttv*
  F:    drivers/media/pci/bt8xx/bttv*
  
  BUSLOGIC SCSI DRIVER
@@@ -2857,7 -2820,7 +2857,7 @@@ M:      Jonathan Corbet <corbet@lwn.net
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  S:    Maintained
 -F:    Documentation/video4linux/cafe_ccic
 +F:    Documentation/media/v4l-drivers/cafe_ccic*
  F:    drivers/media/platform/marvell-ccic/
  
  CAIF NETWORK LAYER
@@@ -2926,14 -2889,6 +2926,14 @@@ S:    Maintaine
  F:    drivers/iio/light/cm*
  F:    Documentation/devicetree/bindings/i2c/trivial-devices.txt
  
 +CAVIUM I2C DRIVER
 +M:    Jan Glauber <jglauber@cavium.com>
 +M:    David Daney <david.daney@cavium.com>
 +W:    http://www.cavium.com
 +S:    Supported
 +F:    drivers/i2c/busses/i2c-octeon*
 +F:    drivers/i2c/busses/i2c-thunderx*
 +
  CAVIUM LIQUIDIO NETWORK DRIVER
  M:     Derek Chickles <derek.chickles@caviumnetworks.com>
  M:     Satanand Burla <satananda.burla@caviumnetworks.com>
@@@ -2959,7 -2914,7 +2959,7 @@@ T:      git git://linuxtv.org/media_tree.gi
  W:    http://linuxtv.org
  S:    Supported
  F:    Documentation/cec.txt
 -F:    Documentation/DocBook/media/v4l/cec*
 +F:    Documentation/media/uapi/cec
  F:    drivers/staging/media/cec/
  F:    drivers/media/cec-edid.c
  F:    drivers/media/rc/keymaps/rc-cec.c
@@@ -3181,7 -3136,7 +3181,7 @@@ L:      cocci@systeme.lip6.fr (moderated fo
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild.git misc
  W:    http://coccinelle.lip6.fr/
  S:    Supported
 -F:    Documentation/coccinelle.txt
 +F:    Documentation/dev-tools/coccinelle.rst
  F:    scripts/coccinelle/
  F:    scripts/coccicheck
  
@@@ -3207,7 -3162,6 +3207,7 @@@ COMMON CLK FRAMEWOR
  M:    Michael Turquette <mturquette@baylibre.com>
  M:    Stephen Boyd <sboyd@codeaurora.org>
  L:    linux-clk@vger.kernel.org
 +Q:    http://patchwork.kernel.org/project/linux-clk/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
  S:    Maintained
  F:    Documentation/devicetree/bindings/clock/
@@@ -3328,7 -3282,6 +3328,7 @@@ L:      linux-pm@vger.kernel.or
  S:    Maintained
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
  T:    git git://git.linaro.org/people/vireshk/linux.git (For ARM Updates)
 +F:    Documentation/cpu-freq/
  F:    drivers/cpufreq/
  F:    include/linux/cpufreq.h
  
@@@ -3447,7 -3400,7 +3447,7 @@@ T:      git git://linuxtv.org/media_tree.gi
  W:    https://linuxtv.org
  W:    http://www.ivtvdriver.org/index.php/Cx18
  S:    Maintained
 -F:    Documentation/video4linux/cx18.txt
 +F:    Documentation/media/v4l-drivers/cx18*
  F:    drivers/media/pci/cx18/
  F:    include/uapi/linux/ivtv*
  
@@@ -3476,7 -3429,7 +3476,7 @@@ L:      linux-media@vger.kernel.or
  W:    https://linuxtv.org
  T:    git git://linuxtv.org/media_tree.git
  S:    Odd fixes
 -F:    Documentation/video4linux/cx88/
 +F:    Documentation/media/v4l-drivers/cx88*
  F:    drivers/media/pci/cx88/
  
  CXD2820R MEDIA DRIVER
@@@ -3509,7 -3462,6 +3509,7 @@@ L:      linux-rdma@vger.kernel.or
  W:    http://www.openfabrics.org
  S:    Supported
  F:    drivers/infiniband/hw/cxgb3/
 +F:    include/uapi/rdma/cxgb3-abi.h
  
  CXGB4 ETHERNET DRIVER (CXGB4)
  M:    Hariprasad S <hariprasad@chelsio.com>
@@@ -3531,7 -3483,6 +3531,7 @@@ L:      linux-rdma@vger.kernel.or
  W:    http://www.openfabrics.org
  S:    Supported
  F:    drivers/infiniband/hw/cxgb4/
 +F:    include/uapi/rdma/cxgb4-abi.h
  
  CXGB4VF ETHERNET DRIVER (CXGB4VF)
  M:    Casey Leedom <leedom@chelsio.com>
@@@ -3542,14 -3493,14 +3542,14 @@@ F:   drivers/net/ethernet/chelsio/cxgb4vf
  
  CXL (IBM Coherent Accelerator Processor Interface CAPI) DRIVER
  M:    Ian Munsie <imunsie@au1.ibm.com>
 -M:    Michael Neuling <mikey@neuling.org>
 +M:    Frederic Barrat <fbarrat@linux.vnet.ibm.com>
  L:    linuxppc-dev@lists.ozlabs.org
  S:    Supported
 +F:    arch/powerpc/platforms/powernv/pci-cxl.c
  F:    drivers/misc/cxl/
  F:    include/misc/cxl*
  F:    include/uapi/misc/cxl.h
  F:    Documentation/powerpc/cxl.txt
 -F:    Documentation/powerpc/cxl.txt
  F:    Documentation/ABI/testing/sysfs-class-cxl
  
  CXLFLASH (IBM Coherent Accelerator Processor Interface CAPI Flash) SCSI DRIVER
@@@ -3812,8 -3763,8 +3812,8 @@@ F:      drivers/leds/leds-da90??.
  F:    drivers/mfd/da903x.c
  F:    drivers/mfd/da90??-*.c
  F:    drivers/mfd/da91??-*.c
 -F:    drivers/power/da9052-battery.c
 -F:    drivers/power/da91??-*.c
 +F:    drivers/power/supply/da9052-battery.c
 +F:    drivers/power/supply/da91??-*.c
  F:    drivers/regulator/da903x.c
  F:    drivers/regulator/da9???-regulator.[ch]
  F:    drivers/rtc/rtc-da90??.c
@@@ -3829,12 -3780,6 +3829,12 @@@ F:    include/linux/regulator/da9211.
  F:    include/sound/da[79]*.h
  F:    sound/soc/codecs/da[79]*.[ch]
  
 +DIAMOND SYSTEMS GPIO-MM GPIO DRIVER
 +M:    William Breathitt Gray <vilhelm.gray@gmail.com>
 +L:    linux-gpio@vger.kernel.org
 +S:    Maintained
 +F:    drivers/gpio/gpio-gpio-mm.c
 +
  DIGI NEO AND CLASSIC PCI PRODUCTS
  M:    Lidza Louina <lidza.louina@gmail.com>
  M:    Mark Hounschell <markh@compro.net>
@@@ -3957,7 -3902,7 +3957,7 @@@ X:      Documentation/devicetree
  X:    Documentation/acpi
  X:    Documentation/power
  X:    Documentation/spi
 -X:    Documentation/DocBook/media
 +X:    Documentation/media
  T:    git git://git.lwn.net/linux.git docs-next
  
  DOUBLETALK DRIVER
@@@ -4064,6 -4009,16 +4064,16 @@@ F:    include/drm/i915
  F:    include/uapi/drm/i915_drm.h
  F:    Documentation/gpu/i915.rst
  
+ INTEL GVT-g DRIVERS (Intel GPU Virtualization)
+ M:      Zhenyu Wang <zhenyuw@linux.intel.com>
+ M:      Zhi Wang <zhi.a.wang@intel.com>
+ L:      igvt-g-dev@lists.01.org
+ L:      intel-gfx@lists.freedesktop.org
+ W:      https://01.org/igvt-g
+ T:      git https://github.com/01org/gvt-linux.git
+ S:      Supported
+ F:      drivers/gpu/drm/i915/gvt/
  DRM DRIVERS FOR ATMEL HLCDC
  M:    Boris Brezillon <boris.brezillon@free-electrons.com>
  L:    dri-devel@lists.freedesktop.org
@@@ -4468,6 -4423,7 +4478,6 @@@ F:      Documentation/filesystems/ecryptfs.t
  F:    fs/ecryptfs/
  
  EDAC-CORE
 -M:    Doug Thompson <dougthompson@xmission.com>
  M:    Borislav Petkov <bp@alien8.de>
  M:    Mauro Carvalho Chehab <mchehab@s-opensource.com>
  M:    Mauro Carvalho Chehab <mchehab@kernel.org>
@@@ -4480,12 -4436,14 +4490,12 @@@ F:   drivers/edac
  F:    include/linux/edac.h
  
  EDAC-AMD64
 -M:    Doug Thompson <dougthompson@xmission.com>
  M:    Borislav Petkov <bp@alien8.de>
  L:    linux-edac@vger.kernel.org
  S:    Maintained
  F:    drivers/edac/amd64_edac*
  
  EDAC-CALXEDA
 -M:    Doug Thompson <dougthompson@xmission.com>
  M:    Robert Richter <rric@kernel.org>
  L:    linux-edac@vger.kernel.org
  S:    Maintained
@@@ -4501,21 -4459,17 +4511,21 @@@ F:   drivers/edac/octeon_edac
  
  EDAC-E752X
  M:    Mark Gross <mark.gross@intel.com>
 -M:    Doug Thompson <dougthompson@xmission.com>
  L:    linux-edac@vger.kernel.org
  S:    Maintained
  F:    drivers/edac/e752x_edac.c
  
  EDAC-E7XXX
 -M:    Doug Thompson <dougthompson@xmission.com>
  L:    linux-edac@vger.kernel.org
  S:    Maintained
  F:    drivers/edac/e7xxx_edac.c
  
 +EDAC-FSL_DDR
 +M:    York Sun <york.sun@nxp.com>
 +L:    linux-edac@vger.kernel.org
 +S:    Maintained
 +F:    drivers/edac/fsl_ddr_edac.*
 +
  EDAC-GHES
  M:    Mauro Carvalho Chehab <mchehab@s-opensource.com>
  M:    Mauro Carvalho Chehab <mchehab@kernel.org>
@@@ -4530,11 -4484,13 +4540,11 @@@ S:   Maintaine
  F:    drivers/edac/i82443bxgx_edac.c
  
  EDAC-I3000
 -M:    Jason Uhlenkott <juhlenko@akamai.com>
  L:    linux-edac@vger.kernel.org
 -S:    Maintained
 +S:    Orphan
  F:    drivers/edac/i3000_edac.c
  
  EDAC-I5000
 -M:    Doug Thompson <dougthompson@xmission.com>
  L:    linux-edac@vger.kernel.org
  S:    Maintained
  F:    drivers/edac/i5000_edac.c
@@@ -4620,9 -4576,8 +4630,9 @@@ F:      sound/usb/misc/ua101.
  
  EXTENSIBLE FIRMWARE INTERFACE (EFI)
  M:    Matt Fleming <matt@codeblueprint.co.uk>
 +M:    Ard Biesheuvel <ard.biesheuvel@linaro.org>
  L:    linux-efi@vger.kernel.org
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/mfleming/efi.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git
  S:    Maintained
  F:    Documentation/efi-stub.txt
  F:    arch/ia64/kernel/efi.c
@@@ -4647,13 -4602,6 +4657,13 @@@ M:    Peter Jones <pjones@redhat.com
  S:    Maintained
  F:    drivers/video/fbdev/efifb.c
  
 +EFI TEST DRIVER
 +L:    linux-efi@vger.kernel.org
 +M:    Ivan Hu <ivan.hu@canonical.com>
 +M:    Matt Fleming <matt@codeblueprint.co.uk>
 +S:    Maintained
 +F:    drivers/firmware/efi/test/
 +
  EFS FILESYSTEM
  W:    http://aeschi.ch.eu.org/efs/
  S:    Orphan
@@@ -4673,7 -4621,6 +4683,7 @@@ W:      https://linuxtv.or
  T:    git git://linuxtv.org/media_tree.git
  S:    Maintained
  F:    drivers/media/usb/em28xx/
 +F:    Documentation/media/v4l-drivers/em28xx*
  
  EMBEDDED LINUX
  M:    Paul Gortmaker <paul.gortmaker@windriver.com>
@@@ -4784,6 -4731,15 +4794,6 @@@ L:     iommu@lists.linux-foundation.or
  S:    Maintained
  F:    drivers/iommu/exynos-iommu.c
  
 -EXYNOS MIPI DISPLAY DRIVERS
 -M:    Inki Dae <inki.dae@samsung.com>
 -M:    Donghwa Lee <dh09.lee@samsung.com>
 -M:    Kyungmin Park <kyungmin.park@samsung.com>
 -L:    linux-fbdev@vger.kernel.org
 -S:    Maintained
 -F:    drivers/video/fbdev/exynos/exynos_mipi*
 -F:    include/video/exynos_mipi*
 -
  EZchip NPS platform support
  M:    Noam Camus <noamc@ezchip.com>
  S:    Supported
@@@ -4913,7 -4869,6 +4923,7 @@@ F:      tools/firewire
  
  FIRMWARE LOADER (request_firmware)
  M:    Ming Lei <ming.lei@canonical.com>
 +M:    Luis R. Rodriguez <mcgrof@kernel.org>
  L:    linux-kernel@vger.kernel.org
  S:    Maintained
  F:    Documentation/firmware_class/
@@@ -4962,9 -4917,12 +4972,9 @@@ F:     drivers/net/wan/dlci.
  F:    drivers/net/wan/sdla.c
  
  FRAMEBUFFER LAYER
 -M:    Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
  M:    Tomi Valkeinen <tomi.valkeinen@ti.com>
  L:    linux-fbdev@vger.kernel.org
 -W:    http://linux-fbdev.sourceforge.net/
  Q:    http://patchwork.kernel.org/project/linux-fbdev/list/
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/plagnioj/linux-fbdev.git
  S:    Maintained
  F:    Documentation/fb/
  F:    drivers/video/
@@@ -5031,13 -4989,6 +5041,13 @@@ F:    drivers/net/ethernet/freescale/fec_p
  F:    drivers/net/ethernet/freescale/fec.h
  F:    Documentation/devicetree/bindings/net/fsl-fec.txt
  
 +FREESCALE QORIQ DPAA FMAN DRIVER
 +M:    Madalin Bucur <madalin.bucur@nxp.com>
 +L:    netdev@vger.kernel.org
 +S:    Maintained
 +F:    drivers/net/ethernet/freescale/fman
 +F:    Documentation/devicetree/bindings/powerpc/fsl/fman.txt
 +
  FREESCALE QUICC ENGINE LIBRARY
  L:    linuxppc-dev@lists.ozlabs.org
  S:    Orphan
@@@ -5138,9 -5089,10 +5148,9 @@@ F:     include/linux/fscrypto.
  
  F2FS FILE SYSTEM
  M:    Jaegeuk Kim <jaegeuk@kernel.org>
 -M:    Changman Lee <cm224.lee@samsung.com>
 -R:    Chao Yu <yuchao0@huawei.com>
 +M:    Chao Yu <yuchao0@huawei.com>
  L:    linux-f2fs-devel@lists.sourceforge.net
 -W:    http://en.wikipedia.org/wiki/F2FS
 +W:    https://f2fs.wiki.kernel.org/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs.git
  S:    Maintained
  F:    Documentation/filesystems/f2fs.txt
@@@ -5202,7 -5154,7 +5212,7 @@@ GCOV BASED KERNEL PROFILIN
  M:    Peter Oberparleiter <oberpar@linux.vnet.ibm.com>
  S:    Maintained
  F:    kernel/gcov/
 -F:    Documentation/gcov.txt
 +F:    Documentation/dev-tools/gcov.rst
  
  GDT SCSI DISK ARRAY CONTROLLER DRIVER
  M:    Achim Leubner <achim_leubner@adaptec.com>
@@@ -5319,13 -5271,6 +5329,13 @@@ L:    linux-input@vger.kernel.or
  S:    Maintained
  F:    drivers/input/touchscreen/goodix.c
  
 +GPIO MOCKUP DRIVER
 +M:    Bamvor Jian Zhang <bamvor.zhangjian@linaro.org>
 +L:    linux-gpio@vger.kernel.org
 +S:    Maintained
 +F:    drivers/gpio/gpio-mockup.c
 +F:    tools/testing/selftests/gpio/
 +
  GPIO SUBSYSTEM
  M:    Linus Walleij <linus.walleij@linaro.org>
  M:    Alexandre Courbot <gnurou@gmail.com>
@@@ -5357,84 -5302,6 +5367,84 @@@ L:    netdev@vger.kernel.or
  S:    Maintained
  F:    drivers/net/ethernet/aeroflex/
  
 +GREYBUS SUBSYSTEM
 +M:    Johan Hovold <johan@kernel.org>
 +M:    Alex Elder <elder@kernel.org>
 +M:    Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 +S:    Maintained
 +F:    drivers/staging/greybus/
 +
 +GREYBUS AUDIO PROTOCOLS DRIVERS
 +M:    Vaibhav Agarwal <vaibhav.sr@gmail.com>
 +M:    Mark Greer <mgreer@animalcreek.com>
 +S:    Maintained
 +F:    drivers/staging/greybus/audio_apbridgea.c
 +F:    drivers/staging/greybus/audio_apbridgea.h
 +F:    drivers/staging/greybus/audio_codec.c
 +F:    drivers/staging/greybus/audio_codec.h
 +F:    drivers/staging/greybus/audio_gb.c
 +F:    drivers/staging/greybus/audio_manager.c
 +F:    drivers/staging/greybus/audio_manager.h
 +F:    drivers/staging/greybus/audio_manager_module.c
 +F:    drivers/staging/greybus/audio_manager_private.h
 +F:    drivers/staging/greybus/audio_manager_sysfs.c
 +F:    drivers/staging/greybus/audio_module.c
 +F:    drivers/staging/greybus/audio_topology.c
 +
 +GREYBUS PROTOCOLS DRIVERS
 +M:    Rui Miguel Silva <rmfrfs@gmail.com>
 +S:    Maintained
 +F:    drivers/staging/greybus/sdio.c
 +F:    drivers/staging/greybus/light.c
 +F:    drivers/staging/greybus/gpio.c
 +F:    drivers/staging/greybus/power_supply.c
 +F:    drivers/staging/greybus/spi.c
 +F:    drivers/staging/greybus/spilib.c
 +
 +GREYBUS PROTOCOLS DRIVERS
 +M:    Bryan O'Donoghue <pure.logic@nexus-software.ie>
 +S:    Maintained
 +F:    drivers/staging/greybus/loopback.c
 +F:    drivers/staging/greybus/timesync.c
 +F:    drivers/staging/greybus/timesync_platform.c
 +
 +GREYBUS PROTOCOLS DRIVERS
 +M:    Viresh Kumar <vireshk@kernel.org>
 +S:    Maintained
 +F:    drivers/staging/greybus/authentication.c
 +F:    drivers/staging/greybus/bootrom.c
 +F:    drivers/staging/greybus/firmware.h
 +F:    drivers/staging/greybus/fw-core.c
 +F:    drivers/staging/greybus/fw-download.c
 +F:    drivers/staging/greybus/fw-managament.c
 +F:    drivers/staging/greybus/greybus_authentication.h
 +F:    drivers/staging/greybus/greybus_firmware.h
 +F:    drivers/staging/greybus/hid.c
 +F:    drivers/staging/greybus/i2c.c
 +F:    drivers/staging/greybus/spi.c
 +F:    drivers/staging/greybus/spilib.c
 +F:    drivers/staging/greybus/spilib.h
 +
 +GREYBUS PROTOCOLS DRIVERS
 +M:    David Lin <dtwlin@gmail.com>
 +S:    Maintained
 +F:    drivers/staging/greybus/uart.c
 +F:    drivers/staging/greybus/log.c
 +
 +GREYBUS PLATFORM DRIVERS
 +M:    Vaibhav Hiremath <hvaibhav.linux@gmail.com>
 +S:    Maintained
 +F:    drivers/staging/greybus/arche-platform.c
 +F:    drivers/staging/greybus/arche-apb-ctrl.c
 +F:    drivers/staging/greybus/arche_platform.h
 +
 +GS1662 VIDEO SERIALIZER
 +M:    Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>
 +L:    linux-media@vger.kernel.org
 +T:    git git://linuxtv.org/media_tree.git
 +S:    Maintained
 +F:    drivers/media/spi/gs1662.c
 +
  GSPCA FINEPIX SUBDRIVER
  M:    Frank Zago <frank@zago.net>
  L:    linux-media@vger.kernel.org
@@@ -5726,14 -5593,6 +5736,14 @@@ S:    Maintaine
  F:    drivers/net/ethernet/hisilicon/
  F:    Documentation/devicetree/bindings/net/hisilicon*.txt
  
 +HISILICON ROCE DRIVER
 +M:    Lijun Ou <oulijun@huawei.com>
 +M:    Wei Hu(Xavier) <xavier.huwei@huawei.com>
 +L:    linux-rdma@vger.kernel.org
 +S:    Maintained
 +F:    drivers/infiniband/hw/hns/
 +F:    Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
 +
  HISILICON SAS Controller
  M:    John Garry <john.garry@huawei.com>
  W:    http://www.hisilicon.com
@@@ -5743,9 -5602,10 +5753,9 @@@ F:     Documentation/devicetree/bindings/sc
  
  HOST AP DRIVER
  M:    Jouni Malinen <j@w1.fi>
 -L:    hostap@shmoo.com (subscribers-only)
  L:    linux-wireless@vger.kernel.org
 -W:    http://hostap.epitest.fi/
 -S:    Maintained
 +W:    http://w1.fi/hostap-driver.html
 +S:    Obsolete
  F:    drivers/net/wireless/intersil/hostap/
  
  HP COMPAQ TC1100 TABLET WMI EXTRAS DRIVER
@@@ -5782,7 -5642,7 +5792,7 @@@ M:      Sebastian Reichel <sre@kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git
  S:    Maintained
  F:    Documentation/ABI/testing/sysfs-bus-hsi
 -F:    Documentation/hsi.txt
 +F:    Documentation/device-drivers/serial-interfaces.rst
  F:    drivers/hsi/
  F:    include/linux/hsi/
  F:    include/uapi/linux/hsi/
@@@ -5810,14 -5670,6 +5820,14 @@@ M:    Nadia Yvette Chambers <nyc@holomorph
  S:    Maintained
  F:    fs/hugetlbfs/
  
 +HVA ST MEDIA DRIVER
 +M:    Jean-Christophe Trotin <jean-christophe.trotin@st.com>
 +L:    linux-media@vger.kernel.org
 +T:    git git://linuxtv.org/media_tree.git
 +W:    https://linuxtv.org
 +S:    Supported
 +F:    drivers/media/platform/sti/hva
 +
  Hyper-V CORE AND DRIVERS
  M:    "K. Y. Srinivasan" <kys@microsoft.com>
  M:    Haiyang Zhang <haiyangz@microsoft.com>
@@@ -5844,8 -5696,6 +5854,8 @@@ S:      Maintaine
  F:    Documentation/i2c/i2c-topology
  F:    Documentation/i2c/muxes/
  F:    Documentation/devicetree/bindings/i2c/i2c-mux*
 +F:    Documentation/devicetree/bindings/i2c/i2c-arb*
 +F:    Documentation/devicetree/bindings/i2c/i2c-gate*
  F:    drivers/i2c/i2c-mux.c
  F:    drivers/i2c/muxes/
  F:    include/linux/i2c-mux.h
@@@ -6132,12 -5982,6 +6142,12 @@@ M:    Stanislaw Gruszka <stf_xl@wp.pl
  S:    Maintained
  F:    drivers/usb/atm/ueagle-atm.c
  
 +IMGTEC ASCII LCD DRIVER
 +M:    Paul Burton <paul.burton@imgtec.com>
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
 +F:    drivers/auxdisplay/img-ascii-lcd.c
 +
  INA209 HARDWARE MONITOR DRIVER
  M:    Guenter Roeck <linux@roeck-us.net>
  L:    linux-hwmon@vger.kernel.org
@@@ -6168,12 -6012,6 +6178,12 @@@ M:    Zubair Lutfullah Kakakhel <Zubair.Ka
  S:    Maintained
  F:    drivers/dma/dma-jz4780.c
  
 +INGENIC JZ4780 NAND DRIVER
 +M:    Harvey Hunt <harveyhuntnexus@gmail.com>
 +L:    linux-mtd@lists.infradead.org
 +S:    Maintained
 +F:    drivers/mtd/nand/jz4780_*
 +
  INTEGRITY MEASUREMENT ARCHITECTURE (IMA)
  M:    Mimi Zohar <zohar@linux.vnet.ibm.com>
  M:    Dmitry Kasatkin <dmitry.kasatkin@gmail.com>
@@@ -6275,13 -6113,6 +6285,13 @@@ T:    git git://git.kernel.org/pub/scm/lin
  S:    Supported
  F:    drivers/idle/intel_idle.c
  
 +INTEL INTEGRATED SENSOR HUB DRIVER
 +M:    Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
 +M:    Jiri Kosina <jikos@kernel.org>
 +L:    linux-input@vger.kernel.org
 +S:    Maintained
 +F:    drivers/hid/intel-ish-hid/
 +
  INTEL PSTATE DRIVER
  M:    Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
  M:    Len Brown <lenb@kernel.org>
@@@ -6449,7 -6280,6 +6459,7 @@@ F:      include/linux/mei_cl_bus.
  F:    drivers/misc/mei/*
  F:    drivers/watchdog/mei_wdt.c
  F:    Documentation/misc-devices/mei/*
 +F:    samples/mei/*
  
  INTEL MIC DRIVERS (mic)
  M:    Sudeep Dutt <sudeep.dutt@intel.com>
@@@ -6636,10 -6466,10 +6646,10 @@@ S:   Maintaine
  F:    drivers/firmware/iscsi_ibft*
  
  ISCSI
 -M:    Mike Christie <michaelc@cs.wisc.edu>
 +M:    Lee Duncan <lduncan@suse.com>
 +M:    Chris Leech <cleech@redhat.com>
  L:    open-iscsi@googlegroups.com
 -W:    www.open-iscsi.org
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/mnc/linux-2.6-iscsi.git
 +W:    www.open-iscsi.com
  S:    Maintained
  F:    drivers/scsi/*iscsi*
  F:    include/scsi/*iscsi*
@@@ -6709,7 -6539,7 +6719,7 @@@ L:      linux-media@vger.kernel.or
  T:    git git://linuxtv.org/media_tree.git
  W:    http://www.ivtvdriver.org
  S:    Maintained
 -F:    Documentation/video4linux/*.ivtv
 +F:    Documentation/media/v4l-drivers/ivtv*
  F:    drivers/media/pci/ivtv/
  F:    include/uapi/linux/ivtv*
  
@@@ -6793,7 -6623,7 +6803,7 @@@ L:      kasan-dev@googlegroups.co
  S:    Maintained
  F:    arch/*/include/asm/kasan.h
  F:    arch/*/mm/kasan_init*
 -F:    Documentation/kasan.txt
 +F:    Documentation/dev-tools/kasan.rst
  F:    include/linux/kasan*.h
  F:    lib/test_kasan.c
  F:    mm/kasan/
@@@ -7009,7 -6839,7 +7019,7 @@@ KMEMCHEC
  M:    Vegard Nossum <vegardno@ifi.uio.no>
  M:    Pekka Enberg <penberg@kernel.org>
  S:    Maintained
 -F:    Documentation/kmemcheck.txt
 +F:    Documentation/dev-tools/kmemcheck.rst
  F:    arch/x86/include/asm/kmemcheck.h
  F:    arch/x86/mm/kmemcheck/
  F:    include/linux/kmemcheck.h
@@@ -7018,7 -6848,7 +7028,7 @@@ F:      mm/kmemcheck.
  KMEMLEAK
  M:    Catalin Marinas <catalin.marinas@arm.com>
  S:    Maintained
 -F:    Documentation/kmemleak.txt
 +F:    Documentation/dev-tools/kmemleak.rst
  F:    include/linux/kmemleak.h
  F:    mm/kmemleak.c
  F:    mm/kmemleak-test.c
@@@ -7217,11 -7047,17 +7227,11 @@@ F:   drivers/lightnvm
  F:    include/linux/lightnvm.h
  F:    include/uapi/linux/lightnvm.h
  
 -LINUX FOR IBM pSERIES (RS/6000)
 -M:    Paul Mackerras <paulus@au.ibm.com>
 -W:    http://www.ibm.com/linux/ltc/projects/ppc
 -S:    Supported
 -F:    arch/powerpc/boot/rs6000.h
 -
  LINUX FOR POWERPC (32-BIT AND 64-BIT)
  M:    Benjamin Herrenschmidt <benh@kernel.crashing.org>
  M:    Paul Mackerras <paulus@samba.org>
  M:    Michael Ellerman <mpe@ellerman.id.au>
 -W:    http://www.penguinppc.org/
 +W:    https://github.com/linuxppc/linux/wiki
  L:    linuxppc-dev@lists.ozlabs.org
  Q:    http://patchwork.ozlabs.org/project/linuxppc-dev/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
@@@ -7236,7 -7072,6 +7246,7 @@@ F:      drivers/net/ethernet/ibm/ibmvnic.
  F:    drivers/pci/hotplug/pnv_php.c
  F:    drivers/pci/hotplug/rpa*
  F:    drivers/scsi/ibmvscsi/
 +F:    tools/testing/selftests/powerpc
  N:    opal
  N:    /pmac
  N:    powermac
@@@ -7293,8 -7128,9 +7303,8 @@@ F:      arch/powerpc/platforms/83xx
  F:    arch/powerpc/platforms/85xx/
  
  LINUX FOR POWERPC PA SEMI PWRFICIENT
 -M:    Olof Johansson <olof@lixom.net>
  L:    linuxppc-dev@lists.ozlabs.org
 -S:    Maintained
 +S:    Orphan
  F:    arch/powerpc/platforms/pasemi/
  F:    drivers/*/*pasemi*
  F:    drivers/*/*/*pasemi*
@@@ -7625,8 -7461,9 +7635,8 @@@ F:      Documentation/hwmon/max2075
  F:    drivers/hwmon/max20751.c
  
  MAX6650 HARDWARE MONITOR AND FAN CONTROLLER DRIVER
 -M:    "Hans J. Koch" <hjk@hansjkoch.de>
  L:    linux-hwmon@vger.kernel.org
 -S:    Maintained
 +S:    Orphan
  F:    Documentation/hwmon/max6650
  F:    drivers/hwmon/max6650.c
  
@@@ -7651,8 -7488,8 +7661,8 @@@ M:      Krzysztof Kozlowski <krzk@kernel.org
  M:    Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
  L:    linux-pm@vger.kernel.org
  S:    Supported
 -F:    drivers/power/max14577_charger.c
 -F:    drivers/power/max77693_charger.c
 +F:    drivers/power/supply/max14577_charger.c
 +F:    drivers/power/supply/max77693_charger.c
  
  MAXIM MAX77802 MULTIFUNCTION PMIC DEVICE DRIVERS
  M:    Javier Martinez Canillas <javier@osg.samsung.com>
@@@ -7697,12 -7534,6 +7707,12 @@@ L:    linux-iio@vger.kernel.or
  S:    Maintained
  F:    drivers/iio/potentiometer/mcp4531.c
  
 +MEASUREMENT COMPUTING CIO-DAC IIO DRIVER
 +M:    William Breathitt Gray <vilhelm.gray@gmail.com>
 +L:    linux-iio@vger.kernel.org
 +S:    Maintained
 +F:    drivers/iio/dac/cio-dac.c
 +
  MEDIA DRIVERS FOR RENESAS - FCP
  M:    Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  L:    linux-media@vger.kernel.org
@@@ -7713,15 -7544,6 +7723,15 @@@ F:    Documentation/devicetree/bindings/me
  F:    drivers/media/platform/rcar-fcp.c
  F:    include/media/rcar-fcp.h
  
 +MEDIA DRIVERS FOR RENESAS - VIN
 +M:    Niklas Söderlund <niklas.soderlund@ragnatech.se>
 +L:    linux-media@vger.kernel.org
 +L:    linux-renesas-soc@vger.kernel.org
 +T:    git git://linuxtv.org/media_tree.git
 +S:    Supported
 +F:    Documentation/devicetree/bindings/media/rcar_vin.txt
 +F:    drivers/media/platform/rcar-vin/
 +
  MEDIA DRIVERS FOR RENESAS - VSP1
  M:    Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  L:    linux-media@vger.kernel.org
@@@ -7799,7 -7621,9 +7809,7 @@@ W:      https://linuxtv.or
  Q:    http://patchwork.kernel.org/project/linux-media/list/
  T:    git git://linuxtv.org/media_tree.git
  S:    Maintained
 -F:    Documentation/dvb/
 -F:    Documentation/video4linux/
 -F:    Documentation/DocBook/media/
 +F:    Documentation/media/
  F:    drivers/media/
  F:    drivers/staging/media/
  F:    include/linux/platform_data/media/
@@@ -7837,13 -7661,6 +7847,13 @@@ F:    Documentation/scsi/megaraid.tx
  F:    drivers/scsi/megaraid.*
  F:    drivers/scsi/megaraid/
  
 +MELFAS MIP4 TOUCHSCREEN DRIVER
 +M:    Sangwon Jee <jeesw@melfas.com>
 +W:    http://www.melfas.com
 +S:    Supported
 +F:    drivers/input/touchscreen/melfas_mip4.c
 +F:    Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt
 +
  MELLANOX ETHERNET DRIVER (mlx4_en)
  M:    Tariq Toukan <tariqt@mellanox.com>
  L:    netdev@vger.kernel.org
@@@ -7869,19 -7686,6 +7879,19 @@@ W:    http://www.mellanox.co
  Q:    http://patchwork.ozlabs.org/project/netdev/list/
  F:    drivers/net/ethernet/mellanox/mlxsw/
  
 +MELLANOX MLXCPLD LED DRIVER
 +M:    Vadim Pasternak <vadimp@mellanox.com>
 +L:    linux-leds@vger.kernel.org
 +S:    Supported
 +F:    drivers/leds/leds-mlxcpld.c
 +F:    Documentation/leds/leds-mlxcpld.txt
 +
 +MELLANOX PLATFORM DRIVER
 +M:      Vadim Pasternak <vadimp@mellanox.com>
 +L:      platform-driver-x86@vger.kernel.org
 +S:      Supported
 +F:      arch/x86/platform/mellanox/mlx-platform.c
 +
  SOFT-ROCE DRIVER (rxe)
  M:    Moni Shoua <monis@mellanox.com>
  L:    linux-rdma@vger.kernel.org
@@@ -7967,20 -7771,6 +7977,20 @@@ T:    git git://git.monstr.eu/linux-2.6-mi
  S:    Supported
  F:    arch/microblaze/
  
 +MICROCHIP / ATMEL AT91 / AT32 SERIAL DRIVER
 +M:    Richard Genoud <richard.genoud@gmail.com>
 +S:    Maintained
 +F:    drivers/tty/serial/atmel_serial.c
 +F:    include/linux/atmel_serial.h
 +
 +MICROCHIP / ATMEL ISC DRIVER
 +M:    Songjun Wu <songjun.wu@microchip.com>
 +L:    linux-media@vger.kernel.org
 +S:    Supported
 +F:    drivers/media/platform/atmel/atmel-isc.c
 +F:    drivers/media/platform/atmel/atmel-isc-regs.h
 +F:    devicetree/bindings/media/atmel-isc.txt
 +
  MICROSOFT SURFACE PRO 3 BUTTON DRIVER
  M:    Chen Yu <yu.c.chen@intel.com>
  L:    platform-driver-x86@vger.kernel.org
@@@ -8029,7 -7819,6 +8039,7 @@@ Q:      http://patchwork.ozlabs.org/project/
  S:    Supported
  F:    drivers/net/ethernet/mellanox/mlx4/
  F:    include/linux/mlx4/
 +F:    include/uapi/rdma/mlx4-abi.h
  
  MELLANOX MLX4 IB driver
  M:    Yishai Hadas <yishaih@mellanox.com>
@@@ -8050,7 -7839,6 +8060,7 @@@ Q:      http://patchwork.ozlabs.org/project/
  S:    Supported
  F:    drivers/net/ethernet/mellanox/mlx5/core/
  F:    include/linux/mlx5/
 +F:    include/uapi/rdma/mlx5-abi.h
  
  MELLANOX MLX5 IB driver
  M:    Matan Barak <matanb@mellanox.com>
@@@ -8069,18 -7857,6 +8079,18 @@@ W:    http://www.melexis.co
  S:    Supported
  F:    drivers/iio/temperature/mlx90614.c
  
 +MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
 +M:    Don Brace <don.brace@microsemi.com>
 +L:    esc.storagedev@microsemi.com
 +L:    linux-scsi@vger.kernel.org
 +S:    Supported
 +F:    drivers/scsi/smartpqi/smartpqi*.[ch]
 +F:    drivers/scsi/smartpqi/Kconfig
 +F:    drivers/scsi/smartpqi/Makefile
 +F:    include/linux/cciss*.h
 +F:    include/uapi/linux/cciss*.h
 +F:    Documentation/scsi/smartpqi.txt
 +
  MN88472 MEDIA DRIVER
  M:    Antti Palosaari <crope@iki.fi>
  L:    linux-media@vger.kernel.org
@@@ -8108,7 -7884,7 +8118,7 @@@ F:      kernel/module.
  MOTION EYE VAIO PICTUREBOOK CAMERA DRIVER
  W:    http://popies.net/meye/
  S:    Orphan
 -F:    Documentation/video4linux/meye.txt
 +F:    Documentation/media/v4l-drivers/meye*
  F:    drivers/media/pci/meye/
  F:    include/uapi/linux/meye.h
  
@@@ -8206,14 -7982,13 +8216,14 @@@ MULTIFUNCTION DEVICES (MFD
  M:    Lee Jones <lee.jones@linaro.org>
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
  S:    Supported
 +F:    Documentation/devicetree/bindings/mfd/
  F:    drivers/mfd/
  F:    include/linux/mfd/
  
  MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
  M:    Ulf Hansson <ulf.hansson@linaro.org>
  L:    linux-mmc@vger.kernel.org
 -T:    git git://git.linaro.org/people/ulf.hansson/mmc.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
  S:    Maintained
  F:    Documentation/devicetree/bindings/mmc/
  F:    drivers/mmc/
@@@ -8293,16 -8068,20 +8303,16 @@@ M:   Michael Schmitz <schmitzmic@gmail.co
  L:    linux-scsi@vger.kernel.org
  S:    Maintained
  F:    Documentation/scsi/g_NCR5380.txt
 -F:    Documentation/scsi/dtc3x80.txt
  F:    drivers/scsi/NCR5380.*
  F:    drivers/scsi/arm/cumana_1.c
  F:    drivers/scsi/arm/oak.c
  F:    drivers/scsi/atari_scsi.*
  F:    drivers/scsi/dmx3191d.c
 -F:    drivers/scsi/dtc.*
  F:    drivers/scsi/g_NCR5380.*
  F:    drivers/scsi/g_NCR5380_mmio.c
  F:    drivers/scsi/mac_scsi.*
 -F:    drivers/scsi/pas16.*
  F:    drivers/scsi/sun3_scsi.*
  F:    drivers/scsi/sun3_scsi_vme.c
 -F:    drivers/scsi/t128.*
  
  NCR DUAL 700 SCSI DRIVER (MICROCHANNEL)
  M:    "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
@@@ -8323,7 -8102,6 +8333,7 @@@ L:      linux-rdma@vger.kernel.or
  W:    http://www.intel.com/Products/Server/Adapters/Server-Cluster/Server-Cluster-overview.htm
  S:    Supported
  F:    drivers/infiniband/hw/nes/
 +F:    include/uapi/rdma/nes-abi.h
  
  NETEM NETWORK EMULATOR
  M:    Stephen Hemminger <stephen@networkplumber.org>
@@@ -8592,11 -8370,11 +8602,11 @@@ R:   Pali Rohár <pali.rohar@gmail.com
  F:    include/linux/power/bq2415x_charger.h
  F:    include/linux/power/bq27xxx_battery.h
  F:    include/linux/power/isp1704_charger.h
 -F:    drivers/power/bq2415x_charger.c
 -F:    drivers/power/bq27xxx_battery.c
 -F:    drivers/power/bq27xxx_battery_i2c.c
 -F:    drivers/power/isp1704_charger.c
 -F:    drivers/power/rx51_battery.c
 +F:    drivers/power/supply/bq2415x_charger.c
 +F:    drivers/power/supply/bq27xxx_battery.c
 +F:    drivers/power/supply/bq27xxx_battery_i2c.c
 +F:    drivers/power/supply/isp1704_charger.c
 +F:    drivers/power/supply/rx51_battery.c
  
  NTB DRIVER CORE
  M:    Jon Mason <jdmason@kudzu.us>
@@@ -8985,7 -8763,7 +8995,7 @@@ F:      drivers/oprofile
  F:    include/linux/oprofile.h
  
  ORACLE CLUSTER FILESYSTEM 2 (OCFS2)
 -M:    Mark Fasheh <mfasheh@suse.com>
 +M:    Mark Fasheh <mfasheh@versity.com>
  M:    Joel Becker <jlbec@evilplan.org>
  L:    ocfs2-devel@oss.oracle.com (moderated for non-subscribers)
  W:    http://ocfs2.wiki.kernel.org
@@@ -9036,13 -8814,15 +9046,13 @@@ S:   Maintaine
  F:    drivers/net/wireless/intersil/p54/
  
  PA SEMI ETHERNET DRIVER
 -M:    Olof Johansson <olof@lixom.net>
  L:    netdev@vger.kernel.org
 -S:    Maintained
 +S:    Orphan
  F:    drivers/net/ethernet/pasemi/*
  
  PA SEMI SMBUS DRIVER
 -M:    Olof Johansson <olof@lixom.net>
  L:    linux-i2c@vger.kernel.org
 -S:    Maintained
 +S:    Orphan
  F:    drivers/i2c/busses/i2c-pasemi.c
  
  PADATA PARALLEL EXECUTION MECHANISM
@@@ -9095,7 -8875,6 +9105,7 @@@ S:      Supporte
  F:    Documentation/virtual/paravirt_ops.txt
  F:    arch/*/kernel/paravirt*
  F:    arch/*/include/asm/paravirt.h
 +F:    include/linux/hypervisor.h
  
  PARIDE DRIVERS FOR PARALLEL PORT IDE DEVICES
  M:    Tim Waugh <tim@cyberelk.net>
@@@ -9204,14 -8983,6 +9214,14 @@@ S:    Maintaine
  F:    Documentation/devicetree/bindings/pci/versatile.txt
  F:    drivers/pci/host/pci-versatile.c
  
 +PCI DRIVER FOR ARMADA 8K
 +M:    Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 +L:    linux-pci@vger.kernel.org
 +L:    linux-arm-kernel@lists.infradead.org
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/pci/pci-armada8k.txt
 +F:    drivers/pci/host/pcie-armada8k.c
 +
  PCI DRIVER FOR APPLIEDMICRO XGENE
  M:    Tanmay Inamdar <tinamdar@apm.com>
  L:    linux-pci@vger.kernel.org
@@@ -9258,7 -9029,6 +9268,7 @@@ M:      Thomas Petazzoni <thomas.petazzoni@f
  L:    linux-pci@vger.kernel.org
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
 +F:    Documentation/devicetree/bindings/pci/aardvark-pci.txt
  F:    drivers/pci/host/pci-aardvark.c
  
  PCI DRIVER FOR NVIDIA TEGRA
@@@ -9300,7 -9070,7 +9310,7 @@@ S:      Maintaine
  F:    drivers/pci/host/*designware*
  
  PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE
 -M:    Joao Pinto <jpinto@synopsys.com>
 +M:    Jose Abreu <Jose.Abreu@synopsys.com>
  L:    linux-pci@vger.kernel.org
  S:    Maintained
  F:    Documentation/devicetree/bindings/pci/designware-pcie.txt
@@@ -9360,15 -9130,6 +9370,15 @@@ S:    Maintaine
  F:    Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
  F:    drivers/pci/host/pcie-hisi.c
  
 +PCIE DRIVER FOR ROCKCHIP
 +M:    Shawn Lin <shawn.lin@rock-chips.com>
 +M:    Wenrui Li <wenrui.li@rock-chips.com>
 +L:    linux-pci@vger.kernel.org
 +L:    linux-rockchip@lists.infradead.org
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/pci/rockchip-pcie.txt
 +F:    drivers/pci/host/pcie-rockchip.c
 +
  PCIE DRIVER FOR QUALCOMM MSM
  M:     Stanimir Varbanov <svarbanov@mm-sol.com>
  L:     linux-pci@vger.kernel.org
@@@ -9391,7 -9152,6 +9401,7 @@@ W:      http://lists.infradead.org/mailman/l
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git
  S:    Maintained
  F:    Documentation/pcmcia/
 +F:    tools/pcmcia/
  F:    drivers/pcmcia/
  F:    include/pcmcia/
  
@@@ -9523,8 -9283,6 +9533,8 @@@ L:      linux-arm-kernel@lists.infradead.or
  L:    linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
  S:    Maintained
  F:    drivers/pinctrl/samsung/
 +F:    include/dt-bindings/pinctrl/samsung.h
 +F:    Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
  
  PIN CONTROLLER - SINGLE
  M:    Tony Lindgren <tony@atomide.com>
@@@ -9615,12 -9373,16 +9625,12 @@@ F:   drivers/powercap
  
  POWER SUPPLY CLASS/SUBSYSTEM and DRIVERS
  M:    Sebastian Reichel <sre@kernel.org>
 -M:    Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
 -M:    David Woodhouse <dwmw2@infradead.org>
  L:    linux-pm@vger.kernel.org
 -T:    git git://git.infradead.org/battery-2.6.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git
  S:    Maintained
 -F:    Documentation/devicetree/bindings/power/
 -F:    Documentation/devicetree/bindings/power_supply/
 +F:    Documentation/devicetree/bindings/power/supply/
  F:    include/linux/power_supply.h
 -F:    drivers/power/
 -X:    drivers/power/avs/
 +F:    drivers/power/supply/
  
  POWER STATE COORDINATION INTERFACE (PSCI)
  M:    Mark Rutland <mark.rutland@arm.com>
@@@ -9775,7 -9537,7 +9785,7 @@@ L:      linux-media@vger.kernel.or
  W:    http://www.isely.net/pvrusb2/
  T:    git git://linuxtv.org/media_tree.git
  S:    Maintained
 -F:    Documentation/video4linux/README.pvrusb2
 +F:    Documentation/media/v4l-drivers/pvrusb2*
  F:    drivers/media/usb/pvrusb2/
  
  PWC WEBCAM DRIVER
@@@ -9956,12 -9718,6 +9966,12 @@@ T:    git git://git.kernel.org/pub/scm/lin
  S:    Supported
  F:    drivers/net/wireless/ath/ath10k/
  
 +QUALCOMM EMAC GIGABIT ETHERNET DRIVER
 +M:    Timur Tabi <timur@codeaurora.org>
 +L:    netdev@vger.kernel.org
 +S:    Supported
 +F:    drivers/net/ethernet/qualcomm/emac/
 +
  QUALCOMM HEXAGON ARCHITECTURE
  M:    Richard Kuo <rkuo@codeaurora.org>
  L:    linux-hexagon@vger.kernel.org
@@@ -10182,12 -9938,6 +10192,12 @@@ F:  drivers/rpmsg
  F:    Documentation/rpmsg.txt
  F:    include/linux/rpmsg.h
  
 +RENESAS CLOCK DRIVERS
 +M:    Geert Uytterhoeven <geert+renesas@glider.be>
 +L:    linux-renesas-soc@vger.kernel.org
 +S:    Supported
 +F:    drivers/clk/renesas/
 +
  RENESAS ETHERNET DRIVERS
  R:    Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
  L:    netdev@vger.kernel.org
@@@ -10223,7 -9973,6 +10233,7 @@@ F:    net/rfkill
  
  RHASHTABLE
  M:    Thomas Graf <tgraf@suug.ch>
 +M:    Herbert Xu <herbert@gondor.apana.org.au>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    lib/rhashtable.c
@@@ -10367,8 -10116,8 +10377,8 @@@ S:   Supporte
  F:    drivers/s390/cio/
  
  S390 DASD DRIVER
 -M:    Stefan Weinhuber <wein@de.ibm.com>
 -M:    Stefan Haberland <stefan.haberland@de.ibm.com>
 +M:    Stefan Haberland <sth@linux.vnet.ibm.com>
 +M:    Jan Hoeppner <hoeppner@linux.vnet.ibm.com>
  L:    linux-s390@vger.kernel.org
  W:    http://www.ibm.com/developerworks/linux/linux390/
  S:    Supported
@@@ -10442,7 -10191,7 +10452,7 @@@ L:   linux-media@vger.kernel.or
  W:    https://linuxtv.org
  T:    git git://linuxtv.org/media_tree.git
  S:    Odd fixes
 -F:    Documentation/video4linux/*.saa7134
 +F:    Documentation/media/v4l-drivers/saa7134*
  F:    drivers/media/pci/saa7134/
  
  SAA7146 VIDEO4LINUX-2 DRIVER
@@@ -10532,12 -10281,9 +10542,12 @@@ F: drivers/nfc/s3fwrn
  SAMSUNG SOC CLOCK DRIVERS
  M:    Sylwester Nawrocki <s.nawrocki@samsung.com>
  M:    Tomasz Figa <tomasz.figa@gmail.com>
 +M:    Chanwoo Choi <cw00.choi@samsung.com>
  S:    Supported
  L:    linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
  F:    drivers/clk/samsung/
 +F:    include/dt-bindings/clock/exynos*.h
 +F:    Documentation/devicetree/bindings/clock/exynos*.txt
  
  SAMSUNG SPI DRIVERS
  M:    Kukjin Kim <kgene@kernel.org>
@@@ -10587,13 -10333,6 +10597,13 @@@ S: Maintaine
  F:    Documentation/devicetree/bindings/serial/
  F:    drivers/tty/serial/
  
 +STI CEC DRIVER
 +M:    Benjamin Gaignard <benjamin.gaignard@linaro.org>
 +L:    kernel@stlinux.com
 +S:    Maintained
 +F:    drivers/staging/media/st-cec/
 +F:    Documentation/devicetree/bindings/media/stih-cec.txt
 +
  SYNOPSYS DESIGNWARE DMAC DRIVER
  M:    Viresh Kumar <vireshk@kernel.org>
  M:    Andy Shevchenko <andriy.shevchenko@linux.intel.com>
@@@ -10642,8 -10381,8 +10652,8 @@@ F:   drivers/thunderbolt
  TI BQ27XXX POWER SUPPLY DRIVER
  R:    Andrew F. Davis <afd@ti.com>
  F:    include/linux/power/bq27xxx_battery.h
 -F:    drivers/power/bq27xxx_battery.c
 -F:    drivers/power/bq27xxx_battery_i2c.c
 +F:    drivers/power/supply/bq27xxx_battery.c
 +F:    drivers/power/supply/bq27xxx_battery_i2c.c
  
  TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
  M:    John Stultz <john.stultz@linaro.org>
@@@ -10871,12 -10610,12 +10881,12 @@@ S:        Maintaine
  F:    drivers/misc/phantom.c
  F:    include/uapi/linux/phantom.h
  
 -SERVER ENGINES 10Gbps iSCSI - BladeEngine 2 DRIVER
 -M:    Jayamohan Kallickal <jayamohan.kallickal@avagotech.com>
 -M:    Ketan Mukadam <ketan.mukadam@avagotech.com>
 -M:    John Soni Jose <sony.john@avagotech.com>
 +Emulex 10Gbps iSCSI - OneConnect DRIVER
 +M:    Subbu Seetharaman <subbu.seetharaman@broadcom.com>
 +M:    Ketan Mukadam <ketan.mukadam@broadcom.com>
 +M:    Jitendra Bhivare <jitendra.bhivare@broadcom.com>
  L:    linux-scsi@vger.kernel.org
 -W:    http://www.avagotech.com
 +W:    http://www.broadcom.com
  S:    Supported
  F:    drivers/scsi/be2iscsi/
  
@@@ -10898,7 -10637,6 +10908,7 @@@ L:   linux-rdma@vger.kernel.or
  W:    http://www.emulex.com
  S:    Supported
  F:    drivers/infiniband/hw/ocrdma/
 +F:    include/uapi/rdma/ocrdma-abi.h
  
  SFC NETWORK DRIVER
  M:    Solarflare linux maintainers <linux-net-drivers@solarflare.com>
@@@ -11404,7 -11142,6 +11414,7 @@@ F:   Documentation/spi
  F:    drivers/spi/
  F:    include/linux/spi/
  F:    include/uapi/linux/spi/
 +F:    tools/spi/
  
  SPIDERNET NETWORK DRIVER for CELL
  M:    Ishizaki Kou <kou.ishizaki@toshiba.co.jp>
@@@ -11475,7 -11212,6 +11485,7 @@@ F:   drivers/staging/media/lirc
  STAGING - LUSTRE PARALLEL FILESYSTEM
  M:    Oleg Drokin <oleg.drokin@intel.com>
  M:    Andreas Dilger <andreas.dilger@intel.com>
 +M:    James Simmons <jsimmons@infradead.org>
  L:    lustre-devel@lists.lustre.org (moderated for non-subscribers)
  W:    http://wiki.lustre.org/
  S:    Maintained
@@@ -11502,6 -11238,13 +11512,6 @@@ M:  Florian Schilhabel <florian.c.schilh
  S:    Odd Fixes
  F:    drivers/staging/rtl8712/
  
 -STAGING - REALTEK RTL8723U WIRELESS DRIVER
 -M:    Larry Finger <Larry.Finger@lwfinger.net>
 -M:    Jes Sorensen <Jes.Sorensen@redhat.com>
 -L:    linux-wireless@vger.kernel.org
 -S:    Maintained
 -F:    drivers/staging/rtl8723au/
 -
  STAGING - SILICON MOTION SM750 FRAME BUFFER DRIVER
  M:    Sudip Mukherjee <sudipm.mukherjee@gmail.com>
  M:    Teddy Wang <teddy.wang@siliconmotion.com>
@@@ -11641,14 -11384,6 +11651,14 @@@ T: git git://git.kernel.org/pub/scm/lin
  S:    Supported
  F:    drivers/mfd/syscon.c
  
 +SYSTEM RESET/SHUTDOWN DRIVERS
 +M:    Sebastian Reichel <sre@kernel.org>
 +L:    linux-pm@vger.kernel.org
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git
 +S:    Maintained
 +F:    Documentation/devicetree/bindings/power/reset/
 +F:    drivers/power/reset/
 +
  SYSV FILESYSTEM
  M:    Christoph Hellwig <hch@infradead.org>
  S:    Maintained
@@@ -11909,7 -11644,7 +11919,7 @@@ F:   Documentation/devicetree/bindings/th
  THERMAL/CPU_COOLING
  M:    Amit Daniel Kachhap <amit.kachhap@gmail.com>
  M:    Viresh Kumar <viresh.kumar@linaro.org>
 -M:    Javi Merino <javi.merino@arm.com>
 +M:    Javi Merino <javi.merino@kernel.org>
  L:    linux-pm@vger.kernel.org
  S:    Supported
  F:    Documentation/thermal/cpu-cooling-api.txt
@@@ -11997,7 -11732,7 +12007,7 @@@ F:   include/linux/platform_data/lp855x.
  TI LP8727 CHARGER DRIVER
  M:    Milo Kim <milo.kim@ti.com>
  S:    Maintained
 -F:    drivers/power/lp8727_charger.c
 +F:    drivers/power/supply/lp8727_charger.c
  F:    include/linux/platform_data/lp8727.h
  
  TI LP8788 MFD DRIVER
@@@ -12006,7 -11741,7 +12016,7 @@@ S:   Maintaine
  F:    drivers/iio/adc/lp8788_adc.c
  F:    drivers/leds/leds-lp8788.c
  F:    drivers/mfd/lp8788*.c
 -F:    drivers/power/lp8788-charger.c
 +F:    drivers/power/supply/lp8788-charger.c
  F:    drivers/regulator/lp8788-*.c
  F:    include/linux/mfd/lp8788*.h
  
@@@ -12158,15 -11893,6 +12168,15 @@@ W: https://linuxtv.or
  T:    git git://linuxtv.org/media_tree.git
  S:    Odd fixes
  F:    drivers/media/usb/tm6000/
 +F:    Documentation/media/v4l-drivers/tm6000*
 +
 +TW5864 VIDEO4LINUX DRIVER
 +M:    Bluecherry Maintainers <maintainers@bluecherrydvr.com>
 +M:    Andrey Utkin <andrey.utkin@corp.bluecherry.net>
 +M:    Andrey Utkin <andrey_utkin@fastmail.com>
 +L:    linux-media@vger.kernel.org
 +S:    Supported
 +F:    drivers/media/pci/tw5864/
  
  TW68 VIDEO4LINUX DRIVER
  M:    Hans Verkuil <hverkuil@xs4all.nl>
@@@ -12284,6 -12010,12 +12294,6 @@@ S:  Maintaine
  F:    drivers/tc/
  F:    include/linux/tc.h
  
 -U14-34F SCSI DRIVER
 -M:    Dario Ballabio <ballabio_dario@emc.com>
 -L:    linux-scsi@vger.kernel.org
 -S:    Maintained
 -F:    drivers/scsi/u14-34f.c
 -
  UBI FILE SYSTEM (UBIFS)
  M:    Richard Weinberger <richard@nod.at>
  M:    Artem Bityutskiy <dedekind1@gmail.com>
@@@ -12479,7 -12211,7 +12489,7 @@@ S:   Maintaine
  F:    drivers/net/usb/lan78xx.*
  
  USB MASS STORAGE DRIVER
 -M:    Matthew Dharm <mdharm-usb@one-eyed-alien.net>
 +M:    Alan Stern <stern@rowland.harvard.edu>
  L:    linux-usb@vger.kernel.org
  L:    usb-storage@lists.one-eyed-alien.net
  S:    Maintained
@@@ -12563,7 -12295,6 +12573,7 @@@ F:   drivers/net/usb/rtl8150.
  USB SERIAL SUBSYSTEM
  M:    Johan Hovold <johan@kernel.org>
  L:    linux-usb@vger.kernel.org
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git
  S:    Maintained
  F:    Documentation/usb/usb-serial.txt
  F:    drivers/usb/serial/
@@@ -12577,7 -12308,6 +12587,7 @@@ F:   drivers/net/usb/smsc75xx.
  
  USB SMSC95XX ETHERNET DRIVER
  M:    Steve Glendinning <steve.glendinning@shawell.net>
 +M:    Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    drivers/net/usb/smsc95xx.*
@@@ -12659,7 -12389,7 +12669,7 @@@ L:   linux-media@vger.kernel.or
  T:    git git://linuxtv.org/media_tree.git
  W:    http://royale.zerezo.com/zr364xx/
  S:    Maintained
 -F:    Documentation/video4linux/zr364xx.txt
 +F:    Documentation/media/v4l-drivers/zr364xx*
  F:    drivers/media/usb/zr364xx/
  
  ULPI BUS
@@@ -12684,6 -12414,7 +12694,6 @@@ F:   fs/hostfs
  F:    fs/hppfs/
  
  USERSPACE I/O (UIO)
 -M:    "Hans J. Koch" <hjk@hansjkoch.de>
  M:    Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  S:    Maintained
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
@@@ -13011,6 -12742,12 +13021,6 @@@ F:  drivers/watchdog
  F:    include/linux/watchdog.h
  F:    include/uapi/linux/watchdog.h
  
 -WD7000 SCSI DRIVER
 -M:    Miroslav Zagorac <zaga@fly.cc.fer.hr>
 -L:    linux-scsi@vger.kernel.org
 -S:    Maintained
 -F:    drivers/scsi/wd7000.c
 -
  WIIMOTE HID DRIVER
  M:    David Herrmann <dh.herrmann@googlemail.com>
  L:    linux-input@vger.kernel.org
@@@ -13080,7 -12817,7 +13090,7 @@@ F:   drivers/input/touchscreen/wm97*.
  F:    drivers/mfd/arizona*
  F:    drivers/mfd/wm*.c
  F:    drivers/mfd/cs47l24*
 -F:    drivers/power/wm83*.c
 +F:    drivers/power/supply/wm83*.c
  F:    drivers/rtc/rtc-wm83*.c
  F:    drivers/regulator/wm8*.c
  F:    drivers/video/backlight/wm83*_bl.c
@@@ -13195,7 -12932,6 +13205,7 @@@ F:   arch/arm64/include/asm/xen
  
  XEN NETWORK BACKEND DRIVER
  M:    Wei Liu <wei.liu2@citrix.com>
 +M:    Paul Durrant <paul.durrant@citrix.com>
  L:    xen-devel@lists.xenproject.org (moderated for non-subscribers)
  L:    netdev@vger.kernel.org
  S:    Supported
@@@ -13233,10 -12969,11 +13243,10 @@@ F:        arch/x86/xen/*swiotlb
  F:    drivers/xen/*swiotlb*
  
  XFS FILESYSTEM
 -P:    Silicon Graphics Inc
  M:    Dave Chinner <david@fromorbit.com>
 -M:    xfs@oss.sgi.com
 -L:    xfs@oss.sgi.com
 -W:    http://oss.sgi.com/projects/xfs
 +M:    linux-xfs@vger.kernel.org
 +L:    linux-xfs@vger.kernel.org
 +W:    http://xfs.org/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/dgc/linux-xfs.git
  S:    Supported
  F:    Documentation/filesystems/xfs.txt
index 6c7bb87f764e3b2a0c2fac16ce8e2b374d570421,dc057c770146931a173ef86709eaec70cd3993d3..20638d22bbad1eae081039fda72a641fc391d3ad
@@@ -79,10 -79,8 +79,8 @@@ static int i915_capabilities(struct seq
        seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
        seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
- #define SEP_SEMICOLON ;
-       DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
+       DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  #undef PRINT_FLAG
- #undef SEP_SEMICOLON
  
        return 0;
  }
@@@ -109,7 -107,7 +107,7 @@@ static char get_tiling_flag(struct drm_
  
  static char get_global_flag(struct drm_i915_gem_object *obj)
  {
-       return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
+       return obj->fault_mappable ? 'g' : ' ';
  }
  
  static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
@@@ -152,7 -150,7 +150,7 @@@ describe_obj(struct seq_file *m, struc
                   obj->base.size / 1024,
                   obj->base.read_domains,
                   obj->base.write_domain);
-       for_each_engine_id(engine, dev_priv, id)
+       for_each_engine(engine, dev_priv, id)
                seq_printf(m, "%x ",
                           i915_gem_active_get_seqno(&obj->last_read[id],
                                                     &obj->base.dev->struct_mutex));
        }
        if (obj->stolen)
                seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
-       if (obj->pin_display || obj->fault_mappable) {
-               char s[3], *t = s;
-               if (obj->pin_display)
-                       *t++ = 'p';
-               if (obj->fault_mappable)
-                       *t++ = 'f';
-               *t = '\0';
-               seq_printf(m, " (%s mappable)", s);
-       }
  
        engine = i915_gem_active_get_engine(&obj->last_write,
                                            &dev_priv->drm.struct_mutex);
@@@ -334,11 -323,12 +323,12 @@@ static void print_batch_pool_stats(stru
        struct drm_i915_gem_object *obj;
        struct file_stats stats;
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int j;
  
        memset(&stats, 0, sizeof(stats));
  
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
                        list_for_each_entry(obj,
                                            &engine->batch_pool.cache_list[j],
@@@ -402,7 -392,7 +392,7 @@@ static int i915_gem_object_info(struct 
        if (ret)
                return ret;
  
-       seq_printf(m, "%u objects, %zu bytes\n",
+       seq_printf(m, "%u objects, %llu bytes\n",
                   dev_priv->mm.object_count,
                   dev_priv->mm.object_memory);
  
@@@ -607,6 -597,7 +597,7 @@@ static int i915_gem_batch_pool_info(str
        struct drm_device *dev = &dev_priv->drm;
        struct drm_i915_gem_object *obj;
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int total = 0;
        int ret, j;
  
        if (ret)
                return ret;
  
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
                        int count;
  
        return 0;
  }
  
+ static void print_request(struct seq_file *m,
+                         struct drm_i915_gem_request *rq,
+                         const char *prefix)
+ {
+       struct pid *pid = rq->ctx->pid;
+       struct task_struct *task;
+       rcu_read_lock();
+       task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
+       seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
+                  rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
+                  jiffies_to_msecs(jiffies - rq->emitted_jiffies),
+                  task ? task->comm : "<unknown>",
+                  task ? task->pid : -1);
+       rcu_read_unlock();
+ }
  static int i915_gem_request_info(struct seq_file *m, void *data)
  {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
        struct drm_device *dev = &dev_priv->drm;
-       struct intel_engine_cs *engine;
        struct drm_i915_gem_request *req;
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int ret, any;
  
        ret = mutex_lock_interruptible(&dev->struct_mutex);
                return ret;
  
        any = 0;
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                int count;
  
                count = 0;
                        continue;
  
                seq_printf(m, "%s requests: %d\n", engine->name, count);
-               list_for_each_entry(req, &engine->request_list, link) {
-                       struct pid *pid = req->ctx->pid;
-                       struct task_struct *task;
-                       rcu_read_lock();
-                       task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
-                       seq_printf(m, "    %x @ %d: %s [%d]\n",
-                                  req->fence.seqno,
-                                  (int) (jiffies - req->emitted_jiffies),
-                                  task ? task->comm : "<unknown>",
-                                  task ? task->pid : -1);
-                       rcu_read_unlock();
-               }
+               list_for_each_entry(req, &engine->request_list, link)
+                       print_request(m, req, "    ");
  
                any++;
        }
@@@ -715,8 -713,9 +713,9 @@@ static int i915_gem_seqno_info(struct s
  {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
  
-       for_each_engine(engine, dev_priv)
+       for_each_engine(engine, dev_priv, id)
                i915_ring_seqno_info(m, engine);
  
        return 0;
@@@ -727,6 -726,7 +726,7 @@@ static int i915_interrupt_info(struct s
  {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int i, pipe;
  
        intel_runtime_pm_get(dev_priv);
                seq_printf(m, "Graphics Interrupt mask:         %08x\n",
                           I915_READ(GTIMR));
        }
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                if (INTEL_GEN(dev_priv) >= 6) {
                        seq_printf(m,
                                   "Graphics Interrupt mask (%s):       %08x\n",
@@@ -943,7 -943,7 +943,7 @@@ static int i915_hws_info(struct seq_fil
        const u32 *hws;
        int i;
  
-       engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
+       engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
        hws = engine->status_page.page_addr;
        if (hws == NULL)
                return 0;
        return 0;
  }
  
+ #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
  static ssize_t
  i915_error_state_write(struct file *filp,
                       const char __user *ubuf,
@@@ -1038,6 -1040,8 +1040,8 @@@ static const struct file_operations i91
        .release = i915_error_state_release,
  };
  
+ #endif
  static int
  i915_next_seqno_get(void *data, u64 *val)
  {
        return ret;
  }
  
+ static void i915_instdone_info(struct drm_i915_private *dev_priv,
+                              struct seq_file *m,
+                              struct intel_instdone *instdone)
+ {
+       int slice;
+       int subslice;
+       seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
+                  instdone->instdone);
+       if (INTEL_GEN(dev_priv) <= 3)
+               return;
+       seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
+                  instdone->slice_common);
+       if (INTEL_GEN(dev_priv) <= 6)
+               return;
+       for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+               seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
+                          slice, subslice, instdone->sampler[slice][subslice]);
+       for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+               seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
+                          slice, subslice, instdone->row[slice][subslice]);
+ }
  static int i915_hangcheck_info(struct seq_file *m, void *unused)
  {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
        struct intel_engine_cs *engine;
        u64 acthd[I915_NUM_ENGINES];
        u32 seqno[I915_NUM_ENGINES];
-       u32 instdone[I915_NUM_INSTDONE_REG];
+       struct intel_instdone instdone;
        enum intel_engine_id id;
-       int j;
  
        if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
                seq_printf(m, "Wedged\n");
  
        intel_runtime_pm_get(dev_priv);
  
-       for_each_engine_id(engine, dev_priv, id) {
+       for_each_engine(engine, dev_priv, id) {
                acthd[id] = intel_engine_get_active_head(engine);
                seqno[id] = intel_engine_get_seqno(engine);
        }
  
-       i915_get_extra_instdone(dev_priv, instdone);
+       intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
  
        intel_runtime_pm_put(dev_priv);
  
        } else
                seq_printf(m, "Hangcheck inactive\n");
  
-       for_each_engine_id(engine, dev_priv, id) {
+       for_each_engine(engine, dev_priv, id) {
+               struct intel_breadcrumbs *b = &engine->breadcrumbs;
+               struct rb_node *rb;
                seq_printf(m, "%s:\n", engine->name);
                seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
                           engine->hangcheck.seqno,
                           yesno(intel_engine_has_waiter(engine)),
                           yesno(test_bit(engine->id,
                                          &dev_priv->gpu_error.missed_irq_rings)));
+               spin_lock(&b->lock);
+               for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
+                       struct intel_wait *w = container_of(rb, typeof(*w), node);
+                       seq_printf(m, "\t%s [%d] waiting for %x\n",
+                                  w->tsk->comm, w->tsk->pid, w->seqno);
+               }
+               spin_unlock(&b->lock);
                seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
                           (long long)engine->hangcheck.acthd,
                           (long long)acthd[id]);
                seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
  
                if (engine->id == RCS) {
-                       seq_puts(m, "\tinstdone read =");
-                       for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
-                               seq_printf(m, " 0x%08x", instdone[j]);
+                       seq_puts(m, "\tinstdone read =\n");
  
-                       seq_puts(m, "\n\tinstdone accu =");
+                       i915_instdone_info(dev_priv, m, &instdone);
  
-                       for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
-                               seq_printf(m, " 0x%08x",
-                                          engine->hangcheck.instdone[j]);
+                       seq_puts(m, "\tinstdone accu =\n");
  
-                       seq_puts(m, "\n");
+                       i915_instdone_info(dev_priv, m,
+                                          &engine->hangcheck.instdone);
                }
        }
  
@@@ -1635,7 -1674,8 +1674,8 @@@ static int i915_fbc_status(struct seq_f
                seq_printf(m, "FBC disabled: %s\n",
                           dev_priv->fbc.no_fbc_reason);
  
-       if (INTEL_GEN(dev_priv) >= 7)
+       if (intel_fbc_is_active(dev_priv) &&
+           INTEL_GEN(dev_priv) >= 7)
                seq_printf(m, "Compressing: %s\n",
                           yesno(I915_READ(FBC_STATUS2) &
                                 FBC_COMPRESSION_MASK));
@@@ -1909,6 -1949,7 +1949,7 @@@ static int i915_context_status(struct s
        struct drm_device *dev = &dev_priv->drm;
        struct intel_engine_cs *engine;
        struct i915_gem_context *ctx;
+       enum intel_engine_id id;
        int ret;
  
        ret = mutex_lock_interruptible(&dev->struct_mutex);
                seq_putc(m, ctx->remap_slice ? 'R' : 'r');
                seq_putc(m, '\n');
  
-               for_each_engine(engine, dev_priv) {
+               for_each_engine(engine, dev_priv, id) {
                        struct intel_context *ce = &ctx->engine[engine->id];
  
                        seq_printf(m, "%s: ", engine->name);
@@@ -2002,6 -2043,7 +2043,7 @@@ static int i915_dump_lrc(struct seq_fil
        struct drm_device *dev = &dev_priv->drm;
        struct intel_engine_cs *engine;
        struct i915_gem_context *ctx;
+       enum intel_engine_id id;
        int ret;
  
        if (!i915.enable_execlists) {
                return ret;
  
        list_for_each_entry(ctx, &dev_priv->context_list, link)
-               for_each_engine(engine, dev_priv)
+               for_each_engine(engine, dev_priv, id)
                        i915_dump_lrc_obj(m, ctx, engine);
  
        mutex_unlock(&dev->struct_mutex);
        return 0;
  }
  
- static int i915_execlists(struct seq_file *m, void *data)
- {
-       struct drm_i915_private *dev_priv = node_to_i915(m->private);
-       struct drm_device *dev = &dev_priv->drm;
-       struct intel_engine_cs *engine;
-       u32 status_pointer;
-       u8 read_pointer;
-       u8 write_pointer;
-       u32 status;
-       u32 ctx_id;
-       struct list_head *cursor;
-       int i, ret;
-       if (!i915.enable_execlists) {
-               seq_puts(m, "Logical Ring Contexts are disabled\n");
-               return 0;
-       }
-       ret = mutex_lock_interruptible(&dev->struct_mutex);
-       if (ret)
-               return ret;
-       intel_runtime_pm_get(dev_priv);
-       for_each_engine(engine, dev_priv) {
-               struct drm_i915_gem_request *head_req = NULL;
-               int count = 0;
-               seq_printf(m, "%s\n", engine->name);
-               status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
-               ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
-               seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
-                          status, ctx_id);
-               status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
-               seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
-               read_pointer = GEN8_CSB_READ_PTR(status_pointer);
-               write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
-               if (read_pointer > write_pointer)
-                       write_pointer += GEN8_CSB_ENTRIES;
-               seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
-                          read_pointer, write_pointer);
-               for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
-                       status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
-                       ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
-                       seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
-                                  i, status, ctx_id);
-               }
-               spin_lock_bh(&engine->execlist_lock);
-               list_for_each(cursor, &engine->execlist_queue)
-                       count++;
-               head_req = list_first_entry_or_null(&engine->execlist_queue,
-                                                   struct drm_i915_gem_request,
-                                                   execlist_link);
-               spin_unlock_bh(&engine->execlist_lock);
-               seq_printf(m, "\t%d requests in queue\n", count);
-               if (head_req) {
-                       seq_printf(m, "\tHead request context: %u\n",
-                                  head_req->ctx->hw_id);
-                       seq_printf(m, "\tHead request tail: %u\n",
-                                  head_req->tail);
-               }
-               seq_putc(m, '\n');
-       }
-       intel_runtime_pm_put(dev_priv);
-       mutex_unlock(&dev->struct_mutex);
-       return 0;
- }
  static const char *swizzle_string(unsigned swizzle)
  {
        switch (swizzle) {
@@@ -2201,14 -2165,15 +2165,15 @@@ static int per_file_ctx(int id, void *p
  static void gen8_ppgtt_info(struct seq_file *m,
                            struct drm_i915_private *dev_priv)
  {
-       struct intel_engine_cs *engine;
        struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int i;
  
        if (!ppgtt)
                return;
  
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                seq_printf(m, "%s\n", engine->name);
                for (i = 0; i < 4; i++) {
                        u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
@@@ -2223,11 -2188,12 +2188,12 @@@ static void gen6_ppgtt_info(struct seq_
                            struct drm_i915_private *dev_priv)
  {
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
  
        if (IS_GEN6(dev_priv))
                seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                seq_printf(m, "%s\n", engine->name);
                if (IS_GEN7(dev_priv))
                        seq_printf(m, "GFX_MODE: 0x%08x\n",
@@@ -2296,9 -2262,10 +2262,10 @@@ out_unlock
  static int count_irq_waiters(struct drm_i915_private *i915)
  {
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int count = 0;
  
-       for_each_engine(engine, i915)
+       for_each_engine(engine, i915, id)
                count += intel_engine_has_waiter(engine);
  
        return count;
@@@ -2461,7 -2428,7 +2428,7 @@@ static void i915_guc_client_info(struc
        seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
        seq_printf(m, "\tLast submission result: %d\n", client->retcode);
  
-       for_each_engine_id(engine, dev_priv, id) {
+       for_each_engine(engine, dev_priv, id) {
                u64 submissions = client->submissions[id];
                tot += submissions;
                seq_printf(m, "\tSubmissions: %llu %s\n",
@@@ -2504,7 -2471,7 +2471,7 @@@ static int i915_guc_info(struct seq_fil
        seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
  
        seq_printf(m, "\nGuC submissions:\n");
-       for_each_engine_id(engine, dev_priv, id) {
+       for_each_engine(engine, dev_priv, id) {
                u64 submissions = guc.submissions[id];
                total += submissions;
                seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
@@@ -3121,6 -3088,134 +3088,134 @@@ static int i915_display_info(struct seq
        return 0;
  }
  
+ static int i915_engine_info(struct seq_file *m, void *unused)
+ {
+       struct drm_i915_private *dev_priv = node_to_i915(m->private);
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
+       for_each_engine(engine, dev_priv, id) {
+               struct intel_breadcrumbs *b = &engine->breadcrumbs;
+               struct drm_i915_gem_request *rq;
+               struct rb_node *rb;
+               u64 addr;
+               seq_printf(m, "%s\n", engine->name);
+               seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
+                          intel_engine_get_seqno(engine),
+                          engine->last_submitted_seqno,
+                          engine->hangcheck.seqno,
+                          engine->hangcheck.score);
+               rcu_read_lock();
+               seq_printf(m, "\tRequests:\n");
+               rq = list_first_entry(&engine->request_list,
+                               struct drm_i915_gem_request, link);
+               if (&rq->link != &engine->request_list)
+                       print_request(m, rq, "\t\tfirst  ");
+               rq = list_last_entry(&engine->request_list,
+                               struct drm_i915_gem_request, link);
+               if (&rq->link != &engine->request_list)
+                       print_request(m, rq, "\t\tlast   ");
+               rq = i915_gem_find_active_request(engine);
+               if (rq) {
+                       print_request(m, rq, "\t\tactive ");
+                       seq_printf(m,
+                                  "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
+                                  rq->head, rq->postfix, rq->tail,
+                                  rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
+                                  rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
+               }
+               seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
+                          I915_READ(RING_START(engine->mmio_base)),
+                          rq ? i915_ggtt_offset(rq->ring->vma) : 0);
+               seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
+                          I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
+                          rq ? rq->ring->head : 0);
+               seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
+                          I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
+                          rq ? rq->ring->tail : 0);
+               seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
+                          I915_READ(RING_CTL(engine->mmio_base)),
+                          I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
+               rcu_read_unlock();
+               addr = intel_engine_get_active_head(engine);
+               seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
+                          upper_32_bits(addr), lower_32_bits(addr));
+               addr = intel_engine_get_last_batch_head(engine);
+               seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
+                          upper_32_bits(addr), lower_32_bits(addr));
+               if (i915.enable_execlists) {
+                       u32 ptr, read, write;
+                       seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
+                                  I915_READ(RING_EXECLIST_STATUS_LO(engine)),
+                                  I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+                       ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
+                       read = GEN8_CSB_READ_PTR(ptr);
+                       write = GEN8_CSB_WRITE_PTR(ptr);
+                       seq_printf(m, "\tExeclist CSB read %d, write %d\n",
+                                  read, write);
+                       if (read >= GEN8_CSB_ENTRIES)
+                               read = 0;
+                       if (write >= GEN8_CSB_ENTRIES)
+                               write = 0;
+                       if (read > write)
+                               write += GEN8_CSB_ENTRIES;
+                       while (read < write) {
+                               unsigned int idx = ++read % GEN8_CSB_ENTRIES;
+                               seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
+                                          idx,
+                                          I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+                                          I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+                       }
+                       rcu_read_lock();
+                       rq = READ_ONCE(engine->execlist_port[0].request);
+                       if (rq)
+                               print_request(m, rq, "\t\tELSP[0] ");
+                       else
+                               seq_printf(m, "\t\tELSP[0] idle\n");
+                       rq = READ_ONCE(engine->execlist_port[1].request);
+                       if (rq)
+                               print_request(m, rq, "\t\tELSP[1] ");
+                       else
+                               seq_printf(m, "\t\tELSP[1] idle\n");
+                       rcu_read_unlock();
+               } else if (INTEL_GEN(dev_priv) > 6) {
+                       seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
+                                  I915_READ(RING_PP_DIR_BASE(engine)));
+                       seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
+                                  I915_READ(RING_PP_DIR_BASE_READ(engine)));
+                       seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
+                                  I915_READ(RING_PP_DIR_DCLV(engine)));
+               }
+               spin_lock(&b->lock);
+               for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
+                       struct intel_wait *w = container_of(rb, typeof(*w), node);
+                       seq_printf(m, "\t%s [%d] waiting for %x\n",
+                                  w->tsk->comm, w->tsk->pid, w->seqno);
+               }
+               spin_unlock(&b->lock);
+               seq_puts(m, "\n");
+       }
+       return 0;
+ }
  static int i915_semaphore_status(struct seq_file *m, void *unused)
  {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
                page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
  
                seqno = (uint64_t *)kmap_atomic(page);
-               for_each_engine_id(engine, dev_priv, id) {
+               for_each_engine(engine, dev_priv, id) {
                        uint64_t offset;
  
                        seq_printf(m, "%s\n", engine->name);
                kunmap_atomic(seqno);
        } else {
                seq_puts(m, "  Last signal:");
-               for_each_engine(engine, dev_priv)
+               for_each_engine(engine, dev_priv, id)
                        for (j = 0; j < num_rings; j++)
                                seq_printf(m, "0x%08x\n",
                                           I915_READ(engine->semaphore.mbox.signal[j]));
        }
  
        seq_puts(m, "\nSync seqno:\n");
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                for (j = 0; j < num_rings; j++)
                        seq_printf(m, "  0x%08x ",
                                   engine->semaphore.sync_seqno[j]);
@@@ -3236,7 -3331,7 +3331,7 @@@ static int i915_wa_registers(struct seq
        intel_runtime_pm_get(dev_priv);
  
        seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
-       for_each_engine_id(engine, dev_priv, id)
+       for_each_engine(engine, dev_priv, id)
                seq_printf(m, "HW whitelist count for %s: %d\n",
                           engine->name, workarounds->hw_whitelist_count[id]);
        for (i = 0; i < workarounds->count; ++i) {
@@@ -3941,9 -4036,10 +4036,9 @@@ static void hsw_trans_edp_pipe_A_crc_wa
  
        ret = drm_atomic_commit(state);
  out:
 -      drm_modeset_unlock_all(dev);
        WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
 -      if (ret)
 -              drm_atomic_state_free(state);
 +      drm_modeset_unlock_all(dev);
 +      drm_atomic_state_put(state);
  }
  
  static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
@@@ -4462,7 -4558,7 +4557,7 @@@ static void wm_latency_show(struct seq_
        else if (IS_VALLEYVIEW(dev_priv))
                num_levels = 1;
        else
-               num_levels = ilk_wm_max_level(dev) + 1;
+               num_levels = ilk_wm_max_level(dev_priv) + 1;
  
        drm_modeset_lock_all(dev);
  
@@@ -4578,7 -4674,7 +4673,7 @@@ static ssize_t wm_latency_write(struct 
        else if (IS_VALLEYVIEW(dev_priv))
                num_levels = 1;
        else
-               num_levels = ilk_wm_max_level(dev) + 1;
+               num_levels = ilk_wm_max_level(dev_priv) + 1;
  
        if (len >= sizeof(tmp))
                return -EINVAL;
@@@ -5274,7 -5370,6 +5369,6 @@@ static const struct drm_info_list i915_
        {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
        {"i915_context_status", i915_context_status, 0},
        {"i915_dump_lrc", i915_dump_lrc, 0},
-       {"i915_execlists", i915_execlists, 0},
        {"i915_forcewake_domains", i915_forcewake_domains, 0},
        {"i915_swizzle_info", i915_swizzle_info, 0},
        {"i915_ppgtt_info", i915_ppgtt_info, 0},
        {"i915_power_domain_info", i915_power_domain_info, 0},
        {"i915_dmc_info", i915_dmc_info, 0},
        {"i915_display_info", i915_display_info, 0},
+       {"i915_engine_info", i915_engine_info, 0},
        {"i915_semaphore_status", i915_semaphore_status, 0},
        {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
        {"i915_dp_mst_info", i915_dp_mst_info, 0},
@@@ -5308,7 -5404,9 +5403,9 @@@ static const struct i915_debugfs_files 
        {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
        {"i915_ring_test_irq", &i915_ring_test_irq_fops},
        {"i915_gem_drop_caches", &i915_drop_caches_fops},
+ #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
        {"i915_error_state", &i915_error_state_fops},
+ #endif
        {"i915_next_seqno", &i915_next_seqno_fops},
        {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
        {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
index 947e82c2b1757993e6b5fff2e6fdf29d4f584ffa,9bb72e503a30792ed0b476e00d0fb4c9f84554c8..8ed8e24025aca7f6f7e8520c2789c1042a9eabe6
@@@ -82,7 -82,7 +82,7 @@@ remove_mappable_node(struct drm_mm_nod
  
  /* some bookkeeping */
  static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
-                                 size_t size)
+                                 u64 size)
  {
        spin_lock(&dev_priv->mm.object_stat_lock);
        dev_priv->mm.object_count++;
@@@ -91,7 -91,7 +91,7 @@@
  }
  
  static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
-                                    size_t size)
+                                    u64 size)
  {
        spin_lock(&dev_priv->mm.object_stat_lock);
        dev_priv->mm.object_count--;
@@@ -860,7 -860,7 +860,7 @@@ i915_gem_gtt_pread(struct drm_device *d
  
        mutex_unlock(&dev->struct_mutex);
        if (likely(!i915.prefault_disable)) {
 -              ret = fault_in_multipages_writeable(user_data, remain);
 +              ret = fault_in_pages_writeable(user_data, remain);
                if (ret) {
                        mutex_lock(&dev->struct_mutex);
                        goto out_unpin;
@@@ -919,8 -919,7 +919,7 @@@ out_unpin
        if (node.allocated) {
                wmb();
                ggtt->base.clear_range(&ggtt->base,
-                                      node.start, node.size,
-                                      true);
+                                      node.start, node.size);
                i915_gem_object_unpin_pages(obj);
                remove_mappable_node(&node);
        } else {
@@@ -983,7 -982,7 +982,7 @@@ i915_gem_shmem_pread(struct drm_device 
                mutex_unlock(&dev->struct_mutex);
  
                if (likely(!i915.prefault_disable) && !prefaulted) {
 -                      ret = fault_in_multipages_writeable(user_data, remain);
 +                      ret = fault_in_pages_writeable(user_data, remain);
                        /* Userspace is tricking us, but we've already clobbered
                         * its pages with the prefault and promised to write the
                         * data up to the first fault. Hence ignore any errors
@@@ -1228,8 -1227,7 +1227,7 @@@ out_unpin
        if (node.allocated) {
                wmb();
                ggtt->base.clear_range(&ggtt->base,
-                                      node.start, node.size,
-                                      true);
+                                      node.start, node.size);
                i915_gem_object_unpin_pages(obj);
                remove_mappable_node(&node);
        } else {
@@@ -1431,7 -1429,7 +1429,7 @@@ i915_gem_pwrite_ioctl(struct drm_devic
                return -EFAULT;
  
        if (likely(!i915.prefault_disable)) {
 -              ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr),
 +              ret = fault_in_pages_readable(u64_to_user_ptr(args->data_ptr),
                                                   args->size);
                if (ret)
                        return -EFAULT;
@@@ -1813,8 -1811,7 +1811,7 @@@ int i915_gem_fault(struct vm_area_struc
                view.params.partial.offset = rounddown(page_offset, chunk_size);
                view.params.partial.size =
                        min_t(unsigned int, chunk_size,
-                             (area->vm_end - area->vm_start) / PAGE_SIZE -
-                             view.params.partial.offset);
+                             vma_pages(area) - view.params.partial.offset);
  
                /* If the partial covers the entire object, just create a
                 * normal VMA.
@@@ -2208,6 -2205,15 +2205,15 @@@ i915_gem_object_put_pages(struct drm_i9
        return 0;
  }
  
+ static unsigned int swiotlb_max_size(void)
+ {
+ #if IS_ENABLED(CONFIG_SWIOTLB)
+       return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE);
+ #else
+       return 0;
+ #endif
+ }
  static int
  i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
  {
        struct sgt_iter sgt_iter;
        struct page *page;
        unsigned long last_pfn = 0;     /* suppress gcc warning */
+       unsigned int max_segment;
        int ret;
        gfp_t gfp;
  
        BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
        BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
  
+       max_segment = swiotlb_max_size();
+       if (!max_segment)
+               max_segment = rounddown(UINT_MAX, PAGE_SIZE);
        st = kmalloc(sizeof(*st), GFP_KERNEL);
        if (st == NULL)
                return -ENOMEM;
                         * our own buffer, now let the real VM do its job and
                         * go down in flames if truly OOM.
                         */
-                       i915_gem_shrink_all(dev_priv);
                        page = shmem_read_mapping_page(mapping, i);
                        if (IS_ERR(page)) {
                                ret = PTR_ERR(page);
                                goto err_pages;
                        }
                }
- #ifdef CONFIG_SWIOTLB
-               if (swiotlb_nr_tbl()) {
-                       st->nents++;
-                       sg_set_page(sg, page, PAGE_SIZE, 0);
-                       sg = sg_next(sg);
-                       continue;
-               }
- #endif
-               if (!i || page_to_pfn(page) != last_pfn + 1) {
+               if (!i ||
+                   sg->length >= max_segment ||
+                   page_to_pfn(page) != last_pfn + 1) {
                        if (i)
                                sg = sg_next(sg);
                        st->nents++;
                /* Check that the i965g/gm workaround works. */
                WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
        }
- #ifdef CONFIG_SWIOTLB
-       if (!swiotlb_nr_tbl())
- #endif
+       if (sg) /* loop terminated early; short sg table */
                sg_mark_end(sg);
        obj->pages = st;
  
@@@ -2581,8 -2583,6 +2583,6 @@@ static void i915_gem_reset_engine(struc
        struct i915_gem_context *incomplete_ctx;
        bool ring_hung;
  
-       /* Ensure irq handler finishes, and not run again. */
-       tasklet_kill(&engine->irq_tasklet);
        if (engine->irq_seqno_barrier)
                engine->irq_seqno_barrier(engine);
  
                return;
  
        ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
+       if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
+               ring_hung = false;
        i915_set_reset_status(request->ctx, ring_hung);
        if (!ring_hung)
                return;
  void i915_gem_reset(struct drm_i915_private *dev_priv)
  {
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
  
        i915_gem_retire_requests(dev_priv);
  
-       for_each_engine(engine, dev_priv)
+       for_each_engine(engine, dev_priv, id)
                i915_gem_reset_engine(engine);
  
        i915_gem_restore_fences(&dev_priv->drm);
@@@ -2672,12 -2676,13 +2676,13 @@@ static void i915_gem_cleanup_engine(str
  void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
  {
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
  
        lockdep_assert_held(&dev_priv->drm.struct_mutex);
        set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
  
        i915_gem_context_lost(dev_priv);
-       for_each_engine(engine, dev_priv)
+       for_each_engine(engine, dev_priv, id)
                i915_gem_cleanup_engine(engine);
        mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
  
@@@ -2716,6 -2721,7 +2721,7 @@@ i915_gem_idle_work_handler(struct work_
                container_of(work, typeof(*dev_priv), gt.idle_work.work);
        struct drm_device *dev = &dev_priv->drm;
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        bool rearm_hangcheck;
  
        if (!READ_ONCE(dev_priv->gt.awake))
        if (dev_priv->gt.active_engines)
                goto out_unlock;
  
-       for_each_engine(engine, dev_priv)
+       for_each_engine(engine, dev_priv, id)
                i915_gem_batch_pool_fini(&engine->batch_pool);
  
        GEM_BUG_ON(!dev_priv->gt.awake);
@@@ -2931,9 -2937,10 +2937,10 @@@ int i915_gem_wait_for_idle(struct drm_i
                           unsigned int flags)
  {
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int ret;
  
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                if (engine->last_context == NULL)
                        continue;
  
@@@ -3095,6 -3102,9 +3102,9 @@@ search_free
  
                        goto err_unpin;
                }
+               GEM_BUG_ON(vma->node.start < start);
+               GEM_BUG_ON(vma->node.start + vma->node.size > end);
        }
        GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level));
  
@@@ -3173,7 -3183,7 +3183,7 @@@ i915_gem_object_flush_gtt_write_domain(
         */
        wmb();
        if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
-               POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base));
+               POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
  
        intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
  
@@@ -3468,7 -3478,7 +3478,7 @@@ int i915_gem_set_caching_ioctl(struct d
                level = I915_CACHE_LLC;
                break;
        case I915_CACHING_DISPLAY:
-               level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
+               level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
                break;
        default:
                return -EINVAL;
@@@ -3526,7 -3536,8 +3536,8 @@@ i915_gem_object_pin_to_display_plane(st
         * with that bit in the PTE to main memory with just one PIPE_CONTROL.
         */
        ret = i915_gem_object_set_cache_level(obj,
-                                             HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
+                                             HAS_WT(to_i915(obj->base.dev)) ?
+                                             I915_CACHE_WT : I915_CACHE_NONE);
        if (ret) {
                vma = ERR_PTR(ret);
                goto err_unpin_display;
@@@ -3793,7 -3804,8 +3804,8 @@@ i915_gem_object_ggtt_pin(struct drm_i91
                         u64 alignment,
                         u64 flags)
  {
-       struct i915_address_space *vm = &to_i915(obj->base.dev)->ggtt.base;
+       struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+       struct i915_address_space *vm = &dev_priv->ggtt.base;
        struct i915_vma *vma;
        int ret;
  
                    (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
                        return ERR_PTR(-ENOSPC);
  
+               if (flags & PIN_MAPPABLE) {
+                       u32 fence_size;
+                       fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
+                                                           i915_gem_object_get_tiling(obj));
+                       /* If the required space is larger than the available
+                        * aperture, we will not able to find a slot for the
+                        * object and unbinding the object now will be in
+                        * vain. Worse, doing so may cause us to ping-pong
+                        * the object in and out of the Global GTT and
+                        * waste a lot of cycles under the mutex.
+                        */
+                       if (fence_size > dev_priv->ggtt.mappable_end)
+                               return ERR_PTR(-E2BIG);
+                       /* If NONBLOCK is set the caller is optimistically
+                        * trying to cache the full object within the mappable
+                        * aperture, and *must* have a fallback in place for
+                        * situations where we cannot bind the object. We
+                        * can be a little more lax here and use the fallback
+                        * more often to avoid costly migrations of ourselves
+                        * and other objects within the aperture.
+                        *
+                        * Half-the-aperture is used as a simple heuristic.
+                        * More interesting would to do search for a free
+                        * block prior to making the commitment to unbind.
+                        * That caters for the self-harm case, and with a
+                        * little more heuristics (e.g. NOFAULT, NOEVICT)
+                        * we could try to minimise harm to others.
+                        */
+                       if (flags & PIN_NONBLOCK &&
+                           fence_size > dev_priv->ggtt.mappable_end / 2)
+                               return ERR_PTR(-ENOSPC);
+               }
                WARN(i915_vma_is_pinned(vma),
                     "bo is already pinned in ggtt with incorrect alignment:"
                     " offset=%08x, req.alignment=%llx,"
@@@ -4084,14 -4131,29 +4131,29 @@@ static const struct drm_i915_gem_object
        .put_pages = i915_gem_object_put_pages_gtt,
  };
  
- struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
-                                                 size_t size)
+ /* Note we don't consider signbits :| */
+ #define overflows_type(x, T) \
+       (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
+ struct drm_i915_gem_object *
+ i915_gem_object_create(struct drm_device *dev, u64 size)
  {
        struct drm_i915_gem_object *obj;
        struct address_space *mapping;
        gfp_t mask;
        int ret;
  
+       /* There is a prevalence of the assumption that we fit the object's
+        * page count inside a 32bit _signed_ variable. Let's document this and
+        * catch if we ever need to fix it. In the meantime, if you do spot
+        * such a local variable, please consider fixing!
+        */
+       if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
+               return ERR_PTR(-E2BIG);
+       if (overflows_type(size, obj->base.size))
+               return ERR_PTR(-E2BIG);
        obj = i915_gem_object_alloc(dev);
        if (obj == NULL)
                return ERR_PTR(-ENOMEM);
@@@ -4268,6 -4330,30 +4330,30 @@@ int i915_gem_suspend(struct drm_device 
         */
        WARN_ON(dev_priv->gt.awake);
  
+       /*
+        * Neither the BIOS, ourselves or any other kernel
+        * expects the system to be in execlists mode on startup,
+        * so we need to reset the GPU back to legacy mode. And the only
+        * known way to disable logical contexts is through a GPU reset.
+        *
+        * So in order to leave the system in a known default configuration,
+        * always reset the GPU upon unload and suspend. Afterwards we then
+        * clean up the GEM state tracking, flushing off the requests and
+        * leaving the system in a known idle state.
+        *
+        * Note that is of the upmost importance that the GPU is idle and
+        * all stray writes are flushed *before* we dismantle the backing
+        * storage for the pinned objects.
+        *
+        * However, since we are uncertain that resetting the GPU on older
+        * machines is a good idea, we don't - just in case it leaves the
+        * machine in an unusable condition.
+        */
+       if (HAS_HW_CONTEXTS(dev)) {
+               int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
+               WARN_ON(reset && reset != -ENODEV);
+       }
        return 0;
  
  err:
@@@ -4302,44 -4388,42 +4388,42 @@@ void i915_gem_init_swizzling(struct drm
        I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
                                 DISP_TILE_SURFACE_SWIZZLING);
  
-       if (IS_GEN5(dev))
+       if (IS_GEN5(dev_priv))
                return;
  
        I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
-       if (IS_GEN6(dev))
+       if (IS_GEN6(dev_priv))
                I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
-       else if (IS_GEN7(dev))
+       else if (IS_GEN7(dev_priv))
                I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
-       else if (IS_GEN8(dev))
+       else if (IS_GEN8(dev_priv))
                I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
        else
                BUG();
  }
  
- static void init_unused_ring(struct drm_device *dev, u32 base)
+ static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
  {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        I915_WRITE(RING_CTL(base), 0);
        I915_WRITE(RING_HEAD(base), 0);
        I915_WRITE(RING_TAIL(base), 0);
        I915_WRITE(RING_START(base), 0);
  }
  
- static void init_unused_rings(struct drm_device *dev)
+ static void init_unused_rings(struct drm_i915_private *dev_priv)
  {
-       if (IS_I830(dev)) {
-               init_unused_ring(dev, PRB1_BASE);
-               init_unused_ring(dev, SRB0_BASE);
-               init_unused_ring(dev, SRB1_BASE);
-               init_unused_ring(dev, SRB2_BASE);
-               init_unused_ring(dev, SRB3_BASE);
-       } else if (IS_GEN2(dev)) {
-               init_unused_ring(dev, SRB0_BASE);
-               init_unused_ring(dev, SRB1_BASE);
-       } else if (IS_GEN3(dev)) {
-               init_unused_ring(dev, PRB1_BASE);
-               init_unused_ring(dev, PRB2_BASE);
+       if (IS_I830(dev_priv)) {
+               init_unused_ring(dev_priv, PRB1_BASE);
+               init_unused_ring(dev_priv, SRB0_BASE);
+               init_unused_ring(dev_priv, SRB1_BASE);
+               init_unused_ring(dev_priv, SRB2_BASE);
+               init_unused_ring(dev_priv, SRB3_BASE);
+       } else if (IS_GEN2(dev_priv)) {
+               init_unused_ring(dev_priv, SRB0_BASE);
+               init_unused_ring(dev_priv, SRB1_BASE);
+       } else if (IS_GEN3(dev_priv)) {
+               init_unused_ring(dev_priv, PRB1_BASE);
+               init_unused_ring(dev_priv, PRB2_BASE);
        }
  }
  
@@@ -4348,6 -4432,7 +4432,7 @@@ i915_gem_init_hw(struct drm_device *dev
  {
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        int ret;
  
        /* Double layer security blanket, see i915_gem_init() */
        if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
                I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
  
-       if (IS_HASWELL(dev))
-               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
+       if (IS_HASWELL(dev_priv))
+               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
                           LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
  
-       if (HAS_PCH_NOP(dev)) {
-               if (IS_IVYBRIDGE(dev)) {
+       if (HAS_PCH_NOP(dev_priv)) {
+               if (IS_IVYBRIDGE(dev_priv)) {
                        u32 temp = I915_READ(GEN7_MSG_CTL);
                        temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
                        I915_WRITE(GEN7_MSG_CTL, temp);
         * will prevent c3 entry. Makes sure all unused rings
         * are totally idle.
         */
-       init_unused_rings(dev);
+       init_unused_rings(dev_priv);
  
        BUG_ON(!dev_priv->kernel_context);
  
        }
  
        /* Need to do basic initialisation of all rings first: */
-       for_each_engine(engine, dev_priv) {
+       for_each_engine(engine, dev_priv, id) {
                ret = engine->init_hw(engine);
                if (ret)
                        goto out;
@@@ -4490,17 -4575,12 +4575,12 @@@ i915_gem_cleanup_engines(struct drm_dev
  {
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_engine_cs *engine;
+       enum intel_engine_id id;
  
-       for_each_engine(engine, dev_priv)
+       for_each_engine(engine, dev_priv, id)
                dev_priv->gt.cleanup_engine(engine);
  }
  
- static void
- init_engine_lists(struct intel_engine_cs *engine)
- {
-       INIT_LIST_HEAD(&engine->request_list);
- }
  void
  i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
  {
@@@ -4537,7 -4617,6 +4617,6 @@@ voi
  i915_gem_load_init(struct drm_device *dev)
  {
        struct drm_i915_private *dev_priv = to_i915(dev);
-       int i;
  
        dev_priv->objects =
                kmem_cache_create("i915_gem_object",
        INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
        INIT_LIST_HEAD(&dev_priv->mm.bound_list);
        INIT_LIST_HEAD(&dev_priv->mm.fence_list);
-       for (i = 0; i < I915_NUM_ENGINES; i++)
-               init_engine_lists(&dev_priv->engine[i]);
        INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
                          i915_gem_retire_work_handler);
        INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
index 7adb4c77cc7f449698f0207d5f51cbf037cff179,d7a663e6a8b263c8d0e9175a389ce2b41b52c17f..e52affdcc125d5585cc3fa45bd25c60aed540084
@@@ -370,8 -370,7 +370,7 @@@ static void reloc_cache_fini(struct rel
  
                        ggtt->base.clear_range(&ggtt->base,
                                               cache->node.start,
-                                              cache->node.size,
-                                              true);
+                                              cache->node.size);
                        drm_mm_remove_node(&cache->node);
                } else {
                        i915_vma_unpin((struct i915_vma *)cache->node.mm);
@@@ -429,7 -428,7 +428,7 @@@ static void *reloc_iomap(struct drm_i91
        }
  
        if (cache->vaddr) {
-               io_mapping_unmap_atomic(unmask_page(cache->vaddr));
+               io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
        } else {
                struct i915_vma *vma;
                int ret;
                offset += page << PAGE_SHIFT;
        }
  
-       vaddr = io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset);
+       vaddr = (void __force *) io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset);
        cache->page = page;
        cache->vaddr = (unsigned long)vaddr;
  
@@@ -552,27 -551,13 +551,13 @@@ repeat
        return 0;
  }
  
- static bool object_is_idle(struct drm_i915_gem_object *obj)
- {
-       unsigned long active = i915_gem_object_get_active(obj);
-       int idx;
-       for_each_active(active, idx) {
-               if (!i915_gem_active_is_idle(&obj->last_read[idx],
-                                            &obj->base.dev->struct_mutex))
-                       return false;
-       }
-       return true;
- }
  static int
  i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
                                   struct eb_vmas *eb,
                                   struct drm_i915_gem_relocation_entry *reloc,
                                   struct reloc_cache *cache)
  {
-       struct drm_device *dev = obj->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
        struct drm_gem_object *target_obj;
        struct drm_i915_gem_object *target_i915_obj;
        struct i915_vma *target_vma;
        /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
         * pipe_control writes because the gpu doesn't properly redirect them
         * through the ppgtt for non_secure batchbuffers. */
-       if (unlikely(IS_GEN6(dev) &&
+       if (unlikely(IS_GEN6(dev_priv) &&
            reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
                ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
                                    PIN_GLOBAL);
                return -EINVAL;
        }
  
-       /* We can't wait for rendering with pagefaults disabled */
-       if (pagefault_disabled() && !object_is_idle(obj))
-               return -EFAULT;
        ret = relocate_entry(obj, reloc, cache, target_offset);
        if (ret)
                return ret;
@@@ -679,12 -660,23 +660,23 @@@ i915_gem_execbuffer_relocate_vma(struc
        remain = entry->relocation_count;
        while (remain) {
                struct drm_i915_gem_relocation_entry *r = stack_reloc;
-               int count = remain;
-               if (count > ARRAY_SIZE(stack_reloc))
-                       count = ARRAY_SIZE(stack_reloc);
+               unsigned long unwritten;
+               unsigned int count;
+               count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc));
                remain -= count;
  
-               if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) {
+               /* This is the fast path and we cannot handle a pagefault
+                * whilst holding the struct mutex lest the user pass in the
+                * relocations contained within a mmaped bo. For in such a case
+                * we, the page fault handler would call i915_gem_fault() and
+                * we would try to acquire the struct mutex again. Obviously
+                * this is bad and so lockdep complains vehemently.
+                */
+               pagefault_disable();
+               unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]));
+               pagefault_enable();
+               if (unlikely(unwritten)) {
                        ret = -EFAULT;
                        goto out;
                }
                        if (ret)
                                goto out;
  
-                       if (r->presumed_offset != offset &&
-                           __put_user(r->presumed_offset,
-                                      &user_relocs->presumed_offset)) {
-                               ret = -EFAULT;
-                               goto out;
+                       if (r->presumed_offset != offset) {
+                               pagefault_disable();
+                               unwritten = __put_user(r->presumed_offset,
+                                                      &user_relocs->presumed_offset);
+                               pagefault_enable();
+                               if (unlikely(unwritten)) {
+                                       /* Note that reporting an error now
+                                        * leaves everything in an inconsistent
+                                        * state as we have *already* changed
+                                        * the relocation value inside the
+                                        * object. As we have not changed the
+                                        * reloc.presumed_offset or will not
+                                        * change the execobject.offset, on the
+                                        * call we may not rewrite the value
+                                        * inside the object, leaving it
+                                        * dangling and causing a GPU hang.
+                                        */
+                                       ret = -EFAULT;
+                                       goto out;
+                               }
                        }
  
                        user_relocs++;
@@@ -740,20 -747,11 +747,11 @@@ i915_gem_execbuffer_relocate(struct eb_
        struct i915_vma *vma;
        int ret = 0;
  
-       /* This is the fast path and we cannot handle a pagefault whilst
-        * holding the struct mutex lest the user pass in the relocations
-        * contained within a mmaped bo. For in such a case we, the page
-        * fault handler would call i915_gem_fault() and we would try to
-        * acquire the struct mutex again. Obviously this is bad and so
-        * lockdep complains vehemently.
-        */
-       pagefault_disable();
        list_for_each_entry(vma, &eb->vmas, exec_list) {
                ret = i915_gem_execbuffer_relocate_vma(vma, eb);
                if (ret)
                        break;
        }
-       pagefault_enable();
  
        return ret;
  }
@@@ -1253,7 -1251,7 +1251,7 @@@ validate_exec_list(struct drm_device *d
                        return -EFAULT;
  
                if (likely(!i915.prefault_disable)) {
 -                      if (fault_in_multipages_readable(ptr, length))
 +                      if (fault_in_pages_readable(ptr, length))
                                return -EFAULT;
                }
        }
@@@ -1599,12 -1597,12 +1597,12 @@@ eb_select_engine(struct drm_i915_privat
                        return NULL;
                }
  
-               engine = &dev_priv->engine[_VCS(bsd_idx)];
+               engine = dev_priv->engine[_VCS(bsd_idx)];
        } else {
-               engine = &dev_priv->engine[user_ring_map[user_ring_id]];
+               engine = dev_priv->engine[user_ring_map[user_ring_id]];
        }
  
-       if (!intel_engine_initialized(engine)) {
+       if (!engine) {
                DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
                return NULL;
        }
index 4c21d2ec2c51b86206963fd56e63935d6bf70f22,6ccedf2af98e901553c5728ece7a80163b72acf3..6f8f6ec5b27a34a7c28d1b9f46719cd79c9c0706
@@@ -600,7 -600,7 +600,7 @@@ int chv_calc_dpll_params(int refclk, st
   * the given connectors.
   */
  
- static bool intel_PLL_is_valid(struct drm_device *dev,
+ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
                               const struct intel_limit *limit,
                               const struct dpll *clock)
  {
        if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
                INTELPllInvalid("m1 out of range\n");
  
-       if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
-           !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
+       if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
+           !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
                if (clock->m1 <= clock->m2)
                        INTELPllInvalid("m1 <= m2\n");
  
-       if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
+       if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
+           !IS_BROXTON(dev_priv)) {
                if (clock->p < limit->p.min || limit->p.max < clock->p)
                        INTELPllInvalid("p out of range\n");
                if (clock->m < limit->m.min || limit->m.max < clock->m)
@@@ -698,7 -699,8 +699,8 @@@ i9xx_find_best_dpll(const struct intel_
                                        int this_err;
  
                                        i9xx_calc_dpll_params(refclk, &clock);
-                                       if (!intel_PLL_is_valid(dev, limit,
+                                       if (!intel_PLL_is_valid(to_i915(dev),
+                                                               limit,
                                                                &clock))
                                                continue;
                                        if (match_clock &&
@@@ -753,7 -755,8 +755,8 @@@ pnv_find_best_dpll(const struct intel_l
                                        int this_err;
  
                                        pnv_calc_dpll_params(refclk, &clock);
-                                       if (!intel_PLL_is_valid(dev, limit,
+                                       if (!intel_PLL_is_valid(to_i915(dev),
+                                                               limit,
                                                                &clock))
                                                continue;
                                        if (match_clock &&
@@@ -813,7 -816,8 +816,8 @@@ g4x_find_best_dpll(const struct intel_l
                                        int this_err;
  
                                        i9xx_calc_dpll_params(refclk, &clock);
-                                       if (!intel_PLL_is_valid(dev, limit,
+                                       if (!intel_PLL_is_valid(to_i915(dev),
+                                                               limit,
                                                                &clock))
                                                continue;
  
@@@ -845,7 -849,7 +849,7 @@@ static bool vlv_PLL_is_optimal(struct d
         * For CHV ignore the error and consider only the P value.
         * Prefer a bigger P value based on HW requirements.
         */
-       if (IS_CHERRYVIEW(dev)) {
+       if (IS_CHERRYVIEW(to_i915(dev))) {
                *error_ppm = 0;
  
                return calculated_clock->p > best_clock->p;
@@@ -909,7 -913,8 +913,8 @@@ vlv_find_best_dpll(const struct intel_l
  
                                        vlv_calc_dpll_params(refclk, &clock);
  
-                                       if (!intel_PLL_is_valid(dev, limit,
+                                       if (!intel_PLL_is_valid(to_i915(dev),
+                                                               limit,
                                                                &clock))
                                                continue;
  
@@@ -977,7 -982,7 +982,7 @@@ chv_find_best_dpll(const struct intel_l
  
                        chv_calc_dpll_params(refclk, &clock);
  
-                       if (!intel_PLL_is_valid(dev, limit, &clock))
+                       if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
                                continue;
  
                        if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
@@@ -1040,7 -1045,7 +1045,7 @@@ static bool pipe_dsl_stopped(struct drm
        u32 line1, line2;
        u32 line_mask;
  
-       if (IS_GEN2(dev))
+       if (IS_GEN2(dev_priv))
                line_mask = DSL_LINEMASK_GEN2;
        else
                line_mask = DSL_LINEMASK_GEN3;
@@@ -1187,19 -1192,17 +1192,17 @@@ void assert_fdi_rx_pll(struct drm_i915_
                        onoff(state), onoff(cur_state));
  }
  
- void assert_panel_unlocked(struct drm_i915_private *dev_priv,
-                          enum pipe pipe)
+ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
  {
-       struct drm_device *dev = &dev_priv->drm;
        i915_reg_t pp_reg;
        u32 val;
        enum pipe panel_pipe = PIPE_A;
        bool locked = true;
  
-       if (WARN_ON(HAS_DDI(dev)))
+       if (WARN_ON(HAS_DDI(dev_priv)))
                return;
  
-       if (HAS_PCH_SPLIT(dev)) {
+       if (HAS_PCH_SPLIT(dev_priv)) {
                u32 port_sel;
  
                pp_reg = PP_CONTROL(0);
                    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
                        panel_pipe = PIPE_B;
                /* XXX: else fix for eDP */
-       } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                /* presumably write lock depends on pipe, not port select */
                pp_reg = PP_CONTROL(pipe);
                panel_pipe = pipe;
  static void assert_cursor(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
  {
-       struct drm_device *dev = &dev_priv->drm;
        bool cur_state;
  
-       if (IS_845G(dev) || IS_I865G(dev))
+       if (IS_845G(dev_priv) || IS_I865G(dev_priv))
                cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
        else
                cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
@@@ -1330,7 -1332,7 +1332,7 @@@ static void assert_sprites_disabled(str
                             "plane %d assertion failure, should be off on pipe %c but is still active\n",
                             sprite, pipe_name(pipe));
                }
-       } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                for_each_sprite(dev_priv, pipe, sprite) {
                        u32 val = I915_READ(SPCNTR(pipe, sprite));
                        I915_STATE_WARN(val & SP_ENABLE,
@@@ -1619,11 -1621,11 +1621,11 @@@ static void i9xx_enable_pll(struct inte
        assert_pipe_disabled(dev_priv, crtc->pipe);
  
        /* PLL is protected by panel, make sure we can write it */
-       if (IS_MOBILE(dev) && !IS_I830(dev))
+       if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
                assert_panel_unlocked(dev_priv, crtc->pipe);
  
        /* Enable DVO 2x clock on both PLLs if necessary */
-       if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
+       if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
                /*
                 * It appears to be important that we don't enable this
                 * for the current pipe before otherwise configuring the
@@@ -1688,7 -1690,7 +1690,7 @@@ static void i9xx_disable_pll(struct int
        enum pipe pipe = crtc->pipe;
  
        /* Disable DVO 2x clock on both PLLs if necessary */
-       if (IS_I830(dev) &&
+       if (IS_I830(dev_priv) &&
            intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
            !intel_num_dvo_pipes(dev)) {
                I915_WRITE(DPLL(PIPE_B),
@@@ -1786,7 -1788,6 +1788,6 @@@ void vlv_wait_port_ready(struct drm_i91
  static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
                                           enum pipe pipe)
  {
-       struct drm_device *dev = &dev_priv->drm;
        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        i915_reg_t reg;
        assert_fdi_tx_enabled(dev_priv, pipe);
        assert_fdi_rx_enabled(dev_priv, pipe);
  
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                /* Workaround: Set the timing override bit before enabling the
                 * pch transcoder. */
                reg = TRANS_CHICKEN2(pipe);
@@@ -1877,7 -1878,6 +1878,6 @@@ static void lpt_enable_pch_transcoder(s
  static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
                                            enum pipe pipe)
  {
-       struct drm_device *dev = &dev_priv->drm;
        i915_reg_t reg;
        uint32_t val;
  
                                    50))
                DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                /* Workaround: Clear the timing override chicken bit again. */
                reg = TRANS_CHICKEN2(pipe);
                val = I915_READ(reg);
@@@ -1926,6 -1926,18 +1926,18 @@@ void lpt_disable_pch_transcoder(struct 
        I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
  }
  
+ enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
+ {
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       WARN_ON(!crtc->config->has_pch_encoder);
+       if (HAS_PCH_LPT(dev_priv))
+               return TRANSCODER_A;
+       else
+               return (enum transcoder) crtc->pipe;
+ }
  /**
   * intel_enable_pipe - enable a pipe, asserting requirements
   * @crtc: crtc responsible for the pipe
@@@ -1939,7 -1951,6 +1951,6 @@@ static void intel_enable_pipe(struct in
        struct drm_i915_private *dev_priv = to_i915(dev);
        enum pipe pipe = crtc->pipe;
        enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
-       enum pipe pch_transcoder;
        i915_reg_t reg;
        u32 val;
  
        assert_cursor_disabled(dev_priv, pipe);
        assert_sprites_disabled(dev_priv, pipe);
  
-       if (HAS_PCH_LPT(dev_priv))
-               pch_transcoder = TRANSCODER_A;
-       else
-               pch_transcoder = pipe;
        /*
         * A pipe without a PLL won't actually be able to drive bits from
         * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
        } else {
                if (crtc->config->has_pch_encoder) {
                        /* if driving the PCH, we need FDI enabled */
-                       assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
+                       assert_fdi_rx_pll_enabled(dev_priv,
+                                                 (enum pipe) intel_crtc_pch_transcoder(crtc));
                        assert_fdi_tx_pll_enabled(dev_priv,
                                                  (enum pipe) cpu_transcoder);
                }
@@@ -2139,7 -2146,7 +2146,7 @@@ intel_fill_fb_ggtt_view(struct i915_ggt
                        const struct drm_framebuffer *fb,
                        unsigned int rotation)
  {
 -      if (intel_rotation_90_or_270(rotation)) {
 +      if (drm_rotation_90_or_270(rotation)) {
                *view = i915_ggtt_view_rotated;
                view->params.rotated = to_intel_framebuffer(fb)->rot_info;
        } else {
@@@ -2260,7 -2267,7 +2267,7 @@@ void intel_unpin_fb_obj(struct drm_fram
  static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
                          unsigned int rotation)
  {
 -      if (intel_rotation_90_or_270(rotation))
 +      if (drm_rotation_90_or_270(rotation))
                return to_intel_framebuffer(fb)->rotated[plane].pitch;
        else
                return fb->pitches[plane];
@@@ -2296,7 -2303,7 +2303,7 @@@ void intel_add_fb_offsets(int *x, int *
        const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
        unsigned int rotation = state->base.rotation;
  
 -      if (intel_rotation_90_or_270(rotation)) {
 +      if (drm_rotation_90_or_270(rotation)) {
                *x += intel_fb->rotated[plane].x;
                *y += intel_fb->rotated[plane].y;
        } else {
@@@ -2360,7 -2367,7 +2367,7 @@@ static u32 intel_adjust_tile_offset(in
                intel_tile_dims(dev_priv, &tile_width, &tile_height,
                                fb->modifier[plane], cpp);
  
 -              if (intel_rotation_90_or_270(rotation)) {
 +              if (drm_rotation_90_or_270(rotation)) {
                        pitch_tiles = pitch / tile_height;
                        swap(tile_width, tile_height);
                } else {
@@@ -2416,7 -2423,7 +2423,7 @@@ static u32 _intel_compute_tile_offset(c
                intel_tile_dims(dev_priv, &tile_width, &tile_height,
                                fb_modifier, cpp);
  
 -              if (intel_rotation_90_or_270(rotation)) {
 +              if (drm_rotation_90_or_270(rotation)) {
                        pitch_tiles = pitch / tile_height;
                        swap(tile_width, tile_height);
                } else {
@@@ -2976,7 -2983,7 +2983,7 @@@ int skl_check_plane_surface(struct inte
        int ret;
  
        /* Rotate src coordinates to match rotated GTT view */
 -      if (intel_rotation_90_or_270(rotation))
 +      if (drm_rotation_90_or_270(rotation))
                drm_rect_rotate(&plane_state->base.src,
                                fb->width, fb->height, DRM_ROTATE_270);
  
@@@ -3033,7 -3040,7 +3040,7 @@@ static void i9xx_update_primary_plane(s
                           ((crtc_state->pipe_src_h - 1) << 16) |
                           (crtc_state->pipe_src_w - 1));
                I915_WRITE(DSPPOS(plane), 0);
-       } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
+       } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
                I915_WRITE(PRIMSIZE(plane),
                           ((crtc_state->pipe_src_h - 1) << 16) |
                           (crtc_state->pipe_src_w - 1));
            fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                dspcntr |= DISPPLANE_TILED;
  
-       if (IS_G4X(dev))
+       if (IS_G4X(dev_priv))
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  
        intel_add_fb_offsets(&x, &y, plane_state, 0);
@@@ -3144,7 -3151,7 +3151,7 @@@ static void ironlake_update_primary_pla
        dspcntr = DISPPLANE_GAMMA_ENABLE;
        dspcntr |= DISPLAY_PLANE_ENABLE;
  
-       if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
  
        switch (fb->pixel_format) {
        if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                dspcntr |= DISPPLANE_TILED;
  
-       if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
+       if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  
        intel_add_fb_offsets(&x, &y, plane_state, 0);
        if (rotation == DRM_ROTATE_180) {
                dspcntr |= DISPPLANE_ROTATE_180;
  
-               if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
+               if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
                        x += (crtc_state->pipe_src_w - 1);
                        y += (crtc_state->pipe_src_h - 1);
                }
        I915_WRITE(DSPSURF(plane),
                   intel_fb_gtt_offset(fb, rotation) +
                   intel_crtc->dspaddr_offset);
-       if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
                I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
        } else {
                I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
@@@ -3276,7 -3283,7 +3283,7 @@@ u32 skl_plane_stride(const struct drm_f
         * The stride is either expressed as a multiple of 64 bytes chunks for
         * linear buffers or in number of tiles for tiled buffers.
         */
 -      if (intel_rotation_90_or_270(rotation)) {
 +      if (drm_rotation_90_or_270(rotation)) {
                int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
  
                stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
@@@ -3378,6 -3385,8 +3385,8 @@@ static void skylake_update_primary_plan
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_framebuffer *fb = plane_state->base.fb;
        const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
+       const struct skl_plane_wm *p_wm =
+               &crtc_state->wm.skl.optimal.planes[0];
        int pipe = intel_crtc->pipe;
        u32 plane_ctl;
        unsigned int rotation = plane_state->base.rotation;
        intel_crtc->adjusted_y = src_y;
  
        if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
-               skl_write_plane_wm(intel_crtc, wm, 0);
+               skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
  
        I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
        I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
@@@ -3448,6 -3457,8 +3457,8 @@@ static void skylake_disable_primary_pla
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+       const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0];
        int pipe = intel_crtc->pipe;
  
        /*
         * plane's visiblity isn't actually changing neither is its watermarks.
         */
        if (!crtc->primary->state->visible)
-               skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
+               skl_write_plane_wm(intel_crtc, p_wm,
+                                  &dev_priv->wm.skl_results.ddb, 0);
  
        I915_WRITE(PLANE_CTL(pipe, 0), 0);
        I915_WRITE(PLANE_SURF(pipe, 0), 0);
@@@ -3584,7 -3596,7 +3596,7 @@@ void intel_prepare_reset(struct drm_i91
        return;
  
  err:
 -      drm_atomic_state_free(state);
 +      drm_atomic_state_put(state);
  }
  
  void intel_finish_reset(struct drm_i915_private *dev_priv)
  
        dev_priv->modeset_restore_state = NULL;
  
-       dev_priv->modeset_restore_state = NULL;
        /* reset doesn't touch the display */
        if (!gpu_reset_clobbers_display(dev_priv)) {
                if (!state) {
                intel_hpd_init(dev_priv);
        }
  
 +      if (state)
 +              drm_atomic_state_put(state);
        drm_modeset_drop_locks(ctx);
        drm_modeset_acquire_fini(ctx);
        mutex_unlock(&dev->mode_config.mutex);
@@@ -3716,7 -3724,7 +3726,7 @@@ static void intel_update_pipe_config(st
  
                if (pipe_config->pch_pfit.enabled)
                        skylake_pfit_enable(crtc);
-       } else if (HAS_PCH_SPLIT(dev)) {
+       } else if (HAS_PCH_SPLIT(dev_priv)) {
                if (pipe_config->pch_pfit.enabled)
                        ironlake_pfit_enable(crtc);
                else if (old_crtc_state->pch_pfit.enabled)
@@@ -3736,7 -3744,7 +3746,7 @@@ static void intel_fdi_normal_train(stru
        /* enable normal train */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
-       if (IS_IVYBRIDGE(dev)) {
+       if (IS_IVYBRIDGE(dev_priv)) {
                temp &= ~FDI_LINK_TRAIN_NONE_IVB;
                temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
        } else {
  
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_NORMAL_CPT;
        } else {
        udelay(1000);
  
        /* IVB wants error correction enabled */
-       if (IS_IVYBRIDGE(dev))
+       if (IS_IVYBRIDGE(dev_priv))
                I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
                           FDI_FE_ERRC_ENABLE);
  }
@@@ -3905,7 -3913,7 +3915,7 @@@ static void gen6_fdi_link_train(struct 
  
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        } else {
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
-       if (IS_GEN6(dev)) {
+       if (IS_GEN6(dev_priv)) {
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                /* SNB-B */
                temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
        } else {
@@@ -4212,7 -4220,7 +4222,7 @@@ static void ironlake_fdi_disable(struc
        udelay(100);
  
        /* Ironlake workaround, disable clock pointer after downing FDI */
-       if (HAS_PCH_IBX(dev))
+       if (HAS_PCH_IBX(dev_priv))
                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  
        /* still set train pattern 1 */
  
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        } else {
@@@ -4547,7 -4555,7 +4557,7 @@@ static void ironlake_pch_enable(struct 
  
        assert_pch_transcoder_disabled(dev_priv, pipe);
  
-       if (IS_IVYBRIDGE(dev))
+       if (IS_IVYBRIDGE(dev_priv))
                ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  
        /* Write the TU size bits before fdi link training, so that error
  
        /* We need to program the right clock selection before writing the pixel
         * mutliplier into the DPLL. */
-       if (HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_CPT(dev_priv)) {
                u32 sel;
  
                temp = I915_READ(PCH_DPLL_SEL);
        intel_fdi_normal_train(crtc);
  
        /* For PCH DP, enable TRANS_DP_CTL */
-       if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
+       if (HAS_PCH_CPT(dev_priv) &&
+           intel_crtc_has_dp_encoder(intel_crtc->config)) {
                const struct drm_display_mode *adjusted_mode =
                        &intel_crtc->config->base.adjusted_mode;
                u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
@@@ -4669,7 -4678,7 +4680,7 @@@ skl_update_scaler(struct intel_crtc_sta
                to_intel_crtc(crtc_state->base.crtc);
        int need_scaling;
  
 -      need_scaling = intel_rotation_90_or_270(rotation) ?
 +      need_scaling = drm_rotation_90_or_270(rotation) ?
                (src_h != dst_w || src_w != dst_h):
                (src_w != dst_w || src_h != dst_h);
  
@@@ -4860,7 -4869,7 +4871,7 @@@ static void ironlake_pfit_enable(struc
                 * as some pre-programmed values are broken,
                 * e.g. x201.
                 */
-               if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+               if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
                        I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
                                                 PF_PIPE_SEL_IVB(pipe));
                else
@@@ -4885,7 -4894,7 +4896,7 @@@ void hsw_enable_ips(struct intel_crtc *
         */
  
        assert_plane_enabled(dev_priv, crtc->plane);
-       if (IS_BROADWELL(dev)) {
+       if (IS_BROADWELL(dev_priv)) {
                mutex_lock(&dev_priv->rps.hw_lock);
                WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
                mutex_unlock(&dev_priv->rps.hw_lock);
@@@ -4917,7 -4926,7 +4928,7 @@@ void hsw_disable_ips(struct intel_crtc 
                return;
  
        assert_plane_enabled(dev_priv, crtc->plane);
-       if (IS_BROADWELL(dev)) {
+       if (IS_BROADWELL(dev_priv)) {
                mutex_lock(&dev_priv->rps.hw_lock);
                WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
                mutex_unlock(&dev_priv->rps.hw_lock);
@@@ -4986,7 -4995,7 +4997,7 @@@ intel_post_enable_primary(struct drm_cr
         * FIXME: Need to fix the logic to work when we turn off all planes
         * but leave the pipe running.
         */
-       if (IS_GEN2(dev))
+       if (IS_GEN2(dev_priv))
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  
        /* Underruns don't always raise interrupts, so check manually. */
@@@ -5009,7 -5018,7 +5020,7 @@@ intel_pre_disable_primary(struct drm_cr
         * FIXME: Need to fix the logic to work when we turn off all planes
         * but leave the pipe running.
         */
-       if (IS_GEN2(dev))
+       if (IS_GEN2(dev_priv))
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  
        /*
@@@ -5041,7 -5050,7 +5052,7 @@@ intel_pre_disable_primary_noatomic(stru
         * event which is after the vblank start event, so we need to have a
         * wait-for-vblank between disabling the plane and the pipe.
         */
-       if (HAS_GMCH_DISPLAY(dev)) {
+       if (HAS_GMCH_DISPLAY(dev_priv)) {
                intel_set_memory_cxsr(dev_priv, false);
                dev_priv->wm.vlv.cxsr = false;
                intel_wait_for_vblank(dev, pipe);
@@@ -5106,7 -5115,7 +5117,7 @@@ static void intel_pre_plane_update(stru
                        intel_pre_disable_primary(&crtc->base);
        }
  
-       if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
+       if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
                crtc->wm.cxsr_allowed = false;
  
                /*
@@@ -5384,7 -5393,7 +5395,7 @@@ static void ironlake_crtc_enable(struc
  
        intel_encoders_enable(crtc, pipe_config, old_state);
  
-       if (HAS_PCH_CPT(dev))
+       if (HAS_PCH_CPT(dev_priv))
                cpt_verify_modeset(dev, intel_crtc->pipe);
  
        /* Must wait for vblank to avoid spurious PCH FIFO underruns */
  /* IPS only exists on ULT machines and is tied to pipe A. */
  static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  {
-       return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
+       return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
  }
  
  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
        /* If we change the relative order between pipe/planes enabling, we need
         * to change the workaround. */
        hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
-       if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
+       if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
                intel_wait_for_vblank(dev, hsw_workaround_pipe);
                intel_wait_for_vblank(dev, hsw_workaround_pipe);
        }
@@@ -5566,7 -5575,7 +5577,7 @@@ static void ironlake_crtc_disable(struc
        if (intel_crtc->config->has_pch_encoder) {
                ironlake_disable_pch_transcoder(dev_priv, pipe);
  
-               if (HAS_PCH_CPT(dev)) {
+               if (HAS_PCH_CPT(dev_priv)) {
                        i915_reg_t reg;
                        u32 temp;
  
@@@ -5700,13 -5709,13 +5711,13 @@@ static enum intel_display_power_domain 
  enum intel_display_power_domain
  intel_display_port_power_domain(struct intel_encoder *intel_encoder)
  {
-       struct drm_device *dev = intel_encoder->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
        struct intel_digital_port *intel_dig_port;
  
        switch (intel_encoder->type) {
        case INTEL_OUTPUT_UNKNOWN:
                /* Only DDI platforms should ever use this output type */
-               WARN_ON_ONCE(!HAS_DDI(dev));
+               WARN_ON_ONCE(!HAS_DDI(dev_priv));
        case INTEL_OUTPUT_DP:
        case INTEL_OUTPUT_HDMI:
        case INTEL_OUTPUT_EDP:
  enum intel_display_power_domain
  intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
  {
-       struct drm_device *dev = intel_encoder->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
        struct intel_digital_port *intel_dig_port;
  
        switch (intel_encoder->type) {
                 * what's the status of the given connectors, play safe and
                 * run the DP detection too.
                 */
-               WARN_ON_ONCE(!HAS_DDI(dev));
+               WARN_ON_ONCE(!HAS_DDI(dev_priv));
        case INTEL_OUTPUT_DP:
        case INTEL_OUTPUT_EDP:
                intel_dig_port = enc_to_dig_port(&intel_encoder->base);
@@@ -5836,7 -5845,7 +5847,7 @@@ static void intel_update_max_cdclk(stru
  {
        struct drm_i915_private *dev_priv = to_i915(dev);
  
-       if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+       if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
                u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
                int max_cdclk, vco;
  
                        max_cdclk = 308571;
  
                dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
-       } else if (IS_BROXTON(dev)) {
+       } else if (IS_BROXTON(dev_priv)) {
                dev_priv->max_cdclk_freq = 624000;
-       } else if (IS_BROADWELL(dev))  {
+       } else if (IS_BROADWELL(dev_priv))  {
                /*
                 * FIXME with extra cooling we can allow
                 * 540 MHz for ULX and 675 Mhz for ULT.
                 */
                if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
                        dev_priv->max_cdclk_freq = 450000;
-               else if (IS_BDW_ULX(dev))
+               else if (IS_BDW_ULX(dev_priv))
                        dev_priv->max_cdclk_freq = 450000;
-               else if (IS_BDW_ULT(dev))
+               else if (IS_BDW_ULT(dev_priv))
                        dev_priv->max_cdclk_freq = 540000;
                else
                        dev_priv->max_cdclk_freq = 675000;
-       } else if (IS_CHERRYVIEW(dev)) {
+       } else if (IS_CHERRYVIEW(dev_priv)) {
                dev_priv->max_cdclk_freq = 320000;
-       } else if (IS_VALLEYVIEW(dev)) {
+       } else if (IS_VALLEYVIEW(dev_priv)) {
                dev_priv->max_cdclk_freq = 400000;
        } else {
                /* otherwise assume cdclk is fixed */
@@@ -6677,7 -6686,7 +6688,7 @@@ static void valleyview_modeset_commit_c
         */
        intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
  
-       if (IS_CHERRYVIEW(dev))
+       if (IS_CHERRYVIEW(dev_priv))
                cherryview_set_cdclk(dev, req_cdclk);
        else
                valleyview_set_cdclk(dev, req_cdclk);
@@@ -6705,7 -6714,7 +6716,7 @@@ static void valleyview_crtc_enable(stru
        intel_set_pipe_timings(intel_crtc);
        intel_set_pipe_src_size(intel_crtc);
  
-       if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
+       if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
                struct drm_i915_private *dev_priv = to_i915(dev);
  
                I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
  
        intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
  
-       if (IS_CHERRYVIEW(dev)) {
+       if (IS_CHERRYVIEW(dev_priv)) {
                chv_prepare_pll(intel_crtc, intel_crtc->config);
                chv_enable_pll(intel_crtc, intel_crtc->config);
        } else {
@@@ -6776,7 -6785,7 +6787,7 @@@ static void i9xx_crtc_enable(struct int
  
        intel_crtc->active = true;
  
-       if (!IS_GEN2(dev))
+       if (!IS_GEN2(dev_priv))
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  
        intel_encoders_pre_enable(crtc, pipe_config, old_state);
@@@ -6824,7 -6833,7 +6835,7 @@@ static void i9xx_crtc_disable(struct in
         * On gen2 planes are double buffered but the pipe isn't, so we must
         * wait for planes to fully turn off before disabling the pipe.
         */
-       if (IS_GEN2(dev))
+       if (IS_GEN2(dev_priv))
                intel_wait_for_vblank(dev, pipe);
  
        intel_encoders_disable(crtc, old_crtc_state, old_state);
        intel_encoders_post_disable(crtc, old_crtc_state, old_state);
  
        if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
-               if (IS_CHERRYVIEW(dev))
+               if (IS_CHERRYVIEW(dev_priv))
                        chv_disable_pll(dev_priv, pipe);
-               else if (IS_VALLEYVIEW(dev))
+               else if (IS_VALLEYVIEW(dev_priv))
                        vlv_disable_pll(dev_priv, pipe);
                else
                        i9xx_disable_pll(intel_crtc);
  
        intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
  
-       if (!IS_GEN2(dev))
+       if (!IS_GEN2(dev_priv))
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  }
  
@@@ -6887,7 -6896,7 +6898,7 @@@ static void intel_crtc_disable_noatomic
  
        dev_priv->display.crtc_disable(crtc_state, state);
  
 -      drm_atomic_state_free(state);
 +      drm_atomic_state_put(state);
  
        DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
                      crtc->base.id, crtc->name);
@@@ -7029,6 -7038,7 +7040,7 @@@ static int pipe_required_fdi_lanes(stru
  static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
                                     struct intel_crtc_state *pipe_config)
  {
+       struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_atomic_state *state = pipe_config->base.state;
        struct intel_crtc *other_crtc;
        struct intel_crtc_state *other_crtc_state;
                return -EINVAL;
        }
  
-       if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
                if (pipe_config->fdi_lanes > 2) {
                        DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
                                      pipe_config->fdi_lanes);
@@@ -7226,11 -7236,11 +7238,11 @@@ static int intel_crtc_compute_config(st
        /* Cantiga+ cannot handle modes with a hsync front porch of 0.
         * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
         */
-       if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
+       if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
                adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
                return -EINVAL;
  
-       if (HAS_IPS(dev))
+       if (HAS_IPS(dev_priv))
                hsw_compute_ips_config(crtc, pipe_config);
  
        if (pipe_config->has_pch_encoder)
@@@ -7368,7 -7378,7 +7380,7 @@@ static int haswell_get_display_clock_sp
                return 450000;
        else if (freq == LCPLL_CLK_FREQ_450)
                return 450000;
-       else if (IS_HSW_ULT(dev))
+       else if (IS_HSW_ULT(dev_priv))
                return 337500;
        else
                return 540000;
@@@ -7538,9 -7548,9 +7550,9 @@@ static unsigned int intel_hpll_vco(stru
        uint8_t tmp = 0;
  
        /* FIXME other chipsets? */
-       if (IS_GM45(dev))
+       if (IS_GM45(dev_priv))
                vco_table = ctg_vco;
-       else if (IS_G4X(dev))
+       else if (IS_G4X(dev_priv))
                vco_table = elk_vco;
        else if (IS_CRESTLINE(dev))
                vco_table = cl_vco;
@@@ -7805,8 -7815,8 +7817,8 @@@ static void intel_cpu_transcoder_set_m_
                 * for gen < 8) and if DRRS is supported (to make sure the
                 * registers are not unnecessarily accessed).
                 */
-               if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
-                       crtc->config->has_drrs) {
+               if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
+                   INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
                        I915_WRITE(PIPE_DATA_M2(transcoder),
                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
                        I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@@ -8108,7 -8118,7 +8120,7 @@@ int vlv_force_pll_on(struct drm_device 
        pipe_config->pixel_multiplier = 1;
        pipe_config->dpll = *dpll;
  
-       if (IS_CHERRYVIEW(dev)) {
+       if (IS_CHERRYVIEW(to_i915(dev))) {
                chv_compute_dpll(crtc, pipe_config);
                chv_prepare_pll(crtc, pipe_config);
                chv_enable_pll(crtc, pipe_config);
   */
  void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
  {
-       if (IS_CHERRYVIEW(dev))
+       if (IS_CHERRYVIEW(to_i915(dev)))
                chv_disable_pll(to_i915(dev), pipe);
        else
                vlv_disable_pll(to_i915(dev), pipe);
@@@ -8157,7 -8167,7 +8169,7 @@@ static void i9xx_compute_dpll(struct in
        else
                dpll |= DPLLB_MODE_DAC_SERIAL;
  
-       if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+       if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
                dpll |= (crtc_state->pixel_multiplier - 1)
                        << SDVO_MULTIPLIER_SHIFT_HIRES;
        }
                dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
        else {
                dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-               if (IS_G4X(dev) && reduced_clock)
+               if (IS_G4X(dev_priv) && reduced_clock)
                        dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
        }
        switch (clock->p2) {
@@@ -8236,7 -8246,8 +8248,8 @@@ static void i8xx_compute_dpll(struct in
                        dpll |= PLL_P2_DIVIDE_BY_4;
        }
  
-       if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
+       if (!IS_I830(dev_priv) &&
+           intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
                dpll |= DPLL_DVO_2X_MODE;
  
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
@@@ -8305,7 -8316,7 +8318,7 @@@ static void intel_set_pipe_timings(stru
         * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
         * documented on the DDI_FUNC_CTL register description, EDP Input Select
         * bits. */
-       if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+       if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
            (pipe == PIPE_B || pipe == PIPE_C))
                I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  
@@@ -8415,7 -8426,8 +8428,8 @@@ static void i9xx_set_pipeconf(struct in
                pipeconf |= PIPECONF_DOUBLE_WIDE;
  
        /* only g4x and later have fancy bpc/dither controls */
-       if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+           IS_CHERRYVIEW(dev_priv)) {
                /* Bspec claims that we can't use dithering for 30bpp pipes. */
                if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
                        pipeconf |= PIPECONF_DITHER_EN |
        } else
                pipeconf |= PIPECONF_PROGRESSIVE;
  
-       if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+       if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
             intel_crtc->config->limited_color_range)
                pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  
@@@ -8659,7 -8671,8 +8673,8 @@@ static void i9xx_get_pfit_config(struc
        struct drm_i915_private *dev_priv = to_i915(dev);
        uint32_t tmp;
  
-       if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
+       if (INTEL_GEN(dev_priv) <= 3 &&
+           (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
                return;
  
        tmp = I915_READ(PFIT_CONTROL);
@@@ -8831,7 -8844,8 +8846,8 @@@ static bool i9xx_get_pipe_config(struc
        if (!(tmp & PIPECONF_ENABLE))
                goto out;
  
-       if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+           IS_CHERRYVIEW(dev_priv)) {
                switch (tmp & PIPECONF_BPC_MASK) {
                case PIPECONF_6BPC:
                        pipe_config->pipe_bpp = 18;
                }
        }
  
-       if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+       if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
            (tmp & PIPECONF_COLOR_RANGE_SELECT))
                pipe_config->limited_color_range = true;
  
  
        if (INTEL_INFO(dev)->gen >= 4) {
                /* No way to read it out on pipes B and C */
-               if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
+               if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
                        tmp = dev_priv->chv_dpll_md[crtc->pipe];
                else
                        tmp = I915_READ(DPLL_MD(crtc->pipe));
                        ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
                         >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
                pipe_config->dpll_hw_state.dpll_md = tmp;
-       } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+       } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
+                  IS_G33(dev_priv)) {
                tmp = I915_READ(DPLL(crtc->pipe));
                pipe_config->pixel_multiplier =
                        ((tmp & SDVO_MULTIPLIER_MASK)
                pipe_config->pixel_multiplier = 1;
        }
        pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
-       if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+       if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
                /*
                 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
                 * on 830. Filter it out here so that we don't
                 * report errors due to that.
                 */
-               if (IS_I830(dev))
+               if (IS_I830(dev_priv))
                        pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
  
                pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
                                                     DPLL_PORTB_READY_MASK);
        }
  
-       if (IS_CHERRYVIEW(dev))
+       if (IS_CHERRYVIEW(dev_priv))
                chv_crtc_clock_get(crtc, pipe_config);
-       else if (IS_VALLEYVIEW(dev))
+       else if (IS_VALLEYVIEW(dev_priv))
                vlv_crtc_clock_get(crtc, pipe_config);
        else
                i9xx_crtc_clock_get(crtc, pipe_config);
@@@ -8952,7 -8967,7 +8969,7 @@@ static void ironlake_init_pch_refclk(st
                }
        }
  
-       if (HAS_PCH_IBX(dev)) {
+       if (HAS_PCH_IBX(dev_priv)) {
                has_ck505 = dev_priv->vbt.display_clock_mode;
                can_ssc = has_ck505;
        } else {
@@@ -9200,7 -9215,8 +9217,8 @@@ static void lpt_enable_clkout_dp(struc
  
        if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
                with_spread = true;
-       if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
+       if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
+           with_fdi, "LP PCH doesn't have FDI\n"))
                with_fdi = false;
  
        mutex_lock(&dev_priv->sb_lock);
                }
        }
  
-       reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
+       reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
        tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
        tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
        intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
@@@ -9239,7 -9255,7 +9257,7 @@@ static void lpt_disable_clkout_dp(struc
  
        mutex_lock(&dev_priv->sb_lock);
  
-       reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
+       reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
        tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
        tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
        intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
@@@ -9347,9 -9363,11 +9365,11 @@@ static void lpt_init_pch_refclk(struct 
   */
  void intel_init_pch_refclk(struct drm_device *dev)
  {
-       if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+       struct drm_i915_private *dev_priv = to_i915(dev);
+       if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
                ironlake_init_pch_refclk(dev);
-       else if (HAS_PCH_LPT(dev))
+       else if (HAS_PCH_LPT(dev_priv))
                lpt_init_pch_refclk(dev);
  }
  
@@@ -9478,7 -9496,7 +9498,7 @@@ static void ironlake_compute_dpll(struc
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
                if ((intel_panel_use_ssc(dev_priv) &&
                     dev_priv->vbt.lvds_ssc_freq == 100000) ||
-                   (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
+                   (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
                        factor = 25;
        } else if (crtc_state->sdvo_tv_clock)
                factor = 20;
@@@ -9838,7 -9856,7 +9858,7 @@@ static void ironlake_get_pfit_config(st
                /* We currently do not free assignements of panel fitters on
                 * ivb/hsw (since we don't use the higher upscaling modes which
                 * differentiates them) so just WARN about this case for now. */
-               if (IS_GEN7(dev)) {
+               if (IS_GEN7(dev_priv)) {
                        WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
                                PF_PIPE_SEL_IVB(crtc->pipe));
                }
@@@ -9883,7 -9901,7 +9903,7 @@@ ironlake_get_initial_plane_config(struc
        fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  
        base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
-       if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
                offset = I915_READ(DSPOFFSET(pipe));
        } else {
                if (plane_config->tiling)
@@@ -10027,7 -10045,7 +10047,7 @@@ static void assert_can_disable_lcpll(st
        I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
        I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
             "CPU PWM1 enabled\n");
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
                     "CPU PWM2 enabled\n");
        I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  
  static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
  {
-       struct drm_device *dev = &dev_priv->drm;
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                return I915_READ(D_COMP_HSW);
        else
                return I915_READ(D_COMP_BDW);
  
  static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
  {
-       struct drm_device *dev = &dev_priv->drm;
-       if (IS_HASWELL(dev)) {
+       if (IS_HASWELL(dev_priv)) {
                mutex_lock(&dev_priv->rps.hw_lock);
                if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
                                            val))
@@@ -10207,7 -10221,7 +10223,7 @@@ void hsw_enable_pc8(struct drm_i915_pri
  
        DRM_DEBUG_KMS("Enabling package C8+\n");
  
-       if (HAS_PCH_LPT_LP(dev)) {
+       if (HAS_PCH_LPT_LP(dev_priv)) {
                val = I915_READ(SOUTH_DSPCLK_GATE_D);
                val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
                I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@@ -10227,7 -10241,7 +10243,7 @@@ void hsw_disable_pc8(struct drm_i915_pr
        hsw_restore_lcpll(dev_priv);
        lpt_init_pch_refclk(dev);
  
-       if (HAS_PCH_LPT_LP(dev)) {
+       if (HAS_PCH_LPT_LP(dev_priv)) {
                val = I915_READ(SOUTH_DSPCLK_GATE_D);
                val |= PCH_LP_PARTITION_LEVEL_DISABLE;
                I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@@ -10651,9 -10665,9 +10667,9 @@@ static void haswell_get_ddi_port_state(
  
        port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
  
-       if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+       if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
                skylake_get_ddi_pll(dev_priv, port, pipe_config);
-       else if (IS_BROXTON(dev))
+       else if (IS_BROXTON(dev_priv))
                bxt_get_ddi_pll(dev_priv, port, pipe_config);
        else
                haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@@ -10736,7 -10750,7 +10752,7 @@@ static bool haswell_get_pipe_config(str
                        ironlake_get_pfit_config(crtc, pipe_config);
        }
  
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
                        (I915_READ(IPS_CTL) & IPS_ENABLE);
  
@@@ -10824,12 -10838,15 +10840,15 @@@ static void i9xx_update_cursor(struct d
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
        const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
+       const struct skl_plane_wm *p_wm =
+               &cstate->wm.skl.optimal.planes[PLANE_CURSOR];
        int pipe = intel_crtc->pipe;
        uint32_t cntl = 0;
  
        if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
-               skl_write_cursor_wm(intel_crtc, wm);
+               skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
  
        if (plane_state && plane_state->base.visible) {
                cntl = MCURSOR_GAMMA_ENABLE;
                }
                cntl |= pipe << 28; /* Connect to correct pipe */
  
-               if (HAS_DDI(dev))
+               if (HAS_DDI(dev_priv))
                        cntl |= CURSOR_PIPE_CSC_ENABLE;
  
                if (plane_state->base.rotation == DRM_ROTATE_180)
@@@ -10897,7 -10914,7 +10916,7 @@@ static void intel_crtc_update_cursor(st
                pos |= y << CURSOR_Y_SHIFT;
  
                /* ILK+ do this automagically */
-               if (HAS_GMCH_DISPLAY(dev) &&
+               if (HAS_GMCH_DISPLAY(dev_priv) &&
                    plane_state->base.rotation == DRM_ROTATE_180) {
                        base += (plane_state->base.crtc_h *
                                 plane_state->base.crtc_w - 1) * 4;
  
        I915_WRITE(CURPOS(pipe), pos);
  
-       if (IS_845G(dev) || IS_I865G(dev))
+       if (IS_845G(dev_priv) || IS_I865G(dev_priv))
                i845_update_cursor(crtc, base, plane_state);
        else
                i9xx_update_cursor(crtc, base, plane_state);
  }
  
- static bool cursor_size_ok(struct drm_device *dev,
+ static bool cursor_size_ok(struct drm_i915_private *dev_priv,
                           uint32_t width, uint32_t height)
  {
        if (width == 0 || height == 0)
         * the precision of the register. Everything else requires
         * square cursors, limited to a few power-of-two sizes.
         */
-       if (IS_845G(dev) || IS_I865G(dev)) {
+       if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
                if ((width & 63) != 0)
                        return false;
  
-               if (width > (IS_845G(dev) ? 64 : 512))
+               if (width > (IS_845G(dev_priv) ? 64 : 512))
                        return false;
  
                if (height > 1023)
                switch (width | height) {
                case 256:
                case 128:
-                       if (IS_GEN2(dev))
+                       if (IS_GEN2(dev_priv))
                                return false;
                case 64:
                        break;
        return true;
  
  fail:
 -      drm_atomic_state_free(state);
 -      drm_atomic_state_free(restore_state);
 -      restore_state = state = NULL;
 +      if (state) {
 +              drm_atomic_state_put(state);
 +              state = NULL;
 +      }
 +      if (restore_state) {
 +              drm_atomic_state_put(restore_state);
 +              restore_state = NULL;
 +      }
  
        if (ret == -EDEADLK) {
                drm_modeset_backoff(ctx);
@@@ -11307,9 -11319,10 +11326,9 @@@ void intel_release_load_detect_pipe(str
                return;
  
        ret = drm_atomic_commit(state);
 -      if (ret) {
 +      if (ret)
                DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
 -              drm_atomic_state_free(state);
 -      }
 +      drm_atomic_state_put(state);
  }
  
  static int i9xx_pll_refclk(struct drm_device *dev,
  
        if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
                return dev_priv->vbt.lvds_ssc_freq;
-       else if (HAS_PCH_SPLIT(dev))
+       else if (HAS_PCH_SPLIT(dev_priv))
                return 120000;
-       else if (!IS_GEN2(dev))
+       else if (!IS_GEN2(dev_priv))
                return 96000;
        else
                return 48000;
@@@ -11355,7 -11368,7 +11374,7 @@@ static void i9xx_crtc_clock_get(struct 
                clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
        }
  
-       if (!IS_GEN2(dev)) {
+       if (!IS_GEN2(dev_priv)) {
                if (IS_PINEVIEW(dev))
                        clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
                                DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
                else
                        port_clock = i9xx_calc_dpll_params(refclk, &clock);
        } else {
-               u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
+               u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
                bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
  
                if (is_lvds) {
@@@ -11584,7 -11597,7 +11603,7 @@@ static bool __pageflip_finished_cs(stru
         * really needed there. But since ctg has the registers,
         * include it in the check anyway.
         */
-       if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
+       if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
                return true;
  
        /*
@@@ -11854,6 -11867,7 +11873,7 @@@ static int intel_gen7_queue_flip(struc
                                 struct drm_i915_gem_request *req,
                                 uint32_t flags)
  {
+       struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_ring *ring = req->ring;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        uint32_t plane_bit = 0;
                 * 48bits addresses, and we need a NOOP for the batch size to
                 * stay even.
                 */
-               if (IS_GEN8(dev))
+               if (IS_GEN8(dev_priv))
                        len += 2;
        }
  
                intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
                                          DERRMR_PIPEB_PRI_FLIP_DONE |
                                          DERRMR_PIPEC_PRI_FLIP_DONE));
-               if (IS_GEN8(dev))
+               if (IS_GEN8(dev_priv))
                        intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
                                              MI_SRM_LRM_GLOBAL_GTT);
                else
                intel_ring_emit_reg(ring, DERRMR);
                intel_ring_emit(ring,
                                i915_ggtt_offset(req->engine->scratch) + 256);
-               if (IS_GEN8(dev)) {
+               if (IS_GEN8(dev_priv)) {
                        intel_ring_emit(ring, 0);
                        intel_ring_emit(ring, MI_NOOP);
                }
@@@ -12247,23 -12261,23 +12267,23 @@@ static int intel_crtc_page_flip(struct 
  
        atomic_inc(&intel_crtc->unpin_work_count);
  
-       if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+       if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
                work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
  
-       if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-               engine = &dev_priv->engine[BCS];
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+               engine = dev_priv->engine[BCS];
                if (fb->modifier[0] != old_fb->modifier[0])
                        /* vlv: DISPLAY_FLIP fails to change tiling */
                        engine = NULL;
-       } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
-               engine = &dev_priv->engine[BCS];
+       } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
+               engine = dev_priv->engine[BCS];
        } else if (INTEL_INFO(dev)->gen >= 7) {
                engine = i915_gem_active_get_engine(&obj->last_write,
                                                    &obj->base.dev->struct_mutex);
                if (engine == NULL || engine->id != RCS)
-                       engine = &dev_priv->engine[BCS];
+                       engine = dev_priv->engine[BCS];
        } else {
-               engine = &dev_priv->engine[RCS];
+               engine = dev_priv->engine[RCS];
        }
  
        mmio_flip = use_mmio_flip(engine, obj);
  
                work->flip_queued_req = i915_gem_active_get(&obj->last_write,
                                                            &obj->base.dev->struct_mutex);
-               schedule_work(&work->mmio_work);
+               queue_work(system_unbound_wq, &work->mmio_work);
        } else {
                request = i915_gem_request_alloc(engine, engine->last_context);
                if (IS_ERR(request)) {
@@@ -12377,7 -12391,8 +12397,7 @@@ retry
                        goto retry;
                }
  
 -              if (ret)
 -                      drm_atomic_state_free(state);
 +              drm_atomic_state_put(state);
  
                if (ret == 0 && event) {
                        spin_lock_irq(&dev->event_lock);
@@@ -12451,7 -12466,7 +12471,7 @@@ int intel_plane_atomic_calc_changes(str
        struct drm_framebuffer *fb = plane_state->fb;
        int ret;
  
-       if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
+       if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
                ret = skl_update_scaler_plane(
                        to_intel_crtc_state(crtc_state),
                        to_intel_plane_state(plane_state));
         * cstate->update_wm was already set above, so this flag will
         * take effect when we commit and program watermarks.
         */
-       if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
+       if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
            needs_scaling(to_intel_plane_state(plane_state)) &&
            !needs_scaling(old_plane_state))
                pipe_config->disable_lp_wm = true;
@@@ -12706,15 -12721,16 +12726,16 @@@ static in
  compute_baseline_pipe_bpp(struct intel_crtc *crtc,
                          struct intel_crtc_state *pipe_config)
  {
-       struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct drm_atomic_state *state;
        struct drm_connector *connector;
        struct drm_connector_state *connector_state;
        int bpp, i;
  
-       if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
+       if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+           IS_CHERRYVIEW(dev_priv)))
                bpp = 10*3;
-       else if (INTEL_INFO(dev)->gen >= 5)
+       else if (INTEL_GEN(dev_priv) >= 5)
                bpp = 12*3;
        else
                bpp = 8*3;
@@@ -12752,6 -12768,7 +12773,7 @@@ static void intel_dump_pipe_config(stru
                                   const char *context)
  {
        struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_plane *plane;
        struct intel_plane *intel_plane;
        struct intel_plane_state *state;
        DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
        DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  
-       if (IS_BROXTON(dev)) {
+       if (IS_BROXTON(dev_priv)) {
                DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
                              "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
                              "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
                              pipe_config->dpll_hw_state.pll9,
                              pipe_config->dpll_hw_state.pll10,
                              pipe_config->dpll_hw_state.pcsdw12);
-       } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+       } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
                DRM_DEBUG_KMS("dpll_hw_state: "
                              "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
                              pipe_config->dpll_hw_state.ctrl1,
                              pipe_config->dpll_hw_state.cfgcr1,
                              pipe_config->dpll_hw_state.cfgcr2);
-       } else if (HAS_DDI(dev)) {
+       } else if (HAS_DDI(dev_priv)) {
                DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
                              pipe_config->dpll_hw_state.wrpll,
                              pipe_config->dpll_hw_state.spll);
@@@ -12912,7 -12929,7 +12934,7 @@@ static bool check_digital_port_conflict
                switch (encoder->type) {
                        unsigned int port_mask;
                case INTEL_OUTPUT_UNKNOWN:
-                       if (WARN_ON(!HAS_DDI(dev)))
+                       if (WARN_ON(!HAS_DDI(to_i915(dev))))
                                break;
                case INTEL_OUTPUT_DP:
                case INTEL_OUTPUT_HDMI:
@@@ -13198,6 -13215,7 +13220,7 @@@ intel_pipe_config_compare(struct drm_de
                          struct intel_crtc_state *pipe_config,
                          bool adjust)
  {
+       struct drm_i915_private *dev_priv = to_i915(dev);
        bool ret = true;
  
  #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
  
        PIPE_CONF_CHECK_I(pixel_multiplier);
        PIPE_CONF_CHECK_I(has_hdmi_sink);
-       if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
-           IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+       if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
+           IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                PIPE_CONF_CHECK_I(limited_color_range);
        PIPE_CONF_CHECK_I(has_infoframe);
  
        }
  
        /* BDW+ don't expose a synchronous way to read the state */
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                PIPE_CONF_CHECK_I(ips_enabled);
  
        PIPE_CONF_CHECK_I(double_wide);
        PIPE_CONF_CHECK_X(dsi_pll.ctrl);
        PIPE_CONF_CHECK_X(dsi_pll.div);
  
-       if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
+       if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
                PIPE_CONF_CHECK_I(pipe_bpp);
  
        PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
@@@ -13444,30 -13462,65 +13467,65 @@@ static void verify_wm_state(struct drm_
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct skl_ddb_allocation hw_ddb, *sw_ddb;
-       struct skl_ddb_entry *hw_entry, *sw_entry;
+       struct skl_pipe_wm hw_wm, *sw_wm;
+       struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
+       struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        const enum pipe pipe = intel_crtc->pipe;
-       int plane;
+       int plane, level, max_level = ilk_wm_max_level(dev_priv);
  
        if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
                return;
  
+       skl_pipe_wm_get_hw_state(crtc, &hw_wm);
+       sw_wm = &intel_crtc->wm.active.skl;
        skl_ddb_get_hw_state(dev_priv, &hw_ddb);
        sw_ddb = &dev_priv->wm.skl_hw.ddb;
  
        /* planes */
        for_each_plane(dev_priv, pipe, plane) {
-               hw_entry = &hw_ddb.plane[pipe][plane];
-               sw_entry = &sw_ddb->plane[pipe][plane];
+               hw_plane_wm = &hw_wm.planes[plane];
+               sw_plane_wm = &sw_wm->planes[plane];
  
-               if (skl_ddb_entry_equal(hw_entry, sw_entry))
-                       continue;
+               /* Watermarks */
+               for (level = 0; level <= max_level; level++) {
+                       if (skl_wm_level_equals(&hw_plane_wm->wm[level],
+                                               &sw_plane_wm->wm[level]))
+                               continue;
+                       DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+                                 pipe_name(pipe), plane + 1, level,
+                                 sw_plane_wm->wm[level].plane_en,
+                                 sw_plane_wm->wm[level].plane_res_b,
+                                 sw_plane_wm->wm[level].plane_res_l,
+                                 hw_plane_wm->wm[level].plane_en,
+                                 hw_plane_wm->wm[level].plane_res_b,
+                                 hw_plane_wm->wm[level].plane_res_l);
+               }
  
-               DRM_ERROR("mismatch in DDB state pipe %c plane %d "
-                         "(expected (%u,%u), found (%u,%u))\n",
-                         pipe_name(pipe), plane + 1,
-                         sw_entry->start, sw_entry->end,
-                         hw_entry->start, hw_entry->end);
+               if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
+                                        &sw_plane_wm->trans_wm)) {
+                       DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+                                 pipe_name(pipe), plane + 1,
+                                 sw_plane_wm->trans_wm.plane_en,
+                                 sw_plane_wm->trans_wm.plane_res_b,
+                                 sw_plane_wm->trans_wm.plane_res_l,
+                                 hw_plane_wm->trans_wm.plane_en,
+                                 hw_plane_wm->trans_wm.plane_res_b,
+                                 hw_plane_wm->trans_wm.plane_res_l);
+               }
+               /* DDB */
+               hw_ddb_entry = &hw_ddb.plane[pipe][plane];
+               sw_ddb_entry = &sw_ddb->plane[pipe][plane];
+               if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
+                       DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
+                                 pipe_name(pipe), plane + 1,
+                                 sw_ddb_entry->start, sw_ddb_entry->end,
+                                 hw_ddb_entry->start, hw_ddb_entry->end);
+               }
        }
  
        /*
         * once the plane becomes visible, we can skip this check
         */
        if (intel_crtc->cursor_addr) {
-               hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
-               sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
+               hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
+               sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
  
-               if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
-                       DRM_ERROR("mismatch in DDB state pipe %c cursor "
-                                 "(expected (%u,%u), found (%u,%u))\n",
+               /* Watermarks */
+               for (level = 0; level <= max_level; level++) {
+                       if (skl_wm_level_equals(&hw_plane_wm->wm[level],
+                                               &sw_plane_wm->wm[level]))
+                               continue;
+                       DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+                                 pipe_name(pipe), level,
+                                 sw_plane_wm->wm[level].plane_en,
+                                 sw_plane_wm->wm[level].plane_res_b,
+                                 sw_plane_wm->wm[level].plane_res_l,
+                                 hw_plane_wm->wm[level].plane_en,
+                                 hw_plane_wm->wm[level].plane_res_b,
+                                 hw_plane_wm->wm[level].plane_res_l);
+               }
+               if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
+                                        &sw_plane_wm->trans_wm)) {
+                       DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+                                 pipe_name(pipe),
+                                 sw_plane_wm->trans_wm.plane_en,
+                                 sw_plane_wm->trans_wm.plane_res_b,
+                                 sw_plane_wm->trans_wm.plane_res_l,
+                                 hw_plane_wm->trans_wm.plane_en,
+                                 hw_plane_wm->trans_wm.plane_res_b,
+                                 hw_plane_wm->trans_wm.plane_res_l);
+               }
+               /* DDB */
+               hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
+               sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
+               if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
+                       DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
                                  pipe_name(pipe),
-                                 sw_entry->start, sw_entry->end,
-                                 hw_entry->start, hw_entry->end);
+                                 sw_ddb_entry->start, sw_ddb_entry->end,
+                                 hw_ddb_entry->start, hw_ddb_entry->end);
                }
        }
  }
@@@ -13736,7 -13820,7 +13825,7 @@@ intel_modeset_verify_disabled(struct dr
  
  static void update_scanline_offset(struct intel_crtc *crtc)
  {
-       struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  
        /*
         * The scanline counter increments at the leading edge of hsync.
         * there's an extra 1 line difference. So we need to add two instead of
         * one to the value.
         */
-       if (IS_GEN2(dev)) {
+       if (IS_GEN2(dev_priv)) {
                const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
                int vtotal;
  
                        vtotal /= 2;
  
                crtc->scanline_offset = vtotal - 1;
-       } else if (HAS_DDI(dev) &&
+       } else if (HAS_DDI(dev_priv) &&
                   intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
                crtc->scanline_offset = 2;
        } else
@@@ -14243,12 -14327,11 +14332,11 @@@ static void skl_update_crtcs(struct drm
                             unsigned int *crtc_vblank_mask)
  {
        struct drm_device *dev = state->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
        struct drm_crtc *crtc;
+       struct intel_crtc *intel_crtc;
        struct drm_crtc_state *old_crtc_state;
-       struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
-       struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
+       struct intel_crtc_state *cstate;
        unsigned int updated = 0;
        bool progress;
        enum pipe pipe;
                for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
                        bool vbl_wait = false;
                        unsigned int cmask = drm_crtc_mask(crtc);
-                       pipe = to_intel_crtc(crtc)->pipe;
+                       intel_crtc = to_intel_crtc(crtc);
+                       cstate = to_intel_crtc_state(crtc->state);
+                       pipe = intel_crtc->pipe;
  
                        if (updated & cmask || !crtc->state->active)
                                continue;
-                       if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
-                                                       pipe))
+                       if (skl_ddb_allocation_overlaps(state, intel_crtc))
                                continue;
  
                        updated |= cmask;
                         * then we need to wait for a vblank to pass for the
                         * new ddb allocation to take effect.
                         */
-                       if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
+                       if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
+                                                &intel_crtc->hw_ddb) &&
                            !crtc->state->active_changed &&
                            intel_state->wm_results.dirty_pipes != updated)
                                vbl_wait = true;
@@@ -14462,7 -14548,7 +14553,7 @@@ static void intel_atomic_commit_tail(st
  
        drm_atomic_helper_commit_cleanup_done(state);
  
 -      drm_atomic_state_free(state);
 +      drm_atomic_state_put(state);
  
        /* As one of the primary mmio accessors, KMS has a high likelihood
         * of triggering bugs in unclaimed access. After we finish
@@@ -14545,7 -14631,6 +14636,7 @@@ static int intel_atomic_commit(struct d
        intel_shared_dpll_commit(state);
        intel_atomic_track_fbs(state);
  
 +      drm_atomic_state_get(state);
        if (nonblock)
                queue_work(system_unbound_wq, &state->commit_work);
        else
@@@ -14587,8 -14672,9 +14678,8 @@@ retry
                goto retry;
        }
  
 -      if (ret)
  out:
 -              drm_atomic_state_free(state);
 +      drm_atomic_state_put(state);
  }
  
  /*
@@@ -14662,6 -14748,7 +14753,7 @@@ intel_prepare_plane_fb(struct drm_plan
                       struct drm_plane_state *new_state)
  {
        struct drm_device *dev = plane->dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_framebuffer *fb = new_state->fb;
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
  
        if (plane->type == DRM_PLANE_TYPE_CURSOR &&
            INTEL_INFO(dev)->cursor_needs_physical) {
-               int align = IS_I830(dev) ? 16 * 1024 : 256;
+               int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
                ret = i915_gem_object_attach_phys(obj, align);
                if (ret)
                        DRM_DEBUG_KMS("failed to attach phys object\n");
@@@ -14838,6 -14925,8 +14930,8 @@@ static void intel_begin_crtc_commit(str
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       struct intel_crtc_state *intel_cstate =
+               to_intel_crtc_state(crtc->state);
        struct intel_crtc_state *old_intel_state =
                to_intel_crtc_state(old_crtc_state);
        bool modeset = needs_modeset(crtc->state);
                intel_color_load_luts(crtc->state);
        }
  
-       if (to_intel_crtc_state(crtc->state)->update_pipe)
+       if (intel_cstate->update_pipe) {
                intel_update_pipe_config(intel_crtc, old_intel_state);
-       else if (INTEL_GEN(dev_priv) >= 9) {
+       else if (INTEL_GEN(dev_priv) >= 9) {
                skl_detach_scalers(intel_crtc);
  
                I915_WRITE(PIPE_WM_LINETIME(pipe),
-                          dev_priv->wm.skl_hw.wm_linetime[pipe]);
+                          intel_cstate->wm.skl.optimal.linetime);
        }
  }
  
@@@ -14903,10 -14992,10 +14997,11 @@@ const struct drm_plane_funcs intel_plan
  static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
                                                    int pipe)
  {
+       struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_plane *primary = NULL;
        struct intel_plane_state *state = NULL;
        const uint32_t *intel_primary_formats;
 +      unsigned int supported_rotations;
        unsigned int num_formats;
        int ret;
  
  
                primary->update_plane = skylake_update_primary_plane;
                primary->disable_plane = skylake_disable_primary_plane;
-       } else if (HAS_PCH_SPLIT(dev)) {
+       } else if (HAS_PCH_SPLIT(dev_priv)) {
                intel_primary_formats = i965_primary_formats;
                num_formats = ARRAY_SIZE(i965_primary_formats);
  
                                               intel_primary_formats, num_formats,
                                               DRM_PLANE_TYPE_PRIMARY,
                                               "plane 1%c", pipe_name(pipe));
-       else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+       else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
                ret = drm_universal_plane_init(dev, &primary->base, 0,
                                               &intel_plane_funcs,
                                               intel_primary_formats, num_formats,
        if (ret)
                goto fail;
  
-       if (INTEL_GEN(dev) >= 9) {
 -      if (INTEL_INFO(dev)->gen >= 4)
 -              intel_create_rotation_property(dev, primary);
++      if (INTEL_GEN(dev_priv) >= 9) {
 +              supported_rotations =
 +                      DRM_ROTATE_0 | DRM_ROTATE_90 |
 +                      DRM_ROTATE_180 | DRM_ROTATE_270;
-       } else if (INTEL_GEN(dev) >= 4) {
++      } else if (INTEL_GEN(dev_priv) >= 4) {
 +              supported_rotations =
 +                      DRM_ROTATE_0 | DRM_ROTATE_180;
 +      } else {
 +              supported_rotations = DRM_ROTATE_0;
 +      }
 +
-       if (INTEL_GEN(dev) >= 4)
++      if (INTEL_GEN(dev_priv) >= 4)
 +              drm_plane_create_rotation_property(&primary->base,
 +                                                 DRM_ROTATE_0,
 +                                                 supported_rotations);
  
        drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
  
        return NULL;
  }
  
 -void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
 -{
 -      if (!dev->mode_config.rotation_property) {
 -              unsigned long flags = DRM_ROTATE_0 |
 -                      DRM_ROTATE_180;
 -
 -              if (INTEL_INFO(dev)->gen >= 9)
 -                      flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
 -
 -              dev->mode_config.rotation_property =
 -                      drm_mode_create_rotation_property(dev, flags);
 -      }
 -      if (dev->mode_config.rotation_property)
 -              drm_object_attach_property(&plane->base.base,
 -                              dev->mode_config.rotation_property,
 -                              plane->base.state->rotation);
 -}
 -
  static int
  intel_check_cursor_plane(struct drm_plane *plane,
                         struct intel_crtc_state *crtc_state,
                return 0;
  
        /* Check for which cursor types we support */
-       if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
+       if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
+                           state->base.crtc_h)) {
                DRM_DEBUG("Cursor dimension %dx%d not supported\n",
                          state->base.crtc_w, state->base.crtc_h);
                return -EINVAL;
         * display power well must be turned off and on again.
         * Refuse the put the cursor into that compromised position.
         */
-       if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
+       if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
            state->base.visible && state->base.crtc_x < 0) {
                DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
                return -EINVAL;
@@@ -15101,6 -15196,6 +15197,7 @@@ intel_update_cursor_plane(struct drm_pl
  static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
                                                   int pipe)
  {
++      struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_plane *cursor = NULL;
        struct intel_plane_state *state = NULL;
        int ret;
        if (ret)
                goto fail;
  
-       if (INTEL_GEN(dev) >= 4)
 -      if (INTEL_INFO(dev)->gen >= 4) {
 -              if (!dev->mode_config.rotation_property)
 -                      dev->mode_config.rotation_property =
 -                              drm_mode_create_rotation_property(dev,
 -                                                      DRM_ROTATE_0 |
 -                                                      DRM_ROTATE_180);
 -              if (dev->mode_config.rotation_property)
 -                      drm_object_attach_property(&cursor->base.base,
 -                              dev->mode_config.rotation_property,
 -                              state->base.rotation);
 -      }
++      if (INTEL_GEN(dev_priv) >= 4)
 +              drm_plane_create_rotation_property(&cursor->base,
 +                                                 DRM_ROTATE_0,
 +                                                 DRM_ROTATE_0 |
 +                                                 DRM_ROTATE_180);
  
        if (INTEL_INFO(dev)->gen >=9)
                state->scaler_id = -1;
@@@ -15305,7 -15406,7 +15402,7 @@@ static bool has_edp_a(struct drm_devic
        if ((I915_READ(DP_A) & DP_DETECTED) == 0)
                return false;
  
-       if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
+       if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
                return false;
  
        return true;
@@@ -15318,17 -15419,18 +15415,18 @@@ static bool intel_crt_present(struct dr
        if (INTEL_INFO(dev)->gen >= 9)
                return false;
  
-       if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
+       if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
                return false;
  
-       if (IS_CHERRYVIEW(dev))
+       if (IS_CHERRYVIEW(dev_priv))
                return false;
  
-       if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
+       if (HAS_PCH_LPT_H(dev_priv) &&
+           I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
                return false;
  
        /* DDI E can't be used if DDI A requires 4 lanes */
-       if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+       if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
                return false;
  
        if (!dev_priv->vbt.int_crt_support)
@@@ -15391,7 -15493,7 +15489,7 @@@ static void intel_setup_outputs(struct 
        if (intel_crt_present(dev))
                intel_crt_init(dev);
  
-       if (IS_BROXTON(dev)) {
+       if (IS_BROXTON(dev_priv)) {
                /*
                 * FIXME: Broxton doesn't support port detection via the
                 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
                intel_ddi_init(dev, PORT_C);
  
                intel_dsi_init(dev);
-       } else if (HAS_DDI(dev)) {
+       } else if (HAS_DDI(dev_priv)) {
                int found;
  
                /*
                 */
                found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
                /* WaIgnoreDDIAStrap: skl */
-               if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+               if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
                        intel_ddi_init(dev, PORT_A);
  
                /* DDI B, C and D detection is indicated by the SFUSE_STRAP
                /*
                 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
                 */
-               if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
+               if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
                    (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
                     dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
                     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
                        intel_ddi_init(dev, PORT_E);
  
-       } else if (HAS_PCH_SPLIT(dev)) {
+       } else if (HAS_PCH_SPLIT(dev_priv)) {
                int found;
                dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
  
  
                if (I915_READ(PCH_DP_D) & DP_DETECTED)
                        intel_dp_init(dev, PCH_DP_D, PORT_D);
-       } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                bool has_edp, has_port;
  
                /*
                if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
                        intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
  
-               if (IS_CHERRYVIEW(dev)) {
+               if (IS_CHERRYVIEW(dev_priv)) {
                        /*
                         * eDP not supported on port D,
                         * so no need to worry about it
                }
  
                intel_dsi_init(dev);
-       } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
+       } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
                bool found = false;
  
                if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
                        DRM_DEBUG_KMS("probing SDVOB\n");
                        found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
-                       if (!found && IS_G4X(dev)) {
+                       if (!found && IS_G4X(dev_priv)) {
                                DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
                                intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
                        }
  
-                       if (!found && IS_G4X(dev))
+                       if (!found && IS_G4X(dev_priv))
                                intel_dp_init(dev, DP_B, PORT_B);
                }
  
  
                if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  
-                       if (IS_G4X(dev)) {
+                       if (IS_G4X(dev_priv)) {
                                DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
                                intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
                        }
-                       if (IS_G4X(dev))
+                       if (IS_G4X(dev_priv))
                                intel_dp_init(dev, DP_C, PORT_C);
                }
  
-               if (IS_G4X(dev) &&
-                   (I915_READ(DP_D) & DP_DETECTED))
+               if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
                        intel_dp_init(dev, DP_D, PORT_D);
-       } else if (IS_GEN2(dev))
+       } else if (IS_GEN2(dev_priv))
                intel_dvo_init(dev);
  
        if (SUPPORTS_TV(dev))
@@@ -15612,10 -15713,10 +15709,10 @@@ static const struct drm_framebuffer_fun
  };
  
  static
- u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
-                        uint32_t pixel_format)
+ u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
+                        uint64_t fb_modifier, uint32_t pixel_format)
  {
-       u32 gen = INTEL_INFO(dev)->gen;
+       u32 gen = INTEL_INFO(dev_priv)->gen;
  
        if (gen >= 9) {
                int cpp = drm_format_plane_cpp(pixel_format, 0);
                 *  pixels and 32K bytes."
                 */
                return min(8192 * cpp, 32768);
-       } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+       } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
+                  !IS_CHERRYVIEW(dev_priv)) {
                return 32*1024;
        } else if (gen >= 4) {
                if (fb_modifier == I915_FORMAT_MOD_X_TILED)
@@@ -15711,7 -15813,7 +15809,7 @@@ static int intel_framebuffer_init(struc
                return -EINVAL;
        }
  
-       pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
+       pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
                                           mode_cmd->pixel_format);
        if (mode_cmd->pitches[0] > pitch_limit) {
                DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
                }
                break;
        case DRM_FORMAT_ABGR8888:
-               if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+               if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
                    INTEL_INFO(dev)->gen < 9) {
                        format_name = drm_get_format_name(mode_cmd->pixel_format);
                        DRM_DEBUG("unsupported pixel format: %s\n", format_name);
                }
                break;
        case DRM_FORMAT_ABGR2101010:
-               if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+               if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
                        format_name = drm_get_format_name(mode_cmd->pixel_format);
                        DRM_DEBUG("unsupported pixel format: %s\n", format_name);
                        kfree(format_name);
@@@ -15835,12 -15937,6 +15933,6 @@@ intel_user_framebuffer_create(struct dr
        return fb;
  }
  
- #ifndef CONFIG_DRM_FBDEV_EMULATION
- static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
- {
- }
- #endif
  static const struct drm_mode_config_funcs intel_mode_funcs = {
        .fb_create = intel_user_framebuffer_create,
        .output_poll_changed = intel_fbdev_output_poll_changed,
@@@ -16221,7 -16317,7 +16313,7 @@@ static void i915_disable_vga(struct drm
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct pci_dev *pdev = dev_priv->drm.pdev;
        u8 sr1;
-       i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
+       i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
  
        /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
        vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
@@@ -16309,7 -16405,7 +16401,7 @@@ retry
                 * BIOS-programmed watermarks untouched and hope for the best.
                 */
                WARN(true, "Could not determine valid watermarks for inherited state\n");
 -              goto fail;
 +              goto put_state;
        }
  
        /* Write calculated watermark values back */
                dev_priv->display.optimize_watermarks(cs);
        }
  
 -      drm_atomic_state_free(state);
 +put_state:
 +      drm_atomic_state_put(state);
  fail:
        drm_modeset_drop_locks(&ctx);
        drm_modeset_acquire_fini(&ctx);
@@@ -16360,7 -16455,7 +16452,7 @@@ void intel_modeset_init(struct drm_devi
         * BIOS isn't using it, don't assume it will work even if the VBT
         * indicates as much.
         */
-       if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+       if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
                bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
                                            DREF_SSC1_ENABLE);
  
                }
        }
  
-       if (IS_GEN2(dev)) {
+       if (IS_GEN2(dev_priv)) {
                dev->mode_config.max_width = 2048;
                dev->mode_config.max_height = 2048;
-       } else if (IS_GEN3(dev)) {
+       } else if (IS_GEN3(dev_priv)) {
                dev->mode_config.max_width = 4096;
                dev->mode_config.max_height = 4096;
        } else {
                dev->mode_config.max_height = 8192;
        }
  
-       if (IS_845G(dev) || IS_I865G(dev)) {
-               dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
+       if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
+               dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
                dev->mode_config.cursor_height = 1023;
-       } else if (IS_GEN2(dev)) {
+       } else if (IS_GEN2(dev_priv)) {
                dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
                dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
        } else {
@@@ -16592,7 -16687,7 +16684,7 @@@ static void intel_sanitize_crtc(struct 
        if (crtc->active && !intel_crtc_has_encoders(crtc))
                intel_crtc_disable_noatomic(&crtc->base);
  
-       if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
+       if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
                /*
                 * We start out with underrun reporting disabled to avoid races.
                 * For correct bookkeeping mark this on active crtcs.
@@@ -16667,7 -16762,7 +16759,7 @@@ static void intel_sanitize_encoder(stru
  void i915_redisable_vga_power_on(struct drm_device *dev)
  {
        struct drm_i915_private *dev_priv = to_i915(dev);
-       i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
+       i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
  
        if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
                DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
@@@ -16905,11 -17000,11 +16997,11 @@@ intel_modeset_setup_hw_state(struct drm
                pll->on = false;
        }
  
-       if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                vlv_wm_get_hw_state(dev);
-       else if (IS_GEN9(dev))
+       else if (IS_GEN9(dev_priv))
                skl_wm_get_hw_state(dev);
-       else if (HAS_PCH_SPLIT(dev))
+       else if (HAS_PCH_SPLIT(dev_priv))
                ilk_wm_get_hw_state(dev);
  
        for_each_intel_crtc(dev, crtc) {
@@@ -16959,9 -17054,10 +17051,9 @@@ void intel_display_resume(struct drm_de
        drm_modeset_acquire_fini(&ctx);
        mutex_unlock(&dev->mode_config.mutex);
  
 -      if (ret) {
 +      if (ret)
                DRM_ERROR("Restoring old state failed with %i\n", ret);
 -              drm_atomic_state_free(state);
 -      }
 +      drm_atomic_state_put(state);
  }
  
  void intel_modeset_gem_init(struct drm_device *dev)
@@@ -17100,6 -17196,8 +17192,8 @@@ int intel_modeset_vga_set_state(struct 
        return 0;
  }
  
+ #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
  struct intel_display_error_state {
  
        u32 power_well_driver;
@@@ -17238,7 -17336,7 +17332,7 @@@ intel_display_print_error_state(struct 
                return;
  
        err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
-       if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                err_printf(m, "PWR_WELL_CTL2: %08x\n",
                           error->power_well_driver);
        for_each_pipe(dev_priv, i) {
                        err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
                        err_printf(m, "  POS: %08x\n", error->plane[i].pos);
                }
-               if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
+               if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
                        err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
                if (INTEL_INFO(dev)->gen >= 4) {
                        err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
                err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
        }
  }
+ #endif
index 3ffba2def09cdb33f43ed2f627d9b852ffb9a937,c06a33e0ff1955c316d89d8d48708ebe8065dd8a..4e90b0760f3f9c45a1338adfac3a016261f84a56
@@@ -206,6 -206,7 +206,7 @@@ struct intel_encoder 
        struct drm_encoder base;
  
        enum intel_output_type type;
+       enum port port;
        unsigned int cloneable;
        void (*hot_plug)(struct intel_encoder *);
        bool (*compute_config)(struct intel_encoder *,
        void (*suspend)(struct intel_encoder *);
        int crtc_mask;
        enum hpd_pin hpd_pin;
+       /* for communication with audio component; protected by av_mutex */
+       const struct drm_connector *audio_connector;
  };
  
  struct intel_panel {
@@@ -465,9 -468,13 +468,13 @@@ struct intel_pipe_wm 
        bool sprites_scaled;
  };
  
- struct skl_pipe_wm {
+ struct skl_plane_wm {
        struct skl_wm_level wm[8];
        struct skl_wm_level trans_wm;
+ };
+ struct skl_pipe_wm {
+       struct skl_plane_wm planes[I915_MAX_PLANES];
        uint32_t linetime;
  };
  
@@@ -493,6 -500,7 +500,7 @@@ struct intel_crtc_wm_state 
                struct {
                        /* gen9+ only needs 1-step wm programming */
                        struct skl_pipe_wm optimal;
+                       struct skl_ddb_entry ddb;
  
                        /* cached plane data rate */
                        unsigned plane_data_rate[I915_MAX_PLANES];
@@@ -730,6 -738,9 +738,9 @@@ struct intel_crtc 
                bool cxsr_allowed;
        } wm;
  
+       /* gen9+: ddb allocation currently being used */
+       struct skl_ddb_entry hw_ddb;
        int scanline_offset;
  
        struct {
@@@ -796,22 -807,22 +807,22 @@@ struct intel_plane 
  };
  
  struct intel_watermark_params {
-       unsigned long fifo_size;
-       unsigned long max_wm;
-       unsigned long default_wm;
-       unsigned long guard_size;
-       unsigned long cacheline_size;
+       u16 fifo_size;
+       u16 max_wm;
+       u8 default_wm;
+       u8 guard_size;
+       u8 cacheline_size;
  };
  
  struct cxsr_latency {
-       int is_desktop;
-       int is_ddr3;
-       unsigned long fsb_freq;
-       unsigned long mem_freq;
-       unsigned long display_sr;
-       unsigned long display_hpll_disable;
-       unsigned long cursor_sr;
-       unsigned long cursor_hpll_disable;
+       bool is_desktop : 1;
+       bool is_ddr3 : 1;
+       u16 fsb_freq;
+       u16 mem_freq;
+       u16 display_sr;
+       u16 display_hpll_disable;
+       u16 cursor_sr;
+       u16 cursor_hpll_disable;
  };
  
  #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
@@@ -950,17 -961,22 +961,22 @@@ struct intel_dp 
        bool compliance_test_active;
  };
  
+ struct intel_lspcon {
+       bool active;
+       enum drm_lspcon_mode mode;
+       struct drm_dp_aux *aux;
+ };
  struct intel_digital_port {
        struct intel_encoder base;
        enum port port;
        u32 saved_port_bits;
        struct intel_dp dp;
        struct intel_hdmi hdmi;
+       struct intel_lspcon lspcon;
        enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
        bool release_cl2_override;
        uint8_t max_lanes;
-       /* for communication with audio component; protected by av_mutex */
-       const struct drm_connector *audio_connector;
  };
  
  struct intel_dp_mst_encoder {
@@@ -1182,6 -1198,7 +1198,7 @@@ void i915_audio_component_init(struct d
  void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
  
  /* intel_display.c */
+ enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
  void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
  void intel_update_rawclk(struct drm_i915_private *dev_priv);
  int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
@@@ -1285,6 -1302,15 +1302,6 @@@ int intel_plane_atomic_calc_changes(str
  unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
                               uint64_t fb_modifier, unsigned int cpp);
  
 -static inline bool
 -intel_rotation_90_or_270(unsigned int rotation)
 -{
 -      return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
 -}
 -
 -void intel_create_rotation_property(struct drm_device *dev,
 -                                      struct intel_plane *plane);
 -
  void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
                                    enum pipe pipe);
  
@@@ -1478,6 -1504,10 +1495,10 @@@ static inline void intel_fbdev_set_susp
  {
  }
  
+ static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
+ {
+ }
  static inline void intel_fbdev_restore_mode(struct drm_device *dev)
  {
  }
@@@ -1504,6 -1534,7 +1525,7 @@@ void intel_fbc_invalidate(struct drm_i9
  void intel_fbc_flush(struct drm_i915_private *dev_priv,
                     unsigned int frontbuffer_bits, enum fb_op_origin origin);
  void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
+ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
  
  /* intel_hdmi.c */
  void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
@@@ -1707,7 -1738,7 +1729,7 @@@ bool chv_phy_powergate_ch(struct drm_i9
  /* intel_pm.c */
  void intel_init_clock_gating(struct drm_device *dev);
  void intel_suspend_hw(struct drm_device *dev);
- int ilk_wm_max_level(const struct drm_device *dev);
+ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
  void intel_update_watermarks(struct drm_crtc *crtc);
  void intel_init_pm(struct drm_device *dev);
  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
@@@ -1733,20 -1764,24 +1755,24 @@@ void ilk_wm_get_hw_state(struct drm_dev
  void skl_wm_get_hw_state(struct drm_device *dev);
  void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
                          struct skl_ddb_allocation *ddb /* out */);
+ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
+                             struct skl_pipe_wm *out);
  bool intel_can_enable_sagv(struct drm_atomic_state *state);
  int intel_enable_sagv(struct drm_i915_private *dev_priv);
  int intel_disable_sagv(struct drm_i915_private *dev_priv);
+ bool skl_wm_level_equals(const struct skl_wm_level *l1,
+                        const struct skl_wm_level *l2);
  bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
                               const struct skl_ddb_allocation *new,
                               enum pipe pipe);
  bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
-                                const struct skl_ddb_allocation *old,
-                                const struct skl_ddb_allocation *new,
-                                enum pipe pipe);
+                                struct intel_crtc *intel_crtc);
  void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
-                        const struct skl_wm_values *wm);
+                        const struct skl_plane_wm *wm,
+                        const struct skl_ddb_allocation *ddb);
  void skl_write_plane_wm(struct intel_crtc *intel_crtc,
-                       const struct skl_wm_values *wm,
+                       const struct skl_plane_wm *wm,
+                       const struct skl_ddb_allocation *ddb,
                        int plane);
  uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
  bool ilk_disable_lp_wm(struct drm_device *dev);
@@@ -1826,4 -1861,7 +1852,7 @@@ int intel_color_check(struct drm_crtc *
  void intel_color_set_csc(struct drm_crtc_state *crtc_state);
  void intel_color_load_luts(struct drm_crtc_state *crtc_state);
  
+ /* intel_lspcon.c */
+ bool lspcon_init(struct intel_digital_port *intel_dig_port);
+ void lspcon_resume(struct intel_lspcon *lspcon);
  #endif /* __INTEL_DRV_H__ */
index afc040be1172245499fdd51484cdca9c8997c451,617189ae04b4ce7adc522d2e20cc435d7379ccc0..49048d9d7895153b2cea961e03de07b147a19f1f
@@@ -84,7 -84,7 +84,7 @@@ static void intel_fbc_get_plane_source_
  {
        int w, h;
  
 -      if (intel_rotation_90_or_270(cache->plane.rotation)) {
 +      if (drm_rotation_90_or_270(cache->plane.rotation)) {
                w = cache->plane.src_h;
                h = cache->plane.src_w;
        } else {
@@@ -774,6 -774,14 +774,14 @@@ static bool intel_fbc_can_activate(stru
        struct intel_fbc *fbc = &dev_priv->fbc;
        struct intel_fbc_state_cache *cache = &fbc->state_cache;
  
+       /* We don't need to use a state cache here since this information is
+        * global for all CRTC.
+        */
+       if (fbc->underrun_detected) {
+               fbc->no_fbc_reason = "underrun detected";
+               return false;
+       }
        if (!cache->plane.visible) {
                fbc->no_fbc_reason = "primary plane not visible";
                return false;
@@@ -859,6 -867,11 +867,11 @@@ static bool intel_fbc_can_choose(struc
                return false;
        }
  
+       if (fbc->underrun_detected) {
+               fbc->no_fbc_reason = "underrun detected";
+               return false;
+       }
        if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
                fbc->no_fbc_reason = "no enabled pipes can have FBC";
                return false;
@@@ -1221,6 -1234,59 +1234,59 @@@ void intel_fbc_global_disable(struct dr
        cancel_work_sync(&fbc->work.work);
  }
  
+ static void intel_fbc_underrun_work_fn(struct work_struct *work)
+ {
+       struct drm_i915_private *dev_priv =
+               container_of(work, struct drm_i915_private, fbc.underrun_work);
+       struct intel_fbc *fbc = &dev_priv->fbc;
+       mutex_lock(&fbc->lock);
+       /* Maybe we were scheduled twice. */
+       if (fbc->underrun_detected)
+               goto out;
+       DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
+       fbc->underrun_detected = true;
+       intel_fbc_deactivate(dev_priv);
+ out:
+       mutex_unlock(&fbc->lock);
+ }
+ /**
+  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
+  * @dev_priv: i915 device instance
+  *
+  * Without FBC, most underruns are harmless and don't really cause too many
+  * problems, except for an annoying message on dmesg. With FBC, underruns can
+  * become black screens or even worse, especially when paired with bad
+  * watermarks. So in order for us to be on the safe side, completely disable FBC
+  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
+  * already suggests that watermarks may be bad, so try to be as safe as
+  * possible.
+  *
+  * This function is called from the IRQ handler.
+  */
+ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
+ {
+       struct intel_fbc *fbc = &dev_priv->fbc;
+       if (!fbc_supported(dev_priv))
+               return;
+       /* There's no guarantee that underrun_detected won't be set to true
+        * right after this check and before the work is scheduled, but that's
+        * not a problem since we'll check it again under the work function
+        * while FBC is locked. This check here is just to prevent us from
+        * unnecessarily scheduling the work, and it relies on the fact that we
+        * never switch underrun_detect back to false after it's true. */
+       if (READ_ONCE(fbc->underrun_detected))
+               return;
+       schedule_work(&fbc->underrun_work);
+ }
  /**
   * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
   * @dev_priv: i915 device instance
@@@ -1292,6 -1358,7 +1358,7 @@@ void intel_fbc_init(struct drm_i915_pri
        enum pipe pipe;
  
        INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
+       INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
        mutex_init(&fbc->lock);
        fbc->enabled = false;
        fbc->active = false;
index e2f0a32279e70a4a02b5c659538e7b8e25cbb7bb,ea01b406d776a79a123a360dde3f895d5a798194..560fc7af8267a07d0009aff5ba6f4acdf671fb87
@@@ -252,8 -252,8 +252,8 @@@ static const struct cxsr_latency cxsr_l
        {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
  };
  
- static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
-                                                        int is_ddr3,
+ static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
+                                                        bool is_ddr3,
                                                         int fsb,
                                                         int mem)
  {
@@@ -322,11 -322,11 +322,11 @@@ void intel_set_memory_cxsr(struct drm_i
        struct drm_device *dev = &dev_priv->drm;
        u32 val;
  
-       if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
                POSTING_READ(FW_BLC_SELF_VLV);
                dev_priv->wm.vlv.cxsr = enable;
-       } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
+       } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
                I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
                POSTING_READ(FW_BLC_SELF);
        } else if (IS_PINEVIEW(dev)) {
                val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
                I915_WRITE(DSPFW3, val);
                POSTING_READ(DSPFW3);
-       } else if (IS_I945G(dev) || IS_I945GM(dev)) {
+       } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
                val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
                               _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
                I915_WRITE(FW_BLC_SELF, val);
                POSTING_READ(FW_BLC_SELF);
-       } else if (IS_I915GM(dev)) {
+       } else if (IS_I915GM(dev_priv)) {
                /*
                 * FIXME can't find a bit like this for 915G, and
                 * and yet it does have the related watermark in
@@@ -648,8 -648,10 +648,10 @@@ static void pineview_update_wm(struct d
        u32 reg;
        unsigned long wm;
  
-       latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
-                                        dev_priv->fsb_freq, dev_priv->mem_freq);
+       latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
+                                        dev_priv->is_ddr3,
+                                        dev_priv->fsb_freq,
+                                        dev_priv->mem_freq);
        if (!latency) {
                DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
                intel_set_memory_cxsr(dev_priv, false);
@@@ -775,13 -777,13 +777,13 @@@ static bool g4x_check_srwm(struct drm_d
                      display_wm, cursor_wm);
  
        if (display_wm > display->max_wm) {
-               DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
+               DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
                              display_wm, display->max_wm);
                return false;
        }
  
        if (cursor_wm > cursor->max_wm) {
-               DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
+               DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
                              cursor_wm, cursor->max_wm);
                return false;
        }
@@@ -1528,7 -1530,7 +1530,7 @@@ static void i9xx_update_wm(struct drm_c
  
        if (IS_I945GM(dev))
                wm_info = &i945_wm_info;
-       else if (!IS_GEN2(dev))
+       else if (!IS_GEN2(dev_priv))
                wm_info = &i915_wm_info;
        else
                wm_info = &i830_a_wm_info;
        if (intel_crtc_active(crtc)) {
                const struct drm_display_mode *adjusted_mode;
                int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
-               if (IS_GEN2(dev))
+               if (IS_GEN2(dev_priv))
                        cpp = 4;
  
                adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
                        planea_wm = wm_info->max_wm;
        }
  
-       if (IS_GEN2(dev))
+       if (IS_GEN2(dev_priv))
                wm_info = &i830_bc_wm_info;
  
        fifo_size = dev_priv->display.get_fifo_size(dev, 1);
        if (intel_crtc_active(crtc)) {
                const struct drm_display_mode *adjusted_mode;
                int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
-               if (IS_GEN2(dev))
+               if (IS_GEN2(dev_priv))
                        cpp = 4;
  
                adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
  
        DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  
-       if (IS_I915GM(dev) && enabled) {
+       if (IS_I915GM(dev_priv) && enabled) {
                struct drm_i915_gem_object *obj;
  
                obj = intel_fb_obj(enabled->primary->state->fb);
                unsigned long line_time_us;
                int entries;
  
-               if (IS_I915GM(dev) || IS_I945GM(dev))
+               if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
                        cpp = 4;
  
                line_time_us = max(htotal * 1000 / clock, 1);
                if (srwm < 0)
                        srwm = 1;
  
-               if (IS_I945G(dev) || IS_I945GM(dev))
+               if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
               &n