#define ATM_SKB(s) (&(s)->atm)
#endif
- /* Spinlock debugging stuff */
-#ifdef NS_DEBUG_SPINLOCKS /* See nicstar.h */
-#define ns_grab_int_lock(card,flags) \
- do { \
- unsigned long nsdsf, nsdsf2; \
- local_irq_save(flags); \
- save_flags(nsdsf); cli();\
- if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
- (flags)&(1<<9)?"en":"dis"); \
- if (spin_is_locked(&(card)->int_lock) && \
- (card)->cpu_int == smp_processor_id()) { \
- printk("nicstar.c: line %d (cpu %d) int_lock already locked at line %d (cpu %d)\n", \
- __LINE__, smp_processor_id(), (card)->has_int_lock, \
- (card)->cpu_int); \
- printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
- } \
- if (spin_is_locked(&(card)->res_lock) && \
- (card)->cpu_res == smp_processor_id()) { \
- printk("nicstar.c: line %d (cpu %d) res_lock locked at line %d (cpu %d)(trying int)\n", \
- __LINE__, smp_processor_id(), (card)->has_res_lock, \
- (card)->cpu_res); \
- printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
- } \
- spin_lock_irq(&(card)->int_lock); \
- (card)->has_int_lock = __LINE__; \
- (card)->cpu_int = smp_processor_id(); \
- restore_flags(nsdsf); } while (0)
-#define ns_grab_res_lock(card,flags) \
- do { \
- unsigned long nsdsf, nsdsf2; \
- local_irq_save(flags); \
- save_flags(nsdsf); cli();\
- if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
- (flags)&(1<<9)?"en":"dis"); \
- if (spin_is_locked(&(card)->res_lock) && \
- (card)->cpu_res == smp_processor_id()) { \
- printk("nicstar.c: line %d (cpu %d) res_lock already locked at line %d (cpu %d)\n", \
- __LINE__, smp_processor_id(), (card)->has_res_lock, \
- (card)->cpu_res); \
- printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
- } \
- spin_lock_irq(&(card)->res_lock); \
- (card)->has_res_lock = __LINE__; \
- (card)->cpu_res = smp_processor_id(); \
- restore_flags(nsdsf); } while (0)
-#define ns_grab_scq_lock(card,scq,flags) \
- do { \
- unsigned long nsdsf, nsdsf2; \
- local_irq_save(flags); \
- save_flags(nsdsf); cli();\
- if (nsdsf & (1<<9)) printk ("nicstar.c: ints %sabled -> enabled.\n", \
- (flags)&(1<<9)?"en":"dis"); \
- if (spin_is_locked(&(scq)->lock) && \
- (scq)->cpu_lock == smp_processor_id()) { \
- printk("nicstar.c: line %d (cpu %d) this scq_lock already locked at line %d (cpu %d)\n", \
- __LINE__, smp_processor_id(), (scq)->has_lock, \
- (scq)->cpu_lock); \
- printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
- } \
- if (spin_is_locked(&(card)->res_lock) && \
- (card)->cpu_res == smp_processor_id()) { \
- printk("nicstar.c: line %d (cpu %d) res_lock locked at line %d (cpu %d)(trying scq)\n", \
- __LINE__, smp_processor_id(), (card)->has_res_lock, \
- (card)->cpu_res); \
- printk("nicstar.c: ints were %sabled.\n", ((flags)&(1<<9)?"en":"dis")); \
- } \
- spin_lock_irq(&(scq)->lock); \
- (scq)->has_lock = __LINE__; \
- (scq)->cpu_lock = smp_processor_id(); \
- restore_flags(nsdsf); } while (0)
-#else /* !NS_DEBUG_SPINLOCKS */
-#define ns_grab_int_lock(card,flags) \
- spin_lock_irqsave(&(card)->int_lock,(flags))
-#define ns_grab_res_lock(card,flags) \
- spin_lock_irqsave(&(card)->res_lock,(flags))
-#define ns_grab_scq_lock(card,scq,flags) \
- spin_lock_irqsave(&(scq)->lock,flags)
-#endif /* NS_DEBUG_SPINLOCKS */
-
/* Function declarations ******************************************************/
sram_address <<= 2;
sram_address &= 0x0007FFFC; /* address must be dword aligned */
sram_address |= 0x50000000; /* SRAM read command */
- ns_grab_res_lock(card, flags);
+ spin_lock_irqsave(&card->res_lock, flags);
while (CMD_BUSY(card));
writel(sram_address, card->membase + CMD);
while (CMD_BUSY(card));
count--; /* count range now is 0..3 instead of 1..4 */
c = count;
c <<= 2; /* to use increments of 4 */
- ns_grab_res_lock(card, flags);
+ spin_lock_irqsave(&card->res_lock, flags);
while (CMD_BUSY(card));
for (i = 0; i <= c; i += 4)
writel(*(value++), card->membase + i);
card->lbfqc += 2;
}
- ns_grab_res_lock(card, flags);
+ spin_lock_irqsave(&card->res_lock, flags);
while (CMD_BUSY(card));
writel(addr2, card->membase + DR3);
PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
stat_r = readl(card->membase + STAT);
unsigned long flags;
addr = NS_RCT + (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
- ns_grab_res_lock(card, flags);
+ spin_lock_irqsave(&card->res_lock, flags);
while(CMD_BUSY(card));
writel(NS_CMD_CLOSE_CONNECTION | addr << 2, card->membase + CMD);
spin_unlock_irqrestore(&card->res_lock, flags);
NS_SKB(iovb)->iovcnt);
NS_SKB(iovb)->iovcnt = 0;
NS_SKB(iovb)->vcc = NULL;
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
recycle_iov_buf(card, iovb);
spin_unlock_irqrestore(&card->int_lock, flags);
vc->rx_iov = NULL;
for (;;)
{
- ns_grab_scq_lock(card, scq, flags);
+ spin_lock_irqsave(&scq->lock, flags);
scqep = scq->next;
if (scqep == scq->base)
scqep = scq->last;
unsigned long flags;
scq_info *scq = card->scq0;
- ns_grab_scq_lock(card, scq, flags);
+ spin_lock_irqsave(&scq->lock, flags);
for(i = 0; i < scq->num_entries; i++) {
if(scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
u32 data;
int index;
- ns_grab_scq_lock(card, scq, flags);
+ spin_lock_irqsave(&scq->lock, flags);
while (scq->tail == scq->next)
{
if (in_interrupt()) {
scq->full = 1;
spin_unlock_irqrestore(&scq->lock, flags);
interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT);
- ns_grab_scq_lock(card, scq, flags);
+ spin_lock_irqsave(&scq->lock, flags);
if (scq->full) {
spin_unlock_irqrestore(&scq->lock, flags);
if (has_run++) break;
spin_unlock_irqrestore(&scq->lock, flags);
interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT);
- ns_grab_scq_lock(card, scq, flags);
+ spin_lock_irqsave(&scq->lock, flags);
}
if (!scq->full)
return;
}
- ns_grab_scq_lock(card, scq, flags);
+ spin_lock_irqsave(&scq->lock, flags);
i = (int) (scq->tail - scq->base);
if (++i == scq->num_entries)
i = 0;
{
struct sk_buff *hb;
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
hb = skb_dequeue(&card->hbpool.queue);
card->hbpool.count--;
spin_unlock_irqrestore(&card->int_lock, flags);
if (hb == NULL)
return -ENOMEM;
NS_SKB_CB(hb)->buf_type = BUF_NONE;
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
skb_queue_tail(&card->hbpool.queue, hb);
card->hbpool.count++;
spin_unlock_irqrestore(&card->int_lock, flags);
{
struct sk_buff *iovb;
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
iovb = skb_dequeue(&card->iovpool.queue);
card->iovpool.count--;
spin_unlock_irqrestore(&card->int_lock, flags);
if (iovb == NULL)
return -ENOMEM;
NS_SKB_CB(iovb)->buf_type = BUF_NONE;
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
skb_queue_tail(&card->iovpool.queue, iovb);
card->iovpool.count++;
spin_unlock_irqrestore(&card->int_lock, flags);
/* Probably it isn't worth spinning */
continue;
}
- ns_grab_int_lock(card, flags);
+ spin_lock_irqsave(&card->int_lock, flags);
stat_w = 0;
stat_r = readl(card->membase + STAT);
unsigned long flags;
card = dev->dev_data;
- ns_grab_res_lock(card, flags);
+ spin_lock_irqsave(&card->res_lock, flags);
while(CMD_BUSY(card));
writel((unsigned long) value, card->membase + DR0);
writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
unsigned long data;
card = dev->dev_data;
- ns_grab_res_lock(card, flags);
+ spin_lock_irqsave(&card->res_lock, flags);
while(CMD_BUSY(card));
writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
card->membase + CMD);
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.90"
-#define DRV_MODULE_RELDATE "April 12, 2008"
+#define DRV_MODULE_VERSION "3.91"
+#define DRV_MODULE_RELDATE "April 18, 2008"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
u32 last_plus_one, u32 *start,
u32 base_flags, u32 mss)
{
- struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
+ struct sk_buff *new_skb;
dma_addr_t new_addr = 0;
u32 entry = *start;
int i, ret = 0;
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
+ new_skb = skb_copy(skb, GFP_ATOMIC);
+ else {
+ int more_headroom = 4 - ((unsigned long)skb->data & 3);
+
+ new_skb = skb_copy_expand(skb,
+ skb_headroom(skb) + more_headroom,
+ skb_tailroom(skb), GFP_ATOMIC);
+ }
+
if (!new_skb) {
ret = -1;
} else {
would_hit_hwbug = 0;
- if (tg3_4g_overflow_test(mapping, len))
+ if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
+ would_hit_hwbug = 1;
+ else if (tg3_4g_overflow_test(mapping, len))
would_hit_hwbug = 1;
tg3_set_txd(tp, entry, mapping, len, base_flags,
}
}
+ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
+ static struct tg3_dev_id {
+ u32 vendor;
+ u32 device;
+ } bridge_chipsets[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
+ { },
+ };
+ struct tg3_dev_id *pci_id = &bridge_chipsets[0];
+ struct pci_dev *bridge = NULL;
+
+ while (pci_id->vendor != 0) {
+ bridge = pci_get_device(pci_id->vendor,
+ pci_id->device,
+ bridge);
+ if (!bridge) {
+ pci_id++;
+ continue;
+ }
+ if (bridge->subordinate &&
+ (bridge->subordinate->number <=
+ tp->pdev->bus->number) &&
+ (bridge->subordinate->subordinate >=
+ tp->pdev->bus->number)) {
+ tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
+ pci_dev_put(bridge);
+ break;
+ }
+ }
+ }
+
/* The EPB bridge inside 5714, 5715, and 5780 cannot support
* DMA addresses > 40-bit. This bridge may have other additional
* 57xx devices behind it in some 4-port NIC designs for example.